prompt
stringlengths 162
4.26M
| response
stringlengths 109
5.16M
|
|---|---|
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_173 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_sink_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_194
connect io_out_sink_valid_1.clock, clock
connect io_out_sink_valid_1.reset, reset
connect io_out_sink_valid_1.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_sink_valid_1.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_173( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_194 io_out_sink_valid_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MSHR_5 :
input clock : Clock
input reset : Reset
output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}}, status : { valid : UInt<1>, bits : { set : UInt<10>, tag : UInt<13>, way : UInt<3>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<13>, set : UInt<10>, param : UInt<3>, source : UInt<4>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<13>, set : UInt<10>, clients : UInt<1>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<13>, set : UInt<10>, way : UInt<3>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<4>, way : UInt<3>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<10>, way : UInt<3>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<10>, tag : UInt<13>, source : UInt<7>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<4>}}, flip nestedwb : { set : UInt<10>, tag : UInt<13>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}}
regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}, clock
regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}, clock
when meta_valid :
node _T = eq(meta.state, UInt<2>(0h0))
when _T :
node _T_1 = orr(meta.clients)
node _T_2 = eq(_T_1, UInt<1>(0h0))
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
node _T_6 = eq(meta.dirty, UInt<1>(0h0))
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1
assert(clock, _T_6, UInt<1>(0h1), "") : assert_1
node _T_10 = eq(meta.state, UInt<2>(0h1))
when _T_10 :
node _T_11 = eq(meta.dirty, UInt<1>(0h0))
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2
assert(clock, _T_11, UInt<1>(0h1), "") : assert_2
node _T_15 = eq(meta.state, UInt<2>(0h2))
when _T_15 :
node _T_16 = orr(meta.clients)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3
assert(clock, _T_16, UInt<1>(0h1), "") : assert_3
node _T_20 = sub(meta.clients, UInt<1>(0h1))
node _T_21 = tail(_T_20, 1)
node _T_22 = and(meta.clients, _T_21)
node _T_23 = eq(_T_22, UInt<1>(0h0))
node _T_24 = asUInt(reset)
node _T_25 = eq(_T_24, UInt<1>(0h0))
when _T_25 :
node _T_26 = eq(_T_23, UInt<1>(0h0))
when _T_26 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4
assert(clock, _T_23, UInt<1>(0h1), "") : assert_4
node _T_27 = eq(meta.state, UInt<2>(0h3))
when _T_27 :
skip
regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1)
reg sink : UInt<3>, clock
reg gotT : UInt<1>, clock
reg bad_grant : UInt<1>, clock
reg probes_done : UInt<1>, clock
reg probes_toN : UInt<1>, clock
reg probes_noT : UInt<1>, clock
node _T_28 = neq(meta.state, UInt<2>(0h0))
node _T_29 = and(meta_valid, _T_28)
node _T_30 = eq(io.nestedwb.set, request.set)
node _T_31 = and(_T_29, _T_30)
node _T_32 = eq(io.nestedwb.tag, meta.tag)
node _T_33 = and(_T_31, _T_32)
when _T_33 :
when io.nestedwb.b_clr_dirty :
connect meta.dirty, UInt<1>(0h0)
when io.nestedwb.c_set_dirty :
connect meta.dirty, UInt<1>(0h1)
when io.nestedwb.b_toB :
connect meta.state, UInt<2>(0h1)
when io.nestedwb.b_toN :
connect meta.hit, UInt<1>(0h0)
connect io.status.valid, request_valid
connect io.status.bits.set, request.set
connect io.status.bits.tag, request.tag
connect io.status.bits.way, meta.way
node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0))
node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0))
node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0))
node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2)
node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0))
node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4)
node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6)
node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7)
connect io.status.bits.blockB, _io_status_bits_blockB_T_8
node _io_status_bits_nestB_T = and(meta_valid, w_releaseack)
node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast)
node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast)
node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3)
connect io.status.bits.nestB, _io_status_bits_nestB_T_4
node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0))
connect io.status.bits.blockC, _io_status_bits_blockC_T
node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1)
node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3)
node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4)
connect io.status.bits.nestC, _io_status_bits_nestC_T_5
node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0))
node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0))
node _T_36 = or(_T_34, _T_35)
node _T_37 = asUInt(reset)
node _T_38 = eq(_T_37, UInt<1>(0h0))
when _T_38 :
node _T_39 = eq(_T_36, UInt<1>(0h0))
when _T_39 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB || !io.status.bits.blockB)\n") : printf_5
assert(clock, _T_36, UInt<1>(0h1), "") : assert_5
node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0))
node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0))
node _T_42 = or(_T_40, _T_41)
node _T_43 = asUInt(reset)
node _T_44 = eq(_T_43, UInt<1>(0h0))
when _T_44 :
node _T_45 = eq(_T_42, UInt<1>(0h0))
when _T_45 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC || !io.status.bits.blockC)\n") : printf_6
assert(clock, _T_42, UInt<1>(0h1), "") : assert_6
node _no_wait_T = and(w_rprobeacklast, w_releaseack)
node _no_wait_T_1 = and(_no_wait_T, w_grantlast)
node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast)
node no_wait = and(_no_wait_T_2, w_grantack)
node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0))
node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release)
node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe)
connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2
node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0))
node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1)
connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2
node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0))
node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst)
node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0))
node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst)
node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3)
connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4
node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0))
node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack)
node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant)
connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2
node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0))
node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst)
connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1
node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0))
node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack)
connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1
node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0))
node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst)
node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0))
node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait)
node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3)
connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4
connect io.schedule.bits.reload, no_wait
node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid)
node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid)
node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid)
node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid)
node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid)
node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid)
connect io.schedule.valid, _io_schedule_valid_T_5
when io.schedule.ready :
connect s_rprobe, UInt<1>(0h1)
when w_rprobeackfirst :
connect s_release, UInt<1>(0h1)
connect s_pprobe, UInt<1>(0h1)
node _T_46 = and(s_release, s_pprobe)
when _T_46 :
connect s_acquire, UInt<1>(0h1)
when w_releaseack :
connect s_flush, UInt<1>(0h1)
when w_pprobeackfirst :
connect s_probeack, UInt<1>(0h1)
when w_grantfirst :
connect s_grantack, UInt<1>(0h1)
node _T_47 = and(w_pprobeack, w_grant)
when _T_47 :
connect s_execute, UInt<1>(0h1)
when no_wait :
connect s_writeback, UInt<1>(0h1)
when no_wait :
connect request_valid, UInt<1>(0h0)
connect meta_valid, UInt<1>(0h0)
wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}
connect final_meta_writeback, meta
node _req_clientBit_uncommonBits_T = or(request.source, UInt<3>(0h0))
node req_clientBit_uncommonBits = bits(_req_clientBit_uncommonBits_T, 2, 0)
node _req_clientBit_T = shr(request.source, 3)
node _req_clientBit_T_1 = eq(_req_clientBit_T, UInt<4>(0h8))
node _req_clientBit_T_2 = leq(UInt<1>(0h0), req_clientBit_uncommonBits)
node _req_clientBit_T_3 = and(_req_clientBit_T_1, _req_clientBit_T_2)
node _req_clientBit_T_4 = leq(req_clientBit_uncommonBits, UInt<3>(0h4))
node req_clientBit = and(_req_clientBit_T_3, _req_clientBit_T_4)
node _req_needT_T = bits(request.opcode, 2, 2)
node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0))
node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5))
node _req_needT_T_3 = eq(request.param, UInt<1>(0h1))
node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3)
node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4)
node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6))
node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7))
node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7)
node _req_needT_T_9 = neq(request.param, UInt<2>(0h0))
node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9)
node req_needT = or(_req_needT_T_5, _req_needT_T_10)
node _req_acquire_T = eq(request.opcode, UInt<3>(0h6))
node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7))
node req_acquire = or(_req_acquire_T, _req_acquire_T_1)
node _meta_no_clients_T = orr(meta.clients)
node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0))
node _req_promoteT_T = eq(meta.state, UInt<2>(0h3))
node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T)
node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT)
node req_promoteT = and(req_acquire, _req_promoteT_T_2)
node _T_48 = and(request.prio[2], UInt<1>(0h1))
when _T_48 :
node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0)
node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T)
connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1
node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3))
node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2))
node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1)
node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state)
connect final_meta_writeback.state, _final_meta_writeback_state_T_3
node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1))
node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2))
node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1)
node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5))
node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3)
node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0))
node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5)
node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7
connect final_meta_writeback.hit, UInt<1>(0h1)
else :
node _T_49 = and(request.control, UInt<1>(0h1))
when _T_49 :
when meta.hit :
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h0)
node _final_meta_writeback_clients_T_8 = not(probes_toN)
node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9
connect final_meta_writeback.hit, UInt<1>(0h0)
else :
node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty)
node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2)
node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0))
node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4)
connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5
node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0))
node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1))
node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire)
node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state)
node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1))
node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state)
node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11)
node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state)
node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13)
node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15)
node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16)
connect final_meta_writeback.state, _final_meta_writeback_state_T_17
node _final_meta_writeback_clients_T_10 = not(probes_toN)
node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10)
node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0))
node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0))
node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14
connect final_meta_writeback.tag, request.tag
connect final_meta_writeback.hit, UInt<1>(0h1)
when bad_grant :
when meta.hit :
node _T_50 = eq(meta_valid, UInt<1>(0h0))
node _T_51 = eq(meta.state, UInt<2>(0h1))
node _T_52 = or(_T_50, _T_51)
node _T_53 = asUInt(reset)
node _T_54 = eq(_T_53, UInt<1>(0h0))
when _T_54 :
node _T_55 = eq(_T_52, UInt<1>(0h0))
when _T_55 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid || meta.state === BRANCH)\n") : printf_7
assert(clock, _T_52, UInt<1>(0h1), "") : assert_7
connect final_meta_writeback.hit, UInt<1>(0h1)
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h1)
node _final_meta_writeback_clients_T_15 = not(probes_toN)
node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16
else :
connect final_meta_writeback.hit, UInt<1>(0h0)
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h0)
connect final_meta_writeback.clients, UInt<1>(0h0)
wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>}
connect invalid.dirty, UInt<1>(0h0)
connect invalid.state, UInt<2>(0h0)
connect invalid.clients, UInt<1>(0h0)
connect invalid.tag, UInt<1>(0h0)
node _honour_BtoT_T = and(meta.clients, req_clientBit)
node _honour_BtoT_T_1 = orr(_honour_BtoT_T)
node honour_BtoT = and(meta.hit, _honour_BtoT_T_1)
node _excluded_client_T = and(meta.hit, request.prio[0])
node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6))
node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7))
node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2)
node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4))
node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4)
node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5))
node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0))
node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7)
node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8)
node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0))
connect io.schedule.bits.a.bits.tag, request.tag
connect io.schedule.bits.a.bits.set, request.set
node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0))
connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1
node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6))
node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0))
node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7))
node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2)
node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0))
node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4)
connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5
connect io.schedule.bits.a.bits.source, UInt<1>(0h0)
node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1)
node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2)
connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3
node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag)
connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1
connect io.schedule.bits.b.bits.set, request.set
node _io_schedule_bits_b_bits_clients_T = not(excluded_client)
node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T)
connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1
node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6))
connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T
node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1))
node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1))
connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1
connect io.schedule.bits.c.bits.source, UInt<1>(0h0)
connect io.schedule.bits.c.bits.tag, meta.tag
connect io.schedule.bits.c.bits.set, request.set
connect io.schedule.bits.c.bits.way, meta.way
connect io.schedule.bits.c.bits.dirty, meta.dirty
connect io.schedule.bits.d.bits.set, request.set
connect io.schedule.bits.d.bits.put, request.put
connect io.schedule.bits.d.bits.offset, request.offset
connect io.schedule.bits.d.bits.tag, request.tag
connect io.schedule.bits.d.bits.source, request.source
connect io.schedule.bits.d.bits.size, request.size
connect io.schedule.bits.d.bits.param, request.param
connect io.schedule.bits.d.bits.opcode, request.opcode
connect io.schedule.bits.d.bits.control, request.control
connect io.schedule.bits.d.bits.prio, request.prio
node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0))
node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0))
node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param)
node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param)
node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param)
node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4)
node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param)
node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6)
node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8)
connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9
connect io.schedule.bits.d.bits.sink, UInt<1>(0h0)
connect io.schedule.bits.d.bits.way, meta.way
connect io.schedule.bits.d.bits.bad, bad_grant
connect io.schedule.bits.e.bits.sink, sink
connect io.schedule.bits.x.bits.fail, UInt<1>(0h0)
connect io.schedule.bits.dir.bits.set, request.set
connect io.schedule.bits.dir.bits.way, meta.way
node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0))
wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>}
connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag
connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients
connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state
connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty
node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE)
connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1
node _evict_T = eq(meta.hit, UInt<1>(0h0))
wire evict : UInt
connect evict, UInt<1>(0h0)
node evict_c = orr(meta.clients)
node _evict_T_1 = eq(UInt<2>(0h1), meta.state)
when _evict_T_1 :
node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1))
connect evict, _evict_out_T
else :
node _evict_T_2 = eq(UInt<2>(0h2), meta.state)
when _evict_T_2 :
node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect evict, _evict_out_T_1
else :
node _evict_T_3 = eq(UInt<2>(0h3), meta.state)
when _evict_T_3 :
node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3)
connect evict, _evict_out_T_4
else :
node _evict_T_4 = eq(UInt<2>(0h0), meta.state)
when _evict_T_4 :
connect evict, UInt<4>(0h8)
node _evict_T_5 = eq(_evict_T, UInt<1>(0h0))
when _evict_T_5 :
connect evict, UInt<4>(0h8)
wire before : UInt
connect before, UInt<1>(0h0)
node before_c = orr(meta.clients)
node _before_T = eq(UInt<2>(0h1), meta.state)
when _before_T :
node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1))
connect before, _before_out_T
else :
node _before_T_1 = eq(UInt<2>(0h2), meta.state)
when _before_T_1 :
node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect before, _before_out_T_1
else :
node _before_T_2 = eq(UInt<2>(0h3), meta.state)
when _before_T_2 :
node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3)
connect before, _before_out_T_4
else :
node _before_T_3 = eq(UInt<2>(0h0), meta.state)
when _before_T_3 :
connect before, UInt<4>(0h8)
node _before_T_4 = eq(meta.hit, UInt<1>(0h0))
when _before_T_4 :
connect before, UInt<4>(0h8)
wire after : UInt
connect after, UInt<1>(0h0)
node after_c = orr(final_meta_writeback.clients)
node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state)
when _after_T :
node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1))
connect after, _after_out_T
else :
node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state)
when _after_T_1 :
node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect after, _after_out_T_1
else :
node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state)
when _after_T_2 :
node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3)
connect after, _after_out_T_4
else :
node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state)
when _after_T_3 :
connect after, UInt<4>(0h8)
node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0))
when _after_T_4 :
connect after, UInt<4>(0h8)
node _T_56 = eq(s_release, UInt<1>(0h0))
node _T_57 = and(_T_56, w_rprobeackfirst)
node _T_58 = and(_T_57, io.schedule.ready)
when _T_58 :
node _T_59 = eq(evict, UInt<1>(0h1))
node _T_60 = eq(_T_59, UInt<1>(0h0))
node _T_61 = asUInt(reset)
node _T_62 = eq(_T_61, UInt<1>(0h0))
when _T_62 :
node _T_63 = eq(_T_60, UInt<1>(0h0))
when _T_63 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8
assert(clock, _T_60, UInt<1>(0h1), "") : assert_8
node _T_64 = eq(before, UInt<1>(0h1))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(_T_65, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9
assert(clock, _T_65, UInt<1>(0h1), "") : assert_9
node _T_69 = eq(evict, UInt<1>(0h0))
node _T_70 = eq(_T_69, UInt<1>(0h0))
node _T_71 = asUInt(reset)
node _T_72 = eq(_T_71, UInt<1>(0h0))
when _T_72 :
node _T_73 = eq(_T_70, UInt<1>(0h0))
when _T_73 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10
assert(clock, _T_70, UInt<1>(0h1), "") : assert_10
node _T_74 = eq(before, UInt<1>(0h0))
node _T_75 = eq(_T_74, UInt<1>(0h0))
node _T_76 = asUInt(reset)
node _T_77 = eq(_T_76, UInt<1>(0h0))
when _T_77 :
node _T_78 = eq(_T_75, UInt<1>(0h0))
when _T_78 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11
assert(clock, _T_75, UInt<1>(0h1), "") : assert_11
node _T_79 = eq(evict, UInt<3>(0h7))
node _T_80 = eq(before, UInt<3>(0h7))
node _T_81 = eq(evict, UInt<3>(0h5))
node _T_82 = eq(before, UInt<3>(0h5))
node _T_83 = eq(evict, UInt<3>(0h4))
node _T_84 = eq(before, UInt<3>(0h4))
node _T_85 = eq(evict, UInt<3>(0h6))
node _T_86 = eq(before, UInt<3>(0h6))
node _T_87 = eq(evict, UInt<2>(0h3))
node _T_88 = eq(before, UInt<2>(0h3))
node _T_89 = eq(evict, UInt<2>(0h2))
node _T_90 = eq(before, UInt<2>(0h2))
node _T_91 = eq(s_writeback, UInt<1>(0h0))
node _T_92 = and(_T_91, no_wait)
node _T_93 = and(_T_92, io.schedule.ready)
when _T_93 :
node _T_94 = eq(before, UInt<4>(0h8))
node _T_95 = eq(after, UInt<1>(0h1))
node _T_96 = and(_T_94, _T_95)
node _T_97 = eq(_T_96, UInt<1>(0h0))
node _T_98 = asUInt(reset)
node _T_99 = eq(_T_98, UInt<1>(0h0))
when _T_99 :
node _T_100 = eq(_T_97, UInt<1>(0h0))
when _T_100 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12
assert(clock, _T_97, UInt<1>(0h1), "") : assert_12
node _T_101 = eq(before, UInt<4>(0h8))
node _T_102 = eq(after, UInt<1>(0h0))
node _T_103 = and(_T_101, _T_102)
node _T_104 = eq(_T_103, UInt<1>(0h0))
node _T_105 = asUInt(reset)
node _T_106 = eq(_T_105, UInt<1>(0h0))
when _T_106 :
node _T_107 = eq(_T_104, UInt<1>(0h0))
when _T_107 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13
assert(clock, _T_104, UInt<1>(0h1), "") : assert_13
node _T_108 = eq(before, UInt<4>(0h8))
node _T_109 = eq(after, UInt<3>(0h7))
node _T_110 = and(_T_108, _T_109)
node _T_111 = eq(before, UInt<4>(0h8))
node _T_112 = eq(after, UInt<3>(0h5))
node _T_113 = and(_T_111, _T_112)
node _T_114 = eq(_T_113, UInt<1>(0h0))
node _T_115 = asUInt(reset)
node _T_116 = eq(_T_115, UInt<1>(0h0))
when _T_116 :
node _T_117 = eq(_T_114, UInt<1>(0h0))
when _T_117 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14
assert(clock, _T_114, UInt<1>(0h1), "") : assert_14
node _T_118 = eq(before, UInt<4>(0h8))
node _T_119 = eq(after, UInt<3>(0h4))
node _T_120 = and(_T_118, _T_119)
node _T_121 = eq(_T_120, UInt<1>(0h0))
node _T_122 = asUInt(reset)
node _T_123 = eq(_T_122, UInt<1>(0h0))
when _T_123 :
node _T_124 = eq(_T_121, UInt<1>(0h0))
when _T_124 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15
assert(clock, _T_121, UInt<1>(0h1), "") : assert_15
node _T_125 = eq(before, UInt<4>(0h8))
node _T_126 = eq(after, UInt<3>(0h6))
node _T_127 = and(_T_125, _T_126)
node _T_128 = eq(before, UInt<4>(0h8))
node _T_129 = eq(after, UInt<2>(0h3))
node _T_130 = and(_T_128, _T_129)
node _T_131 = eq(before, UInt<4>(0h8))
node _T_132 = eq(after, UInt<2>(0h2))
node _T_133 = and(_T_131, _T_132)
node _T_134 = eq(_T_133, UInt<1>(0h0))
node _T_135 = asUInt(reset)
node _T_136 = eq(_T_135, UInt<1>(0h0))
when _T_136 :
node _T_137 = eq(_T_134, UInt<1>(0h0))
when _T_137 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16
assert(clock, _T_134, UInt<1>(0h1), "") : assert_16
node _T_138 = eq(before, UInt<1>(0h1))
node _T_139 = eq(after, UInt<4>(0h8))
node _T_140 = and(_T_138, _T_139)
node _T_141 = eq(_T_140, UInt<1>(0h0))
node _T_142 = asUInt(reset)
node _T_143 = eq(_T_142, UInt<1>(0h0))
when _T_143 :
node _T_144 = eq(_T_141, UInt<1>(0h0))
when _T_144 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17
assert(clock, _T_141, UInt<1>(0h1), "") : assert_17
node _T_145 = eq(before, UInt<1>(0h1))
node _T_146 = eq(after, UInt<1>(0h0))
node _T_147 = and(_T_145, _T_146)
node _T_148 = eq(_T_147, UInt<1>(0h0))
node _T_149 = asUInt(reset)
node _T_150 = eq(_T_149, UInt<1>(0h0))
when _T_150 :
node _T_151 = eq(_T_148, UInt<1>(0h0))
when _T_151 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18
assert(clock, _T_148, UInt<1>(0h1), "") : assert_18
node _T_152 = eq(before, UInt<1>(0h1))
node _T_153 = eq(after, UInt<3>(0h7))
node _T_154 = and(_T_152, _T_153)
node _T_155 = eq(_T_154, UInt<1>(0h0))
node _T_156 = asUInt(reset)
node _T_157 = eq(_T_156, UInt<1>(0h0))
when _T_157 :
node _T_158 = eq(_T_155, UInt<1>(0h0))
when _T_158 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19
assert(clock, _T_155, UInt<1>(0h1), "") : assert_19
node _T_159 = eq(before, UInt<1>(0h1))
node _T_160 = eq(after, UInt<3>(0h5))
node _T_161 = and(_T_159, _T_160)
node _T_162 = eq(_T_161, UInt<1>(0h0))
node _T_163 = asUInt(reset)
node _T_164 = eq(_T_163, UInt<1>(0h0))
when _T_164 :
node _T_165 = eq(_T_162, UInt<1>(0h0))
when _T_165 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20
assert(clock, _T_162, UInt<1>(0h1), "") : assert_20
node _T_166 = eq(before, UInt<1>(0h1))
node _T_167 = eq(after, UInt<3>(0h4))
node _T_168 = and(_T_166, _T_167)
node _T_169 = eq(_T_168, UInt<1>(0h0))
node _T_170 = asUInt(reset)
node _T_171 = eq(_T_170, UInt<1>(0h0))
when _T_171 :
node _T_172 = eq(_T_169, UInt<1>(0h0))
when _T_172 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21
assert(clock, _T_169, UInt<1>(0h1), "") : assert_21
node _T_173 = eq(before, UInt<1>(0h1))
node _T_174 = eq(after, UInt<3>(0h6))
node _T_175 = and(_T_173, _T_174)
node _T_176 = eq(_T_175, UInt<1>(0h0))
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_T_176, UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22
assert(clock, _T_176, UInt<1>(0h1), "") : assert_22
node _T_180 = eq(before, UInt<1>(0h1))
node _T_181 = eq(after, UInt<2>(0h3))
node _T_182 = and(_T_180, _T_181)
node _T_183 = eq(_T_182, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(before, UInt<1>(0h1))
node _T_188 = eq(after, UInt<2>(0h2))
node _T_189 = and(_T_187, _T_188)
node _T_190 = eq(_T_189, UInt<1>(0h0))
node _T_191 = asUInt(reset)
node _T_192 = eq(_T_191, UInt<1>(0h0))
when _T_192 :
node _T_193 = eq(_T_190, UInt<1>(0h0))
when _T_193 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24
assert(clock, _T_190, UInt<1>(0h1), "") : assert_24
node _T_194 = eq(before, UInt<1>(0h0))
node _T_195 = eq(after, UInt<4>(0h8))
node _T_196 = and(_T_194, _T_195)
node _T_197 = eq(_T_196, UInt<1>(0h0))
node _T_198 = asUInt(reset)
node _T_199 = eq(_T_198, UInt<1>(0h0))
when _T_199 :
node _T_200 = eq(_T_197, UInt<1>(0h0))
when _T_200 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25
assert(clock, _T_197, UInt<1>(0h1), "") : assert_25
node _T_201 = eq(before, UInt<1>(0h0))
node _T_202 = eq(after, UInt<1>(0h1))
node _T_203 = and(_T_201, _T_202)
node _T_204 = eq(_T_203, UInt<1>(0h0))
node _T_205 = asUInt(reset)
node _T_206 = eq(_T_205, UInt<1>(0h0))
when _T_206 :
node _T_207 = eq(_T_204, UInt<1>(0h0))
when _T_207 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26
assert(clock, _T_204, UInt<1>(0h1), "") : assert_26
node _T_208 = eq(before, UInt<1>(0h0))
node _T_209 = eq(after, UInt<3>(0h7))
node _T_210 = and(_T_208, _T_209)
node _T_211 = eq(_T_210, UInt<1>(0h0))
node _T_212 = asUInt(reset)
node _T_213 = eq(_T_212, UInt<1>(0h0))
when _T_213 :
node _T_214 = eq(_T_211, UInt<1>(0h0))
when _T_214 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27
assert(clock, _T_211, UInt<1>(0h1), "") : assert_27
node _T_215 = eq(before, UInt<1>(0h0))
node _T_216 = eq(after, UInt<3>(0h5))
node _T_217 = and(_T_215, _T_216)
node _T_218 = eq(_T_217, UInt<1>(0h0))
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28
assert(clock, _T_218, UInt<1>(0h1), "") : assert_28
node _T_222 = eq(before, UInt<1>(0h0))
node _T_223 = eq(after, UInt<3>(0h6))
node _T_224 = and(_T_222, _T_223)
node _T_225 = eq(_T_224, UInt<1>(0h0))
node _T_226 = asUInt(reset)
node _T_227 = eq(_T_226, UInt<1>(0h0))
when _T_227 :
node _T_228 = eq(_T_225, UInt<1>(0h0))
when _T_228 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29
assert(clock, _T_225, UInt<1>(0h1), "") : assert_29
node _T_229 = eq(before, UInt<1>(0h0))
node _T_230 = eq(after, UInt<3>(0h4))
node _T_231 = and(_T_229, _T_230)
node _T_232 = eq(_T_231, UInt<1>(0h0))
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30
assert(clock, _T_232, UInt<1>(0h1), "") : assert_30
node _T_236 = eq(before, UInt<1>(0h0))
node _T_237 = eq(after, UInt<2>(0h3))
node _T_238 = and(_T_236, _T_237)
node _T_239 = eq(_T_238, UInt<1>(0h0))
node _T_240 = asUInt(reset)
node _T_241 = eq(_T_240, UInt<1>(0h0))
when _T_241 :
node _T_242 = eq(_T_239, UInt<1>(0h0))
when _T_242 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31
assert(clock, _T_239, UInt<1>(0h1), "") : assert_31
node _T_243 = eq(before, UInt<1>(0h0))
node _T_244 = eq(after, UInt<2>(0h2))
node _T_245 = and(_T_243, _T_244)
node _T_246 = eq(_T_245, UInt<1>(0h0))
node _T_247 = asUInt(reset)
node _T_248 = eq(_T_247, UInt<1>(0h0))
when _T_248 :
node _T_249 = eq(_T_246, UInt<1>(0h0))
when _T_249 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32
assert(clock, _T_246, UInt<1>(0h1), "") : assert_32
node _T_250 = eq(before, UInt<3>(0h7))
node _T_251 = eq(after, UInt<4>(0h8))
node _T_252 = and(_T_250, _T_251)
node _T_253 = eq(_T_252, UInt<1>(0h0))
node _T_254 = asUInt(reset)
node _T_255 = eq(_T_254, UInt<1>(0h0))
when _T_255 :
node _T_256 = eq(_T_253, UInt<1>(0h0))
when _T_256 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33
assert(clock, _T_253, UInt<1>(0h1), "") : assert_33
node _T_257 = eq(before, UInt<3>(0h7))
node _T_258 = eq(after, UInt<1>(0h1))
node _T_259 = and(_T_257, _T_258)
node _T_260 = eq(_T_259, UInt<1>(0h0))
node _T_261 = asUInt(reset)
node _T_262 = eq(_T_261, UInt<1>(0h0))
when _T_262 :
node _T_263 = eq(_T_260, UInt<1>(0h0))
when _T_263 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34
assert(clock, _T_260, UInt<1>(0h1), "") : assert_34
node _T_264 = eq(before, UInt<3>(0h7))
node _T_265 = eq(after, UInt<1>(0h0))
node _T_266 = and(_T_264, _T_265)
node _T_267 = eq(_T_266, UInt<1>(0h0))
node _T_268 = asUInt(reset)
node _T_269 = eq(_T_268, UInt<1>(0h0))
when _T_269 :
node _T_270 = eq(_T_267, UInt<1>(0h0))
when _T_270 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35
assert(clock, _T_267, UInt<1>(0h1), "") : assert_35
node _T_271 = eq(before, UInt<3>(0h7))
node _T_272 = eq(after, UInt<3>(0h5))
node _T_273 = and(_T_271, _T_272)
node _T_274 = eq(_T_273, UInt<1>(0h0))
node _T_275 = asUInt(reset)
node _T_276 = eq(_T_275, UInt<1>(0h0))
when _T_276 :
node _T_277 = eq(_T_274, UInt<1>(0h0))
when _T_277 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36
assert(clock, _T_274, UInt<1>(0h1), "") : assert_36
node _T_278 = eq(before, UInt<3>(0h7))
node _T_279 = eq(after, UInt<3>(0h6))
node _T_280 = and(_T_278, _T_279)
node _T_281 = eq(before, UInt<3>(0h7))
node _T_282 = eq(after, UInt<3>(0h4))
node _T_283 = and(_T_281, _T_282)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = asUInt(reset)
node _T_286 = eq(_T_285, UInt<1>(0h0))
when _T_286 :
node _T_287 = eq(_T_284, UInt<1>(0h0))
when _T_287 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37
assert(clock, _T_284, UInt<1>(0h1), "") : assert_37
node _T_288 = eq(before, UInt<3>(0h7))
node _T_289 = eq(after, UInt<2>(0h3))
node _T_290 = and(_T_288, _T_289)
node _T_291 = eq(before, UInt<3>(0h7))
node _T_292 = eq(after, UInt<2>(0h2))
node _T_293 = and(_T_291, _T_292)
node _T_294 = eq(_T_293, UInt<1>(0h0))
node _T_295 = asUInt(reset)
node _T_296 = eq(_T_295, UInt<1>(0h0))
when _T_296 :
node _T_297 = eq(_T_294, UInt<1>(0h0))
when _T_297 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38
assert(clock, _T_294, UInt<1>(0h1), "") : assert_38
node _T_298 = eq(before, UInt<3>(0h5))
node _T_299 = eq(after, UInt<4>(0h8))
node _T_300 = and(_T_298, _T_299)
node _T_301 = eq(_T_300, UInt<1>(0h0))
node _T_302 = asUInt(reset)
node _T_303 = eq(_T_302, UInt<1>(0h0))
when _T_303 :
node _T_304 = eq(_T_301, UInt<1>(0h0))
when _T_304 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39
assert(clock, _T_301, UInt<1>(0h1), "") : assert_39
node _T_305 = eq(before, UInt<3>(0h5))
node _T_306 = eq(after, UInt<1>(0h1))
node _T_307 = and(_T_305, _T_306)
node _T_308 = eq(_T_307, UInt<1>(0h0))
node _T_309 = asUInt(reset)
node _T_310 = eq(_T_309, UInt<1>(0h0))
when _T_310 :
node _T_311 = eq(_T_308, UInt<1>(0h0))
when _T_311 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40
assert(clock, _T_308, UInt<1>(0h1), "") : assert_40
node _T_312 = eq(before, UInt<3>(0h5))
node _T_313 = eq(after, UInt<1>(0h0))
node _T_314 = and(_T_312, _T_313)
node _T_315 = eq(_T_314, UInt<1>(0h0))
node _T_316 = asUInt(reset)
node _T_317 = eq(_T_316, UInt<1>(0h0))
when _T_317 :
node _T_318 = eq(_T_315, UInt<1>(0h0))
when _T_318 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41
assert(clock, _T_315, UInt<1>(0h1), "") : assert_41
node _T_319 = eq(before, UInt<3>(0h5))
node _T_320 = eq(after, UInt<3>(0h7))
node _T_321 = and(_T_319, _T_320)
node _T_322 = eq(before, UInt<3>(0h5))
node _T_323 = eq(after, UInt<3>(0h6))
node _T_324 = and(_T_322, _T_323)
node _T_325 = eq(before, UInt<3>(0h5))
node _T_326 = eq(after, UInt<3>(0h4))
node _T_327 = and(_T_325, _T_326)
node _T_328 = eq(_T_327, UInt<1>(0h0))
node _T_329 = asUInt(reset)
node _T_330 = eq(_T_329, UInt<1>(0h0))
when _T_330 :
node _T_331 = eq(_T_328, UInt<1>(0h0))
when _T_331 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42
assert(clock, _T_328, UInt<1>(0h1), "") : assert_42
node _T_332 = eq(before, UInt<3>(0h5))
node _T_333 = eq(after, UInt<2>(0h3))
node _T_334 = and(_T_332, _T_333)
node _T_335 = eq(before, UInt<3>(0h5))
node _T_336 = eq(after, UInt<2>(0h2))
node _T_337 = and(_T_335, _T_336)
node _T_338 = eq(_T_337, UInt<1>(0h0))
node _T_339 = asUInt(reset)
node _T_340 = eq(_T_339, UInt<1>(0h0))
when _T_340 :
node _T_341 = eq(_T_338, UInt<1>(0h0))
when _T_341 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43
assert(clock, _T_338, UInt<1>(0h1), "") : assert_43
node _T_342 = eq(before, UInt<3>(0h6))
node _T_343 = eq(after, UInt<4>(0h8))
node _T_344 = and(_T_342, _T_343)
node _T_345 = eq(_T_344, UInt<1>(0h0))
node _T_346 = asUInt(reset)
node _T_347 = eq(_T_346, UInt<1>(0h0))
when _T_347 :
node _T_348 = eq(_T_345, UInt<1>(0h0))
when _T_348 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44
assert(clock, _T_345, UInt<1>(0h1), "") : assert_44
node _T_349 = eq(before, UInt<3>(0h6))
node _T_350 = eq(after, UInt<1>(0h1))
node _T_351 = and(_T_349, _T_350)
node _T_352 = eq(_T_351, UInt<1>(0h0))
node _T_353 = asUInt(reset)
node _T_354 = eq(_T_353, UInt<1>(0h0))
when _T_354 :
node _T_355 = eq(_T_352, UInt<1>(0h0))
when _T_355 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45
assert(clock, _T_352, UInt<1>(0h1), "") : assert_45
node _T_356 = eq(before, UInt<3>(0h6))
node _T_357 = eq(after, UInt<1>(0h0))
node _T_358 = and(_T_356, _T_357)
node _T_359 = eq(_T_358, UInt<1>(0h0))
node _T_360 = asUInt(reset)
node _T_361 = eq(_T_360, UInt<1>(0h0))
when _T_361 :
node _T_362 = eq(_T_359, UInt<1>(0h0))
when _T_362 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46
assert(clock, _T_359, UInt<1>(0h1), "") : assert_46
node _T_363 = eq(before, UInt<3>(0h6))
node _T_364 = eq(after, UInt<3>(0h7))
node _T_365 = and(_T_363, _T_364)
node _T_366 = eq(_T_365, UInt<1>(0h0))
node _T_367 = asUInt(reset)
node _T_368 = eq(_T_367, UInt<1>(0h0))
when _T_368 :
node _T_369 = eq(_T_366, UInt<1>(0h0))
when _T_369 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47
assert(clock, _T_366, UInt<1>(0h1), "") : assert_47
node _T_370 = eq(before, UInt<3>(0h6))
node _T_371 = eq(after, UInt<3>(0h5))
node _T_372 = and(_T_370, _T_371)
node _T_373 = eq(_T_372, UInt<1>(0h0))
node _T_374 = asUInt(reset)
node _T_375 = eq(_T_374, UInt<1>(0h0))
when _T_375 :
node _T_376 = eq(_T_373, UInt<1>(0h0))
when _T_376 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48
assert(clock, _T_373, UInt<1>(0h1), "") : assert_48
node _T_377 = eq(before, UInt<3>(0h6))
node _T_378 = eq(after, UInt<3>(0h4))
node _T_379 = and(_T_377, _T_378)
node _T_380 = eq(_T_379, UInt<1>(0h0))
node _T_381 = asUInt(reset)
node _T_382 = eq(_T_381, UInt<1>(0h0))
when _T_382 :
node _T_383 = eq(_T_380, UInt<1>(0h0))
when _T_383 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49
assert(clock, _T_380, UInt<1>(0h1), "") : assert_49
node _T_384 = eq(before, UInt<3>(0h6))
node _T_385 = eq(after, UInt<2>(0h3))
node _T_386 = and(_T_384, _T_385)
node _T_387 = eq(_T_386, UInt<1>(0h0))
node _T_388 = asUInt(reset)
node _T_389 = eq(_T_388, UInt<1>(0h0))
when _T_389 :
node _T_390 = eq(_T_387, UInt<1>(0h0))
when _T_390 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50
assert(clock, _T_387, UInt<1>(0h1), "") : assert_50
node _T_391 = eq(before, UInt<3>(0h6))
node _T_392 = eq(after, UInt<2>(0h2))
node _T_393 = and(_T_391, _T_392)
node _T_394 = eq(before, UInt<3>(0h4))
node _T_395 = eq(after, UInt<4>(0h8))
node _T_396 = and(_T_394, _T_395)
node _T_397 = eq(_T_396, UInt<1>(0h0))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51
assert(clock, _T_397, UInt<1>(0h1), "") : assert_51
node _T_401 = eq(before, UInt<3>(0h4))
node _T_402 = eq(after, UInt<1>(0h1))
node _T_403 = and(_T_401, _T_402)
node _T_404 = eq(_T_403, UInt<1>(0h0))
node _T_405 = asUInt(reset)
node _T_406 = eq(_T_405, UInt<1>(0h0))
when _T_406 :
node _T_407 = eq(_T_404, UInt<1>(0h0))
when _T_407 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52
assert(clock, _T_404, UInt<1>(0h1), "") : assert_52
node _T_408 = eq(before, UInt<3>(0h4))
node _T_409 = eq(after, UInt<1>(0h0))
node _T_410 = and(_T_408, _T_409)
node _T_411 = eq(_T_410, UInt<1>(0h0))
node _T_412 = asUInt(reset)
node _T_413 = eq(_T_412, UInt<1>(0h0))
when _T_413 :
node _T_414 = eq(_T_411, UInt<1>(0h0))
when _T_414 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53
assert(clock, _T_411, UInt<1>(0h1), "") : assert_53
node _T_415 = eq(before, UInt<3>(0h4))
node _T_416 = eq(after, UInt<3>(0h7))
node _T_417 = and(_T_415, _T_416)
node _T_418 = eq(_T_417, UInt<1>(0h0))
node _T_419 = asUInt(reset)
node _T_420 = eq(_T_419, UInt<1>(0h0))
when _T_420 :
node _T_421 = eq(_T_418, UInt<1>(0h0))
when _T_421 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54
assert(clock, _T_418, UInt<1>(0h1), "") : assert_54
node _T_422 = eq(before, UInt<3>(0h4))
node _T_423 = eq(after, UInt<3>(0h5))
node _T_424 = and(_T_422, _T_423)
node _T_425 = eq(_T_424, UInt<1>(0h0))
node _T_426 = asUInt(reset)
node _T_427 = eq(_T_426, UInt<1>(0h0))
when _T_427 :
node _T_428 = eq(_T_425, UInt<1>(0h0))
when _T_428 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55
assert(clock, _T_425, UInt<1>(0h1), "") : assert_55
node _T_429 = eq(before, UInt<3>(0h4))
node _T_430 = eq(after, UInt<3>(0h6))
node _T_431 = and(_T_429, _T_430)
node _T_432 = eq(before, UInt<3>(0h4))
node _T_433 = eq(after, UInt<2>(0h3))
node _T_434 = and(_T_432, _T_433)
node _T_435 = eq(_T_434, UInt<1>(0h0))
node _T_436 = asUInt(reset)
node _T_437 = eq(_T_436, UInt<1>(0h0))
when _T_437 :
node _T_438 = eq(_T_435, UInt<1>(0h0))
when _T_438 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56
assert(clock, _T_435, UInt<1>(0h1), "") : assert_56
node _T_439 = eq(before, UInt<3>(0h4))
node _T_440 = eq(after, UInt<2>(0h2))
node _T_441 = and(_T_439, _T_440)
node _T_442 = eq(before, UInt<2>(0h3))
node _T_443 = eq(after, UInt<4>(0h8))
node _T_444 = and(_T_442, _T_443)
node _T_445 = eq(_T_444, UInt<1>(0h0))
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57
assert(clock, _T_445, UInt<1>(0h1), "") : assert_57
node _T_449 = eq(before, UInt<2>(0h3))
node _T_450 = eq(after, UInt<1>(0h1))
node _T_451 = and(_T_449, _T_450)
node _T_452 = eq(_T_451, UInt<1>(0h0))
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(_T_452, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58
assert(clock, _T_452, UInt<1>(0h1), "") : assert_58
node _T_456 = eq(before, UInt<2>(0h3))
node _T_457 = eq(after, UInt<1>(0h0))
node _T_458 = and(_T_456, _T_457)
node _T_459 = eq(_T_458, UInt<1>(0h0))
node _T_460 = asUInt(reset)
node _T_461 = eq(_T_460, UInt<1>(0h0))
when _T_461 :
node _T_462 = eq(_T_459, UInt<1>(0h0))
when _T_462 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59
assert(clock, _T_459, UInt<1>(0h1), "") : assert_59
node _T_463 = eq(before, UInt<2>(0h3))
node _T_464 = eq(after, UInt<3>(0h7))
node _T_465 = and(_T_463, _T_464)
node _T_466 = eq(before, UInt<2>(0h3))
node _T_467 = eq(after, UInt<3>(0h5))
node _T_468 = and(_T_466, _T_467)
node _T_469 = eq(before, UInt<2>(0h3))
node _T_470 = eq(after, UInt<3>(0h6))
node _T_471 = and(_T_469, _T_470)
node _T_472 = eq(before, UInt<2>(0h3))
node _T_473 = eq(after, UInt<3>(0h4))
node _T_474 = and(_T_472, _T_473)
node _T_475 = eq(before, UInt<2>(0h3))
node _T_476 = eq(after, UInt<2>(0h2))
node _T_477 = and(_T_475, _T_476)
node _T_478 = eq(before, UInt<2>(0h2))
node _T_479 = eq(after, UInt<4>(0h8))
node _T_480 = and(_T_478, _T_479)
node _T_481 = eq(_T_480, UInt<1>(0h0))
node _T_482 = asUInt(reset)
node _T_483 = eq(_T_482, UInt<1>(0h0))
when _T_483 :
node _T_484 = eq(_T_481, UInt<1>(0h0))
when _T_484 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60
assert(clock, _T_481, UInt<1>(0h1), "") : assert_60
node _T_485 = eq(before, UInt<2>(0h2))
node _T_486 = eq(after, UInt<1>(0h1))
node _T_487 = and(_T_485, _T_486)
node _T_488 = eq(_T_487, UInt<1>(0h0))
node _T_489 = asUInt(reset)
node _T_490 = eq(_T_489, UInt<1>(0h0))
when _T_490 :
node _T_491 = eq(_T_488, UInt<1>(0h0))
when _T_491 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61
assert(clock, _T_488, UInt<1>(0h1), "") : assert_61
node _T_492 = eq(before, UInt<2>(0h2))
node _T_493 = eq(after, UInt<1>(0h0))
node _T_494 = and(_T_492, _T_493)
node _T_495 = eq(_T_494, UInt<1>(0h0))
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_T_495, UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62
assert(clock, _T_495, UInt<1>(0h1), "") : assert_62
node _T_499 = eq(before, UInt<2>(0h2))
node _T_500 = eq(after, UInt<3>(0h7))
node _T_501 = and(_T_499, _T_500)
node _T_502 = eq(_T_501, UInt<1>(0h0))
node _T_503 = asUInt(reset)
node _T_504 = eq(_T_503, UInt<1>(0h0))
when _T_504 :
node _T_505 = eq(_T_502, UInt<1>(0h0))
when _T_505 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63
assert(clock, _T_502, UInt<1>(0h1), "") : assert_63
node _T_506 = eq(before, UInt<2>(0h2))
node _T_507 = eq(after, UInt<3>(0h5))
node _T_508 = and(_T_506, _T_507)
node _T_509 = eq(_T_508, UInt<1>(0h0))
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64
assert(clock, _T_509, UInt<1>(0h1), "") : assert_64
node _T_513 = eq(before, UInt<2>(0h2))
node _T_514 = eq(after, UInt<3>(0h6))
node _T_515 = and(_T_513, _T_514)
node _T_516 = eq(before, UInt<2>(0h2))
node _T_517 = eq(after, UInt<3>(0h4))
node _T_518 = and(_T_516, _T_517)
node _T_519 = eq(before, UInt<2>(0h2))
node _T_520 = eq(after, UInt<2>(0h3))
node _T_521 = and(_T_519, _T_520)
node _T_522 = eq(_T_521, UInt<1>(0h0))
node _T_523 = asUInt(reset)
node _T_524 = eq(_T_523, UInt<1>(0h0))
when _T_524 :
node _T_525 = eq(_T_522, UInt<1>(0h0))
when _T_525 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65
assert(clock, _T_522, UInt<1>(0h1), "") : assert_65
node _probe_bit_uncommonBits_T = or(io.sinkc.bits.source, UInt<3>(0h0))
node probe_bit_uncommonBits = bits(_probe_bit_uncommonBits_T, 2, 0)
node _probe_bit_T = shr(io.sinkc.bits.source, 3)
node _probe_bit_T_1 = eq(_probe_bit_T, UInt<4>(0h8))
node _probe_bit_T_2 = leq(UInt<1>(0h0), probe_bit_uncommonBits)
node _probe_bit_T_3 = and(_probe_bit_T_1, _probe_bit_T_2)
node _probe_bit_T_4 = leq(probe_bit_uncommonBits, UInt<3>(0h4))
node probe_bit = and(_probe_bit_T_3, _probe_bit_T_4)
node _last_probe_T = or(probes_done, probe_bit)
node _last_probe_T_1 = not(excluded_client)
node _last_probe_T_2 = and(meta.clients, _last_probe_T_1)
node last_probe = eq(_last_probe_T, _last_probe_T_2)
node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1))
node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2))
node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1)
node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5))
node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3)
when io.sinkc.valid :
node _T_526 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1))
node _T_527 = and(probe_toN, _T_526)
node _T_528 = eq(probe_toN, UInt<1>(0h0))
node _T_529 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1))
node _T_530 = and(_T_528, _T_529)
node _probes_done_T = or(probes_done, probe_bit)
connect probes_done, _probes_done_T
node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0))
node _probes_toN_T_1 = or(probes_toN, _probes_toN_T)
connect probes_toN, _probes_toN_T_1
node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3))
node _probes_noT_T_1 = or(probes_noT, _probes_noT_T)
connect probes_noT, _probes_noT_T_1
node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe)
connect w_rprobeackfirst, _w_rprobeackfirst_T
node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last)
node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T)
connect w_rprobeacklast, _w_rprobeacklast_T_1
node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe)
connect w_pprobeackfirst, _w_pprobeackfirst_T
node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last)
node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T)
connect w_pprobeacklast, _w_pprobeacklast_T_1
node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0))
node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T)
node set_pprobeack = and(last_probe, _set_pprobeack_T_1)
node _w_pprobeack_T = or(w_pprobeack, set_pprobeack)
connect w_pprobeack, _w_pprobeack_T
node _T_531 = eq(set_pprobeack, UInt<1>(0h0))
node _T_532 = and(_T_531, w_rprobeackfirst)
node _T_533 = and(set_pprobeack, w_rprobeackfirst)
node _T_534 = neq(meta.state, UInt<2>(0h0))
node _T_535 = eq(io.sinkc.bits.tag, meta.tag)
node _T_536 = and(_T_534, _T_535)
node _T_537 = and(_T_536, io.sinkc.bits.data)
when _T_537 :
connect meta.dirty, UInt<1>(0h1)
when io.sinkd.valid :
node _T_538 = eq(io.sinkd.bits.opcode, UInt<3>(0h4))
node _T_539 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_540 = or(_T_538, _T_539)
when _T_540 :
connect sink, io.sinkd.bits.sink
connect w_grantfirst, UInt<1>(0h1)
connect w_grantlast, io.sinkd.bits.last
connect bad_grant, io.sinkd.bits.denied
node _w_grant_T = eq(request.offset, UInt<1>(0h0))
node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last)
connect w_grant, _w_grant_T_1
node _T_541 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_542 = eq(request.offset, UInt<1>(0h0))
node _T_543 = and(_T_541, _T_542)
node _T_544 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_545 = neq(request.offset, UInt<1>(0h0))
node _T_546 = and(_T_544, _T_545)
node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0))
connect gotT, _gotT_T
else :
node _T_547 = eq(io.sinkd.bits.opcode, UInt<3>(0h6))
when _T_547 :
connect w_releaseack, UInt<1>(0h1)
when io.sinke.valid :
connect w_grantack, UInt<1>(0h1)
wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}
connect allocate_as_full.set, io.allocate.bits.set
connect allocate_as_full.put, io.allocate.bits.put
connect allocate_as_full.offset, io.allocate.bits.offset
connect allocate_as_full.tag, io.allocate.bits.tag
connect allocate_as_full.source, io.allocate.bits.source
connect allocate_as_full.size, io.allocate.bits.size
connect allocate_as_full.param, io.allocate.bits.param
connect allocate_as_full.opcode, io.allocate.bits.opcode
connect allocate_as_full.control, io.allocate.bits.control
connect allocate_as_full.prio, io.allocate.bits.prio
node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat)
node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits)
node new_request = mux(io.allocate.valid, allocate_as_full, request)
node _new_needT_T = bits(new_request.opcode, 2, 2)
node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0))
node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5))
node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1))
node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3)
node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4)
node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6))
node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7))
node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7)
node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0))
node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9)
node new_needT = or(_new_needT_T_5, _new_needT_T_10)
node _new_clientBit_uncommonBits_T = or(new_request.source, UInt<3>(0h0))
node new_clientBit_uncommonBits = bits(_new_clientBit_uncommonBits_T, 2, 0)
node _new_clientBit_T = shr(new_request.source, 3)
node _new_clientBit_T_1 = eq(_new_clientBit_T, UInt<4>(0h8))
node _new_clientBit_T_2 = leq(UInt<1>(0h0), new_clientBit_uncommonBits)
node _new_clientBit_T_3 = and(_new_clientBit_T_1, _new_clientBit_T_2)
node _new_clientBit_T_4 = leq(new_clientBit_uncommonBits, UInt<3>(0h4))
node new_clientBit = and(_new_clientBit_T_3, _new_clientBit_T_4)
node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6))
node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7))
node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1)
node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4))
node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3)
node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5))
node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0))
node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6)
node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0))
wire prior : UInt
connect prior, UInt<1>(0h0)
node prior_c = orr(final_meta_writeback.clients)
node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state)
when _prior_T :
node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1))
connect prior, _prior_out_T
else :
node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state)
when _prior_T_1 :
node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect prior, _prior_out_T_1
else :
node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state)
when _prior_T_2 :
node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3)
connect prior, _prior_out_T_4
else :
node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state)
when _prior_T_3 :
connect prior, UInt<4>(0h8)
node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0))
when _prior_T_4 :
connect prior, UInt<4>(0h8)
node _T_548 = and(io.allocate.valid, io.allocate.bits.repeat)
when _T_548 :
node _T_549 = eq(prior, UInt<4>(0h8))
node _T_550 = eq(prior, UInt<1>(0h1))
node _T_551 = eq(_T_550, UInt<1>(0h0))
node _T_552 = asUInt(reset)
node _T_553 = eq(_T_552, UInt<1>(0h0))
when _T_553 :
node _T_554 = eq(_T_551, UInt<1>(0h0))
when _T_554 :
printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_66
assert(clock, _T_551, UInt<1>(0h1), "") : assert_66
node _T_555 = eq(prior, UInt<1>(0h0))
node _T_556 = eq(_T_555, UInt<1>(0h0))
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_67
assert(clock, _T_556, UInt<1>(0h1), "") : assert_67
node _T_560 = eq(prior, UInt<3>(0h7))
node _T_561 = eq(prior, UInt<3>(0h5))
node _T_562 = eq(prior, UInt<3>(0h4))
node _T_563 = eq(prior, UInt<3>(0h6))
node _T_564 = eq(prior, UInt<2>(0h3))
node _T_565 = eq(prior, UInt<2>(0h2))
when io.allocate.valid :
node _T_566 = eq(request_valid, UInt<1>(0h0))
node _T_567 = and(io.schedule.ready, io.schedule.valid)
node _T_568 = and(no_wait, _T_567)
node _T_569 = or(_T_566, _T_568)
node _T_570 = asUInt(reset)
node _T_571 = eq(_T_570, UInt<1>(0h0))
when _T_571 :
node _T_572 = eq(_T_569, UInt<1>(0h0))
when _T_572 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid || (no_wait && io.schedule.fire))\n") : printf_68
assert(clock, _T_569, UInt<1>(0h1), "") : assert_68
connect request_valid, UInt<1>(0h1)
connect request.set, io.allocate.bits.set
connect request.put, io.allocate.bits.put
connect request.offset, io.allocate.bits.offset
connect request.tag, io.allocate.bits.tag
connect request.source, io.allocate.bits.source
connect request.size, io.allocate.bits.size
connect request.param, io.allocate.bits.param
connect request.opcode, io.allocate.bits.opcode
connect request.control, io.allocate.bits.control
connect request.prio, io.allocate.bits.prio
node _T_573 = and(io.allocate.valid, io.allocate.bits.repeat)
node _T_574 = or(io.directory.valid, _T_573)
when _T_574 :
connect meta_valid, UInt<1>(0h1)
connect meta, new_meta
connect probes_done, UInt<1>(0h0)
connect probes_toN, UInt<1>(0h0)
connect probes_noT, UInt<1>(0h0)
connect gotT, UInt<1>(0h0)
connect bad_grant, UInt<1>(0h0)
connect s_rprobe, UInt<1>(0h1)
connect w_rprobeackfirst, UInt<1>(0h1)
connect w_rprobeacklast, UInt<1>(0h1)
connect s_release, UInt<1>(0h1)
connect w_releaseack, UInt<1>(0h1)
connect s_pprobe, UInt<1>(0h1)
connect s_acquire, UInt<1>(0h1)
connect s_flush, UInt<1>(0h1)
connect w_grantfirst, UInt<1>(0h1)
connect w_grantlast, UInt<1>(0h1)
connect w_grant, UInt<1>(0h1)
connect w_pprobeackfirst, UInt<1>(0h1)
connect w_pprobeacklast, UInt<1>(0h1)
connect w_pprobeack, UInt<1>(0h1)
connect s_probeack, UInt<1>(0h1)
connect s_grantack, UInt<1>(0h1)
connect s_execute, UInt<1>(0h1)
connect w_grantack, UInt<1>(0h1)
connect s_writeback, UInt<1>(0h1)
node _T_575 = and(new_request.prio[2], UInt<1>(0h1))
when _T_575 :
connect s_execute, UInt<1>(0h0)
node _T_576 = bits(new_request.opcode, 0, 0)
node _T_577 = eq(new_meta.dirty, UInt<1>(0h0))
node _T_578 = and(_T_576, _T_577)
when _T_578 :
connect s_writeback, UInt<1>(0h0)
node _T_579 = eq(new_request.param, UInt<3>(0h0))
node _T_580 = eq(new_request.param, UInt<3>(0h4))
node _T_581 = or(_T_579, _T_580)
node _T_582 = eq(new_meta.state, UInt<2>(0h2))
node _T_583 = and(_T_581, _T_582)
when _T_583 :
connect s_writeback, UInt<1>(0h0)
node _T_584 = eq(new_request.param, UInt<3>(0h1))
node _T_585 = eq(new_request.param, UInt<3>(0h2))
node _T_586 = or(_T_584, _T_585)
node _T_587 = eq(new_request.param, UInt<3>(0h5))
node _T_588 = or(_T_586, _T_587)
node _T_589 = and(new_meta.clients, new_clientBit)
node _T_590 = neq(_T_589, UInt<1>(0h0))
node _T_591 = and(_T_588, _T_590)
when _T_591 :
connect s_writeback, UInt<1>(0h0)
node _T_592 = asUInt(reset)
node _T_593 = eq(_T_592, UInt<1>(0h0))
when _T_593 :
node _T_594 = eq(new_meta.hit, UInt<1>(0h0))
when _T_594 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_69
assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_69
else :
node _T_595 = and(new_request.control, UInt<1>(0h1))
when _T_595 :
connect s_flush, UInt<1>(0h0)
when new_meta.hit :
connect s_release, UInt<1>(0h0)
connect w_releaseack, UInt<1>(0h0)
node _T_596 = neq(new_meta.clients, UInt<1>(0h0))
node _T_597 = and(UInt<1>(0h1), _T_596)
when _T_597 :
connect s_rprobe, UInt<1>(0h0)
connect w_rprobeackfirst, UInt<1>(0h0)
connect w_rprobeacklast, UInt<1>(0h0)
else :
connect s_execute, UInt<1>(0h0)
node _T_598 = eq(new_meta.hit, UInt<1>(0h0))
node _T_599 = neq(new_meta.state, UInt<2>(0h0))
node _T_600 = and(_T_598, _T_599)
when _T_600 :
connect s_release, UInt<1>(0h0)
connect w_releaseack, UInt<1>(0h0)
node _T_601 = neq(new_meta.clients, UInt<1>(0h0))
node _T_602 = and(UInt<1>(0h1), _T_601)
when _T_602 :
connect s_rprobe, UInt<1>(0h0)
connect w_rprobeackfirst, UInt<1>(0h0)
connect w_rprobeacklast, UInt<1>(0h0)
node _T_603 = eq(new_meta.hit, UInt<1>(0h0))
node _T_604 = eq(new_meta.state, UInt<2>(0h1))
node _T_605 = and(_T_604, new_needT)
node _T_606 = or(_T_603, _T_605)
when _T_606 :
connect s_acquire, UInt<1>(0h0)
connect w_grantfirst, UInt<1>(0h0)
connect w_grantlast, UInt<1>(0h0)
connect w_grant, UInt<1>(0h0)
connect s_grantack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_607 = eq(new_meta.state, UInt<2>(0h2))
node _T_608 = or(new_needT, _T_607)
node _T_609 = and(new_meta.hit, _T_608)
node _T_610 = not(new_skipProbe)
node _T_611 = and(new_meta.clients, _T_610)
node _T_612 = neq(_T_611, UInt<1>(0h0))
node _T_613 = and(_T_609, _T_612)
node _T_614 = and(UInt<1>(0h1), _T_613)
when _T_614 :
connect s_pprobe, UInt<1>(0h0)
connect w_pprobeackfirst, UInt<1>(0h0)
connect w_pprobeacklast, UInt<1>(0h0)
connect w_pprobeack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_615 = eq(new_request.opcode, UInt<3>(0h6))
node _T_616 = eq(new_request.opcode, UInt<3>(0h7))
node _T_617 = or(_T_615, _T_616)
when _T_617 :
connect w_grantack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_618 = bits(new_request.opcode, 2, 2)
node _T_619 = eq(_T_618, UInt<1>(0h0))
node _T_620 = and(_T_619, new_meta.hit)
node _T_621 = eq(new_meta.dirty, UInt<1>(0h0))
node _T_622 = and(_T_620, _T_621)
when _T_622 :
connect s_writeback, UInt<1>(0h0) | module MSHR_5( // @[MSHR.scala:84:7]
input clock, // @[MSHR.scala:84:7]
input reset, // @[MSHR.scala:84:7]
input io_allocate_valid, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_0, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_1, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_2, // @[MSHR.scala:86:14]
input io_allocate_bits_control, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14]
input [6:0] io_allocate_bits_source, // @[MSHR.scala:86:14]
input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14]
input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14]
input io_allocate_bits_repeat, // @[MSHR.scala:86:14]
input io_directory_valid, // @[MSHR.scala:86:14]
input io_directory_bits_dirty, // @[MSHR.scala:86:14]
input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14]
input io_directory_bits_clients, // @[MSHR.scala:86:14]
input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14]
input io_directory_bits_hit, // @[MSHR.scala:86:14]
input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14]
output io_status_valid, // @[MSHR.scala:86:14]
output [9:0] io_status_bits_set, // @[MSHR.scala:86:14]
output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14]
output [2:0] io_status_bits_way, // @[MSHR.scala:86:14]
output io_status_bits_blockB, // @[MSHR.scala:86:14]
output io_status_bits_nestB, // @[MSHR.scala:86:14]
output io_status_bits_blockC, // @[MSHR.scala:86:14]
output io_status_bits_nestC, // @[MSHR.scala:86:14]
input io_schedule_ready, // @[MSHR.scala:86:14]
output io_schedule_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_a_valid, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14]
output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14]
output io_schedule_bits_b_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14]
output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14]
output io_schedule_bits_c_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14]
output io_schedule_bits_d_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14]
output [6:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14]
output io_schedule_bits_e_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14]
output io_schedule_bits_x_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14]
output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14]
output io_schedule_bits_reload, // @[MSHR.scala:86:14]
input io_sinkc_valid, // @[MSHR.scala:86:14]
input io_sinkc_bits_last, // @[MSHR.scala:86:14]
input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14]
input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14]
input [6:0] io_sinkc_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14]
input io_sinkc_bits_data, // @[MSHR.scala:86:14]
input io_sinkd_valid, // @[MSHR.scala:86:14]
input io_sinkd_bits_last, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14]
input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14]
input io_sinkd_bits_denied, // @[MSHR.scala:86:14]
input io_sinke_valid, // @[MSHR.scala:86:14]
input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14]
input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14]
input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14]
input io_nestedwb_b_toN, // @[MSHR.scala:86:14]
input io_nestedwb_b_toB, // @[MSHR.scala:86:14]
input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14]
input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14]
);
wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38]
wire final_meta_writeback_clients; // @[MSHR.scala:215:38]
wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38]
wire final_meta_writeback_dirty; // @[MSHR.scala:215:38]
wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7]
wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7]
wire [6:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7]
wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7]
wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7]
wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7]
wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7]
wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7]
wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7]
wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7]
wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7]
wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7]
wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7]
wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7]
wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7]
wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7]
wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7]
wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7]
wire [6:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7]
wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7]
wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7]
wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7]
wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7]
wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7]
wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7]
wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7]
wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7]
wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7]
wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7]
wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7]
wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68]
wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80]
wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21]
wire invalid_clients = 1'h0; // @[MSHR.scala:268:21]
wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137]
wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137]
wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire _req_clientBit_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _probe_bit_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _new_clientBit_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21]
wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21]
wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70]
wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34]
wire [6:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34]
wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34]
wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34]
wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40]
wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93]
wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28]
wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39]
wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105]
wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55]
wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91]
wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41]
wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41]
wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41]
wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51]
wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64]
wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41]
wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41]
wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57]
wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41]
wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43]
wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40]
wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66]
wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41]
wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41]
wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41]
wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41]
wire no_wait; // @[MSHR.scala:183:83]
wire [6:0] _probe_bit_uncommonBits_T = io_sinkc_bits_source_0; // @[Parameters.scala:52:29]
wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7]
wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7]
wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockB_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestB_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockC_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestC_0; // @[MSHR.scala:84:7]
wire io_status_valid_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7]
wire [6:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7]
wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7]
wire io_schedule_valid_0; // @[MSHR.scala:84:7]
reg request_valid; // @[MSHR.scala:97:30]
assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30]
reg request_prio_0; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20]
reg request_prio_1; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20]
reg request_prio_2; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20]
reg request_control; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_opcode; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_param; // @[MSHR.scala:98:20]
reg [2:0] request_size; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20]
reg [6:0] request_source; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20]
wire [6:0] _req_clientBit_uncommonBits_T = request_source; // @[Parameters.scala:52:29]
reg [12:0] request_tag; // @[MSHR.scala:98:20]
assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_offset; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_put; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20]
reg [9:0] request_set; // @[MSHR.scala:98:20]
assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
reg meta_valid; // @[MSHR.scala:99:27]
reg meta_dirty; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17]
reg [1:0] meta_state; // @[MSHR.scala:100:17]
reg meta_clients; // @[MSHR.scala:100:17]
wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39]
wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
reg [12:0] meta_tag; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17]
reg meta_hit; // @[MSHR.scala:100:17]
reg [2:0] meta_way; // @[MSHR.scala:100:17]
assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38]
reg s_rprobe; // @[MSHR.scala:121:33]
reg w_rprobeackfirst; // @[MSHR.scala:122:33]
reg w_rprobeacklast; // @[MSHR.scala:123:33]
reg s_release; // @[MSHR.scala:124:33]
reg w_releaseack; // @[MSHR.scala:125:33]
reg s_pprobe; // @[MSHR.scala:126:33]
reg s_acquire; // @[MSHR.scala:127:33]
reg s_flush; // @[MSHR.scala:128:33]
reg w_grantfirst; // @[MSHR.scala:129:33]
reg w_grantlast; // @[MSHR.scala:130:33]
reg w_grant; // @[MSHR.scala:131:33]
reg w_pprobeackfirst; // @[MSHR.scala:132:33]
reg w_pprobeacklast; // @[MSHR.scala:133:33]
reg w_pprobeack; // @[MSHR.scala:134:33]
reg s_grantack; // @[MSHR.scala:136:33]
reg s_execute; // @[MSHR.scala:137:33]
reg w_grantack; // @[MSHR.scala:138:33]
reg s_writeback; // @[MSHR.scala:139:33]
reg [2:0] sink; // @[MSHR.scala:147:17]
assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17]
reg gotT; // @[MSHR.scala:148:17]
reg bad_grant; // @[MSHR.scala:149:22]
assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22]
reg probes_done; // @[MSHR.scala:150:24]
reg probes_toN; // @[MSHR.scala:151:23]
reg probes_noT; // @[MSHR.scala:152:23]
wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28]
wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45]
wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62]
wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}]
wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82]
wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}]
wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103]
wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}]
assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}]
assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40]
wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39]
wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}]
wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}]
wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96]
assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}]
assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93]
assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28]
assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28]
wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43]
wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64]
wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}]
wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85]
wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}]
assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}]
assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39]
wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33]
wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}]
wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}]
assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}]
assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83]
wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31]
wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}]
assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}]
assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55]
wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31]
wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44]
assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}]
assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41]
wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32]
wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}]
assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}]
assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64]
wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31]
wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}]
assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}]
assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57]
wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31]
assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}]
assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43]
wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31]
assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}]
assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40]
wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34]
wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}]
wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70]
wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}]
assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}]
assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66]
wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49]
wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}]
wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}]
wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49]
wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}]
assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}]
assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105]
wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71]
wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71]
wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71]
wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71]
wire final_meta_writeback_hit; // @[MSHR.scala:215:38]
wire [2:0] req_clientBit_uncommonBits = _req_clientBit_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _req_clientBit_T = request_source[6:3]; // @[Parameters.scala:54:10]
wire _req_clientBit_T_1 = _req_clientBit_T == 4'h8; // @[Parameters.scala:54:{10,32}]
wire _req_clientBit_T_3 = _req_clientBit_T_1; // @[Parameters.scala:54:{32,67}]
wire _req_clientBit_T_4 = req_clientBit_uncommonBits < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire req_clientBit = _req_clientBit_T_3 & _req_clientBit_T_4; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12]
wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12]
wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _req_needT_T_2; // @[Parameters.scala:270:13]
assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13]
wire _excluded_client_T_6; // @[Parameters.scala:279:117]
assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117]
wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42]
wire _req_needT_T_3; // @[Parameters.scala:270:42]
assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42]
wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11]
assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11]
wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42]
wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _req_needT_T_6; // @[Parameters.scala:271:14]
assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14]
wire _req_acquire_T; // @[MSHR.scala:219:36]
assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14]
wire _excluded_client_T_1; // @[Parameters.scala:279:12]
assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12]
wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52]
wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89]
wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52]
wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}]
wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}]
wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81]
wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}]
wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}]
wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}]
wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65]
wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}]
wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55]
wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78]
wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78]
assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78]
wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70]
wire _evict_T_2; // @[MSHR.scala:317:26]
assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _before_T_1; // @[MSHR.scala:317:26]
assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}]
wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}]
wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43]
assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43]
wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75]
wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}]
wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:56:48]
wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}]
wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}]
wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54]
wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}]
wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45]
wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}]
wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}]
wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40]
wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40]
assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40]
wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65]
assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65]
wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41]
wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}]
wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72]
wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}]
wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70]
wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70]
wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53]
assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53]
wire _evict_T_1; // @[MSHR.scala:317:26]
assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire _before_T; // @[MSHR.scala:317:26]
assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70]
wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70]
wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55]
wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70]
wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70]
wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66]
wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}]
wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}]
wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:56:48]
wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40]
assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30]
wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54]
wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}]
assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21]
assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21]
assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36]
assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36]
wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:56:48]
wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}]
wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}]
wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38]
wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}]
wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}]
wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}]
wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106]
wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:56:48]
wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56]
wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70]
assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}]
wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51]
wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55]
wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52]
wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}]
wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}]
assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38]
assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91]
wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42]
wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70]
wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}]
assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}]
assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41]
wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42]
assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}]
assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41]
wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53]
assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}]
assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51]
assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41]
assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41]
assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}]
assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41]
wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42]
wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53]
wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53]
wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89]
wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79]
assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41]
wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42]
assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}]
assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41]
wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32]
wire [3:0] evict; // @[MSHR.scala:314:26]
wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32]
wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32]
wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32]
assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32]
assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39]
wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39]
assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39]
assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76]
wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76]
assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76]
assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32]
assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] before_0; // @[MSHR.scala:314:26]
wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32]
wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11]
assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] after; // @[MSHR.scala:314:26]
wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26]
wire _after_T; // @[MSHR.scala:317:26]
assign _after_T = _GEN_9; // @[MSHR.scala:317:26]
wire _prior_T; // @[MSHR.scala:317:26]
assign _prior_T = _GEN_9; // @[MSHR.scala:317:26]
wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32]
wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26]
wire _after_T_1; // @[MSHR.scala:317:26]
assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire _prior_T_1; // @[MSHR.scala:317:26]
assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32]
wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32]
assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32]
assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39]
wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39]
assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39]
assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76]
wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76]
assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76]
assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26]
wire _after_T_3; // @[MSHR.scala:317:26]
assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26]
wire _prior_T_3; // @[MSHR.scala:317:26]
assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26]
assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire [2:0] probe_bit_uncommonBits = _probe_bit_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _probe_bit_T = io_sinkc_bits_source_0[6:3]; // @[Parameters.scala:54:10]
wire _probe_bit_T_1 = _probe_bit_T == 4'h8; // @[Parameters.scala:54:{10,32}]
wire _probe_bit_T_3 = _probe_bit_T_1; // @[Parameters.scala:54:{32,67}]
wire _probe_bit_T_4 = probe_bit_uncommonBits < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire probe_bit = _probe_bit_T_3 & _probe_bit_T_4; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:56:48]
wire _last_probe_T; // @[MSHR.scala:459:33]
assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33]
wire _probes_done_T; // @[MSHR.scala:467:32]
assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32]
wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66]
wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}]
wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}]
wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11]
wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43]
wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75]
wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}]
wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:56:48]
wire _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}]
wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53]
wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}]
wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42]
wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55]
wire _w_rprobeacklast_T; // @[MSHR.scala:471:55]
assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55]
wire _w_pprobeacklast_T; // @[MSHR.scala:473:55]
assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55]
wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}]
wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42]
wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}]
wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77]
wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}]
wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}]
wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32]
wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33]
wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}]
wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35]
wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40]
wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [6:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [6:0] _new_clientBit_uncommonBits_T = new_request_source; // @[Parameters.scala:52:29]
wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12]
wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _new_needT_T_2; // @[Parameters.scala:270:13]
assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13]
wire _new_skipProbe_T_5; // @[Parameters.scala:279:117]
assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117]
wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42]
wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _new_needT_T_6; // @[Parameters.scala:271:14]
assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14]
wire _new_skipProbe_T; // @[Parameters.scala:279:12]
assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12]
wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52]
wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89]
wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire [2:0] new_clientBit_uncommonBits = _new_clientBit_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _new_clientBit_T = new_request_source[6:3]; // @[Parameters.scala:54:10]
wire _new_clientBit_T_1 = _new_clientBit_T == 4'h8; // @[Parameters.scala:54:{10,32}]
wire _new_clientBit_T_3 = _new_clientBit_T_1; // @[Parameters.scala:54:{32,67}]
wire _new_clientBit_T_4 = new_clientBit_uncommonBits < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire new_clientBit = _new_clientBit_T_3 & _new_clientBit_T_4; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}]
wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}]
wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}]
wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:56:48]
wire [3:0] prior; // @[MSHR.scala:314:26]
wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32]
wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28] |
Generate the Verilog code corresponding to this FIRRTL code module MSHR_56 :
input clock : Clock
input reset : Reset
output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}}, status : { valid : UInt<1>, bits : { set : UInt<11>, tag : UInt<9>, way : UInt<4>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<9>, set : UInt<11>, param : UInt<3>, source : UInt<4>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<9>, set : UInt<11>, clients : UInt<1>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<9>, set : UInt<11>, way : UInt<4>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<11>, way : UInt<4>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<11>, tag : UInt<9>, source : UInt<6>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<4>}}, flip nestedwb : { set : UInt<11>, tag : UInt<9>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}}
regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>}, clock
regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}, clock
when meta_valid :
node _T = eq(meta.state, UInt<2>(0h0))
when _T :
node _T_1 = orr(meta.clients)
node _T_2 = eq(_T_1, UInt<1>(0h0))
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
node _T_6 = eq(meta.dirty, UInt<1>(0h0))
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1
assert(clock, _T_6, UInt<1>(0h1), "") : assert_1
node _T_10 = eq(meta.state, UInt<2>(0h1))
when _T_10 :
node _T_11 = eq(meta.dirty, UInt<1>(0h0))
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2
assert(clock, _T_11, UInt<1>(0h1), "") : assert_2
node _T_15 = eq(meta.state, UInt<2>(0h2))
when _T_15 :
node _T_16 = orr(meta.clients)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3
assert(clock, _T_16, UInt<1>(0h1), "") : assert_3
node _T_20 = sub(meta.clients, UInt<1>(0h1))
node _T_21 = tail(_T_20, 1)
node _T_22 = and(meta.clients, _T_21)
node _T_23 = eq(_T_22, UInt<1>(0h0))
node _T_24 = asUInt(reset)
node _T_25 = eq(_T_24, UInt<1>(0h0))
when _T_25 :
node _T_26 = eq(_T_23, UInt<1>(0h0))
when _T_26 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4
assert(clock, _T_23, UInt<1>(0h1), "") : assert_4
node _T_27 = eq(meta.state, UInt<2>(0h3))
when _T_27 :
skip
regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1)
reg sink : UInt<3>, clock
reg gotT : UInt<1>, clock
reg bad_grant : UInt<1>, clock
reg probes_done : UInt<1>, clock
reg probes_toN : UInt<1>, clock
reg probes_noT : UInt<1>, clock
node _T_28 = neq(meta.state, UInt<2>(0h0))
node _T_29 = and(meta_valid, _T_28)
node _T_30 = eq(io.nestedwb.set, request.set)
node _T_31 = and(_T_29, _T_30)
node _T_32 = eq(io.nestedwb.tag, meta.tag)
node _T_33 = and(_T_31, _T_32)
when _T_33 :
when io.nestedwb.b_clr_dirty :
connect meta.dirty, UInt<1>(0h0)
when io.nestedwb.c_set_dirty :
connect meta.dirty, UInt<1>(0h1)
when io.nestedwb.b_toB :
connect meta.state, UInt<2>(0h1)
when io.nestedwb.b_toN :
connect meta.hit, UInt<1>(0h0)
connect io.status.valid, request_valid
connect io.status.bits.set, request.set
connect io.status.bits.tag, request.tag
connect io.status.bits.way, meta.way
node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0))
node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0))
node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0))
node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2)
node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0))
node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4)
node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6)
node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7)
connect io.status.bits.blockB, _io_status_bits_blockB_T_8
node _io_status_bits_nestB_T = and(meta_valid, w_releaseack)
node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast)
node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast)
node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3)
connect io.status.bits.nestB, _io_status_bits_nestB_T_4
node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0))
connect io.status.bits.blockC, _io_status_bits_blockC_T
node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1)
node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3)
node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4)
connect io.status.bits.nestC, _io_status_bits_nestC_T_5
node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0))
node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0))
node _T_36 = or(_T_34, _T_35)
node _T_37 = asUInt(reset)
node _T_38 = eq(_T_37, UInt<1>(0h0))
when _T_38 :
node _T_39 = eq(_T_36, UInt<1>(0h0))
when _T_39 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB || !io.status.bits.blockB)\n") : printf_5
assert(clock, _T_36, UInt<1>(0h1), "") : assert_5
node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0))
node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0))
node _T_42 = or(_T_40, _T_41)
node _T_43 = asUInt(reset)
node _T_44 = eq(_T_43, UInt<1>(0h0))
when _T_44 :
node _T_45 = eq(_T_42, UInt<1>(0h0))
when _T_45 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC || !io.status.bits.blockC)\n") : printf_6
assert(clock, _T_42, UInt<1>(0h1), "") : assert_6
node _no_wait_T = and(w_rprobeacklast, w_releaseack)
node _no_wait_T_1 = and(_no_wait_T, w_grantlast)
node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast)
node no_wait = and(_no_wait_T_2, w_grantack)
node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0))
node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release)
node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe)
connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2
node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0))
node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1)
connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2
node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0))
node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst)
node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0))
node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst)
node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3)
connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4
node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0))
node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack)
node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant)
connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2
node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0))
node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst)
connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1
node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0))
node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack)
connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1
node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0))
node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst)
node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0))
node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait)
node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3)
connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4
connect io.schedule.bits.reload, no_wait
node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid)
node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid)
node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid)
node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid)
node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid)
node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid)
connect io.schedule.valid, _io_schedule_valid_T_5
when io.schedule.ready :
connect s_rprobe, UInt<1>(0h1)
when w_rprobeackfirst :
connect s_release, UInt<1>(0h1)
connect s_pprobe, UInt<1>(0h1)
node _T_46 = and(s_release, s_pprobe)
when _T_46 :
connect s_acquire, UInt<1>(0h1)
when w_releaseack :
connect s_flush, UInt<1>(0h1)
when w_pprobeackfirst :
connect s_probeack, UInt<1>(0h1)
when w_grantfirst :
connect s_grantack, UInt<1>(0h1)
node _T_47 = and(w_pprobeack, w_grant)
when _T_47 :
connect s_execute, UInt<1>(0h1)
when no_wait :
connect s_writeback, UInt<1>(0h1)
when no_wait :
connect request_valid, UInt<1>(0h0)
connect meta_valid, UInt<1>(0h0)
wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}
connect final_meta_writeback, meta
node req_clientBit = eq(request.source, UInt<6>(0h28))
node _req_needT_T = bits(request.opcode, 2, 2)
node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0))
node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5))
node _req_needT_T_3 = eq(request.param, UInt<1>(0h1))
node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3)
node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4)
node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6))
node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7))
node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7)
node _req_needT_T_9 = neq(request.param, UInt<2>(0h0))
node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9)
node req_needT = or(_req_needT_T_5, _req_needT_T_10)
node _req_acquire_T = eq(request.opcode, UInt<3>(0h6))
node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7))
node req_acquire = or(_req_acquire_T, _req_acquire_T_1)
node _meta_no_clients_T = orr(meta.clients)
node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0))
node _req_promoteT_T = eq(meta.state, UInt<2>(0h3))
node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T)
node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT)
node req_promoteT = and(req_acquire, _req_promoteT_T_2)
node _T_48 = and(request.prio[2], UInt<1>(0h1))
when _T_48 :
node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0)
node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T)
connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1
node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3))
node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2))
node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1)
node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state)
connect final_meta_writeback.state, _final_meta_writeback_state_T_3
node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1))
node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2))
node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1)
node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5))
node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3)
node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0))
node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5)
node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7
connect final_meta_writeback.hit, UInt<1>(0h1)
else :
node _T_49 = and(request.control, UInt<1>(0h1))
when _T_49 :
when meta.hit :
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h0)
node _final_meta_writeback_clients_T_8 = not(probes_toN)
node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9
connect final_meta_writeback.hit, UInt<1>(0h0)
else :
node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty)
node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2)
node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0))
node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4)
connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5
node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0))
node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1))
node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire)
node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state)
node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1))
node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state)
node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11)
node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state)
node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13)
node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15)
node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16)
connect final_meta_writeback.state, _final_meta_writeback_state_T_17
node _final_meta_writeback_clients_T_10 = not(probes_toN)
node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10)
node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0))
node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0))
node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14
connect final_meta_writeback.tag, request.tag
connect final_meta_writeback.hit, UInt<1>(0h1)
when bad_grant :
when meta.hit :
node _T_50 = eq(meta_valid, UInt<1>(0h0))
node _T_51 = eq(meta.state, UInt<2>(0h1))
node _T_52 = or(_T_50, _T_51)
node _T_53 = asUInt(reset)
node _T_54 = eq(_T_53, UInt<1>(0h0))
when _T_54 :
node _T_55 = eq(_T_52, UInt<1>(0h0))
when _T_55 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid || meta.state === BRANCH)\n") : printf_7
assert(clock, _T_52, UInt<1>(0h1), "") : assert_7
connect final_meta_writeback.hit, UInt<1>(0h1)
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h1)
node _final_meta_writeback_clients_T_15 = not(probes_toN)
node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16
else :
connect final_meta_writeback.hit, UInt<1>(0h0)
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h0)
connect final_meta_writeback.clients, UInt<1>(0h0)
wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}
connect invalid.dirty, UInt<1>(0h0)
connect invalid.state, UInt<2>(0h0)
connect invalid.clients, UInt<1>(0h0)
connect invalid.tag, UInt<1>(0h0)
node _honour_BtoT_T = and(meta.clients, req_clientBit)
node _honour_BtoT_T_1 = orr(_honour_BtoT_T)
node honour_BtoT = and(meta.hit, _honour_BtoT_T_1)
node _excluded_client_T = and(meta.hit, request.prio[0])
node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6))
node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7))
node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2)
node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4))
node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4)
node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5))
node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0))
node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7)
node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8)
node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0))
connect io.schedule.bits.a.bits.tag, request.tag
connect io.schedule.bits.a.bits.set, request.set
node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0))
connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1
node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6))
node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0))
node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7))
node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2)
node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0))
node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4)
connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5
connect io.schedule.bits.a.bits.source, UInt<1>(0h0)
node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1)
node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2)
connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3
node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag)
connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1
connect io.schedule.bits.b.bits.set, request.set
node _io_schedule_bits_b_bits_clients_T = not(excluded_client)
node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T)
connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1
node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6))
connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T
node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1))
node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1))
connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1
connect io.schedule.bits.c.bits.source, UInt<1>(0h0)
connect io.schedule.bits.c.bits.tag, meta.tag
connect io.schedule.bits.c.bits.set, request.set
connect io.schedule.bits.c.bits.way, meta.way
connect io.schedule.bits.c.bits.dirty, meta.dirty
connect io.schedule.bits.d.bits.set, request.set
connect io.schedule.bits.d.bits.put, request.put
connect io.schedule.bits.d.bits.offset, request.offset
connect io.schedule.bits.d.bits.tag, request.tag
connect io.schedule.bits.d.bits.source, request.source
connect io.schedule.bits.d.bits.size, request.size
connect io.schedule.bits.d.bits.param, request.param
connect io.schedule.bits.d.bits.opcode, request.opcode
connect io.schedule.bits.d.bits.control, request.control
connect io.schedule.bits.d.bits.prio, request.prio
node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0))
node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0))
node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param)
node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param)
node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param)
node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4)
node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param)
node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6)
node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8)
connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9
connect io.schedule.bits.d.bits.sink, UInt<1>(0h0)
connect io.schedule.bits.d.bits.way, meta.way
connect io.schedule.bits.d.bits.bad, bad_grant
connect io.schedule.bits.e.bits.sink, sink
connect io.schedule.bits.x.bits.fail, UInt<1>(0h0)
connect io.schedule.bits.dir.bits.set, request.set
connect io.schedule.bits.dir.bits.way, meta.way
node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0))
wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}
connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag
connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients
connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state
connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty
node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE)
connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1
node _evict_T = eq(meta.hit, UInt<1>(0h0))
wire evict : UInt
connect evict, UInt<1>(0h0)
node evict_c = orr(meta.clients)
node _evict_T_1 = eq(UInt<2>(0h1), meta.state)
when _evict_T_1 :
node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1))
connect evict, _evict_out_T
else :
node _evict_T_2 = eq(UInt<2>(0h2), meta.state)
when _evict_T_2 :
node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect evict, _evict_out_T_1
else :
node _evict_T_3 = eq(UInt<2>(0h3), meta.state)
when _evict_T_3 :
node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3)
connect evict, _evict_out_T_4
else :
node _evict_T_4 = eq(UInt<2>(0h0), meta.state)
when _evict_T_4 :
connect evict, UInt<4>(0h8)
node _evict_T_5 = eq(_evict_T, UInt<1>(0h0))
when _evict_T_5 :
connect evict, UInt<4>(0h8)
wire before : UInt
connect before, UInt<1>(0h0)
node before_c = orr(meta.clients)
node _before_T = eq(UInt<2>(0h1), meta.state)
when _before_T :
node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1))
connect before, _before_out_T
else :
node _before_T_1 = eq(UInt<2>(0h2), meta.state)
when _before_T_1 :
node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect before, _before_out_T_1
else :
node _before_T_2 = eq(UInt<2>(0h3), meta.state)
when _before_T_2 :
node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3)
connect before, _before_out_T_4
else :
node _before_T_3 = eq(UInt<2>(0h0), meta.state)
when _before_T_3 :
connect before, UInt<4>(0h8)
node _before_T_4 = eq(meta.hit, UInt<1>(0h0))
when _before_T_4 :
connect before, UInt<4>(0h8)
wire after : UInt
connect after, UInt<1>(0h0)
node after_c = orr(final_meta_writeback.clients)
node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state)
when _after_T :
node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1))
connect after, _after_out_T
else :
node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state)
when _after_T_1 :
node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect after, _after_out_T_1
else :
node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state)
when _after_T_2 :
node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3)
connect after, _after_out_T_4
else :
node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state)
when _after_T_3 :
connect after, UInt<4>(0h8)
node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0))
when _after_T_4 :
connect after, UInt<4>(0h8)
node _T_56 = eq(s_release, UInt<1>(0h0))
node _T_57 = and(_T_56, w_rprobeackfirst)
node _T_58 = and(_T_57, io.schedule.ready)
when _T_58 :
node _T_59 = eq(evict, UInt<1>(0h1))
node _T_60 = eq(_T_59, UInt<1>(0h0))
node _T_61 = asUInt(reset)
node _T_62 = eq(_T_61, UInt<1>(0h0))
when _T_62 :
node _T_63 = eq(_T_60, UInt<1>(0h0))
when _T_63 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8
assert(clock, _T_60, UInt<1>(0h1), "") : assert_8
node _T_64 = eq(before, UInt<1>(0h1))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(_T_65, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9
assert(clock, _T_65, UInt<1>(0h1), "") : assert_9
node _T_69 = eq(evict, UInt<1>(0h0))
node _T_70 = eq(_T_69, UInt<1>(0h0))
node _T_71 = asUInt(reset)
node _T_72 = eq(_T_71, UInt<1>(0h0))
when _T_72 :
node _T_73 = eq(_T_70, UInt<1>(0h0))
when _T_73 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10
assert(clock, _T_70, UInt<1>(0h1), "") : assert_10
node _T_74 = eq(before, UInt<1>(0h0))
node _T_75 = eq(_T_74, UInt<1>(0h0))
node _T_76 = asUInt(reset)
node _T_77 = eq(_T_76, UInt<1>(0h0))
when _T_77 :
node _T_78 = eq(_T_75, UInt<1>(0h0))
when _T_78 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11
assert(clock, _T_75, UInt<1>(0h1), "") : assert_11
node _T_79 = eq(evict, UInt<3>(0h7))
node _T_80 = eq(before, UInt<3>(0h7))
node _T_81 = eq(evict, UInt<3>(0h5))
node _T_82 = eq(before, UInt<3>(0h5))
node _T_83 = eq(evict, UInt<3>(0h4))
node _T_84 = eq(before, UInt<3>(0h4))
node _T_85 = eq(evict, UInt<3>(0h6))
node _T_86 = eq(before, UInt<3>(0h6))
node _T_87 = eq(evict, UInt<2>(0h3))
node _T_88 = eq(before, UInt<2>(0h3))
node _T_89 = eq(evict, UInt<2>(0h2))
node _T_90 = eq(before, UInt<2>(0h2))
node _T_91 = eq(s_writeback, UInt<1>(0h0))
node _T_92 = and(_T_91, no_wait)
node _T_93 = and(_T_92, io.schedule.ready)
when _T_93 :
node _T_94 = eq(before, UInt<4>(0h8))
node _T_95 = eq(after, UInt<1>(0h1))
node _T_96 = and(_T_94, _T_95)
node _T_97 = eq(_T_96, UInt<1>(0h0))
node _T_98 = asUInt(reset)
node _T_99 = eq(_T_98, UInt<1>(0h0))
when _T_99 :
node _T_100 = eq(_T_97, UInt<1>(0h0))
when _T_100 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12
assert(clock, _T_97, UInt<1>(0h1), "") : assert_12
node _T_101 = eq(before, UInt<4>(0h8))
node _T_102 = eq(after, UInt<1>(0h0))
node _T_103 = and(_T_101, _T_102)
node _T_104 = eq(_T_103, UInt<1>(0h0))
node _T_105 = asUInt(reset)
node _T_106 = eq(_T_105, UInt<1>(0h0))
when _T_106 :
node _T_107 = eq(_T_104, UInt<1>(0h0))
when _T_107 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13
assert(clock, _T_104, UInt<1>(0h1), "") : assert_13
node _T_108 = eq(before, UInt<4>(0h8))
node _T_109 = eq(after, UInt<3>(0h7))
node _T_110 = and(_T_108, _T_109)
node _T_111 = eq(before, UInt<4>(0h8))
node _T_112 = eq(after, UInt<3>(0h5))
node _T_113 = and(_T_111, _T_112)
node _T_114 = eq(_T_113, UInt<1>(0h0))
node _T_115 = asUInt(reset)
node _T_116 = eq(_T_115, UInt<1>(0h0))
when _T_116 :
node _T_117 = eq(_T_114, UInt<1>(0h0))
when _T_117 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14
assert(clock, _T_114, UInt<1>(0h1), "") : assert_14
node _T_118 = eq(before, UInt<4>(0h8))
node _T_119 = eq(after, UInt<3>(0h4))
node _T_120 = and(_T_118, _T_119)
node _T_121 = eq(_T_120, UInt<1>(0h0))
node _T_122 = asUInt(reset)
node _T_123 = eq(_T_122, UInt<1>(0h0))
when _T_123 :
node _T_124 = eq(_T_121, UInt<1>(0h0))
when _T_124 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15
assert(clock, _T_121, UInt<1>(0h1), "") : assert_15
node _T_125 = eq(before, UInt<4>(0h8))
node _T_126 = eq(after, UInt<3>(0h6))
node _T_127 = and(_T_125, _T_126)
node _T_128 = eq(before, UInt<4>(0h8))
node _T_129 = eq(after, UInt<2>(0h3))
node _T_130 = and(_T_128, _T_129)
node _T_131 = eq(before, UInt<4>(0h8))
node _T_132 = eq(after, UInt<2>(0h2))
node _T_133 = and(_T_131, _T_132)
node _T_134 = eq(_T_133, UInt<1>(0h0))
node _T_135 = asUInt(reset)
node _T_136 = eq(_T_135, UInt<1>(0h0))
when _T_136 :
node _T_137 = eq(_T_134, UInt<1>(0h0))
when _T_137 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16
assert(clock, _T_134, UInt<1>(0h1), "") : assert_16
node _T_138 = eq(before, UInt<1>(0h1))
node _T_139 = eq(after, UInt<4>(0h8))
node _T_140 = and(_T_138, _T_139)
node _T_141 = eq(_T_140, UInt<1>(0h0))
node _T_142 = asUInt(reset)
node _T_143 = eq(_T_142, UInt<1>(0h0))
when _T_143 :
node _T_144 = eq(_T_141, UInt<1>(0h0))
when _T_144 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17
assert(clock, _T_141, UInt<1>(0h1), "") : assert_17
node _T_145 = eq(before, UInt<1>(0h1))
node _T_146 = eq(after, UInt<1>(0h0))
node _T_147 = and(_T_145, _T_146)
node _T_148 = eq(_T_147, UInt<1>(0h0))
node _T_149 = asUInt(reset)
node _T_150 = eq(_T_149, UInt<1>(0h0))
when _T_150 :
node _T_151 = eq(_T_148, UInt<1>(0h0))
when _T_151 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18
assert(clock, _T_148, UInt<1>(0h1), "") : assert_18
node _T_152 = eq(before, UInt<1>(0h1))
node _T_153 = eq(after, UInt<3>(0h7))
node _T_154 = and(_T_152, _T_153)
node _T_155 = eq(_T_154, UInt<1>(0h0))
node _T_156 = asUInt(reset)
node _T_157 = eq(_T_156, UInt<1>(0h0))
when _T_157 :
node _T_158 = eq(_T_155, UInt<1>(0h0))
when _T_158 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19
assert(clock, _T_155, UInt<1>(0h1), "") : assert_19
node _T_159 = eq(before, UInt<1>(0h1))
node _T_160 = eq(after, UInt<3>(0h5))
node _T_161 = and(_T_159, _T_160)
node _T_162 = eq(_T_161, UInt<1>(0h0))
node _T_163 = asUInt(reset)
node _T_164 = eq(_T_163, UInt<1>(0h0))
when _T_164 :
node _T_165 = eq(_T_162, UInt<1>(0h0))
when _T_165 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20
assert(clock, _T_162, UInt<1>(0h1), "") : assert_20
node _T_166 = eq(before, UInt<1>(0h1))
node _T_167 = eq(after, UInt<3>(0h4))
node _T_168 = and(_T_166, _T_167)
node _T_169 = eq(_T_168, UInt<1>(0h0))
node _T_170 = asUInt(reset)
node _T_171 = eq(_T_170, UInt<1>(0h0))
when _T_171 :
node _T_172 = eq(_T_169, UInt<1>(0h0))
when _T_172 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21
assert(clock, _T_169, UInt<1>(0h1), "") : assert_21
node _T_173 = eq(before, UInt<1>(0h1))
node _T_174 = eq(after, UInt<3>(0h6))
node _T_175 = and(_T_173, _T_174)
node _T_176 = eq(_T_175, UInt<1>(0h0))
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_T_176, UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22
assert(clock, _T_176, UInt<1>(0h1), "") : assert_22
node _T_180 = eq(before, UInt<1>(0h1))
node _T_181 = eq(after, UInt<2>(0h3))
node _T_182 = and(_T_180, _T_181)
node _T_183 = eq(_T_182, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(before, UInt<1>(0h1))
node _T_188 = eq(after, UInt<2>(0h2))
node _T_189 = and(_T_187, _T_188)
node _T_190 = eq(_T_189, UInt<1>(0h0))
node _T_191 = asUInt(reset)
node _T_192 = eq(_T_191, UInt<1>(0h0))
when _T_192 :
node _T_193 = eq(_T_190, UInt<1>(0h0))
when _T_193 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24
assert(clock, _T_190, UInt<1>(0h1), "") : assert_24
node _T_194 = eq(before, UInt<1>(0h0))
node _T_195 = eq(after, UInt<4>(0h8))
node _T_196 = and(_T_194, _T_195)
node _T_197 = eq(_T_196, UInt<1>(0h0))
node _T_198 = asUInt(reset)
node _T_199 = eq(_T_198, UInt<1>(0h0))
when _T_199 :
node _T_200 = eq(_T_197, UInt<1>(0h0))
when _T_200 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25
assert(clock, _T_197, UInt<1>(0h1), "") : assert_25
node _T_201 = eq(before, UInt<1>(0h0))
node _T_202 = eq(after, UInt<1>(0h1))
node _T_203 = and(_T_201, _T_202)
node _T_204 = eq(_T_203, UInt<1>(0h0))
node _T_205 = asUInt(reset)
node _T_206 = eq(_T_205, UInt<1>(0h0))
when _T_206 :
node _T_207 = eq(_T_204, UInt<1>(0h0))
when _T_207 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26
assert(clock, _T_204, UInt<1>(0h1), "") : assert_26
node _T_208 = eq(before, UInt<1>(0h0))
node _T_209 = eq(after, UInt<3>(0h7))
node _T_210 = and(_T_208, _T_209)
node _T_211 = eq(_T_210, UInt<1>(0h0))
node _T_212 = asUInt(reset)
node _T_213 = eq(_T_212, UInt<1>(0h0))
when _T_213 :
node _T_214 = eq(_T_211, UInt<1>(0h0))
when _T_214 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27
assert(clock, _T_211, UInt<1>(0h1), "") : assert_27
node _T_215 = eq(before, UInt<1>(0h0))
node _T_216 = eq(after, UInt<3>(0h5))
node _T_217 = and(_T_215, _T_216)
node _T_218 = eq(_T_217, UInt<1>(0h0))
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28
assert(clock, _T_218, UInt<1>(0h1), "") : assert_28
node _T_222 = eq(before, UInt<1>(0h0))
node _T_223 = eq(after, UInt<3>(0h6))
node _T_224 = and(_T_222, _T_223)
node _T_225 = eq(_T_224, UInt<1>(0h0))
node _T_226 = asUInt(reset)
node _T_227 = eq(_T_226, UInt<1>(0h0))
when _T_227 :
node _T_228 = eq(_T_225, UInt<1>(0h0))
when _T_228 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29
assert(clock, _T_225, UInt<1>(0h1), "") : assert_29
node _T_229 = eq(before, UInt<1>(0h0))
node _T_230 = eq(after, UInt<3>(0h4))
node _T_231 = and(_T_229, _T_230)
node _T_232 = eq(_T_231, UInt<1>(0h0))
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30
assert(clock, _T_232, UInt<1>(0h1), "") : assert_30
node _T_236 = eq(before, UInt<1>(0h0))
node _T_237 = eq(after, UInt<2>(0h3))
node _T_238 = and(_T_236, _T_237)
node _T_239 = eq(_T_238, UInt<1>(0h0))
node _T_240 = asUInt(reset)
node _T_241 = eq(_T_240, UInt<1>(0h0))
when _T_241 :
node _T_242 = eq(_T_239, UInt<1>(0h0))
when _T_242 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31
assert(clock, _T_239, UInt<1>(0h1), "") : assert_31
node _T_243 = eq(before, UInt<1>(0h0))
node _T_244 = eq(after, UInt<2>(0h2))
node _T_245 = and(_T_243, _T_244)
node _T_246 = eq(_T_245, UInt<1>(0h0))
node _T_247 = asUInt(reset)
node _T_248 = eq(_T_247, UInt<1>(0h0))
when _T_248 :
node _T_249 = eq(_T_246, UInt<1>(0h0))
when _T_249 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32
assert(clock, _T_246, UInt<1>(0h1), "") : assert_32
node _T_250 = eq(before, UInt<3>(0h7))
node _T_251 = eq(after, UInt<4>(0h8))
node _T_252 = and(_T_250, _T_251)
node _T_253 = eq(_T_252, UInt<1>(0h0))
node _T_254 = asUInt(reset)
node _T_255 = eq(_T_254, UInt<1>(0h0))
when _T_255 :
node _T_256 = eq(_T_253, UInt<1>(0h0))
when _T_256 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33
assert(clock, _T_253, UInt<1>(0h1), "") : assert_33
node _T_257 = eq(before, UInt<3>(0h7))
node _T_258 = eq(after, UInt<1>(0h1))
node _T_259 = and(_T_257, _T_258)
node _T_260 = eq(_T_259, UInt<1>(0h0))
node _T_261 = asUInt(reset)
node _T_262 = eq(_T_261, UInt<1>(0h0))
when _T_262 :
node _T_263 = eq(_T_260, UInt<1>(0h0))
when _T_263 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34
assert(clock, _T_260, UInt<1>(0h1), "") : assert_34
node _T_264 = eq(before, UInt<3>(0h7))
node _T_265 = eq(after, UInt<1>(0h0))
node _T_266 = and(_T_264, _T_265)
node _T_267 = eq(_T_266, UInt<1>(0h0))
node _T_268 = asUInt(reset)
node _T_269 = eq(_T_268, UInt<1>(0h0))
when _T_269 :
node _T_270 = eq(_T_267, UInt<1>(0h0))
when _T_270 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35
assert(clock, _T_267, UInt<1>(0h1), "") : assert_35
node _T_271 = eq(before, UInt<3>(0h7))
node _T_272 = eq(after, UInt<3>(0h5))
node _T_273 = and(_T_271, _T_272)
node _T_274 = eq(_T_273, UInt<1>(0h0))
node _T_275 = asUInt(reset)
node _T_276 = eq(_T_275, UInt<1>(0h0))
when _T_276 :
node _T_277 = eq(_T_274, UInt<1>(0h0))
when _T_277 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36
assert(clock, _T_274, UInt<1>(0h1), "") : assert_36
node _T_278 = eq(before, UInt<3>(0h7))
node _T_279 = eq(after, UInt<3>(0h6))
node _T_280 = and(_T_278, _T_279)
node _T_281 = eq(before, UInt<3>(0h7))
node _T_282 = eq(after, UInt<3>(0h4))
node _T_283 = and(_T_281, _T_282)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = asUInt(reset)
node _T_286 = eq(_T_285, UInt<1>(0h0))
when _T_286 :
node _T_287 = eq(_T_284, UInt<1>(0h0))
when _T_287 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37
assert(clock, _T_284, UInt<1>(0h1), "") : assert_37
node _T_288 = eq(before, UInt<3>(0h7))
node _T_289 = eq(after, UInt<2>(0h3))
node _T_290 = and(_T_288, _T_289)
node _T_291 = eq(before, UInt<3>(0h7))
node _T_292 = eq(after, UInt<2>(0h2))
node _T_293 = and(_T_291, _T_292)
node _T_294 = eq(_T_293, UInt<1>(0h0))
node _T_295 = asUInt(reset)
node _T_296 = eq(_T_295, UInt<1>(0h0))
when _T_296 :
node _T_297 = eq(_T_294, UInt<1>(0h0))
when _T_297 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38
assert(clock, _T_294, UInt<1>(0h1), "") : assert_38
node _T_298 = eq(before, UInt<3>(0h5))
node _T_299 = eq(after, UInt<4>(0h8))
node _T_300 = and(_T_298, _T_299)
node _T_301 = eq(_T_300, UInt<1>(0h0))
node _T_302 = asUInt(reset)
node _T_303 = eq(_T_302, UInt<1>(0h0))
when _T_303 :
node _T_304 = eq(_T_301, UInt<1>(0h0))
when _T_304 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39
assert(clock, _T_301, UInt<1>(0h1), "") : assert_39
node _T_305 = eq(before, UInt<3>(0h5))
node _T_306 = eq(after, UInt<1>(0h1))
node _T_307 = and(_T_305, _T_306)
node _T_308 = eq(_T_307, UInt<1>(0h0))
node _T_309 = asUInt(reset)
node _T_310 = eq(_T_309, UInt<1>(0h0))
when _T_310 :
node _T_311 = eq(_T_308, UInt<1>(0h0))
when _T_311 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40
assert(clock, _T_308, UInt<1>(0h1), "") : assert_40
node _T_312 = eq(before, UInt<3>(0h5))
node _T_313 = eq(after, UInt<1>(0h0))
node _T_314 = and(_T_312, _T_313)
node _T_315 = eq(_T_314, UInt<1>(0h0))
node _T_316 = asUInt(reset)
node _T_317 = eq(_T_316, UInt<1>(0h0))
when _T_317 :
node _T_318 = eq(_T_315, UInt<1>(0h0))
when _T_318 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41
assert(clock, _T_315, UInt<1>(0h1), "") : assert_41
node _T_319 = eq(before, UInt<3>(0h5))
node _T_320 = eq(after, UInt<3>(0h7))
node _T_321 = and(_T_319, _T_320)
node _T_322 = eq(before, UInt<3>(0h5))
node _T_323 = eq(after, UInt<3>(0h6))
node _T_324 = and(_T_322, _T_323)
node _T_325 = eq(before, UInt<3>(0h5))
node _T_326 = eq(after, UInt<3>(0h4))
node _T_327 = and(_T_325, _T_326)
node _T_328 = eq(_T_327, UInt<1>(0h0))
node _T_329 = asUInt(reset)
node _T_330 = eq(_T_329, UInt<1>(0h0))
when _T_330 :
node _T_331 = eq(_T_328, UInt<1>(0h0))
when _T_331 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42
assert(clock, _T_328, UInt<1>(0h1), "") : assert_42
node _T_332 = eq(before, UInt<3>(0h5))
node _T_333 = eq(after, UInt<2>(0h3))
node _T_334 = and(_T_332, _T_333)
node _T_335 = eq(before, UInt<3>(0h5))
node _T_336 = eq(after, UInt<2>(0h2))
node _T_337 = and(_T_335, _T_336)
node _T_338 = eq(_T_337, UInt<1>(0h0))
node _T_339 = asUInt(reset)
node _T_340 = eq(_T_339, UInt<1>(0h0))
when _T_340 :
node _T_341 = eq(_T_338, UInt<1>(0h0))
when _T_341 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43
assert(clock, _T_338, UInt<1>(0h1), "") : assert_43
node _T_342 = eq(before, UInt<3>(0h6))
node _T_343 = eq(after, UInt<4>(0h8))
node _T_344 = and(_T_342, _T_343)
node _T_345 = eq(_T_344, UInt<1>(0h0))
node _T_346 = asUInt(reset)
node _T_347 = eq(_T_346, UInt<1>(0h0))
when _T_347 :
node _T_348 = eq(_T_345, UInt<1>(0h0))
when _T_348 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44
assert(clock, _T_345, UInt<1>(0h1), "") : assert_44
node _T_349 = eq(before, UInt<3>(0h6))
node _T_350 = eq(after, UInt<1>(0h1))
node _T_351 = and(_T_349, _T_350)
node _T_352 = eq(_T_351, UInt<1>(0h0))
node _T_353 = asUInt(reset)
node _T_354 = eq(_T_353, UInt<1>(0h0))
when _T_354 :
node _T_355 = eq(_T_352, UInt<1>(0h0))
when _T_355 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45
assert(clock, _T_352, UInt<1>(0h1), "") : assert_45
node _T_356 = eq(before, UInt<3>(0h6))
node _T_357 = eq(after, UInt<1>(0h0))
node _T_358 = and(_T_356, _T_357)
node _T_359 = eq(_T_358, UInt<1>(0h0))
node _T_360 = asUInt(reset)
node _T_361 = eq(_T_360, UInt<1>(0h0))
when _T_361 :
node _T_362 = eq(_T_359, UInt<1>(0h0))
when _T_362 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46
assert(clock, _T_359, UInt<1>(0h1), "") : assert_46
node _T_363 = eq(before, UInt<3>(0h6))
node _T_364 = eq(after, UInt<3>(0h7))
node _T_365 = and(_T_363, _T_364)
node _T_366 = eq(_T_365, UInt<1>(0h0))
node _T_367 = asUInt(reset)
node _T_368 = eq(_T_367, UInt<1>(0h0))
when _T_368 :
node _T_369 = eq(_T_366, UInt<1>(0h0))
when _T_369 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47
assert(clock, _T_366, UInt<1>(0h1), "") : assert_47
node _T_370 = eq(before, UInt<3>(0h6))
node _T_371 = eq(after, UInt<3>(0h5))
node _T_372 = and(_T_370, _T_371)
node _T_373 = eq(_T_372, UInt<1>(0h0))
node _T_374 = asUInt(reset)
node _T_375 = eq(_T_374, UInt<1>(0h0))
when _T_375 :
node _T_376 = eq(_T_373, UInt<1>(0h0))
when _T_376 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48
assert(clock, _T_373, UInt<1>(0h1), "") : assert_48
node _T_377 = eq(before, UInt<3>(0h6))
node _T_378 = eq(after, UInt<3>(0h4))
node _T_379 = and(_T_377, _T_378)
node _T_380 = eq(_T_379, UInt<1>(0h0))
node _T_381 = asUInt(reset)
node _T_382 = eq(_T_381, UInt<1>(0h0))
when _T_382 :
node _T_383 = eq(_T_380, UInt<1>(0h0))
when _T_383 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49
assert(clock, _T_380, UInt<1>(0h1), "") : assert_49
node _T_384 = eq(before, UInt<3>(0h6))
node _T_385 = eq(after, UInt<2>(0h3))
node _T_386 = and(_T_384, _T_385)
node _T_387 = eq(_T_386, UInt<1>(0h0))
node _T_388 = asUInt(reset)
node _T_389 = eq(_T_388, UInt<1>(0h0))
when _T_389 :
node _T_390 = eq(_T_387, UInt<1>(0h0))
when _T_390 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50
assert(clock, _T_387, UInt<1>(0h1), "") : assert_50
node _T_391 = eq(before, UInt<3>(0h6))
node _T_392 = eq(after, UInt<2>(0h2))
node _T_393 = and(_T_391, _T_392)
node _T_394 = eq(before, UInt<3>(0h4))
node _T_395 = eq(after, UInt<4>(0h8))
node _T_396 = and(_T_394, _T_395)
node _T_397 = eq(_T_396, UInt<1>(0h0))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51
assert(clock, _T_397, UInt<1>(0h1), "") : assert_51
node _T_401 = eq(before, UInt<3>(0h4))
node _T_402 = eq(after, UInt<1>(0h1))
node _T_403 = and(_T_401, _T_402)
node _T_404 = eq(_T_403, UInt<1>(0h0))
node _T_405 = asUInt(reset)
node _T_406 = eq(_T_405, UInt<1>(0h0))
when _T_406 :
node _T_407 = eq(_T_404, UInt<1>(0h0))
when _T_407 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52
assert(clock, _T_404, UInt<1>(0h1), "") : assert_52
node _T_408 = eq(before, UInt<3>(0h4))
node _T_409 = eq(after, UInt<1>(0h0))
node _T_410 = and(_T_408, _T_409)
node _T_411 = eq(_T_410, UInt<1>(0h0))
node _T_412 = asUInt(reset)
node _T_413 = eq(_T_412, UInt<1>(0h0))
when _T_413 :
node _T_414 = eq(_T_411, UInt<1>(0h0))
when _T_414 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53
assert(clock, _T_411, UInt<1>(0h1), "") : assert_53
node _T_415 = eq(before, UInt<3>(0h4))
node _T_416 = eq(after, UInt<3>(0h7))
node _T_417 = and(_T_415, _T_416)
node _T_418 = eq(_T_417, UInt<1>(0h0))
node _T_419 = asUInt(reset)
node _T_420 = eq(_T_419, UInt<1>(0h0))
when _T_420 :
node _T_421 = eq(_T_418, UInt<1>(0h0))
when _T_421 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54
assert(clock, _T_418, UInt<1>(0h1), "") : assert_54
node _T_422 = eq(before, UInt<3>(0h4))
node _T_423 = eq(after, UInt<3>(0h5))
node _T_424 = and(_T_422, _T_423)
node _T_425 = eq(_T_424, UInt<1>(0h0))
node _T_426 = asUInt(reset)
node _T_427 = eq(_T_426, UInt<1>(0h0))
when _T_427 :
node _T_428 = eq(_T_425, UInt<1>(0h0))
when _T_428 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55
assert(clock, _T_425, UInt<1>(0h1), "") : assert_55
node _T_429 = eq(before, UInt<3>(0h4))
node _T_430 = eq(after, UInt<3>(0h6))
node _T_431 = and(_T_429, _T_430)
node _T_432 = eq(before, UInt<3>(0h4))
node _T_433 = eq(after, UInt<2>(0h3))
node _T_434 = and(_T_432, _T_433)
node _T_435 = eq(_T_434, UInt<1>(0h0))
node _T_436 = asUInt(reset)
node _T_437 = eq(_T_436, UInt<1>(0h0))
when _T_437 :
node _T_438 = eq(_T_435, UInt<1>(0h0))
when _T_438 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56
assert(clock, _T_435, UInt<1>(0h1), "") : assert_56
node _T_439 = eq(before, UInt<3>(0h4))
node _T_440 = eq(after, UInt<2>(0h2))
node _T_441 = and(_T_439, _T_440)
node _T_442 = eq(before, UInt<2>(0h3))
node _T_443 = eq(after, UInt<4>(0h8))
node _T_444 = and(_T_442, _T_443)
node _T_445 = eq(_T_444, UInt<1>(0h0))
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57
assert(clock, _T_445, UInt<1>(0h1), "") : assert_57
node _T_449 = eq(before, UInt<2>(0h3))
node _T_450 = eq(after, UInt<1>(0h1))
node _T_451 = and(_T_449, _T_450)
node _T_452 = eq(_T_451, UInt<1>(0h0))
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(_T_452, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58
assert(clock, _T_452, UInt<1>(0h1), "") : assert_58
node _T_456 = eq(before, UInt<2>(0h3))
node _T_457 = eq(after, UInt<1>(0h0))
node _T_458 = and(_T_456, _T_457)
node _T_459 = eq(_T_458, UInt<1>(0h0))
node _T_460 = asUInt(reset)
node _T_461 = eq(_T_460, UInt<1>(0h0))
when _T_461 :
node _T_462 = eq(_T_459, UInt<1>(0h0))
when _T_462 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59
assert(clock, _T_459, UInt<1>(0h1), "") : assert_59
node _T_463 = eq(before, UInt<2>(0h3))
node _T_464 = eq(after, UInt<3>(0h7))
node _T_465 = and(_T_463, _T_464)
node _T_466 = eq(before, UInt<2>(0h3))
node _T_467 = eq(after, UInt<3>(0h5))
node _T_468 = and(_T_466, _T_467)
node _T_469 = eq(before, UInt<2>(0h3))
node _T_470 = eq(after, UInt<3>(0h6))
node _T_471 = and(_T_469, _T_470)
node _T_472 = eq(before, UInt<2>(0h3))
node _T_473 = eq(after, UInt<3>(0h4))
node _T_474 = and(_T_472, _T_473)
node _T_475 = eq(before, UInt<2>(0h3))
node _T_476 = eq(after, UInt<2>(0h2))
node _T_477 = and(_T_475, _T_476)
node _T_478 = eq(before, UInt<2>(0h2))
node _T_479 = eq(after, UInt<4>(0h8))
node _T_480 = and(_T_478, _T_479)
node _T_481 = eq(_T_480, UInt<1>(0h0))
node _T_482 = asUInt(reset)
node _T_483 = eq(_T_482, UInt<1>(0h0))
when _T_483 :
node _T_484 = eq(_T_481, UInt<1>(0h0))
when _T_484 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60
assert(clock, _T_481, UInt<1>(0h1), "") : assert_60
node _T_485 = eq(before, UInt<2>(0h2))
node _T_486 = eq(after, UInt<1>(0h1))
node _T_487 = and(_T_485, _T_486)
node _T_488 = eq(_T_487, UInt<1>(0h0))
node _T_489 = asUInt(reset)
node _T_490 = eq(_T_489, UInt<1>(0h0))
when _T_490 :
node _T_491 = eq(_T_488, UInt<1>(0h0))
when _T_491 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61
assert(clock, _T_488, UInt<1>(0h1), "") : assert_61
node _T_492 = eq(before, UInt<2>(0h2))
node _T_493 = eq(after, UInt<1>(0h0))
node _T_494 = and(_T_492, _T_493)
node _T_495 = eq(_T_494, UInt<1>(0h0))
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_T_495, UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62
assert(clock, _T_495, UInt<1>(0h1), "") : assert_62
node _T_499 = eq(before, UInt<2>(0h2))
node _T_500 = eq(after, UInt<3>(0h7))
node _T_501 = and(_T_499, _T_500)
node _T_502 = eq(_T_501, UInt<1>(0h0))
node _T_503 = asUInt(reset)
node _T_504 = eq(_T_503, UInt<1>(0h0))
when _T_504 :
node _T_505 = eq(_T_502, UInt<1>(0h0))
when _T_505 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63
assert(clock, _T_502, UInt<1>(0h1), "") : assert_63
node _T_506 = eq(before, UInt<2>(0h2))
node _T_507 = eq(after, UInt<3>(0h5))
node _T_508 = and(_T_506, _T_507)
node _T_509 = eq(_T_508, UInt<1>(0h0))
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64
assert(clock, _T_509, UInt<1>(0h1), "") : assert_64
node _T_513 = eq(before, UInt<2>(0h2))
node _T_514 = eq(after, UInt<3>(0h6))
node _T_515 = and(_T_513, _T_514)
node _T_516 = eq(before, UInt<2>(0h2))
node _T_517 = eq(after, UInt<3>(0h4))
node _T_518 = and(_T_516, _T_517)
node _T_519 = eq(before, UInt<2>(0h2))
node _T_520 = eq(after, UInt<2>(0h3))
node _T_521 = and(_T_519, _T_520)
node _T_522 = eq(_T_521, UInt<1>(0h0))
node _T_523 = asUInt(reset)
node _T_524 = eq(_T_523, UInt<1>(0h0))
when _T_524 :
node _T_525 = eq(_T_522, UInt<1>(0h0))
when _T_525 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65
assert(clock, _T_522, UInt<1>(0h1), "") : assert_65
node probe_bit = eq(io.sinkc.bits.source, UInt<6>(0h28))
node _last_probe_T = or(probes_done, probe_bit)
node _last_probe_T_1 = not(excluded_client)
node _last_probe_T_2 = and(meta.clients, _last_probe_T_1)
node last_probe = eq(_last_probe_T, _last_probe_T_2)
node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1))
node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2))
node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1)
node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5))
node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3)
when io.sinkc.valid :
node _T_526 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1))
node _T_527 = and(probe_toN, _T_526)
node _T_528 = eq(probe_toN, UInt<1>(0h0))
node _T_529 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1))
node _T_530 = and(_T_528, _T_529)
node _probes_done_T = or(probes_done, probe_bit)
connect probes_done, _probes_done_T
node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0))
node _probes_toN_T_1 = or(probes_toN, _probes_toN_T)
connect probes_toN, _probes_toN_T_1
node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3))
node _probes_noT_T_1 = or(probes_noT, _probes_noT_T)
connect probes_noT, _probes_noT_T_1
node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe)
connect w_rprobeackfirst, _w_rprobeackfirst_T
node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last)
node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T)
connect w_rprobeacklast, _w_rprobeacklast_T_1
node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe)
connect w_pprobeackfirst, _w_pprobeackfirst_T
node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last)
node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T)
connect w_pprobeacklast, _w_pprobeacklast_T_1
node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0))
node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T)
node set_pprobeack = and(last_probe, _set_pprobeack_T_1)
node _w_pprobeack_T = or(w_pprobeack, set_pprobeack)
connect w_pprobeack, _w_pprobeack_T
node _T_531 = eq(set_pprobeack, UInt<1>(0h0))
node _T_532 = and(_T_531, w_rprobeackfirst)
node _T_533 = and(set_pprobeack, w_rprobeackfirst)
node _T_534 = neq(meta.state, UInt<2>(0h0))
node _T_535 = eq(io.sinkc.bits.tag, meta.tag)
node _T_536 = and(_T_534, _T_535)
node _T_537 = and(_T_536, io.sinkc.bits.data)
when _T_537 :
connect meta.dirty, UInt<1>(0h1)
when io.sinkd.valid :
node _T_538 = eq(io.sinkd.bits.opcode, UInt<3>(0h4))
node _T_539 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_540 = or(_T_538, _T_539)
when _T_540 :
connect sink, io.sinkd.bits.sink
connect w_grantfirst, UInt<1>(0h1)
connect w_grantlast, io.sinkd.bits.last
connect bad_grant, io.sinkd.bits.denied
node _w_grant_T = eq(request.offset, UInt<1>(0h0))
node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last)
connect w_grant, _w_grant_T_1
node _T_541 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_542 = eq(request.offset, UInt<1>(0h0))
node _T_543 = and(_T_541, _T_542)
node _T_544 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_545 = neq(request.offset, UInt<1>(0h0))
node _T_546 = and(_T_544, _T_545)
node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0))
connect gotT, _gotT_T
else :
node _T_547 = eq(io.sinkd.bits.opcode, UInt<3>(0h6))
when _T_547 :
connect w_releaseack, UInt<1>(0h1)
when io.sinke.valid :
connect w_grantack, UInt<1>(0h1)
wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>}
connect allocate_as_full.set, io.allocate.bits.set
connect allocate_as_full.put, io.allocate.bits.put
connect allocate_as_full.offset, io.allocate.bits.offset
connect allocate_as_full.tag, io.allocate.bits.tag
connect allocate_as_full.source, io.allocate.bits.source
connect allocate_as_full.size, io.allocate.bits.size
connect allocate_as_full.param, io.allocate.bits.param
connect allocate_as_full.opcode, io.allocate.bits.opcode
connect allocate_as_full.control, io.allocate.bits.control
connect allocate_as_full.prio, io.allocate.bits.prio
node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat)
node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits)
node new_request = mux(io.allocate.valid, allocate_as_full, request)
node _new_needT_T = bits(new_request.opcode, 2, 2)
node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0))
node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5))
node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1))
node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3)
node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4)
node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6))
node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7))
node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7)
node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0))
node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9)
node new_needT = or(_new_needT_T_5, _new_needT_T_10)
node new_clientBit = eq(new_request.source, UInt<6>(0h28))
node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6))
node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7))
node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1)
node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4))
node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3)
node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5))
node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0))
node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6)
node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0))
wire prior : UInt
connect prior, UInt<1>(0h0)
node prior_c = orr(final_meta_writeback.clients)
node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state)
when _prior_T :
node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1))
connect prior, _prior_out_T
else :
node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state)
when _prior_T_1 :
node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect prior, _prior_out_T_1
else :
node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state)
when _prior_T_2 :
node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3)
connect prior, _prior_out_T_4
else :
node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state)
when _prior_T_3 :
connect prior, UInt<4>(0h8)
node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0))
when _prior_T_4 :
connect prior, UInt<4>(0h8)
node _T_548 = and(io.allocate.valid, io.allocate.bits.repeat)
when _T_548 :
node _T_549 = eq(prior, UInt<4>(0h8))
node _T_550 = eq(prior, UInt<1>(0h1))
node _T_551 = eq(_T_550, UInt<1>(0h0))
node _T_552 = asUInt(reset)
node _T_553 = eq(_T_552, UInt<1>(0h0))
when _T_553 :
node _T_554 = eq(_T_551, UInt<1>(0h0))
when _T_554 :
printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_66
assert(clock, _T_551, UInt<1>(0h1), "") : assert_66
node _T_555 = eq(prior, UInt<1>(0h0))
node _T_556 = eq(_T_555, UInt<1>(0h0))
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_67
assert(clock, _T_556, UInt<1>(0h1), "") : assert_67
node _T_560 = eq(prior, UInt<3>(0h7))
node _T_561 = eq(prior, UInt<3>(0h5))
node _T_562 = eq(prior, UInt<3>(0h4))
node _T_563 = eq(prior, UInt<3>(0h6))
node _T_564 = eq(prior, UInt<2>(0h3))
node _T_565 = eq(prior, UInt<2>(0h2))
when io.allocate.valid :
node _T_566 = eq(request_valid, UInt<1>(0h0))
node _T_567 = and(io.schedule.ready, io.schedule.valid)
node _T_568 = and(no_wait, _T_567)
node _T_569 = or(_T_566, _T_568)
node _T_570 = asUInt(reset)
node _T_571 = eq(_T_570, UInt<1>(0h0))
when _T_571 :
node _T_572 = eq(_T_569, UInt<1>(0h0))
when _T_572 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid || (no_wait && io.schedule.fire))\n") : printf_68
assert(clock, _T_569, UInt<1>(0h1), "") : assert_68
connect request_valid, UInt<1>(0h1)
connect request.set, io.allocate.bits.set
connect request.put, io.allocate.bits.put
connect request.offset, io.allocate.bits.offset
connect request.tag, io.allocate.bits.tag
connect request.source, io.allocate.bits.source
connect request.size, io.allocate.bits.size
connect request.param, io.allocate.bits.param
connect request.opcode, io.allocate.bits.opcode
connect request.control, io.allocate.bits.control
connect request.prio, io.allocate.bits.prio
node _T_573 = and(io.allocate.valid, io.allocate.bits.repeat)
node _T_574 = or(io.directory.valid, _T_573)
when _T_574 :
connect meta_valid, UInt<1>(0h1)
connect meta, new_meta
connect probes_done, UInt<1>(0h0)
connect probes_toN, UInt<1>(0h0)
connect probes_noT, UInt<1>(0h0)
connect gotT, UInt<1>(0h0)
connect bad_grant, UInt<1>(0h0)
connect s_rprobe, UInt<1>(0h1)
connect w_rprobeackfirst, UInt<1>(0h1)
connect w_rprobeacklast, UInt<1>(0h1)
connect s_release, UInt<1>(0h1)
connect w_releaseack, UInt<1>(0h1)
connect s_pprobe, UInt<1>(0h1)
connect s_acquire, UInt<1>(0h1)
connect s_flush, UInt<1>(0h1)
connect w_grantfirst, UInt<1>(0h1)
connect w_grantlast, UInt<1>(0h1)
connect w_grant, UInt<1>(0h1)
connect w_pprobeackfirst, UInt<1>(0h1)
connect w_pprobeacklast, UInt<1>(0h1)
connect w_pprobeack, UInt<1>(0h1)
connect s_probeack, UInt<1>(0h1)
connect s_grantack, UInt<1>(0h1)
connect s_execute, UInt<1>(0h1)
connect w_grantack, UInt<1>(0h1)
connect s_writeback, UInt<1>(0h1)
node _T_575 = and(new_request.prio[2], UInt<1>(0h1))
when _T_575 :
connect s_execute, UInt<1>(0h0)
node _T_576 = bits(new_request.opcode, 0, 0)
node _T_577 = eq(new_meta.dirty, UInt<1>(0h0))
node _T_578 = and(_T_576, _T_577)
when _T_578 :
connect s_writeback, UInt<1>(0h0)
node _T_579 = eq(new_request.param, UInt<3>(0h0))
node _T_580 = eq(new_request.param, UInt<3>(0h4))
node _T_581 = or(_T_579, _T_580)
node _T_582 = eq(new_meta.state, UInt<2>(0h2))
node _T_583 = and(_T_581, _T_582)
when _T_583 :
connect s_writeback, UInt<1>(0h0)
node _T_584 = eq(new_request.param, UInt<3>(0h1))
node _T_585 = eq(new_request.param, UInt<3>(0h2))
node _T_586 = or(_T_584, _T_585)
node _T_587 = eq(new_request.param, UInt<3>(0h5))
node _T_588 = or(_T_586, _T_587)
node _T_589 = and(new_meta.clients, new_clientBit)
node _T_590 = neq(_T_589, UInt<1>(0h0))
node _T_591 = and(_T_588, _T_590)
when _T_591 :
connect s_writeback, UInt<1>(0h0)
node _T_592 = asUInt(reset)
node _T_593 = eq(_T_592, UInt<1>(0h0))
when _T_593 :
node _T_594 = eq(new_meta.hit, UInt<1>(0h0))
when _T_594 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_69
assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_69
else :
node _T_595 = and(new_request.control, UInt<1>(0h1))
when _T_595 :
connect s_flush, UInt<1>(0h0)
when new_meta.hit :
connect s_release, UInt<1>(0h0)
connect w_releaseack, UInt<1>(0h0)
node _T_596 = neq(new_meta.clients, UInt<1>(0h0))
node _T_597 = and(UInt<1>(0h1), _T_596)
when _T_597 :
connect s_rprobe, UInt<1>(0h0)
connect w_rprobeackfirst, UInt<1>(0h0)
connect w_rprobeacklast, UInt<1>(0h0)
else :
connect s_execute, UInt<1>(0h0)
node _T_598 = eq(new_meta.hit, UInt<1>(0h0))
node _T_599 = neq(new_meta.state, UInt<2>(0h0))
node _T_600 = and(_T_598, _T_599)
when _T_600 :
connect s_release, UInt<1>(0h0)
connect w_releaseack, UInt<1>(0h0)
node _T_601 = neq(new_meta.clients, UInt<1>(0h0))
node _T_602 = and(UInt<1>(0h1), _T_601)
when _T_602 :
connect s_rprobe, UInt<1>(0h0)
connect w_rprobeackfirst, UInt<1>(0h0)
connect w_rprobeacklast, UInt<1>(0h0)
node _T_603 = eq(new_meta.hit, UInt<1>(0h0))
node _T_604 = eq(new_meta.state, UInt<2>(0h1))
node _T_605 = and(_T_604, new_needT)
node _T_606 = or(_T_603, _T_605)
when _T_606 :
connect s_acquire, UInt<1>(0h0)
connect w_grantfirst, UInt<1>(0h0)
connect w_grantlast, UInt<1>(0h0)
connect w_grant, UInt<1>(0h0)
connect s_grantack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_607 = eq(new_meta.state, UInt<2>(0h2))
node _T_608 = or(new_needT, _T_607)
node _T_609 = and(new_meta.hit, _T_608)
node _T_610 = not(new_skipProbe)
node _T_611 = and(new_meta.clients, _T_610)
node _T_612 = neq(_T_611, UInt<1>(0h0))
node _T_613 = and(_T_609, _T_612)
node _T_614 = and(UInt<1>(0h1), _T_613)
when _T_614 :
connect s_pprobe, UInt<1>(0h0)
connect w_pprobeackfirst, UInt<1>(0h0)
connect w_pprobeacklast, UInt<1>(0h0)
connect w_pprobeack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_615 = eq(new_request.opcode, UInt<3>(0h6))
node _T_616 = eq(new_request.opcode, UInt<3>(0h7))
node _T_617 = or(_T_615, _T_616)
when _T_617 :
connect w_grantack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_618 = bits(new_request.opcode, 2, 2)
node _T_619 = eq(_T_618, UInt<1>(0h0))
node _T_620 = and(_T_619, new_meta.hit)
node _T_621 = eq(new_meta.dirty, UInt<1>(0h0))
node _T_622 = and(_T_620, _T_621)
when _T_622 :
connect s_writeback, UInt<1>(0h0) | module MSHR_56( // @[MSHR.scala:84:7]
input clock, // @[MSHR.scala:84:7]
input reset, // @[MSHR.scala:84:7]
input io_allocate_valid, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_0, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_1, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_2, // @[MSHR.scala:86:14]
input io_allocate_bits_control, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14]
input [8:0] io_allocate_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14]
input [10:0] io_allocate_bits_set, // @[MSHR.scala:86:14]
input io_allocate_bits_repeat, // @[MSHR.scala:86:14]
input io_directory_valid, // @[MSHR.scala:86:14]
input io_directory_bits_dirty, // @[MSHR.scala:86:14]
input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14]
input io_directory_bits_clients, // @[MSHR.scala:86:14]
input [8:0] io_directory_bits_tag, // @[MSHR.scala:86:14]
input io_directory_bits_hit, // @[MSHR.scala:86:14]
input [3:0] io_directory_bits_way, // @[MSHR.scala:86:14]
output io_status_valid, // @[MSHR.scala:86:14]
output [10:0] io_status_bits_set, // @[MSHR.scala:86:14]
output [8:0] io_status_bits_tag, // @[MSHR.scala:86:14]
output [3:0] io_status_bits_way, // @[MSHR.scala:86:14]
output io_status_bits_blockB, // @[MSHR.scala:86:14]
output io_status_bits_nestB, // @[MSHR.scala:86:14]
output io_status_bits_blockC, // @[MSHR.scala:86:14]
output io_status_bits_nestC, // @[MSHR.scala:86:14]
input io_schedule_ready, // @[MSHR.scala:86:14]
output io_schedule_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_a_valid, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14]
output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14]
output io_schedule_bits_b_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14]
output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14]
output io_schedule_bits_c_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14]
output [3:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14]
output io_schedule_bits_d_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14]
output [3:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14]
output io_schedule_bits_e_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14]
output io_schedule_bits_x_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14]
output [3:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14]
output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14]
output io_schedule_bits_reload, // @[MSHR.scala:86:14]
input io_sinkc_valid, // @[MSHR.scala:86:14]
input io_sinkc_bits_last, // @[MSHR.scala:86:14]
input [10:0] io_sinkc_bits_set, // @[MSHR.scala:86:14]
input [8:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14]
input io_sinkc_bits_data, // @[MSHR.scala:86:14]
input io_sinkd_valid, // @[MSHR.scala:86:14]
input io_sinkd_bits_last, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14]
input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14]
input io_sinkd_bits_denied, // @[MSHR.scala:86:14]
input io_sinke_valid, // @[MSHR.scala:86:14]
input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14]
input [10:0] io_nestedwb_set, // @[MSHR.scala:86:14]
input [8:0] io_nestedwb_tag, // @[MSHR.scala:86:14]
input io_nestedwb_b_toN, // @[MSHR.scala:86:14]
input io_nestedwb_b_toB, // @[MSHR.scala:86:14]
input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14]
input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14]
);
wire [8:0] final_meta_writeback_tag; // @[MSHR.scala:215:38]
wire final_meta_writeback_clients; // @[MSHR.scala:215:38]
wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38]
wire final_meta_writeback_dirty; // @[MSHR.scala:215:38]
wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7]
wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7]
wire [8:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7]
wire [10:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7]
wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7]
wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7]
wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7]
wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7]
wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7]
wire [8:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7]
wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7]
wire [3:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7]
wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7]
wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7]
wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7]
wire [10:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7]
wire [8:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7]
wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7]
wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7]
wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7]
wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7]
wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7]
wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7]
wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7]
wire [10:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7]
wire [8:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7]
wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7]
wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7]
wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68]
wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80]
wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21]
wire invalid_clients = 1'h0; // @[MSHR.scala:268:21]
wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137]
wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137]
wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire [8:0] invalid_tag = 9'h0; // @[MSHR.scala:268:21]
wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21]
wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70]
wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34]
wire [8:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34]
wire [10:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34]
wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40]
wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93]
wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28]
wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39]
wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105]
wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55]
wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91]
wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41]
wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41]
wire [8:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41]
wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51]
wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64]
wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41]
wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41]
wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57]
wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41]
wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43]
wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40]
wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66]
wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41]
wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41]
wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41]
wire [8:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41]
wire no_wait; // @[MSHR.scala:183:83]
wire [10:0] io_status_bits_set_0; // @[MSHR.scala:84:7]
wire [8:0] io_status_bits_tag_0; // @[MSHR.scala:84:7]
wire [3:0] io_status_bits_way_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockB_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestB_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockC_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestC_0; // @[MSHR.scala:84:7]
wire io_status_valid_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7]
wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7]
wire io_schedule_valid_0; // @[MSHR.scala:84:7]
reg request_valid; // @[MSHR.scala:97:30]
assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30]
reg request_prio_0; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20]
reg request_prio_1; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20]
reg request_prio_2; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20]
reg request_control; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_opcode; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_param; // @[MSHR.scala:98:20]
reg [2:0] request_size; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_source; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20]
reg [8:0] request_tag; // @[MSHR.scala:98:20]
assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_offset; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_put; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20]
reg [10:0] request_set; // @[MSHR.scala:98:20]
assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
reg meta_valid; // @[MSHR.scala:99:27]
reg meta_dirty; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17]
reg [1:0] meta_state; // @[MSHR.scala:100:17]
reg meta_clients; // @[MSHR.scala:100:17]
wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39]
wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
reg [8:0] meta_tag; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17]
reg meta_hit; // @[MSHR.scala:100:17]
reg [3:0] meta_way; // @[MSHR.scala:100:17]
assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
wire [3:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38]
reg s_rprobe; // @[MSHR.scala:121:33]
reg w_rprobeackfirst; // @[MSHR.scala:122:33]
reg w_rprobeacklast; // @[MSHR.scala:123:33]
reg s_release; // @[MSHR.scala:124:33]
reg w_releaseack; // @[MSHR.scala:125:33]
reg s_pprobe; // @[MSHR.scala:126:33]
reg s_acquire; // @[MSHR.scala:127:33]
reg s_flush; // @[MSHR.scala:128:33]
reg w_grantfirst; // @[MSHR.scala:129:33]
reg w_grantlast; // @[MSHR.scala:130:33]
reg w_grant; // @[MSHR.scala:131:33]
reg w_pprobeackfirst; // @[MSHR.scala:132:33]
reg w_pprobeacklast; // @[MSHR.scala:133:33]
reg w_pprobeack; // @[MSHR.scala:134:33]
reg s_grantack; // @[MSHR.scala:136:33]
reg s_execute; // @[MSHR.scala:137:33]
reg w_grantack; // @[MSHR.scala:138:33]
reg s_writeback; // @[MSHR.scala:139:33]
reg [2:0] sink; // @[MSHR.scala:147:17]
assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17]
reg gotT; // @[MSHR.scala:148:17]
reg bad_grant; // @[MSHR.scala:149:22]
assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22]
reg probes_done; // @[MSHR.scala:150:24]
reg probes_toN; // @[MSHR.scala:151:23]
reg probes_noT; // @[MSHR.scala:152:23]
wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28]
wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45]
wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62]
wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}]
wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82]
wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}]
wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103]
wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}]
assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}]
assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40]
wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39]
wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}]
wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}]
wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96]
assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}]
assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93]
assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28]
assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28]
wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43]
wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64]
wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}]
wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85]
wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}]
assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}]
assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39]
wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33]
wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}]
wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}]
assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}]
assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83]
wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31]
wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}]
assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}]
assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55]
wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31]
wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44]
assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}]
assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41]
wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32]
wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}]
assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}]
assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64]
wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31]
wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}]
assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}]
assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57]
wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31]
assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}]
assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43]
wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31]
assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}]
assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40]
wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34]
wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}]
wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70]
wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}]
assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}]
assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66]
wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49]
wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}]
wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}]
wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49]
wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}]
assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}]
assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105]
wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71]
wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71]
wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71]
wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire [8:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71]
wire final_meta_writeback_hit; // @[MSHR.scala:215:38]
wire req_clientBit = request_source == 6'h28; // @[Parameters.scala:46:9]
wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12]
wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12]
wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _req_needT_T_2; // @[Parameters.scala:270:13]
assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13]
wire _excluded_client_T_6; // @[Parameters.scala:279:117]
assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117]
wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42]
wire _req_needT_T_3; // @[Parameters.scala:270:42]
assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42]
wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11]
assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11]
wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42]
wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _req_needT_T_6; // @[Parameters.scala:271:14]
assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14]
wire _req_acquire_T; // @[MSHR.scala:219:36]
assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14]
wire _excluded_client_T_1; // @[Parameters.scala:279:12]
assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12]
wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52]
wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89]
wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52]
wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}]
wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}]
wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81]
wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}]
wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}]
wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}]
wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65]
wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}]
wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55]
wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78]
wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78]
assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78]
wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70]
wire _evict_T_2; // @[MSHR.scala:317:26]
assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _before_T_1; // @[MSHR.scala:317:26]
assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}]
wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}]
wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43]
assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43]
wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75]
wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}]
wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9]
wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}]
wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}]
wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54]
wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}]
wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45]
wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}]
wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}]
wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40]
wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40]
assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40]
wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65]
assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65]
wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41]
wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}]
wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72]
wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}]
wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70]
wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70]
wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53]
assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53]
wire _evict_T_1; // @[MSHR.scala:317:26]
assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire _before_T; // @[MSHR.scala:317:26]
assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70]
wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70]
wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55]
wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70]
wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70]
wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66]
wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}]
wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}]
wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9]
wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40]
assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30]
wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54]
wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}]
assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21]
assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21]
assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36]
assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36]
wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9]
wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}]
wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}]
wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38]
wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}]
wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}]
wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}]
wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106]
wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:46:9]
wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56]
wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70]
assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}]
wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51]
wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55]
wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52]
wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}]
wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}]
assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38]
assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91]
wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42]
wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70]
wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}]
assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}]
assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41]
wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42]
assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}]
assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41]
wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53]
assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}]
assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51]
assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41]
assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41]
assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}]
assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41]
wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42]
wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53]
wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53]
wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89]
wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79]
assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41]
wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42]
assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 9'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}]
assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41]
wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32]
wire [3:0] evict; // @[MSHR.scala:314:26]
wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32]
wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32]
wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32]
assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32]
assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39]
wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39]
assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39]
assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76]
wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76]
assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76]
assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32]
assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] before_0; // @[MSHR.scala:314:26]
wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32]
wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11]
assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] after; // @[MSHR.scala:314:26]
wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26]
wire _after_T; // @[MSHR.scala:317:26]
assign _after_T = _GEN_9; // @[MSHR.scala:317:26]
wire _prior_T; // @[MSHR.scala:317:26]
assign _prior_T = _GEN_9; // @[MSHR.scala:317:26]
wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32]
wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26]
wire _after_T_1; // @[MSHR.scala:317:26]
assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire _prior_T_1; // @[MSHR.scala:317:26]
assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32]
wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32]
assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32]
assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39]
wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39]
assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39]
assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76]
wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76]
assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76]
assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26]
wire _after_T_3; // @[MSHR.scala:317:26]
assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26]
wire _prior_T_3; // @[MSHR.scala:317:26]
assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26]
assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire probe_bit = io_sinkc_bits_source_0 == 6'h28; // @[Parameters.scala:46:9]
wire _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:46:9]
wire _last_probe_T; // @[MSHR.scala:459:33]
assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33]
wire _probes_done_T; // @[MSHR.scala:467:32]
assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32]
wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66]
wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}]
wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}]
wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11]
wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43]
wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75]
wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}]
wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9]
wire _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}]
wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53]
wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}]
wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42]
wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55]
wire _w_rprobeacklast_T; // @[MSHR.scala:471:55]
assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55]
wire _w_pprobeacklast_T; // @[MSHR.scala:473:55]
assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55]
wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}]
wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42]
wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}]
wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77]
wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}]
wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}]
wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32]
wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33]
wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}]
wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35]
wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40]
wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [8:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [3:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [8:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [10:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12]
wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _new_needT_T_2; // @[Parameters.scala:270:13]
assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13]
wire _new_skipProbe_T_5; // @[Parameters.scala:279:117]
assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117]
wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42]
wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _new_needT_T_6; // @[Parameters.scala:271:14]
assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14]
wire _new_skipProbe_T; // @[Parameters.scala:279:12]
assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12]
wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52]
wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89]
wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire new_clientBit = new_request_source == 6'h28; // @[Parameters.scala:46:9]
wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}]
wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}]
wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}]
wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9]
wire [3:0] prior; // @[MSHR.scala:314:26]
wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32]
wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28] |
Generate the Verilog code corresponding to this FIRRTL code module RotatingSingleVCAllocator :
input clock : Clock
input reset : Reset
output io : { req : { flip `6` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<0>, vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}}}, flip `5` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<0>, vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}}}, flip `4` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<0>, vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}}}, flip `3` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<0>, vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}}}, flip `2` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<0>, vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}}}, flip `1` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<2>, vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}}}, flip `0` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<2>, vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}}}}, resp : { `6` : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, `5` : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, `4` : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, `3` : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, `2` : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, `1` : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, `0` : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}}}, channel_status : { flip `5` : { occupied : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], flip `4` : { occupied : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], flip `3` : { occupied : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], flip `2` : { occupied : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], flip `1` : { occupied : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[3], flip `0` : { occupied : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[3]}, out_allocs : { `5` : { alloc : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], `4` : { alloc : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], `3` : { alloc : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], `2` : { alloc : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], `1` : { alloc : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[3], `0` : { alloc : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[3]}}
regreset mask : UInt<7>, clock, reset, UInt<7>(0h0)
wire in_arb_reqs : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}[7]
wire in_arb_vals : UInt<1>[7]
node in_arb_filter_lo_hi = cat(in_arb_vals[2], in_arb_vals[1])
node in_arb_filter_lo = cat(in_arb_filter_lo_hi, in_arb_vals[0])
node in_arb_filter_hi_lo = cat(in_arb_vals[4], in_arb_vals[3])
node in_arb_filter_hi_hi = cat(in_arb_vals[6], in_arb_vals[5])
node in_arb_filter_hi = cat(in_arb_filter_hi_hi, in_arb_filter_hi_lo)
node _in_arb_filter_T = cat(in_arb_filter_hi, in_arb_filter_lo)
node in_arb_filter_lo_hi_1 = cat(in_arb_vals[2], in_arb_vals[1])
node in_arb_filter_lo_1 = cat(in_arb_filter_lo_hi_1, in_arb_vals[0])
node in_arb_filter_hi_lo_1 = cat(in_arb_vals[4], in_arb_vals[3])
node in_arb_filter_hi_hi_1 = cat(in_arb_vals[6], in_arb_vals[5])
node in_arb_filter_hi_1 = cat(in_arb_filter_hi_hi_1, in_arb_filter_hi_lo_1)
node _in_arb_filter_T_1 = cat(in_arb_filter_hi_1, in_arb_filter_lo_1)
node _in_arb_filter_T_2 = not(mask)
node _in_arb_filter_T_3 = and(_in_arb_filter_T_1, _in_arb_filter_T_2)
node _in_arb_filter_T_4 = cat(_in_arb_filter_T, _in_arb_filter_T_3)
node _in_arb_filter_T_5 = bits(_in_arb_filter_T_4, 0, 0)
node _in_arb_filter_T_6 = bits(_in_arb_filter_T_4, 1, 1)
node _in_arb_filter_T_7 = bits(_in_arb_filter_T_4, 2, 2)
node _in_arb_filter_T_8 = bits(_in_arb_filter_T_4, 3, 3)
node _in_arb_filter_T_9 = bits(_in_arb_filter_T_4, 4, 4)
node _in_arb_filter_T_10 = bits(_in_arb_filter_T_4, 5, 5)
node _in_arb_filter_T_11 = bits(_in_arb_filter_T_4, 6, 6)
node _in_arb_filter_T_12 = bits(_in_arb_filter_T_4, 7, 7)
node _in_arb_filter_T_13 = bits(_in_arb_filter_T_4, 8, 8)
node _in_arb_filter_T_14 = bits(_in_arb_filter_T_4, 9, 9)
node _in_arb_filter_T_15 = bits(_in_arb_filter_T_4, 10, 10)
node _in_arb_filter_T_16 = bits(_in_arb_filter_T_4, 11, 11)
node _in_arb_filter_T_17 = bits(_in_arb_filter_T_4, 12, 12)
node _in_arb_filter_T_18 = bits(_in_arb_filter_T_4, 13, 13)
node _in_arb_filter_T_19 = mux(_in_arb_filter_T_18, UInt<14>(0h2000), UInt<14>(0h0))
node _in_arb_filter_T_20 = mux(_in_arb_filter_T_17, UInt<14>(0h1000), _in_arb_filter_T_19)
node _in_arb_filter_T_21 = mux(_in_arb_filter_T_16, UInt<14>(0h800), _in_arb_filter_T_20)
node _in_arb_filter_T_22 = mux(_in_arb_filter_T_15, UInt<14>(0h400), _in_arb_filter_T_21)
node _in_arb_filter_T_23 = mux(_in_arb_filter_T_14, UInt<14>(0h200), _in_arb_filter_T_22)
node _in_arb_filter_T_24 = mux(_in_arb_filter_T_13, UInt<14>(0h100), _in_arb_filter_T_23)
node _in_arb_filter_T_25 = mux(_in_arb_filter_T_12, UInt<14>(0h80), _in_arb_filter_T_24)
node _in_arb_filter_T_26 = mux(_in_arb_filter_T_11, UInt<14>(0h40), _in_arb_filter_T_25)
node _in_arb_filter_T_27 = mux(_in_arb_filter_T_10, UInt<14>(0h20), _in_arb_filter_T_26)
node _in_arb_filter_T_28 = mux(_in_arb_filter_T_9, UInt<14>(0h10), _in_arb_filter_T_27)
node _in_arb_filter_T_29 = mux(_in_arb_filter_T_8, UInt<14>(0h8), _in_arb_filter_T_28)
node _in_arb_filter_T_30 = mux(_in_arb_filter_T_7, UInt<14>(0h4), _in_arb_filter_T_29)
node _in_arb_filter_T_31 = mux(_in_arb_filter_T_6, UInt<14>(0h2), _in_arb_filter_T_30)
node in_arb_filter = mux(_in_arb_filter_T_5, UInt<14>(0h1), _in_arb_filter_T_31)
node _in_arb_sel_T = bits(in_arb_filter, 6, 0)
node _in_arb_sel_T_1 = shr(in_arb_filter, 7)
node in_arb_sel = or(_in_arb_sel_T, _in_arb_sel_T_1)
node _T = or(in_arb_vals[0], in_arb_vals[1])
node _T_1 = or(_T, in_arb_vals[2])
node _T_2 = or(_T_1, in_arb_vals[3])
node _T_3 = or(_T_2, in_arb_vals[4])
node _T_4 = or(_T_3, in_arb_vals[5])
node _T_5 = or(_T_4, in_arb_vals[6])
when _T_5 :
node _mask_T = not(UInt<1>(0h0))
node _mask_T_1 = not(UInt<2>(0h0))
node _mask_T_2 = not(UInt<3>(0h0))
node _mask_T_3 = not(UInt<4>(0h0))
node _mask_T_4 = not(UInt<5>(0h0))
node _mask_T_5 = not(UInt<6>(0h0))
node _mask_T_6 = not(UInt<7>(0h0))
node _mask_T_7 = bits(in_arb_sel, 0, 0)
node _mask_T_8 = bits(in_arb_sel, 1, 1)
node _mask_T_9 = bits(in_arb_sel, 2, 2)
node _mask_T_10 = bits(in_arb_sel, 3, 3)
node _mask_T_11 = bits(in_arb_sel, 4, 4)
node _mask_T_12 = bits(in_arb_sel, 5, 5)
node _mask_T_13 = bits(in_arb_sel, 6, 6)
node _mask_T_14 = mux(_mask_T_7, _mask_T, UInt<1>(0h0))
node _mask_T_15 = mux(_mask_T_8, _mask_T_1, UInt<1>(0h0))
node _mask_T_16 = mux(_mask_T_9, _mask_T_2, UInt<1>(0h0))
node _mask_T_17 = mux(_mask_T_10, _mask_T_3, UInt<1>(0h0))
node _mask_T_18 = mux(_mask_T_11, _mask_T_4, UInt<1>(0h0))
node _mask_T_19 = mux(_mask_T_12, _mask_T_5, UInt<1>(0h0))
node _mask_T_20 = mux(_mask_T_13, _mask_T_6, UInt<1>(0h0))
node _mask_T_21 = or(_mask_T_14, _mask_T_15)
node _mask_T_22 = or(_mask_T_21, _mask_T_16)
node _mask_T_23 = or(_mask_T_22, _mask_T_17)
node _mask_T_24 = or(_mask_T_23, _mask_T_18)
node _mask_T_25 = or(_mask_T_24, _mask_T_19)
node _mask_T_26 = or(_mask_T_25, _mask_T_20)
wire _mask_WIRE : UInt<7>
connect _mask_WIRE, _mask_T_26
connect mask, _mask_WIRE
node _in_arb_reqs_0_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_0_0_T_1 = and(io.req.`0`.bits.vc_sel.`0`[0], _in_arb_reqs_0_0_0_T)
connect in_arb_reqs[0].`0`[0], _in_arb_reqs_0_0_0_T_1
node _in_arb_reqs_0_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_0_1_T_1 = and(io.req.`0`.bits.vc_sel.`0`[1], _in_arb_reqs_0_0_1_T)
connect in_arb_reqs[0].`0`[1], _in_arb_reqs_0_0_1_T_1
node _in_arb_reqs_0_0_2_T = eq(io.channel_status.`0`[2].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_0_2_T_1 = and(io.req.`0`.bits.vc_sel.`0`[2], _in_arb_reqs_0_0_2_T)
connect in_arb_reqs[0].`0`[2], _in_arb_reqs_0_0_2_T_1
node _in_arb_reqs_0_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_1_0_T_1 = and(io.req.`0`.bits.vc_sel.`1`[0], _in_arb_reqs_0_1_0_T)
connect in_arb_reqs[0].`1`[0], _in_arb_reqs_0_1_0_T_1
node _in_arb_reqs_0_1_1_T = eq(io.channel_status.`1`[1].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_1_1_T_1 = and(io.req.`0`.bits.vc_sel.`1`[1], _in_arb_reqs_0_1_1_T)
connect in_arb_reqs[0].`1`[1], _in_arb_reqs_0_1_1_T_1
node _in_arb_reqs_0_1_2_T = eq(io.channel_status.`1`[2].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_1_2_T_1 = and(io.req.`0`.bits.vc_sel.`1`[2], _in_arb_reqs_0_1_2_T)
connect in_arb_reqs[0].`1`[2], _in_arb_reqs_0_1_2_T_1
node _in_arb_reqs_0_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_2_0_T_1 = and(io.req.`0`.bits.vc_sel.`2`[0], _in_arb_reqs_0_2_0_T)
connect in_arb_reqs[0].`2`[0], _in_arb_reqs_0_2_0_T_1
node _in_arb_reqs_0_3_0_T = eq(io.channel_status.`3`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_3_0_T_1 = and(io.req.`0`.bits.vc_sel.`3`[0], _in_arb_reqs_0_3_0_T)
connect in_arb_reqs[0].`3`[0], _in_arb_reqs_0_3_0_T_1
node _in_arb_reqs_0_4_0_T = eq(io.channel_status.`4`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_4_0_T_1 = and(io.req.`0`.bits.vc_sel.`4`[0], _in_arb_reqs_0_4_0_T)
connect in_arb_reqs[0].`4`[0], _in_arb_reqs_0_4_0_T_1
node _in_arb_reqs_0_5_0_T = eq(io.channel_status.`5`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_5_0_T_1 = and(io.req.`0`.bits.vc_sel.`5`[0], _in_arb_reqs_0_5_0_T)
connect in_arb_reqs[0].`5`[0], _in_arb_reqs_0_5_0_T_1
node _in_arb_vals_0_T = or(in_arb_reqs[0].`0`[0], in_arb_reqs[0].`0`[1])
node _in_arb_vals_0_T_1 = or(_in_arb_vals_0_T, in_arb_reqs[0].`0`[2])
node _in_arb_vals_0_T_2 = or(in_arb_reqs[0].`1`[0], in_arb_reqs[0].`1`[1])
node _in_arb_vals_0_T_3 = or(_in_arb_vals_0_T_2, in_arb_reqs[0].`1`[2])
node _in_arb_vals_0_T_4 = or(_in_arb_vals_0_T_1, _in_arb_vals_0_T_3)
node _in_arb_vals_0_T_5 = or(_in_arb_vals_0_T_4, in_arb_reqs[0].`2`[0])
node _in_arb_vals_0_T_6 = or(_in_arb_vals_0_T_5, in_arb_reqs[0].`3`[0])
node _in_arb_vals_0_T_7 = or(_in_arb_vals_0_T_6, in_arb_reqs[0].`4`[0])
node _in_arb_vals_0_T_8 = or(_in_arb_vals_0_T_7, in_arb_reqs[0].`5`[0])
node _in_arb_vals_0_T_9 = and(io.req.`0`.valid, _in_arb_vals_0_T_8)
connect in_arb_vals[0], _in_arb_vals_0_T_9
node _in_arb_reqs_1_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_0_0_T_1 = and(io.req.`1`.bits.vc_sel.`0`[0], _in_arb_reqs_1_0_0_T)
connect in_arb_reqs[1].`0`[0], _in_arb_reqs_1_0_0_T_1
node _in_arb_reqs_1_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_0_1_T_1 = and(io.req.`1`.bits.vc_sel.`0`[1], _in_arb_reqs_1_0_1_T)
connect in_arb_reqs[1].`0`[1], _in_arb_reqs_1_0_1_T_1
node _in_arb_reqs_1_0_2_T = eq(io.channel_status.`0`[2].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_0_2_T_1 = and(io.req.`1`.bits.vc_sel.`0`[2], _in_arb_reqs_1_0_2_T)
connect in_arb_reqs[1].`0`[2], _in_arb_reqs_1_0_2_T_1
node _in_arb_reqs_1_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_1_0_T_1 = and(io.req.`1`.bits.vc_sel.`1`[0], _in_arb_reqs_1_1_0_T)
connect in_arb_reqs[1].`1`[0], _in_arb_reqs_1_1_0_T_1
node _in_arb_reqs_1_1_1_T = eq(io.channel_status.`1`[1].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_1_1_T_1 = and(io.req.`1`.bits.vc_sel.`1`[1], _in_arb_reqs_1_1_1_T)
connect in_arb_reqs[1].`1`[1], _in_arb_reqs_1_1_1_T_1
node _in_arb_reqs_1_1_2_T = eq(io.channel_status.`1`[2].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_1_2_T_1 = and(io.req.`1`.bits.vc_sel.`1`[2], _in_arb_reqs_1_1_2_T)
connect in_arb_reqs[1].`1`[2], _in_arb_reqs_1_1_2_T_1
node _in_arb_reqs_1_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_2_0_T_1 = and(io.req.`1`.bits.vc_sel.`2`[0], _in_arb_reqs_1_2_0_T)
connect in_arb_reqs[1].`2`[0], _in_arb_reqs_1_2_0_T_1
node _in_arb_reqs_1_3_0_T = eq(io.channel_status.`3`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_3_0_T_1 = and(io.req.`1`.bits.vc_sel.`3`[0], _in_arb_reqs_1_3_0_T)
connect in_arb_reqs[1].`3`[0], _in_arb_reqs_1_3_0_T_1
node _in_arb_reqs_1_4_0_T = eq(io.channel_status.`4`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_4_0_T_1 = and(io.req.`1`.bits.vc_sel.`4`[0], _in_arb_reqs_1_4_0_T)
connect in_arb_reqs[1].`4`[0], _in_arb_reqs_1_4_0_T_1
node _in_arb_reqs_1_5_0_T = eq(io.channel_status.`5`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_5_0_T_1 = and(io.req.`1`.bits.vc_sel.`5`[0], _in_arb_reqs_1_5_0_T)
connect in_arb_reqs[1].`5`[0], _in_arb_reqs_1_5_0_T_1
node _in_arb_vals_1_T = or(in_arb_reqs[1].`0`[0], in_arb_reqs[1].`0`[1])
node _in_arb_vals_1_T_1 = or(_in_arb_vals_1_T, in_arb_reqs[1].`0`[2])
node _in_arb_vals_1_T_2 = or(in_arb_reqs[1].`1`[0], in_arb_reqs[1].`1`[1])
node _in_arb_vals_1_T_3 = or(_in_arb_vals_1_T_2, in_arb_reqs[1].`1`[2])
node _in_arb_vals_1_T_4 = or(_in_arb_vals_1_T_1, _in_arb_vals_1_T_3)
node _in_arb_vals_1_T_5 = or(_in_arb_vals_1_T_4, in_arb_reqs[1].`2`[0])
node _in_arb_vals_1_T_6 = or(_in_arb_vals_1_T_5, in_arb_reqs[1].`3`[0])
node _in_arb_vals_1_T_7 = or(_in_arb_vals_1_T_6, in_arb_reqs[1].`4`[0])
node _in_arb_vals_1_T_8 = or(_in_arb_vals_1_T_7, in_arb_reqs[1].`5`[0])
node _in_arb_vals_1_T_9 = and(io.req.`1`.valid, _in_arb_vals_1_T_8)
connect in_arb_vals[1], _in_arb_vals_1_T_9
node _in_arb_reqs_2_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_0_0_T_1 = and(io.req.`2`.bits.vc_sel.`0`[0], _in_arb_reqs_2_0_0_T)
connect in_arb_reqs[2].`0`[0], _in_arb_reqs_2_0_0_T_1
node _in_arb_reqs_2_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_0_1_T_1 = and(io.req.`2`.bits.vc_sel.`0`[1], _in_arb_reqs_2_0_1_T)
connect in_arb_reqs[2].`0`[1], _in_arb_reqs_2_0_1_T_1
node _in_arb_reqs_2_0_2_T = eq(io.channel_status.`0`[2].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_0_2_T_1 = and(io.req.`2`.bits.vc_sel.`0`[2], _in_arb_reqs_2_0_2_T)
connect in_arb_reqs[2].`0`[2], _in_arb_reqs_2_0_2_T_1
node _in_arb_reqs_2_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_1_0_T_1 = and(io.req.`2`.bits.vc_sel.`1`[0], _in_arb_reqs_2_1_0_T)
connect in_arb_reqs[2].`1`[0], _in_arb_reqs_2_1_0_T_1
node _in_arb_reqs_2_1_1_T = eq(io.channel_status.`1`[1].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_1_1_T_1 = and(io.req.`2`.bits.vc_sel.`1`[1], _in_arb_reqs_2_1_1_T)
connect in_arb_reqs[2].`1`[1], _in_arb_reqs_2_1_1_T_1
node _in_arb_reqs_2_1_2_T = eq(io.channel_status.`1`[2].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_1_2_T_1 = and(io.req.`2`.bits.vc_sel.`1`[2], _in_arb_reqs_2_1_2_T)
connect in_arb_reqs[2].`1`[2], _in_arb_reqs_2_1_2_T_1
node _in_arb_reqs_2_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_2_0_T_1 = and(io.req.`2`.bits.vc_sel.`2`[0], _in_arb_reqs_2_2_0_T)
connect in_arb_reqs[2].`2`[0], _in_arb_reqs_2_2_0_T_1
node _in_arb_reqs_2_3_0_T = eq(io.channel_status.`3`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_3_0_T_1 = and(io.req.`2`.bits.vc_sel.`3`[0], _in_arb_reqs_2_3_0_T)
connect in_arb_reqs[2].`3`[0], _in_arb_reqs_2_3_0_T_1
node _in_arb_reqs_2_4_0_T = eq(io.channel_status.`4`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_4_0_T_1 = and(io.req.`2`.bits.vc_sel.`4`[0], _in_arb_reqs_2_4_0_T)
connect in_arb_reqs[2].`4`[0], _in_arb_reqs_2_4_0_T_1
node _in_arb_reqs_2_5_0_T = eq(io.channel_status.`5`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_5_0_T_1 = and(io.req.`2`.bits.vc_sel.`5`[0], _in_arb_reqs_2_5_0_T)
connect in_arb_reqs[2].`5`[0], _in_arb_reqs_2_5_0_T_1
node _in_arb_vals_2_T = or(in_arb_reqs[2].`0`[0], in_arb_reqs[2].`0`[1])
node _in_arb_vals_2_T_1 = or(_in_arb_vals_2_T, in_arb_reqs[2].`0`[2])
node _in_arb_vals_2_T_2 = or(in_arb_reqs[2].`1`[0], in_arb_reqs[2].`1`[1])
node _in_arb_vals_2_T_3 = or(_in_arb_vals_2_T_2, in_arb_reqs[2].`1`[2])
node _in_arb_vals_2_T_4 = or(_in_arb_vals_2_T_1, _in_arb_vals_2_T_3)
node _in_arb_vals_2_T_5 = or(_in_arb_vals_2_T_4, in_arb_reqs[2].`2`[0])
node _in_arb_vals_2_T_6 = or(_in_arb_vals_2_T_5, in_arb_reqs[2].`3`[0])
node _in_arb_vals_2_T_7 = or(_in_arb_vals_2_T_6, in_arb_reqs[2].`4`[0])
node _in_arb_vals_2_T_8 = or(_in_arb_vals_2_T_7, in_arb_reqs[2].`5`[0])
node _in_arb_vals_2_T_9 = and(io.req.`2`.valid, _in_arb_vals_2_T_8)
connect in_arb_vals[2], _in_arb_vals_2_T_9
node _in_arb_reqs_3_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_3_0_0_T_1 = and(io.req.`3`.bits.vc_sel.`0`[0], _in_arb_reqs_3_0_0_T)
connect in_arb_reqs[3].`0`[0], _in_arb_reqs_3_0_0_T_1
node _in_arb_reqs_3_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0))
node _in_arb_reqs_3_0_1_T_1 = and(io.req.`3`.bits.vc_sel.`0`[1], _in_arb_reqs_3_0_1_T)
connect in_arb_reqs[3].`0`[1], _in_arb_reqs_3_0_1_T_1
node _in_arb_reqs_3_0_2_T = eq(io.channel_status.`0`[2].occupied, UInt<1>(0h0))
node _in_arb_reqs_3_0_2_T_1 = and(io.req.`3`.bits.vc_sel.`0`[2], _in_arb_reqs_3_0_2_T)
connect in_arb_reqs[3].`0`[2], _in_arb_reqs_3_0_2_T_1
node _in_arb_reqs_3_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_3_1_0_T_1 = and(io.req.`3`.bits.vc_sel.`1`[0], _in_arb_reqs_3_1_0_T)
connect in_arb_reqs[3].`1`[0], _in_arb_reqs_3_1_0_T_1
node _in_arb_reqs_3_1_1_T = eq(io.channel_status.`1`[1].occupied, UInt<1>(0h0))
node _in_arb_reqs_3_1_1_T_1 = and(io.req.`3`.bits.vc_sel.`1`[1], _in_arb_reqs_3_1_1_T)
connect in_arb_reqs[3].`1`[1], _in_arb_reqs_3_1_1_T_1
node _in_arb_reqs_3_1_2_T = eq(io.channel_status.`1`[2].occupied, UInt<1>(0h0))
node _in_arb_reqs_3_1_2_T_1 = and(io.req.`3`.bits.vc_sel.`1`[2], _in_arb_reqs_3_1_2_T)
connect in_arb_reqs[3].`1`[2], _in_arb_reqs_3_1_2_T_1
node _in_arb_reqs_3_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_3_2_0_T_1 = and(io.req.`3`.bits.vc_sel.`2`[0], _in_arb_reqs_3_2_0_T)
connect in_arb_reqs[3].`2`[0], _in_arb_reqs_3_2_0_T_1
node _in_arb_reqs_3_3_0_T = eq(io.channel_status.`3`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_3_3_0_T_1 = and(io.req.`3`.bits.vc_sel.`3`[0], _in_arb_reqs_3_3_0_T)
connect in_arb_reqs[3].`3`[0], _in_arb_reqs_3_3_0_T_1
node _in_arb_reqs_3_4_0_T = eq(io.channel_status.`4`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_3_4_0_T_1 = and(io.req.`3`.bits.vc_sel.`4`[0], _in_arb_reqs_3_4_0_T)
connect in_arb_reqs[3].`4`[0], _in_arb_reqs_3_4_0_T_1
node _in_arb_reqs_3_5_0_T = eq(io.channel_status.`5`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_3_5_0_T_1 = and(io.req.`3`.bits.vc_sel.`5`[0], _in_arb_reqs_3_5_0_T)
connect in_arb_reqs[3].`5`[0], _in_arb_reqs_3_5_0_T_1
node _in_arb_vals_3_T = or(in_arb_reqs[3].`0`[0], in_arb_reqs[3].`0`[1])
node _in_arb_vals_3_T_1 = or(_in_arb_vals_3_T, in_arb_reqs[3].`0`[2])
node _in_arb_vals_3_T_2 = or(in_arb_reqs[3].`1`[0], in_arb_reqs[3].`1`[1])
node _in_arb_vals_3_T_3 = or(_in_arb_vals_3_T_2, in_arb_reqs[3].`1`[2])
node _in_arb_vals_3_T_4 = or(_in_arb_vals_3_T_1, _in_arb_vals_3_T_3)
node _in_arb_vals_3_T_5 = or(_in_arb_vals_3_T_4, in_arb_reqs[3].`2`[0])
node _in_arb_vals_3_T_6 = or(_in_arb_vals_3_T_5, in_arb_reqs[3].`3`[0])
node _in_arb_vals_3_T_7 = or(_in_arb_vals_3_T_6, in_arb_reqs[3].`4`[0])
node _in_arb_vals_3_T_8 = or(_in_arb_vals_3_T_7, in_arb_reqs[3].`5`[0])
node _in_arb_vals_3_T_9 = and(io.req.`3`.valid, _in_arb_vals_3_T_8)
connect in_arb_vals[3], _in_arb_vals_3_T_9
node _in_arb_reqs_4_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_4_0_0_T_1 = and(io.req.`4`.bits.vc_sel.`0`[0], _in_arb_reqs_4_0_0_T)
connect in_arb_reqs[4].`0`[0], _in_arb_reqs_4_0_0_T_1
node _in_arb_reqs_4_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0))
node _in_arb_reqs_4_0_1_T_1 = and(io.req.`4`.bits.vc_sel.`0`[1], _in_arb_reqs_4_0_1_T)
connect in_arb_reqs[4].`0`[1], _in_arb_reqs_4_0_1_T_1
node _in_arb_reqs_4_0_2_T = eq(io.channel_status.`0`[2].occupied, UInt<1>(0h0))
node _in_arb_reqs_4_0_2_T_1 = and(io.req.`4`.bits.vc_sel.`0`[2], _in_arb_reqs_4_0_2_T)
connect in_arb_reqs[4].`0`[2], _in_arb_reqs_4_0_2_T_1
node _in_arb_reqs_4_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_4_1_0_T_1 = and(io.req.`4`.bits.vc_sel.`1`[0], _in_arb_reqs_4_1_0_T)
connect in_arb_reqs[4].`1`[0], _in_arb_reqs_4_1_0_T_1
node _in_arb_reqs_4_1_1_T = eq(io.channel_status.`1`[1].occupied, UInt<1>(0h0))
node _in_arb_reqs_4_1_1_T_1 = and(io.req.`4`.bits.vc_sel.`1`[1], _in_arb_reqs_4_1_1_T)
connect in_arb_reqs[4].`1`[1], _in_arb_reqs_4_1_1_T_1
node _in_arb_reqs_4_1_2_T = eq(io.channel_status.`1`[2].occupied, UInt<1>(0h0))
node _in_arb_reqs_4_1_2_T_1 = and(io.req.`4`.bits.vc_sel.`1`[2], _in_arb_reqs_4_1_2_T)
connect in_arb_reqs[4].`1`[2], _in_arb_reqs_4_1_2_T_1
node _in_arb_reqs_4_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_4_2_0_T_1 = and(io.req.`4`.bits.vc_sel.`2`[0], _in_arb_reqs_4_2_0_T)
connect in_arb_reqs[4].`2`[0], _in_arb_reqs_4_2_0_T_1
node _in_arb_reqs_4_3_0_T = eq(io.channel_status.`3`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_4_3_0_T_1 = and(io.req.`4`.bits.vc_sel.`3`[0], _in_arb_reqs_4_3_0_T)
connect in_arb_reqs[4].`3`[0], _in_arb_reqs_4_3_0_T_1
node _in_arb_reqs_4_4_0_T = eq(io.channel_status.`4`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_4_4_0_T_1 = and(io.req.`4`.bits.vc_sel.`4`[0], _in_arb_reqs_4_4_0_T)
connect in_arb_reqs[4].`4`[0], _in_arb_reqs_4_4_0_T_1
node _in_arb_reqs_4_5_0_T = eq(io.channel_status.`5`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_4_5_0_T_1 = and(io.req.`4`.bits.vc_sel.`5`[0], _in_arb_reqs_4_5_0_T)
connect in_arb_reqs[4].`5`[0], _in_arb_reqs_4_5_0_T_1
node _in_arb_vals_4_T = or(in_arb_reqs[4].`0`[0], in_arb_reqs[4].`0`[1])
node _in_arb_vals_4_T_1 = or(_in_arb_vals_4_T, in_arb_reqs[4].`0`[2])
node _in_arb_vals_4_T_2 = or(in_arb_reqs[4].`1`[0], in_arb_reqs[4].`1`[1])
node _in_arb_vals_4_T_3 = or(_in_arb_vals_4_T_2, in_arb_reqs[4].`1`[2])
node _in_arb_vals_4_T_4 = or(_in_arb_vals_4_T_1, _in_arb_vals_4_T_3)
node _in_arb_vals_4_T_5 = or(_in_arb_vals_4_T_4, in_arb_reqs[4].`2`[0])
node _in_arb_vals_4_T_6 = or(_in_arb_vals_4_T_5, in_arb_reqs[4].`3`[0])
node _in_arb_vals_4_T_7 = or(_in_arb_vals_4_T_6, in_arb_reqs[4].`4`[0])
node _in_arb_vals_4_T_8 = or(_in_arb_vals_4_T_7, in_arb_reqs[4].`5`[0])
node _in_arb_vals_4_T_9 = and(io.req.`4`.valid, _in_arb_vals_4_T_8)
connect in_arb_vals[4], _in_arb_vals_4_T_9
node _in_arb_reqs_5_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_5_0_0_T_1 = and(io.req.`5`.bits.vc_sel.`0`[0], _in_arb_reqs_5_0_0_T)
connect in_arb_reqs[5].`0`[0], _in_arb_reqs_5_0_0_T_1
node _in_arb_reqs_5_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0))
node _in_arb_reqs_5_0_1_T_1 = and(io.req.`5`.bits.vc_sel.`0`[1], _in_arb_reqs_5_0_1_T)
connect in_arb_reqs[5].`0`[1], _in_arb_reqs_5_0_1_T_1
node _in_arb_reqs_5_0_2_T = eq(io.channel_status.`0`[2].occupied, UInt<1>(0h0))
node _in_arb_reqs_5_0_2_T_1 = and(io.req.`5`.bits.vc_sel.`0`[2], _in_arb_reqs_5_0_2_T)
connect in_arb_reqs[5].`0`[2], _in_arb_reqs_5_0_2_T_1
node _in_arb_reqs_5_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_5_1_0_T_1 = and(io.req.`5`.bits.vc_sel.`1`[0], _in_arb_reqs_5_1_0_T)
connect in_arb_reqs[5].`1`[0], _in_arb_reqs_5_1_0_T_1
node _in_arb_reqs_5_1_1_T = eq(io.channel_status.`1`[1].occupied, UInt<1>(0h0))
node _in_arb_reqs_5_1_1_T_1 = and(io.req.`5`.bits.vc_sel.`1`[1], _in_arb_reqs_5_1_1_T)
connect in_arb_reqs[5].`1`[1], _in_arb_reqs_5_1_1_T_1
node _in_arb_reqs_5_1_2_T = eq(io.channel_status.`1`[2].occupied, UInt<1>(0h0))
node _in_arb_reqs_5_1_2_T_1 = and(io.req.`5`.bits.vc_sel.`1`[2], _in_arb_reqs_5_1_2_T)
connect in_arb_reqs[5].`1`[2], _in_arb_reqs_5_1_2_T_1
node _in_arb_reqs_5_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_5_2_0_T_1 = and(io.req.`5`.bits.vc_sel.`2`[0], _in_arb_reqs_5_2_0_T)
connect in_arb_reqs[5].`2`[0], _in_arb_reqs_5_2_0_T_1
node _in_arb_reqs_5_3_0_T = eq(io.channel_status.`3`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_5_3_0_T_1 = and(io.req.`5`.bits.vc_sel.`3`[0], _in_arb_reqs_5_3_0_T)
connect in_arb_reqs[5].`3`[0], _in_arb_reqs_5_3_0_T_1
node _in_arb_reqs_5_4_0_T = eq(io.channel_status.`4`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_5_4_0_T_1 = and(io.req.`5`.bits.vc_sel.`4`[0], _in_arb_reqs_5_4_0_T)
connect in_arb_reqs[5].`4`[0], _in_arb_reqs_5_4_0_T_1
node _in_arb_reqs_5_5_0_T = eq(io.channel_status.`5`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_5_5_0_T_1 = and(io.req.`5`.bits.vc_sel.`5`[0], _in_arb_reqs_5_5_0_T)
connect in_arb_reqs[5].`5`[0], _in_arb_reqs_5_5_0_T_1
node _in_arb_vals_5_T = or(in_arb_reqs[5].`0`[0], in_arb_reqs[5].`0`[1])
node _in_arb_vals_5_T_1 = or(_in_arb_vals_5_T, in_arb_reqs[5].`0`[2])
node _in_arb_vals_5_T_2 = or(in_arb_reqs[5].`1`[0], in_arb_reqs[5].`1`[1])
node _in_arb_vals_5_T_3 = or(_in_arb_vals_5_T_2, in_arb_reqs[5].`1`[2])
node _in_arb_vals_5_T_4 = or(_in_arb_vals_5_T_1, _in_arb_vals_5_T_3)
node _in_arb_vals_5_T_5 = or(_in_arb_vals_5_T_4, in_arb_reqs[5].`2`[0])
node _in_arb_vals_5_T_6 = or(_in_arb_vals_5_T_5, in_arb_reqs[5].`3`[0])
node _in_arb_vals_5_T_7 = or(_in_arb_vals_5_T_6, in_arb_reqs[5].`4`[0])
node _in_arb_vals_5_T_8 = or(_in_arb_vals_5_T_7, in_arb_reqs[5].`5`[0])
node _in_arb_vals_5_T_9 = and(io.req.`5`.valid, _in_arb_vals_5_T_8)
connect in_arb_vals[5], _in_arb_vals_5_T_9
node _in_arb_reqs_6_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_6_0_0_T_1 = and(io.req.`6`.bits.vc_sel.`0`[0], _in_arb_reqs_6_0_0_T)
connect in_arb_reqs[6].`0`[0], _in_arb_reqs_6_0_0_T_1
node _in_arb_reqs_6_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0))
node _in_arb_reqs_6_0_1_T_1 = and(io.req.`6`.bits.vc_sel.`0`[1], _in_arb_reqs_6_0_1_T)
connect in_arb_reqs[6].`0`[1], _in_arb_reqs_6_0_1_T_1
node _in_arb_reqs_6_0_2_T = eq(io.channel_status.`0`[2].occupied, UInt<1>(0h0))
node _in_arb_reqs_6_0_2_T_1 = and(io.req.`6`.bits.vc_sel.`0`[2], _in_arb_reqs_6_0_2_T)
connect in_arb_reqs[6].`0`[2], _in_arb_reqs_6_0_2_T_1
node _in_arb_reqs_6_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_6_1_0_T_1 = and(io.req.`6`.bits.vc_sel.`1`[0], _in_arb_reqs_6_1_0_T)
connect in_arb_reqs[6].`1`[0], _in_arb_reqs_6_1_0_T_1
node _in_arb_reqs_6_1_1_T = eq(io.channel_status.`1`[1].occupied, UInt<1>(0h0))
node _in_arb_reqs_6_1_1_T_1 = and(io.req.`6`.bits.vc_sel.`1`[1], _in_arb_reqs_6_1_1_T)
connect in_arb_reqs[6].`1`[1], _in_arb_reqs_6_1_1_T_1
node _in_arb_reqs_6_1_2_T = eq(io.channel_status.`1`[2].occupied, UInt<1>(0h0))
node _in_arb_reqs_6_1_2_T_1 = and(io.req.`6`.bits.vc_sel.`1`[2], _in_arb_reqs_6_1_2_T)
connect in_arb_reqs[6].`1`[2], _in_arb_reqs_6_1_2_T_1
node _in_arb_reqs_6_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_6_2_0_T_1 = and(io.req.`6`.bits.vc_sel.`2`[0], _in_arb_reqs_6_2_0_T)
connect in_arb_reqs[6].`2`[0], _in_arb_reqs_6_2_0_T_1
node _in_arb_reqs_6_3_0_T = eq(io.channel_status.`3`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_6_3_0_T_1 = and(io.req.`6`.bits.vc_sel.`3`[0], _in_arb_reqs_6_3_0_T)
connect in_arb_reqs[6].`3`[0], _in_arb_reqs_6_3_0_T_1
node _in_arb_reqs_6_4_0_T = eq(io.channel_status.`4`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_6_4_0_T_1 = and(io.req.`6`.bits.vc_sel.`4`[0], _in_arb_reqs_6_4_0_T)
connect in_arb_reqs[6].`4`[0], _in_arb_reqs_6_4_0_T_1
node _in_arb_reqs_6_5_0_T = eq(io.channel_status.`5`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_6_5_0_T_1 = and(io.req.`6`.bits.vc_sel.`5`[0], _in_arb_reqs_6_5_0_T)
connect in_arb_reqs[6].`5`[0], _in_arb_reqs_6_5_0_T_1
node _in_arb_vals_6_T = or(in_arb_reqs[6].`0`[0], in_arb_reqs[6].`0`[1])
node _in_arb_vals_6_T_1 = or(_in_arb_vals_6_T, in_arb_reqs[6].`0`[2])
node _in_arb_vals_6_T_2 = or(in_arb_reqs[6].`1`[0], in_arb_reqs[6].`1`[1])
node _in_arb_vals_6_T_3 = or(_in_arb_vals_6_T_2, in_arb_reqs[6].`1`[2])
node _in_arb_vals_6_T_4 = or(_in_arb_vals_6_T_1, _in_arb_vals_6_T_3)
node _in_arb_vals_6_T_5 = or(_in_arb_vals_6_T_4, in_arb_reqs[6].`2`[0])
node _in_arb_vals_6_T_6 = or(_in_arb_vals_6_T_5, in_arb_reqs[6].`3`[0])
node _in_arb_vals_6_T_7 = or(_in_arb_vals_6_T_6, in_arb_reqs[6].`4`[0])
node _in_arb_vals_6_T_8 = or(_in_arb_vals_6_T_7, in_arb_reqs[6].`5`[0])
node _in_arb_vals_6_T_9 = and(io.req.`6`.valid, _in_arb_vals_6_T_8)
connect in_arb_vals[6], _in_arb_vals_6_T_9
connect io.req.`0`.ready, UInt<1>(0h0)
connect io.req.`1`.ready, UInt<1>(0h0)
connect io.req.`2`.ready, UInt<1>(0h0)
connect io.req.`3`.ready, UInt<1>(0h0)
connect io.req.`4`.ready, UInt<1>(0h0)
connect io.req.`5`.ready, UInt<1>(0h0)
connect io.req.`6`.ready, UInt<1>(0h0)
wire in_alloc : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}
node _in_flow_T = bits(in_arb_sel, 0, 0)
node _in_flow_T_1 = bits(in_arb_sel, 1, 1)
node _in_flow_T_2 = bits(in_arb_sel, 2, 2)
node _in_flow_T_3 = bits(in_arb_sel, 3, 3)
node _in_flow_T_4 = bits(in_arb_sel, 4, 4)
node _in_flow_T_5 = bits(in_arb_sel, 5, 5)
node _in_flow_T_6 = bits(in_arb_sel, 6, 6)
wire in_flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}
node _in_flow_T_7 = mux(_in_flow_T, io.req.`0`.bits.flow.egress_node_id, UInt<1>(0h0))
node _in_flow_T_8 = mux(_in_flow_T_1, io.req.`1`.bits.flow.egress_node_id, UInt<1>(0h0))
node _in_flow_T_9 = mux(_in_flow_T_2, io.req.`2`.bits.flow.egress_node_id, UInt<1>(0h0))
node _in_flow_T_10 = mux(_in_flow_T_3, io.req.`3`.bits.flow.egress_node_id, UInt<1>(0h0))
node _in_flow_T_11 = mux(_in_flow_T_4, io.req.`4`.bits.flow.egress_node_id, UInt<1>(0h0))
node _in_flow_T_12 = mux(_in_flow_T_5, io.req.`5`.bits.flow.egress_node_id, UInt<1>(0h0))
node _in_flow_T_13 = mux(_in_flow_T_6, io.req.`6`.bits.flow.egress_node_id, UInt<1>(0h0))
node _in_flow_T_14 = or(_in_flow_T_7, _in_flow_T_8)
node _in_flow_T_15 = or(_in_flow_T_14, _in_flow_T_9)
node _in_flow_T_16 = or(_in_flow_T_15, _in_flow_T_10)
node _in_flow_T_17 = or(_in_flow_T_16, _in_flow_T_11)
node _in_flow_T_18 = or(_in_flow_T_17, _in_flow_T_12)
node _in_flow_T_19 = or(_in_flow_T_18, _in_flow_T_13)
wire _in_flow_WIRE : UInt<2>
connect _in_flow_WIRE, _in_flow_T_19
connect in_flow.egress_node_id, _in_flow_WIRE
node _in_flow_T_20 = mux(_in_flow_T, io.req.`0`.bits.flow.egress_node, UInt<1>(0h0))
node _in_flow_T_21 = mux(_in_flow_T_1, io.req.`1`.bits.flow.egress_node, UInt<1>(0h0))
node _in_flow_T_22 = mux(_in_flow_T_2, io.req.`2`.bits.flow.egress_node, UInt<1>(0h0))
node _in_flow_T_23 = mux(_in_flow_T_3, io.req.`3`.bits.flow.egress_node, UInt<1>(0h0))
node _in_flow_T_24 = mux(_in_flow_T_4, io.req.`4`.bits.flow.egress_node, UInt<1>(0h0))
node _in_flow_T_25 = mux(_in_flow_T_5, io.req.`5`.bits.flow.egress_node, UInt<1>(0h0))
node _in_flow_T_26 = mux(_in_flow_T_6, io.req.`6`.bits.flow.egress_node, UInt<1>(0h0))
node _in_flow_T_27 = or(_in_flow_T_20, _in_flow_T_21)
node _in_flow_T_28 = or(_in_flow_T_27, _in_flow_T_22)
node _in_flow_T_29 = or(_in_flow_T_28, _in_flow_T_23)
node _in_flow_T_30 = or(_in_flow_T_29, _in_flow_T_24)
node _in_flow_T_31 = or(_in_flow_T_30, _in_flow_T_25)
node _in_flow_T_32 = or(_in_flow_T_31, _in_flow_T_26)
wire _in_flow_WIRE_1 : UInt<4>
connect _in_flow_WIRE_1, _in_flow_T_32
connect in_flow.egress_node, _in_flow_WIRE_1
node _in_flow_T_33 = mux(_in_flow_T, io.req.`0`.bits.flow.ingress_node_id, UInt<1>(0h0))
node _in_flow_T_34 = mux(_in_flow_T_1, io.req.`1`.bits.flow.ingress_node_id, UInt<1>(0h0))
node _in_flow_T_35 = mux(_in_flow_T_2, io.req.`2`.bits.flow.ingress_node_id, UInt<1>(0h0))
node _in_flow_T_36 = mux(_in_flow_T_3, io.req.`3`.bits.flow.ingress_node_id, UInt<1>(0h0))
node _in_flow_T_37 = mux(_in_flow_T_4, io.req.`4`.bits.flow.ingress_node_id, UInt<1>(0h0))
node _in_flow_T_38 = mux(_in_flow_T_5, io.req.`5`.bits.flow.ingress_node_id, UInt<1>(0h0))
node _in_flow_T_39 = mux(_in_flow_T_6, io.req.`6`.bits.flow.ingress_node_id, UInt<1>(0h0))
node _in_flow_T_40 = or(_in_flow_T_33, _in_flow_T_34)
node _in_flow_T_41 = or(_in_flow_T_40, _in_flow_T_35)
node _in_flow_T_42 = or(_in_flow_T_41, _in_flow_T_36)
node _in_flow_T_43 = or(_in_flow_T_42, _in_flow_T_37)
node _in_flow_T_44 = or(_in_flow_T_43, _in_flow_T_38)
node _in_flow_T_45 = or(_in_flow_T_44, _in_flow_T_39)
wire _in_flow_WIRE_2 : UInt<3>
connect _in_flow_WIRE_2, _in_flow_T_45
connect in_flow.ingress_node_id, _in_flow_WIRE_2
node _in_flow_T_46 = mux(_in_flow_T, io.req.`0`.bits.flow.ingress_node, UInt<1>(0h0))
node _in_flow_T_47 = mux(_in_flow_T_1, io.req.`1`.bits.flow.ingress_node, UInt<1>(0h0))
node _in_flow_T_48 = mux(_in_flow_T_2, io.req.`2`.bits.flow.ingress_node, UInt<1>(0h0))
node _in_flow_T_49 = mux(_in_flow_T_3, io.req.`3`.bits.flow.ingress_node, UInt<1>(0h0))
node _in_flow_T_50 = mux(_in_flow_T_4, io.req.`4`.bits.flow.ingress_node, UInt<1>(0h0))
node _in_flow_T_51 = mux(_in_flow_T_5, io.req.`5`.bits.flow.ingress_node, UInt<1>(0h0))
node _in_flow_T_52 = mux(_in_flow_T_6, io.req.`6`.bits.flow.ingress_node, UInt<1>(0h0))
node _in_flow_T_53 = or(_in_flow_T_46, _in_flow_T_47)
node _in_flow_T_54 = or(_in_flow_T_53, _in_flow_T_48)
node _in_flow_T_55 = or(_in_flow_T_54, _in_flow_T_49)
node _in_flow_T_56 = or(_in_flow_T_55, _in_flow_T_50)
node _in_flow_T_57 = or(_in_flow_T_56, _in_flow_T_51)
node _in_flow_T_58 = or(_in_flow_T_57, _in_flow_T_52)
wire _in_flow_WIRE_3 : UInt<4>
connect _in_flow_WIRE_3, _in_flow_T_58
connect in_flow.ingress_node, _in_flow_WIRE_3
node _in_flow_T_59 = mux(_in_flow_T, io.req.`0`.bits.flow.vnet_id, UInt<1>(0h0))
node _in_flow_T_60 = mux(_in_flow_T_1, io.req.`1`.bits.flow.vnet_id, UInt<1>(0h0))
node _in_flow_T_61 = mux(_in_flow_T_2, io.req.`2`.bits.flow.vnet_id, UInt<1>(0h0))
node _in_flow_T_62 = mux(_in_flow_T_3, io.req.`3`.bits.flow.vnet_id, UInt<1>(0h0))
node _in_flow_T_63 = mux(_in_flow_T_4, io.req.`4`.bits.flow.vnet_id, UInt<1>(0h0))
node _in_flow_T_64 = mux(_in_flow_T_5, io.req.`5`.bits.flow.vnet_id, UInt<1>(0h0))
node _in_flow_T_65 = mux(_in_flow_T_6, io.req.`6`.bits.flow.vnet_id, UInt<1>(0h0))
node _in_flow_T_66 = or(_in_flow_T_59, _in_flow_T_60)
node _in_flow_T_67 = or(_in_flow_T_66, _in_flow_T_61)
node _in_flow_T_68 = or(_in_flow_T_67, _in_flow_T_62)
node _in_flow_T_69 = or(_in_flow_T_68, _in_flow_T_63)
node _in_flow_T_70 = or(_in_flow_T_69, _in_flow_T_64)
node _in_flow_T_71 = or(_in_flow_T_70, _in_flow_T_65)
wire _in_flow_WIRE_4 : UInt<2>
connect _in_flow_WIRE_4, _in_flow_T_71
connect in_flow.vnet_id, _in_flow_WIRE_4
node _in_vc_T = bits(in_arb_sel, 0, 0)
node _in_vc_T_1 = bits(in_arb_sel, 1, 1)
node _in_vc_T_2 = bits(in_arb_sel, 2, 2)
node _in_vc_T_3 = bits(in_arb_sel, 3, 3)
node _in_vc_T_4 = bits(in_arb_sel, 4, 4)
node _in_vc_T_5 = bits(in_arb_sel, 5, 5)
node _in_vc_T_6 = bits(in_arb_sel, 6, 6)
node _in_vc_T_7 = mux(_in_vc_T, io.req.`0`.bits.in_vc, UInt<1>(0h0))
node _in_vc_T_8 = mux(_in_vc_T_1, io.req.`1`.bits.in_vc, UInt<1>(0h0))
node _in_vc_T_9 = mux(_in_vc_T_2, io.req.`2`.bits.in_vc, UInt<1>(0h0))
node _in_vc_T_10 = mux(_in_vc_T_3, io.req.`3`.bits.in_vc, UInt<1>(0h0))
node _in_vc_T_11 = mux(_in_vc_T_4, io.req.`4`.bits.in_vc, UInt<1>(0h0))
node _in_vc_T_12 = mux(_in_vc_T_5, io.req.`5`.bits.in_vc, UInt<1>(0h0))
node _in_vc_T_13 = mux(_in_vc_T_6, io.req.`6`.bits.in_vc, UInt<1>(0h0))
node _in_vc_T_14 = or(_in_vc_T_7, _in_vc_T_8)
node _in_vc_T_15 = or(_in_vc_T_14, _in_vc_T_9)
node _in_vc_T_16 = or(_in_vc_T_15, _in_vc_T_10)
node _in_vc_T_17 = or(_in_vc_T_16, _in_vc_T_11)
node _in_vc_T_18 = or(_in_vc_T_17, _in_vc_T_12)
node _in_vc_T_19 = or(_in_vc_T_18, _in_vc_T_13)
wire in_vc : UInt<2>
connect in_vc, _in_vc_T_19
node _in_vc_sel_T = bits(in_arb_sel, 0, 0)
node _in_vc_sel_T_1 = bits(in_arb_sel, 1, 1)
node _in_vc_sel_T_2 = bits(in_arb_sel, 2, 2)
node _in_vc_sel_T_3 = bits(in_arb_sel, 3, 3)
node _in_vc_sel_T_4 = bits(in_arb_sel, 4, 4)
node _in_vc_sel_T_5 = bits(in_arb_sel, 5, 5)
node _in_vc_sel_T_6 = bits(in_arb_sel, 6, 6)
wire in_vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}
wire _in_vc_sel_WIRE : UInt<1>[3]
node _in_vc_sel_T_7 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[0], UInt<1>(0h0))
node _in_vc_sel_T_8 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[0], UInt<1>(0h0))
node _in_vc_sel_T_9 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[0], UInt<1>(0h0))
node _in_vc_sel_T_10 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`0`[0], UInt<1>(0h0))
node _in_vc_sel_T_11 = mux(_in_vc_sel_T_4, in_arb_reqs[4].`0`[0], UInt<1>(0h0))
node _in_vc_sel_T_12 = mux(_in_vc_sel_T_5, in_arb_reqs[5].`0`[0], UInt<1>(0h0))
node _in_vc_sel_T_13 = mux(_in_vc_sel_T_6, in_arb_reqs[6].`0`[0], UInt<1>(0h0))
node _in_vc_sel_T_14 = or(_in_vc_sel_T_7, _in_vc_sel_T_8)
node _in_vc_sel_T_15 = or(_in_vc_sel_T_14, _in_vc_sel_T_9)
node _in_vc_sel_T_16 = or(_in_vc_sel_T_15, _in_vc_sel_T_10)
node _in_vc_sel_T_17 = or(_in_vc_sel_T_16, _in_vc_sel_T_11)
node _in_vc_sel_T_18 = or(_in_vc_sel_T_17, _in_vc_sel_T_12)
node _in_vc_sel_T_19 = or(_in_vc_sel_T_18, _in_vc_sel_T_13)
wire _in_vc_sel_WIRE_1 : UInt<1>
connect _in_vc_sel_WIRE_1, _in_vc_sel_T_19
connect _in_vc_sel_WIRE[0], _in_vc_sel_WIRE_1
node _in_vc_sel_T_20 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[1], UInt<1>(0h0))
node _in_vc_sel_T_21 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[1], UInt<1>(0h0))
node _in_vc_sel_T_22 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[1], UInt<1>(0h0))
node _in_vc_sel_T_23 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`0`[1], UInt<1>(0h0))
node _in_vc_sel_T_24 = mux(_in_vc_sel_T_4, in_arb_reqs[4].`0`[1], UInt<1>(0h0))
node _in_vc_sel_T_25 = mux(_in_vc_sel_T_5, in_arb_reqs[5].`0`[1], UInt<1>(0h0))
node _in_vc_sel_T_26 = mux(_in_vc_sel_T_6, in_arb_reqs[6].`0`[1], UInt<1>(0h0))
node _in_vc_sel_T_27 = or(_in_vc_sel_T_20, _in_vc_sel_T_21)
node _in_vc_sel_T_28 = or(_in_vc_sel_T_27, _in_vc_sel_T_22)
node _in_vc_sel_T_29 = or(_in_vc_sel_T_28, _in_vc_sel_T_23)
node _in_vc_sel_T_30 = or(_in_vc_sel_T_29, _in_vc_sel_T_24)
node _in_vc_sel_T_31 = or(_in_vc_sel_T_30, _in_vc_sel_T_25)
node _in_vc_sel_T_32 = or(_in_vc_sel_T_31, _in_vc_sel_T_26)
wire _in_vc_sel_WIRE_2 : UInt<1>
connect _in_vc_sel_WIRE_2, _in_vc_sel_T_32
connect _in_vc_sel_WIRE[1], _in_vc_sel_WIRE_2
node _in_vc_sel_T_33 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[2], UInt<1>(0h0))
node _in_vc_sel_T_34 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[2], UInt<1>(0h0))
node _in_vc_sel_T_35 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[2], UInt<1>(0h0))
node _in_vc_sel_T_36 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`0`[2], UInt<1>(0h0))
node _in_vc_sel_T_37 = mux(_in_vc_sel_T_4, in_arb_reqs[4].`0`[2], UInt<1>(0h0))
node _in_vc_sel_T_38 = mux(_in_vc_sel_T_5, in_arb_reqs[5].`0`[2], UInt<1>(0h0))
node _in_vc_sel_T_39 = mux(_in_vc_sel_T_6, in_arb_reqs[6].`0`[2], UInt<1>(0h0))
node _in_vc_sel_T_40 = or(_in_vc_sel_T_33, _in_vc_sel_T_34)
node _in_vc_sel_T_41 = or(_in_vc_sel_T_40, _in_vc_sel_T_35)
node _in_vc_sel_T_42 = or(_in_vc_sel_T_41, _in_vc_sel_T_36)
node _in_vc_sel_T_43 = or(_in_vc_sel_T_42, _in_vc_sel_T_37)
node _in_vc_sel_T_44 = or(_in_vc_sel_T_43, _in_vc_sel_T_38)
node _in_vc_sel_T_45 = or(_in_vc_sel_T_44, _in_vc_sel_T_39)
wire _in_vc_sel_WIRE_3 : UInt<1>
connect _in_vc_sel_WIRE_3, _in_vc_sel_T_45
connect _in_vc_sel_WIRE[2], _in_vc_sel_WIRE_3
connect in_vc_sel.`0`, _in_vc_sel_WIRE
wire _in_vc_sel_WIRE_4 : UInt<1>[3]
node _in_vc_sel_T_46 = mux(_in_vc_sel_T, in_arb_reqs[0].`1`[0], UInt<1>(0h0))
node _in_vc_sel_T_47 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`1`[0], UInt<1>(0h0))
node _in_vc_sel_T_48 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`1`[0], UInt<1>(0h0))
node _in_vc_sel_T_49 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`1`[0], UInt<1>(0h0))
node _in_vc_sel_T_50 = mux(_in_vc_sel_T_4, in_arb_reqs[4].`1`[0], UInt<1>(0h0))
node _in_vc_sel_T_51 = mux(_in_vc_sel_T_5, in_arb_reqs[5].`1`[0], UInt<1>(0h0))
node _in_vc_sel_T_52 = mux(_in_vc_sel_T_6, in_arb_reqs[6].`1`[0], UInt<1>(0h0))
node _in_vc_sel_T_53 = or(_in_vc_sel_T_46, _in_vc_sel_T_47)
node _in_vc_sel_T_54 = or(_in_vc_sel_T_53, _in_vc_sel_T_48)
node _in_vc_sel_T_55 = or(_in_vc_sel_T_54, _in_vc_sel_T_49)
node _in_vc_sel_T_56 = or(_in_vc_sel_T_55, _in_vc_sel_T_50)
node _in_vc_sel_T_57 = or(_in_vc_sel_T_56, _in_vc_sel_T_51)
node _in_vc_sel_T_58 = or(_in_vc_sel_T_57, _in_vc_sel_T_52)
wire _in_vc_sel_WIRE_5 : UInt<1>
connect _in_vc_sel_WIRE_5, _in_vc_sel_T_58
connect _in_vc_sel_WIRE_4[0], _in_vc_sel_WIRE_5
node _in_vc_sel_T_59 = mux(_in_vc_sel_T, in_arb_reqs[0].`1`[1], UInt<1>(0h0))
node _in_vc_sel_T_60 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`1`[1], UInt<1>(0h0))
node _in_vc_sel_T_61 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`1`[1], UInt<1>(0h0))
node _in_vc_sel_T_62 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`1`[1], UInt<1>(0h0))
node _in_vc_sel_T_63 = mux(_in_vc_sel_T_4, in_arb_reqs[4].`1`[1], UInt<1>(0h0))
node _in_vc_sel_T_64 = mux(_in_vc_sel_T_5, in_arb_reqs[5].`1`[1], UInt<1>(0h0))
node _in_vc_sel_T_65 = mux(_in_vc_sel_T_6, in_arb_reqs[6].`1`[1], UInt<1>(0h0))
node _in_vc_sel_T_66 = or(_in_vc_sel_T_59, _in_vc_sel_T_60)
node _in_vc_sel_T_67 = or(_in_vc_sel_T_66, _in_vc_sel_T_61)
node _in_vc_sel_T_68 = or(_in_vc_sel_T_67, _in_vc_sel_T_62)
node _in_vc_sel_T_69 = or(_in_vc_sel_T_68, _in_vc_sel_T_63)
node _in_vc_sel_T_70 = or(_in_vc_sel_T_69, _in_vc_sel_T_64)
node _in_vc_sel_T_71 = or(_in_vc_sel_T_70, _in_vc_sel_T_65)
wire _in_vc_sel_WIRE_6 : UInt<1>
connect _in_vc_sel_WIRE_6, _in_vc_sel_T_71
connect _in_vc_sel_WIRE_4[1], _in_vc_sel_WIRE_6
node _in_vc_sel_T_72 = mux(_in_vc_sel_T, in_arb_reqs[0].`1`[2], UInt<1>(0h0))
node _in_vc_sel_T_73 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`1`[2], UInt<1>(0h0))
node _in_vc_sel_T_74 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`1`[2], UInt<1>(0h0))
node _in_vc_sel_T_75 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`1`[2], UInt<1>(0h0))
node _in_vc_sel_T_76 = mux(_in_vc_sel_T_4, in_arb_reqs[4].`1`[2], UInt<1>(0h0))
node _in_vc_sel_T_77 = mux(_in_vc_sel_T_5, in_arb_reqs[5].`1`[2], UInt<1>(0h0))
node _in_vc_sel_T_78 = mux(_in_vc_sel_T_6, in_arb_reqs[6].`1`[2], UInt<1>(0h0))
node _in_vc_sel_T_79 = or(_in_vc_sel_T_72, _in_vc_sel_T_73)
node _in_vc_sel_T_80 = or(_in_vc_sel_T_79, _in_vc_sel_T_74)
node _in_vc_sel_T_81 = or(_in_vc_sel_T_80, _in_vc_sel_T_75)
node _in_vc_sel_T_82 = or(_in_vc_sel_T_81, _in_vc_sel_T_76)
node _in_vc_sel_T_83 = or(_in_vc_sel_T_82, _in_vc_sel_T_77)
node _in_vc_sel_T_84 = or(_in_vc_sel_T_83, _in_vc_sel_T_78)
wire _in_vc_sel_WIRE_7 : UInt<1>
connect _in_vc_sel_WIRE_7, _in_vc_sel_T_84
connect _in_vc_sel_WIRE_4[2], _in_vc_sel_WIRE_7
connect in_vc_sel.`1`, _in_vc_sel_WIRE_4
wire _in_vc_sel_WIRE_8 : UInt<1>[1]
node _in_vc_sel_T_85 = mux(_in_vc_sel_T, in_arb_reqs[0].`2`[0], UInt<1>(0h0))
node _in_vc_sel_T_86 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`2`[0], UInt<1>(0h0))
node _in_vc_sel_T_87 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`2`[0], UInt<1>(0h0))
node _in_vc_sel_T_88 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`2`[0], UInt<1>(0h0))
node _in_vc_sel_T_89 = mux(_in_vc_sel_T_4, in_arb_reqs[4].`2`[0], UInt<1>(0h0))
node _in_vc_sel_T_90 = mux(_in_vc_sel_T_5, in_arb_reqs[5].`2`[0], UInt<1>(0h0))
node _in_vc_sel_T_91 = mux(_in_vc_sel_T_6, in_arb_reqs[6].`2`[0], UInt<1>(0h0))
node _in_vc_sel_T_92 = or(_in_vc_sel_T_85, _in_vc_sel_T_86)
node _in_vc_sel_T_93 = or(_in_vc_sel_T_92, _in_vc_sel_T_87)
node _in_vc_sel_T_94 = or(_in_vc_sel_T_93, _in_vc_sel_T_88)
node _in_vc_sel_T_95 = or(_in_vc_sel_T_94, _in_vc_sel_T_89)
node _in_vc_sel_T_96 = or(_in_vc_sel_T_95, _in_vc_sel_T_90)
node _in_vc_sel_T_97 = or(_in_vc_sel_T_96, _in_vc_sel_T_91)
wire _in_vc_sel_WIRE_9 : UInt<1>
connect _in_vc_sel_WIRE_9, _in_vc_sel_T_97
connect _in_vc_sel_WIRE_8[0], _in_vc_sel_WIRE_9
connect in_vc_sel.`2`, _in_vc_sel_WIRE_8
wire _in_vc_sel_WIRE_10 : UInt<1>[1]
node _in_vc_sel_T_98 = mux(_in_vc_sel_T, in_arb_reqs[0].`3`[0], UInt<1>(0h0))
node _in_vc_sel_T_99 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`3`[0], UInt<1>(0h0))
node _in_vc_sel_T_100 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`3`[0], UInt<1>(0h0))
node _in_vc_sel_T_101 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`3`[0], UInt<1>(0h0))
node _in_vc_sel_T_102 = mux(_in_vc_sel_T_4, in_arb_reqs[4].`3`[0], UInt<1>(0h0))
node _in_vc_sel_T_103 = mux(_in_vc_sel_T_5, in_arb_reqs[5].`3`[0], UInt<1>(0h0))
node _in_vc_sel_T_104 = mux(_in_vc_sel_T_6, in_arb_reqs[6].`3`[0], UInt<1>(0h0))
node _in_vc_sel_T_105 = or(_in_vc_sel_T_98, _in_vc_sel_T_99)
node _in_vc_sel_T_106 = or(_in_vc_sel_T_105, _in_vc_sel_T_100)
node _in_vc_sel_T_107 = or(_in_vc_sel_T_106, _in_vc_sel_T_101)
node _in_vc_sel_T_108 = or(_in_vc_sel_T_107, _in_vc_sel_T_102)
node _in_vc_sel_T_109 = or(_in_vc_sel_T_108, _in_vc_sel_T_103)
node _in_vc_sel_T_110 = or(_in_vc_sel_T_109, _in_vc_sel_T_104)
wire _in_vc_sel_WIRE_11 : UInt<1>
connect _in_vc_sel_WIRE_11, _in_vc_sel_T_110
connect _in_vc_sel_WIRE_10[0], _in_vc_sel_WIRE_11
connect in_vc_sel.`3`, _in_vc_sel_WIRE_10
wire _in_vc_sel_WIRE_12 : UInt<1>[1]
node _in_vc_sel_T_111 = mux(_in_vc_sel_T, in_arb_reqs[0].`4`[0], UInt<1>(0h0))
node _in_vc_sel_T_112 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`4`[0], UInt<1>(0h0))
node _in_vc_sel_T_113 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`4`[0], UInt<1>(0h0))
node _in_vc_sel_T_114 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`4`[0], UInt<1>(0h0))
node _in_vc_sel_T_115 = mux(_in_vc_sel_T_4, in_arb_reqs[4].`4`[0], UInt<1>(0h0))
node _in_vc_sel_T_116 = mux(_in_vc_sel_T_5, in_arb_reqs[5].`4`[0], UInt<1>(0h0))
node _in_vc_sel_T_117 = mux(_in_vc_sel_T_6, in_arb_reqs[6].`4`[0], UInt<1>(0h0))
node _in_vc_sel_T_118 = or(_in_vc_sel_T_111, _in_vc_sel_T_112)
node _in_vc_sel_T_119 = or(_in_vc_sel_T_118, _in_vc_sel_T_113)
node _in_vc_sel_T_120 = or(_in_vc_sel_T_119, _in_vc_sel_T_114)
node _in_vc_sel_T_121 = or(_in_vc_sel_T_120, _in_vc_sel_T_115)
node _in_vc_sel_T_122 = or(_in_vc_sel_T_121, _in_vc_sel_T_116)
node _in_vc_sel_T_123 = or(_in_vc_sel_T_122, _in_vc_sel_T_117)
wire _in_vc_sel_WIRE_13 : UInt<1>
connect _in_vc_sel_WIRE_13, _in_vc_sel_T_123
connect _in_vc_sel_WIRE_12[0], _in_vc_sel_WIRE_13
connect in_vc_sel.`4`, _in_vc_sel_WIRE_12
wire _in_vc_sel_WIRE_14 : UInt<1>[1]
node _in_vc_sel_T_124 = mux(_in_vc_sel_T, in_arb_reqs[0].`5`[0], UInt<1>(0h0))
node _in_vc_sel_T_125 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`5`[0], UInt<1>(0h0))
node _in_vc_sel_T_126 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`5`[0], UInt<1>(0h0))
node _in_vc_sel_T_127 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`5`[0], UInt<1>(0h0))
node _in_vc_sel_T_128 = mux(_in_vc_sel_T_4, in_arb_reqs[4].`5`[0], UInt<1>(0h0))
node _in_vc_sel_T_129 = mux(_in_vc_sel_T_5, in_arb_reqs[5].`5`[0], UInt<1>(0h0))
node _in_vc_sel_T_130 = mux(_in_vc_sel_T_6, in_arb_reqs[6].`5`[0], UInt<1>(0h0))
node _in_vc_sel_T_131 = or(_in_vc_sel_T_124, _in_vc_sel_T_125)
node _in_vc_sel_T_132 = or(_in_vc_sel_T_131, _in_vc_sel_T_126)
node _in_vc_sel_T_133 = or(_in_vc_sel_T_132, _in_vc_sel_T_127)
node _in_vc_sel_T_134 = or(_in_vc_sel_T_133, _in_vc_sel_T_128)
node _in_vc_sel_T_135 = or(_in_vc_sel_T_134, _in_vc_sel_T_129)
node _in_vc_sel_T_136 = or(_in_vc_sel_T_135, _in_vc_sel_T_130)
wire _in_vc_sel_WIRE_15 : UInt<1>
connect _in_vc_sel_WIRE_15, _in_vc_sel_T_136
connect _in_vc_sel_WIRE_14[0], _in_vc_sel_WIRE_15
connect in_vc_sel.`5`, _in_vc_sel_WIRE_14
node _T_6 = or(in_arb_vals[0], in_arb_vals[1])
node _T_7 = or(_T_6, in_arb_vals[2])
node _T_8 = or(_T_7, in_arb_vals[3])
node _T_9 = or(_T_8, in_arb_vals[4])
node _T_10 = or(_T_9, in_arb_vals[5])
node _T_11 = or(_T_10, in_arb_vals[6])
node hi = bits(in_arb_sel, 6, 4)
node lo = bits(in_arb_sel, 3, 0)
node _T_12 = orr(hi)
node _T_13 = or(hi, lo)
node hi_1 = bits(_T_13, 3, 2)
node lo_1 = bits(_T_13, 1, 0)
node _T_14 = orr(hi_1)
node _T_15 = or(hi_1, lo_1)
node _T_16 = bits(_T_15, 1, 1)
node _T_17 = cat(_T_14, _T_16)
node _T_18 = cat(_T_12, _T_17)
node _T_19 = and(io.req.`0`.ready, io.req.`0`.valid)
node _T_20 = and(io.req.`1`.ready, io.req.`1`.valid)
node _T_21 = and(io.req.`2`.ready, io.req.`2`.valid)
node _T_22 = and(io.req.`3`.ready, io.req.`3`.valid)
node _T_23 = and(io.req.`4`.ready, io.req.`4`.valid)
node _T_24 = and(io.req.`5`.ready, io.req.`5`.valid)
node _T_25 = and(io.req.`6`.ready, io.req.`6`.valid)
node _T_26 = or(_T_19, _T_20)
node _T_27 = or(_T_26, _T_21)
node _T_28 = or(_T_27, _T_22)
node _T_29 = or(_T_28, _T_23)
node _T_30 = or(_T_29, _T_24)
node _T_31 = or(_T_30, _T_25)
node hi_2 = cat(in_vc_sel.`0`[2], in_vc_sel.`0`[1])
node _T_32 = cat(hi_2, in_vc_sel.`0`[0])
node hi_3 = cat(in_vc_sel.`1`[2], in_vc_sel.`1`[1])
node _T_33 = cat(hi_3, in_vc_sel.`1`[0])
node lo_hi = cat(in_vc_sel.`2`[0], _T_33)
node lo_2 = cat(lo_hi, _T_32)
node hi_hi = cat(in_vc_sel.`5`[0], in_vc_sel.`4`[0])
node hi_4 = cat(hi_hi, in_vc_sel.`3`[0])
node _T_34 = cat(hi_4, lo_2)
regreset mask_1 : UInt<10>, clock, reset, UInt<10>(0h0)
node _full_T = not(mask_1)
node _full_T_1 = and(_T_34, _full_T)
node full = cat(_T_34, _full_T_1)
node _oh_T = bits(full, 0, 0)
node _oh_T_1 = bits(full, 1, 1)
node _oh_T_2 = bits(full, 2, 2)
node _oh_T_3 = bits(full, 3, 3)
node _oh_T_4 = bits(full, 4, 4)
node _oh_T_5 = bits(full, 5, 5)
node _oh_T_6 = bits(full, 6, 6)
node _oh_T_7 = bits(full, 7, 7)
node _oh_T_8 = bits(full, 8, 8)
node _oh_T_9 = bits(full, 9, 9)
node _oh_T_10 = bits(full, 10, 10)
node _oh_T_11 = bits(full, 11, 11)
node _oh_T_12 = bits(full, 12, 12)
node _oh_T_13 = bits(full, 13, 13)
node _oh_T_14 = bits(full, 14, 14)
node _oh_T_15 = bits(full, 15, 15)
node _oh_T_16 = bits(full, 16, 16)
node _oh_T_17 = bits(full, 17, 17)
node _oh_T_18 = bits(full, 18, 18)
node _oh_T_19 = bits(full, 19, 19)
node _oh_T_20 = mux(_oh_T_19, UInt<20>(0h80000), UInt<20>(0h0))
node _oh_T_21 = mux(_oh_T_18, UInt<20>(0h40000), _oh_T_20)
node _oh_T_22 = mux(_oh_T_17, UInt<20>(0h20000), _oh_T_21)
node _oh_T_23 = mux(_oh_T_16, UInt<20>(0h10000), _oh_T_22)
node _oh_T_24 = mux(_oh_T_15, UInt<20>(0h8000), _oh_T_23)
node _oh_T_25 = mux(_oh_T_14, UInt<20>(0h4000), _oh_T_24)
node _oh_T_26 = mux(_oh_T_13, UInt<20>(0h2000), _oh_T_25)
node _oh_T_27 = mux(_oh_T_12, UInt<20>(0h1000), _oh_T_26)
node _oh_T_28 = mux(_oh_T_11, UInt<20>(0h800), _oh_T_27)
node _oh_T_29 = mux(_oh_T_10, UInt<20>(0h400), _oh_T_28)
node _oh_T_30 = mux(_oh_T_9, UInt<20>(0h200), _oh_T_29)
node _oh_T_31 = mux(_oh_T_8, UInt<20>(0h100), _oh_T_30)
node _oh_T_32 = mux(_oh_T_7, UInt<20>(0h80), _oh_T_31)
node _oh_T_33 = mux(_oh_T_6, UInt<20>(0h40), _oh_T_32)
node _oh_T_34 = mux(_oh_T_5, UInt<20>(0h20), _oh_T_33)
node _oh_T_35 = mux(_oh_T_4, UInt<20>(0h10), _oh_T_34)
node _oh_T_36 = mux(_oh_T_3, UInt<20>(0h8), _oh_T_35)
node _oh_T_37 = mux(_oh_T_2, UInt<20>(0h4), _oh_T_36)
node _oh_T_38 = mux(_oh_T_1, UInt<20>(0h2), _oh_T_37)
node oh = mux(_oh_T, UInt<20>(0h1), _oh_T_38)
node _sel_T = bits(oh, 9, 0)
node _sel_T_1 = shr(oh, 10)
node sel = or(_sel_T, _sel_T_1)
when _T_31 :
node _mask_T_27 = bits(sel, 0, 0)
node _mask_T_28 = not(UInt<1>(0h0))
node _mask_T_29 = bits(sel, 1, 1)
node _mask_T_30 = not(UInt<2>(0h0))
node _mask_T_31 = bits(sel, 2, 2)
node _mask_T_32 = not(UInt<3>(0h0))
node _mask_T_33 = bits(sel, 3, 3)
node _mask_T_34 = not(UInt<4>(0h0))
node _mask_T_35 = bits(sel, 4, 4)
node _mask_T_36 = not(UInt<5>(0h0))
node _mask_T_37 = bits(sel, 5, 5)
node _mask_T_38 = not(UInt<6>(0h0))
node _mask_T_39 = bits(sel, 6, 6)
node _mask_T_40 = not(UInt<7>(0h0))
node _mask_T_41 = bits(sel, 7, 7)
node _mask_T_42 = not(UInt<8>(0h0))
node _mask_T_43 = bits(sel, 8, 8)
node _mask_T_44 = not(UInt<9>(0h0))
node _mask_T_45 = bits(sel, 9, 9)
node _mask_T_46 = not(UInt<10>(0h0))
node _mask_T_47 = mux(_mask_T_45, _mask_T_46, UInt<1>(0h0))
node _mask_T_48 = mux(_mask_T_43, _mask_T_44, _mask_T_47)
node _mask_T_49 = mux(_mask_T_41, _mask_T_42, _mask_T_48)
node _mask_T_50 = mux(_mask_T_39, _mask_T_40, _mask_T_49)
node _mask_T_51 = mux(_mask_T_37, _mask_T_38, _mask_T_50)
node _mask_T_52 = mux(_mask_T_35, _mask_T_36, _mask_T_51)
node _mask_T_53 = mux(_mask_T_33, _mask_T_34, _mask_T_52)
node _mask_T_54 = mux(_mask_T_31, _mask_T_32, _mask_T_53)
node _mask_T_55 = mux(_mask_T_29, _mask_T_30, _mask_T_54)
node _mask_T_56 = mux(_mask_T_27, _mask_T_28, _mask_T_55)
connect mask_1, _mask_T_56
wire _WIRE : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}
wire _WIRE_1 : UInt<10>
connect _WIRE_1, sel
node _T_35 = bits(_WIRE_1, 0, 0)
connect _WIRE.`0`[0], _T_35
node _T_36 = bits(_WIRE_1, 1, 1)
connect _WIRE.`0`[1], _T_36
node _T_37 = bits(_WIRE_1, 2, 2)
connect _WIRE.`0`[2], _T_37
node _T_38 = bits(_WIRE_1, 3, 3)
connect _WIRE.`1`[0], _T_38
node _T_39 = bits(_WIRE_1, 4, 4)
connect _WIRE.`1`[1], _T_39
node _T_40 = bits(_WIRE_1, 5, 5)
connect _WIRE.`1`[2], _T_40
node _T_41 = bits(_WIRE_1, 6, 6)
connect _WIRE.`2`[0], _T_41
node _T_42 = bits(_WIRE_1, 7, 7)
connect _WIRE.`3`[0], _T_42
node _T_43 = bits(_WIRE_1, 8, 8)
connect _WIRE.`4`[0], _T_43
node _T_44 = bits(_WIRE_1, 9, 9)
connect _WIRE.`5`[0], _T_44
wire _WIRE_2 : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}
connect _WIRE_2.`0`[0], UInt<1>(0h0)
connect _WIRE_2.`0`[1], UInt<1>(0h0)
connect _WIRE_2.`0`[2], UInt<1>(0h0)
connect _WIRE_2.`1`[0], UInt<1>(0h0)
connect _WIRE_2.`1`[1], UInt<1>(0h0)
connect _WIRE_2.`1`[2], UInt<1>(0h0)
connect _WIRE_2.`2`[0], UInt<1>(0h0)
connect _WIRE_2.`3`[0], UInt<1>(0h0)
connect _WIRE_2.`4`[0], UInt<1>(0h0)
connect _WIRE_2.`5`[0], UInt<1>(0h0)
node _T_45 = mux(_T_11, _WIRE, _WIRE_2)
connect in_alloc.`0`, _T_45.`0`
connect in_alloc.`1`, _T_45.`1`
connect in_alloc.`2`, _T_45.`2`
connect in_alloc.`3`, _T_45.`3`
connect in_alloc.`4`, _T_45.`4`
connect in_alloc.`5`, _T_45.`5`
node _io_req_0_ready_T = bits(in_arb_sel, 0, 0)
connect io.req.`0`.ready, _io_req_0_ready_T
connect io.resp.`0`.vc_sel.`0`[0], in_alloc.`0`[0]
connect io.resp.`0`.vc_sel.`0`[1], in_alloc.`0`[1]
connect io.resp.`0`.vc_sel.`0`[2], in_alloc.`0`[2]
connect io.resp.`0`.vc_sel.`1`[0], in_alloc.`1`[0]
connect io.resp.`0`.vc_sel.`1`[1], in_alloc.`1`[1]
connect io.resp.`0`.vc_sel.`1`[2], in_alloc.`1`[2]
connect io.resp.`0`.vc_sel.`2`[0], in_alloc.`2`[0]
connect io.resp.`0`.vc_sel.`3`[0], in_alloc.`3`[0]
connect io.resp.`0`.vc_sel.`4`[0], in_alloc.`4`[0]
connect io.resp.`0`.vc_sel.`5`[0], in_alloc.`5`[0]
node hi_5 = cat(io.resp.`0`.vc_sel.`0`[2], io.resp.`0`.vc_sel.`0`[1])
node _T_46 = cat(hi_5, io.resp.`0`.vc_sel.`0`[0])
node hi_6 = cat(io.resp.`0`.vc_sel.`1`[2], io.resp.`0`.vc_sel.`1`[1])
node _T_47 = cat(hi_6, io.resp.`0`.vc_sel.`1`[0])
node lo_hi_1 = cat(io.resp.`0`.vc_sel.`2`[0], _T_47)
node lo_3 = cat(lo_hi_1, _T_46)
node hi_hi_1 = cat(io.resp.`0`.vc_sel.`5`[0], io.resp.`0`.vc_sel.`4`[0])
node hi_7 = cat(hi_hi_1, io.resp.`0`.vc_sel.`3`[0])
node _T_48 = cat(hi_7, lo_3)
node _T_49 = bits(_T_48, 0, 0)
node _T_50 = bits(_T_48, 1, 1)
node _T_51 = bits(_T_48, 2, 2)
node _T_52 = bits(_T_48, 3, 3)
node _T_53 = bits(_T_48, 4, 4)
node _T_54 = bits(_T_48, 5, 5)
node _T_55 = bits(_T_48, 6, 6)
node _T_56 = bits(_T_48, 7, 7)
node _T_57 = bits(_T_48, 8, 8)
node _T_58 = bits(_T_48, 9, 9)
node _T_59 = add(_T_49, _T_50)
node _T_60 = bits(_T_59, 1, 0)
node _T_61 = add(_T_52, _T_53)
node _T_62 = bits(_T_61, 1, 0)
node _T_63 = add(_T_51, _T_62)
node _T_64 = bits(_T_63, 1, 0)
node _T_65 = add(_T_60, _T_64)
node _T_66 = bits(_T_65, 2, 0)
node _T_67 = add(_T_54, _T_55)
node _T_68 = bits(_T_67, 1, 0)
node _T_69 = add(_T_57, _T_58)
node _T_70 = bits(_T_69, 1, 0)
node _T_71 = add(_T_56, _T_70)
node _T_72 = bits(_T_71, 1, 0)
node _T_73 = add(_T_68, _T_72)
node _T_74 = bits(_T_73, 2, 0)
node _T_75 = add(_T_66, _T_74)
node _T_76 = bits(_T_75, 3, 0)
node _T_77 = leq(_T_76, UInt<1>(0h1))
node _T_78 = asUInt(reset)
node _T_79 = eq(_T_78, UInt<1>(0h0))
when _T_79 :
node _T_80 = eq(_T_77, UInt<1>(0h0))
when _T_80 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf
assert(clock, _T_77, UInt<1>(0h1), "") : assert
node _io_req_1_ready_T = bits(in_arb_sel, 1, 1)
connect io.req.`1`.ready, _io_req_1_ready_T
connect io.resp.`1`.vc_sel.`0`[0], in_alloc.`0`[0]
connect io.resp.`1`.vc_sel.`0`[1], in_alloc.`0`[1]
connect io.resp.`1`.vc_sel.`0`[2], in_alloc.`0`[2]
connect io.resp.`1`.vc_sel.`1`[0], in_alloc.`1`[0]
connect io.resp.`1`.vc_sel.`1`[1], in_alloc.`1`[1]
connect io.resp.`1`.vc_sel.`1`[2], in_alloc.`1`[2]
connect io.resp.`1`.vc_sel.`2`[0], in_alloc.`2`[0]
connect io.resp.`1`.vc_sel.`3`[0], in_alloc.`3`[0]
connect io.resp.`1`.vc_sel.`4`[0], in_alloc.`4`[0]
connect io.resp.`1`.vc_sel.`5`[0], in_alloc.`5`[0]
node hi_8 = cat(io.resp.`1`.vc_sel.`0`[2], io.resp.`1`.vc_sel.`0`[1])
node _T_81 = cat(hi_8, io.resp.`1`.vc_sel.`0`[0])
node hi_9 = cat(io.resp.`1`.vc_sel.`1`[2], io.resp.`1`.vc_sel.`1`[1])
node _T_82 = cat(hi_9, io.resp.`1`.vc_sel.`1`[0])
node lo_hi_2 = cat(io.resp.`1`.vc_sel.`2`[0], _T_82)
node lo_4 = cat(lo_hi_2, _T_81)
node hi_hi_2 = cat(io.resp.`1`.vc_sel.`5`[0], io.resp.`1`.vc_sel.`4`[0])
node hi_10 = cat(hi_hi_2, io.resp.`1`.vc_sel.`3`[0])
node _T_83 = cat(hi_10, lo_4)
node _T_84 = bits(_T_83, 0, 0)
node _T_85 = bits(_T_83, 1, 1)
node _T_86 = bits(_T_83, 2, 2)
node _T_87 = bits(_T_83, 3, 3)
node _T_88 = bits(_T_83, 4, 4)
node _T_89 = bits(_T_83, 5, 5)
node _T_90 = bits(_T_83, 6, 6)
node _T_91 = bits(_T_83, 7, 7)
node _T_92 = bits(_T_83, 8, 8)
node _T_93 = bits(_T_83, 9, 9)
node _T_94 = add(_T_84, _T_85)
node _T_95 = bits(_T_94, 1, 0)
node _T_96 = add(_T_87, _T_88)
node _T_97 = bits(_T_96, 1, 0)
node _T_98 = add(_T_86, _T_97)
node _T_99 = bits(_T_98, 1, 0)
node _T_100 = add(_T_95, _T_99)
node _T_101 = bits(_T_100, 2, 0)
node _T_102 = add(_T_89, _T_90)
node _T_103 = bits(_T_102, 1, 0)
node _T_104 = add(_T_92, _T_93)
node _T_105 = bits(_T_104, 1, 0)
node _T_106 = add(_T_91, _T_105)
node _T_107 = bits(_T_106, 1, 0)
node _T_108 = add(_T_103, _T_107)
node _T_109 = bits(_T_108, 2, 0)
node _T_110 = add(_T_101, _T_109)
node _T_111 = bits(_T_110, 3, 0)
node _T_112 = leq(_T_111, UInt<1>(0h1))
node _T_113 = asUInt(reset)
node _T_114 = eq(_T_113, UInt<1>(0h0))
when _T_114 :
node _T_115 = eq(_T_112, UInt<1>(0h0))
when _T_115 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf_1
assert(clock, _T_112, UInt<1>(0h1), "") : assert_1
node _io_req_2_ready_T = bits(in_arb_sel, 2, 2)
connect io.req.`2`.ready, _io_req_2_ready_T
connect io.resp.`2`.vc_sel.`0`[0], in_alloc.`0`[0]
connect io.resp.`2`.vc_sel.`0`[1], in_alloc.`0`[1]
connect io.resp.`2`.vc_sel.`0`[2], in_alloc.`0`[2]
connect io.resp.`2`.vc_sel.`1`[0], in_alloc.`1`[0]
connect io.resp.`2`.vc_sel.`1`[1], in_alloc.`1`[1]
connect io.resp.`2`.vc_sel.`1`[2], in_alloc.`1`[2]
connect io.resp.`2`.vc_sel.`2`[0], in_alloc.`2`[0]
connect io.resp.`2`.vc_sel.`3`[0], in_alloc.`3`[0]
connect io.resp.`2`.vc_sel.`4`[0], in_alloc.`4`[0]
connect io.resp.`2`.vc_sel.`5`[0], in_alloc.`5`[0]
node hi_11 = cat(io.resp.`2`.vc_sel.`0`[2], io.resp.`2`.vc_sel.`0`[1])
node _T_116 = cat(hi_11, io.resp.`2`.vc_sel.`0`[0])
node hi_12 = cat(io.resp.`2`.vc_sel.`1`[2], io.resp.`2`.vc_sel.`1`[1])
node _T_117 = cat(hi_12, io.resp.`2`.vc_sel.`1`[0])
node lo_hi_3 = cat(io.resp.`2`.vc_sel.`2`[0], _T_117)
node lo_5 = cat(lo_hi_3, _T_116)
node hi_hi_3 = cat(io.resp.`2`.vc_sel.`5`[0], io.resp.`2`.vc_sel.`4`[0])
node hi_13 = cat(hi_hi_3, io.resp.`2`.vc_sel.`3`[0])
node _T_118 = cat(hi_13, lo_5)
node _T_119 = bits(_T_118, 0, 0)
node _T_120 = bits(_T_118, 1, 1)
node _T_121 = bits(_T_118, 2, 2)
node _T_122 = bits(_T_118, 3, 3)
node _T_123 = bits(_T_118, 4, 4)
node _T_124 = bits(_T_118, 5, 5)
node _T_125 = bits(_T_118, 6, 6)
node _T_126 = bits(_T_118, 7, 7)
node _T_127 = bits(_T_118, 8, 8)
node _T_128 = bits(_T_118, 9, 9)
node _T_129 = add(_T_119, _T_120)
node _T_130 = bits(_T_129, 1, 0)
node _T_131 = add(_T_122, _T_123)
node _T_132 = bits(_T_131, 1, 0)
node _T_133 = add(_T_121, _T_132)
node _T_134 = bits(_T_133, 1, 0)
node _T_135 = add(_T_130, _T_134)
node _T_136 = bits(_T_135, 2, 0)
node _T_137 = add(_T_124, _T_125)
node _T_138 = bits(_T_137, 1, 0)
node _T_139 = add(_T_127, _T_128)
node _T_140 = bits(_T_139, 1, 0)
node _T_141 = add(_T_126, _T_140)
node _T_142 = bits(_T_141, 1, 0)
node _T_143 = add(_T_138, _T_142)
node _T_144 = bits(_T_143, 2, 0)
node _T_145 = add(_T_136, _T_144)
node _T_146 = bits(_T_145, 3, 0)
node _T_147 = leq(_T_146, UInt<1>(0h1))
node _T_148 = asUInt(reset)
node _T_149 = eq(_T_148, UInt<1>(0h0))
when _T_149 :
node _T_150 = eq(_T_147, UInt<1>(0h0))
when _T_150 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf_2
assert(clock, _T_147, UInt<1>(0h1), "") : assert_2
node _io_req_3_ready_T = bits(in_arb_sel, 3, 3)
connect io.req.`3`.ready, _io_req_3_ready_T
connect io.resp.`3`.vc_sel.`0`[0], in_alloc.`0`[0]
connect io.resp.`3`.vc_sel.`0`[1], in_alloc.`0`[1]
connect io.resp.`3`.vc_sel.`0`[2], in_alloc.`0`[2]
connect io.resp.`3`.vc_sel.`1`[0], in_alloc.`1`[0]
connect io.resp.`3`.vc_sel.`1`[1], in_alloc.`1`[1]
connect io.resp.`3`.vc_sel.`1`[2], in_alloc.`1`[2]
connect io.resp.`3`.vc_sel.`2`[0], in_alloc.`2`[0]
connect io.resp.`3`.vc_sel.`3`[0], in_alloc.`3`[0]
connect io.resp.`3`.vc_sel.`4`[0], in_alloc.`4`[0]
connect io.resp.`3`.vc_sel.`5`[0], in_alloc.`5`[0]
node hi_14 = cat(io.resp.`3`.vc_sel.`0`[2], io.resp.`3`.vc_sel.`0`[1])
node _T_151 = cat(hi_14, io.resp.`3`.vc_sel.`0`[0])
node hi_15 = cat(io.resp.`3`.vc_sel.`1`[2], io.resp.`3`.vc_sel.`1`[1])
node _T_152 = cat(hi_15, io.resp.`3`.vc_sel.`1`[0])
node lo_hi_4 = cat(io.resp.`3`.vc_sel.`2`[0], _T_152)
node lo_6 = cat(lo_hi_4, _T_151)
node hi_hi_4 = cat(io.resp.`3`.vc_sel.`5`[0], io.resp.`3`.vc_sel.`4`[0])
node hi_16 = cat(hi_hi_4, io.resp.`3`.vc_sel.`3`[0])
node _T_153 = cat(hi_16, lo_6)
node _T_154 = bits(_T_153, 0, 0)
node _T_155 = bits(_T_153, 1, 1)
node _T_156 = bits(_T_153, 2, 2)
node _T_157 = bits(_T_153, 3, 3)
node _T_158 = bits(_T_153, 4, 4)
node _T_159 = bits(_T_153, 5, 5)
node _T_160 = bits(_T_153, 6, 6)
node _T_161 = bits(_T_153, 7, 7)
node _T_162 = bits(_T_153, 8, 8)
node _T_163 = bits(_T_153, 9, 9)
node _T_164 = add(_T_154, _T_155)
node _T_165 = bits(_T_164, 1, 0)
node _T_166 = add(_T_157, _T_158)
node _T_167 = bits(_T_166, 1, 0)
node _T_168 = add(_T_156, _T_167)
node _T_169 = bits(_T_168, 1, 0)
node _T_170 = add(_T_165, _T_169)
node _T_171 = bits(_T_170, 2, 0)
node _T_172 = add(_T_159, _T_160)
node _T_173 = bits(_T_172, 1, 0)
node _T_174 = add(_T_162, _T_163)
node _T_175 = bits(_T_174, 1, 0)
node _T_176 = add(_T_161, _T_175)
node _T_177 = bits(_T_176, 1, 0)
node _T_178 = add(_T_173, _T_177)
node _T_179 = bits(_T_178, 2, 0)
node _T_180 = add(_T_171, _T_179)
node _T_181 = bits(_T_180, 3, 0)
node _T_182 = leq(_T_181, UInt<1>(0h1))
node _T_183 = asUInt(reset)
node _T_184 = eq(_T_183, UInt<1>(0h0))
when _T_184 :
node _T_185 = eq(_T_182, UInt<1>(0h0))
when _T_185 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf_3
assert(clock, _T_182, UInt<1>(0h1), "") : assert_3
node _io_req_4_ready_T = bits(in_arb_sel, 4, 4)
connect io.req.`4`.ready, _io_req_4_ready_T
connect io.resp.`4`.vc_sel.`0`[0], in_alloc.`0`[0]
connect io.resp.`4`.vc_sel.`0`[1], in_alloc.`0`[1]
connect io.resp.`4`.vc_sel.`0`[2], in_alloc.`0`[2]
connect io.resp.`4`.vc_sel.`1`[0], in_alloc.`1`[0]
connect io.resp.`4`.vc_sel.`1`[1], in_alloc.`1`[1]
connect io.resp.`4`.vc_sel.`1`[2], in_alloc.`1`[2]
connect io.resp.`4`.vc_sel.`2`[0], in_alloc.`2`[0]
connect io.resp.`4`.vc_sel.`3`[0], in_alloc.`3`[0]
connect io.resp.`4`.vc_sel.`4`[0], in_alloc.`4`[0]
connect io.resp.`4`.vc_sel.`5`[0], in_alloc.`5`[0]
node hi_17 = cat(io.resp.`4`.vc_sel.`0`[2], io.resp.`4`.vc_sel.`0`[1])
node _T_186 = cat(hi_17, io.resp.`4`.vc_sel.`0`[0])
node hi_18 = cat(io.resp.`4`.vc_sel.`1`[2], io.resp.`4`.vc_sel.`1`[1])
node _T_187 = cat(hi_18, io.resp.`4`.vc_sel.`1`[0])
node lo_hi_5 = cat(io.resp.`4`.vc_sel.`2`[0], _T_187)
node lo_7 = cat(lo_hi_5, _T_186)
node hi_hi_5 = cat(io.resp.`4`.vc_sel.`5`[0], io.resp.`4`.vc_sel.`4`[0])
node hi_19 = cat(hi_hi_5, io.resp.`4`.vc_sel.`3`[0])
node _T_188 = cat(hi_19, lo_7)
node _T_189 = bits(_T_188, 0, 0)
node _T_190 = bits(_T_188, 1, 1)
node _T_191 = bits(_T_188, 2, 2)
node _T_192 = bits(_T_188, 3, 3)
node _T_193 = bits(_T_188, 4, 4)
node _T_194 = bits(_T_188, 5, 5)
node _T_195 = bits(_T_188, 6, 6)
node _T_196 = bits(_T_188, 7, 7)
node _T_197 = bits(_T_188, 8, 8)
node _T_198 = bits(_T_188, 9, 9)
node _T_199 = add(_T_189, _T_190)
node _T_200 = bits(_T_199, 1, 0)
node _T_201 = add(_T_192, _T_193)
node _T_202 = bits(_T_201, 1, 0)
node _T_203 = add(_T_191, _T_202)
node _T_204 = bits(_T_203, 1, 0)
node _T_205 = add(_T_200, _T_204)
node _T_206 = bits(_T_205, 2, 0)
node _T_207 = add(_T_194, _T_195)
node _T_208 = bits(_T_207, 1, 0)
node _T_209 = add(_T_197, _T_198)
node _T_210 = bits(_T_209, 1, 0)
node _T_211 = add(_T_196, _T_210)
node _T_212 = bits(_T_211, 1, 0)
node _T_213 = add(_T_208, _T_212)
node _T_214 = bits(_T_213, 2, 0)
node _T_215 = add(_T_206, _T_214)
node _T_216 = bits(_T_215, 3, 0)
node _T_217 = leq(_T_216, UInt<1>(0h1))
node _T_218 = asUInt(reset)
node _T_219 = eq(_T_218, UInt<1>(0h0))
when _T_219 :
node _T_220 = eq(_T_217, UInt<1>(0h0))
when _T_220 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf_4
assert(clock, _T_217, UInt<1>(0h1), "") : assert_4
node _io_req_5_ready_T = bits(in_arb_sel, 5, 5)
connect io.req.`5`.ready, _io_req_5_ready_T
connect io.resp.`5`.vc_sel.`0`[0], in_alloc.`0`[0]
connect io.resp.`5`.vc_sel.`0`[1], in_alloc.`0`[1]
connect io.resp.`5`.vc_sel.`0`[2], in_alloc.`0`[2]
connect io.resp.`5`.vc_sel.`1`[0], in_alloc.`1`[0]
connect io.resp.`5`.vc_sel.`1`[1], in_alloc.`1`[1]
connect io.resp.`5`.vc_sel.`1`[2], in_alloc.`1`[2]
connect io.resp.`5`.vc_sel.`2`[0], in_alloc.`2`[0]
connect io.resp.`5`.vc_sel.`3`[0], in_alloc.`3`[0]
connect io.resp.`5`.vc_sel.`4`[0], in_alloc.`4`[0]
connect io.resp.`5`.vc_sel.`5`[0], in_alloc.`5`[0]
node hi_20 = cat(io.resp.`5`.vc_sel.`0`[2], io.resp.`5`.vc_sel.`0`[1])
node _T_221 = cat(hi_20, io.resp.`5`.vc_sel.`0`[0])
node hi_21 = cat(io.resp.`5`.vc_sel.`1`[2], io.resp.`5`.vc_sel.`1`[1])
node _T_222 = cat(hi_21, io.resp.`5`.vc_sel.`1`[0])
node lo_hi_6 = cat(io.resp.`5`.vc_sel.`2`[0], _T_222)
node lo_8 = cat(lo_hi_6, _T_221)
node hi_hi_6 = cat(io.resp.`5`.vc_sel.`5`[0], io.resp.`5`.vc_sel.`4`[0])
node hi_22 = cat(hi_hi_6, io.resp.`5`.vc_sel.`3`[0])
node _T_223 = cat(hi_22, lo_8)
node _T_224 = bits(_T_223, 0, 0)
node _T_225 = bits(_T_223, 1, 1)
node _T_226 = bits(_T_223, 2, 2)
node _T_227 = bits(_T_223, 3, 3)
node _T_228 = bits(_T_223, 4, 4)
node _T_229 = bits(_T_223, 5, 5)
node _T_230 = bits(_T_223, 6, 6)
node _T_231 = bits(_T_223, 7, 7)
node _T_232 = bits(_T_223, 8, 8)
node _T_233 = bits(_T_223, 9, 9)
node _T_234 = add(_T_224, _T_225)
node _T_235 = bits(_T_234, 1, 0)
node _T_236 = add(_T_227, _T_228)
node _T_237 = bits(_T_236, 1, 0)
node _T_238 = add(_T_226, _T_237)
node _T_239 = bits(_T_238, 1, 0)
node _T_240 = add(_T_235, _T_239)
node _T_241 = bits(_T_240, 2, 0)
node _T_242 = add(_T_229, _T_230)
node _T_243 = bits(_T_242, 1, 0)
node _T_244 = add(_T_232, _T_233)
node _T_245 = bits(_T_244, 1, 0)
node _T_246 = add(_T_231, _T_245)
node _T_247 = bits(_T_246, 1, 0)
node _T_248 = add(_T_243, _T_247)
node _T_249 = bits(_T_248, 2, 0)
node _T_250 = add(_T_241, _T_249)
node _T_251 = bits(_T_250, 3, 0)
node _T_252 = leq(_T_251, UInt<1>(0h1))
node _T_253 = asUInt(reset)
node _T_254 = eq(_T_253, UInt<1>(0h0))
when _T_254 :
node _T_255 = eq(_T_252, UInt<1>(0h0))
when _T_255 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf_5
assert(clock, _T_252, UInt<1>(0h1), "") : assert_5
node _io_req_6_ready_T = bits(in_arb_sel, 6, 6)
connect io.req.`6`.ready, _io_req_6_ready_T
connect io.resp.`6`.vc_sel.`0`[0], in_alloc.`0`[0]
connect io.resp.`6`.vc_sel.`0`[1], in_alloc.`0`[1]
connect io.resp.`6`.vc_sel.`0`[2], in_alloc.`0`[2]
connect io.resp.`6`.vc_sel.`1`[0], in_alloc.`1`[0]
connect io.resp.`6`.vc_sel.`1`[1], in_alloc.`1`[1]
connect io.resp.`6`.vc_sel.`1`[2], in_alloc.`1`[2]
connect io.resp.`6`.vc_sel.`2`[0], in_alloc.`2`[0]
connect io.resp.`6`.vc_sel.`3`[0], in_alloc.`3`[0]
connect io.resp.`6`.vc_sel.`4`[0], in_alloc.`4`[0]
connect io.resp.`6`.vc_sel.`5`[0], in_alloc.`5`[0]
node hi_23 = cat(io.resp.`6`.vc_sel.`0`[2], io.resp.`6`.vc_sel.`0`[1])
node _T_256 = cat(hi_23, io.resp.`6`.vc_sel.`0`[0])
node hi_24 = cat(io.resp.`6`.vc_sel.`1`[2], io.resp.`6`.vc_sel.`1`[1])
node _T_257 = cat(hi_24, io.resp.`6`.vc_sel.`1`[0])
node lo_hi_7 = cat(io.resp.`6`.vc_sel.`2`[0], _T_257)
node lo_9 = cat(lo_hi_7, _T_256)
node hi_hi_7 = cat(io.resp.`6`.vc_sel.`5`[0], io.resp.`6`.vc_sel.`4`[0])
node hi_25 = cat(hi_hi_7, io.resp.`6`.vc_sel.`3`[0])
node _T_258 = cat(hi_25, lo_9)
node _T_259 = bits(_T_258, 0, 0)
node _T_260 = bits(_T_258, 1, 1)
node _T_261 = bits(_T_258, 2, 2)
node _T_262 = bits(_T_258, 3, 3)
node _T_263 = bits(_T_258, 4, 4)
node _T_264 = bits(_T_258, 5, 5)
node _T_265 = bits(_T_258, 6, 6)
node _T_266 = bits(_T_258, 7, 7)
node _T_267 = bits(_T_258, 8, 8)
node _T_268 = bits(_T_258, 9, 9)
node _T_269 = add(_T_259, _T_260)
node _T_270 = bits(_T_269, 1, 0)
node _T_271 = add(_T_262, _T_263)
node _T_272 = bits(_T_271, 1, 0)
node _T_273 = add(_T_261, _T_272)
node _T_274 = bits(_T_273, 1, 0)
node _T_275 = add(_T_270, _T_274)
node _T_276 = bits(_T_275, 2, 0)
node _T_277 = add(_T_264, _T_265)
node _T_278 = bits(_T_277, 1, 0)
node _T_279 = add(_T_267, _T_268)
node _T_280 = bits(_T_279, 1, 0)
node _T_281 = add(_T_266, _T_280)
node _T_282 = bits(_T_281, 1, 0)
node _T_283 = add(_T_278, _T_282)
node _T_284 = bits(_T_283, 2, 0)
node _T_285 = add(_T_276, _T_284)
node _T_286 = bits(_T_285, 3, 0)
node _T_287 = leq(_T_286, UInt<1>(0h1))
node _T_288 = asUInt(reset)
node _T_289 = eq(_T_288, UInt<1>(0h0))
when _T_289 :
node _T_290 = eq(_T_287, UInt<1>(0h0))
when _T_290 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf_6
assert(clock, _T_287, UInt<1>(0h1), "") : assert_6
connect io.out_allocs.`0`[0].alloc, in_alloc.`0`[0]
connect io.out_allocs.`0`[0].flow, in_flow
connect io.out_allocs.`0`[1].alloc, in_alloc.`0`[1]
connect io.out_allocs.`0`[1].flow, in_flow
connect io.out_allocs.`0`[2].alloc, in_alloc.`0`[2]
connect io.out_allocs.`0`[2].flow, in_flow
connect io.out_allocs.`1`[0].alloc, in_alloc.`1`[0]
connect io.out_allocs.`1`[0].flow, in_flow
connect io.out_allocs.`1`[1].alloc, in_alloc.`1`[1]
connect io.out_allocs.`1`[1].flow, in_flow
connect io.out_allocs.`1`[2].alloc, in_alloc.`1`[2]
connect io.out_allocs.`1`[2].flow, in_flow
connect io.out_allocs.`2`[0].alloc, in_alloc.`2`[0]
connect io.out_allocs.`2`[0].flow, in_flow
connect io.out_allocs.`3`[0].alloc, in_alloc.`3`[0]
connect io.out_allocs.`3`[0].flow, in_flow
connect io.out_allocs.`4`[0].alloc, in_alloc.`4`[0]
connect io.out_allocs.`4`[0].flow, in_flow
connect io.out_allocs.`5`[0].alloc, in_alloc.`5`[0]
connect io.out_allocs.`5`[0].flow, in_flow | module RotatingSingleVCAllocator( // @[ISLIP.scala:43:7]
input clock, // @[ISLIP.scala:43:7]
input reset, // @[ISLIP.scala:43:7]
output io_req_6_ready, // @[VCAllocator.scala:49:14]
input io_req_6_valid, // @[VCAllocator.scala:49:14]
input io_req_6_bits_vc_sel_5_0, // @[VCAllocator.scala:49:14]
input io_req_6_bits_vc_sel_4_0, // @[VCAllocator.scala:49:14]
input io_req_6_bits_vc_sel_3_0, // @[VCAllocator.scala:49:14]
input io_req_6_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14]
input io_req_6_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14]
input io_req_6_bits_vc_sel_1_1, // @[VCAllocator.scala:49:14]
input io_req_6_bits_vc_sel_1_2, // @[VCAllocator.scala:49:14]
input io_req_6_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14]
input io_req_6_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14]
input io_req_6_bits_vc_sel_0_2, // @[VCAllocator.scala:49:14]
output io_req_5_ready, // @[VCAllocator.scala:49:14]
input io_req_5_valid, // @[VCAllocator.scala:49:14]
input io_req_5_bits_vc_sel_5_0, // @[VCAllocator.scala:49:14]
input io_req_5_bits_vc_sel_4_0, // @[VCAllocator.scala:49:14]
input io_req_5_bits_vc_sel_3_0, // @[VCAllocator.scala:49:14]
input io_req_5_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14]
input io_req_5_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14]
input io_req_5_bits_vc_sel_1_1, // @[VCAllocator.scala:49:14]
input io_req_5_bits_vc_sel_1_2, // @[VCAllocator.scala:49:14]
input io_req_5_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14]
input io_req_5_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14]
input io_req_5_bits_vc_sel_0_2, // @[VCAllocator.scala:49:14]
output io_req_4_ready, // @[VCAllocator.scala:49:14]
input io_req_4_valid, // @[VCAllocator.scala:49:14]
input io_req_4_bits_vc_sel_5_0, // @[VCAllocator.scala:49:14]
input io_req_4_bits_vc_sel_4_0, // @[VCAllocator.scala:49:14]
input io_req_4_bits_vc_sel_3_0, // @[VCAllocator.scala:49:14]
input io_req_4_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14]
input io_req_4_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14]
input io_req_4_bits_vc_sel_1_1, // @[VCAllocator.scala:49:14]
input io_req_4_bits_vc_sel_1_2, // @[VCAllocator.scala:49:14]
input io_req_4_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14]
input io_req_4_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14]
input io_req_4_bits_vc_sel_0_2, // @[VCAllocator.scala:49:14]
output io_req_2_ready, // @[VCAllocator.scala:49:14]
input io_req_2_valid, // @[VCAllocator.scala:49:14]
input io_req_2_bits_vc_sel_5_0, // @[VCAllocator.scala:49:14]
input io_req_2_bits_vc_sel_4_0, // @[VCAllocator.scala:49:14]
input io_req_2_bits_vc_sel_3_0, // @[VCAllocator.scala:49:14]
input io_req_2_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14]
input io_req_2_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14]
input io_req_2_bits_vc_sel_1_1, // @[VCAllocator.scala:49:14]
input io_req_2_bits_vc_sel_1_2, // @[VCAllocator.scala:49:14]
input io_req_2_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14]
input io_req_2_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14]
input io_req_2_bits_vc_sel_0_2, // @[VCAllocator.scala:49:14]
output io_req_1_ready, // @[VCAllocator.scala:49:14]
input io_req_1_valid, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_5_0, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_4_0, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_3_0, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14]
output io_req_0_ready, // @[VCAllocator.scala:49:14]
input io_req_0_valid, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_5_0, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_4_0, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_3_0, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14]
output io_resp_6_vc_sel_5_0, // @[VCAllocator.scala:49:14]
output io_resp_6_vc_sel_4_0, // @[VCAllocator.scala:49:14]
output io_resp_6_vc_sel_3_0, // @[VCAllocator.scala:49:14]
output io_resp_6_vc_sel_2_0, // @[VCAllocator.scala:49:14]
output io_resp_6_vc_sel_1_0, // @[VCAllocator.scala:49:14]
output io_resp_6_vc_sel_1_1, // @[VCAllocator.scala:49:14]
output io_resp_6_vc_sel_1_2, // @[VCAllocator.scala:49:14]
output io_resp_6_vc_sel_0_0, // @[VCAllocator.scala:49:14]
output io_resp_6_vc_sel_0_1, // @[VCAllocator.scala:49:14]
output io_resp_6_vc_sel_0_2, // @[VCAllocator.scala:49:14]
output io_resp_5_vc_sel_5_0, // @[VCAllocator.scala:49:14]
output io_resp_5_vc_sel_4_0, // @[VCAllocator.scala:49:14]
output io_resp_5_vc_sel_3_0, // @[VCAllocator.scala:49:14]
output io_resp_5_vc_sel_2_0, // @[VCAllocator.scala:49:14]
output io_resp_5_vc_sel_1_0, // @[VCAllocator.scala:49:14]
output io_resp_5_vc_sel_1_1, // @[VCAllocator.scala:49:14]
output io_resp_5_vc_sel_1_2, // @[VCAllocator.scala:49:14]
output io_resp_5_vc_sel_0_0, // @[VCAllocator.scala:49:14]
output io_resp_5_vc_sel_0_1, // @[VCAllocator.scala:49:14]
output io_resp_5_vc_sel_0_2, // @[VCAllocator.scala:49:14]
output io_resp_4_vc_sel_5_0, // @[VCAllocator.scala:49:14]
output io_resp_4_vc_sel_4_0, // @[VCAllocator.scala:49:14]
output io_resp_4_vc_sel_3_0, // @[VCAllocator.scala:49:14]
output io_resp_4_vc_sel_2_0, // @[VCAllocator.scala:49:14]
output io_resp_4_vc_sel_1_0, // @[VCAllocator.scala:49:14]
output io_resp_4_vc_sel_1_1, // @[VCAllocator.scala:49:14]
output io_resp_4_vc_sel_1_2, // @[VCAllocator.scala:49:14]
output io_resp_4_vc_sel_0_0, // @[VCAllocator.scala:49:14]
output io_resp_4_vc_sel_0_1, // @[VCAllocator.scala:49:14]
output io_resp_4_vc_sel_0_2, // @[VCAllocator.scala:49:14]
output io_resp_2_vc_sel_5_0, // @[VCAllocator.scala:49:14]
output io_resp_2_vc_sel_4_0, // @[VCAllocator.scala:49:14]
output io_resp_2_vc_sel_3_0, // @[VCAllocator.scala:49:14]
output io_resp_2_vc_sel_2_0, // @[VCAllocator.scala:49:14]
output io_resp_2_vc_sel_1_0, // @[VCAllocator.scala:49:14]
output io_resp_2_vc_sel_1_1, // @[VCAllocator.scala:49:14]
output io_resp_2_vc_sel_1_2, // @[VCAllocator.scala:49:14]
output io_resp_2_vc_sel_0_0, // @[VCAllocator.scala:49:14]
output io_resp_2_vc_sel_0_1, // @[VCAllocator.scala:49:14]
output io_resp_2_vc_sel_0_2, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_5_0, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_4_0, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_3_0, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_2_0, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_5_0, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_4_0, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_3_0, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_2_0, // @[VCAllocator.scala:49:14]
input io_channel_status_5_0_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_4_0_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_3_0_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_2_0_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_1_0_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_0_0_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_0_1_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_0_2_occupied, // @[VCAllocator.scala:49:14]
output io_out_allocs_5_0_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_4_0_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_3_0_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_2_0_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_1_0_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_0_0_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_0_1_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_0_2_alloc // @[VCAllocator.scala:49:14]
);
wire in_arb_vals_6; // @[SingleVCAllocator.scala:32:39]
wire in_arb_vals_5; // @[SingleVCAllocator.scala:32:39]
wire in_arb_vals_4; // @[SingleVCAllocator.scala:32:39]
wire in_arb_vals_2; // @[SingleVCAllocator.scala:32:39]
wire in_arb_vals_1; // @[SingleVCAllocator.scala:32:39]
wire in_arb_vals_0; // @[SingleVCAllocator.scala:32:39]
reg [6:0] mask; // @[SingleVCAllocator.scala:16:21]
wire [6:0] _in_arb_filter_T_3 = {in_arb_vals_6, in_arb_vals_5, in_arb_vals_4, 1'h0, in_arb_vals_2, in_arb_vals_1, in_arb_vals_0} & ~mask; // @[SingleVCAllocator.scala:16:21, :19:{77,84,86}, :32:39]
wire [13:0] in_arb_filter = _in_arb_filter_T_3[0] ? 14'h1 : _in_arb_filter_T_3[1] ? 14'h2 : _in_arb_filter_T_3[2] ? 14'h4 : _in_arb_filter_T_3[3] ? 14'h8 : _in_arb_filter_T_3[4] ? 14'h10 : _in_arb_filter_T_3[5] ? 14'h20 : _in_arb_filter_T_3[6] ? 14'h40 : in_arb_vals_0 ? 14'h80 : in_arb_vals_1 ? 14'h100 : in_arb_vals_2 ? 14'h200 : in_arb_vals_4 ? 14'h800 : in_arb_vals_5 ? 14'h1000 : {in_arb_vals_6, 13'h0}; // @[OneHot.scala:85:71]
wire [6:0] in_arb_sel = in_arb_filter[6:0] | in_arb_filter[13:7]; // @[Mux.scala:50:70]
wire _GEN = in_arb_vals_0 | in_arb_vals_1 | in_arb_vals_2 | in_arb_vals_4 | in_arb_vals_5 | in_arb_vals_6; // @[package.scala:81:59]
wire in_arb_reqs_0_2_0 = io_req_0_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_3_0 = io_req_0_bits_vc_sel_3_0 & ~io_channel_status_3_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_4_0 = io_req_0_bits_vc_sel_4_0 & ~io_channel_status_4_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_5_0 = io_req_0_bits_vc_sel_5_0 & ~io_channel_status_5_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
assign in_arb_vals_0 = io_req_0_valid & (in_arb_reqs_0_2_0 | in_arb_reqs_0_3_0 | in_arb_reqs_0_4_0 | in_arb_reqs_0_5_0); // @[package.scala:81:59]
wire in_arb_reqs_1_2_0 = io_req_1_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_3_0 = io_req_1_bits_vc_sel_3_0 & ~io_channel_status_3_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_4_0 = io_req_1_bits_vc_sel_4_0 & ~io_channel_status_4_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_5_0 = io_req_1_bits_vc_sel_5_0 & ~io_channel_status_5_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
assign in_arb_vals_1 = io_req_1_valid & (in_arb_reqs_1_2_0 | in_arb_reqs_1_3_0 | in_arb_reqs_1_4_0 | in_arb_reqs_1_5_0); // @[package.scala:81:59]
wire in_arb_reqs_2_0_0 = io_req_2_bits_vc_sel_0_0 & ~io_channel_status_0_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_2_0_1 = io_req_2_bits_vc_sel_0_1 & ~io_channel_status_0_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_2_0_2 = io_req_2_bits_vc_sel_0_2 & ~io_channel_status_0_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_2_1_0 = io_req_2_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_2_2_0 = io_req_2_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_2_3_0 = io_req_2_bits_vc_sel_3_0 & ~io_channel_status_3_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_2_4_0 = io_req_2_bits_vc_sel_4_0 & ~io_channel_status_4_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_2_5_0 = io_req_2_bits_vc_sel_5_0 & ~io_channel_status_5_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
assign in_arb_vals_2 = io_req_2_valid & (in_arb_reqs_2_0_0 | in_arb_reqs_2_0_1 | in_arb_reqs_2_0_2 | in_arb_reqs_2_1_0 | io_req_2_bits_vc_sel_1_1 | io_req_2_bits_vc_sel_1_2 | in_arb_reqs_2_2_0 | in_arb_reqs_2_3_0 | in_arb_reqs_2_4_0 | in_arb_reqs_2_5_0); // @[package.scala:81:59]
wire in_arb_reqs_4_0_0 = io_req_4_bits_vc_sel_0_0 & ~io_channel_status_0_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_4_0_1 = io_req_4_bits_vc_sel_0_1 & ~io_channel_status_0_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_4_0_2 = io_req_4_bits_vc_sel_0_2 & ~io_channel_status_0_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_4_1_0 = io_req_4_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_4_2_0 = io_req_4_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_4_3_0 = io_req_4_bits_vc_sel_3_0 & ~io_channel_status_3_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_4_4_0 = io_req_4_bits_vc_sel_4_0 & ~io_channel_status_4_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_4_5_0 = io_req_4_bits_vc_sel_5_0 & ~io_channel_status_5_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
assign in_arb_vals_4 = io_req_4_valid & (in_arb_reqs_4_0_0 | in_arb_reqs_4_0_1 | in_arb_reqs_4_0_2 | in_arb_reqs_4_1_0 | io_req_4_bits_vc_sel_1_1 | io_req_4_bits_vc_sel_1_2 | in_arb_reqs_4_2_0 | in_arb_reqs_4_3_0 | in_arb_reqs_4_4_0 | in_arb_reqs_4_5_0); // @[package.scala:81:59]
wire in_arb_reqs_5_0_0 = io_req_5_bits_vc_sel_0_0 & ~io_channel_status_0_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_5_0_1 = io_req_5_bits_vc_sel_0_1 & ~io_channel_status_0_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_5_0_2 = io_req_5_bits_vc_sel_0_2 & ~io_channel_status_0_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_5_1_0 = io_req_5_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_5_2_0 = io_req_5_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_5_3_0 = io_req_5_bits_vc_sel_3_0 & ~io_channel_status_3_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_5_4_0 = io_req_5_bits_vc_sel_4_0 & ~io_channel_status_4_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_5_5_0 = io_req_5_bits_vc_sel_5_0 & ~io_channel_status_5_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
assign in_arb_vals_5 = io_req_5_valid & (in_arb_reqs_5_0_0 | in_arb_reqs_5_0_1 | in_arb_reqs_5_0_2 | in_arb_reqs_5_1_0 | io_req_5_bits_vc_sel_1_1 | io_req_5_bits_vc_sel_1_2 | in_arb_reqs_5_2_0 | in_arb_reqs_5_3_0 | in_arb_reqs_5_4_0 | in_arb_reqs_5_5_0); // @[package.scala:81:59]
wire in_arb_reqs_6_0_0 = io_req_6_bits_vc_sel_0_0 & ~io_channel_status_0_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_6_0_1 = io_req_6_bits_vc_sel_0_1 & ~io_channel_status_0_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_6_0_2 = io_req_6_bits_vc_sel_0_2 & ~io_channel_status_0_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_6_1_0 = io_req_6_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_6_2_0 = io_req_6_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_6_3_0 = io_req_6_bits_vc_sel_3_0 & ~io_channel_status_3_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_6_4_0 = io_req_6_bits_vc_sel_4_0 & ~io_channel_status_4_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_6_5_0 = io_req_6_bits_vc_sel_5_0 & ~io_channel_status_5_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
assign in_arb_vals_6 = io_req_6_valid & (in_arb_reqs_6_0_0 | in_arb_reqs_6_0_1 | in_arb_reqs_6_0_2 | in_arb_reqs_6_1_0 | io_req_6_bits_vc_sel_1_1 | io_req_6_bits_vc_sel_1_2 | in_arb_reqs_6_2_0 | in_arb_reqs_6_3_0 | in_arb_reqs_6_4_0 | in_arb_reqs_6_5_0); // @[package.scala:81:59]
wire _in_vc_sel_T_19 = in_arb_sel[2] & in_arb_reqs_2_0_0 | in_arb_sel[4] & in_arb_reqs_4_0_0 | in_arb_sel[5] & in_arb_reqs_5_0_0 | in_arb_sel[6] & in_arb_reqs_6_0_0; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_32 = in_arb_sel[2] & in_arb_reqs_2_0_1 | in_arb_sel[4] & in_arb_reqs_4_0_1 | in_arb_sel[5] & in_arb_reqs_5_0_1 | in_arb_sel[6] & in_arb_reqs_6_0_1; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_45 = in_arb_sel[2] & in_arb_reqs_2_0_2 | in_arb_sel[4] & in_arb_reqs_4_0_2 | in_arb_sel[5] & in_arb_reqs_5_0_2 | in_arb_sel[6] & in_arb_reqs_6_0_2; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_58 = in_arb_sel[2] & in_arb_reqs_2_1_0 | in_arb_sel[4] & in_arb_reqs_4_1_0 | in_arb_sel[5] & in_arb_reqs_5_1_0 | in_arb_sel[6] & in_arb_reqs_6_1_0; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_71 = in_arb_sel[2] & io_req_2_bits_vc_sel_1_1 | in_arb_sel[4] & io_req_4_bits_vc_sel_1_1 | in_arb_sel[5] & io_req_5_bits_vc_sel_1_1 | in_arb_sel[6] & io_req_6_bits_vc_sel_1_1; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_84 = in_arb_sel[2] & io_req_2_bits_vc_sel_1_2 | in_arb_sel[4] & io_req_4_bits_vc_sel_1_2 | in_arb_sel[5] & io_req_5_bits_vc_sel_1_2 | in_arb_sel[6] & io_req_6_bits_vc_sel_1_2; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_97 = in_arb_sel[0] & in_arb_reqs_0_2_0 | in_arb_sel[1] & in_arb_reqs_1_2_0 | in_arb_sel[2] & in_arb_reqs_2_2_0 | in_arb_sel[4] & in_arb_reqs_4_2_0 | in_arb_sel[5] & in_arb_reqs_5_2_0 | in_arb_sel[6] & in_arb_reqs_6_2_0; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_110 = in_arb_sel[0] & in_arb_reqs_0_3_0 | in_arb_sel[1] & in_arb_reqs_1_3_0 | in_arb_sel[2] & in_arb_reqs_2_3_0 | in_arb_sel[4] & in_arb_reqs_4_3_0 | in_arb_sel[5] & in_arb_reqs_5_3_0 | in_arb_sel[6] & in_arb_reqs_6_3_0; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_123 = in_arb_sel[0] & in_arb_reqs_0_4_0 | in_arb_sel[1] & in_arb_reqs_1_4_0 | in_arb_sel[2] & in_arb_reqs_2_4_0 | in_arb_sel[4] & in_arb_reqs_4_4_0 | in_arb_sel[5] & in_arb_reqs_5_4_0 | in_arb_sel[6] & in_arb_reqs_6_4_0; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_136 = in_arb_sel[0] & in_arb_reqs_0_5_0 | in_arb_sel[1] & in_arb_reqs_1_5_0 | in_arb_sel[2] & in_arb_reqs_2_5_0 | in_arb_sel[4] & in_arb_reqs_4_5_0 | in_arb_sel[5] & in_arb_reqs_5_5_0 | in_arb_sel[6] & in_arb_reqs_6_5_0; // @[Mux.scala:30:73, :32:36]
reg [9:0] mask_1; // @[ISLIP.scala:17:25]
wire [9:0] _full_T_1 = {_in_vc_sel_T_136, _in_vc_sel_T_123, _in_vc_sel_T_110, _in_vc_sel_T_97, _in_vc_sel_T_84, _in_vc_sel_T_71, _in_vc_sel_T_58, _in_vc_sel_T_45, _in_vc_sel_T_32, _in_vc_sel_T_19} & ~mask_1; // @[Mux.scala:30:73]
wire [19:0] oh = _full_T_1[0] ? 20'h1 : _full_T_1[1] ? 20'h2 : _full_T_1[2] ? 20'h4 : _full_T_1[3] ? 20'h8 : _full_T_1[4] ? 20'h10 : _full_T_1[5] ? 20'h20 : _full_T_1[6] ? 20'h40 : _full_T_1[7] ? 20'h80 : _full_T_1[8] ? 20'h100 : _full_T_1[9] ? 20'h200 : _in_vc_sel_T_19 ? 20'h400 : _in_vc_sel_T_32 ? 20'h800 : _in_vc_sel_T_45 ? 20'h1000 : _in_vc_sel_T_58 ? 20'h2000 : _in_vc_sel_T_71 ? 20'h4000 : _in_vc_sel_T_84 ? 20'h8000 : _in_vc_sel_T_97 ? 20'h10000 : _in_vc_sel_T_110 ? 20'h20000 : _in_vc_sel_T_123 ? 20'h40000 : {_in_vc_sel_T_136, 19'h0}; // @[OneHot.scala:85:71]
wire [9:0] sel = oh[9:0] | oh[19:10]; // @[Mux.scala:50:70]
wire in_alloc_5_0 = _GEN & sel[9]; // @[package.scala:81:59]
wire in_alloc_4_0 = _GEN & sel[8]; // @[package.scala:81:59]
wire in_alloc_3_0 = _GEN & sel[7]; // @[package.scala:81:59]
wire in_alloc_2_0 = _GEN & sel[6]; // @[package.scala:81:59]
wire in_alloc_1_0 = _GEN & sel[3]; // @[package.scala:81:59]
wire in_alloc_1_1 = _GEN & sel[4]; // @[package.scala:81:59]
wire in_alloc_1_2 = _GEN & sel[5]; // @[package.scala:81:59]
wire in_alloc_0_0 = _GEN & sel[0]; // @[package.scala:81:59]
wire in_alloc_0_1 = _GEN & sel[1]; // @[package.scala:81:59]
wire in_alloc_0_2 = _GEN & sel[2]; // @[package.scala:81:59] |
Generate the Verilog code corresponding to this FIRRTL code module ForwardingAgeLogic_1 :
input clock : Clock
input reset : Reset
output io : { flip addr_matches : UInt<24>, flip youngest_st_idx : UInt<5>, forwarding_val : UInt<1>, forwarding_idx : UInt<5>}
wire age_mask : UInt<1>[24]
connect age_mask[0], UInt<1>(0h1)
node _T = geq(UInt<1>(0h0), io.youngest_st_idx)
when _T :
connect age_mask[0], UInt<1>(0h0)
connect age_mask[1], UInt<1>(0h1)
node _T_1 = geq(UInt<1>(0h1), io.youngest_st_idx)
when _T_1 :
connect age_mask[1], UInt<1>(0h0)
connect age_mask[2], UInt<1>(0h1)
node _T_2 = geq(UInt<2>(0h2), io.youngest_st_idx)
when _T_2 :
connect age_mask[2], UInt<1>(0h0)
connect age_mask[3], UInt<1>(0h1)
node _T_3 = geq(UInt<2>(0h3), io.youngest_st_idx)
when _T_3 :
connect age_mask[3], UInt<1>(0h0)
connect age_mask[4], UInt<1>(0h1)
node _T_4 = geq(UInt<3>(0h4), io.youngest_st_idx)
when _T_4 :
connect age_mask[4], UInt<1>(0h0)
connect age_mask[5], UInt<1>(0h1)
node _T_5 = geq(UInt<3>(0h5), io.youngest_st_idx)
when _T_5 :
connect age_mask[5], UInt<1>(0h0)
connect age_mask[6], UInt<1>(0h1)
node _T_6 = geq(UInt<3>(0h6), io.youngest_st_idx)
when _T_6 :
connect age_mask[6], UInt<1>(0h0)
connect age_mask[7], UInt<1>(0h1)
node _T_7 = geq(UInt<3>(0h7), io.youngest_st_idx)
when _T_7 :
connect age_mask[7], UInt<1>(0h0)
connect age_mask[8], UInt<1>(0h1)
node _T_8 = geq(UInt<4>(0h8), io.youngest_st_idx)
when _T_8 :
connect age_mask[8], UInt<1>(0h0)
connect age_mask[9], UInt<1>(0h1)
node _T_9 = geq(UInt<4>(0h9), io.youngest_st_idx)
when _T_9 :
connect age_mask[9], UInt<1>(0h0)
connect age_mask[10], UInt<1>(0h1)
node _T_10 = geq(UInt<4>(0ha), io.youngest_st_idx)
when _T_10 :
connect age_mask[10], UInt<1>(0h0)
connect age_mask[11], UInt<1>(0h1)
node _T_11 = geq(UInt<4>(0hb), io.youngest_st_idx)
when _T_11 :
connect age_mask[11], UInt<1>(0h0)
connect age_mask[12], UInt<1>(0h1)
node _T_12 = geq(UInt<4>(0hc), io.youngest_st_idx)
when _T_12 :
connect age_mask[12], UInt<1>(0h0)
connect age_mask[13], UInt<1>(0h1)
node _T_13 = geq(UInt<4>(0hd), io.youngest_st_idx)
when _T_13 :
connect age_mask[13], UInt<1>(0h0)
connect age_mask[14], UInt<1>(0h1)
node _T_14 = geq(UInt<4>(0he), io.youngest_st_idx)
when _T_14 :
connect age_mask[14], UInt<1>(0h0)
connect age_mask[15], UInt<1>(0h1)
node _T_15 = geq(UInt<4>(0hf), io.youngest_st_idx)
when _T_15 :
connect age_mask[15], UInt<1>(0h0)
connect age_mask[16], UInt<1>(0h1)
node _T_16 = geq(UInt<5>(0h10), io.youngest_st_idx)
when _T_16 :
connect age_mask[16], UInt<1>(0h0)
connect age_mask[17], UInt<1>(0h1)
node _T_17 = geq(UInt<5>(0h11), io.youngest_st_idx)
when _T_17 :
connect age_mask[17], UInt<1>(0h0)
connect age_mask[18], UInt<1>(0h1)
node _T_18 = geq(UInt<5>(0h12), io.youngest_st_idx)
when _T_18 :
connect age_mask[18], UInt<1>(0h0)
connect age_mask[19], UInt<1>(0h1)
node _T_19 = geq(UInt<5>(0h13), io.youngest_st_idx)
when _T_19 :
connect age_mask[19], UInt<1>(0h0)
connect age_mask[20], UInt<1>(0h1)
node _T_20 = geq(UInt<5>(0h14), io.youngest_st_idx)
when _T_20 :
connect age_mask[20], UInt<1>(0h0)
connect age_mask[21], UInt<1>(0h1)
node _T_21 = geq(UInt<5>(0h15), io.youngest_st_idx)
when _T_21 :
connect age_mask[21], UInt<1>(0h0)
connect age_mask[22], UInt<1>(0h1)
node _T_22 = geq(UInt<5>(0h16), io.youngest_st_idx)
when _T_22 :
connect age_mask[22], UInt<1>(0h0)
connect age_mask[23], UInt<1>(0h1)
node _T_23 = geq(UInt<5>(0h17), io.youngest_st_idx)
when _T_23 :
connect age_mask[23], UInt<1>(0h0)
wire matches : UInt<48>
node matches_lo_lo_lo_hi = cat(age_mask[2], age_mask[1])
node matches_lo_lo_lo = cat(matches_lo_lo_lo_hi, age_mask[0])
node matches_lo_lo_hi_hi = cat(age_mask[5], age_mask[4])
node matches_lo_lo_hi = cat(matches_lo_lo_hi_hi, age_mask[3])
node matches_lo_lo = cat(matches_lo_lo_hi, matches_lo_lo_lo)
node matches_lo_hi_lo_hi = cat(age_mask[8], age_mask[7])
node matches_lo_hi_lo = cat(matches_lo_hi_lo_hi, age_mask[6])
node matches_lo_hi_hi_hi = cat(age_mask[11], age_mask[10])
node matches_lo_hi_hi = cat(matches_lo_hi_hi_hi, age_mask[9])
node matches_lo_hi = cat(matches_lo_hi_hi, matches_lo_hi_lo)
node matches_lo = cat(matches_lo_hi, matches_lo_lo)
node matches_hi_lo_lo_hi = cat(age_mask[14], age_mask[13])
node matches_hi_lo_lo = cat(matches_hi_lo_lo_hi, age_mask[12])
node matches_hi_lo_hi_hi = cat(age_mask[17], age_mask[16])
node matches_hi_lo_hi = cat(matches_hi_lo_hi_hi, age_mask[15])
node matches_hi_lo = cat(matches_hi_lo_hi, matches_hi_lo_lo)
node matches_hi_hi_lo_hi = cat(age_mask[20], age_mask[19])
node matches_hi_hi_lo = cat(matches_hi_hi_lo_hi, age_mask[18])
node matches_hi_hi_hi_hi = cat(age_mask[23], age_mask[22])
node matches_hi_hi_hi = cat(matches_hi_hi_hi_hi, age_mask[21])
node matches_hi_hi = cat(matches_hi_hi_hi, matches_hi_hi_lo)
node matches_hi = cat(matches_hi_hi, matches_hi_lo)
node _matches_T = cat(matches_hi, matches_lo)
node _matches_T_1 = and(io.addr_matches, _matches_T)
node _matches_T_2 = cat(_matches_T_1, io.addr_matches)
connect matches, _matches_T_2
wire found_match : UInt<1>
connect found_match, UInt<1>(0h0)
connect io.forwarding_idx, UInt<1>(0h0)
node _T_24 = bits(matches, 0, 0)
when _T_24 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<1>(0h0)
node _T_25 = bits(matches, 1, 1)
when _T_25 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<1>(0h1)
node _T_26 = bits(matches, 2, 2)
when _T_26 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<2>(0h2)
node _T_27 = bits(matches, 3, 3)
when _T_27 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<2>(0h3)
node _T_28 = bits(matches, 4, 4)
when _T_28 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<3>(0h4)
node _T_29 = bits(matches, 5, 5)
when _T_29 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<3>(0h5)
node _T_30 = bits(matches, 6, 6)
when _T_30 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<3>(0h6)
node _T_31 = bits(matches, 7, 7)
when _T_31 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<3>(0h7)
node _T_32 = bits(matches, 8, 8)
when _T_32 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<4>(0h8)
node _T_33 = bits(matches, 9, 9)
when _T_33 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<4>(0h9)
node _T_34 = bits(matches, 10, 10)
when _T_34 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<4>(0ha)
node _T_35 = bits(matches, 11, 11)
when _T_35 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<4>(0hb)
node _T_36 = bits(matches, 12, 12)
when _T_36 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<4>(0hc)
node _T_37 = bits(matches, 13, 13)
when _T_37 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<4>(0hd)
node _T_38 = bits(matches, 14, 14)
when _T_38 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<4>(0he)
node _T_39 = bits(matches, 15, 15)
when _T_39 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<4>(0hf)
node _T_40 = bits(matches, 16, 16)
when _T_40 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<5>(0h10)
node _T_41 = bits(matches, 17, 17)
when _T_41 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<5>(0h11)
node _T_42 = bits(matches, 18, 18)
when _T_42 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<5>(0h12)
node _T_43 = bits(matches, 19, 19)
when _T_43 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<5>(0h13)
node _T_44 = bits(matches, 20, 20)
when _T_44 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<5>(0h14)
node _T_45 = bits(matches, 21, 21)
when _T_45 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<5>(0h15)
node _T_46 = bits(matches, 22, 22)
when _T_46 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<5>(0h16)
node _T_47 = bits(matches, 23, 23)
when _T_47 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<5>(0h17)
node _T_48 = bits(matches, 24, 24)
when _T_48 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<1>(0h0)
node _T_49 = bits(matches, 25, 25)
when _T_49 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<1>(0h1)
node _T_50 = bits(matches, 26, 26)
when _T_50 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<2>(0h2)
node _T_51 = bits(matches, 27, 27)
when _T_51 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<2>(0h3)
node _T_52 = bits(matches, 28, 28)
when _T_52 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<3>(0h4)
node _T_53 = bits(matches, 29, 29)
when _T_53 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<3>(0h5)
node _T_54 = bits(matches, 30, 30)
when _T_54 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<3>(0h6)
node _T_55 = bits(matches, 31, 31)
when _T_55 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<3>(0h7)
node _T_56 = bits(matches, 32, 32)
when _T_56 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<4>(0h8)
node _T_57 = bits(matches, 33, 33)
when _T_57 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<4>(0h9)
node _T_58 = bits(matches, 34, 34)
when _T_58 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<4>(0ha)
node _T_59 = bits(matches, 35, 35)
when _T_59 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<4>(0hb)
node _T_60 = bits(matches, 36, 36)
when _T_60 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<4>(0hc)
node _T_61 = bits(matches, 37, 37)
when _T_61 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<4>(0hd)
node _T_62 = bits(matches, 38, 38)
when _T_62 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<4>(0he)
node _T_63 = bits(matches, 39, 39)
when _T_63 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<4>(0hf)
node _T_64 = bits(matches, 40, 40)
when _T_64 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<5>(0h10)
node _T_65 = bits(matches, 41, 41)
when _T_65 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<5>(0h11)
node _T_66 = bits(matches, 42, 42)
when _T_66 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<5>(0h12)
node _T_67 = bits(matches, 43, 43)
when _T_67 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<5>(0h13)
node _T_68 = bits(matches, 44, 44)
when _T_68 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<5>(0h14)
node _T_69 = bits(matches, 45, 45)
when _T_69 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<5>(0h15)
node _T_70 = bits(matches, 46, 46)
when _T_70 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<5>(0h16)
node _T_71 = bits(matches, 47, 47)
when _T_71 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<5>(0h17)
connect io.forwarding_val, found_match | module ForwardingAgeLogic_1( // @[lsu.scala:1678:7]
input clock, // @[lsu.scala:1678:7]
input reset, // @[lsu.scala:1678:7]
input [23:0] io_addr_matches, // @[lsu.scala:1680:15]
input [4:0] io_youngest_st_idx, // @[lsu.scala:1680:15]
output [4:0] io_forwarding_idx // @[lsu.scala:1680:15]
);
wire [23:0] io_addr_matches_0 = io_addr_matches; // @[lsu.scala:1678:7]
wire [4:0] io_youngest_st_idx_0 = io_youngest_st_idx; // @[lsu.scala:1678:7]
wire found_match; // @[lsu.scala:1706:26]
wire io_forwarding_val; // @[lsu.scala:1678:7]
wire [4:0] io_forwarding_idx_0; // @[lsu.scala:1678:7]
wire age_mask_0; // @[lsu.scala:1691:23]
wire age_mask_1; // @[lsu.scala:1691:23]
wire age_mask_2; // @[lsu.scala:1691:23]
wire age_mask_3; // @[lsu.scala:1691:23]
wire age_mask_4; // @[lsu.scala:1691:23]
wire age_mask_5; // @[lsu.scala:1691:23]
wire age_mask_6; // @[lsu.scala:1691:23]
wire age_mask_7; // @[lsu.scala:1691:23]
wire age_mask_8; // @[lsu.scala:1691:23]
wire age_mask_9; // @[lsu.scala:1691:23]
wire age_mask_10; // @[lsu.scala:1691:23]
wire age_mask_11; // @[lsu.scala:1691:23]
wire age_mask_12; // @[lsu.scala:1691:23]
wire age_mask_13; // @[lsu.scala:1691:23]
wire age_mask_14; // @[lsu.scala:1691:23]
wire age_mask_15; // @[lsu.scala:1691:23]
wire age_mask_16; // @[lsu.scala:1691:23]
wire age_mask_17; // @[lsu.scala:1691:23]
wire age_mask_18; // @[lsu.scala:1691:23]
wire age_mask_19; // @[lsu.scala:1691:23]
wire age_mask_20; // @[lsu.scala:1691:23]
wire age_mask_21; // @[lsu.scala:1691:23]
wire age_mask_22; // @[lsu.scala:1691:23]
wire age_mask_23; // @[lsu.scala:1691:23]
assign age_mask_0 = |io_youngest_st_idx_0; // @[lsu.scala:1678:7, :1691:23, :1694:19, :1695:17, :1696:7, :1697:22]
assign age_mask_1 = |(io_youngest_st_idx_0[4:1]); // @[lsu.scala:1678:7, :1691:23, :1694:19, :1695:17, :1696:7, :1697:22]
assign age_mask_2 = io_youngest_st_idx_0 > 5'h2; // @[lsu.scala:1678:7, :1691:23, :1694:19, :1695:17, :1696:7, :1697:22]
assign age_mask_3 = |(io_youngest_st_idx_0[4:2]); // @[lsu.scala:1678:7, :1691:23, :1694:19, :1695:17, :1696:7, :1697:22]
assign age_mask_4 = io_youngest_st_idx_0 > 5'h4; // @[lsu.scala:1678:7, :1691:23, :1694:19, :1695:17, :1696:7, :1697:22]
assign age_mask_5 = io_youngest_st_idx_0 > 5'h5; // @[lsu.scala:1678:7, :1691:23, :1694:19, :1695:17, :1696:7, :1697:22]
assign age_mask_6 = io_youngest_st_idx_0 > 5'h6; // @[lsu.scala:1678:7, :1691:23, :1694:19, :1695:17, :1696:7, :1697:22]
assign age_mask_7 = |(io_youngest_st_idx_0[4:3]); // @[lsu.scala:1678:7, :1691:23, :1694:19, :1695:17, :1696:7, :1697:22]
assign age_mask_8 = io_youngest_st_idx_0 > 5'h8; // @[lsu.scala:1678:7, :1691:23, :1694:19, :1695:17, :1696:7, :1697:22]
assign age_mask_9 = io_youngest_st_idx_0 > 5'h9; // @[lsu.scala:1678:7, :1691:23, :1694:19, :1695:17, :1696:7, :1697:22]
assign age_mask_10 = io_youngest_st_idx_0 > 5'hA; // @[lsu.scala:1678:7, :1691:23, :1694:19, :1695:17, :1696:7, :1697:22]
assign age_mask_11 = io_youngest_st_idx_0 > 5'hB; // @[lsu.scala:1678:7, :1691:23, :1694:19, :1695:17, :1696:7, :1697:22]
assign age_mask_12 = io_youngest_st_idx_0 > 5'hC; // @[lsu.scala:1678:7, :1691:23, :1694:19, :1695:17, :1696:7, :1697:22]
assign age_mask_13 = io_youngest_st_idx_0 > 5'hD; // @[lsu.scala:1678:7, :1691:23, :1694:19, :1695:17, :1696:7, :1697:22]
assign age_mask_14 = io_youngest_st_idx_0 > 5'hE; // @[lsu.scala:1678:7, :1691:23, :1694:19, :1695:17, :1696:7, :1697:22]
assign age_mask_15 = io_youngest_st_idx_0[4]; // @[lsu.scala:1678:7, :1691:23, :1694:19, :1695:17, :1696:7, :1697:22]
assign age_mask_16 = io_youngest_st_idx_0 > 5'h10; // @[lsu.scala:1678:7, :1691:23, :1694:19, :1695:17, :1696:7, :1697:22]
assign age_mask_17 = io_youngest_st_idx_0 > 5'h11; // @[lsu.scala:1678:7, :1691:23, :1694:19, :1695:17, :1696:7, :1697:22]
assign age_mask_18 = io_youngest_st_idx_0 > 5'h12; // @[lsu.scala:1678:7, :1691:23, :1694:19, :1695:17, :1696:7, :1697:22]
assign age_mask_19 = io_youngest_st_idx_0 > 5'h13; // @[lsu.scala:1678:7, :1691:23, :1694:19, :1695:17, :1696:7, :1697:22]
assign age_mask_20 = io_youngest_st_idx_0 > 5'h14; // @[lsu.scala:1678:7, :1691:23, :1694:19, :1695:17, :1696:7, :1697:22]
assign age_mask_21 = io_youngest_st_idx_0 > 5'h15; // @[lsu.scala:1678:7, :1691:23, :1694:19, :1695:17, :1696:7, :1697:22]
assign age_mask_22 = io_youngest_st_idx_0 > 5'h16; // @[lsu.scala:1678:7, :1691:23, :1694:19, :1695:17, :1696:7, :1697:22]
assign age_mask_23 = io_youngest_st_idx_0 > 5'h17; // @[lsu.scala:1678:7, :1691:23, :1694:19, :1695:17, :1696:7, :1697:22]
wire [47:0] _matches_T_2; // @[lsu.scala:1703:18]
wire [47:0] matches_0; // @[lsu.scala:1702:22]
wire [1:0] matches_lo_lo_lo_hi = {age_mask_2, age_mask_1}; // @[lsu.scala:1691:23, :1703:46]
wire [2:0] matches_lo_lo_lo = {matches_lo_lo_lo_hi, age_mask_0}; // @[lsu.scala:1691:23, :1703:46]
wire [1:0] matches_lo_lo_hi_hi = {age_mask_5, age_mask_4}; // @[lsu.scala:1691:23, :1703:46]
wire [2:0] matches_lo_lo_hi = {matches_lo_lo_hi_hi, age_mask_3}; // @[lsu.scala:1691:23, :1703:46]
wire [5:0] matches_lo_lo = {matches_lo_lo_hi, matches_lo_lo_lo}; // @[lsu.scala:1703:46]
wire [1:0] matches_lo_hi_lo_hi = {age_mask_8, age_mask_7}; // @[lsu.scala:1691:23, :1703:46]
wire [2:0] matches_lo_hi_lo = {matches_lo_hi_lo_hi, age_mask_6}; // @[lsu.scala:1691:23, :1703:46]
wire [1:0] matches_lo_hi_hi_hi = {age_mask_11, age_mask_10}; // @[lsu.scala:1691:23, :1703:46]
wire [2:0] matches_lo_hi_hi = {matches_lo_hi_hi_hi, age_mask_9}; // @[lsu.scala:1691:23, :1703:46]
wire [5:0] matches_lo_hi = {matches_lo_hi_hi, matches_lo_hi_lo}; // @[lsu.scala:1703:46]
wire [11:0] matches_lo = {matches_lo_hi, matches_lo_lo}; // @[lsu.scala:1703:46]
wire [1:0] matches_hi_lo_lo_hi = {age_mask_14, age_mask_13}; // @[lsu.scala:1691:23, :1703:46]
wire [2:0] matches_hi_lo_lo = {matches_hi_lo_lo_hi, age_mask_12}; // @[lsu.scala:1691:23, :1703:46]
wire [1:0] matches_hi_lo_hi_hi = {age_mask_17, age_mask_16}; // @[lsu.scala:1691:23, :1703:46]
wire [2:0] matches_hi_lo_hi = {matches_hi_lo_hi_hi, age_mask_15}; // @[lsu.scala:1691:23, :1703:46]
wire [5:0] matches_hi_lo = {matches_hi_lo_hi, matches_hi_lo_lo}; // @[lsu.scala:1703:46]
wire [1:0] matches_hi_hi_lo_hi = {age_mask_20, age_mask_19}; // @[lsu.scala:1691:23, :1703:46]
wire [2:0] matches_hi_hi_lo = {matches_hi_hi_lo_hi, age_mask_18}; // @[lsu.scala:1691:23, :1703:46]
wire [1:0] matches_hi_hi_hi_hi = {age_mask_23, age_mask_22}; // @[lsu.scala:1691:23, :1703:46]
wire [2:0] matches_hi_hi_hi = {matches_hi_hi_hi_hi, age_mask_21}; // @[lsu.scala:1691:23, :1703:46]
wire [5:0] matches_hi_hi = {matches_hi_hi_hi, matches_hi_hi_lo}; // @[lsu.scala:1703:46]
wire [11:0] matches_hi = {matches_hi_hi, matches_hi_lo}; // @[lsu.scala:1703:46]
wire [23:0] _matches_T = {matches_hi, matches_lo}; // @[lsu.scala:1703:46]
wire [23:0] _matches_T_1 = io_addr_matches_0 & _matches_T; // @[lsu.scala:1678:7, :1703:{35,46}]
assign _matches_T_2 = {_matches_T_1, io_addr_matches_0}; // @[lsu.scala:1678:7, :1703:{18,35}]
assign matches_0 = _matches_T_2; // @[lsu.scala:1702:22, :1703:18]
assign io_forwarding_val = found_match; // @[lsu.scala:1678:7, :1706:26]
assign found_match = |matches_0; // @[lsu.scala:1702:22, :1706:26, :1714:7, :1715:22]
assign io_forwarding_idx_0 = matches_0[47] ? 5'h17 : matches_0[46] ? 5'h16 : matches_0[45] ? 5'h15 : matches_0[44] ? 5'h14 : matches_0[43] ? 5'h13 : matches_0[42] ? 5'h12 : matches_0[41] ? 5'h11 : matches_0[40] ? 5'h10 : matches_0[39] ? 5'hF : matches_0[38] ? 5'hE : matches_0[37] ? 5'hD : matches_0[36] ? 5'hC : matches_0[35] ? 5'hB : matches_0[34] ? 5'hA : matches_0[33] ? 5'h9 : matches_0[32] ? 5'h8 : matches_0[31] ? 5'h7 : matches_0[30] ? 5'h6 : matches_0[29] ? 5'h5 : matches_0[28] ? 5'h4 : matches_0[27] ? 5'h3 : matches_0[26] ? 5'h2 : matches_0[25] ? 5'h1 : matches_0[24] ? 5'h0 : matches_0[23] ? 5'h17 : matches_0[22] ? 5'h16 : matches_0[21] ? 5'h15 : matches_0[20] ? 5'h14 : matches_0[19] ? 5'h13 : matches_0[18] ? 5'h12 : matches_0[17] ? 5'h11 : matches_0[16] ? 5'h10 : matches_0[15] ? 5'hF : matches_0[14] ? 5'hE : matches_0[13] ? 5'hD : matches_0[12] ? 5'hC : matches_0[11] ? 5'hB : matches_0[10] ? 5'hA : matches_0[9] ? 5'h9 : matches_0[8] ? 5'h8 : matches_0[7] ? 5'h7 : matches_0[6] ? 5'h6 : matches_0[5] ? 5'h5 : matches_0[4] ? 5'h4 : matches_0[3] ? 5'h3 : matches_0[2] ? 5'h2 : {4'h0, matches_0[1]}; // @[lsu.scala:1678:7, :1694:19, :1695:17, :1696:7, :1697:22, :1702:22, :1713:20, :1714:7, :1716:28]
assign io_forwarding_idx = io_forwarding_idx_0; // @[lsu.scala:1678:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_12 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_sink_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_18
connect io_out_sink_valid_0.clock, clock
connect io_out_sink_valid_0.reset, reset
connect io_out_sink_valid_0.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_sink_valid_0.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_12( // @[AsyncQueue.scala:58:7]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in = 1'h1; // @[ShiftReg.scala:45:23]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_18 io_out_sink_valid_0 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_2 :
output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<4>, sig : UInt<2>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0))
node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1))
node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2))
node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3))
node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4))
node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6))
node _roundMagUp_T = and(roundingMode_min, io.in.sign)
node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0))
node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1)
node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2)
node _sAdjustedExp_T = add(io.in.sExp, asSInt(UInt<9>(0hfc)))
node _sAdjustedExp_T_1 = bits(_sAdjustedExp_T, 8, 0)
node sAdjustedExp = cvt(_sAdjustedExp_T_1)
node adjustedSig = shl(io.in.sig, 25)
wire common_expOut : UInt<9>
wire common_fractOut : UInt<23>
wire common_overflow : UInt<1>
wire common_totalUnderflow : UInt<1>
wire common_underflow : UInt<1>
wire common_inexact : UInt<1>
node _common_expOut_T = bits(sAdjustedExp, 8, 0)
node _common_expOut_T_1 = add(_common_expOut_T, UInt<1>(0h0))
node _common_expOut_T_2 = tail(_common_expOut_T_1, 1)
connect common_expOut, _common_expOut_T_2
node _common_fractOut_T = bits(adjustedSig, 25, 3)
node _common_fractOut_T_1 = bits(adjustedSig, 24, 2)
node _common_fractOut_T_2 = mux(UInt<1>(0h0), _common_fractOut_T, _common_fractOut_T_1)
connect common_fractOut, _common_fractOut_T_2
connect common_overflow, UInt<1>(0h0)
connect common_totalUnderflow, UInt<1>(0h0)
connect common_underflow, UInt<1>(0h0)
connect common_inexact, UInt<1>(0h0)
node isNaNOut = or(io.invalidExc, io.in.isNaN)
node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf)
node _commonCase_T = eq(isNaNOut, UInt<1>(0h0))
node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0))
node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1)
node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0))
node commonCase = and(_commonCase_T_2, _commonCase_T_3)
node overflow = and(commonCase, common_overflow)
node underflow = and(commonCase, common_underflow)
node _inexact_T = and(commonCase, common_inexact)
node inexact = or(overflow, _inexact_T)
node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp)
node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow)
node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd)
node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1)
node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0))
node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T)
node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp)
node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T)
node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign)
node _expOut_T = or(io.in.isZero, common_totalUnderflow)
node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0))
node _expOut_T_2 = not(_expOut_T_1)
node _expOut_T_3 = and(common_expOut, _expOut_T_2)
node _expOut_T_4 = not(UInt<9>(0h6b))
node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0))
node _expOut_T_6 = not(_expOut_T_5)
node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6)
node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0))
node _expOut_T_9 = not(_expOut_T_8)
node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9)
node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0))
node _expOut_T_12 = not(_expOut_T_11)
node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12)
node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0))
node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14)
node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0))
node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16)
node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0))
node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18)
node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0))
node expOut = or(_expOut_T_19, _expOut_T_20)
node _fractOut_T = or(isNaNOut, io.in.isZero)
node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow)
node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0))
node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut)
node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0))
node fractOut = or(_fractOut_T_3, _fractOut_T_4)
node _io_out_T = cat(signOut, expOut)
node _io_out_T_1 = cat(_io_out_T, fractOut)
connect io.out, _io_out_T_1
node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc)
node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow)
node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact)
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_2(); // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19]
wire [26:0] adjustedSig = 27'h2000000; // @[RoundAnyRawFNToRecFN.scala:114:22]
wire [22:0] _common_fractOut_T = 23'h400000; // @[RoundAnyRawFNToRecFN.scala:139:28]
wire [8:0] _expOut_T_2 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14]
wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14]
wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14]
wire [8:0] _expOut_T_12 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14]
wire [8:0] _expOut_T_1 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_11 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_18 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_20 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _sAdjustedExp_T_1 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] common_expOut = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _common_expOut_T = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _common_expOut_T_2 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_3 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_7 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_10 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_13 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_15 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_17 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_19 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] expOut = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [22:0] common_fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _common_fractOut_T_1 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _common_fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _fractOut_T_3 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [9:0] _sAdjustedExp_T = 10'h100; // @[RoundAnyRawFNToRecFN.scala:104:25, :136:55, :286:23]
wire [9:0] sAdjustedExp = 10'h100; // @[RoundAnyRawFNToRecFN.scala:106:31, :136:55, :286:23]
wire [9:0] _common_expOut_T_1 = 10'h100; // @[RoundAnyRawFNToRecFN.scala:136:55, :286:23]
wire [9:0] _io_out_T = 10'h100; // @[RoundAnyRawFNToRecFN.scala:136:55, :286:23]
wire [1:0] _io_exceptionFlags_T = 2'h0; // @[RoundAnyRawFNToRecFN.scala:288:23]
wire [3:0] _io_exceptionFlags_T_2 = 4'h0; // @[RoundAnyRawFNToRecFN.scala:288:53]
wire [4:0] io_exceptionFlags = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66]
wire [4:0] _io_exceptionFlags_T_3 = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66]
wire [32:0] io_out = 33'h80000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33]
wire [32:0] _io_out_T_1 = 33'h80000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _roundMagUp_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _commonCase_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _commonCase_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _commonCase_T_2 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _commonCase_T_3 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire commonCase = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41]
wire [2:0] _io_exceptionFlags_T_1 = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41]
wire [1:0] io_in_sig = 2'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16]
wire [3:0] io_in_sExp = 4'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16]
wire io_invalidExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isNaN = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isInf = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isZero = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_sign = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53]
wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53]
wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53]
wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53]
wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53]
wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27]
wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63]
wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42]
wire common_overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:124:37]
wire common_totalUnderflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:125:37]
wire common_underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:126:37]
wire common_inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:127:37]
wire isNaNOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:235:34]
wire notNaN_isSpecialInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:236:49]
wire overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:238:32]
wire underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:239:32]
wire _inexact_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:43]
wire inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:28]
wire _pegMinNonzeroMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:20]
wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60]
wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45]
wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42]
wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39]
wire _notNaN_isInfOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:45]
wire notNaN_isInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:32]
wire signOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:250:22]
wire _expOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:253:32]
wire _fractOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:280:22]
wire _fractOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:280:38]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_preMul_e8_s24_42 :
output io : { flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, mulAddA : UInt<24>, mulAddB : UInt<24>, mulAddC : UInt<48>, toPostMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}}
node rawA_exp = bits(io.a, 31, 23)
node _rawA_isZero_T = bits(rawA_exp, 8, 6)
node rawA_isZero = eq(_rawA_isZero_T, UInt<1>(0h0))
node _rawA_isSpecial_T = bits(rawA_exp, 8, 7)
node rawA_isSpecial = eq(_rawA_isSpecial_T, UInt<2>(0h3))
wire rawA : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawA_out_isNaN_T = bits(rawA_exp, 6, 6)
node _rawA_out_isNaN_T_1 = and(rawA_isSpecial, _rawA_out_isNaN_T)
connect rawA.isNaN, _rawA_out_isNaN_T_1
node _rawA_out_isInf_T = bits(rawA_exp, 6, 6)
node _rawA_out_isInf_T_1 = eq(_rawA_out_isInf_T, UInt<1>(0h0))
node _rawA_out_isInf_T_2 = and(rawA_isSpecial, _rawA_out_isInf_T_1)
connect rawA.isInf, _rawA_out_isInf_T_2
connect rawA.isZero, rawA_isZero
node _rawA_out_sign_T = bits(io.a, 32, 32)
connect rawA.sign, _rawA_out_sign_T
node _rawA_out_sExp_T = cvt(rawA_exp)
connect rawA.sExp, _rawA_out_sExp_T
node _rawA_out_sig_T = eq(rawA_isZero, UInt<1>(0h0))
node _rawA_out_sig_T_1 = cat(UInt<1>(0h0), _rawA_out_sig_T)
node _rawA_out_sig_T_2 = bits(io.a, 22, 0)
node _rawA_out_sig_T_3 = cat(_rawA_out_sig_T_1, _rawA_out_sig_T_2)
connect rawA.sig, _rawA_out_sig_T_3
node rawB_exp = bits(io.b, 31, 23)
node _rawB_isZero_T = bits(rawB_exp, 8, 6)
node rawB_isZero = eq(_rawB_isZero_T, UInt<1>(0h0))
node _rawB_isSpecial_T = bits(rawB_exp, 8, 7)
node rawB_isSpecial = eq(_rawB_isSpecial_T, UInt<2>(0h3))
wire rawB : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawB_out_isNaN_T = bits(rawB_exp, 6, 6)
node _rawB_out_isNaN_T_1 = and(rawB_isSpecial, _rawB_out_isNaN_T)
connect rawB.isNaN, _rawB_out_isNaN_T_1
node _rawB_out_isInf_T = bits(rawB_exp, 6, 6)
node _rawB_out_isInf_T_1 = eq(_rawB_out_isInf_T, UInt<1>(0h0))
node _rawB_out_isInf_T_2 = and(rawB_isSpecial, _rawB_out_isInf_T_1)
connect rawB.isInf, _rawB_out_isInf_T_2
connect rawB.isZero, rawB_isZero
node _rawB_out_sign_T = bits(io.b, 32, 32)
connect rawB.sign, _rawB_out_sign_T
node _rawB_out_sExp_T = cvt(rawB_exp)
connect rawB.sExp, _rawB_out_sExp_T
node _rawB_out_sig_T = eq(rawB_isZero, UInt<1>(0h0))
node _rawB_out_sig_T_1 = cat(UInt<1>(0h0), _rawB_out_sig_T)
node _rawB_out_sig_T_2 = bits(io.b, 22, 0)
node _rawB_out_sig_T_3 = cat(_rawB_out_sig_T_1, _rawB_out_sig_T_2)
connect rawB.sig, _rawB_out_sig_T_3
node rawC_exp = bits(io.c, 31, 23)
node _rawC_isZero_T = bits(rawC_exp, 8, 6)
node rawC_isZero = eq(_rawC_isZero_T, UInt<1>(0h0))
node _rawC_isSpecial_T = bits(rawC_exp, 8, 7)
node rawC_isSpecial = eq(_rawC_isSpecial_T, UInt<2>(0h3))
wire rawC : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawC_out_isNaN_T = bits(rawC_exp, 6, 6)
node _rawC_out_isNaN_T_1 = and(rawC_isSpecial, _rawC_out_isNaN_T)
connect rawC.isNaN, _rawC_out_isNaN_T_1
node _rawC_out_isInf_T = bits(rawC_exp, 6, 6)
node _rawC_out_isInf_T_1 = eq(_rawC_out_isInf_T, UInt<1>(0h0))
node _rawC_out_isInf_T_2 = and(rawC_isSpecial, _rawC_out_isInf_T_1)
connect rawC.isInf, _rawC_out_isInf_T_2
connect rawC.isZero, rawC_isZero
node _rawC_out_sign_T = bits(io.c, 32, 32)
connect rawC.sign, _rawC_out_sign_T
node _rawC_out_sExp_T = cvt(rawC_exp)
connect rawC.sExp, _rawC_out_sExp_T
node _rawC_out_sig_T = eq(rawC_isZero, UInt<1>(0h0))
node _rawC_out_sig_T_1 = cat(UInt<1>(0h0), _rawC_out_sig_T)
node _rawC_out_sig_T_2 = bits(io.c, 22, 0)
node _rawC_out_sig_T_3 = cat(_rawC_out_sig_T_1, _rawC_out_sig_T_2)
connect rawC.sig, _rawC_out_sig_T_3
node _signProd_T = xor(rawA.sign, rawB.sign)
node _signProd_T_1 = bits(io.op, 1, 1)
node signProd = xor(_signProd_T, _signProd_T_1)
node _sExpAlignedProd_T = add(rawA.sExp, rawB.sExp)
node _sExpAlignedProd_T_1 = add(_sExpAlignedProd_T, asSInt(UInt<9>(0h11b)))
node _sExpAlignedProd_T_2 = tail(_sExpAlignedProd_T_1, 1)
node sExpAlignedProd = asSInt(_sExpAlignedProd_T_2)
node _doSubMags_T = xor(signProd, rawC.sign)
node _doSubMags_T_1 = bits(io.op, 0, 0)
node doSubMags = xor(_doSubMags_T, _doSubMags_T_1)
node _sNatCAlignDist_T = sub(sExpAlignedProd, rawC.sExp)
node _sNatCAlignDist_T_1 = tail(_sNatCAlignDist_T, 1)
node sNatCAlignDist = asSInt(_sNatCAlignDist_T_1)
node posNatCAlignDist = bits(sNatCAlignDist, 9, 0)
node _isMinCAlign_T = or(rawA.isZero, rawB.isZero)
node _isMinCAlign_T_1 = lt(sNatCAlignDist, asSInt(UInt<1>(0h0)))
node isMinCAlign = or(_isMinCAlign_T, _isMinCAlign_T_1)
node _CIsDominant_T = eq(rawC.isZero, UInt<1>(0h0))
node _CIsDominant_T_1 = leq(posNatCAlignDist, UInt<5>(0h18))
node _CIsDominant_T_2 = or(isMinCAlign, _CIsDominant_T_1)
node CIsDominant = and(_CIsDominant_T, _CIsDominant_T_2)
node _CAlignDist_T = lt(posNatCAlignDist, UInt<7>(0h4a))
node _CAlignDist_T_1 = bits(posNatCAlignDist, 6, 0)
node _CAlignDist_T_2 = mux(_CAlignDist_T, _CAlignDist_T_1, UInt<7>(0h4a))
node CAlignDist = mux(isMinCAlign, UInt<1>(0h0), _CAlignDist_T_2)
node _mainAlignedSigC_T = not(rawC.sig)
node _mainAlignedSigC_T_1 = mux(doSubMags, _mainAlignedSigC_T, rawC.sig)
node _mainAlignedSigC_T_2 = mux(doSubMags, UInt<53>(0h1fffffffffffff), UInt<53>(0h0))
node _mainAlignedSigC_T_3 = cat(_mainAlignedSigC_T_1, _mainAlignedSigC_T_2)
node _mainAlignedSigC_T_4 = asSInt(_mainAlignedSigC_T_3)
node mainAlignedSigC = dshr(_mainAlignedSigC_T_4, CAlignDist)
node _reduced4CExtra_T = shl(rawC.sig, 2)
wire reduced4CExtra_reducedVec : UInt<1>[7]
node _reduced4CExtra_reducedVec_0_T = bits(_reduced4CExtra_T, 3, 0)
node _reduced4CExtra_reducedVec_0_T_1 = orr(_reduced4CExtra_reducedVec_0_T)
connect reduced4CExtra_reducedVec[0], _reduced4CExtra_reducedVec_0_T_1
node _reduced4CExtra_reducedVec_1_T = bits(_reduced4CExtra_T, 7, 4)
node _reduced4CExtra_reducedVec_1_T_1 = orr(_reduced4CExtra_reducedVec_1_T)
connect reduced4CExtra_reducedVec[1], _reduced4CExtra_reducedVec_1_T_1
node _reduced4CExtra_reducedVec_2_T = bits(_reduced4CExtra_T, 11, 8)
node _reduced4CExtra_reducedVec_2_T_1 = orr(_reduced4CExtra_reducedVec_2_T)
connect reduced4CExtra_reducedVec[2], _reduced4CExtra_reducedVec_2_T_1
node _reduced4CExtra_reducedVec_3_T = bits(_reduced4CExtra_T, 15, 12)
node _reduced4CExtra_reducedVec_3_T_1 = orr(_reduced4CExtra_reducedVec_3_T)
connect reduced4CExtra_reducedVec[3], _reduced4CExtra_reducedVec_3_T_1
node _reduced4CExtra_reducedVec_4_T = bits(_reduced4CExtra_T, 19, 16)
node _reduced4CExtra_reducedVec_4_T_1 = orr(_reduced4CExtra_reducedVec_4_T)
connect reduced4CExtra_reducedVec[4], _reduced4CExtra_reducedVec_4_T_1
node _reduced4CExtra_reducedVec_5_T = bits(_reduced4CExtra_T, 23, 20)
node _reduced4CExtra_reducedVec_5_T_1 = orr(_reduced4CExtra_reducedVec_5_T)
connect reduced4CExtra_reducedVec[5], _reduced4CExtra_reducedVec_5_T_1
node _reduced4CExtra_reducedVec_6_T = bits(_reduced4CExtra_T, 26, 24)
node _reduced4CExtra_reducedVec_6_T_1 = orr(_reduced4CExtra_reducedVec_6_T)
connect reduced4CExtra_reducedVec[6], _reduced4CExtra_reducedVec_6_T_1
node reduced4CExtra_lo_hi = cat(reduced4CExtra_reducedVec[2], reduced4CExtra_reducedVec[1])
node reduced4CExtra_lo = cat(reduced4CExtra_lo_hi, reduced4CExtra_reducedVec[0])
node reduced4CExtra_hi_lo = cat(reduced4CExtra_reducedVec[4], reduced4CExtra_reducedVec[3])
node reduced4CExtra_hi_hi = cat(reduced4CExtra_reducedVec[6], reduced4CExtra_reducedVec[5])
node reduced4CExtra_hi = cat(reduced4CExtra_hi_hi, reduced4CExtra_hi_lo)
node _reduced4CExtra_T_1 = cat(reduced4CExtra_hi, reduced4CExtra_lo)
node _reduced4CExtra_T_2 = shr(CAlignDist, 2)
node reduced4CExtra_shift = dshr(asSInt(UInt<33>(0h100000000)), _reduced4CExtra_T_2)
node _reduced4CExtra_T_3 = bits(reduced4CExtra_shift, 19, 14)
node _reduced4CExtra_T_4 = bits(_reduced4CExtra_T_3, 3, 0)
node _reduced4CExtra_T_5 = bits(_reduced4CExtra_T_4, 1, 0)
node _reduced4CExtra_T_6 = bits(_reduced4CExtra_T_5, 0, 0)
node _reduced4CExtra_T_7 = bits(_reduced4CExtra_T_5, 1, 1)
node _reduced4CExtra_T_8 = cat(_reduced4CExtra_T_6, _reduced4CExtra_T_7)
node _reduced4CExtra_T_9 = bits(_reduced4CExtra_T_4, 3, 2)
node _reduced4CExtra_T_10 = bits(_reduced4CExtra_T_9, 0, 0)
node _reduced4CExtra_T_11 = bits(_reduced4CExtra_T_9, 1, 1)
node _reduced4CExtra_T_12 = cat(_reduced4CExtra_T_10, _reduced4CExtra_T_11)
node _reduced4CExtra_T_13 = cat(_reduced4CExtra_T_8, _reduced4CExtra_T_12)
node _reduced4CExtra_T_14 = bits(_reduced4CExtra_T_3, 5, 4)
node _reduced4CExtra_T_15 = bits(_reduced4CExtra_T_14, 0, 0)
node _reduced4CExtra_T_16 = bits(_reduced4CExtra_T_14, 1, 1)
node _reduced4CExtra_T_17 = cat(_reduced4CExtra_T_15, _reduced4CExtra_T_16)
node _reduced4CExtra_T_18 = cat(_reduced4CExtra_T_13, _reduced4CExtra_T_17)
node _reduced4CExtra_T_19 = and(_reduced4CExtra_T_1, _reduced4CExtra_T_18)
node reduced4CExtra = orr(_reduced4CExtra_T_19)
node _alignedSigC_T = shr(mainAlignedSigC, 3)
node _alignedSigC_T_1 = bits(mainAlignedSigC, 2, 0)
node _alignedSigC_T_2 = andr(_alignedSigC_T_1)
node _alignedSigC_T_3 = eq(reduced4CExtra, UInt<1>(0h0))
node _alignedSigC_T_4 = and(_alignedSigC_T_2, _alignedSigC_T_3)
node _alignedSigC_T_5 = bits(mainAlignedSigC, 2, 0)
node _alignedSigC_T_6 = orr(_alignedSigC_T_5)
node _alignedSigC_T_7 = or(_alignedSigC_T_6, reduced4CExtra)
node _alignedSigC_T_8 = mux(doSubMags, _alignedSigC_T_4, _alignedSigC_T_7)
node alignedSigC_hi = asUInt(_alignedSigC_T)
node alignedSigC = cat(alignedSigC_hi, _alignedSigC_T_8)
connect io.mulAddA, rawA.sig
connect io.mulAddB, rawB.sig
node _io_mulAddC_T = bits(alignedSigC, 48, 1)
connect io.mulAddC, _io_mulAddC_T
node _io_toPostMul_isSigNaNAny_T = bits(rawA.sig, 22, 22)
node _io_toPostMul_isSigNaNAny_T_1 = eq(_io_toPostMul_isSigNaNAny_T, UInt<1>(0h0))
node _io_toPostMul_isSigNaNAny_T_2 = and(rawA.isNaN, _io_toPostMul_isSigNaNAny_T_1)
node _io_toPostMul_isSigNaNAny_T_3 = bits(rawB.sig, 22, 22)
node _io_toPostMul_isSigNaNAny_T_4 = eq(_io_toPostMul_isSigNaNAny_T_3, UInt<1>(0h0))
node _io_toPostMul_isSigNaNAny_T_5 = and(rawB.isNaN, _io_toPostMul_isSigNaNAny_T_4)
node _io_toPostMul_isSigNaNAny_T_6 = or(_io_toPostMul_isSigNaNAny_T_2, _io_toPostMul_isSigNaNAny_T_5)
node _io_toPostMul_isSigNaNAny_T_7 = bits(rawC.sig, 22, 22)
node _io_toPostMul_isSigNaNAny_T_8 = eq(_io_toPostMul_isSigNaNAny_T_7, UInt<1>(0h0))
node _io_toPostMul_isSigNaNAny_T_9 = and(rawC.isNaN, _io_toPostMul_isSigNaNAny_T_8)
node _io_toPostMul_isSigNaNAny_T_10 = or(_io_toPostMul_isSigNaNAny_T_6, _io_toPostMul_isSigNaNAny_T_9)
connect io.toPostMul.isSigNaNAny, _io_toPostMul_isSigNaNAny_T_10
node _io_toPostMul_isNaNAOrB_T = or(rawA.isNaN, rawB.isNaN)
connect io.toPostMul.isNaNAOrB, _io_toPostMul_isNaNAOrB_T
connect io.toPostMul.isInfA, rawA.isInf
connect io.toPostMul.isZeroA, rawA.isZero
connect io.toPostMul.isInfB, rawB.isInf
connect io.toPostMul.isZeroB, rawB.isZero
connect io.toPostMul.signProd, signProd
connect io.toPostMul.isNaNC, rawC.isNaN
connect io.toPostMul.isInfC, rawC.isInf
connect io.toPostMul.isZeroC, rawC.isZero
node _io_toPostMul_sExpSum_T = sub(sExpAlignedProd, asSInt(UInt<6>(0h18)))
node _io_toPostMul_sExpSum_T_1 = tail(_io_toPostMul_sExpSum_T, 1)
node _io_toPostMul_sExpSum_T_2 = asSInt(_io_toPostMul_sExpSum_T_1)
node _io_toPostMul_sExpSum_T_3 = mux(CIsDominant, rawC.sExp, _io_toPostMul_sExpSum_T_2)
connect io.toPostMul.sExpSum, _io_toPostMul_sExpSum_T_3
connect io.toPostMul.doSubMags, doSubMags
connect io.toPostMul.CIsDominant, CIsDominant
node _io_toPostMul_CDom_CAlignDist_T = bits(CAlignDist, 4, 0)
connect io.toPostMul.CDom_CAlignDist, _io_toPostMul_CDom_CAlignDist_T
node _io_toPostMul_highAlignedSigC_T = bits(alignedSigC, 74, 49)
connect io.toPostMul.highAlignedSigC, _io_toPostMul_highAlignedSigC_T
node _io_toPostMul_bit0AlignedSigC_T = bits(alignedSigC, 0, 0)
connect io.toPostMul.bit0AlignedSigC, _io_toPostMul_bit0AlignedSigC_T | module MulAddRecFNToRaw_preMul_e8_s24_42( // @[MulAddRecFN.scala:71:7]
input [32:0] io_a, // @[MulAddRecFN.scala:74:16]
input [32:0] io_c, // @[MulAddRecFN.scala:74:16]
output [23:0] io_mulAddA, // @[MulAddRecFN.scala:74:16]
output [47:0] io_mulAddC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isNaNAOrB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfA, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroA, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_signProd, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isNaNC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroC, // @[MulAddRecFN.scala:74:16]
output [9:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_CIsDominant, // @[MulAddRecFN.scala:74:16]
output [4:0] io_toPostMul_CDom_CAlignDist, // @[MulAddRecFN.scala:74:16]
output [25:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16]
);
wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23]
wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:71:7]
wire [32:0] io_c_0 = io_c; // @[MulAddRecFN.scala:71:7]
wire [8:0] rawB_exp = 9'h100; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawB_isZero_T = 3'h4; // @[rawFloatFromRecFN.scala:52:28]
wire [1:0] _rawB_isSpecial_T = 2'h2; // @[rawFloatFromRecFN.scala:53:28]
wire [9:0] rawB_sExp = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire [9:0] _rawB_out_sExp_T = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire [1:0] _rawB_out_sig_T_1 = 2'h1; // @[rawFloatFromRecFN.scala:61:32]
wire [22:0] _rawB_out_sig_T_2 = 23'h0; // @[rawFloatFromRecFN.scala:61:49]
wire [24:0] rawB_sig = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [24:0] _rawB_out_sig_T_3 = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire _rawB_out_isInf_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:57:36, :61:35]
wire _rawB_out_sig_T = 1'h1; // @[rawFloatFromRecFN.scala:57:36, :61:35]
wire _io_toPostMul_isSigNaNAny_T_4 = 1'h1; // @[rawFloatFromRecFN.scala:57:36, :61:35]
wire io_toPostMul_isInfB = 1'h0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroB = 1'h0; // @[MulAddRecFN.scala:71:7]
wire rawB_isZero = 1'h0; // @[rawFloatFromRecFN.scala:52:53]
wire rawB_isSpecial = 1'h0; // @[rawFloatFromRecFN.scala:53:53]
wire rawB_isNaN = 1'h0; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_isInf = 1'h0; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_isZero_0 = 1'h0; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_sign = 1'h0; // @[rawFloatFromRecFN.scala:55:23]
wire _rawB_out_isNaN_T = 1'h0; // @[rawFloatFromRecFN.scala:56:41]
wire _rawB_out_isNaN_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:56:33]
wire _rawB_out_isInf_T = 1'h0; // @[rawFloatFromRecFN.scala:57:41]
wire _rawB_out_isInf_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:57:33]
wire _rawB_out_sign_T = 1'h0; // @[rawFloatFromRecFN.scala:59:25]
wire _signProd_T_1 = 1'h0; // @[MulAddRecFN.scala:97:49]
wire _doSubMags_T_1 = 1'h0; // @[MulAddRecFN.scala:102:49]
wire _io_toPostMul_isSigNaNAny_T_3 = 1'h0; // @[common.scala:82:56]
wire _io_toPostMul_isSigNaNAny_T_5 = 1'h0; // @[common.scala:82:46]
wire [23:0] io_mulAddB = 24'h800000; // @[MulAddRecFN.scala:71:7, :74:16, :142:16]
wire [32:0] io_b = 33'h80000000; // @[MulAddRecFN.scala:71:7, :74:16]
wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:71:7, :74:16]
wire [47:0] _io_mulAddC_T; // @[MulAddRecFN.scala:143:30]
wire _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:146:58]
wire _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:148:42]
wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawA_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire signProd; // @[MulAddRecFN.scala:97:42]
wire rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawC_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire doSubMags; // @[MulAddRecFN.scala:102:42]
wire CIsDominant; // @[MulAddRecFN.scala:110:23]
wire [4:0] _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:161:47]
wire [25:0] _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:163:20]
wire _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:164:48]
wire io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7]
wire [9:0] io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7]
wire [4:0] io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7]
wire [25:0] io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7]
wire [23:0] io_mulAddA_0; // @[MulAddRecFN.scala:71:7]
wire [47:0] io_mulAddC_0; // @[MulAddRecFN.scala:71:7]
wire [8:0] rawA_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawA_isZero_T = rawA_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawA_isZero_0 = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawA_isZero = rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawA_isSpecial_T = rawA_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign _io_toPostMul_isNaNAOrB_T = rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isInfA_0 = rawA_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroA_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire _isMinCAlign_T = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire _signProd_T = rawA_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire [9:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawA_out_isNaN_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawA_out_isInf_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawA_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawA_out_sig_T = ~rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawA_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [8:0] rawC_exp = io_c_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawC_isZero_T = rawC_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawC_isZero_0 = _rawC_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawC_isZero = rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawC_isSpecial_T = rawC_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawC_isSpecial = &_rawC_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
assign io_toPostMul_isNaNC_0 = rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign io_toPostMul_isInfC_0 = rawC_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroC_0 = rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawC_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawC_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_isNaN_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawC_out_isInf_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawC_out_isNaN_T_1 = rawC_isSpecial & _rawC_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawC_isNaN = _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawC_out_isInf_T_1 = ~_rawC_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawC_out_isInf_T_2 = rawC_isSpecial & _rawC_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawC_isInf = _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawC_out_sign_T = io_c_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawC_sign = _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawC_out_sExp_T = {1'h0, rawC_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawC_sExp = _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawC_out_sig_T = ~rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawC_out_sig_T_1 = {1'h0, _rawC_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawC_out_sig_T_2 = io_c_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawC_out_sig_T_3 = {_rawC_out_sig_T_1, _rawC_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawC_sig = _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
assign signProd = _signProd_T; // @[MulAddRecFN.scala:97:{30,42}]
assign io_toPostMul_signProd_0 = signProd; // @[MulAddRecFN.scala:71:7, :97:42]
wire [10:0] _sExpAlignedProd_T = {rawA_sExp[9], rawA_sExp} + 11'h100; // @[rawFloatFromRecFN.scala:55:23]
wire [11:0] _sExpAlignedProd_T_1 = {_sExpAlignedProd_T[10], _sExpAlignedProd_T} - 12'hE5; // @[MulAddRecFN.scala:100:{19,32}]
wire [10:0] _sExpAlignedProd_T_2 = _sExpAlignedProd_T_1[10:0]; // @[MulAddRecFN.scala:100:32]
wire [10:0] sExpAlignedProd = _sExpAlignedProd_T_2; // @[MulAddRecFN.scala:100:32]
wire _doSubMags_T = signProd ^ rawC_sign; // @[rawFloatFromRecFN.scala:55:23]
assign doSubMags = _doSubMags_T; // @[MulAddRecFN.scala:102:{30,42}]
assign io_toPostMul_doSubMags_0 = doSubMags; // @[MulAddRecFN.scala:71:7, :102:42]
wire [11:0] _GEN = {sExpAlignedProd[10], sExpAlignedProd}; // @[MulAddRecFN.scala:100:32, :106:42]
wire [11:0] _sNatCAlignDist_T = _GEN - {{2{rawC_sExp[9]}}, rawC_sExp}; // @[rawFloatFromRecFN.scala:55:23]
wire [10:0] _sNatCAlignDist_T_1 = _sNatCAlignDist_T[10:0]; // @[MulAddRecFN.scala:106:42]
wire [10:0] sNatCAlignDist = _sNatCAlignDist_T_1; // @[MulAddRecFN.scala:106:42]
wire [9:0] posNatCAlignDist = sNatCAlignDist[9:0]; // @[MulAddRecFN.scala:106:42, :107:42]
wire _isMinCAlign_T_1 = $signed(sNatCAlignDist) < 11'sh0; // @[MulAddRecFN.scala:106:42, :108:69]
wire isMinCAlign = _isMinCAlign_T | _isMinCAlign_T_1; // @[MulAddRecFN.scala:108:{35,50,69}]
wire _CIsDominant_T = ~rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _CIsDominant_T_1 = posNatCAlignDist < 10'h19; // @[MulAddRecFN.scala:107:42, :110:60]
wire _CIsDominant_T_2 = isMinCAlign | _CIsDominant_T_1; // @[MulAddRecFN.scala:108:50, :110:{39,60}]
assign CIsDominant = _CIsDominant_T & _CIsDominant_T_2; // @[MulAddRecFN.scala:110:{9,23,39}]
assign io_toPostMul_CIsDominant_0 = CIsDominant; // @[MulAddRecFN.scala:71:7, :110:23]
wire _CAlignDist_T = posNatCAlignDist < 10'h4A; // @[MulAddRecFN.scala:107:42, :114:34]
wire [6:0] _CAlignDist_T_1 = posNatCAlignDist[6:0]; // @[MulAddRecFN.scala:107:42, :115:33]
wire [6:0] _CAlignDist_T_2 = _CAlignDist_T ? _CAlignDist_T_1 : 7'h4A; // @[MulAddRecFN.scala:114:{16,34}, :115:33]
wire [6:0] CAlignDist = isMinCAlign ? 7'h0 : _CAlignDist_T_2; // @[MulAddRecFN.scala:108:50, :112:12, :114:16]
wire [24:0] _mainAlignedSigC_T = ~rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] _mainAlignedSigC_T_1 = doSubMags ? _mainAlignedSigC_T : rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire [52:0] _mainAlignedSigC_T_2 = {53{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:53]
wire [77:0] _mainAlignedSigC_T_3 = {_mainAlignedSigC_T_1, _mainAlignedSigC_T_2}; // @[MulAddRecFN.scala:120:{13,46,53}]
wire [77:0] _mainAlignedSigC_T_4 = _mainAlignedSigC_T_3; // @[MulAddRecFN.scala:120:{46,94}]
wire [77:0] mainAlignedSigC = $signed($signed(_mainAlignedSigC_T_4) >>> CAlignDist); // @[MulAddRecFN.scala:112:12, :120:{94,100}]
wire [26:0] _reduced4CExtra_T = {rawC_sig, 2'h0}; // @[rawFloatFromRecFN.scala:55:23]
wire _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:123:57]
wire reduced4CExtra_reducedVec_0; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_1; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_2; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_3; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_4; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_5; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_6; // @[primitives.scala:118:30]
wire [3:0] _reduced4CExtra_reducedVec_0_T = _reduced4CExtra_T[3:0]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_0_T_1 = |_reduced4CExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_0 = _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_1_T = _reduced4CExtra_T[7:4]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_1_T_1 = |_reduced4CExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_1 = _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_2_T = _reduced4CExtra_T[11:8]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_2_T_1 = |_reduced4CExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_2 = _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_3_T = _reduced4CExtra_T[15:12]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_3_T_1 = |_reduced4CExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_3 = _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_4_T = _reduced4CExtra_T[19:16]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_4_T_1 = |_reduced4CExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_4 = _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_5_T = _reduced4CExtra_T[23:20]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_5_T_1 = |_reduced4CExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_5 = _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54]
wire [2:0] _reduced4CExtra_reducedVec_6_T = _reduced4CExtra_T[26:24]; // @[primitives.scala:123:15]
assign _reduced4CExtra_reducedVec_6_T_1 = |_reduced4CExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}]
assign reduced4CExtra_reducedVec_6 = _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57]
wire [1:0] reduced4CExtra_lo_hi = {reduced4CExtra_reducedVec_2, reduced4CExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20]
wire [2:0] reduced4CExtra_lo = {reduced4CExtra_lo_hi, reduced4CExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20]
wire [1:0] reduced4CExtra_hi_lo = {reduced4CExtra_reducedVec_4, reduced4CExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20]
wire [1:0] reduced4CExtra_hi_hi = {reduced4CExtra_reducedVec_6, reduced4CExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20]
wire [3:0] reduced4CExtra_hi = {reduced4CExtra_hi_hi, reduced4CExtra_hi_lo}; // @[primitives.scala:124:20]
wire [6:0] _reduced4CExtra_T_1 = {reduced4CExtra_hi, reduced4CExtra_lo}; // @[primitives.scala:124:20]
wire [4:0] _reduced4CExtra_T_2 = CAlignDist[6:2]; // @[MulAddRecFN.scala:112:12, :124:28]
wire [32:0] reduced4CExtra_shift = $signed(33'sh100000000 >>> _reduced4CExtra_T_2); // @[primitives.scala:76:56]
wire [5:0] _reduced4CExtra_T_3 = reduced4CExtra_shift[19:14]; // @[primitives.scala:76:56, :78:22]
wire [3:0] _reduced4CExtra_T_4 = _reduced4CExtra_T_3[3:0]; // @[primitives.scala:77:20, :78:22]
wire [1:0] _reduced4CExtra_T_5 = _reduced4CExtra_T_4[1:0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_6 = _reduced4CExtra_T_5[0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_7 = _reduced4CExtra_T_5[1]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_8 = {_reduced4CExtra_T_6, _reduced4CExtra_T_7}; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_9 = _reduced4CExtra_T_4[3:2]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_10 = _reduced4CExtra_T_9[0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_11 = _reduced4CExtra_T_9[1]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_12 = {_reduced4CExtra_T_10, _reduced4CExtra_T_11}; // @[primitives.scala:77:20]
wire [3:0] _reduced4CExtra_T_13 = {_reduced4CExtra_T_8, _reduced4CExtra_T_12}; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_14 = _reduced4CExtra_T_3[5:4]; // @[primitives.scala:77:20, :78:22]
wire _reduced4CExtra_T_15 = _reduced4CExtra_T_14[0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_16 = _reduced4CExtra_T_14[1]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_17 = {_reduced4CExtra_T_15, _reduced4CExtra_T_16}; // @[primitives.scala:77:20]
wire [5:0] _reduced4CExtra_T_18 = {_reduced4CExtra_T_13, _reduced4CExtra_T_17}; // @[primitives.scala:77:20]
wire [6:0] _reduced4CExtra_T_19 = {1'h0, _reduced4CExtra_T_1[5:0] & _reduced4CExtra_T_18}; // @[primitives.scala:77:20, :124:20]
wire reduced4CExtra = |_reduced4CExtra_T_19; // @[MulAddRecFN.scala:122:68, :130:11]
wire [74:0] _alignedSigC_T = mainAlignedSigC[77:3]; // @[MulAddRecFN.scala:120:100, :132:28]
wire [74:0] alignedSigC_hi = _alignedSigC_T; // @[MulAddRecFN.scala:132:{12,28}]
wire [2:0] _alignedSigC_T_1 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32]
wire [2:0] _alignedSigC_T_5 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32, :135:32]
wire _alignedSigC_T_2 = &_alignedSigC_T_1; // @[MulAddRecFN.scala:134:{32,39}]
wire _alignedSigC_T_3 = ~reduced4CExtra; // @[MulAddRecFN.scala:130:11, :134:47]
wire _alignedSigC_T_4 = _alignedSigC_T_2 & _alignedSigC_T_3; // @[MulAddRecFN.scala:134:{39,44,47}]
wire _alignedSigC_T_6 = |_alignedSigC_T_5; // @[MulAddRecFN.scala:135:{32,39}]
wire _alignedSigC_T_7 = _alignedSigC_T_6 | reduced4CExtra; // @[MulAddRecFN.scala:130:11, :135:{39,44}]
wire _alignedSigC_T_8 = doSubMags ? _alignedSigC_T_4 : _alignedSigC_T_7; // @[MulAddRecFN.scala:102:42, :133:16, :134:44, :135:44]
wire [75:0] alignedSigC = {alignedSigC_hi, _alignedSigC_T_8}; // @[MulAddRecFN.scala:132:12, :133:16]
assign io_mulAddA_0 = rawA_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23]
assign _io_mulAddC_T = alignedSigC[48:1]; // @[MulAddRecFN.scala:132:12, :143:30]
assign io_mulAddC_0 = _io_mulAddC_T; // @[MulAddRecFN.scala:71:7, :143:30]
wire _io_toPostMul_isSigNaNAny_T = rawA_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_1 = ~_io_toPostMul_isSigNaNAny_T; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_2 = rawA_isNaN & _io_toPostMul_isSigNaNAny_T_1; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_6 = _io_toPostMul_isSigNaNAny_T_2; // @[common.scala:82:46]
wire _io_toPostMul_isSigNaNAny_T_7 = rawC_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_8 = ~_io_toPostMul_isSigNaNAny_T_7; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_9 = rawC_isNaN & _io_toPostMul_isSigNaNAny_T_8; // @[rawFloatFromRecFN.scala:55:23]
assign _io_toPostMul_isSigNaNAny_T_10 = _io_toPostMul_isSigNaNAny_T_6 | _io_toPostMul_isSigNaNAny_T_9; // @[common.scala:82:46]
assign io_toPostMul_isSigNaNAny_0 = _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:71:7, :146:58]
assign io_toPostMul_isNaNAOrB_0 = _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:71:7, :148:42]
wire [11:0] _io_toPostMul_sExpSum_T = _GEN - 12'h18; // @[MulAddRecFN.scala:106:42, :158:53]
wire [10:0] _io_toPostMul_sExpSum_T_1 = _io_toPostMul_sExpSum_T[10:0]; // @[MulAddRecFN.scala:158:53]
wire [10:0] _io_toPostMul_sExpSum_T_2 = _io_toPostMul_sExpSum_T_1; // @[MulAddRecFN.scala:158:53]
wire [10:0] _io_toPostMul_sExpSum_T_3 = CIsDominant ? {rawC_sExp[9], rawC_sExp} : _io_toPostMul_sExpSum_T_2; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_sExpSum_0 = _io_toPostMul_sExpSum_T_3[9:0]; // @[MulAddRecFN.scala:71:7, :157:28, :158:12]
assign _io_toPostMul_CDom_CAlignDist_T = CAlignDist[4:0]; // @[MulAddRecFN.scala:112:12, :161:47]
assign io_toPostMul_CDom_CAlignDist_0 = _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:71:7, :161:47]
assign _io_toPostMul_highAlignedSigC_T = alignedSigC[74:49]; // @[MulAddRecFN.scala:132:12, :163:20]
assign io_toPostMul_highAlignedSigC_0 = _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:71:7, :163:20]
assign _io_toPostMul_bit0AlignedSigC_T = alignedSigC[0]; // @[MulAddRecFN.scala:132:12, :164:48]
assign io_toPostMul_bit0AlignedSigC_0 = _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:71:7, :164:48]
assign io_mulAddA = io_mulAddA_0; // @[MulAddRecFN.scala:71:7]
assign io_mulAddC = io_mulAddC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isSigNaNAny = io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isNaNAOrB = io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfA = io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroA = io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_signProd = io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isNaNC = io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfC = io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroC = io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_sExpSum = io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_doSubMags = io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_CIsDominant = io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_CDom_CAlignDist = io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_highAlignedSigC = io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_bit0AlignedSigC = io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_198 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_source_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_215
connect io_out_source_extend.clock, clock
connect io_out_source_extend.reset, reset
connect io_out_source_extend.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_source_extend.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_198( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_215 io_out_source_extend ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_99 :
input clock : Clock
input reset : Reset
output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `2` : UInt<1>[5], `1` : UInt<1>[5], `0` : UInt<1>[5]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `2` : UInt<1>[5], `1` : UInt<1>[5], `0` : UInt<1>[5]}}}, flip vcalloc_resp : { vc_sel : { `2` : UInt<1>[5], `1` : UInt<1>[5], `0` : UInt<1>[5]}}, flip out_credit_available : { `2` : UInt<1>[5], `1` : UInt<1>[5], `0` : UInt<1>[5]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[5], `1` : UInt<1>[5], `0` : UInt<1>[5]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<3>, sa_stall : UInt<3>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}}
inst input_buffer of InputBuffer_99
connect input_buffer.clock, clock
connect input_buffer.reset, reset
connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id
connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id
connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node
connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id
connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node
connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id
connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload
connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail
connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head
connect input_buffer.io.enq[0].valid, io.in.flit[0].valid
connect input_buffer.io.deq[0].ready, UInt<1>(0h0)
connect input_buffer.io.deq[1].ready, UInt<1>(0h0)
connect input_buffer.io.deq[2].ready, UInt<1>(0h0)
connect input_buffer.io.deq[3].ready, UInt<1>(0h0)
connect input_buffer.io.deq[4].ready, UInt<1>(0h0)
inst route_arbiter of Arbiter5_RouteComputerReq_27
connect route_arbiter.clock, clock
connect route_arbiter.reset, reset
connect io.router_req.bits, route_arbiter.io.out.bits
connect io.router_req.valid, route_arbiter.io.out.valid
connect route_arbiter.io.out.ready, io.router_req.ready
reg states : { g : UInt<3>, vc_sel : { `2` : UInt<1>[5], `1` : UInt<1>[5], `0` : UInt<1>[5]}, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, fifo_deps : UInt<5>}[5], clock
node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T :
node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h5))
node _T_2 = asUInt(reset)
node _T_3 = eq(_T_2, UInt<1>(0h0))
when _T_3 :
node _T_4 = eq(_T_1, UInt<1>(0h0))
when _T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf
assert(clock, _T_1, UInt<1>(0h1), "") : assert
node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0))
node _T_6 = asUInt(reset)
node _T_7 = eq(_T_6, UInt<1>(0h0))
when _T_7 :
node _T_8 = eq(_T_5, UInt<1>(0h0))
when _T_8 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1
assert(clock, _T_5, UInt<1>(0h1), "") : assert_1
node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hf))
node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1))
connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[3], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[4], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[3], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[4], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[3], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[4], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow
connect route_arbiter.io.in[0].valid, UInt<1>(0h0)
invalidate route_arbiter.io.in[0].bits.flow.egress_node_id
invalidate route_arbiter.io.in[0].bits.flow.egress_node
invalidate route_arbiter.io.in[0].bits.flow.ingress_node_id
invalidate route_arbiter.io.in[0].bits.flow.ingress_node
invalidate route_arbiter.io.in[0].bits.flow.vnet_id
invalidate route_arbiter.io.in[0].bits.src_virt_id
connect route_arbiter.io.in[1].valid, UInt<1>(0h0)
invalidate route_arbiter.io.in[1].bits.flow.egress_node_id
invalidate route_arbiter.io.in[1].bits.flow.egress_node
invalidate route_arbiter.io.in[1].bits.flow.ingress_node_id
invalidate route_arbiter.io.in[1].bits.flow.ingress_node
invalidate route_arbiter.io.in[1].bits.flow.vnet_id
invalidate route_arbiter.io.in[1].bits.src_virt_id
connect route_arbiter.io.in[2].valid, UInt<1>(0h0)
invalidate route_arbiter.io.in[2].bits.flow.egress_node_id
invalidate route_arbiter.io.in[2].bits.flow.egress_node
invalidate route_arbiter.io.in[2].bits.flow.ingress_node_id
invalidate route_arbiter.io.in[2].bits.flow.ingress_node
invalidate route_arbiter.io.in[2].bits.flow.vnet_id
invalidate route_arbiter.io.in[2].bits.src_virt_id
connect route_arbiter.io.in[3].valid, UInt<1>(0h0)
invalidate route_arbiter.io.in[3].bits.flow.egress_node_id
invalidate route_arbiter.io.in[3].bits.flow.egress_node
invalidate route_arbiter.io.in[3].bits.flow.ingress_node_id
invalidate route_arbiter.io.in[3].bits.flow.ingress_node
invalidate route_arbiter.io.in[3].bits.flow.vnet_id
invalidate route_arbiter.io.in[3].bits.src_virt_id
node _route_arbiter_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h1))
connect route_arbiter.io.in[4].valid, _route_arbiter_io_in_4_valid_T
connect route_arbiter.io.in[4].bits.flow.egress_node_id, states[4].flow.egress_node_id
connect route_arbiter.io.in[4].bits.flow.egress_node, states[4].flow.egress_node
connect route_arbiter.io.in[4].bits.flow.ingress_node_id, states[4].flow.ingress_node_id
connect route_arbiter.io.in[4].bits.flow.ingress_node, states[4].flow.ingress_node
connect route_arbiter.io.in[4].bits.flow.vnet_id, states[4].flow.vnet_id
connect route_arbiter.io.in[4].bits.src_virt_id, UInt<3>(0h4)
node _T_9 = and(route_arbiter.io.in[4].ready, route_arbiter.io.in[4].valid)
when _T_9 :
connect states[4].g, UInt<3>(0h2)
node _T_10 = and(io.router_req.ready, io.router_req.valid)
when _T_10 :
node _T_11 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1))
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2
assert(clock, _T_11, UInt<1>(0h1), "") : assert_2
connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2)
node _T_15 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id)
when _T_15 :
connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2`
node _T_16 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id)
when _T_16 :
connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2`
node _T_17 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id)
when _T_17 :
connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[2].vc_sel.`2`, io.router_resp.vc_sel.`2`
node _T_18 = eq(UInt<2>(0h3), io.router_req.bits.src_virt_id)
when _T_18 :
connect states[3].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[3].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[3].vc_sel.`2`, io.router_resp.vc_sel.`2`
node _T_19 = eq(UInt<3>(0h4), io.router_req.bits.src_virt_id)
when _T_19 :
connect states[4].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[4].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[4].vc_sel.`2`, io.router_resp.vc_sel.`2`
regreset mask : UInt<5>, clock, reset, UInt<5>(0h0)
wire vcalloc_reqs : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `2` : UInt<1>[5], `1` : UInt<1>[5], `0` : UInt<1>[5]}}[5]
wire vcalloc_vals : UInt<1>[5]
node vcalloc_filter_lo = cat(vcalloc_vals[1], vcalloc_vals[0])
node vcalloc_filter_hi_hi = cat(vcalloc_vals[4], vcalloc_vals[3])
node vcalloc_filter_hi = cat(vcalloc_filter_hi_hi, vcalloc_vals[2])
node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_filter_lo)
node vcalloc_filter_lo_1 = cat(vcalloc_vals[1], vcalloc_vals[0])
node vcalloc_filter_hi_hi_1 = cat(vcalloc_vals[4], vcalloc_vals[3])
node vcalloc_filter_hi_1 = cat(vcalloc_filter_hi_hi_1, vcalloc_vals[2])
node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_filter_lo_1)
node _vcalloc_filter_T_2 = not(mask)
node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2)
node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3)
node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0)
node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1)
node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2)
node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3)
node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4)
node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5)
node _vcalloc_filter_T_11 = bits(_vcalloc_filter_T_4, 6, 6)
node _vcalloc_filter_T_12 = bits(_vcalloc_filter_T_4, 7, 7)
node _vcalloc_filter_T_13 = bits(_vcalloc_filter_T_4, 8, 8)
node _vcalloc_filter_T_14 = bits(_vcalloc_filter_T_4, 9, 9)
node _vcalloc_filter_T_15 = mux(_vcalloc_filter_T_14, UInt<10>(0h200), UInt<10>(0h0))
node _vcalloc_filter_T_16 = mux(_vcalloc_filter_T_13, UInt<10>(0h100), _vcalloc_filter_T_15)
node _vcalloc_filter_T_17 = mux(_vcalloc_filter_T_12, UInt<10>(0h80), _vcalloc_filter_T_16)
node _vcalloc_filter_T_18 = mux(_vcalloc_filter_T_11, UInt<10>(0h40), _vcalloc_filter_T_17)
node _vcalloc_filter_T_19 = mux(_vcalloc_filter_T_10, UInt<10>(0h20), _vcalloc_filter_T_18)
node _vcalloc_filter_T_20 = mux(_vcalloc_filter_T_9, UInt<10>(0h10), _vcalloc_filter_T_19)
node _vcalloc_filter_T_21 = mux(_vcalloc_filter_T_8, UInt<10>(0h8), _vcalloc_filter_T_20)
node _vcalloc_filter_T_22 = mux(_vcalloc_filter_T_7, UInt<10>(0h4), _vcalloc_filter_T_21)
node _vcalloc_filter_T_23 = mux(_vcalloc_filter_T_6, UInt<10>(0h2), _vcalloc_filter_T_22)
node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<10>(0h1), _vcalloc_filter_T_23)
node _vcalloc_sel_T = bits(vcalloc_filter, 4, 0)
node _vcalloc_sel_T_1 = shr(vcalloc_filter, 5)
node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1)
node _T_20 = and(io.router_req.ready, io.router_req.valid)
when _T_20 :
node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id)
node _mask_T_1 = sub(_mask_T, UInt<1>(0h1))
node _mask_T_2 = tail(_mask_T_1, 1)
connect mask, _mask_T_2
else :
node _T_21 = or(vcalloc_vals[0], vcalloc_vals[1])
node _T_22 = or(_T_21, vcalloc_vals[2])
node _T_23 = or(_T_22, vcalloc_vals[3])
node _T_24 = or(_T_23, vcalloc_vals[4])
when _T_24 :
node _mask_T_3 = not(UInt<1>(0h0))
node _mask_T_4 = not(UInt<2>(0h0))
node _mask_T_5 = not(UInt<3>(0h0))
node _mask_T_6 = not(UInt<4>(0h0))
node _mask_T_7 = not(UInt<5>(0h0))
node _mask_T_8 = bits(vcalloc_sel, 0, 0)
node _mask_T_9 = bits(vcalloc_sel, 1, 1)
node _mask_T_10 = bits(vcalloc_sel, 2, 2)
node _mask_T_11 = bits(vcalloc_sel, 3, 3)
node _mask_T_12 = bits(vcalloc_sel, 4, 4)
node _mask_T_13 = mux(_mask_T_8, _mask_T_3, UInt<1>(0h0))
node _mask_T_14 = mux(_mask_T_9, _mask_T_4, UInt<1>(0h0))
node _mask_T_15 = mux(_mask_T_10, _mask_T_5, UInt<1>(0h0))
node _mask_T_16 = mux(_mask_T_11, _mask_T_6, UInt<1>(0h0))
node _mask_T_17 = mux(_mask_T_12, _mask_T_7, UInt<1>(0h0))
node _mask_T_18 = or(_mask_T_13, _mask_T_14)
node _mask_T_19 = or(_mask_T_18, _mask_T_15)
node _mask_T_20 = or(_mask_T_19, _mask_T_16)
node _mask_T_21 = or(_mask_T_20, _mask_T_17)
wire _mask_WIRE : UInt<5>
connect _mask_WIRE, _mask_T_21
connect mask, _mask_WIRE
node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1])
node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2])
node _io_vcalloc_req_valid_T_2 = or(_io_vcalloc_req_valid_T_1, vcalloc_vals[3])
node _io_vcalloc_req_valid_T_3 = or(_io_vcalloc_req_valid_T_2, vcalloc_vals[4])
connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3
node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0)
node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1)
node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2)
node _io_vcalloc_req_bits_T_3 = bits(vcalloc_sel, 3, 3)
node _io_vcalloc_req_bits_T_4 = bits(vcalloc_sel, 4, 4)
wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `2` : UInt<1>[5], `1` : UInt<1>[5], `0` : UInt<1>[5]}}
wire _io_vcalloc_req_bits_WIRE_1 : { `2` : UInt<1>[5], `1` : UInt<1>[5], `0` : UInt<1>[5]}
wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[5]
node _io_vcalloc_req_bits_T_5 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_6 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_7 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_10 = or(_io_vcalloc_req_bits_T_5, _io_vcalloc_req_bits_T_6)
node _io_vcalloc_req_bits_T_11 = or(_io_vcalloc_req_bits_T_10, _io_vcalloc_req_bits_T_7)
node _io_vcalloc_req_bits_T_12 = or(_io_vcalloc_req_bits_T_11, _io_vcalloc_req_bits_T_8)
node _io_vcalloc_req_bits_T_13 = or(_io_vcalloc_req_bits_T_12, _io_vcalloc_req_bits_T_9)
wire _io_vcalloc_req_bits_WIRE_3 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_13
connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3
node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_16 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_17 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_18 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_19 = or(_io_vcalloc_req_bits_T_14, _io_vcalloc_req_bits_T_15)
node _io_vcalloc_req_bits_T_20 = or(_io_vcalloc_req_bits_T_19, _io_vcalloc_req_bits_T_16)
node _io_vcalloc_req_bits_T_21 = or(_io_vcalloc_req_bits_T_20, _io_vcalloc_req_bits_T_17)
node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_21, _io_vcalloc_req_bits_T_18)
wire _io_vcalloc_req_bits_WIRE_4 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_22
connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4
node _io_vcalloc_req_bits_T_23 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_24 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_25 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_26 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_27 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_28 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_24)
node _io_vcalloc_req_bits_T_29 = or(_io_vcalloc_req_bits_T_28, _io_vcalloc_req_bits_T_25)
node _io_vcalloc_req_bits_T_30 = or(_io_vcalloc_req_bits_T_29, _io_vcalloc_req_bits_T_26)
node _io_vcalloc_req_bits_T_31 = or(_io_vcalloc_req_bits_T_30, _io_vcalloc_req_bits_T_27)
wire _io_vcalloc_req_bits_WIRE_5 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_31
connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5
node _io_vcalloc_req_bits_T_32 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_33 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_34 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_35 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_36 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_32, _io_vcalloc_req_bits_T_33)
node _io_vcalloc_req_bits_T_38 = or(_io_vcalloc_req_bits_T_37, _io_vcalloc_req_bits_T_34)
node _io_vcalloc_req_bits_T_39 = or(_io_vcalloc_req_bits_T_38, _io_vcalloc_req_bits_T_35)
node _io_vcalloc_req_bits_T_40 = or(_io_vcalloc_req_bits_T_39, _io_vcalloc_req_bits_T_36)
wire _io_vcalloc_req_bits_WIRE_6 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_6, _io_vcalloc_req_bits_T_40
connect _io_vcalloc_req_bits_WIRE_2[3], _io_vcalloc_req_bits_WIRE_6
node _io_vcalloc_req_bits_T_41 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_42 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_43 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_44 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_45 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_41, _io_vcalloc_req_bits_T_42)
node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_43)
node _io_vcalloc_req_bits_T_48 = or(_io_vcalloc_req_bits_T_47, _io_vcalloc_req_bits_T_44)
node _io_vcalloc_req_bits_T_49 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_45)
wire _io_vcalloc_req_bits_WIRE_7 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_49
connect _io_vcalloc_req_bits_WIRE_2[4], _io_vcalloc_req_bits_WIRE_7
connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2
wire _io_vcalloc_req_bits_WIRE_8 : UInt<1>[5]
node _io_vcalloc_req_bits_T_50 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_51 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_52 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_55 = or(_io_vcalloc_req_bits_T_50, _io_vcalloc_req_bits_T_51)
node _io_vcalloc_req_bits_T_56 = or(_io_vcalloc_req_bits_T_55, _io_vcalloc_req_bits_T_52)
node _io_vcalloc_req_bits_T_57 = or(_io_vcalloc_req_bits_T_56, _io_vcalloc_req_bits_T_53)
node _io_vcalloc_req_bits_T_58 = or(_io_vcalloc_req_bits_T_57, _io_vcalloc_req_bits_T_54)
wire _io_vcalloc_req_bits_WIRE_9 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_58
connect _io_vcalloc_req_bits_WIRE_8[0], _io_vcalloc_req_bits_WIRE_9
node _io_vcalloc_req_bits_T_59 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_60 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_61 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_62 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_63 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_64 = or(_io_vcalloc_req_bits_T_59, _io_vcalloc_req_bits_T_60)
node _io_vcalloc_req_bits_T_65 = or(_io_vcalloc_req_bits_T_64, _io_vcalloc_req_bits_T_61)
node _io_vcalloc_req_bits_T_66 = or(_io_vcalloc_req_bits_T_65, _io_vcalloc_req_bits_T_62)
node _io_vcalloc_req_bits_T_67 = or(_io_vcalloc_req_bits_T_66, _io_vcalloc_req_bits_T_63)
wire _io_vcalloc_req_bits_WIRE_10 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_10, _io_vcalloc_req_bits_T_67
connect _io_vcalloc_req_bits_WIRE_8[1], _io_vcalloc_req_bits_WIRE_10
node _io_vcalloc_req_bits_T_68 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_69 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_70 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_71 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_72 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_73 = or(_io_vcalloc_req_bits_T_68, _io_vcalloc_req_bits_T_69)
node _io_vcalloc_req_bits_T_74 = or(_io_vcalloc_req_bits_T_73, _io_vcalloc_req_bits_T_70)
node _io_vcalloc_req_bits_T_75 = or(_io_vcalloc_req_bits_T_74, _io_vcalloc_req_bits_T_71)
node _io_vcalloc_req_bits_T_76 = or(_io_vcalloc_req_bits_T_75, _io_vcalloc_req_bits_T_72)
wire _io_vcalloc_req_bits_WIRE_11 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_11, _io_vcalloc_req_bits_T_76
connect _io_vcalloc_req_bits_WIRE_8[2], _io_vcalloc_req_bits_WIRE_11
node _io_vcalloc_req_bits_T_77 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_78 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_79 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_80 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_81 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_77, _io_vcalloc_req_bits_T_78)
node _io_vcalloc_req_bits_T_83 = or(_io_vcalloc_req_bits_T_82, _io_vcalloc_req_bits_T_79)
node _io_vcalloc_req_bits_T_84 = or(_io_vcalloc_req_bits_T_83, _io_vcalloc_req_bits_T_80)
node _io_vcalloc_req_bits_T_85 = or(_io_vcalloc_req_bits_T_84, _io_vcalloc_req_bits_T_81)
wire _io_vcalloc_req_bits_WIRE_12 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_85
connect _io_vcalloc_req_bits_WIRE_8[3], _io_vcalloc_req_bits_WIRE_12
node _io_vcalloc_req_bits_T_86 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_87 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_88 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_89 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_90 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_91 = or(_io_vcalloc_req_bits_T_86, _io_vcalloc_req_bits_T_87)
node _io_vcalloc_req_bits_T_92 = or(_io_vcalloc_req_bits_T_91, _io_vcalloc_req_bits_T_88)
node _io_vcalloc_req_bits_T_93 = or(_io_vcalloc_req_bits_T_92, _io_vcalloc_req_bits_T_89)
node _io_vcalloc_req_bits_T_94 = or(_io_vcalloc_req_bits_T_93, _io_vcalloc_req_bits_T_90)
wire _io_vcalloc_req_bits_WIRE_13 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_13, _io_vcalloc_req_bits_T_94
connect _io_vcalloc_req_bits_WIRE_8[4], _io_vcalloc_req_bits_WIRE_13
connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_8
wire _io_vcalloc_req_bits_WIRE_14 : UInt<1>[5]
node _io_vcalloc_req_bits_T_95 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_96 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_97 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_98 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_99 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_100 = or(_io_vcalloc_req_bits_T_95, _io_vcalloc_req_bits_T_96)
node _io_vcalloc_req_bits_T_101 = or(_io_vcalloc_req_bits_T_100, _io_vcalloc_req_bits_T_97)
node _io_vcalloc_req_bits_T_102 = or(_io_vcalloc_req_bits_T_101, _io_vcalloc_req_bits_T_98)
node _io_vcalloc_req_bits_T_103 = or(_io_vcalloc_req_bits_T_102, _io_vcalloc_req_bits_T_99)
wire _io_vcalloc_req_bits_WIRE_15 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_103
connect _io_vcalloc_req_bits_WIRE_14[0], _io_vcalloc_req_bits_WIRE_15
node _io_vcalloc_req_bits_T_104 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_105 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_106 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_107 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_108 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_109 = or(_io_vcalloc_req_bits_T_104, _io_vcalloc_req_bits_T_105)
node _io_vcalloc_req_bits_T_110 = or(_io_vcalloc_req_bits_T_109, _io_vcalloc_req_bits_T_106)
node _io_vcalloc_req_bits_T_111 = or(_io_vcalloc_req_bits_T_110, _io_vcalloc_req_bits_T_107)
node _io_vcalloc_req_bits_T_112 = or(_io_vcalloc_req_bits_T_111, _io_vcalloc_req_bits_T_108)
wire _io_vcalloc_req_bits_WIRE_16 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_112
connect _io_vcalloc_req_bits_WIRE_14[1], _io_vcalloc_req_bits_WIRE_16
node _io_vcalloc_req_bits_T_113 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_114 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_115 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_116 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_117 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_118 = or(_io_vcalloc_req_bits_T_113, _io_vcalloc_req_bits_T_114)
node _io_vcalloc_req_bits_T_119 = or(_io_vcalloc_req_bits_T_118, _io_vcalloc_req_bits_T_115)
node _io_vcalloc_req_bits_T_120 = or(_io_vcalloc_req_bits_T_119, _io_vcalloc_req_bits_T_116)
node _io_vcalloc_req_bits_T_121 = or(_io_vcalloc_req_bits_T_120, _io_vcalloc_req_bits_T_117)
wire _io_vcalloc_req_bits_WIRE_17 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_17, _io_vcalloc_req_bits_T_121
connect _io_vcalloc_req_bits_WIRE_14[2], _io_vcalloc_req_bits_WIRE_17
node _io_vcalloc_req_bits_T_122 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_123 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_124 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_125 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_126 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_127 = or(_io_vcalloc_req_bits_T_122, _io_vcalloc_req_bits_T_123)
node _io_vcalloc_req_bits_T_128 = or(_io_vcalloc_req_bits_T_127, _io_vcalloc_req_bits_T_124)
node _io_vcalloc_req_bits_T_129 = or(_io_vcalloc_req_bits_T_128, _io_vcalloc_req_bits_T_125)
node _io_vcalloc_req_bits_T_130 = or(_io_vcalloc_req_bits_T_129, _io_vcalloc_req_bits_T_126)
wire _io_vcalloc_req_bits_WIRE_18 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_130
connect _io_vcalloc_req_bits_WIRE_14[3], _io_vcalloc_req_bits_WIRE_18
node _io_vcalloc_req_bits_T_131 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_132 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_133 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_134 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_135 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_136 = or(_io_vcalloc_req_bits_T_131, _io_vcalloc_req_bits_T_132)
node _io_vcalloc_req_bits_T_137 = or(_io_vcalloc_req_bits_T_136, _io_vcalloc_req_bits_T_133)
node _io_vcalloc_req_bits_T_138 = or(_io_vcalloc_req_bits_T_137, _io_vcalloc_req_bits_T_134)
node _io_vcalloc_req_bits_T_139 = or(_io_vcalloc_req_bits_T_138, _io_vcalloc_req_bits_T_135)
wire _io_vcalloc_req_bits_WIRE_19 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_139
connect _io_vcalloc_req_bits_WIRE_14[4], _io_vcalloc_req_bits_WIRE_19
connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_14
connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1
node _io_vcalloc_req_bits_T_140 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_141 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_142 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_143 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_144 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_145 = or(_io_vcalloc_req_bits_T_140, _io_vcalloc_req_bits_T_141)
node _io_vcalloc_req_bits_T_146 = or(_io_vcalloc_req_bits_T_145, _io_vcalloc_req_bits_T_142)
node _io_vcalloc_req_bits_T_147 = or(_io_vcalloc_req_bits_T_146, _io_vcalloc_req_bits_T_143)
node _io_vcalloc_req_bits_T_148 = or(_io_vcalloc_req_bits_T_147, _io_vcalloc_req_bits_T_144)
wire _io_vcalloc_req_bits_WIRE_20 : UInt<3>
connect _io_vcalloc_req_bits_WIRE_20, _io_vcalloc_req_bits_T_148
connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_20
wire _io_vcalloc_req_bits_WIRE_21 : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}
node _io_vcalloc_req_bits_T_149 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_150 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_151 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_152 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_153 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_154 = or(_io_vcalloc_req_bits_T_149, _io_vcalloc_req_bits_T_150)
node _io_vcalloc_req_bits_T_155 = or(_io_vcalloc_req_bits_T_154, _io_vcalloc_req_bits_T_151)
node _io_vcalloc_req_bits_T_156 = or(_io_vcalloc_req_bits_T_155, _io_vcalloc_req_bits_T_152)
node _io_vcalloc_req_bits_T_157 = or(_io_vcalloc_req_bits_T_156, _io_vcalloc_req_bits_T_153)
wire _io_vcalloc_req_bits_WIRE_22 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_22, _io_vcalloc_req_bits_T_157
connect _io_vcalloc_req_bits_WIRE_21.egress_node_id, _io_vcalloc_req_bits_WIRE_22
node _io_vcalloc_req_bits_T_158 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_159 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_160 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_161 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_162 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_163 = or(_io_vcalloc_req_bits_T_158, _io_vcalloc_req_bits_T_159)
node _io_vcalloc_req_bits_T_164 = or(_io_vcalloc_req_bits_T_163, _io_vcalloc_req_bits_T_160)
node _io_vcalloc_req_bits_T_165 = or(_io_vcalloc_req_bits_T_164, _io_vcalloc_req_bits_T_161)
node _io_vcalloc_req_bits_T_166 = or(_io_vcalloc_req_bits_T_165, _io_vcalloc_req_bits_T_162)
wire _io_vcalloc_req_bits_WIRE_23 : UInt<5>
connect _io_vcalloc_req_bits_WIRE_23, _io_vcalloc_req_bits_T_166
connect _io_vcalloc_req_bits_WIRE_21.egress_node, _io_vcalloc_req_bits_WIRE_23
node _io_vcalloc_req_bits_T_167 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_168 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_169 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_170 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_171 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_172 = or(_io_vcalloc_req_bits_T_167, _io_vcalloc_req_bits_T_168)
node _io_vcalloc_req_bits_T_173 = or(_io_vcalloc_req_bits_T_172, _io_vcalloc_req_bits_T_169)
node _io_vcalloc_req_bits_T_174 = or(_io_vcalloc_req_bits_T_173, _io_vcalloc_req_bits_T_170)
node _io_vcalloc_req_bits_T_175 = or(_io_vcalloc_req_bits_T_174, _io_vcalloc_req_bits_T_171)
wire _io_vcalloc_req_bits_WIRE_24 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_24, _io_vcalloc_req_bits_T_175
connect _io_vcalloc_req_bits_WIRE_21.ingress_node_id, _io_vcalloc_req_bits_WIRE_24
node _io_vcalloc_req_bits_T_176 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_177 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_178 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_179 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_180 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_181 = or(_io_vcalloc_req_bits_T_176, _io_vcalloc_req_bits_T_177)
node _io_vcalloc_req_bits_T_182 = or(_io_vcalloc_req_bits_T_181, _io_vcalloc_req_bits_T_178)
node _io_vcalloc_req_bits_T_183 = or(_io_vcalloc_req_bits_T_182, _io_vcalloc_req_bits_T_179)
node _io_vcalloc_req_bits_T_184 = or(_io_vcalloc_req_bits_T_183, _io_vcalloc_req_bits_T_180)
wire _io_vcalloc_req_bits_WIRE_25 : UInt<5>
connect _io_vcalloc_req_bits_WIRE_25, _io_vcalloc_req_bits_T_184
connect _io_vcalloc_req_bits_WIRE_21.ingress_node, _io_vcalloc_req_bits_WIRE_25
node _io_vcalloc_req_bits_T_185 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_186 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_187 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_188 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_189 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_190 = or(_io_vcalloc_req_bits_T_185, _io_vcalloc_req_bits_T_186)
node _io_vcalloc_req_bits_T_191 = or(_io_vcalloc_req_bits_T_190, _io_vcalloc_req_bits_T_187)
node _io_vcalloc_req_bits_T_192 = or(_io_vcalloc_req_bits_T_191, _io_vcalloc_req_bits_T_188)
node _io_vcalloc_req_bits_T_193 = or(_io_vcalloc_req_bits_T_192, _io_vcalloc_req_bits_T_189)
wire _io_vcalloc_req_bits_WIRE_26 : UInt<3>
connect _io_vcalloc_req_bits_WIRE_26, _io_vcalloc_req_bits_T_193
connect _io_vcalloc_req_bits_WIRE_21.vnet_id, _io_vcalloc_req_bits_WIRE_26
connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_21
connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE
connect vcalloc_vals[0], UInt<1>(0h0)
invalidate vcalloc_reqs[0].vc_sel.`0`[0]
invalidate vcalloc_reqs[0].vc_sel.`0`[1]
invalidate vcalloc_reqs[0].vc_sel.`0`[2]
invalidate vcalloc_reqs[0].vc_sel.`0`[3]
invalidate vcalloc_reqs[0].vc_sel.`0`[4]
invalidate vcalloc_reqs[0].vc_sel.`1`[0]
invalidate vcalloc_reqs[0].vc_sel.`1`[1]
invalidate vcalloc_reqs[0].vc_sel.`1`[2]
invalidate vcalloc_reqs[0].vc_sel.`1`[3]
invalidate vcalloc_reqs[0].vc_sel.`1`[4]
invalidate vcalloc_reqs[0].vc_sel.`2`[0]
invalidate vcalloc_reqs[0].vc_sel.`2`[1]
invalidate vcalloc_reqs[0].vc_sel.`2`[2]
invalidate vcalloc_reqs[0].vc_sel.`2`[3]
invalidate vcalloc_reqs[0].vc_sel.`2`[4]
invalidate vcalloc_reqs[0].in_vc
invalidate vcalloc_reqs[0].flow.egress_node_id
invalidate vcalloc_reqs[0].flow.egress_node
invalidate vcalloc_reqs[0].flow.ingress_node_id
invalidate vcalloc_reqs[0].flow.ingress_node
invalidate vcalloc_reqs[0].flow.vnet_id
connect vcalloc_vals[1], UInt<1>(0h0)
invalidate vcalloc_reqs[1].vc_sel.`0`[0]
invalidate vcalloc_reqs[1].vc_sel.`0`[1]
invalidate vcalloc_reqs[1].vc_sel.`0`[2]
invalidate vcalloc_reqs[1].vc_sel.`0`[3]
invalidate vcalloc_reqs[1].vc_sel.`0`[4]
invalidate vcalloc_reqs[1].vc_sel.`1`[0]
invalidate vcalloc_reqs[1].vc_sel.`1`[1]
invalidate vcalloc_reqs[1].vc_sel.`1`[2]
invalidate vcalloc_reqs[1].vc_sel.`1`[3]
invalidate vcalloc_reqs[1].vc_sel.`1`[4]
invalidate vcalloc_reqs[1].vc_sel.`2`[0]
invalidate vcalloc_reqs[1].vc_sel.`2`[1]
invalidate vcalloc_reqs[1].vc_sel.`2`[2]
invalidate vcalloc_reqs[1].vc_sel.`2`[3]
invalidate vcalloc_reqs[1].vc_sel.`2`[4]
invalidate vcalloc_reqs[1].in_vc
invalidate vcalloc_reqs[1].flow.egress_node_id
invalidate vcalloc_reqs[1].flow.egress_node
invalidate vcalloc_reqs[1].flow.ingress_node_id
invalidate vcalloc_reqs[1].flow.ingress_node
invalidate vcalloc_reqs[1].flow.vnet_id
connect vcalloc_vals[2], UInt<1>(0h0)
invalidate vcalloc_reqs[2].vc_sel.`0`[0]
invalidate vcalloc_reqs[2].vc_sel.`0`[1]
invalidate vcalloc_reqs[2].vc_sel.`0`[2]
invalidate vcalloc_reqs[2].vc_sel.`0`[3]
invalidate vcalloc_reqs[2].vc_sel.`0`[4]
invalidate vcalloc_reqs[2].vc_sel.`1`[0]
invalidate vcalloc_reqs[2].vc_sel.`1`[1]
invalidate vcalloc_reqs[2].vc_sel.`1`[2]
invalidate vcalloc_reqs[2].vc_sel.`1`[3]
invalidate vcalloc_reqs[2].vc_sel.`1`[4]
invalidate vcalloc_reqs[2].vc_sel.`2`[0]
invalidate vcalloc_reqs[2].vc_sel.`2`[1]
invalidate vcalloc_reqs[2].vc_sel.`2`[2]
invalidate vcalloc_reqs[2].vc_sel.`2`[3]
invalidate vcalloc_reqs[2].vc_sel.`2`[4]
invalidate vcalloc_reqs[2].in_vc
invalidate vcalloc_reqs[2].flow.egress_node_id
invalidate vcalloc_reqs[2].flow.egress_node
invalidate vcalloc_reqs[2].flow.ingress_node_id
invalidate vcalloc_reqs[2].flow.ingress_node
invalidate vcalloc_reqs[2].flow.vnet_id
connect vcalloc_vals[3], UInt<1>(0h0)
invalidate vcalloc_reqs[3].vc_sel.`0`[0]
invalidate vcalloc_reqs[3].vc_sel.`0`[1]
invalidate vcalloc_reqs[3].vc_sel.`0`[2]
invalidate vcalloc_reqs[3].vc_sel.`0`[3]
invalidate vcalloc_reqs[3].vc_sel.`0`[4]
invalidate vcalloc_reqs[3].vc_sel.`1`[0]
invalidate vcalloc_reqs[3].vc_sel.`1`[1]
invalidate vcalloc_reqs[3].vc_sel.`1`[2]
invalidate vcalloc_reqs[3].vc_sel.`1`[3]
invalidate vcalloc_reqs[3].vc_sel.`1`[4]
invalidate vcalloc_reqs[3].vc_sel.`2`[0]
invalidate vcalloc_reqs[3].vc_sel.`2`[1]
invalidate vcalloc_reqs[3].vc_sel.`2`[2]
invalidate vcalloc_reqs[3].vc_sel.`2`[3]
invalidate vcalloc_reqs[3].vc_sel.`2`[4]
invalidate vcalloc_reqs[3].in_vc
invalidate vcalloc_reqs[3].flow.egress_node_id
invalidate vcalloc_reqs[3].flow.egress_node
invalidate vcalloc_reqs[3].flow.ingress_node_id
invalidate vcalloc_reqs[3].flow.ingress_node
invalidate vcalloc_reqs[3].flow.vnet_id
node _vcalloc_vals_4_T = eq(states[4].g, UInt<3>(0h2))
node _vcalloc_vals_4_T_1 = eq(states[4].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_4_T_2 = and(_vcalloc_vals_4_T, _vcalloc_vals_4_T_1)
connect vcalloc_vals[4], _vcalloc_vals_4_T_2
connect vcalloc_reqs[4].in_vc, UInt<3>(0h4)
connect vcalloc_reqs[4].vc_sel.`0`, states[4].vc_sel.`0`
connect vcalloc_reqs[4].vc_sel.`1`, states[4].vc_sel.`1`
connect vcalloc_reqs[4].vc_sel.`2`, states[4].vc_sel.`2`
connect vcalloc_reqs[4].flow, states[4].flow
node _T_25 = bits(vcalloc_sel, 4, 4)
node _T_26 = and(vcalloc_vals[4], _T_25)
node _T_27 = and(_T_26, io.vcalloc_req.ready)
when _T_27 :
connect states[4].g, UInt<3>(0h3)
node _io_debug_va_stall_T = add(vcalloc_vals[0], vcalloc_vals[1])
node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0)
node _io_debug_va_stall_T_2 = add(vcalloc_vals[3], vcalloc_vals[4])
node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0)
node _io_debug_va_stall_T_4 = add(vcalloc_vals[2], _io_debug_va_stall_T_3)
node _io_debug_va_stall_T_5 = bits(_io_debug_va_stall_T_4, 1, 0)
node _io_debug_va_stall_T_6 = add(_io_debug_va_stall_T_1, _io_debug_va_stall_T_5)
node _io_debug_va_stall_T_7 = bits(_io_debug_va_stall_T_6, 2, 0)
node _io_debug_va_stall_T_8 = sub(_io_debug_va_stall_T_7, io.vcalloc_req.ready)
node _io_debug_va_stall_T_9 = tail(_io_debug_va_stall_T_8, 1)
connect io.debug.va_stall, _io_debug_va_stall_T_9
node _T_28 = and(io.vcalloc_req.ready, io.vcalloc_req.valid)
when _T_28 :
node _T_29 = bits(vcalloc_sel, 0, 0)
when _T_29 :
connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[0].g, UInt<3>(0h3)
node _T_30 = eq(states[0].g, UInt<3>(0h2))
node _T_31 = asUInt(reset)
node _T_32 = eq(_T_31, UInt<1>(0h0))
when _T_32 :
node _T_33 = eq(_T_30, UInt<1>(0h0))
when _T_33 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_3
assert(clock, _T_30, UInt<1>(0h1), "") : assert_3
node _T_34 = bits(vcalloc_sel, 1, 1)
when _T_34 :
connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[1].g, UInt<3>(0h3)
node _T_35 = eq(states[1].g, UInt<3>(0h2))
node _T_36 = asUInt(reset)
node _T_37 = eq(_T_36, UInt<1>(0h0))
when _T_37 :
node _T_38 = eq(_T_35, UInt<1>(0h0))
when _T_38 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_4
assert(clock, _T_35, UInt<1>(0h1), "") : assert_4
node _T_39 = bits(vcalloc_sel, 2, 2)
when _T_39 :
connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[2].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[2].g, UInt<3>(0h3)
node _T_40 = eq(states[2].g, UInt<3>(0h2))
node _T_41 = asUInt(reset)
node _T_42 = eq(_T_41, UInt<1>(0h0))
when _T_42 :
node _T_43 = eq(_T_40, UInt<1>(0h0))
when _T_43 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_5
assert(clock, _T_40, UInt<1>(0h1), "") : assert_5
node _T_44 = bits(vcalloc_sel, 3, 3)
when _T_44 :
connect states[3].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[3].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[3].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[3].g, UInt<3>(0h3)
node _T_45 = eq(states[3].g, UInt<3>(0h2))
node _T_46 = asUInt(reset)
node _T_47 = eq(_T_46, UInt<1>(0h0))
when _T_47 :
node _T_48 = eq(_T_45, UInt<1>(0h0))
when _T_48 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_6
assert(clock, _T_45, UInt<1>(0h1), "") : assert_6
node _T_49 = bits(vcalloc_sel, 4, 4)
when _T_49 :
connect states[4].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[4].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[4].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[4].g, UInt<3>(0h3)
node _T_50 = eq(states[4].g, UInt<3>(0h2))
node _T_51 = asUInt(reset)
node _T_52 = eq(_T_51, UInt<1>(0h0))
when _T_52 :
node _T_53 = eq(_T_50, UInt<1>(0h0))
when _T_53 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_7
assert(clock, _T_50, UInt<1>(0h1), "") : assert_7
inst salloc_arb of SwitchArbiter_256
connect salloc_arb.clock, clock
connect salloc_arb.reset, reset
connect salloc_arb.io.in[0].valid, UInt<1>(0h0)
invalidate salloc_arb.io.in[0].bits.tail
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[0]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[1]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[2]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[3]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[4]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[0]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[1]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[2]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[3]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[4]
invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[0]
invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[1]
invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[2]
invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[3]
invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[4]
connect salloc_arb.io.in[1].valid, UInt<1>(0h0)
invalidate salloc_arb.io.in[1].bits.tail
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[0]
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[1]
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[2]
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[3]
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[4]
invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[0]
invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[1]
invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[2]
invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[3]
invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[4]
invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[0]
invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[1]
invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[2]
invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[3]
invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[4]
connect salloc_arb.io.in[2].valid, UInt<1>(0h0)
invalidate salloc_arb.io.in[2].bits.tail
invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[0]
invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[1]
invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[2]
invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[3]
invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[4]
invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[0]
invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[1]
invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[2]
invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[3]
invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[4]
invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[0]
invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[1]
invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[2]
invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[3]
invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[4]
connect salloc_arb.io.in[3].valid, UInt<1>(0h0)
invalidate salloc_arb.io.in[3].bits.tail
invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[0]
invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[1]
invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[2]
invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[3]
invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[4]
invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[0]
invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[1]
invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[2]
invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[3]
invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[4]
invalidate salloc_arb.io.in[3].bits.vc_sel.`2`[0]
invalidate salloc_arb.io.in[3].bits.vc_sel.`2`[1]
invalidate salloc_arb.io.in[3].bits.vc_sel.`2`[2]
invalidate salloc_arb.io.in[3].bits.vc_sel.`2`[3]
invalidate salloc_arb.io.in[3].bits.vc_sel.`2`[4]
node credit_available_lo = cat(states[4].vc_sel.`0`[1], states[4].vc_sel.`0`[0])
node credit_available_hi_hi = cat(states[4].vc_sel.`0`[4], states[4].vc_sel.`0`[3])
node credit_available_hi = cat(credit_available_hi_hi, states[4].vc_sel.`0`[2])
node _credit_available_T = cat(credit_available_hi, credit_available_lo)
node credit_available_lo_1 = cat(states[4].vc_sel.`1`[1], states[4].vc_sel.`1`[0])
node credit_available_hi_hi_1 = cat(states[4].vc_sel.`1`[4], states[4].vc_sel.`1`[3])
node credit_available_hi_1 = cat(credit_available_hi_hi_1, states[4].vc_sel.`1`[2])
node _credit_available_T_1 = cat(credit_available_hi_1, credit_available_lo_1)
node credit_available_lo_2 = cat(states[4].vc_sel.`2`[1], states[4].vc_sel.`2`[0])
node credit_available_hi_hi_2 = cat(states[4].vc_sel.`2`[4], states[4].vc_sel.`2`[3])
node credit_available_hi_2 = cat(credit_available_hi_hi_2, states[4].vc_sel.`2`[2])
node _credit_available_T_2 = cat(credit_available_hi_2, credit_available_lo_2)
node credit_available_hi_3 = cat(_credit_available_T_2, _credit_available_T_1)
node _credit_available_T_3 = cat(credit_available_hi_3, _credit_available_T)
node credit_available_lo_3 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_hi_hi_3 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3])
node credit_available_hi_4 = cat(credit_available_hi_hi_3, io.out_credit_available.`0`[2])
node _credit_available_T_4 = cat(credit_available_hi_4, credit_available_lo_3)
node credit_available_lo_4 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_hi_hi_4 = cat(io.out_credit_available.`1`[4], io.out_credit_available.`1`[3])
node credit_available_hi_5 = cat(credit_available_hi_hi_4, io.out_credit_available.`1`[2])
node _credit_available_T_5 = cat(credit_available_hi_5, credit_available_lo_4)
node credit_available_lo_5 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_hi_hi_5 = cat(io.out_credit_available.`2`[4], io.out_credit_available.`2`[3])
node credit_available_hi_6 = cat(credit_available_hi_hi_5, io.out_credit_available.`2`[2])
node _credit_available_T_6 = cat(credit_available_hi_6, credit_available_lo_5)
node credit_available_hi_7 = cat(_credit_available_T_6, _credit_available_T_5)
node _credit_available_T_7 = cat(credit_available_hi_7, _credit_available_T_4)
node _credit_available_T_8 = and(_credit_available_T_3, _credit_available_T_7)
node credit_available = neq(_credit_available_T_8, UInt<1>(0h0))
node _salloc_arb_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h3))
node _salloc_arb_io_in_4_valid_T_1 = and(_salloc_arb_io_in_4_valid_T, credit_available)
node _salloc_arb_io_in_4_valid_T_2 = and(_salloc_arb_io_in_4_valid_T_1, input_buffer.io.deq[4].valid)
connect salloc_arb.io.in[4].valid, _salloc_arb_io_in_4_valid_T_2
connect salloc_arb.io.in[4].bits.vc_sel.`0`[0], states[4].vc_sel.`0`[0]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[1], states[4].vc_sel.`0`[1]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[2], states[4].vc_sel.`0`[2]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[3], states[4].vc_sel.`0`[3]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[4], states[4].vc_sel.`0`[4]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[0], states[4].vc_sel.`1`[0]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[1], states[4].vc_sel.`1`[1]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[2], states[4].vc_sel.`1`[2]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[3], states[4].vc_sel.`1`[3]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[4], states[4].vc_sel.`1`[4]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[0], states[4].vc_sel.`2`[0]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[1], states[4].vc_sel.`2`[1]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[2], states[4].vc_sel.`2`[2]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[3], states[4].vc_sel.`2`[3]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[4], states[4].vc_sel.`2`[4]
connect salloc_arb.io.in[4].bits.tail, input_buffer.io.deq[4].bits.tail
node _T_54 = and(salloc_arb.io.in[4].ready, salloc_arb.io.in[4].valid)
node _T_55 = and(_T_54, input_buffer.io.deq[4].bits.tail)
when _T_55 :
connect states[4].g, UInt<3>(0h0)
connect input_buffer.io.deq[4].ready, salloc_arb.io.in[4].ready
node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T)
node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2)
node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4)
node _io_debug_sa_stall_T_6 = eq(salloc_arb.io.in[3].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_7 = and(salloc_arb.io.in[3].valid, _io_debug_sa_stall_T_6)
node _io_debug_sa_stall_T_8 = eq(salloc_arb.io.in[4].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_9 = and(salloc_arb.io.in[4].valid, _io_debug_sa_stall_T_8)
node _io_debug_sa_stall_T_10 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_3)
node _io_debug_sa_stall_T_11 = bits(_io_debug_sa_stall_T_10, 1, 0)
node _io_debug_sa_stall_T_12 = add(_io_debug_sa_stall_T_7, _io_debug_sa_stall_T_9)
node _io_debug_sa_stall_T_13 = bits(_io_debug_sa_stall_T_12, 1, 0)
node _io_debug_sa_stall_T_14 = add(_io_debug_sa_stall_T_5, _io_debug_sa_stall_T_13)
node _io_debug_sa_stall_T_15 = bits(_io_debug_sa_stall_T_14, 1, 0)
node _io_debug_sa_stall_T_16 = add(_io_debug_sa_stall_T_11, _io_debug_sa_stall_T_15)
node _io_debug_sa_stall_T_17 = bits(_io_debug_sa_stall_T_16, 2, 0)
connect io.debug.sa_stall, _io_debug_sa_stall_T_17
connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits
connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid
connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready
when io.block :
connect salloc_arb.io.out[0].ready, UInt<1>(0h0)
connect io.salloc_req[0].valid, UInt<1>(0h0)
reg salloc_outs : { valid : UInt<1>, vid : UInt<3>, out_vid : UInt<3>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], clock
node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0))
connect io.in.credit_return, _io_in_credit_return_T_1
node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _io_in_vc_free_T_4 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _io_in_vc_free_T_5 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _io_in_vc_free_T_6 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_7 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_8 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_9 = mux(_io_in_vc_free_T_4, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_10 = mux(_io_in_vc_free_T_5, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_11 = or(_io_in_vc_free_T_6, _io_in_vc_free_T_7)
node _io_in_vc_free_T_12 = or(_io_in_vc_free_T_11, _io_in_vc_free_T_8)
node _io_in_vc_free_T_13 = or(_io_in_vc_free_T_12, _io_in_vc_free_T_9)
node _io_in_vc_free_T_14 = or(_io_in_vc_free_T_13, _io_in_vc_free_T_10)
wire _io_in_vc_free_WIRE : UInt<1>
connect _io_in_vc_free_WIRE, _io_in_vc_free_T_14
node _io_in_vc_free_T_15 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE)
node _io_in_vc_free_T_16 = mux(_io_in_vc_free_T_15, salloc_arb.io.chosen_oh[0], UInt<1>(0h0))
connect io.in.vc_free, _io_in_vc_free_T_16
node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
connect salloc_outs[0].valid, _salloc_outs_0_valid_T
node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 3, 0)
node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi)
node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo)
node salloc_outs_0_vid_hi_1 = bits(_salloc_outs_0_vid_T_1, 3, 2)
node salloc_outs_0_vid_lo_1 = bits(_salloc_outs_0_vid_T_1, 1, 0)
node _salloc_outs_0_vid_T_2 = orr(salloc_outs_0_vid_hi_1)
node _salloc_outs_0_vid_T_3 = or(salloc_outs_0_vid_hi_1, salloc_outs_0_vid_lo_1)
node _salloc_outs_0_vid_T_4 = bits(_salloc_outs_0_vid_T_3, 1, 1)
node _salloc_outs_0_vid_T_5 = cat(_salloc_outs_0_vid_T_2, _salloc_outs_0_vid_T_4)
node _salloc_outs_0_vid_T_6 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_5)
connect salloc_outs[0].vid, _salloc_outs_0_vid_T_6
node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _vc_sel_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _vc_sel_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
wire vc_sel : { `2` : UInt<1>[5], `1` : UInt<1>[5], `0` : UInt<1>[5]}
wire _vc_sel_WIRE : UInt<1>[5]
node _vc_sel_T_5 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_6 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_7 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_8 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_9 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_10 = or(_vc_sel_T_5, _vc_sel_T_6)
node _vc_sel_T_11 = or(_vc_sel_T_10, _vc_sel_T_7)
node _vc_sel_T_12 = or(_vc_sel_T_11, _vc_sel_T_8)
node _vc_sel_T_13 = or(_vc_sel_T_12, _vc_sel_T_9)
wire _vc_sel_WIRE_1 : UInt<1>
connect _vc_sel_WIRE_1, _vc_sel_T_13
connect _vc_sel_WIRE[0], _vc_sel_WIRE_1
node _vc_sel_T_14 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_15 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_16 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_17 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_18 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_19 = or(_vc_sel_T_14, _vc_sel_T_15)
node _vc_sel_T_20 = or(_vc_sel_T_19, _vc_sel_T_16)
node _vc_sel_T_21 = or(_vc_sel_T_20, _vc_sel_T_17)
node _vc_sel_T_22 = or(_vc_sel_T_21, _vc_sel_T_18)
wire _vc_sel_WIRE_2 : UInt<1>
connect _vc_sel_WIRE_2, _vc_sel_T_22
connect _vc_sel_WIRE[1], _vc_sel_WIRE_2
node _vc_sel_T_23 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_24 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_25 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_26 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_27 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_28 = or(_vc_sel_T_23, _vc_sel_T_24)
node _vc_sel_T_29 = or(_vc_sel_T_28, _vc_sel_T_25)
node _vc_sel_T_30 = or(_vc_sel_T_29, _vc_sel_T_26)
node _vc_sel_T_31 = or(_vc_sel_T_30, _vc_sel_T_27)
wire _vc_sel_WIRE_3 : UInt<1>
connect _vc_sel_WIRE_3, _vc_sel_T_31
connect _vc_sel_WIRE[2], _vc_sel_WIRE_3
node _vc_sel_T_32 = mux(_vc_sel_T, states[0].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_33 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_34 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_35 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_36 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_37 = or(_vc_sel_T_32, _vc_sel_T_33)
node _vc_sel_T_38 = or(_vc_sel_T_37, _vc_sel_T_34)
node _vc_sel_T_39 = or(_vc_sel_T_38, _vc_sel_T_35)
node _vc_sel_T_40 = or(_vc_sel_T_39, _vc_sel_T_36)
wire _vc_sel_WIRE_4 : UInt<1>
connect _vc_sel_WIRE_4, _vc_sel_T_40
connect _vc_sel_WIRE[3], _vc_sel_WIRE_4
node _vc_sel_T_41 = mux(_vc_sel_T, states[0].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_42 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_43 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_44 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_45 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_46 = or(_vc_sel_T_41, _vc_sel_T_42)
node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_43)
node _vc_sel_T_48 = or(_vc_sel_T_47, _vc_sel_T_44)
node _vc_sel_T_49 = or(_vc_sel_T_48, _vc_sel_T_45)
wire _vc_sel_WIRE_5 : UInt<1>
connect _vc_sel_WIRE_5, _vc_sel_T_49
connect _vc_sel_WIRE[4], _vc_sel_WIRE_5
connect vc_sel.`0`, _vc_sel_WIRE
wire _vc_sel_WIRE_6 : UInt<1>[5]
node _vc_sel_T_50 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_51 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_52 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_53 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_54 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_55 = or(_vc_sel_T_50, _vc_sel_T_51)
node _vc_sel_T_56 = or(_vc_sel_T_55, _vc_sel_T_52)
node _vc_sel_T_57 = or(_vc_sel_T_56, _vc_sel_T_53)
node _vc_sel_T_58 = or(_vc_sel_T_57, _vc_sel_T_54)
wire _vc_sel_WIRE_7 : UInt<1>
connect _vc_sel_WIRE_7, _vc_sel_T_58
connect _vc_sel_WIRE_6[0], _vc_sel_WIRE_7
node _vc_sel_T_59 = mux(_vc_sel_T, states[0].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_60 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_61 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_62 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_63 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_64 = or(_vc_sel_T_59, _vc_sel_T_60)
node _vc_sel_T_65 = or(_vc_sel_T_64, _vc_sel_T_61)
node _vc_sel_T_66 = or(_vc_sel_T_65, _vc_sel_T_62)
node _vc_sel_T_67 = or(_vc_sel_T_66, _vc_sel_T_63)
wire _vc_sel_WIRE_8 : UInt<1>
connect _vc_sel_WIRE_8, _vc_sel_T_67
connect _vc_sel_WIRE_6[1], _vc_sel_WIRE_8
node _vc_sel_T_68 = mux(_vc_sel_T, states[0].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_69 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_70 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_71 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_72 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_73 = or(_vc_sel_T_68, _vc_sel_T_69)
node _vc_sel_T_74 = or(_vc_sel_T_73, _vc_sel_T_70)
node _vc_sel_T_75 = or(_vc_sel_T_74, _vc_sel_T_71)
node _vc_sel_T_76 = or(_vc_sel_T_75, _vc_sel_T_72)
wire _vc_sel_WIRE_9 : UInt<1>
connect _vc_sel_WIRE_9, _vc_sel_T_76
connect _vc_sel_WIRE_6[2], _vc_sel_WIRE_9
node _vc_sel_T_77 = mux(_vc_sel_T, states[0].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_78 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_79 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_80 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_81 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_82 = or(_vc_sel_T_77, _vc_sel_T_78)
node _vc_sel_T_83 = or(_vc_sel_T_82, _vc_sel_T_79)
node _vc_sel_T_84 = or(_vc_sel_T_83, _vc_sel_T_80)
node _vc_sel_T_85 = or(_vc_sel_T_84, _vc_sel_T_81)
wire _vc_sel_WIRE_10 : UInt<1>
connect _vc_sel_WIRE_10, _vc_sel_T_85
connect _vc_sel_WIRE_6[3], _vc_sel_WIRE_10
node _vc_sel_T_86 = mux(_vc_sel_T, states[0].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_87 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_88 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_89 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_90 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_91 = or(_vc_sel_T_86, _vc_sel_T_87)
node _vc_sel_T_92 = or(_vc_sel_T_91, _vc_sel_T_88)
node _vc_sel_T_93 = or(_vc_sel_T_92, _vc_sel_T_89)
node _vc_sel_T_94 = or(_vc_sel_T_93, _vc_sel_T_90)
wire _vc_sel_WIRE_11 : UInt<1>
connect _vc_sel_WIRE_11, _vc_sel_T_94
connect _vc_sel_WIRE_6[4], _vc_sel_WIRE_11
connect vc_sel.`1`, _vc_sel_WIRE_6
wire _vc_sel_WIRE_12 : UInt<1>[5]
node _vc_sel_T_95 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_96 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_97 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_98 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_99 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_100 = or(_vc_sel_T_95, _vc_sel_T_96)
node _vc_sel_T_101 = or(_vc_sel_T_100, _vc_sel_T_97)
node _vc_sel_T_102 = or(_vc_sel_T_101, _vc_sel_T_98)
node _vc_sel_T_103 = or(_vc_sel_T_102, _vc_sel_T_99)
wire _vc_sel_WIRE_13 : UInt<1>
connect _vc_sel_WIRE_13, _vc_sel_T_103
connect _vc_sel_WIRE_12[0], _vc_sel_WIRE_13
node _vc_sel_T_104 = mux(_vc_sel_T, states[0].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_105 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_106 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_107 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_108 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_109 = or(_vc_sel_T_104, _vc_sel_T_105)
node _vc_sel_T_110 = or(_vc_sel_T_109, _vc_sel_T_106)
node _vc_sel_T_111 = or(_vc_sel_T_110, _vc_sel_T_107)
node _vc_sel_T_112 = or(_vc_sel_T_111, _vc_sel_T_108)
wire _vc_sel_WIRE_14 : UInt<1>
connect _vc_sel_WIRE_14, _vc_sel_T_112
connect _vc_sel_WIRE_12[1], _vc_sel_WIRE_14
node _vc_sel_T_113 = mux(_vc_sel_T, states[0].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_114 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_115 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_116 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_117 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_118 = or(_vc_sel_T_113, _vc_sel_T_114)
node _vc_sel_T_119 = or(_vc_sel_T_118, _vc_sel_T_115)
node _vc_sel_T_120 = or(_vc_sel_T_119, _vc_sel_T_116)
node _vc_sel_T_121 = or(_vc_sel_T_120, _vc_sel_T_117)
wire _vc_sel_WIRE_15 : UInt<1>
connect _vc_sel_WIRE_15, _vc_sel_T_121
connect _vc_sel_WIRE_12[2], _vc_sel_WIRE_15
node _vc_sel_T_122 = mux(_vc_sel_T, states[0].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_123 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_124 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_125 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_126 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_127 = or(_vc_sel_T_122, _vc_sel_T_123)
node _vc_sel_T_128 = or(_vc_sel_T_127, _vc_sel_T_124)
node _vc_sel_T_129 = or(_vc_sel_T_128, _vc_sel_T_125)
node _vc_sel_T_130 = or(_vc_sel_T_129, _vc_sel_T_126)
wire _vc_sel_WIRE_16 : UInt<1>
connect _vc_sel_WIRE_16, _vc_sel_T_130
connect _vc_sel_WIRE_12[3], _vc_sel_WIRE_16
node _vc_sel_T_131 = mux(_vc_sel_T, states[0].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_132 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_133 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_134 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_135 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_136 = or(_vc_sel_T_131, _vc_sel_T_132)
node _vc_sel_T_137 = or(_vc_sel_T_136, _vc_sel_T_133)
node _vc_sel_T_138 = or(_vc_sel_T_137, _vc_sel_T_134)
node _vc_sel_T_139 = or(_vc_sel_T_138, _vc_sel_T_135)
wire _vc_sel_WIRE_17 : UInt<1>
connect _vc_sel_WIRE_17, _vc_sel_T_139
connect _vc_sel_WIRE_12[4], _vc_sel_WIRE_17
connect vc_sel.`2`, _vc_sel_WIRE_12
node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1])
node _channel_oh_T_1 = or(_channel_oh_T, vc_sel.`0`[2])
node _channel_oh_T_2 = or(_channel_oh_T_1, vc_sel.`0`[3])
node channel_oh_0 = or(_channel_oh_T_2, vc_sel.`0`[4])
node _channel_oh_T_3 = or(vc_sel.`1`[0], vc_sel.`1`[1])
node _channel_oh_T_4 = or(_channel_oh_T_3, vc_sel.`1`[2])
node _channel_oh_T_5 = or(_channel_oh_T_4, vc_sel.`1`[3])
node channel_oh_1 = or(_channel_oh_T_5, vc_sel.`1`[4])
node _channel_oh_T_6 = or(vc_sel.`2`[0], vc_sel.`2`[1])
node _channel_oh_T_7 = or(_channel_oh_T_6, vc_sel.`2`[2])
node _channel_oh_T_8 = or(_channel_oh_T_7, vc_sel.`2`[3])
node channel_oh_2 = or(_channel_oh_T_8, vc_sel.`2`[4])
node virt_channel_lo = cat(vc_sel.`0`[1], vc_sel.`0`[0])
node virt_channel_hi_hi = cat(vc_sel.`0`[4], vc_sel.`0`[3])
node virt_channel_hi = cat(virt_channel_hi_hi, vc_sel.`0`[2])
node _virt_channel_T = cat(virt_channel_hi, virt_channel_lo)
node virt_channel_hi_1 = bits(_virt_channel_T, 4, 4)
node virt_channel_lo_1 = bits(_virt_channel_T, 3, 0)
node _virt_channel_T_1 = orr(virt_channel_hi_1)
node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo_1)
node virt_channel_hi_2 = bits(_virt_channel_T_2, 3, 2)
node virt_channel_lo_2 = bits(_virt_channel_T_2, 1, 0)
node _virt_channel_T_3 = orr(virt_channel_hi_2)
node _virt_channel_T_4 = or(virt_channel_hi_2, virt_channel_lo_2)
node _virt_channel_T_5 = bits(_virt_channel_T_4, 1, 1)
node _virt_channel_T_6 = cat(_virt_channel_T_3, _virt_channel_T_5)
node _virt_channel_T_7 = cat(_virt_channel_T_1, _virt_channel_T_6)
node virt_channel_lo_3 = cat(vc_sel.`1`[1], vc_sel.`1`[0])
node virt_channel_hi_hi_1 = cat(vc_sel.`1`[4], vc_sel.`1`[3])
node virt_channel_hi_3 = cat(virt_channel_hi_hi_1, vc_sel.`1`[2])
node _virt_channel_T_8 = cat(virt_channel_hi_3, virt_channel_lo_3)
node virt_channel_hi_4 = bits(_virt_channel_T_8, 4, 4)
node virt_channel_lo_4 = bits(_virt_channel_T_8, 3, 0)
node _virt_channel_T_9 = orr(virt_channel_hi_4)
node _virt_channel_T_10 = or(virt_channel_hi_4, virt_channel_lo_4)
node virt_channel_hi_5 = bits(_virt_channel_T_10, 3, 2)
node virt_channel_lo_5 = bits(_virt_channel_T_10, 1, 0)
node _virt_channel_T_11 = orr(virt_channel_hi_5)
node _virt_channel_T_12 = or(virt_channel_hi_5, virt_channel_lo_5)
node _virt_channel_T_13 = bits(_virt_channel_T_12, 1, 1)
node _virt_channel_T_14 = cat(_virt_channel_T_11, _virt_channel_T_13)
node _virt_channel_T_15 = cat(_virt_channel_T_9, _virt_channel_T_14)
node virt_channel_lo_6 = cat(vc_sel.`2`[1], vc_sel.`2`[0])
node virt_channel_hi_hi_2 = cat(vc_sel.`2`[4], vc_sel.`2`[3])
node virt_channel_hi_6 = cat(virt_channel_hi_hi_2, vc_sel.`2`[2])
node _virt_channel_T_16 = cat(virt_channel_hi_6, virt_channel_lo_6)
node virt_channel_hi_7 = bits(_virt_channel_T_16, 4, 4)
node virt_channel_lo_7 = bits(_virt_channel_T_16, 3, 0)
node _virt_channel_T_17 = orr(virt_channel_hi_7)
node _virt_channel_T_18 = or(virt_channel_hi_7, virt_channel_lo_7)
node virt_channel_hi_8 = bits(_virt_channel_T_18, 3, 2)
node virt_channel_lo_8 = bits(_virt_channel_T_18, 1, 0)
node _virt_channel_T_19 = orr(virt_channel_hi_8)
node _virt_channel_T_20 = or(virt_channel_hi_8, virt_channel_lo_8)
node _virt_channel_T_21 = bits(_virt_channel_T_20, 1, 1)
node _virt_channel_T_22 = cat(_virt_channel_T_19, _virt_channel_T_21)
node _virt_channel_T_23 = cat(_virt_channel_T_17, _virt_channel_T_22)
node _virt_channel_T_24 = mux(channel_oh_0, _virt_channel_T_7, UInt<1>(0h0))
node _virt_channel_T_25 = mux(channel_oh_1, _virt_channel_T_15, UInt<1>(0h0))
node _virt_channel_T_26 = mux(channel_oh_2, _virt_channel_T_23, UInt<1>(0h0))
node _virt_channel_T_27 = or(_virt_channel_T_24, _virt_channel_T_25)
node _virt_channel_T_28 = or(_virt_channel_T_27, _virt_channel_T_26)
wire virt_channel : UInt<3>
connect virt_channel, _virt_channel_T_28
node _T_56 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
when _T_56 :
connect salloc_outs[0].out_vid, virt_channel
node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_payload_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_payload_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_payload_T_5 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_6 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_7 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_8 = mux(_salloc_outs_0_flit_payload_T_3, input_buffer.io.deq[3].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_9 = mux(_salloc_outs_0_flit_payload_T_4, input_buffer.io.deq[4].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_10 = or(_salloc_outs_0_flit_payload_T_5, _salloc_outs_0_flit_payload_T_6)
node _salloc_outs_0_flit_payload_T_11 = or(_salloc_outs_0_flit_payload_T_10, _salloc_outs_0_flit_payload_T_7)
node _salloc_outs_0_flit_payload_T_12 = or(_salloc_outs_0_flit_payload_T_11, _salloc_outs_0_flit_payload_T_8)
node _salloc_outs_0_flit_payload_T_13 = or(_salloc_outs_0_flit_payload_T_12, _salloc_outs_0_flit_payload_T_9)
wire _salloc_outs_0_flit_payload_WIRE : UInt<73>
connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_13
connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE
node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_head_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_head_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_head_T_5 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_6 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_7 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_8 = mux(_salloc_outs_0_flit_head_T_3, input_buffer.io.deq[3].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_9 = mux(_salloc_outs_0_flit_head_T_4, input_buffer.io.deq[4].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_10 = or(_salloc_outs_0_flit_head_T_5, _salloc_outs_0_flit_head_T_6)
node _salloc_outs_0_flit_head_T_11 = or(_salloc_outs_0_flit_head_T_10, _salloc_outs_0_flit_head_T_7)
node _salloc_outs_0_flit_head_T_12 = or(_salloc_outs_0_flit_head_T_11, _salloc_outs_0_flit_head_T_8)
node _salloc_outs_0_flit_head_T_13 = or(_salloc_outs_0_flit_head_T_12, _salloc_outs_0_flit_head_T_9)
wire _salloc_outs_0_flit_head_WIRE : UInt<1>
connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_13
connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE
node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_tail_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_tail_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_tail_T_5 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_6 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_7 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_8 = mux(_salloc_outs_0_flit_tail_T_3, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_9 = mux(_salloc_outs_0_flit_tail_T_4, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_10 = or(_salloc_outs_0_flit_tail_T_5, _salloc_outs_0_flit_tail_T_6)
node _salloc_outs_0_flit_tail_T_11 = or(_salloc_outs_0_flit_tail_T_10, _salloc_outs_0_flit_tail_T_7)
node _salloc_outs_0_flit_tail_T_12 = or(_salloc_outs_0_flit_tail_T_11, _salloc_outs_0_flit_tail_T_8)
node _salloc_outs_0_flit_tail_T_13 = or(_salloc_outs_0_flit_tail_T_12, _salloc_outs_0_flit_tail_T_9)
wire _salloc_outs_0_flit_tail_WIRE : UInt<1>
connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_13
connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE
node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_flow_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_flow_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}
node _salloc_outs_0_flit_flow_T_5 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_6 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_7 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_10 = or(_salloc_outs_0_flit_flow_T_5, _salloc_outs_0_flit_flow_T_6)
node _salloc_outs_0_flit_flow_T_11 = or(_salloc_outs_0_flit_flow_T_10, _salloc_outs_0_flit_flow_T_7)
node _salloc_outs_0_flit_flow_T_12 = or(_salloc_outs_0_flit_flow_T_11, _salloc_outs_0_flit_flow_T_8)
node _salloc_outs_0_flit_flow_T_13 = or(_salloc_outs_0_flit_flow_T_12, _salloc_outs_0_flit_flow_T_9)
wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2>
connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_13
connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1
node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_16 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_17 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_18 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_19 = or(_salloc_outs_0_flit_flow_T_14, _salloc_outs_0_flit_flow_T_15)
node _salloc_outs_0_flit_flow_T_20 = or(_salloc_outs_0_flit_flow_T_19, _salloc_outs_0_flit_flow_T_16)
node _salloc_outs_0_flit_flow_T_21 = or(_salloc_outs_0_flit_flow_T_20, _salloc_outs_0_flit_flow_T_17)
node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_21, _salloc_outs_0_flit_flow_T_18)
wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<5>
connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_22
connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2
node _salloc_outs_0_flit_flow_T_23 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_24 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_25 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_26 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_27 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_28 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_24)
node _salloc_outs_0_flit_flow_T_29 = or(_salloc_outs_0_flit_flow_T_28, _salloc_outs_0_flit_flow_T_25)
node _salloc_outs_0_flit_flow_T_30 = or(_salloc_outs_0_flit_flow_T_29, _salloc_outs_0_flit_flow_T_26)
node _salloc_outs_0_flit_flow_T_31 = or(_salloc_outs_0_flit_flow_T_30, _salloc_outs_0_flit_flow_T_27)
wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<2>
connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_31
connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3
node _salloc_outs_0_flit_flow_T_32 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_33 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_34 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_35 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_36 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_37 = or(_salloc_outs_0_flit_flow_T_32, _salloc_outs_0_flit_flow_T_33)
node _salloc_outs_0_flit_flow_T_38 = or(_salloc_outs_0_flit_flow_T_37, _salloc_outs_0_flit_flow_T_34)
node _salloc_outs_0_flit_flow_T_39 = or(_salloc_outs_0_flit_flow_T_38, _salloc_outs_0_flit_flow_T_35)
node _salloc_outs_0_flit_flow_T_40 = or(_salloc_outs_0_flit_flow_T_39, _salloc_outs_0_flit_flow_T_36)
wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<5>
connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_40
connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4
node _salloc_outs_0_flit_flow_T_41 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_42 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_43 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_44 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_45 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_46 = or(_salloc_outs_0_flit_flow_T_41, _salloc_outs_0_flit_flow_T_42)
node _salloc_outs_0_flit_flow_T_47 = or(_salloc_outs_0_flit_flow_T_46, _salloc_outs_0_flit_flow_T_43)
node _salloc_outs_0_flit_flow_T_48 = or(_salloc_outs_0_flit_flow_T_47, _salloc_outs_0_flit_flow_T_44)
node _salloc_outs_0_flit_flow_T_49 = or(_salloc_outs_0_flit_flow_T_48, _salloc_outs_0_flit_flow_T_45)
wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<3>
connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_49
connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5
connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE
else :
invalidate salloc_outs[0].out_vid
invalidate salloc_outs[0].flit.virt_channel_id
invalidate salloc_outs[0].flit.flow.egress_node_id
invalidate salloc_outs[0].flit.flow.egress_node
invalidate salloc_outs[0].flit.flow.ingress_node_id
invalidate salloc_outs[0].flit.flow.ingress_node
invalidate salloc_outs[0].flit.flow.vnet_id
invalidate salloc_outs[0].flit.payload
invalidate salloc_outs[0].flit.tail
invalidate salloc_outs[0].flit.head
invalidate salloc_outs[0].flit.virt_channel_id
connect io.out[0].valid, salloc_outs[0].valid
connect io.out[0].bits.flit, salloc_outs[0].flit
connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid
invalidate states[0].fifo_deps
invalidate states[0].flow.egress_node_id
invalidate states[0].flow.egress_node
invalidate states[0].flow.ingress_node_id
invalidate states[0].flow.ingress_node
invalidate states[0].flow.vnet_id
invalidate states[0].vc_sel.`0`[0]
invalidate states[0].vc_sel.`0`[1]
invalidate states[0].vc_sel.`0`[2]
invalidate states[0].vc_sel.`0`[3]
invalidate states[0].vc_sel.`0`[4]
invalidate states[0].vc_sel.`1`[0]
invalidate states[0].vc_sel.`1`[1]
invalidate states[0].vc_sel.`1`[2]
invalidate states[0].vc_sel.`1`[3]
invalidate states[0].vc_sel.`1`[4]
invalidate states[0].vc_sel.`2`[0]
invalidate states[0].vc_sel.`2`[1]
invalidate states[0].vc_sel.`2`[2]
invalidate states[0].vc_sel.`2`[3]
invalidate states[0].vc_sel.`2`[4]
invalidate states[0].g
invalidate states[1].fifo_deps
invalidate states[1].flow.egress_node_id
invalidate states[1].flow.egress_node
invalidate states[1].flow.ingress_node_id
invalidate states[1].flow.ingress_node
invalidate states[1].flow.vnet_id
invalidate states[1].vc_sel.`0`[0]
invalidate states[1].vc_sel.`0`[1]
invalidate states[1].vc_sel.`0`[2]
invalidate states[1].vc_sel.`0`[3]
invalidate states[1].vc_sel.`0`[4]
invalidate states[1].vc_sel.`1`[0]
invalidate states[1].vc_sel.`1`[1]
invalidate states[1].vc_sel.`1`[2]
invalidate states[1].vc_sel.`1`[3]
invalidate states[1].vc_sel.`1`[4]
invalidate states[1].vc_sel.`2`[0]
invalidate states[1].vc_sel.`2`[1]
invalidate states[1].vc_sel.`2`[2]
invalidate states[1].vc_sel.`2`[3]
invalidate states[1].vc_sel.`2`[4]
invalidate states[1].g
invalidate states[2].fifo_deps
invalidate states[2].flow.egress_node_id
invalidate states[2].flow.egress_node
invalidate states[2].flow.ingress_node_id
invalidate states[2].flow.ingress_node
invalidate states[2].flow.vnet_id
invalidate states[2].vc_sel.`0`[0]
invalidate states[2].vc_sel.`0`[1]
invalidate states[2].vc_sel.`0`[2]
invalidate states[2].vc_sel.`0`[3]
invalidate states[2].vc_sel.`0`[4]
invalidate states[2].vc_sel.`1`[0]
invalidate states[2].vc_sel.`1`[1]
invalidate states[2].vc_sel.`1`[2]
invalidate states[2].vc_sel.`1`[3]
invalidate states[2].vc_sel.`1`[4]
invalidate states[2].vc_sel.`2`[0]
invalidate states[2].vc_sel.`2`[1]
invalidate states[2].vc_sel.`2`[2]
invalidate states[2].vc_sel.`2`[3]
invalidate states[2].vc_sel.`2`[4]
invalidate states[2].g
invalidate states[3].fifo_deps
invalidate states[3].flow.egress_node_id
invalidate states[3].flow.egress_node
invalidate states[3].flow.ingress_node_id
invalidate states[3].flow.ingress_node
invalidate states[3].flow.vnet_id
invalidate states[3].vc_sel.`0`[0]
invalidate states[3].vc_sel.`0`[1]
invalidate states[3].vc_sel.`0`[2]
invalidate states[3].vc_sel.`0`[3]
invalidate states[3].vc_sel.`0`[4]
invalidate states[3].vc_sel.`1`[0]
invalidate states[3].vc_sel.`1`[1]
invalidate states[3].vc_sel.`1`[2]
invalidate states[3].vc_sel.`1`[3]
invalidate states[3].vc_sel.`1`[4]
invalidate states[3].vc_sel.`2`[0]
invalidate states[3].vc_sel.`2`[1]
invalidate states[3].vc_sel.`2`[2]
invalidate states[3].vc_sel.`2`[3]
invalidate states[3].vc_sel.`2`[4]
invalidate states[3].g
connect states[4].vc_sel.`0`[0], UInt<1>(0h0)
connect states[4].vc_sel.`0`[1], UInt<1>(0h0)
connect states[4].vc_sel.`0`[2], UInt<1>(0h0)
connect states[4].vc_sel.`0`[3], UInt<1>(0h0)
connect states[4].vc_sel.`1`[0], UInt<1>(0h0)
connect states[4].vc_sel.`1`[1], UInt<1>(0h0)
connect states[4].vc_sel.`1`[2], UInt<1>(0h0)
connect states[4].vc_sel.`1`[3], UInt<1>(0h0)
connect states[4].vc_sel.`1`[4], UInt<1>(0h0)
connect states[4].vc_sel.`2`[0], UInt<1>(0h0)
connect states[4].vc_sel.`2`[1], UInt<1>(0h0)
connect states[4].vc_sel.`2`[2], UInt<1>(0h0)
connect states[4].vc_sel.`2`[3], UInt<1>(0h0)
node _T_57 = asUInt(reset)
when _T_57 :
connect states[0].g, UInt<3>(0h0)
connect states[1].g, UInt<3>(0h0)
connect states[2].g, UInt<3>(0h0)
connect states[3].g, UInt<3>(0h0)
connect states[4].g, UInt<3>(0h0) | module InputUnit_99( // @[InputUnit.scala:158:7]
input clock, // @[InputUnit.scala:158:7]
input reset, // @[InputUnit.scala:158:7]
output [2:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14]
output [2:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
output [4:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [4:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14]
output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_4, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_4, // @[InputUnit.scala:170:14]
input io_vcalloc_req_ready, // @[InputUnit.scala:170:14]
output io_vcalloc_req_valid, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_4, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_4, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_4, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_4, // @[InputUnit.scala:170:14]
input io_salloc_req_0_ready, // @[InputUnit.scala:170:14]
output io_salloc_req_0_valid, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14]
output io_out_0_valid, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14]
output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14]
output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14]
output [4:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [4:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14]
output [2:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14]
output [2:0] io_debug_va_stall, // @[InputUnit.scala:170:14]
output [2:0] io_debug_sa_stall, // @[InputUnit.scala:170:14]
input io_in_flit_0_valid, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14]
input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14]
input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
input [4:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input [2:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14]
output [4:0] io_in_credit_return, // @[InputUnit.scala:170:14]
output [4:0] io_in_vc_free // @[InputUnit.scala:170:14]
);
wire vcalloc_vals_4; // @[InputUnit.scala:266:32]
wire _salloc_arb_io_in_4_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26]
wire [4:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26]
wire _route_arbiter_io_in_4_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29]
wire [2:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29]
wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28]
reg [2:0] states_4_g; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg [2:0] states_4_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_4_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_4_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_4_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_4_flow_egress_node_id; // @[InputUnit.scala:192:19]
wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30]
wire route_arbiter_io_in_4_valid = states_4_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
reg [4:0] mask; // @[InputUnit.scala:250:21]
wire [4:0] _vcalloc_filter_T_3 = {vcalloc_vals_4, 4'h0} & ~mask; // @[InputUnit.scala:158:7, :250:21, :253:{80,87,89}, :266:32]
wire [9:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 10'h1 : _vcalloc_filter_T_3[1] ? 10'h2 : _vcalloc_filter_T_3[2] ? 10'h4 : _vcalloc_filter_T_3[3] ? 10'h8 : _vcalloc_filter_T_3[4] ? 10'h10 : {vcalloc_vals_4, 9'h0}; // @[OneHot.scala:85:71]
wire [4:0] vcalloc_sel = vcalloc_filter[4:0] | vcalloc_filter[9:5]; // @[Mux.scala:50:70]
assign vcalloc_vals_4 = states_4_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
wire _GEN_0 = io_vcalloc_req_ready & vcalloc_vals_4; // @[Decoupled.scala:51:35]
wire _GEN_1 = _GEN_0 & vcalloc_sel[4]; // @[Mux.scala:32:36] |
Generate the Verilog code corresponding to this FIRRTL code module BoomMSHR_6 :
input clock : Clock
input reset : Reset
output io : { flip id : UInt, flip req_pri_val : UInt<1>, req_pri_rdy : UInt<1>, flip req_sec_val : UInt<1>, req_sec_rdy : UInt<1>, flip clear_prefetch : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<4>, mispredict_mask : UInt<4>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<34>, target_offset : SInt<21>}}, flip exception : UInt<1>, flip rob_pnr_idx : UInt<5>, flip rob_head_idx : UInt<5>, flip req : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}, flip req_is_probe : UInt<1>, idx : { valid : UInt<1>, bits : UInt}, way : { valid : UInt<1>, bits : UInt}, tag : { valid : UInt<1>, bits : UInt}, mem_acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip mem_grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, mem_finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}, flip prober_state : { valid : UInt<1>, bits : UInt<34>}, refill : { flip ready : UInt<1>, valid : UInt<1>, bits : { way_en : UInt<2>, addr : UInt<10>, wmask : UInt<1>, data : UInt<64>}}, meta_write : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<4>, way_en : UInt<2>, tag : UInt<22>, data : { coh : { state : UInt<2>}, tag : UInt<22>}}}, meta_read : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<4>, way_en : UInt<2>, tag : UInt<22>}}, flip meta_resp : { valid : UInt<1>, bits : { coh : { state : UInt<2>}, tag : UInt<22>}}, wb_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { tag : UInt<22>, idx : UInt<4>, source : UInt<4>, param : UInt<3>, way_en : UInt<2>, voluntary : UInt<1>}}, commit_val : UInt<1>, commit_addr : UInt<34>, commit_coh : { state : UInt<2>}, lb_read : { offset : UInt<3>}, flip lb_resp : UInt<64>, lb_write : { valid : UInt<1>, bits : { offset : UInt<3>, data : UInt<64>}}, replay : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<64>, is_hella : UInt<1>}}, flip wb_resp : UInt<1>, probe_rdy : UInt<1>}
regreset state : UInt<5>, clock, reset, UInt<5>(0h0)
reg req : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}, clock
node req_idx = bits(req.addr, 9, 6)
node req_tag = shr(req.addr, 10)
node _req_block_addr_T = shr(req.addr, 6)
node req_block_addr = shl(_req_block_addr_T, 6)
regreset req_needs_wb : UInt<1>, clock, reset, UInt<1>(0h0)
wire new_coh_meta : { state : UInt<2>}
connect new_coh_meta.state, UInt<2>(0h0)
regreset new_coh : { state : UInt<2>}, clock, reset, new_coh_meta
node _r_T = eq(UInt<5>(0h10), UInt<5>(0h10))
node _r_T_1 = mux(_r_T, UInt<2>(0h2), UInt<2>(0h2))
node _r_T_2 = eq(UInt<5>(0h12), UInt<5>(0h10))
node _r_T_3 = mux(_r_T_2, UInt<2>(0h1), _r_T_1)
node _r_T_4 = eq(UInt<5>(0h13), UInt<5>(0h10))
node _r_T_5 = mux(_r_T_4, UInt<2>(0h0), _r_T_3)
node _r_T_6 = cat(_r_T_5, req.old_meta.coh.state)
node _r_T_7 = cat(UInt<2>(0h0), UInt<2>(0h3))
node _r_T_8 = cat(UInt<2>(0h0), UInt<2>(0h2))
node _r_T_9 = cat(UInt<2>(0h0), UInt<2>(0h1))
node _r_T_10 = cat(UInt<2>(0h0), UInt<2>(0h0))
node _r_T_11 = cat(UInt<2>(0h1), UInt<2>(0h3))
node _r_T_12 = cat(UInt<2>(0h1), UInt<2>(0h2))
node _r_T_13 = cat(UInt<2>(0h1), UInt<2>(0h1))
node _r_T_14 = cat(UInt<2>(0h1), UInt<2>(0h0))
node _r_T_15 = cat(UInt<2>(0h2), UInt<2>(0h3))
node _r_T_16 = cat(UInt<2>(0h2), UInt<2>(0h2))
node _r_T_17 = cat(UInt<2>(0h2), UInt<2>(0h1))
node _r_T_18 = cat(UInt<2>(0h2), UInt<2>(0h0))
node _r_T_19 = eq(_r_T_18, _r_T_6)
node _r_T_20 = mux(_r_T_19, UInt<1>(0h0), UInt<1>(0h0))
node _r_T_21 = mux(_r_T_19, UInt<3>(0h5), UInt<1>(0h0))
node _r_T_22 = mux(_r_T_19, UInt<2>(0h0), UInt<1>(0h0))
node _r_T_23 = eq(_r_T_17, _r_T_6)
node _r_T_24 = mux(_r_T_23, UInt<1>(0h0), _r_T_20)
node _r_T_25 = mux(_r_T_23, UInt<3>(0h2), _r_T_21)
node _r_T_26 = mux(_r_T_23, UInt<2>(0h0), _r_T_22)
node _r_T_27 = eq(_r_T_16, _r_T_6)
node _r_T_28 = mux(_r_T_27, UInt<1>(0h0), _r_T_24)
node _r_T_29 = mux(_r_T_27, UInt<3>(0h1), _r_T_25)
node _r_T_30 = mux(_r_T_27, UInt<2>(0h0), _r_T_26)
node _r_T_31 = eq(_r_T_15, _r_T_6)
node _r_T_32 = mux(_r_T_31, UInt<1>(0h1), _r_T_28)
node _r_T_33 = mux(_r_T_31, UInt<3>(0h1), _r_T_29)
node _r_T_34 = mux(_r_T_31, UInt<2>(0h0), _r_T_30)
node _r_T_35 = eq(_r_T_14, _r_T_6)
node _r_T_36 = mux(_r_T_35, UInt<1>(0h0), _r_T_32)
node _r_T_37 = mux(_r_T_35, UInt<3>(0h5), _r_T_33)
node _r_T_38 = mux(_r_T_35, UInt<2>(0h0), _r_T_34)
node _r_T_39 = eq(_r_T_13, _r_T_6)
node _r_T_40 = mux(_r_T_39, UInt<1>(0h0), _r_T_36)
node _r_T_41 = mux(_r_T_39, UInt<3>(0h4), _r_T_37)
node _r_T_42 = mux(_r_T_39, UInt<2>(0h1), _r_T_38)
node _r_T_43 = eq(_r_T_12, _r_T_6)
node _r_T_44 = mux(_r_T_43, UInt<1>(0h0), _r_T_40)
node _r_T_45 = mux(_r_T_43, UInt<3>(0h0), _r_T_41)
node _r_T_46 = mux(_r_T_43, UInt<2>(0h1), _r_T_42)
node _r_T_47 = eq(_r_T_11, _r_T_6)
node _r_T_48 = mux(_r_T_47, UInt<1>(0h1), _r_T_44)
node _r_T_49 = mux(_r_T_47, UInt<3>(0h0), _r_T_45)
node _r_T_50 = mux(_r_T_47, UInt<2>(0h1), _r_T_46)
node _r_T_51 = eq(_r_T_10, _r_T_6)
node _r_T_52 = mux(_r_T_51, UInt<1>(0h0), _r_T_48)
node _r_T_53 = mux(_r_T_51, UInt<3>(0h5), _r_T_49)
node _r_T_54 = mux(_r_T_51, UInt<2>(0h0), _r_T_50)
node _r_T_55 = eq(_r_T_9, _r_T_6)
node _r_T_56 = mux(_r_T_55, UInt<1>(0h0), _r_T_52)
node _r_T_57 = mux(_r_T_55, UInt<3>(0h4), _r_T_53)
node _r_T_58 = mux(_r_T_55, UInt<2>(0h1), _r_T_54)
node _r_T_59 = eq(_r_T_8, _r_T_6)
node _r_T_60 = mux(_r_T_59, UInt<1>(0h0), _r_T_56)
node _r_T_61 = mux(_r_T_59, UInt<3>(0h3), _r_T_57)
node _r_T_62 = mux(_r_T_59, UInt<2>(0h2), _r_T_58)
node _r_T_63 = eq(_r_T_7, _r_T_6)
node r_1 = mux(_r_T_63, UInt<1>(0h1), _r_T_60)
node shrink_param = mux(_r_T_63, UInt<3>(0h3), _r_T_61)
node r_3 = mux(_r_T_63, UInt<2>(0h2), _r_T_62)
wire coh_on_clear : { state : UInt<2>}
connect coh_on_clear.state, r_3
node _grow_param_r_c_cat_T = eq(req.uop.mem_cmd, UInt<1>(0h1))
node _grow_param_r_c_cat_T_1 = eq(req.uop.mem_cmd, UInt<5>(0h11))
node _grow_param_r_c_cat_T_2 = or(_grow_param_r_c_cat_T, _grow_param_r_c_cat_T_1)
node _grow_param_r_c_cat_T_3 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _grow_param_r_c_cat_T_4 = or(_grow_param_r_c_cat_T_2, _grow_param_r_c_cat_T_3)
node _grow_param_r_c_cat_T_5 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _grow_param_r_c_cat_T_6 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _grow_param_r_c_cat_T_7 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _grow_param_r_c_cat_T_8 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _grow_param_r_c_cat_T_9 = or(_grow_param_r_c_cat_T_5, _grow_param_r_c_cat_T_6)
node _grow_param_r_c_cat_T_10 = or(_grow_param_r_c_cat_T_9, _grow_param_r_c_cat_T_7)
node _grow_param_r_c_cat_T_11 = or(_grow_param_r_c_cat_T_10, _grow_param_r_c_cat_T_8)
node _grow_param_r_c_cat_T_12 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _grow_param_r_c_cat_T_13 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _grow_param_r_c_cat_T_14 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _grow_param_r_c_cat_T_15 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _grow_param_r_c_cat_T_16 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _grow_param_r_c_cat_T_17 = or(_grow_param_r_c_cat_T_12, _grow_param_r_c_cat_T_13)
node _grow_param_r_c_cat_T_18 = or(_grow_param_r_c_cat_T_17, _grow_param_r_c_cat_T_14)
node _grow_param_r_c_cat_T_19 = or(_grow_param_r_c_cat_T_18, _grow_param_r_c_cat_T_15)
node _grow_param_r_c_cat_T_20 = or(_grow_param_r_c_cat_T_19, _grow_param_r_c_cat_T_16)
node _grow_param_r_c_cat_T_21 = or(_grow_param_r_c_cat_T_11, _grow_param_r_c_cat_T_20)
node _grow_param_r_c_cat_T_22 = or(_grow_param_r_c_cat_T_4, _grow_param_r_c_cat_T_21)
node _grow_param_r_c_cat_T_23 = eq(req.uop.mem_cmd, UInt<1>(0h1))
node _grow_param_r_c_cat_T_24 = eq(req.uop.mem_cmd, UInt<5>(0h11))
node _grow_param_r_c_cat_T_25 = or(_grow_param_r_c_cat_T_23, _grow_param_r_c_cat_T_24)
node _grow_param_r_c_cat_T_26 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _grow_param_r_c_cat_T_27 = or(_grow_param_r_c_cat_T_25, _grow_param_r_c_cat_T_26)
node _grow_param_r_c_cat_T_28 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _grow_param_r_c_cat_T_29 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _grow_param_r_c_cat_T_30 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _grow_param_r_c_cat_T_31 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _grow_param_r_c_cat_T_32 = or(_grow_param_r_c_cat_T_28, _grow_param_r_c_cat_T_29)
node _grow_param_r_c_cat_T_33 = or(_grow_param_r_c_cat_T_32, _grow_param_r_c_cat_T_30)
node _grow_param_r_c_cat_T_34 = or(_grow_param_r_c_cat_T_33, _grow_param_r_c_cat_T_31)
node _grow_param_r_c_cat_T_35 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _grow_param_r_c_cat_T_36 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _grow_param_r_c_cat_T_37 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _grow_param_r_c_cat_T_38 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _grow_param_r_c_cat_T_39 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _grow_param_r_c_cat_T_40 = or(_grow_param_r_c_cat_T_35, _grow_param_r_c_cat_T_36)
node _grow_param_r_c_cat_T_41 = or(_grow_param_r_c_cat_T_40, _grow_param_r_c_cat_T_37)
node _grow_param_r_c_cat_T_42 = or(_grow_param_r_c_cat_T_41, _grow_param_r_c_cat_T_38)
node _grow_param_r_c_cat_T_43 = or(_grow_param_r_c_cat_T_42, _grow_param_r_c_cat_T_39)
node _grow_param_r_c_cat_T_44 = or(_grow_param_r_c_cat_T_34, _grow_param_r_c_cat_T_43)
node _grow_param_r_c_cat_T_45 = or(_grow_param_r_c_cat_T_27, _grow_param_r_c_cat_T_44)
node _grow_param_r_c_cat_T_46 = eq(req.uop.mem_cmd, UInt<2>(0h3))
node _grow_param_r_c_cat_T_47 = or(_grow_param_r_c_cat_T_45, _grow_param_r_c_cat_T_46)
node _grow_param_r_c_cat_T_48 = eq(req.uop.mem_cmd, UInt<3>(0h6))
node _grow_param_r_c_cat_T_49 = or(_grow_param_r_c_cat_T_47, _grow_param_r_c_cat_T_48)
node grow_param_r_c = cat(_grow_param_r_c_cat_T_22, _grow_param_r_c_cat_T_49)
node _grow_param_r_T = cat(grow_param_r_c, new_coh.state)
node _grow_param_r_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _grow_param_r_T_2 = cat(_grow_param_r_T_1, UInt<2>(0h3))
node _grow_param_r_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _grow_param_r_T_4 = cat(_grow_param_r_T_3, UInt<2>(0h2))
node _grow_param_r_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _grow_param_r_T_6 = cat(_grow_param_r_T_5, UInt<2>(0h1))
node _grow_param_r_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _grow_param_r_T_8 = cat(_grow_param_r_T_7, UInt<2>(0h3))
node _grow_param_r_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _grow_param_r_T_10 = cat(_grow_param_r_T_9, UInt<2>(0h2))
node _grow_param_r_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _grow_param_r_T_12 = cat(_grow_param_r_T_11, UInt<2>(0h3))
node _grow_param_r_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _grow_param_r_T_14 = cat(_grow_param_r_T_13, UInt<2>(0h2))
node _grow_param_r_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _grow_param_r_T_16 = cat(_grow_param_r_T_15, UInt<2>(0h0))
node _grow_param_r_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _grow_param_r_T_18 = cat(_grow_param_r_T_17, UInt<2>(0h1))
node _grow_param_r_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _grow_param_r_T_20 = cat(_grow_param_r_T_19, UInt<2>(0h0))
node _grow_param_r_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _grow_param_r_T_22 = cat(_grow_param_r_T_21, UInt<2>(0h1))
node _grow_param_r_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _grow_param_r_T_24 = cat(_grow_param_r_T_23, UInt<2>(0h0))
node _grow_param_r_T_25 = eq(_grow_param_r_T_24, _grow_param_r_T)
node _grow_param_r_T_26 = mux(_grow_param_r_T_25, UInt<1>(0h0), UInt<1>(0h0))
node _grow_param_r_T_27 = mux(_grow_param_r_T_25, UInt<2>(0h1), UInt<1>(0h0))
node _grow_param_r_T_28 = eq(_grow_param_r_T_22, _grow_param_r_T)
node _grow_param_r_T_29 = mux(_grow_param_r_T_28, UInt<1>(0h0), _grow_param_r_T_26)
node _grow_param_r_T_30 = mux(_grow_param_r_T_28, UInt<2>(0h2), _grow_param_r_T_27)
node _grow_param_r_T_31 = eq(_grow_param_r_T_20, _grow_param_r_T)
node _grow_param_r_T_32 = mux(_grow_param_r_T_31, UInt<1>(0h0), _grow_param_r_T_29)
node _grow_param_r_T_33 = mux(_grow_param_r_T_31, UInt<2>(0h1), _grow_param_r_T_30)
node _grow_param_r_T_34 = eq(_grow_param_r_T_18, _grow_param_r_T)
node _grow_param_r_T_35 = mux(_grow_param_r_T_34, UInt<1>(0h0), _grow_param_r_T_32)
node _grow_param_r_T_36 = mux(_grow_param_r_T_34, UInt<2>(0h2), _grow_param_r_T_33)
node _grow_param_r_T_37 = eq(_grow_param_r_T_16, _grow_param_r_T)
node _grow_param_r_T_38 = mux(_grow_param_r_T_37, UInt<1>(0h0), _grow_param_r_T_35)
node _grow_param_r_T_39 = mux(_grow_param_r_T_37, UInt<2>(0h0), _grow_param_r_T_36)
node _grow_param_r_T_40 = eq(_grow_param_r_T_14, _grow_param_r_T)
node _grow_param_r_T_41 = mux(_grow_param_r_T_40, UInt<1>(0h1), _grow_param_r_T_38)
node _grow_param_r_T_42 = mux(_grow_param_r_T_40, UInt<2>(0h3), _grow_param_r_T_39)
node _grow_param_r_T_43 = eq(_grow_param_r_T_12, _grow_param_r_T)
node _grow_param_r_T_44 = mux(_grow_param_r_T_43, UInt<1>(0h1), _grow_param_r_T_41)
node _grow_param_r_T_45 = mux(_grow_param_r_T_43, UInt<2>(0h3), _grow_param_r_T_42)
node _grow_param_r_T_46 = eq(_grow_param_r_T_10, _grow_param_r_T)
node _grow_param_r_T_47 = mux(_grow_param_r_T_46, UInt<1>(0h1), _grow_param_r_T_44)
node _grow_param_r_T_48 = mux(_grow_param_r_T_46, UInt<2>(0h2), _grow_param_r_T_45)
node _grow_param_r_T_49 = eq(_grow_param_r_T_8, _grow_param_r_T)
node _grow_param_r_T_50 = mux(_grow_param_r_T_49, UInt<1>(0h1), _grow_param_r_T_47)
node _grow_param_r_T_51 = mux(_grow_param_r_T_49, UInt<2>(0h3), _grow_param_r_T_48)
node _grow_param_r_T_52 = eq(_grow_param_r_T_6, _grow_param_r_T)
node _grow_param_r_T_53 = mux(_grow_param_r_T_52, UInt<1>(0h1), _grow_param_r_T_50)
node _grow_param_r_T_54 = mux(_grow_param_r_T_52, UInt<2>(0h1), _grow_param_r_T_51)
node _grow_param_r_T_55 = eq(_grow_param_r_T_4, _grow_param_r_T)
node _grow_param_r_T_56 = mux(_grow_param_r_T_55, UInt<1>(0h1), _grow_param_r_T_53)
node _grow_param_r_T_57 = mux(_grow_param_r_T_55, UInt<2>(0h2), _grow_param_r_T_54)
node _grow_param_r_T_58 = eq(_grow_param_r_T_2, _grow_param_r_T)
node grow_param_r_1 = mux(_grow_param_r_T_58, UInt<1>(0h1), _grow_param_r_T_56)
node grow_param = mux(_grow_param_r_T_58, UInt<2>(0h3), _grow_param_r_T_57)
wire grow_param_meta : { state : UInt<2>}
connect grow_param_meta.state, grow_param
node _coh_on_grant_c_cat_T = eq(req.uop.mem_cmd, UInt<1>(0h1))
node _coh_on_grant_c_cat_T_1 = eq(req.uop.mem_cmd, UInt<5>(0h11))
node _coh_on_grant_c_cat_T_2 = or(_coh_on_grant_c_cat_T, _coh_on_grant_c_cat_T_1)
node _coh_on_grant_c_cat_T_3 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _coh_on_grant_c_cat_T_4 = or(_coh_on_grant_c_cat_T_2, _coh_on_grant_c_cat_T_3)
node _coh_on_grant_c_cat_T_5 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _coh_on_grant_c_cat_T_6 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _coh_on_grant_c_cat_T_7 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _coh_on_grant_c_cat_T_8 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _coh_on_grant_c_cat_T_9 = or(_coh_on_grant_c_cat_T_5, _coh_on_grant_c_cat_T_6)
node _coh_on_grant_c_cat_T_10 = or(_coh_on_grant_c_cat_T_9, _coh_on_grant_c_cat_T_7)
node _coh_on_grant_c_cat_T_11 = or(_coh_on_grant_c_cat_T_10, _coh_on_grant_c_cat_T_8)
node _coh_on_grant_c_cat_T_12 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _coh_on_grant_c_cat_T_13 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _coh_on_grant_c_cat_T_14 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _coh_on_grant_c_cat_T_15 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _coh_on_grant_c_cat_T_16 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _coh_on_grant_c_cat_T_17 = or(_coh_on_grant_c_cat_T_12, _coh_on_grant_c_cat_T_13)
node _coh_on_grant_c_cat_T_18 = or(_coh_on_grant_c_cat_T_17, _coh_on_grant_c_cat_T_14)
node _coh_on_grant_c_cat_T_19 = or(_coh_on_grant_c_cat_T_18, _coh_on_grant_c_cat_T_15)
node _coh_on_grant_c_cat_T_20 = or(_coh_on_grant_c_cat_T_19, _coh_on_grant_c_cat_T_16)
node _coh_on_grant_c_cat_T_21 = or(_coh_on_grant_c_cat_T_11, _coh_on_grant_c_cat_T_20)
node _coh_on_grant_c_cat_T_22 = or(_coh_on_grant_c_cat_T_4, _coh_on_grant_c_cat_T_21)
node _coh_on_grant_c_cat_T_23 = eq(req.uop.mem_cmd, UInt<1>(0h1))
node _coh_on_grant_c_cat_T_24 = eq(req.uop.mem_cmd, UInt<5>(0h11))
node _coh_on_grant_c_cat_T_25 = or(_coh_on_grant_c_cat_T_23, _coh_on_grant_c_cat_T_24)
node _coh_on_grant_c_cat_T_26 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _coh_on_grant_c_cat_T_27 = or(_coh_on_grant_c_cat_T_25, _coh_on_grant_c_cat_T_26)
node _coh_on_grant_c_cat_T_28 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _coh_on_grant_c_cat_T_29 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _coh_on_grant_c_cat_T_30 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _coh_on_grant_c_cat_T_31 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _coh_on_grant_c_cat_T_32 = or(_coh_on_grant_c_cat_T_28, _coh_on_grant_c_cat_T_29)
node _coh_on_grant_c_cat_T_33 = or(_coh_on_grant_c_cat_T_32, _coh_on_grant_c_cat_T_30)
node _coh_on_grant_c_cat_T_34 = or(_coh_on_grant_c_cat_T_33, _coh_on_grant_c_cat_T_31)
node _coh_on_grant_c_cat_T_35 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _coh_on_grant_c_cat_T_36 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _coh_on_grant_c_cat_T_37 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _coh_on_grant_c_cat_T_38 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _coh_on_grant_c_cat_T_39 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _coh_on_grant_c_cat_T_40 = or(_coh_on_grant_c_cat_T_35, _coh_on_grant_c_cat_T_36)
node _coh_on_grant_c_cat_T_41 = or(_coh_on_grant_c_cat_T_40, _coh_on_grant_c_cat_T_37)
node _coh_on_grant_c_cat_T_42 = or(_coh_on_grant_c_cat_T_41, _coh_on_grant_c_cat_T_38)
node _coh_on_grant_c_cat_T_43 = or(_coh_on_grant_c_cat_T_42, _coh_on_grant_c_cat_T_39)
node _coh_on_grant_c_cat_T_44 = or(_coh_on_grant_c_cat_T_34, _coh_on_grant_c_cat_T_43)
node _coh_on_grant_c_cat_T_45 = or(_coh_on_grant_c_cat_T_27, _coh_on_grant_c_cat_T_44)
node _coh_on_grant_c_cat_T_46 = eq(req.uop.mem_cmd, UInt<2>(0h3))
node _coh_on_grant_c_cat_T_47 = or(_coh_on_grant_c_cat_T_45, _coh_on_grant_c_cat_T_46)
node _coh_on_grant_c_cat_T_48 = eq(req.uop.mem_cmd, UInt<3>(0h6))
node _coh_on_grant_c_cat_T_49 = or(_coh_on_grant_c_cat_T_47, _coh_on_grant_c_cat_T_48)
node coh_on_grant_c = cat(_coh_on_grant_c_cat_T_22, _coh_on_grant_c_cat_T_49)
node _coh_on_grant_T = cat(coh_on_grant_c, io.mem_grant.bits.param)
node _coh_on_grant_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _coh_on_grant_T_2 = cat(_coh_on_grant_T_1, UInt<2>(0h1))
node _coh_on_grant_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _coh_on_grant_T_4 = cat(_coh_on_grant_T_3, UInt<2>(0h0))
node _coh_on_grant_T_5 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _coh_on_grant_T_6 = cat(_coh_on_grant_T_5, UInt<2>(0h0))
node _coh_on_grant_T_7 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _coh_on_grant_T_8 = cat(_coh_on_grant_T_7, UInt<2>(0h0))
node _coh_on_grant_T_9 = eq(_coh_on_grant_T_2, _coh_on_grant_T)
node _coh_on_grant_T_10 = mux(_coh_on_grant_T_9, UInt<2>(0h1), UInt<2>(0h0))
node _coh_on_grant_T_11 = eq(_coh_on_grant_T_4, _coh_on_grant_T)
node _coh_on_grant_T_12 = mux(_coh_on_grant_T_11, UInt<2>(0h2), _coh_on_grant_T_10)
node _coh_on_grant_T_13 = eq(_coh_on_grant_T_6, _coh_on_grant_T)
node _coh_on_grant_T_14 = mux(_coh_on_grant_T_13, UInt<2>(0h2), _coh_on_grant_T_12)
node _coh_on_grant_T_15 = eq(_coh_on_grant_T_8, _coh_on_grant_T)
node _coh_on_grant_T_16 = mux(_coh_on_grant_T_15, UInt<2>(0h3), _coh_on_grant_T_14)
wire coh_on_grant : { state : UInt<2>}
connect coh_on_grant.state, _coh_on_grant_T_16
node _r1_c_cat_T = eq(req.uop.mem_cmd, UInt<1>(0h1))
node _r1_c_cat_T_1 = eq(req.uop.mem_cmd, UInt<5>(0h11))
node _r1_c_cat_T_2 = or(_r1_c_cat_T, _r1_c_cat_T_1)
node _r1_c_cat_T_3 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _r1_c_cat_T_4 = or(_r1_c_cat_T_2, _r1_c_cat_T_3)
node _r1_c_cat_T_5 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _r1_c_cat_T_6 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _r1_c_cat_T_7 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _r1_c_cat_T_8 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _r1_c_cat_T_9 = or(_r1_c_cat_T_5, _r1_c_cat_T_6)
node _r1_c_cat_T_10 = or(_r1_c_cat_T_9, _r1_c_cat_T_7)
node _r1_c_cat_T_11 = or(_r1_c_cat_T_10, _r1_c_cat_T_8)
node _r1_c_cat_T_12 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _r1_c_cat_T_13 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _r1_c_cat_T_14 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _r1_c_cat_T_15 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _r1_c_cat_T_16 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _r1_c_cat_T_17 = or(_r1_c_cat_T_12, _r1_c_cat_T_13)
node _r1_c_cat_T_18 = or(_r1_c_cat_T_17, _r1_c_cat_T_14)
node _r1_c_cat_T_19 = or(_r1_c_cat_T_18, _r1_c_cat_T_15)
node _r1_c_cat_T_20 = or(_r1_c_cat_T_19, _r1_c_cat_T_16)
node _r1_c_cat_T_21 = or(_r1_c_cat_T_11, _r1_c_cat_T_20)
node _r1_c_cat_T_22 = or(_r1_c_cat_T_4, _r1_c_cat_T_21)
node _r1_c_cat_T_23 = eq(req.uop.mem_cmd, UInt<1>(0h1))
node _r1_c_cat_T_24 = eq(req.uop.mem_cmd, UInt<5>(0h11))
node _r1_c_cat_T_25 = or(_r1_c_cat_T_23, _r1_c_cat_T_24)
node _r1_c_cat_T_26 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _r1_c_cat_T_27 = or(_r1_c_cat_T_25, _r1_c_cat_T_26)
node _r1_c_cat_T_28 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _r1_c_cat_T_29 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _r1_c_cat_T_30 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _r1_c_cat_T_31 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _r1_c_cat_T_32 = or(_r1_c_cat_T_28, _r1_c_cat_T_29)
node _r1_c_cat_T_33 = or(_r1_c_cat_T_32, _r1_c_cat_T_30)
node _r1_c_cat_T_34 = or(_r1_c_cat_T_33, _r1_c_cat_T_31)
node _r1_c_cat_T_35 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _r1_c_cat_T_36 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _r1_c_cat_T_37 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _r1_c_cat_T_38 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _r1_c_cat_T_39 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _r1_c_cat_T_40 = or(_r1_c_cat_T_35, _r1_c_cat_T_36)
node _r1_c_cat_T_41 = or(_r1_c_cat_T_40, _r1_c_cat_T_37)
node _r1_c_cat_T_42 = or(_r1_c_cat_T_41, _r1_c_cat_T_38)
node _r1_c_cat_T_43 = or(_r1_c_cat_T_42, _r1_c_cat_T_39)
node _r1_c_cat_T_44 = or(_r1_c_cat_T_34, _r1_c_cat_T_43)
node _r1_c_cat_T_45 = or(_r1_c_cat_T_27, _r1_c_cat_T_44)
node _r1_c_cat_T_46 = eq(req.uop.mem_cmd, UInt<2>(0h3))
node _r1_c_cat_T_47 = or(_r1_c_cat_T_45, _r1_c_cat_T_46)
node _r1_c_cat_T_48 = eq(req.uop.mem_cmd, UInt<3>(0h6))
node _r1_c_cat_T_49 = or(_r1_c_cat_T_47, _r1_c_cat_T_48)
node r1_c = cat(_r1_c_cat_T_22, _r1_c_cat_T_49)
node _r1_T = cat(r1_c, new_coh.state)
node _r1_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r1_T_2 = cat(_r1_T_1, UInt<2>(0h3))
node _r1_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r1_T_4 = cat(_r1_T_3, UInt<2>(0h2))
node _r1_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r1_T_6 = cat(_r1_T_5, UInt<2>(0h1))
node _r1_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r1_T_8 = cat(_r1_T_7, UInt<2>(0h3))
node _r1_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r1_T_10 = cat(_r1_T_9, UInt<2>(0h2))
node _r1_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r1_T_12 = cat(_r1_T_11, UInt<2>(0h3))
node _r1_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r1_T_14 = cat(_r1_T_13, UInt<2>(0h2))
node _r1_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r1_T_16 = cat(_r1_T_15, UInt<2>(0h0))
node _r1_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r1_T_18 = cat(_r1_T_17, UInt<2>(0h1))
node _r1_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r1_T_20 = cat(_r1_T_19, UInt<2>(0h0))
node _r1_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r1_T_22 = cat(_r1_T_21, UInt<2>(0h1))
node _r1_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r1_T_24 = cat(_r1_T_23, UInt<2>(0h0))
node _r1_T_25 = eq(_r1_T_24, _r1_T)
node _r1_T_26 = mux(_r1_T_25, UInt<1>(0h0), UInt<1>(0h0))
node _r1_T_27 = mux(_r1_T_25, UInt<2>(0h1), UInt<1>(0h0))
node _r1_T_28 = eq(_r1_T_22, _r1_T)
node _r1_T_29 = mux(_r1_T_28, UInt<1>(0h0), _r1_T_26)
node _r1_T_30 = mux(_r1_T_28, UInt<2>(0h2), _r1_T_27)
node _r1_T_31 = eq(_r1_T_20, _r1_T)
node _r1_T_32 = mux(_r1_T_31, UInt<1>(0h0), _r1_T_29)
node _r1_T_33 = mux(_r1_T_31, UInt<2>(0h1), _r1_T_30)
node _r1_T_34 = eq(_r1_T_18, _r1_T)
node _r1_T_35 = mux(_r1_T_34, UInt<1>(0h0), _r1_T_32)
node _r1_T_36 = mux(_r1_T_34, UInt<2>(0h2), _r1_T_33)
node _r1_T_37 = eq(_r1_T_16, _r1_T)
node _r1_T_38 = mux(_r1_T_37, UInt<1>(0h0), _r1_T_35)
node _r1_T_39 = mux(_r1_T_37, UInt<2>(0h0), _r1_T_36)
node _r1_T_40 = eq(_r1_T_14, _r1_T)
node _r1_T_41 = mux(_r1_T_40, UInt<1>(0h1), _r1_T_38)
node _r1_T_42 = mux(_r1_T_40, UInt<2>(0h3), _r1_T_39)
node _r1_T_43 = eq(_r1_T_12, _r1_T)
node _r1_T_44 = mux(_r1_T_43, UInt<1>(0h1), _r1_T_41)
node _r1_T_45 = mux(_r1_T_43, UInt<2>(0h3), _r1_T_42)
node _r1_T_46 = eq(_r1_T_10, _r1_T)
node _r1_T_47 = mux(_r1_T_46, UInt<1>(0h1), _r1_T_44)
node _r1_T_48 = mux(_r1_T_46, UInt<2>(0h2), _r1_T_45)
node _r1_T_49 = eq(_r1_T_8, _r1_T)
node _r1_T_50 = mux(_r1_T_49, UInt<1>(0h1), _r1_T_47)
node _r1_T_51 = mux(_r1_T_49, UInt<2>(0h3), _r1_T_48)
node _r1_T_52 = eq(_r1_T_6, _r1_T)
node _r1_T_53 = mux(_r1_T_52, UInt<1>(0h1), _r1_T_50)
node _r1_T_54 = mux(_r1_T_52, UInt<2>(0h1), _r1_T_51)
node _r1_T_55 = eq(_r1_T_4, _r1_T)
node _r1_T_56 = mux(_r1_T_55, UInt<1>(0h1), _r1_T_53)
node _r1_T_57 = mux(_r1_T_55, UInt<2>(0h2), _r1_T_54)
node _r1_T_58 = eq(_r1_T_2, _r1_T)
node r1_1 = mux(_r1_T_58, UInt<1>(0h1), _r1_T_56)
node r1_2 = mux(_r1_T_58, UInt<2>(0h3), _r1_T_57)
node _r2_c_cat_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _r2_c_cat_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _r2_c_cat_T_2 = or(_r2_c_cat_T, _r2_c_cat_T_1)
node _r2_c_cat_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _r2_c_cat_T_4 = or(_r2_c_cat_T_2, _r2_c_cat_T_3)
node _r2_c_cat_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _r2_c_cat_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _r2_c_cat_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _r2_c_cat_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _r2_c_cat_T_9 = or(_r2_c_cat_T_5, _r2_c_cat_T_6)
node _r2_c_cat_T_10 = or(_r2_c_cat_T_9, _r2_c_cat_T_7)
node _r2_c_cat_T_11 = or(_r2_c_cat_T_10, _r2_c_cat_T_8)
node _r2_c_cat_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _r2_c_cat_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _r2_c_cat_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _r2_c_cat_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _r2_c_cat_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _r2_c_cat_T_17 = or(_r2_c_cat_T_12, _r2_c_cat_T_13)
node _r2_c_cat_T_18 = or(_r2_c_cat_T_17, _r2_c_cat_T_14)
node _r2_c_cat_T_19 = or(_r2_c_cat_T_18, _r2_c_cat_T_15)
node _r2_c_cat_T_20 = or(_r2_c_cat_T_19, _r2_c_cat_T_16)
node _r2_c_cat_T_21 = or(_r2_c_cat_T_11, _r2_c_cat_T_20)
node _r2_c_cat_T_22 = or(_r2_c_cat_T_4, _r2_c_cat_T_21)
node _r2_c_cat_T_23 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _r2_c_cat_T_24 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _r2_c_cat_T_25 = or(_r2_c_cat_T_23, _r2_c_cat_T_24)
node _r2_c_cat_T_26 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _r2_c_cat_T_27 = or(_r2_c_cat_T_25, _r2_c_cat_T_26)
node _r2_c_cat_T_28 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _r2_c_cat_T_29 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _r2_c_cat_T_30 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _r2_c_cat_T_31 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _r2_c_cat_T_32 = or(_r2_c_cat_T_28, _r2_c_cat_T_29)
node _r2_c_cat_T_33 = or(_r2_c_cat_T_32, _r2_c_cat_T_30)
node _r2_c_cat_T_34 = or(_r2_c_cat_T_33, _r2_c_cat_T_31)
node _r2_c_cat_T_35 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _r2_c_cat_T_36 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _r2_c_cat_T_37 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _r2_c_cat_T_38 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _r2_c_cat_T_39 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _r2_c_cat_T_40 = or(_r2_c_cat_T_35, _r2_c_cat_T_36)
node _r2_c_cat_T_41 = or(_r2_c_cat_T_40, _r2_c_cat_T_37)
node _r2_c_cat_T_42 = or(_r2_c_cat_T_41, _r2_c_cat_T_38)
node _r2_c_cat_T_43 = or(_r2_c_cat_T_42, _r2_c_cat_T_39)
node _r2_c_cat_T_44 = or(_r2_c_cat_T_34, _r2_c_cat_T_43)
node _r2_c_cat_T_45 = or(_r2_c_cat_T_27, _r2_c_cat_T_44)
node _r2_c_cat_T_46 = eq(io.req.uop.mem_cmd, UInt<2>(0h3))
node _r2_c_cat_T_47 = or(_r2_c_cat_T_45, _r2_c_cat_T_46)
node _r2_c_cat_T_48 = eq(io.req.uop.mem_cmd, UInt<3>(0h6))
node _r2_c_cat_T_49 = or(_r2_c_cat_T_47, _r2_c_cat_T_48)
node r2_c = cat(_r2_c_cat_T_22, _r2_c_cat_T_49)
node _r2_T = cat(r2_c, new_coh.state)
node _r2_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r2_T_2 = cat(_r2_T_1, UInt<2>(0h3))
node _r2_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r2_T_4 = cat(_r2_T_3, UInt<2>(0h2))
node _r2_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r2_T_6 = cat(_r2_T_5, UInt<2>(0h1))
node _r2_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r2_T_8 = cat(_r2_T_7, UInt<2>(0h3))
node _r2_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r2_T_10 = cat(_r2_T_9, UInt<2>(0h2))
node _r2_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r2_T_12 = cat(_r2_T_11, UInt<2>(0h3))
node _r2_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r2_T_14 = cat(_r2_T_13, UInt<2>(0h2))
node _r2_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r2_T_16 = cat(_r2_T_15, UInt<2>(0h0))
node _r2_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r2_T_18 = cat(_r2_T_17, UInt<2>(0h1))
node _r2_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r2_T_20 = cat(_r2_T_19, UInt<2>(0h0))
node _r2_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r2_T_22 = cat(_r2_T_21, UInt<2>(0h1))
node _r2_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r2_T_24 = cat(_r2_T_23, UInt<2>(0h0))
node _r2_T_25 = eq(_r2_T_24, _r2_T)
node _r2_T_26 = mux(_r2_T_25, UInt<1>(0h0), UInt<1>(0h0))
node _r2_T_27 = mux(_r2_T_25, UInt<2>(0h1), UInt<1>(0h0))
node _r2_T_28 = eq(_r2_T_22, _r2_T)
node _r2_T_29 = mux(_r2_T_28, UInt<1>(0h0), _r2_T_26)
node _r2_T_30 = mux(_r2_T_28, UInt<2>(0h2), _r2_T_27)
node _r2_T_31 = eq(_r2_T_20, _r2_T)
node _r2_T_32 = mux(_r2_T_31, UInt<1>(0h0), _r2_T_29)
node _r2_T_33 = mux(_r2_T_31, UInt<2>(0h1), _r2_T_30)
node _r2_T_34 = eq(_r2_T_18, _r2_T)
node _r2_T_35 = mux(_r2_T_34, UInt<1>(0h0), _r2_T_32)
node _r2_T_36 = mux(_r2_T_34, UInt<2>(0h2), _r2_T_33)
node _r2_T_37 = eq(_r2_T_16, _r2_T)
node _r2_T_38 = mux(_r2_T_37, UInt<1>(0h0), _r2_T_35)
node _r2_T_39 = mux(_r2_T_37, UInt<2>(0h0), _r2_T_36)
node _r2_T_40 = eq(_r2_T_14, _r2_T)
node _r2_T_41 = mux(_r2_T_40, UInt<1>(0h1), _r2_T_38)
node _r2_T_42 = mux(_r2_T_40, UInt<2>(0h3), _r2_T_39)
node _r2_T_43 = eq(_r2_T_12, _r2_T)
node _r2_T_44 = mux(_r2_T_43, UInt<1>(0h1), _r2_T_41)
node _r2_T_45 = mux(_r2_T_43, UInt<2>(0h3), _r2_T_42)
node _r2_T_46 = eq(_r2_T_10, _r2_T)
node _r2_T_47 = mux(_r2_T_46, UInt<1>(0h1), _r2_T_44)
node _r2_T_48 = mux(_r2_T_46, UInt<2>(0h2), _r2_T_45)
node _r2_T_49 = eq(_r2_T_8, _r2_T)
node _r2_T_50 = mux(_r2_T_49, UInt<1>(0h1), _r2_T_47)
node _r2_T_51 = mux(_r2_T_49, UInt<2>(0h3), _r2_T_48)
node _r2_T_52 = eq(_r2_T_6, _r2_T)
node _r2_T_53 = mux(_r2_T_52, UInt<1>(0h1), _r2_T_50)
node _r2_T_54 = mux(_r2_T_52, UInt<2>(0h1), _r2_T_51)
node _r2_T_55 = eq(_r2_T_4, _r2_T)
node _r2_T_56 = mux(_r2_T_55, UInt<1>(0h1), _r2_T_53)
node _r2_T_57 = mux(_r2_T_55, UInt<2>(0h2), _r2_T_54)
node _r2_T_58 = eq(_r2_T_2, _r2_T)
node r2_1 = mux(_r2_T_58, UInt<1>(0h1), _r2_T_56)
node r2_2 = mux(_r2_T_58, UInt<2>(0h3), _r2_T_57)
node _needs_second_acq_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _needs_second_acq_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _needs_second_acq_T_2 = or(_needs_second_acq_T, _needs_second_acq_T_1)
node _needs_second_acq_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _needs_second_acq_T_4 = or(_needs_second_acq_T_2, _needs_second_acq_T_3)
node _needs_second_acq_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _needs_second_acq_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _needs_second_acq_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _needs_second_acq_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _needs_second_acq_T_9 = or(_needs_second_acq_T_5, _needs_second_acq_T_6)
node _needs_second_acq_T_10 = or(_needs_second_acq_T_9, _needs_second_acq_T_7)
node _needs_second_acq_T_11 = or(_needs_second_acq_T_10, _needs_second_acq_T_8)
node _needs_second_acq_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _needs_second_acq_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _needs_second_acq_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _needs_second_acq_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _needs_second_acq_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _needs_second_acq_T_17 = or(_needs_second_acq_T_12, _needs_second_acq_T_13)
node _needs_second_acq_T_18 = or(_needs_second_acq_T_17, _needs_second_acq_T_14)
node _needs_second_acq_T_19 = or(_needs_second_acq_T_18, _needs_second_acq_T_15)
node _needs_second_acq_T_20 = or(_needs_second_acq_T_19, _needs_second_acq_T_16)
node _needs_second_acq_T_21 = or(_needs_second_acq_T_11, _needs_second_acq_T_20)
node _needs_second_acq_T_22 = or(_needs_second_acq_T_4, _needs_second_acq_T_21)
node _needs_second_acq_T_23 = eq(io.req.uop.mem_cmd, UInt<2>(0h3))
node _needs_second_acq_T_24 = or(_needs_second_acq_T_22, _needs_second_acq_T_23)
node _needs_second_acq_T_25 = eq(io.req.uop.mem_cmd, UInt<3>(0h6))
node _needs_second_acq_T_26 = or(_needs_second_acq_T_24, _needs_second_acq_T_25)
node _needs_second_acq_T_27 = eq(req.uop.mem_cmd, UInt<1>(0h1))
node _needs_second_acq_T_28 = eq(req.uop.mem_cmd, UInt<5>(0h11))
node _needs_second_acq_T_29 = or(_needs_second_acq_T_27, _needs_second_acq_T_28)
node _needs_second_acq_T_30 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _needs_second_acq_T_31 = or(_needs_second_acq_T_29, _needs_second_acq_T_30)
node _needs_second_acq_T_32 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _needs_second_acq_T_33 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _needs_second_acq_T_34 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _needs_second_acq_T_35 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _needs_second_acq_T_36 = or(_needs_second_acq_T_32, _needs_second_acq_T_33)
node _needs_second_acq_T_37 = or(_needs_second_acq_T_36, _needs_second_acq_T_34)
node _needs_second_acq_T_38 = or(_needs_second_acq_T_37, _needs_second_acq_T_35)
node _needs_second_acq_T_39 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _needs_second_acq_T_40 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _needs_second_acq_T_41 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _needs_second_acq_T_42 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _needs_second_acq_T_43 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _needs_second_acq_T_44 = or(_needs_second_acq_T_39, _needs_second_acq_T_40)
node _needs_second_acq_T_45 = or(_needs_second_acq_T_44, _needs_second_acq_T_41)
node _needs_second_acq_T_46 = or(_needs_second_acq_T_45, _needs_second_acq_T_42)
node _needs_second_acq_T_47 = or(_needs_second_acq_T_46, _needs_second_acq_T_43)
node _needs_second_acq_T_48 = or(_needs_second_acq_T_38, _needs_second_acq_T_47)
node _needs_second_acq_T_49 = or(_needs_second_acq_T_31, _needs_second_acq_T_48)
node _needs_second_acq_T_50 = eq(req.uop.mem_cmd, UInt<2>(0h3))
node _needs_second_acq_T_51 = or(_needs_second_acq_T_49, _needs_second_acq_T_50)
node _needs_second_acq_T_52 = eq(req.uop.mem_cmd, UInt<3>(0h6))
node _needs_second_acq_T_53 = or(_needs_second_acq_T_51, _needs_second_acq_T_52)
node _needs_second_acq_T_54 = eq(_needs_second_acq_T_53, UInt<1>(0h0))
node cmd_requires_second_acquire = and(_needs_second_acq_T_26, _needs_second_acq_T_54)
node is_hit_again = and(r1_1, r2_1)
node _dirties_cat_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _dirties_cat_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _dirties_cat_T_2 = or(_dirties_cat_T, _dirties_cat_T_1)
node _dirties_cat_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _dirties_cat_T_4 = or(_dirties_cat_T_2, _dirties_cat_T_3)
node _dirties_cat_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _dirties_cat_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _dirties_cat_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _dirties_cat_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _dirties_cat_T_9 = or(_dirties_cat_T_5, _dirties_cat_T_6)
node _dirties_cat_T_10 = or(_dirties_cat_T_9, _dirties_cat_T_7)
node _dirties_cat_T_11 = or(_dirties_cat_T_10, _dirties_cat_T_8)
node _dirties_cat_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _dirties_cat_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _dirties_cat_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _dirties_cat_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _dirties_cat_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _dirties_cat_T_17 = or(_dirties_cat_T_12, _dirties_cat_T_13)
node _dirties_cat_T_18 = or(_dirties_cat_T_17, _dirties_cat_T_14)
node _dirties_cat_T_19 = or(_dirties_cat_T_18, _dirties_cat_T_15)
node _dirties_cat_T_20 = or(_dirties_cat_T_19, _dirties_cat_T_16)
node _dirties_cat_T_21 = or(_dirties_cat_T_11, _dirties_cat_T_20)
node _dirties_cat_T_22 = or(_dirties_cat_T_4, _dirties_cat_T_21)
node _dirties_cat_T_23 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _dirties_cat_T_24 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _dirties_cat_T_25 = or(_dirties_cat_T_23, _dirties_cat_T_24)
node _dirties_cat_T_26 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _dirties_cat_T_27 = or(_dirties_cat_T_25, _dirties_cat_T_26)
node _dirties_cat_T_28 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _dirties_cat_T_29 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _dirties_cat_T_30 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _dirties_cat_T_31 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _dirties_cat_T_32 = or(_dirties_cat_T_28, _dirties_cat_T_29)
node _dirties_cat_T_33 = or(_dirties_cat_T_32, _dirties_cat_T_30)
node _dirties_cat_T_34 = or(_dirties_cat_T_33, _dirties_cat_T_31)
node _dirties_cat_T_35 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _dirties_cat_T_36 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _dirties_cat_T_37 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _dirties_cat_T_38 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _dirties_cat_T_39 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _dirties_cat_T_40 = or(_dirties_cat_T_35, _dirties_cat_T_36)
node _dirties_cat_T_41 = or(_dirties_cat_T_40, _dirties_cat_T_37)
node _dirties_cat_T_42 = or(_dirties_cat_T_41, _dirties_cat_T_38)
node _dirties_cat_T_43 = or(_dirties_cat_T_42, _dirties_cat_T_39)
node _dirties_cat_T_44 = or(_dirties_cat_T_34, _dirties_cat_T_43)
node _dirties_cat_T_45 = or(_dirties_cat_T_27, _dirties_cat_T_44)
node _dirties_cat_T_46 = eq(io.req.uop.mem_cmd, UInt<2>(0h3))
node _dirties_cat_T_47 = or(_dirties_cat_T_45, _dirties_cat_T_46)
node _dirties_cat_T_48 = eq(io.req.uop.mem_cmd, UInt<3>(0h6))
node _dirties_cat_T_49 = or(_dirties_cat_T_47, _dirties_cat_T_48)
node dirties_cat = cat(_dirties_cat_T_22, _dirties_cat_T_49)
node _dirties_T = cat(UInt<1>(0h1), UInt<1>(0h1))
node dirties = eq(dirties_cat, _dirties_T)
node biggest_grow_param = mux(dirties, r2_2, r1_2)
wire dirtier_coh : { state : UInt<2>}
connect dirtier_coh.state, biggest_grow_param
node dirtier_cmd = mux(dirties, io.req.uop.mem_cmd, req.uop.mem_cmd)
node _T = and(io.mem_grant.ready, io.mem_grant.valid)
node _r_beats1_decode_T = dshl(UInt<12>(0hfff), io.mem_grant.bits.size)
node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 11, 0)
node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1)
node r_beats1_decode = shr(_r_beats1_decode_T_2, 3)
node r_beats1_opdata = bits(io.mem_grant.bits.opcode, 0, 0)
node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0))
regreset r_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _r_counter1_T = sub(r_counter, UInt<1>(0h1))
node r_counter1 = tail(_r_counter1_T, 1)
node r_1_1 = eq(r_counter, UInt<1>(0h0))
node _r_last_T = eq(r_counter, UInt<1>(0h1))
node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0))
node r_2 = or(_r_last_T, _r_last_T_1)
node refill_done = and(r_2, _T)
node _r_count_T = not(r_counter1)
node r_4 = and(r_beats1, _r_count_T)
when _T :
node _r_counter_T = mux(r_1_1, r_beats1, r_counter1)
connect r_counter, _r_counter_T
node refill_address_inc = shl(r_4, 3)
node _sec_rdy_T = eq(cmd_requires_second_acquire, UInt<1>(0h0))
node _sec_rdy_T_1 = eq(io.req_is_probe, UInt<1>(0h0))
node _sec_rdy_T_2 = and(_sec_rdy_T, _sec_rdy_T_1)
node _sec_rdy_T_3 = eq(state, UInt<5>(0h0))
node _sec_rdy_T_4 = eq(state, UInt<5>(0hd))
node _sec_rdy_T_5 = eq(state, UInt<5>(0he))
node _sec_rdy_T_6 = eq(state, UInt<5>(0hf))
node _sec_rdy_T_7 = or(_sec_rdy_T_3, _sec_rdy_T_4)
node _sec_rdy_T_8 = or(_sec_rdy_T_7, _sec_rdy_T_5)
node _sec_rdy_T_9 = or(_sec_rdy_T_8, _sec_rdy_T_6)
node _sec_rdy_T_10 = eq(_sec_rdy_T_9, UInt<1>(0h0))
node sec_rdy = and(_sec_rdy_T_2, _sec_rdy_T_10)
inst rpq of BranchKillableQueue_13
connect rpq.clock, clock
connect rpq.reset, reset
connect rpq.io.brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect rpq.io.brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect rpq.io.brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect rpq.io.brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect rpq.io.brupdate.b2.taken, io.brupdate.b2.taken
connect rpq.io.brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect rpq.io.brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect rpq.io.brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect rpq.io.brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect rpq.io.brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect rpq.io.brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect rpq.io.brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect rpq.io.brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect rpq.io.brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ
connect rpq.io.brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm
connect rpq.io.brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect rpq.io.brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op
connect rpq.io.brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw
connect rpq.io.brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect rpq.io.brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect rpq.io.brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect rpq.io.brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect rpq.io.brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect rpq.io.brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect rpq.io.brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect rpq.io.brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect rpq.io.brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect rpq.io.brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd
connect rpq.io.brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect rpq.io.brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect rpq.io.brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect rpq.io.brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect rpq.io.brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect rpq.io.brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect rpq.io.brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect rpq.io.brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect rpq.io.brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect rpq.io.brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect rpq.io.brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect rpq.io.brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect rpq.io.brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect rpq.io.brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect rpq.io.brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect rpq.io.brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect rpq.io.brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect rpq.io.brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect rpq.io.brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect rpq.io.brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect rpq.io.brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect rpq.io.brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect rpq.io.brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect rpq.io.brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec
connect rpq.io.brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags
connect rpq.io.brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt
connect rpq.io.brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div
connect rpq.io.brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma
connect rpq.io.brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe
connect rpq.io.brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint
connect rpq.io.brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint
connect rpq.io.brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut
connect rpq.io.brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn
connect rpq.io.brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23
connect rpq.io.brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12
connect rpq.io.brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3
connect rpq.io.brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2
connect rpq.io.brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1
connect rpq.io.brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen
connect rpq.io.brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst
connect rpq.io.brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel
connect rpq.io.brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel
connect rpq.io.brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect rpq.io.brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm
connect rpq.io.brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel
connect rpq.io.brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename
connect rpq.io.brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect rpq.io.brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect rpq.io.brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect rpq.io.brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect rpq.io.brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov
connect rpq.io.brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc
connect rpq.io.brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect rpq.io.brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret
connect rpq.io.brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect rpq.io.brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence
connect rpq.io.brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect rpq.io.brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect rpq.io.brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect rpq.io.brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type
connect rpq.io.brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect rpq.io.brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect rpq.io.brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel
connect rpq.io.brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint
connect rpq.io.brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint
connect rpq.io.brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint
connect rpq.io.brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child
connect rpq.io.brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child
connect rpq.io.brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen
connect rpq.io.brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen
connect rpq.io.brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued
connect rpq.io.brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0]
connect rpq.io.brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1]
connect rpq.io.brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2]
connect rpq.io.brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3]
connect rpq.io.brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4]
connect rpq.io.brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5]
connect rpq.io.brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6]
connect rpq.io.brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7]
connect rpq.io.brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8]
connect rpq.io.brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9]
connect rpq.io.brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0]
connect rpq.io.brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1]
connect rpq.io.brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2]
connect rpq.io.brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3]
connect rpq.io.brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect rpq.io.brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect rpq.io.brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect rpq.io.brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect rpq.io.brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect rpq.io.brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect rpq.io.flush, io.exception
node _T_1 = eq(state, UInt<5>(0h0))
node _T_2 = eq(rpq.io.empty, UInt<1>(0h0))
node _T_3 = and(_T_1, _T_2)
node _T_4 = eq(_T_3, UInt<1>(0h0))
node _T_5 = asUInt(reset)
node _T_6 = eq(_T_5, UInt<1>(0h0))
when _T_6 :
node _T_7 = eq(_T_4, UInt<1>(0h0))
when _T_7 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:131 assert(!(state === s_invalid && !rpq.io.empty))\n") : printf
assert(clock, _T_4, UInt<1>(0h1), "") : assert
node _rpq_io_enq_valid_T = and(io.req_pri_val, io.req_pri_rdy)
node _rpq_io_enq_valid_T_1 = and(io.req_sec_val, io.req_sec_rdy)
node _rpq_io_enq_valid_T_2 = or(_rpq_io_enq_valid_T, _rpq_io_enq_valid_T_1)
node _rpq_io_enq_valid_T_3 = eq(io.req.uop.mem_cmd, UInt<2>(0h2))
node _rpq_io_enq_valid_T_4 = eq(io.req.uop.mem_cmd, UInt<2>(0h3))
node _rpq_io_enq_valid_T_5 = or(_rpq_io_enq_valid_T_3, _rpq_io_enq_valid_T_4)
node _rpq_io_enq_valid_T_6 = eq(_rpq_io_enq_valid_T_5, UInt<1>(0h0))
node _rpq_io_enq_valid_T_7 = and(_rpq_io_enq_valid_T_2, _rpq_io_enq_valid_T_6)
connect rpq.io.enq.valid, _rpq_io_enq_valid_T_7
connect rpq.io.enq.bits.sdq_id, io.req.sdq_id
connect rpq.io.enq.bits.way_en, io.req.way_en
connect rpq.io.enq.bits.old_meta.tag, io.req.old_meta.tag
connect rpq.io.enq.bits.old_meta.coh.state, io.req.old_meta.coh.state
connect rpq.io.enq.bits.tag_match, io.req.tag_match
connect rpq.io.enq.bits.is_hella, io.req.is_hella
connect rpq.io.enq.bits.data, io.req.data
connect rpq.io.enq.bits.addr, io.req.addr
connect rpq.io.enq.bits.uop.debug_tsrc, io.req.uop.debug_tsrc
connect rpq.io.enq.bits.uop.debug_fsrc, io.req.uop.debug_fsrc
connect rpq.io.enq.bits.uop.bp_xcpt_if, io.req.uop.bp_xcpt_if
connect rpq.io.enq.bits.uop.bp_debug_if, io.req.uop.bp_debug_if
connect rpq.io.enq.bits.uop.xcpt_ma_if, io.req.uop.xcpt_ma_if
connect rpq.io.enq.bits.uop.xcpt_ae_if, io.req.uop.xcpt_ae_if
connect rpq.io.enq.bits.uop.xcpt_pf_if, io.req.uop.xcpt_pf_if
connect rpq.io.enq.bits.uop.fp_typ, io.req.uop.fp_typ
connect rpq.io.enq.bits.uop.fp_rm, io.req.uop.fp_rm
connect rpq.io.enq.bits.uop.fp_val, io.req.uop.fp_val
connect rpq.io.enq.bits.uop.fcn_op, io.req.uop.fcn_op
connect rpq.io.enq.bits.uop.fcn_dw, io.req.uop.fcn_dw
connect rpq.io.enq.bits.uop.frs3_en, io.req.uop.frs3_en
connect rpq.io.enq.bits.uop.lrs2_rtype, io.req.uop.lrs2_rtype
connect rpq.io.enq.bits.uop.lrs1_rtype, io.req.uop.lrs1_rtype
connect rpq.io.enq.bits.uop.dst_rtype, io.req.uop.dst_rtype
connect rpq.io.enq.bits.uop.lrs3, io.req.uop.lrs3
connect rpq.io.enq.bits.uop.lrs2, io.req.uop.lrs2
connect rpq.io.enq.bits.uop.lrs1, io.req.uop.lrs1
connect rpq.io.enq.bits.uop.ldst, io.req.uop.ldst
connect rpq.io.enq.bits.uop.ldst_is_rs1, io.req.uop.ldst_is_rs1
connect rpq.io.enq.bits.uop.csr_cmd, io.req.uop.csr_cmd
connect rpq.io.enq.bits.uop.flush_on_commit, io.req.uop.flush_on_commit
connect rpq.io.enq.bits.uop.is_unique, io.req.uop.is_unique
connect rpq.io.enq.bits.uop.uses_stq, io.req.uop.uses_stq
connect rpq.io.enq.bits.uop.uses_ldq, io.req.uop.uses_ldq
connect rpq.io.enq.bits.uop.mem_signed, io.req.uop.mem_signed
connect rpq.io.enq.bits.uop.mem_size, io.req.uop.mem_size
connect rpq.io.enq.bits.uop.mem_cmd, io.req.uop.mem_cmd
connect rpq.io.enq.bits.uop.exc_cause, io.req.uop.exc_cause
connect rpq.io.enq.bits.uop.exception, io.req.uop.exception
connect rpq.io.enq.bits.uop.stale_pdst, io.req.uop.stale_pdst
connect rpq.io.enq.bits.uop.ppred_busy, io.req.uop.ppred_busy
connect rpq.io.enq.bits.uop.prs3_busy, io.req.uop.prs3_busy
connect rpq.io.enq.bits.uop.prs2_busy, io.req.uop.prs2_busy
connect rpq.io.enq.bits.uop.prs1_busy, io.req.uop.prs1_busy
connect rpq.io.enq.bits.uop.ppred, io.req.uop.ppred
connect rpq.io.enq.bits.uop.prs3, io.req.uop.prs3
connect rpq.io.enq.bits.uop.prs2, io.req.uop.prs2
connect rpq.io.enq.bits.uop.prs1, io.req.uop.prs1
connect rpq.io.enq.bits.uop.pdst, io.req.uop.pdst
connect rpq.io.enq.bits.uop.rxq_idx, io.req.uop.rxq_idx
connect rpq.io.enq.bits.uop.stq_idx, io.req.uop.stq_idx
connect rpq.io.enq.bits.uop.ldq_idx, io.req.uop.ldq_idx
connect rpq.io.enq.bits.uop.rob_idx, io.req.uop.rob_idx
connect rpq.io.enq.bits.uop.fp_ctrl.vec, io.req.uop.fp_ctrl.vec
connect rpq.io.enq.bits.uop.fp_ctrl.wflags, io.req.uop.fp_ctrl.wflags
connect rpq.io.enq.bits.uop.fp_ctrl.sqrt, io.req.uop.fp_ctrl.sqrt
connect rpq.io.enq.bits.uop.fp_ctrl.div, io.req.uop.fp_ctrl.div
connect rpq.io.enq.bits.uop.fp_ctrl.fma, io.req.uop.fp_ctrl.fma
connect rpq.io.enq.bits.uop.fp_ctrl.fastpipe, io.req.uop.fp_ctrl.fastpipe
connect rpq.io.enq.bits.uop.fp_ctrl.toint, io.req.uop.fp_ctrl.toint
connect rpq.io.enq.bits.uop.fp_ctrl.fromint, io.req.uop.fp_ctrl.fromint
connect rpq.io.enq.bits.uop.fp_ctrl.typeTagOut, io.req.uop.fp_ctrl.typeTagOut
connect rpq.io.enq.bits.uop.fp_ctrl.typeTagIn, io.req.uop.fp_ctrl.typeTagIn
connect rpq.io.enq.bits.uop.fp_ctrl.swap23, io.req.uop.fp_ctrl.swap23
connect rpq.io.enq.bits.uop.fp_ctrl.swap12, io.req.uop.fp_ctrl.swap12
connect rpq.io.enq.bits.uop.fp_ctrl.ren3, io.req.uop.fp_ctrl.ren3
connect rpq.io.enq.bits.uop.fp_ctrl.ren2, io.req.uop.fp_ctrl.ren2
connect rpq.io.enq.bits.uop.fp_ctrl.ren1, io.req.uop.fp_ctrl.ren1
connect rpq.io.enq.bits.uop.fp_ctrl.wen, io.req.uop.fp_ctrl.wen
connect rpq.io.enq.bits.uop.fp_ctrl.ldst, io.req.uop.fp_ctrl.ldst
connect rpq.io.enq.bits.uop.op2_sel, io.req.uop.op2_sel
connect rpq.io.enq.bits.uop.op1_sel, io.req.uop.op1_sel
connect rpq.io.enq.bits.uop.imm_packed, io.req.uop.imm_packed
connect rpq.io.enq.bits.uop.pimm, io.req.uop.pimm
connect rpq.io.enq.bits.uop.imm_sel, io.req.uop.imm_sel
connect rpq.io.enq.bits.uop.imm_rename, io.req.uop.imm_rename
connect rpq.io.enq.bits.uop.taken, io.req.uop.taken
connect rpq.io.enq.bits.uop.pc_lob, io.req.uop.pc_lob
connect rpq.io.enq.bits.uop.edge_inst, io.req.uop.edge_inst
connect rpq.io.enq.bits.uop.ftq_idx, io.req.uop.ftq_idx
connect rpq.io.enq.bits.uop.is_mov, io.req.uop.is_mov
connect rpq.io.enq.bits.uop.is_rocc, io.req.uop.is_rocc
connect rpq.io.enq.bits.uop.is_sys_pc2epc, io.req.uop.is_sys_pc2epc
connect rpq.io.enq.bits.uop.is_eret, io.req.uop.is_eret
connect rpq.io.enq.bits.uop.is_amo, io.req.uop.is_amo
connect rpq.io.enq.bits.uop.is_sfence, io.req.uop.is_sfence
connect rpq.io.enq.bits.uop.is_fencei, io.req.uop.is_fencei
connect rpq.io.enq.bits.uop.is_fence, io.req.uop.is_fence
connect rpq.io.enq.bits.uop.is_sfb, io.req.uop.is_sfb
connect rpq.io.enq.bits.uop.br_type, io.req.uop.br_type
connect rpq.io.enq.bits.uop.br_tag, io.req.uop.br_tag
connect rpq.io.enq.bits.uop.br_mask, io.req.uop.br_mask
connect rpq.io.enq.bits.uop.dis_col_sel, io.req.uop.dis_col_sel
connect rpq.io.enq.bits.uop.iw_p3_bypass_hint, io.req.uop.iw_p3_bypass_hint
connect rpq.io.enq.bits.uop.iw_p2_bypass_hint, io.req.uop.iw_p2_bypass_hint
connect rpq.io.enq.bits.uop.iw_p1_bypass_hint, io.req.uop.iw_p1_bypass_hint
connect rpq.io.enq.bits.uop.iw_p2_speculative_child, io.req.uop.iw_p2_speculative_child
connect rpq.io.enq.bits.uop.iw_p1_speculative_child, io.req.uop.iw_p1_speculative_child
connect rpq.io.enq.bits.uop.iw_issued_partial_dgen, io.req.uop.iw_issued_partial_dgen
connect rpq.io.enq.bits.uop.iw_issued_partial_agen, io.req.uop.iw_issued_partial_agen
connect rpq.io.enq.bits.uop.iw_issued, io.req.uop.iw_issued
connect rpq.io.enq.bits.uop.fu_code[0], io.req.uop.fu_code[0]
connect rpq.io.enq.bits.uop.fu_code[1], io.req.uop.fu_code[1]
connect rpq.io.enq.bits.uop.fu_code[2], io.req.uop.fu_code[2]
connect rpq.io.enq.bits.uop.fu_code[3], io.req.uop.fu_code[3]
connect rpq.io.enq.bits.uop.fu_code[4], io.req.uop.fu_code[4]
connect rpq.io.enq.bits.uop.fu_code[5], io.req.uop.fu_code[5]
connect rpq.io.enq.bits.uop.fu_code[6], io.req.uop.fu_code[6]
connect rpq.io.enq.bits.uop.fu_code[7], io.req.uop.fu_code[7]
connect rpq.io.enq.bits.uop.fu_code[8], io.req.uop.fu_code[8]
connect rpq.io.enq.bits.uop.fu_code[9], io.req.uop.fu_code[9]
connect rpq.io.enq.bits.uop.iq_type[0], io.req.uop.iq_type[0]
connect rpq.io.enq.bits.uop.iq_type[1], io.req.uop.iq_type[1]
connect rpq.io.enq.bits.uop.iq_type[2], io.req.uop.iq_type[2]
connect rpq.io.enq.bits.uop.iq_type[3], io.req.uop.iq_type[3]
connect rpq.io.enq.bits.uop.debug_pc, io.req.uop.debug_pc
connect rpq.io.enq.bits.uop.is_rvc, io.req.uop.is_rvc
connect rpq.io.enq.bits.uop.debug_inst, io.req.uop.debug_inst
connect rpq.io.enq.bits.uop.inst, io.req.uop.inst
connect rpq.io.deq.ready, UInt<1>(0h0)
reg grantack : { valid : UInt<1>, bits : { sink : UInt<3>}}, clock
reg refill_ctr : UInt<3>, clock
reg commit_line : UInt<1>, clock
reg grant_had_data : UInt<1>, clock
reg finish_to_prefetch : UInt<1>, clock
regreset meta_hazard : UInt<2>, clock, reset, UInt<2>(0h0)
node _T_8 = neq(meta_hazard, UInt<1>(0h0))
when _T_8 :
node _meta_hazard_T = add(meta_hazard, UInt<1>(0h1))
node _meta_hazard_T_1 = tail(_meta_hazard_T, 1)
connect meta_hazard, _meta_hazard_T_1
node _T_9 = and(io.meta_write.ready, io.meta_write.valid)
when _T_9 :
connect meta_hazard, UInt<1>(0h1)
node _io_probe_rdy_T = eq(meta_hazard, UInt<1>(0h0))
node _io_probe_rdy_T_1 = eq(state, UInt<5>(0h0))
node _io_probe_rdy_T_2 = eq(state, UInt<5>(0h1))
node _io_probe_rdy_T_3 = eq(state, UInt<5>(0h2))
node _io_probe_rdy_T_4 = eq(state, UInt<5>(0h3))
node _io_probe_rdy_T_5 = or(_io_probe_rdy_T_1, _io_probe_rdy_T_2)
node _io_probe_rdy_T_6 = or(_io_probe_rdy_T_5, _io_probe_rdy_T_3)
node _io_probe_rdy_T_7 = or(_io_probe_rdy_T_6, _io_probe_rdy_T_4)
node _io_probe_rdy_T_8 = eq(state, UInt<5>(0h4))
node _io_probe_rdy_T_9 = and(_io_probe_rdy_T_8, grantack.valid)
node _io_probe_rdy_T_10 = or(_io_probe_rdy_T_7, _io_probe_rdy_T_9)
node _io_probe_rdy_T_11 = and(_io_probe_rdy_T, _io_probe_rdy_T_10)
connect io.probe_rdy, _io_probe_rdy_T_11
node _io_idx_valid_T = neq(state, UInt<5>(0h0))
connect io.idx.valid, _io_idx_valid_T
node _io_tag_valid_T = neq(state, UInt<5>(0h0))
connect io.tag.valid, _io_tag_valid_T
node _io_way_valid_T = eq(state, UInt<5>(0h0))
node _io_way_valid_T_1 = eq(state, UInt<5>(0h11))
node _io_way_valid_T_2 = or(_io_way_valid_T, _io_way_valid_T_1)
node _io_way_valid_T_3 = eq(_io_way_valid_T_2, UInt<1>(0h0))
connect io.way.valid, _io_way_valid_T_3
connect io.idx.bits, req_idx
connect io.tag.bits, req_tag
connect io.way.bits, req.way_en
connect io.meta_write.valid, UInt<1>(0h0)
connect io.meta_write.bits.idx, req_idx
connect io.meta_write.bits.data.coh, coh_on_clear
connect io.meta_write.bits.data.tag, req_tag
connect io.meta_write.bits.way_en, req.way_en
connect io.meta_write.bits.tag, req_tag
connect io.req_pri_rdy, UInt<1>(0h0)
node _io_req_sec_rdy_T = and(sec_rdy, rpq.io.enq.ready)
connect io.req_sec_rdy, _io_req_sec_rdy_T
connect io.mem_acquire.valid, UInt<1>(0h0)
node _io_mem_acquire_bits_T = cat(req_tag, req_idx)
node _io_mem_acquire_bits_T_1 = shl(_io_mem_acquire_bits_T, 6)
node _io_mem_acquire_bits_legal_T = or(UInt<1>(0h0), UInt<1>(0h0))
node _io_mem_acquire_bits_legal_T_1 = xor(_io_mem_acquire_bits_T_1, UInt<1>(0h0))
node _io_mem_acquire_bits_legal_T_2 = cvt(_io_mem_acquire_bits_legal_T_1)
node _io_mem_acquire_bits_legal_T_3 = and(_io_mem_acquire_bits_legal_T_2, asSInt(UInt<33>(0h80000000)))
node _io_mem_acquire_bits_legal_T_4 = asSInt(_io_mem_acquire_bits_legal_T_3)
node _io_mem_acquire_bits_legal_T_5 = eq(_io_mem_acquire_bits_legal_T_4, asSInt(UInt<1>(0h0)))
node _io_mem_acquire_bits_legal_T_6 = and(_io_mem_acquire_bits_legal_T, _io_mem_acquire_bits_legal_T_5)
node _io_mem_acquire_bits_legal_T_7 = eq(UInt<3>(0h6), UInt<3>(0h6))
node _io_mem_acquire_bits_legal_T_8 = or(UInt<1>(0h0), _io_mem_acquire_bits_legal_T_7)
node _io_mem_acquire_bits_legal_T_9 = xor(_io_mem_acquire_bits_T_1, UInt<32>(0h80000000))
node _io_mem_acquire_bits_legal_T_10 = cvt(_io_mem_acquire_bits_legal_T_9)
node _io_mem_acquire_bits_legal_T_11 = and(_io_mem_acquire_bits_legal_T_10, asSInt(UInt<33>(0h80000000)))
node _io_mem_acquire_bits_legal_T_12 = asSInt(_io_mem_acquire_bits_legal_T_11)
node _io_mem_acquire_bits_legal_T_13 = eq(_io_mem_acquire_bits_legal_T_12, asSInt(UInt<1>(0h0)))
node _io_mem_acquire_bits_legal_T_14 = and(_io_mem_acquire_bits_legal_T_8, _io_mem_acquire_bits_legal_T_13)
node _io_mem_acquire_bits_legal_T_15 = or(UInt<1>(0h0), _io_mem_acquire_bits_legal_T_6)
node io_mem_acquire_bits_legal = or(_io_mem_acquire_bits_legal_T_15, _io_mem_acquire_bits_legal_T_14)
wire io_mem_acquire_bits_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect io_mem_acquire_bits_a.opcode, UInt<3>(0h6)
connect io_mem_acquire_bits_a.param, grow_param
connect io_mem_acquire_bits_a.size, UInt<3>(0h6)
connect io_mem_acquire_bits_a.source, io.id
connect io_mem_acquire_bits_a.address, _io_mem_acquire_bits_T_1
node _io_mem_acquire_bits_a_mask_sizeOH_T = or(UInt<3>(0h6), UInt<3>(0h0))
node io_mem_acquire_bits_a_mask_sizeOH_shiftAmount = bits(_io_mem_acquire_bits_a_mask_sizeOH_T, 1, 0)
node _io_mem_acquire_bits_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sizeOH_shiftAmount)
node _io_mem_acquire_bits_a_mask_sizeOH_T_2 = bits(_io_mem_acquire_bits_a_mask_sizeOH_T_1, 2, 0)
node io_mem_acquire_bits_a_mask_sizeOH = or(_io_mem_acquire_bits_a_mask_sizeOH_T_2, UInt<1>(0h1))
node io_mem_acquire_bits_a_mask_sub_sub_sub_0_1 = geq(UInt<3>(0h6), UInt<2>(0h3))
node io_mem_acquire_bits_a_mask_sub_sub_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 2, 2)
node io_mem_acquire_bits_a_mask_sub_sub_bit = bits(_io_mem_acquire_bits_T_1, 2, 2)
node io_mem_acquire_bits_a_mask_sub_sub_nbit = eq(io_mem_acquire_bits_a_mask_sub_sub_bit, UInt<1>(0h0))
node io_mem_acquire_bits_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sub_sub_nbit)
node _io_mem_acquire_bits_a_mask_sub_sub_acc_T = and(io_mem_acquire_bits_a_mask_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_0_2)
node io_mem_acquire_bits_a_mask_sub_sub_0_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_sub_acc_T)
node io_mem_acquire_bits_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sub_sub_bit)
node _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1 = and(io_mem_acquire_bits_a_mask_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_1_2)
node io_mem_acquire_bits_a_mask_sub_sub_1_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1)
node io_mem_acquire_bits_a_mask_sub_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 1, 1)
node io_mem_acquire_bits_a_mask_sub_bit = bits(_io_mem_acquire_bits_T_1, 1, 1)
node io_mem_acquire_bits_a_mask_sub_nbit = eq(io_mem_acquire_bits_a_mask_sub_bit, UInt<1>(0h0))
node io_mem_acquire_bits_a_mask_sub_0_2 = and(io_mem_acquire_bits_a_mask_sub_sub_0_2, io_mem_acquire_bits_a_mask_sub_nbit)
node _io_mem_acquire_bits_a_mask_sub_acc_T = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_0_2)
node io_mem_acquire_bits_a_mask_sub_0_1 = or(io_mem_acquire_bits_a_mask_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_acc_T)
node io_mem_acquire_bits_a_mask_sub_1_2 = and(io_mem_acquire_bits_a_mask_sub_sub_0_2, io_mem_acquire_bits_a_mask_sub_bit)
node _io_mem_acquire_bits_a_mask_sub_acc_T_1 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_1_2)
node io_mem_acquire_bits_a_mask_sub_1_1 = or(io_mem_acquire_bits_a_mask_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_acc_T_1)
node io_mem_acquire_bits_a_mask_sub_2_2 = and(io_mem_acquire_bits_a_mask_sub_sub_1_2, io_mem_acquire_bits_a_mask_sub_nbit)
node _io_mem_acquire_bits_a_mask_sub_acc_T_2 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_2_2)
node io_mem_acquire_bits_a_mask_sub_2_1 = or(io_mem_acquire_bits_a_mask_sub_sub_1_1, _io_mem_acquire_bits_a_mask_sub_acc_T_2)
node io_mem_acquire_bits_a_mask_sub_3_2 = and(io_mem_acquire_bits_a_mask_sub_sub_1_2, io_mem_acquire_bits_a_mask_sub_bit)
node _io_mem_acquire_bits_a_mask_sub_acc_T_3 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_3_2)
node io_mem_acquire_bits_a_mask_sub_3_1 = or(io_mem_acquire_bits_a_mask_sub_sub_1_1, _io_mem_acquire_bits_a_mask_sub_acc_T_3)
node io_mem_acquire_bits_a_mask_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 0, 0)
node io_mem_acquire_bits_a_mask_bit = bits(_io_mem_acquire_bits_T_1, 0, 0)
node io_mem_acquire_bits_a_mask_nbit = eq(io_mem_acquire_bits_a_mask_bit, UInt<1>(0h0))
node io_mem_acquire_bits_a_mask_eq = and(io_mem_acquire_bits_a_mask_sub_0_2, io_mem_acquire_bits_a_mask_nbit)
node _io_mem_acquire_bits_a_mask_acc_T = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq)
node io_mem_acquire_bits_a_mask_acc = or(io_mem_acquire_bits_a_mask_sub_0_1, _io_mem_acquire_bits_a_mask_acc_T)
node io_mem_acquire_bits_a_mask_eq_1 = and(io_mem_acquire_bits_a_mask_sub_0_2, io_mem_acquire_bits_a_mask_bit)
node _io_mem_acquire_bits_a_mask_acc_T_1 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_1)
node io_mem_acquire_bits_a_mask_acc_1 = or(io_mem_acquire_bits_a_mask_sub_0_1, _io_mem_acquire_bits_a_mask_acc_T_1)
node io_mem_acquire_bits_a_mask_eq_2 = and(io_mem_acquire_bits_a_mask_sub_1_2, io_mem_acquire_bits_a_mask_nbit)
node _io_mem_acquire_bits_a_mask_acc_T_2 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_2)
node io_mem_acquire_bits_a_mask_acc_2 = or(io_mem_acquire_bits_a_mask_sub_1_1, _io_mem_acquire_bits_a_mask_acc_T_2)
node io_mem_acquire_bits_a_mask_eq_3 = and(io_mem_acquire_bits_a_mask_sub_1_2, io_mem_acquire_bits_a_mask_bit)
node _io_mem_acquire_bits_a_mask_acc_T_3 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_3)
node io_mem_acquire_bits_a_mask_acc_3 = or(io_mem_acquire_bits_a_mask_sub_1_1, _io_mem_acquire_bits_a_mask_acc_T_3)
node io_mem_acquire_bits_a_mask_eq_4 = and(io_mem_acquire_bits_a_mask_sub_2_2, io_mem_acquire_bits_a_mask_nbit)
node _io_mem_acquire_bits_a_mask_acc_T_4 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_4)
node io_mem_acquire_bits_a_mask_acc_4 = or(io_mem_acquire_bits_a_mask_sub_2_1, _io_mem_acquire_bits_a_mask_acc_T_4)
node io_mem_acquire_bits_a_mask_eq_5 = and(io_mem_acquire_bits_a_mask_sub_2_2, io_mem_acquire_bits_a_mask_bit)
node _io_mem_acquire_bits_a_mask_acc_T_5 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_5)
node io_mem_acquire_bits_a_mask_acc_5 = or(io_mem_acquire_bits_a_mask_sub_2_1, _io_mem_acquire_bits_a_mask_acc_T_5)
node io_mem_acquire_bits_a_mask_eq_6 = and(io_mem_acquire_bits_a_mask_sub_3_2, io_mem_acquire_bits_a_mask_nbit)
node _io_mem_acquire_bits_a_mask_acc_T_6 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_6)
node io_mem_acquire_bits_a_mask_acc_6 = or(io_mem_acquire_bits_a_mask_sub_3_1, _io_mem_acquire_bits_a_mask_acc_T_6)
node io_mem_acquire_bits_a_mask_eq_7 = and(io_mem_acquire_bits_a_mask_sub_3_2, io_mem_acquire_bits_a_mask_bit)
node _io_mem_acquire_bits_a_mask_acc_T_7 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_7)
node io_mem_acquire_bits_a_mask_acc_7 = or(io_mem_acquire_bits_a_mask_sub_3_1, _io_mem_acquire_bits_a_mask_acc_T_7)
node io_mem_acquire_bits_a_mask_lo_lo = cat(io_mem_acquire_bits_a_mask_acc_1, io_mem_acquire_bits_a_mask_acc)
node io_mem_acquire_bits_a_mask_lo_hi = cat(io_mem_acquire_bits_a_mask_acc_3, io_mem_acquire_bits_a_mask_acc_2)
node io_mem_acquire_bits_a_mask_lo = cat(io_mem_acquire_bits_a_mask_lo_hi, io_mem_acquire_bits_a_mask_lo_lo)
node io_mem_acquire_bits_a_mask_hi_lo = cat(io_mem_acquire_bits_a_mask_acc_5, io_mem_acquire_bits_a_mask_acc_4)
node io_mem_acquire_bits_a_mask_hi_hi = cat(io_mem_acquire_bits_a_mask_acc_7, io_mem_acquire_bits_a_mask_acc_6)
node io_mem_acquire_bits_a_mask_hi = cat(io_mem_acquire_bits_a_mask_hi_hi, io_mem_acquire_bits_a_mask_hi_lo)
node _io_mem_acquire_bits_a_mask_T = cat(io_mem_acquire_bits_a_mask_hi, io_mem_acquire_bits_a_mask_lo)
connect io_mem_acquire_bits_a.mask, _io_mem_acquire_bits_a_mask_T
invalidate io_mem_acquire_bits_a.data
connect io_mem_acquire_bits_a.corrupt, UInt<1>(0h0)
connect io.mem_acquire.bits, io_mem_acquire_bits_a
connect io.refill.valid, UInt<1>(0h0)
node _io_refill_bits_addr_T = shl(refill_ctr, 3)
node _io_refill_bits_addr_T_1 = or(req_block_addr, _io_refill_bits_addr_T)
connect io.refill.bits.addr, _io_refill_bits_addr_T_1
connect io.refill.bits.way_en, req.way_en
node _io_refill_bits_wmask_T = not(UInt<1>(0h0))
connect io.refill.bits.wmask, _io_refill_bits_wmask_T
connect io.refill.bits.data, io.lb_resp
connect io.replay.valid, UInt<1>(0h0)
connect io.replay.bits, rpq.io.deq.bits
connect io.wb_req.valid, UInt<1>(0h0)
connect io.wb_req.bits.tag, req.old_meta.tag
connect io.wb_req.bits.idx, req_idx
connect io.wb_req.bits.param, shrink_param
connect io.wb_req.bits.way_en, req.way_en
connect io.wb_req.bits.source, io.id
connect io.wb_req.bits.voluntary, UInt<1>(0h1)
connect io.resp.valid, UInt<1>(0h0)
connect io.resp.bits.is_hella, rpq.io.deq.bits.is_hella
connect io.resp.bits.data, rpq.io.deq.bits.data
connect io.resp.bits.uop, rpq.io.deq.bits.uop
connect io.commit_val, UInt<1>(0h0)
connect io.commit_addr, req.addr
connect io.commit_coh, coh_on_grant
connect io.meta_read.valid, UInt<1>(0h0)
connect io.meta_read.bits.idx, req_idx
connect io.meta_read.bits.tag, req_tag
connect io.meta_read.bits.way_en, req.way_en
connect io.mem_finish.valid, UInt<1>(0h0)
connect io.mem_finish.bits, grantack.bits
connect io.lb_write.valid, UInt<1>(0h0)
node _io_lb_write_bits_offset_T = shr(refill_address_inc, 3)
connect io.lb_write.bits.offset, _io_lb_write_bits_offset_T
connect io.lb_write.bits.data, io.mem_grant.bits.data
connect io.mem_grant.ready, UInt<1>(0h0)
node _io_lb_read_offset_T = shr(rpq.io.deq.bits.addr, 3)
connect io.lb_read.offset, _io_lb_read_offset_T
node _T_10 = and(io.req_sec_val, io.req_sec_rdy)
when _T_10 :
connect req.uop.mem_cmd, dirtier_cmd
when is_hit_again :
connect new_coh, dirtier_coh
node _T_11 = eq(state, UInt<5>(0h0))
when _T_11 :
connect io.req_pri_rdy, UInt<1>(0h1)
connect grant_had_data, UInt<1>(0h0)
node _T_12 = and(io.req_pri_val, io.req_pri_rdy)
when _T_12 :
wire state_new_state : UInt
connect state_new_state, state
connect grantack.valid, UInt<1>(0h0)
connect refill_ctr, UInt<1>(0h0)
node _state_T = asUInt(reset)
node _state_T_1 = eq(_state_T, UInt<1>(0h0))
when _state_T_1 :
node _state_T_2 = eq(rpq.io.enq.ready, UInt<1>(0h0))
when _state_T_2 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:213 assert(rpq.io.enq.ready)\n") : state_printf
assert(clock, rpq.io.enq.ready, UInt<1>(0h1), "") : state_assert
connect req, io.req
node _state_req_needs_wb_r_T = eq(UInt<5>(0h10), UInt<5>(0h10))
node _state_req_needs_wb_r_T_1 = mux(_state_req_needs_wb_r_T, UInt<2>(0h2), UInt<2>(0h2))
node _state_req_needs_wb_r_T_2 = eq(UInt<5>(0h12), UInt<5>(0h10))
node _state_req_needs_wb_r_T_3 = mux(_state_req_needs_wb_r_T_2, UInt<2>(0h1), _state_req_needs_wb_r_T_1)
node _state_req_needs_wb_r_T_4 = eq(UInt<5>(0h13), UInt<5>(0h10))
node _state_req_needs_wb_r_T_5 = mux(_state_req_needs_wb_r_T_4, UInt<2>(0h0), _state_req_needs_wb_r_T_3)
node _state_req_needs_wb_r_T_6 = cat(_state_req_needs_wb_r_T_5, io.req.old_meta.coh.state)
node _state_req_needs_wb_r_T_7 = cat(UInt<2>(0h0), UInt<2>(0h3))
node _state_req_needs_wb_r_T_8 = cat(UInt<2>(0h0), UInt<2>(0h2))
node _state_req_needs_wb_r_T_9 = cat(UInt<2>(0h0), UInt<2>(0h1))
node _state_req_needs_wb_r_T_10 = cat(UInt<2>(0h0), UInt<2>(0h0))
node _state_req_needs_wb_r_T_11 = cat(UInt<2>(0h1), UInt<2>(0h3))
node _state_req_needs_wb_r_T_12 = cat(UInt<2>(0h1), UInt<2>(0h2))
node _state_req_needs_wb_r_T_13 = cat(UInt<2>(0h1), UInt<2>(0h1))
node _state_req_needs_wb_r_T_14 = cat(UInt<2>(0h1), UInt<2>(0h0))
node _state_req_needs_wb_r_T_15 = cat(UInt<2>(0h2), UInt<2>(0h3))
node _state_req_needs_wb_r_T_16 = cat(UInt<2>(0h2), UInt<2>(0h2))
node _state_req_needs_wb_r_T_17 = cat(UInt<2>(0h2), UInt<2>(0h1))
node _state_req_needs_wb_r_T_18 = cat(UInt<2>(0h2), UInt<2>(0h0))
node _state_req_needs_wb_r_T_19 = eq(_state_req_needs_wb_r_T_18, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_20 = mux(_state_req_needs_wb_r_T_19, UInt<1>(0h0), UInt<1>(0h0))
node _state_req_needs_wb_r_T_21 = mux(_state_req_needs_wb_r_T_19, UInt<3>(0h5), UInt<1>(0h0))
node _state_req_needs_wb_r_T_22 = mux(_state_req_needs_wb_r_T_19, UInt<2>(0h0), UInt<1>(0h0))
node _state_req_needs_wb_r_T_23 = eq(_state_req_needs_wb_r_T_17, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_24 = mux(_state_req_needs_wb_r_T_23, UInt<1>(0h0), _state_req_needs_wb_r_T_20)
node _state_req_needs_wb_r_T_25 = mux(_state_req_needs_wb_r_T_23, UInt<3>(0h2), _state_req_needs_wb_r_T_21)
node _state_req_needs_wb_r_T_26 = mux(_state_req_needs_wb_r_T_23, UInt<2>(0h0), _state_req_needs_wb_r_T_22)
node _state_req_needs_wb_r_T_27 = eq(_state_req_needs_wb_r_T_16, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_28 = mux(_state_req_needs_wb_r_T_27, UInt<1>(0h0), _state_req_needs_wb_r_T_24)
node _state_req_needs_wb_r_T_29 = mux(_state_req_needs_wb_r_T_27, UInt<3>(0h1), _state_req_needs_wb_r_T_25)
node _state_req_needs_wb_r_T_30 = mux(_state_req_needs_wb_r_T_27, UInt<2>(0h0), _state_req_needs_wb_r_T_26)
node _state_req_needs_wb_r_T_31 = eq(_state_req_needs_wb_r_T_15, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_32 = mux(_state_req_needs_wb_r_T_31, UInt<1>(0h1), _state_req_needs_wb_r_T_28)
node _state_req_needs_wb_r_T_33 = mux(_state_req_needs_wb_r_T_31, UInt<3>(0h1), _state_req_needs_wb_r_T_29)
node _state_req_needs_wb_r_T_34 = mux(_state_req_needs_wb_r_T_31, UInt<2>(0h0), _state_req_needs_wb_r_T_30)
node _state_req_needs_wb_r_T_35 = eq(_state_req_needs_wb_r_T_14, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_36 = mux(_state_req_needs_wb_r_T_35, UInt<1>(0h0), _state_req_needs_wb_r_T_32)
node _state_req_needs_wb_r_T_37 = mux(_state_req_needs_wb_r_T_35, UInt<3>(0h5), _state_req_needs_wb_r_T_33)
node _state_req_needs_wb_r_T_38 = mux(_state_req_needs_wb_r_T_35, UInt<2>(0h0), _state_req_needs_wb_r_T_34)
node _state_req_needs_wb_r_T_39 = eq(_state_req_needs_wb_r_T_13, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_40 = mux(_state_req_needs_wb_r_T_39, UInt<1>(0h0), _state_req_needs_wb_r_T_36)
node _state_req_needs_wb_r_T_41 = mux(_state_req_needs_wb_r_T_39, UInt<3>(0h4), _state_req_needs_wb_r_T_37)
node _state_req_needs_wb_r_T_42 = mux(_state_req_needs_wb_r_T_39, UInt<2>(0h1), _state_req_needs_wb_r_T_38)
node _state_req_needs_wb_r_T_43 = eq(_state_req_needs_wb_r_T_12, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_44 = mux(_state_req_needs_wb_r_T_43, UInt<1>(0h0), _state_req_needs_wb_r_T_40)
node _state_req_needs_wb_r_T_45 = mux(_state_req_needs_wb_r_T_43, UInt<3>(0h0), _state_req_needs_wb_r_T_41)
node _state_req_needs_wb_r_T_46 = mux(_state_req_needs_wb_r_T_43, UInt<2>(0h1), _state_req_needs_wb_r_T_42)
node _state_req_needs_wb_r_T_47 = eq(_state_req_needs_wb_r_T_11, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_48 = mux(_state_req_needs_wb_r_T_47, UInt<1>(0h1), _state_req_needs_wb_r_T_44)
node _state_req_needs_wb_r_T_49 = mux(_state_req_needs_wb_r_T_47, UInt<3>(0h0), _state_req_needs_wb_r_T_45)
node _state_req_needs_wb_r_T_50 = mux(_state_req_needs_wb_r_T_47, UInt<2>(0h1), _state_req_needs_wb_r_T_46)
node _state_req_needs_wb_r_T_51 = eq(_state_req_needs_wb_r_T_10, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_52 = mux(_state_req_needs_wb_r_T_51, UInt<1>(0h0), _state_req_needs_wb_r_T_48)
node _state_req_needs_wb_r_T_53 = mux(_state_req_needs_wb_r_T_51, UInt<3>(0h5), _state_req_needs_wb_r_T_49)
node _state_req_needs_wb_r_T_54 = mux(_state_req_needs_wb_r_T_51, UInt<2>(0h0), _state_req_needs_wb_r_T_50)
node _state_req_needs_wb_r_T_55 = eq(_state_req_needs_wb_r_T_9, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_56 = mux(_state_req_needs_wb_r_T_55, UInt<1>(0h0), _state_req_needs_wb_r_T_52)
node _state_req_needs_wb_r_T_57 = mux(_state_req_needs_wb_r_T_55, UInt<3>(0h4), _state_req_needs_wb_r_T_53)
node _state_req_needs_wb_r_T_58 = mux(_state_req_needs_wb_r_T_55, UInt<2>(0h1), _state_req_needs_wb_r_T_54)
node _state_req_needs_wb_r_T_59 = eq(_state_req_needs_wb_r_T_8, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_60 = mux(_state_req_needs_wb_r_T_59, UInt<1>(0h0), _state_req_needs_wb_r_T_56)
node _state_req_needs_wb_r_T_61 = mux(_state_req_needs_wb_r_T_59, UInt<3>(0h3), _state_req_needs_wb_r_T_57)
node _state_req_needs_wb_r_T_62 = mux(_state_req_needs_wb_r_T_59, UInt<2>(0h2), _state_req_needs_wb_r_T_58)
node _state_req_needs_wb_r_T_63 = eq(_state_req_needs_wb_r_T_7, _state_req_needs_wb_r_T_6)
node state_req_needs_wb_r_1 = mux(_state_req_needs_wb_r_T_63, UInt<1>(0h1), _state_req_needs_wb_r_T_60)
node state_req_needs_wb_r_2 = mux(_state_req_needs_wb_r_T_63, UInt<3>(0h3), _state_req_needs_wb_r_T_61)
node state_req_needs_wb_r_3 = mux(_state_req_needs_wb_r_T_63, UInt<2>(0h2), _state_req_needs_wb_r_T_62)
wire state_req_needs_wb_meta : { state : UInt<2>}
connect state_req_needs_wb_meta.state, state_req_needs_wb_r_3
connect req_needs_wb, state_req_needs_wb_r_1
when io.req.tag_match :
node _state_r_c_cat_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _state_r_c_cat_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _state_r_c_cat_T_2 = or(_state_r_c_cat_T, _state_r_c_cat_T_1)
node _state_r_c_cat_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _state_r_c_cat_T_4 = or(_state_r_c_cat_T_2, _state_r_c_cat_T_3)
node _state_r_c_cat_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _state_r_c_cat_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _state_r_c_cat_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _state_r_c_cat_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _state_r_c_cat_T_9 = or(_state_r_c_cat_T_5, _state_r_c_cat_T_6)
node _state_r_c_cat_T_10 = or(_state_r_c_cat_T_9, _state_r_c_cat_T_7)
node _state_r_c_cat_T_11 = or(_state_r_c_cat_T_10, _state_r_c_cat_T_8)
node _state_r_c_cat_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _state_r_c_cat_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _state_r_c_cat_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _state_r_c_cat_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _state_r_c_cat_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _state_r_c_cat_T_17 = or(_state_r_c_cat_T_12, _state_r_c_cat_T_13)
node _state_r_c_cat_T_18 = or(_state_r_c_cat_T_17, _state_r_c_cat_T_14)
node _state_r_c_cat_T_19 = or(_state_r_c_cat_T_18, _state_r_c_cat_T_15)
node _state_r_c_cat_T_20 = or(_state_r_c_cat_T_19, _state_r_c_cat_T_16)
node _state_r_c_cat_T_21 = or(_state_r_c_cat_T_11, _state_r_c_cat_T_20)
node _state_r_c_cat_T_22 = or(_state_r_c_cat_T_4, _state_r_c_cat_T_21)
node _state_r_c_cat_T_23 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _state_r_c_cat_T_24 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _state_r_c_cat_T_25 = or(_state_r_c_cat_T_23, _state_r_c_cat_T_24)
node _state_r_c_cat_T_26 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _state_r_c_cat_T_27 = or(_state_r_c_cat_T_25, _state_r_c_cat_T_26)
node _state_r_c_cat_T_28 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _state_r_c_cat_T_29 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _state_r_c_cat_T_30 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _state_r_c_cat_T_31 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _state_r_c_cat_T_32 = or(_state_r_c_cat_T_28, _state_r_c_cat_T_29)
node _state_r_c_cat_T_33 = or(_state_r_c_cat_T_32, _state_r_c_cat_T_30)
node _state_r_c_cat_T_34 = or(_state_r_c_cat_T_33, _state_r_c_cat_T_31)
node _state_r_c_cat_T_35 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _state_r_c_cat_T_36 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _state_r_c_cat_T_37 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _state_r_c_cat_T_38 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _state_r_c_cat_T_39 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _state_r_c_cat_T_40 = or(_state_r_c_cat_T_35, _state_r_c_cat_T_36)
node _state_r_c_cat_T_41 = or(_state_r_c_cat_T_40, _state_r_c_cat_T_37)
node _state_r_c_cat_T_42 = or(_state_r_c_cat_T_41, _state_r_c_cat_T_38)
node _state_r_c_cat_T_43 = or(_state_r_c_cat_T_42, _state_r_c_cat_T_39)
node _state_r_c_cat_T_44 = or(_state_r_c_cat_T_34, _state_r_c_cat_T_43)
node _state_r_c_cat_T_45 = or(_state_r_c_cat_T_27, _state_r_c_cat_T_44)
node _state_r_c_cat_T_46 = eq(io.req.uop.mem_cmd, UInt<2>(0h3))
node _state_r_c_cat_T_47 = or(_state_r_c_cat_T_45, _state_r_c_cat_T_46)
node _state_r_c_cat_T_48 = eq(io.req.uop.mem_cmd, UInt<3>(0h6))
node _state_r_c_cat_T_49 = or(_state_r_c_cat_T_47, _state_r_c_cat_T_48)
node state_r_c = cat(_state_r_c_cat_T_22, _state_r_c_cat_T_49)
node _state_r_T = cat(state_r_c, io.req.old_meta.coh.state)
node _state_r_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_2 = cat(_state_r_T_1, UInt<2>(0h3))
node _state_r_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_4 = cat(_state_r_T_3, UInt<2>(0h2))
node _state_r_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_6 = cat(_state_r_T_5, UInt<2>(0h1))
node _state_r_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_8 = cat(_state_r_T_7, UInt<2>(0h3))
node _state_r_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_10 = cat(_state_r_T_9, UInt<2>(0h2))
node _state_r_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_12 = cat(_state_r_T_11, UInt<2>(0h3))
node _state_r_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_14 = cat(_state_r_T_13, UInt<2>(0h2))
node _state_r_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_16 = cat(_state_r_T_15, UInt<2>(0h0))
node _state_r_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_18 = cat(_state_r_T_17, UInt<2>(0h1))
node _state_r_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_20 = cat(_state_r_T_19, UInt<2>(0h0))
node _state_r_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_22 = cat(_state_r_T_21, UInt<2>(0h1))
node _state_r_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_24 = cat(_state_r_T_23, UInt<2>(0h0))
node _state_r_T_25 = eq(_state_r_T_24, _state_r_T)
node _state_r_T_26 = mux(_state_r_T_25, UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_27 = mux(_state_r_T_25, UInt<2>(0h1), UInt<1>(0h0))
node _state_r_T_28 = eq(_state_r_T_22, _state_r_T)
node _state_r_T_29 = mux(_state_r_T_28, UInt<1>(0h0), _state_r_T_26)
node _state_r_T_30 = mux(_state_r_T_28, UInt<2>(0h2), _state_r_T_27)
node _state_r_T_31 = eq(_state_r_T_20, _state_r_T)
node _state_r_T_32 = mux(_state_r_T_31, UInt<1>(0h0), _state_r_T_29)
node _state_r_T_33 = mux(_state_r_T_31, UInt<2>(0h1), _state_r_T_30)
node _state_r_T_34 = eq(_state_r_T_18, _state_r_T)
node _state_r_T_35 = mux(_state_r_T_34, UInt<1>(0h0), _state_r_T_32)
node _state_r_T_36 = mux(_state_r_T_34, UInt<2>(0h2), _state_r_T_33)
node _state_r_T_37 = eq(_state_r_T_16, _state_r_T)
node _state_r_T_38 = mux(_state_r_T_37, UInt<1>(0h0), _state_r_T_35)
node _state_r_T_39 = mux(_state_r_T_37, UInt<2>(0h0), _state_r_T_36)
node _state_r_T_40 = eq(_state_r_T_14, _state_r_T)
node _state_r_T_41 = mux(_state_r_T_40, UInt<1>(0h1), _state_r_T_38)
node _state_r_T_42 = mux(_state_r_T_40, UInt<2>(0h3), _state_r_T_39)
node _state_r_T_43 = eq(_state_r_T_12, _state_r_T)
node _state_r_T_44 = mux(_state_r_T_43, UInt<1>(0h1), _state_r_T_41)
node _state_r_T_45 = mux(_state_r_T_43, UInt<2>(0h3), _state_r_T_42)
node _state_r_T_46 = eq(_state_r_T_10, _state_r_T)
node _state_r_T_47 = mux(_state_r_T_46, UInt<1>(0h1), _state_r_T_44)
node _state_r_T_48 = mux(_state_r_T_46, UInt<2>(0h2), _state_r_T_45)
node _state_r_T_49 = eq(_state_r_T_8, _state_r_T)
node _state_r_T_50 = mux(_state_r_T_49, UInt<1>(0h1), _state_r_T_47)
node _state_r_T_51 = mux(_state_r_T_49, UInt<2>(0h3), _state_r_T_48)
node _state_r_T_52 = eq(_state_r_T_6, _state_r_T)
node _state_r_T_53 = mux(_state_r_T_52, UInt<1>(0h1), _state_r_T_50)
node _state_r_T_54 = mux(_state_r_T_52, UInt<2>(0h1), _state_r_T_51)
node _state_r_T_55 = eq(_state_r_T_4, _state_r_T)
node _state_r_T_56 = mux(_state_r_T_55, UInt<1>(0h1), _state_r_T_53)
node _state_r_T_57 = mux(_state_r_T_55, UInt<2>(0h2), _state_r_T_54)
node _state_r_T_58 = eq(_state_r_T_2, _state_r_T)
node state_is_hit = mux(_state_r_T_58, UInt<1>(0h1), _state_r_T_56)
node state_r_2 = mux(_state_r_T_58, UInt<2>(0h3), _state_r_T_57)
wire state_coh_on_hit : { state : UInt<2>}
connect state_coh_on_hit.state, state_r_2
when state_is_hit :
node _state_T_3 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _state_T_4 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _state_T_5 = or(_state_T_3, _state_T_4)
node _state_T_6 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _state_T_7 = or(_state_T_5, _state_T_6)
node _state_T_8 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _state_T_9 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _state_T_10 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _state_T_11 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _state_T_12 = or(_state_T_8, _state_T_9)
node _state_T_13 = or(_state_T_12, _state_T_10)
node _state_T_14 = or(_state_T_13, _state_T_11)
node _state_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _state_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _state_T_17 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _state_T_18 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _state_T_19 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _state_T_20 = or(_state_T_15, _state_T_16)
node _state_T_21 = or(_state_T_20, _state_T_17)
node _state_T_22 = or(_state_T_21, _state_T_18)
node _state_T_23 = or(_state_T_22, _state_T_19)
node _state_T_24 = or(_state_T_14, _state_T_23)
node _state_T_25 = or(_state_T_7, _state_T_24)
node _state_T_26 = asUInt(reset)
node _state_T_27 = eq(_state_T_26, UInt<1>(0h0))
when _state_T_27 :
node _state_T_28 = eq(_state_T_25, UInt<1>(0h0))
when _state_T_28 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:220 assert(isWrite(io.req.uop.mem_cmd))\n") : state_printf_1
assert(clock, _state_T_25, UInt<1>(0h1), "") : state_assert_1
connect new_coh, state_coh_on_hit
connect state_new_state, UInt<5>(0hc)
else :
connect new_coh, io.req.old_meta.coh
connect state_new_state, UInt<5>(0h1)
else :
wire state_new_coh_meta : { state : UInt<2>}
connect state_new_coh_meta.state, UInt<2>(0h0)
connect new_coh, state_new_coh_meta
connect state_new_state, UInt<5>(0h1)
connect state, state_new_state
else :
node _T_13 = eq(state, UInt<5>(0h1))
when _T_13 :
connect io.mem_acquire.valid, UInt<1>(0h1)
node _T_14 = and(io.mem_acquire.ready, io.mem_acquire.valid)
when _T_14 :
connect state, UInt<5>(0h2)
else :
node _T_15 = eq(state, UInt<5>(0h2))
when _T_15 :
connect io.mem_grant.ready, UInt<1>(0h1)
node opdata = bits(io.mem_grant.bits.opcode, 0, 0)
when opdata :
connect io.lb_write.valid, io.mem_grant.valid
else :
connect io.mem_grant.ready, UInt<1>(0h1)
node _T_16 = and(io.mem_grant.ready, io.mem_grant.valid)
when _T_16 :
node grant_had_data_opdata = bits(io.mem_grant.bits.opcode, 0, 0)
connect grant_had_data, grant_had_data_opdata
when refill_done :
node _grantack_valid_T = bits(io.mem_grant.bits.opcode, 2, 2)
node _grantack_valid_T_1 = bits(io.mem_grant.bits.opcode, 1, 1)
node _grantack_valid_T_2 = eq(_grantack_valid_T_1, UInt<1>(0h0))
node _grantack_valid_T_3 = and(_grantack_valid_T, _grantack_valid_T_2)
connect grantack.valid, _grantack_valid_T_3
wire grantack_bits_e : { sink : UInt<3>}
connect grantack_bits_e.sink, io.mem_grant.bits.sink
connect grantack.bits, grantack_bits_e
node _state_T_29 = mux(grant_had_data, UInt<5>(0h3), UInt<5>(0hc))
connect state, _state_T_29
node _T_17 = eq(grant_had_data, UInt<1>(0h0))
node _T_18 = and(_T_17, req_needs_wb)
node _T_19 = eq(_T_18, UInt<1>(0h0))
node _T_20 = asUInt(reset)
node _T_21 = eq(_T_20, UInt<1>(0h0))
when _T_21 :
node _T_22 = eq(_T_19, UInt<1>(0h0))
when _T_22 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:261 assert(!(!grant_had_data && req_needs_wb))\n") : printf_1
assert(clock, _T_19, UInt<1>(0h1), "") : assert_1
connect commit_line, UInt<1>(0h0)
connect new_coh, coh_on_grant
else :
node _T_23 = eq(state, UInt<5>(0h3))
when _T_23 :
node _drain_load_T = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h0))
node _drain_load_T_1 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h10))
node _drain_load_T_2 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h6))
node _drain_load_T_3 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7))
node _drain_load_T_4 = or(_drain_load_T, _drain_load_T_1)
node _drain_load_T_5 = or(_drain_load_T_4, _drain_load_T_2)
node _drain_load_T_6 = or(_drain_load_T_5, _drain_load_T_3)
node _drain_load_T_7 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4))
node _drain_load_T_8 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9))
node _drain_load_T_9 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha))
node _drain_load_T_10 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb))
node _drain_load_T_11 = or(_drain_load_T_7, _drain_load_T_8)
node _drain_load_T_12 = or(_drain_load_T_11, _drain_load_T_9)
node _drain_load_T_13 = or(_drain_load_T_12, _drain_load_T_10)
node _drain_load_T_14 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8))
node _drain_load_T_15 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc))
node _drain_load_T_16 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd))
node _drain_load_T_17 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he))
node _drain_load_T_18 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf))
node _drain_load_T_19 = or(_drain_load_T_14, _drain_load_T_15)
node _drain_load_T_20 = or(_drain_load_T_19, _drain_load_T_16)
node _drain_load_T_21 = or(_drain_load_T_20, _drain_load_T_17)
node _drain_load_T_22 = or(_drain_load_T_21, _drain_load_T_18)
node _drain_load_T_23 = or(_drain_load_T_13, _drain_load_T_22)
node _drain_load_T_24 = or(_drain_load_T_6, _drain_load_T_23)
node _drain_load_T_25 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1))
node _drain_load_T_26 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11))
node _drain_load_T_27 = or(_drain_load_T_25, _drain_load_T_26)
node _drain_load_T_28 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7))
node _drain_load_T_29 = or(_drain_load_T_27, _drain_load_T_28)
node _drain_load_T_30 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4))
node _drain_load_T_31 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9))
node _drain_load_T_32 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha))
node _drain_load_T_33 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb))
node _drain_load_T_34 = or(_drain_load_T_30, _drain_load_T_31)
node _drain_load_T_35 = or(_drain_load_T_34, _drain_load_T_32)
node _drain_load_T_36 = or(_drain_load_T_35, _drain_load_T_33)
node _drain_load_T_37 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8))
node _drain_load_T_38 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc))
node _drain_load_T_39 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd))
node _drain_load_T_40 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he))
node _drain_load_T_41 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf))
node _drain_load_T_42 = or(_drain_load_T_37, _drain_load_T_38)
node _drain_load_T_43 = or(_drain_load_T_42, _drain_load_T_39)
node _drain_load_T_44 = or(_drain_load_T_43, _drain_load_T_40)
node _drain_load_T_45 = or(_drain_load_T_44, _drain_load_T_41)
node _drain_load_T_46 = or(_drain_load_T_36, _drain_load_T_45)
node _drain_load_T_47 = or(_drain_load_T_29, _drain_load_T_46)
node _drain_load_T_48 = eq(_drain_load_T_47, UInt<1>(0h0))
node _drain_load_T_49 = and(_drain_load_T_24, _drain_load_T_48)
node _drain_load_T_50 = neq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h6))
node drain_load = and(_drain_load_T_49, _drain_load_T_50)
node _rp_addr_T = bits(rpq.io.deq.bits.addr, 5, 0)
node rp_addr_hi = cat(req_tag, req_idx)
node rp_addr = cat(rp_addr_hi, _rp_addr_T)
node _data_word_T = cat(UInt<1>(0h0), UInt<6>(0h0))
node data_word = dshr(io.lb_resp, _data_word_T)
node _T_24 = bits(rpq.io.deq.bits.addr, 5, 0)
node hi = cat(req_tag, req_idx)
node _T_25 = cat(hi, _T_24)
wire size : UInt<2>
connect size, rpq.io.deq.bits.uop.mem_size
node _rpq_io_deq_ready_T = and(io.resp.ready, drain_load)
connect rpq.io.deq.ready, _rpq_io_deq_ready_T
node _io_lb_read_offset_T_1 = shr(rpq.io.deq.bits.addr, 3)
connect io.lb_read.offset, _io_lb_read_offset_T_1
node _io_resp_valid_T = and(rpq.io.deq.valid, drain_load)
connect io.resp.valid, _io_resp_valid_T
node _io_resp_bits_data_shifted_T = bits(_T_25, 2, 2)
node _io_resp_bits_data_shifted_T_1 = bits(data_word, 63, 32)
node _io_resp_bits_data_shifted_T_2 = bits(data_word, 31, 0)
node io_resp_bits_data_shifted = mux(_io_resp_bits_data_shifted_T, _io_resp_bits_data_shifted_T_1, _io_resp_bits_data_shifted_T_2)
node io_resp_bits_data_doZero = and(UInt<1>(0h0), UInt<1>(0h0))
node io_resp_bits_data_zeroed = mux(io_resp_bits_data_doZero, UInt<1>(0h0), io_resp_bits_data_shifted)
node _io_resp_bits_data_T = eq(size, UInt<2>(0h2))
node _io_resp_bits_data_T_1 = or(_io_resp_bits_data_T, io_resp_bits_data_doZero)
node _io_resp_bits_data_T_2 = bits(io_resp_bits_data_zeroed, 31, 31)
node _io_resp_bits_data_T_3 = and(rpq.io.deq.bits.uop.mem_signed, _io_resp_bits_data_T_2)
node _io_resp_bits_data_T_4 = mux(_io_resp_bits_data_T_3, UInt<32>(0hffffffff), UInt<32>(0h0))
node _io_resp_bits_data_T_5 = bits(data_word, 63, 32)
node _io_resp_bits_data_T_6 = mux(_io_resp_bits_data_T_1, _io_resp_bits_data_T_4, _io_resp_bits_data_T_5)
node _io_resp_bits_data_T_7 = cat(_io_resp_bits_data_T_6, io_resp_bits_data_zeroed)
node _io_resp_bits_data_shifted_T_3 = bits(_T_25, 1, 1)
node _io_resp_bits_data_shifted_T_4 = bits(_io_resp_bits_data_T_7, 31, 16)
node _io_resp_bits_data_shifted_T_5 = bits(_io_resp_bits_data_T_7, 15, 0)
node io_resp_bits_data_shifted_1 = mux(_io_resp_bits_data_shifted_T_3, _io_resp_bits_data_shifted_T_4, _io_resp_bits_data_shifted_T_5)
node io_resp_bits_data_doZero_1 = and(UInt<1>(0h0), UInt<1>(0h0))
node io_resp_bits_data_zeroed_1 = mux(io_resp_bits_data_doZero_1, UInt<1>(0h0), io_resp_bits_data_shifted_1)
node _io_resp_bits_data_T_8 = eq(size, UInt<1>(0h1))
node _io_resp_bits_data_T_9 = or(_io_resp_bits_data_T_8, io_resp_bits_data_doZero_1)
node _io_resp_bits_data_T_10 = bits(io_resp_bits_data_zeroed_1, 15, 15)
node _io_resp_bits_data_T_11 = and(rpq.io.deq.bits.uop.mem_signed, _io_resp_bits_data_T_10)
node _io_resp_bits_data_T_12 = mux(_io_resp_bits_data_T_11, UInt<48>(0hffffffffffff), UInt<48>(0h0))
node _io_resp_bits_data_T_13 = bits(_io_resp_bits_data_T_7, 63, 16)
node _io_resp_bits_data_T_14 = mux(_io_resp_bits_data_T_9, _io_resp_bits_data_T_12, _io_resp_bits_data_T_13)
node _io_resp_bits_data_T_15 = cat(_io_resp_bits_data_T_14, io_resp_bits_data_zeroed_1)
node _io_resp_bits_data_shifted_T_6 = bits(_T_25, 0, 0)
node _io_resp_bits_data_shifted_T_7 = bits(_io_resp_bits_data_T_15, 15, 8)
node _io_resp_bits_data_shifted_T_8 = bits(_io_resp_bits_data_T_15, 7, 0)
node io_resp_bits_data_shifted_2 = mux(_io_resp_bits_data_shifted_T_6, _io_resp_bits_data_shifted_T_7, _io_resp_bits_data_shifted_T_8)
node io_resp_bits_data_doZero_2 = and(UInt<1>(0h1), UInt<1>(0h0))
node io_resp_bits_data_zeroed_2 = mux(io_resp_bits_data_doZero_2, UInt<1>(0h0), io_resp_bits_data_shifted_2)
node _io_resp_bits_data_T_16 = eq(size, UInt<1>(0h0))
node _io_resp_bits_data_T_17 = or(_io_resp_bits_data_T_16, io_resp_bits_data_doZero_2)
node _io_resp_bits_data_T_18 = bits(io_resp_bits_data_zeroed_2, 7, 7)
node _io_resp_bits_data_T_19 = and(rpq.io.deq.bits.uop.mem_signed, _io_resp_bits_data_T_18)
node _io_resp_bits_data_T_20 = mux(_io_resp_bits_data_T_19, UInt<56>(0hffffffffffffff), UInt<56>(0h0))
node _io_resp_bits_data_T_21 = bits(_io_resp_bits_data_T_15, 63, 8)
node _io_resp_bits_data_T_22 = mux(_io_resp_bits_data_T_17, _io_resp_bits_data_T_20, _io_resp_bits_data_T_21)
node _io_resp_bits_data_T_23 = cat(_io_resp_bits_data_T_22, io_resp_bits_data_zeroed_2)
connect io.resp.bits.data, _io_resp_bits_data_T_23
connect io.resp.bits.is_hella, rpq.io.deq.bits.is_hella
node _T_26 = and(rpq.io.deq.ready, rpq.io.deq.valid)
when _T_26 :
connect commit_line, UInt<1>(0h1)
else :
node _T_27 = eq(commit_line, UInt<1>(0h0))
node _T_28 = and(rpq.io.empty, _T_27)
when _T_28 :
node _T_29 = and(rpq.io.enq.ready, rpq.io.enq.valid)
node _T_30 = eq(_T_29, UInt<1>(0h0))
when _T_30 :
connect state, UInt<5>(0he)
connect finish_to_prefetch, UInt<1>(0h0)
else :
node _T_31 = eq(drain_load, UInt<1>(0h0))
node _T_32 = and(rpq.io.deq.valid, _T_31)
node _T_33 = or(rpq.io.empty, _T_32)
when _T_33 :
connect io.commit_val, UInt<1>(0h1)
connect state, UInt<5>(0h4)
else :
node _T_34 = eq(state, UInt<5>(0h4))
when _T_34 :
node _io_meta_read_valid_T = eq(io.prober_state.valid, UInt<1>(0h0))
node _io_meta_read_valid_T_1 = eq(grantack.valid, UInt<1>(0h0))
node _io_meta_read_valid_T_2 = or(_io_meta_read_valid_T, _io_meta_read_valid_T_1)
node _io_meta_read_valid_T_3 = bits(io.prober_state.bits, 9, 6)
node _io_meta_read_valid_T_4 = neq(_io_meta_read_valid_T_3, req_idx)
node _io_meta_read_valid_T_5 = or(_io_meta_read_valid_T_2, _io_meta_read_valid_T_4)
connect io.meta_read.valid, _io_meta_read_valid_T_5
node _T_35 = and(io.meta_read.ready, io.meta_read.valid)
when _T_35 :
connect state, UInt<5>(0h5)
else :
node _T_36 = eq(state, UInt<5>(0h5))
when _T_36 :
connect state, UInt<5>(0h6)
else :
node _T_37 = eq(state, UInt<5>(0h6))
when _T_37 :
node _needs_wb_r_T = eq(UInt<5>(0h10), UInt<5>(0h10))
node _needs_wb_r_T_1 = mux(_needs_wb_r_T, UInt<2>(0h2), UInt<2>(0h2))
node _needs_wb_r_T_2 = eq(UInt<5>(0h12), UInt<5>(0h10))
node _needs_wb_r_T_3 = mux(_needs_wb_r_T_2, UInt<2>(0h1), _needs_wb_r_T_1)
node _needs_wb_r_T_4 = eq(UInt<5>(0h13), UInt<5>(0h10))
node _needs_wb_r_T_5 = mux(_needs_wb_r_T_4, UInt<2>(0h0), _needs_wb_r_T_3)
node _needs_wb_r_T_6 = cat(_needs_wb_r_T_5, io.meta_resp.bits.coh.state)
node _needs_wb_r_T_7 = cat(UInt<2>(0h0), UInt<2>(0h3))
node _needs_wb_r_T_8 = cat(UInt<2>(0h0), UInt<2>(0h2))
node _needs_wb_r_T_9 = cat(UInt<2>(0h0), UInt<2>(0h1))
node _needs_wb_r_T_10 = cat(UInt<2>(0h0), UInt<2>(0h0))
node _needs_wb_r_T_11 = cat(UInt<2>(0h1), UInt<2>(0h3))
node _needs_wb_r_T_12 = cat(UInt<2>(0h1), UInt<2>(0h2))
node _needs_wb_r_T_13 = cat(UInt<2>(0h1), UInt<2>(0h1))
node _needs_wb_r_T_14 = cat(UInt<2>(0h1), UInt<2>(0h0))
node _needs_wb_r_T_15 = cat(UInt<2>(0h2), UInt<2>(0h3))
node _needs_wb_r_T_16 = cat(UInt<2>(0h2), UInt<2>(0h2))
node _needs_wb_r_T_17 = cat(UInt<2>(0h2), UInt<2>(0h1))
node _needs_wb_r_T_18 = cat(UInt<2>(0h2), UInt<2>(0h0))
node _needs_wb_r_T_19 = eq(_needs_wb_r_T_18, _needs_wb_r_T_6)
node _needs_wb_r_T_20 = mux(_needs_wb_r_T_19, UInt<1>(0h0), UInt<1>(0h0))
node _needs_wb_r_T_21 = mux(_needs_wb_r_T_19, UInt<3>(0h5), UInt<1>(0h0))
node _needs_wb_r_T_22 = mux(_needs_wb_r_T_19, UInt<2>(0h0), UInt<1>(0h0))
node _needs_wb_r_T_23 = eq(_needs_wb_r_T_17, _needs_wb_r_T_6)
node _needs_wb_r_T_24 = mux(_needs_wb_r_T_23, UInt<1>(0h0), _needs_wb_r_T_20)
node _needs_wb_r_T_25 = mux(_needs_wb_r_T_23, UInt<3>(0h2), _needs_wb_r_T_21)
node _needs_wb_r_T_26 = mux(_needs_wb_r_T_23, UInt<2>(0h0), _needs_wb_r_T_22)
node _needs_wb_r_T_27 = eq(_needs_wb_r_T_16, _needs_wb_r_T_6)
node _needs_wb_r_T_28 = mux(_needs_wb_r_T_27, UInt<1>(0h0), _needs_wb_r_T_24)
node _needs_wb_r_T_29 = mux(_needs_wb_r_T_27, UInt<3>(0h1), _needs_wb_r_T_25)
node _needs_wb_r_T_30 = mux(_needs_wb_r_T_27, UInt<2>(0h0), _needs_wb_r_T_26)
node _needs_wb_r_T_31 = eq(_needs_wb_r_T_15, _needs_wb_r_T_6)
node _needs_wb_r_T_32 = mux(_needs_wb_r_T_31, UInt<1>(0h1), _needs_wb_r_T_28)
node _needs_wb_r_T_33 = mux(_needs_wb_r_T_31, UInt<3>(0h1), _needs_wb_r_T_29)
node _needs_wb_r_T_34 = mux(_needs_wb_r_T_31, UInt<2>(0h0), _needs_wb_r_T_30)
node _needs_wb_r_T_35 = eq(_needs_wb_r_T_14, _needs_wb_r_T_6)
node _needs_wb_r_T_36 = mux(_needs_wb_r_T_35, UInt<1>(0h0), _needs_wb_r_T_32)
node _needs_wb_r_T_37 = mux(_needs_wb_r_T_35, UInt<3>(0h5), _needs_wb_r_T_33)
node _needs_wb_r_T_38 = mux(_needs_wb_r_T_35, UInt<2>(0h0), _needs_wb_r_T_34)
node _needs_wb_r_T_39 = eq(_needs_wb_r_T_13, _needs_wb_r_T_6)
node _needs_wb_r_T_40 = mux(_needs_wb_r_T_39, UInt<1>(0h0), _needs_wb_r_T_36)
node _needs_wb_r_T_41 = mux(_needs_wb_r_T_39, UInt<3>(0h4), _needs_wb_r_T_37)
node _needs_wb_r_T_42 = mux(_needs_wb_r_T_39, UInt<2>(0h1), _needs_wb_r_T_38)
node _needs_wb_r_T_43 = eq(_needs_wb_r_T_12, _needs_wb_r_T_6)
node _needs_wb_r_T_44 = mux(_needs_wb_r_T_43, UInt<1>(0h0), _needs_wb_r_T_40)
node _needs_wb_r_T_45 = mux(_needs_wb_r_T_43, UInt<3>(0h0), _needs_wb_r_T_41)
node _needs_wb_r_T_46 = mux(_needs_wb_r_T_43, UInt<2>(0h1), _needs_wb_r_T_42)
node _needs_wb_r_T_47 = eq(_needs_wb_r_T_11, _needs_wb_r_T_6)
node _needs_wb_r_T_48 = mux(_needs_wb_r_T_47, UInt<1>(0h1), _needs_wb_r_T_44)
node _needs_wb_r_T_49 = mux(_needs_wb_r_T_47, UInt<3>(0h0), _needs_wb_r_T_45)
node _needs_wb_r_T_50 = mux(_needs_wb_r_T_47, UInt<2>(0h1), _needs_wb_r_T_46)
node _needs_wb_r_T_51 = eq(_needs_wb_r_T_10, _needs_wb_r_T_6)
node _needs_wb_r_T_52 = mux(_needs_wb_r_T_51, UInt<1>(0h0), _needs_wb_r_T_48)
node _needs_wb_r_T_53 = mux(_needs_wb_r_T_51, UInt<3>(0h5), _needs_wb_r_T_49)
node _needs_wb_r_T_54 = mux(_needs_wb_r_T_51, UInt<2>(0h0), _needs_wb_r_T_50)
node _needs_wb_r_T_55 = eq(_needs_wb_r_T_9, _needs_wb_r_T_6)
node _needs_wb_r_T_56 = mux(_needs_wb_r_T_55, UInt<1>(0h0), _needs_wb_r_T_52)
node _needs_wb_r_T_57 = mux(_needs_wb_r_T_55, UInt<3>(0h4), _needs_wb_r_T_53)
node _needs_wb_r_T_58 = mux(_needs_wb_r_T_55, UInt<2>(0h1), _needs_wb_r_T_54)
node _needs_wb_r_T_59 = eq(_needs_wb_r_T_8, _needs_wb_r_T_6)
node _needs_wb_r_T_60 = mux(_needs_wb_r_T_59, UInt<1>(0h0), _needs_wb_r_T_56)
node _needs_wb_r_T_61 = mux(_needs_wb_r_T_59, UInt<3>(0h3), _needs_wb_r_T_57)
node _needs_wb_r_T_62 = mux(_needs_wb_r_T_59, UInt<2>(0h2), _needs_wb_r_T_58)
node _needs_wb_r_T_63 = eq(_needs_wb_r_T_7, _needs_wb_r_T_6)
node needs_wb = mux(_needs_wb_r_T_63, UInt<1>(0h1), _needs_wb_r_T_60)
node needs_wb_r_2 = mux(_needs_wb_r_T_63, UInt<3>(0h3), _needs_wb_r_T_61)
node needs_wb_r_3 = mux(_needs_wb_r_T_63, UInt<2>(0h2), _needs_wb_r_T_62)
wire needs_wb_meta : { state : UInt<2>}
connect needs_wb_meta.state, needs_wb_r_3
node _state_T_30 = eq(io.meta_resp.valid, UInt<1>(0h0))
node _state_T_31 = mux(needs_wb, UInt<5>(0h7), UInt<5>(0hb))
node _state_T_32 = mux(_state_T_30, UInt<5>(0h4), _state_T_31)
connect state, _state_T_32
else :
node _T_38 = eq(state, UInt<5>(0h7))
when _T_38 :
connect io.meta_write.valid, UInt<1>(0h1)
node _T_39 = and(io.meta_write.ready, io.meta_write.valid)
when _T_39 :
connect state, UInt<5>(0h9)
else :
node _T_40 = eq(state, UInt<5>(0h9))
when _T_40 :
connect io.wb_req.valid, UInt<1>(0h1)
node _T_41 = and(io.wb_req.ready, io.wb_req.valid)
when _T_41 :
connect state, UInt<5>(0ha)
else :
node _T_42 = eq(state, UInt<5>(0ha))
when _T_42 :
when io.wb_resp :
connect state, UInt<5>(0hb)
else :
node _T_43 = eq(state, UInt<5>(0hb))
when _T_43 :
connect io.lb_read.offset, refill_ctr
connect io.refill.valid, UInt<1>(0h1)
node _T_44 = and(io.refill.ready, io.refill.valid)
when _T_44 :
node _refill_ctr_T = add(refill_ctr, UInt<1>(0h1))
node _refill_ctr_T_1 = tail(_refill_ctr_T, 1)
connect refill_ctr, _refill_ctr_T_1
node _T_45 = eq(refill_ctr, UInt<3>(0h7))
when _T_45 :
connect state, UInt<5>(0hc)
else :
node _T_46 = eq(state, UInt<5>(0hc))
when _T_46 :
connect io.replay.bits, rpq.io.deq.bits
connect io.replay.valid, rpq.io.deq.valid
connect rpq.io.deq.ready, io.replay.ready
connect io.replay.bits.way_en, req.way_en
node _io_replay_bits_addr_T = bits(rpq.io.deq.bits.addr, 5, 0)
node io_replay_bits_addr_hi = cat(req_tag, req_idx)
node _io_replay_bits_addr_T_1 = cat(io_replay_bits_addr_hi, _io_replay_bits_addr_T)
connect io.replay.bits.addr, _io_replay_bits_addr_T_1
node _T_47 = and(io.replay.ready, io.replay.valid)
node _T_48 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1))
node _T_49 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11))
node _T_50 = or(_T_48, _T_49)
node _T_51 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7))
node _T_52 = or(_T_50, _T_51)
node _T_53 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4))
node _T_54 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9))
node _T_55 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha))
node _T_56 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb))
node _T_57 = or(_T_53, _T_54)
node _T_58 = or(_T_57, _T_55)
node _T_59 = or(_T_58, _T_56)
node _T_60 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8))
node _T_61 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc))
node _T_62 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd))
node _T_63 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he))
node _T_64 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf))
node _T_65 = or(_T_60, _T_61)
node _T_66 = or(_T_65, _T_62)
node _T_67 = or(_T_66, _T_63)
node _T_68 = or(_T_67, _T_64)
node _T_69 = or(_T_59, _T_68)
node _T_70 = or(_T_52, _T_69)
node _T_71 = and(_T_47, _T_70)
when _T_71 :
node _r_c_cat_T = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1))
node _r_c_cat_T_1 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11))
node _r_c_cat_T_2 = or(_r_c_cat_T, _r_c_cat_T_1)
node _r_c_cat_T_3 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7))
node _r_c_cat_T_4 = or(_r_c_cat_T_2, _r_c_cat_T_3)
node _r_c_cat_T_5 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4))
node _r_c_cat_T_6 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9))
node _r_c_cat_T_7 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha))
node _r_c_cat_T_8 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb))
node _r_c_cat_T_9 = or(_r_c_cat_T_5, _r_c_cat_T_6)
node _r_c_cat_T_10 = or(_r_c_cat_T_9, _r_c_cat_T_7)
node _r_c_cat_T_11 = or(_r_c_cat_T_10, _r_c_cat_T_8)
node _r_c_cat_T_12 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8))
node _r_c_cat_T_13 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc))
node _r_c_cat_T_14 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd))
node _r_c_cat_T_15 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he))
node _r_c_cat_T_16 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf))
node _r_c_cat_T_17 = or(_r_c_cat_T_12, _r_c_cat_T_13)
node _r_c_cat_T_18 = or(_r_c_cat_T_17, _r_c_cat_T_14)
node _r_c_cat_T_19 = or(_r_c_cat_T_18, _r_c_cat_T_15)
node _r_c_cat_T_20 = or(_r_c_cat_T_19, _r_c_cat_T_16)
node _r_c_cat_T_21 = or(_r_c_cat_T_11, _r_c_cat_T_20)
node _r_c_cat_T_22 = or(_r_c_cat_T_4, _r_c_cat_T_21)
node _r_c_cat_T_23 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1))
node _r_c_cat_T_24 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11))
node _r_c_cat_T_25 = or(_r_c_cat_T_23, _r_c_cat_T_24)
node _r_c_cat_T_26 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7))
node _r_c_cat_T_27 = or(_r_c_cat_T_25, _r_c_cat_T_26)
node _r_c_cat_T_28 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4))
node _r_c_cat_T_29 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9))
node _r_c_cat_T_30 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha))
node _r_c_cat_T_31 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb))
node _r_c_cat_T_32 = or(_r_c_cat_T_28, _r_c_cat_T_29)
node _r_c_cat_T_33 = or(_r_c_cat_T_32, _r_c_cat_T_30)
node _r_c_cat_T_34 = or(_r_c_cat_T_33, _r_c_cat_T_31)
node _r_c_cat_T_35 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8))
node _r_c_cat_T_36 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc))
node _r_c_cat_T_37 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd))
node _r_c_cat_T_38 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he))
node _r_c_cat_T_39 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf))
node _r_c_cat_T_40 = or(_r_c_cat_T_35, _r_c_cat_T_36)
node _r_c_cat_T_41 = or(_r_c_cat_T_40, _r_c_cat_T_37)
node _r_c_cat_T_42 = or(_r_c_cat_T_41, _r_c_cat_T_38)
node _r_c_cat_T_43 = or(_r_c_cat_T_42, _r_c_cat_T_39)
node _r_c_cat_T_44 = or(_r_c_cat_T_34, _r_c_cat_T_43)
node _r_c_cat_T_45 = or(_r_c_cat_T_27, _r_c_cat_T_44)
node _r_c_cat_T_46 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<2>(0h3))
node _r_c_cat_T_47 = or(_r_c_cat_T_45, _r_c_cat_T_46)
node _r_c_cat_T_48 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h6))
node _r_c_cat_T_49 = or(_r_c_cat_T_47, _r_c_cat_T_48)
node r_c = cat(_r_c_cat_T_22, _r_c_cat_T_49)
node _r_T_64 = cat(r_c, new_coh.state)
node _r_T_65 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_66 = cat(_r_T_65, UInt<2>(0h3))
node _r_T_67 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_68 = cat(_r_T_67, UInt<2>(0h2))
node _r_T_69 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_70 = cat(_r_T_69, UInt<2>(0h1))
node _r_T_71 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_72 = cat(_r_T_71, UInt<2>(0h3))
node _r_T_73 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_74 = cat(_r_T_73, UInt<2>(0h2))
node _r_T_75 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_76 = cat(_r_T_75, UInt<2>(0h3))
node _r_T_77 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_78 = cat(_r_T_77, UInt<2>(0h2))
node _r_T_79 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_80 = cat(_r_T_79, UInt<2>(0h0))
node _r_T_81 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_82 = cat(_r_T_81, UInt<2>(0h1))
node _r_T_83 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_84 = cat(_r_T_83, UInt<2>(0h0))
node _r_T_85 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_86 = cat(_r_T_85, UInt<2>(0h1))
node _r_T_87 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_88 = cat(_r_T_87, UInt<2>(0h0))
node _r_T_89 = eq(_r_T_88, _r_T_64)
node _r_T_90 = mux(_r_T_89, UInt<1>(0h0), UInt<1>(0h0))
node _r_T_91 = mux(_r_T_89, UInt<2>(0h1), UInt<1>(0h0))
node _r_T_92 = eq(_r_T_86, _r_T_64)
node _r_T_93 = mux(_r_T_92, UInt<1>(0h0), _r_T_90)
node _r_T_94 = mux(_r_T_92, UInt<2>(0h2), _r_T_91)
node _r_T_95 = eq(_r_T_84, _r_T_64)
node _r_T_96 = mux(_r_T_95, UInt<1>(0h0), _r_T_93)
node _r_T_97 = mux(_r_T_95, UInt<2>(0h1), _r_T_94)
node _r_T_98 = eq(_r_T_82, _r_T_64)
node _r_T_99 = mux(_r_T_98, UInt<1>(0h0), _r_T_96)
node _r_T_100 = mux(_r_T_98, UInt<2>(0h2), _r_T_97)
node _r_T_101 = eq(_r_T_80, _r_T_64)
node _r_T_102 = mux(_r_T_101, UInt<1>(0h0), _r_T_99)
node _r_T_103 = mux(_r_T_101, UInt<2>(0h0), _r_T_100)
node _r_T_104 = eq(_r_T_78, _r_T_64)
node _r_T_105 = mux(_r_T_104, UInt<1>(0h1), _r_T_102)
node _r_T_106 = mux(_r_T_104, UInt<2>(0h3), _r_T_103)
node _r_T_107 = eq(_r_T_76, _r_T_64)
node _r_T_108 = mux(_r_T_107, UInt<1>(0h1), _r_T_105)
node _r_T_109 = mux(_r_T_107, UInt<2>(0h3), _r_T_106)
node _r_T_110 = eq(_r_T_74, _r_T_64)
node _r_T_111 = mux(_r_T_110, UInt<1>(0h1), _r_T_108)
node _r_T_112 = mux(_r_T_110, UInt<2>(0h2), _r_T_109)
node _r_T_113 = eq(_r_T_72, _r_T_64)
node _r_T_114 = mux(_r_T_113, UInt<1>(0h1), _r_T_111)
node _r_T_115 = mux(_r_T_113, UInt<2>(0h3), _r_T_112)
node _r_T_116 = eq(_r_T_70, _r_T_64)
node _r_T_117 = mux(_r_T_116, UInt<1>(0h1), _r_T_114)
node _r_T_118 = mux(_r_T_116, UInt<2>(0h1), _r_T_115)
node _r_T_119 = eq(_r_T_68, _r_T_64)
node _r_T_120 = mux(_r_T_119, UInt<1>(0h1), _r_T_117)
node _r_T_121 = mux(_r_T_119, UInt<2>(0h2), _r_T_118)
node _r_T_122 = eq(_r_T_66, _r_T_64)
node is_hit = mux(_r_T_122, UInt<1>(0h1), _r_T_120)
node r_2_1 = mux(_r_T_122, UInt<2>(0h3), _r_T_121)
wire coh_on_hit : { state : UInt<2>}
connect coh_on_hit.state, r_2_1
node _T_72 = asUInt(reset)
node _T_73 = eq(_T_72, UInt<1>(0h0))
when _T_73 :
node _T_74 = eq(is_hit, UInt<1>(0h0))
when _T_74 :
printf(clock, UInt<1>(0h1), "Assertion failed: We still don't have permissions for this store\n at mshrs.scala:345 assert(is_hit, \"We still don't have permissions for this store\")\n") : printf_2
assert(clock, is_hit, UInt<1>(0h1), "") : assert_2
connect new_coh, coh_on_hit
node _T_75 = eq(rpq.io.enq.valid, UInt<1>(0h0))
node _T_76 = and(rpq.io.empty, _T_75)
when _T_76 :
connect state, UInt<5>(0hd)
else :
node _T_77 = eq(state, UInt<5>(0hd))
when _T_77 :
connect io.meta_write.valid, UInt<1>(0h1)
connect io.meta_write.bits.idx, req_idx
connect io.meta_write.bits.data.coh, new_coh
connect io.meta_write.bits.data.tag, req_tag
connect io.meta_write.bits.way_en, req.way_en
node _T_78 = and(io.meta_write.ready, io.meta_write.valid)
when _T_78 :
connect state, UInt<5>(0he)
connect finish_to_prefetch, UInt<1>(0h0)
else :
node _T_79 = eq(state, UInt<5>(0he))
when _T_79 :
connect io.mem_finish.valid, grantack.valid
node _T_80 = and(io.mem_finish.ready, io.mem_finish.valid)
node _T_81 = eq(grantack.valid, UInt<1>(0h0))
node _T_82 = or(_T_80, _T_81)
when _T_82 :
connect grantack.valid, UInt<1>(0h0)
connect state, UInt<5>(0hf)
else :
node _T_83 = eq(state, UInt<5>(0hf))
when _T_83 :
node _state_T_33 = mux(finish_to_prefetch, UInt<5>(0h11), UInt<5>(0h0))
connect state, _state_T_33
else :
node _T_84 = eq(state, UInt<5>(0h11))
when _T_84 :
connect io.req_pri_rdy, UInt<1>(0h1)
node _T_85 = eq(io.req_sec_rdy, UInt<1>(0h0))
node _T_86 = and(io.req_sec_val, _T_85)
node _T_87 = or(_T_86, io.clear_prefetch)
when _T_87 :
connect state, UInt<5>(0h0)
else :
node _T_88 = and(io.req_sec_val, io.req_sec_rdy)
when _T_88 :
node _r_c_cat_T_50 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _r_c_cat_T_51 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _r_c_cat_T_52 = or(_r_c_cat_T_50, _r_c_cat_T_51)
node _r_c_cat_T_53 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _r_c_cat_T_54 = or(_r_c_cat_T_52, _r_c_cat_T_53)
node _r_c_cat_T_55 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _r_c_cat_T_56 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _r_c_cat_T_57 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _r_c_cat_T_58 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _r_c_cat_T_59 = or(_r_c_cat_T_55, _r_c_cat_T_56)
node _r_c_cat_T_60 = or(_r_c_cat_T_59, _r_c_cat_T_57)
node _r_c_cat_T_61 = or(_r_c_cat_T_60, _r_c_cat_T_58)
node _r_c_cat_T_62 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _r_c_cat_T_63 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _r_c_cat_T_64 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _r_c_cat_T_65 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _r_c_cat_T_66 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _r_c_cat_T_67 = or(_r_c_cat_T_62, _r_c_cat_T_63)
node _r_c_cat_T_68 = or(_r_c_cat_T_67, _r_c_cat_T_64)
node _r_c_cat_T_69 = or(_r_c_cat_T_68, _r_c_cat_T_65)
node _r_c_cat_T_70 = or(_r_c_cat_T_69, _r_c_cat_T_66)
node _r_c_cat_T_71 = or(_r_c_cat_T_61, _r_c_cat_T_70)
node _r_c_cat_T_72 = or(_r_c_cat_T_54, _r_c_cat_T_71)
node _r_c_cat_T_73 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _r_c_cat_T_74 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _r_c_cat_T_75 = or(_r_c_cat_T_73, _r_c_cat_T_74)
node _r_c_cat_T_76 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _r_c_cat_T_77 = or(_r_c_cat_T_75, _r_c_cat_T_76)
node _r_c_cat_T_78 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _r_c_cat_T_79 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _r_c_cat_T_80 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _r_c_cat_T_81 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _r_c_cat_T_82 = or(_r_c_cat_T_78, _r_c_cat_T_79)
node _r_c_cat_T_83 = or(_r_c_cat_T_82, _r_c_cat_T_80)
node _r_c_cat_T_84 = or(_r_c_cat_T_83, _r_c_cat_T_81)
node _r_c_cat_T_85 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _r_c_cat_T_86 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _r_c_cat_T_87 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _r_c_cat_T_88 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _r_c_cat_T_89 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _r_c_cat_T_90 = or(_r_c_cat_T_85, _r_c_cat_T_86)
node _r_c_cat_T_91 = or(_r_c_cat_T_90, _r_c_cat_T_87)
node _r_c_cat_T_92 = or(_r_c_cat_T_91, _r_c_cat_T_88)
node _r_c_cat_T_93 = or(_r_c_cat_T_92, _r_c_cat_T_89)
node _r_c_cat_T_94 = or(_r_c_cat_T_84, _r_c_cat_T_93)
node _r_c_cat_T_95 = or(_r_c_cat_T_77, _r_c_cat_T_94)
node _r_c_cat_T_96 = eq(io.req.uop.mem_cmd, UInt<2>(0h3))
node _r_c_cat_T_97 = or(_r_c_cat_T_95, _r_c_cat_T_96)
node _r_c_cat_T_98 = eq(io.req.uop.mem_cmd, UInt<3>(0h6))
node _r_c_cat_T_99 = or(_r_c_cat_T_97, _r_c_cat_T_98)
node r_c_1 = cat(_r_c_cat_T_72, _r_c_cat_T_99)
node _r_T_123 = cat(r_c_1, new_coh.state)
node _r_T_124 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_125 = cat(_r_T_124, UInt<2>(0h3))
node _r_T_126 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_127 = cat(_r_T_126, UInt<2>(0h2))
node _r_T_128 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_129 = cat(_r_T_128, UInt<2>(0h1))
node _r_T_130 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_131 = cat(_r_T_130, UInt<2>(0h3))
node _r_T_132 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_133 = cat(_r_T_132, UInt<2>(0h2))
node _r_T_134 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_135 = cat(_r_T_134, UInt<2>(0h3))
node _r_T_136 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_137 = cat(_r_T_136, UInt<2>(0h2))
node _r_T_138 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_139 = cat(_r_T_138, UInt<2>(0h0))
node _r_T_140 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_141 = cat(_r_T_140, UInt<2>(0h1))
node _r_T_142 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_143 = cat(_r_T_142, UInt<2>(0h0))
node _r_T_144 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_145 = cat(_r_T_144, UInt<2>(0h1))
node _r_T_146 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_147 = cat(_r_T_146, UInt<2>(0h0))
node _r_T_148 = eq(_r_T_147, _r_T_123)
node _r_T_149 = mux(_r_T_148, UInt<1>(0h0), UInt<1>(0h0))
node _r_T_150 = mux(_r_T_148, UInt<2>(0h1), UInt<1>(0h0))
node _r_T_151 = eq(_r_T_145, _r_T_123)
node _r_T_152 = mux(_r_T_151, UInt<1>(0h0), _r_T_149)
node _r_T_153 = mux(_r_T_151, UInt<2>(0h2), _r_T_150)
node _r_T_154 = eq(_r_T_143, _r_T_123)
node _r_T_155 = mux(_r_T_154, UInt<1>(0h0), _r_T_152)
node _r_T_156 = mux(_r_T_154, UInt<2>(0h1), _r_T_153)
node _r_T_157 = eq(_r_T_141, _r_T_123)
node _r_T_158 = mux(_r_T_157, UInt<1>(0h0), _r_T_155)
node _r_T_159 = mux(_r_T_157, UInt<2>(0h2), _r_T_156)
node _r_T_160 = eq(_r_T_139, _r_T_123)
node _r_T_161 = mux(_r_T_160, UInt<1>(0h0), _r_T_158)
node _r_T_162 = mux(_r_T_160, UInt<2>(0h0), _r_T_159)
node _r_T_163 = eq(_r_T_137, _r_T_123)
node _r_T_164 = mux(_r_T_163, UInt<1>(0h1), _r_T_161)
node _r_T_165 = mux(_r_T_163, UInt<2>(0h3), _r_T_162)
node _r_T_166 = eq(_r_T_135, _r_T_123)
node _r_T_167 = mux(_r_T_166, UInt<1>(0h1), _r_T_164)
node _r_T_168 = mux(_r_T_166, UInt<2>(0h3), _r_T_165)
node _r_T_169 = eq(_r_T_133, _r_T_123)
node _r_T_170 = mux(_r_T_169, UInt<1>(0h1), _r_T_167)
node _r_T_171 = mux(_r_T_169, UInt<2>(0h2), _r_T_168)
node _r_T_172 = eq(_r_T_131, _r_T_123)
node _r_T_173 = mux(_r_T_172, UInt<1>(0h1), _r_T_170)
node _r_T_174 = mux(_r_T_172, UInt<2>(0h3), _r_T_171)
node _r_T_175 = eq(_r_T_129, _r_T_123)
node _r_T_176 = mux(_r_T_175, UInt<1>(0h1), _r_T_173)
node _r_T_177 = mux(_r_T_175, UInt<2>(0h1), _r_T_174)
node _r_T_178 = eq(_r_T_127, _r_T_123)
node _r_T_179 = mux(_r_T_178, UInt<1>(0h1), _r_T_176)
node _r_T_180 = mux(_r_T_178, UInt<2>(0h2), _r_T_177)
node _r_T_181 = eq(_r_T_125, _r_T_123)
node is_hit_1 = mux(_r_T_181, UInt<1>(0h1), _r_T_179)
node r_2_2 = mux(_r_T_181, UInt<2>(0h3), _r_T_180)
wire coh_on_hit_1 : { state : UInt<2>}
connect coh_on_hit_1.state, r_2_2
when is_hit_1 :
connect new_coh, coh_on_hit_1
connect state, UInt<5>(0h4)
else :
wire new_coh_meta_1 : { state : UInt<2>}
connect new_coh_meta_1.state, UInt<2>(0h0)
connect new_coh, new_coh_meta_1
connect state, UInt<5>(0h1)
else :
node _T_89 = and(io.req_pri_val, io.req_pri_rdy)
when _T_89 :
connect grant_had_data, UInt<1>(0h0)
wire state_new_state_1 : UInt
connect state_new_state_1, state
connect grantack.valid, UInt<1>(0h0)
connect refill_ctr, UInt<1>(0h0)
node _state_T_34 = asUInt(reset)
node _state_T_35 = eq(_state_T_34, UInt<1>(0h0))
when _state_T_35 :
node _state_T_36 = eq(rpq.io.enq.ready, UInt<1>(0h0))
when _state_T_36 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:213 assert(rpq.io.enq.ready)\n") : state_printf_2
assert(clock, rpq.io.enq.ready, UInt<1>(0h1), "") : state_assert_2
connect req, io.req
node _state_req_needs_wb_r_T_64 = eq(UInt<5>(0h10), UInt<5>(0h10))
node _state_req_needs_wb_r_T_65 = mux(_state_req_needs_wb_r_T_64, UInt<2>(0h2), UInt<2>(0h2))
node _state_req_needs_wb_r_T_66 = eq(UInt<5>(0h12), UInt<5>(0h10))
node _state_req_needs_wb_r_T_67 = mux(_state_req_needs_wb_r_T_66, UInt<2>(0h1), _state_req_needs_wb_r_T_65)
node _state_req_needs_wb_r_T_68 = eq(UInt<5>(0h13), UInt<5>(0h10))
node _state_req_needs_wb_r_T_69 = mux(_state_req_needs_wb_r_T_68, UInt<2>(0h0), _state_req_needs_wb_r_T_67)
node _state_req_needs_wb_r_T_70 = cat(_state_req_needs_wb_r_T_69, io.req.old_meta.coh.state)
node _state_req_needs_wb_r_T_71 = cat(UInt<2>(0h0), UInt<2>(0h3))
node _state_req_needs_wb_r_T_72 = cat(UInt<2>(0h0), UInt<2>(0h2))
node _state_req_needs_wb_r_T_73 = cat(UInt<2>(0h0), UInt<2>(0h1))
node _state_req_needs_wb_r_T_74 = cat(UInt<2>(0h0), UInt<2>(0h0))
node _state_req_needs_wb_r_T_75 = cat(UInt<2>(0h1), UInt<2>(0h3))
node _state_req_needs_wb_r_T_76 = cat(UInt<2>(0h1), UInt<2>(0h2))
node _state_req_needs_wb_r_T_77 = cat(UInt<2>(0h1), UInt<2>(0h1))
node _state_req_needs_wb_r_T_78 = cat(UInt<2>(0h1), UInt<2>(0h0))
node _state_req_needs_wb_r_T_79 = cat(UInt<2>(0h2), UInt<2>(0h3))
node _state_req_needs_wb_r_T_80 = cat(UInt<2>(0h2), UInt<2>(0h2))
node _state_req_needs_wb_r_T_81 = cat(UInt<2>(0h2), UInt<2>(0h1))
node _state_req_needs_wb_r_T_82 = cat(UInt<2>(0h2), UInt<2>(0h0))
node _state_req_needs_wb_r_T_83 = eq(_state_req_needs_wb_r_T_82, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_84 = mux(_state_req_needs_wb_r_T_83, UInt<1>(0h0), UInt<1>(0h0))
node _state_req_needs_wb_r_T_85 = mux(_state_req_needs_wb_r_T_83, UInt<3>(0h5), UInt<1>(0h0))
node _state_req_needs_wb_r_T_86 = mux(_state_req_needs_wb_r_T_83, UInt<2>(0h0), UInt<1>(0h0))
node _state_req_needs_wb_r_T_87 = eq(_state_req_needs_wb_r_T_81, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_88 = mux(_state_req_needs_wb_r_T_87, UInt<1>(0h0), _state_req_needs_wb_r_T_84)
node _state_req_needs_wb_r_T_89 = mux(_state_req_needs_wb_r_T_87, UInt<3>(0h2), _state_req_needs_wb_r_T_85)
node _state_req_needs_wb_r_T_90 = mux(_state_req_needs_wb_r_T_87, UInt<2>(0h0), _state_req_needs_wb_r_T_86)
node _state_req_needs_wb_r_T_91 = eq(_state_req_needs_wb_r_T_80, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_92 = mux(_state_req_needs_wb_r_T_91, UInt<1>(0h0), _state_req_needs_wb_r_T_88)
node _state_req_needs_wb_r_T_93 = mux(_state_req_needs_wb_r_T_91, UInt<3>(0h1), _state_req_needs_wb_r_T_89)
node _state_req_needs_wb_r_T_94 = mux(_state_req_needs_wb_r_T_91, UInt<2>(0h0), _state_req_needs_wb_r_T_90)
node _state_req_needs_wb_r_T_95 = eq(_state_req_needs_wb_r_T_79, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_96 = mux(_state_req_needs_wb_r_T_95, UInt<1>(0h1), _state_req_needs_wb_r_T_92)
node _state_req_needs_wb_r_T_97 = mux(_state_req_needs_wb_r_T_95, UInt<3>(0h1), _state_req_needs_wb_r_T_93)
node _state_req_needs_wb_r_T_98 = mux(_state_req_needs_wb_r_T_95, UInt<2>(0h0), _state_req_needs_wb_r_T_94)
node _state_req_needs_wb_r_T_99 = eq(_state_req_needs_wb_r_T_78, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_100 = mux(_state_req_needs_wb_r_T_99, UInt<1>(0h0), _state_req_needs_wb_r_T_96)
node _state_req_needs_wb_r_T_101 = mux(_state_req_needs_wb_r_T_99, UInt<3>(0h5), _state_req_needs_wb_r_T_97)
node _state_req_needs_wb_r_T_102 = mux(_state_req_needs_wb_r_T_99, UInt<2>(0h0), _state_req_needs_wb_r_T_98)
node _state_req_needs_wb_r_T_103 = eq(_state_req_needs_wb_r_T_77, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_104 = mux(_state_req_needs_wb_r_T_103, UInt<1>(0h0), _state_req_needs_wb_r_T_100)
node _state_req_needs_wb_r_T_105 = mux(_state_req_needs_wb_r_T_103, UInt<3>(0h4), _state_req_needs_wb_r_T_101)
node _state_req_needs_wb_r_T_106 = mux(_state_req_needs_wb_r_T_103, UInt<2>(0h1), _state_req_needs_wb_r_T_102)
node _state_req_needs_wb_r_T_107 = eq(_state_req_needs_wb_r_T_76, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_108 = mux(_state_req_needs_wb_r_T_107, UInt<1>(0h0), _state_req_needs_wb_r_T_104)
node _state_req_needs_wb_r_T_109 = mux(_state_req_needs_wb_r_T_107, UInt<3>(0h0), _state_req_needs_wb_r_T_105)
node _state_req_needs_wb_r_T_110 = mux(_state_req_needs_wb_r_T_107, UInt<2>(0h1), _state_req_needs_wb_r_T_106)
node _state_req_needs_wb_r_T_111 = eq(_state_req_needs_wb_r_T_75, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_112 = mux(_state_req_needs_wb_r_T_111, UInt<1>(0h1), _state_req_needs_wb_r_T_108)
node _state_req_needs_wb_r_T_113 = mux(_state_req_needs_wb_r_T_111, UInt<3>(0h0), _state_req_needs_wb_r_T_109)
node _state_req_needs_wb_r_T_114 = mux(_state_req_needs_wb_r_T_111, UInt<2>(0h1), _state_req_needs_wb_r_T_110)
node _state_req_needs_wb_r_T_115 = eq(_state_req_needs_wb_r_T_74, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_116 = mux(_state_req_needs_wb_r_T_115, UInt<1>(0h0), _state_req_needs_wb_r_T_112)
node _state_req_needs_wb_r_T_117 = mux(_state_req_needs_wb_r_T_115, UInt<3>(0h5), _state_req_needs_wb_r_T_113)
node _state_req_needs_wb_r_T_118 = mux(_state_req_needs_wb_r_T_115, UInt<2>(0h0), _state_req_needs_wb_r_T_114)
node _state_req_needs_wb_r_T_119 = eq(_state_req_needs_wb_r_T_73, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_120 = mux(_state_req_needs_wb_r_T_119, UInt<1>(0h0), _state_req_needs_wb_r_T_116)
node _state_req_needs_wb_r_T_121 = mux(_state_req_needs_wb_r_T_119, UInt<3>(0h4), _state_req_needs_wb_r_T_117)
node _state_req_needs_wb_r_T_122 = mux(_state_req_needs_wb_r_T_119, UInt<2>(0h1), _state_req_needs_wb_r_T_118)
node _state_req_needs_wb_r_T_123 = eq(_state_req_needs_wb_r_T_72, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_124 = mux(_state_req_needs_wb_r_T_123, UInt<1>(0h0), _state_req_needs_wb_r_T_120)
node _state_req_needs_wb_r_T_125 = mux(_state_req_needs_wb_r_T_123, UInt<3>(0h3), _state_req_needs_wb_r_T_121)
node _state_req_needs_wb_r_T_126 = mux(_state_req_needs_wb_r_T_123, UInt<2>(0h2), _state_req_needs_wb_r_T_122)
node _state_req_needs_wb_r_T_127 = eq(_state_req_needs_wb_r_T_71, _state_req_needs_wb_r_T_70)
node state_req_needs_wb_r_1_1 = mux(_state_req_needs_wb_r_T_127, UInt<1>(0h1), _state_req_needs_wb_r_T_124)
node state_req_needs_wb_r_2_1 = mux(_state_req_needs_wb_r_T_127, UInt<3>(0h3), _state_req_needs_wb_r_T_125)
node state_req_needs_wb_r_3_1 = mux(_state_req_needs_wb_r_T_127, UInt<2>(0h2), _state_req_needs_wb_r_T_126)
wire state_req_needs_wb_meta_1 : { state : UInt<2>}
connect state_req_needs_wb_meta_1.state, state_req_needs_wb_r_3_1
connect req_needs_wb, state_req_needs_wb_r_1_1
when io.req.tag_match :
node _state_r_c_cat_T_50 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _state_r_c_cat_T_51 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _state_r_c_cat_T_52 = or(_state_r_c_cat_T_50, _state_r_c_cat_T_51)
node _state_r_c_cat_T_53 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _state_r_c_cat_T_54 = or(_state_r_c_cat_T_52, _state_r_c_cat_T_53)
node _state_r_c_cat_T_55 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _state_r_c_cat_T_56 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _state_r_c_cat_T_57 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _state_r_c_cat_T_58 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _state_r_c_cat_T_59 = or(_state_r_c_cat_T_55, _state_r_c_cat_T_56)
node _state_r_c_cat_T_60 = or(_state_r_c_cat_T_59, _state_r_c_cat_T_57)
node _state_r_c_cat_T_61 = or(_state_r_c_cat_T_60, _state_r_c_cat_T_58)
node _state_r_c_cat_T_62 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _state_r_c_cat_T_63 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _state_r_c_cat_T_64 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _state_r_c_cat_T_65 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _state_r_c_cat_T_66 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _state_r_c_cat_T_67 = or(_state_r_c_cat_T_62, _state_r_c_cat_T_63)
node _state_r_c_cat_T_68 = or(_state_r_c_cat_T_67, _state_r_c_cat_T_64)
node _state_r_c_cat_T_69 = or(_state_r_c_cat_T_68, _state_r_c_cat_T_65)
node _state_r_c_cat_T_70 = or(_state_r_c_cat_T_69, _state_r_c_cat_T_66)
node _state_r_c_cat_T_71 = or(_state_r_c_cat_T_61, _state_r_c_cat_T_70)
node _state_r_c_cat_T_72 = or(_state_r_c_cat_T_54, _state_r_c_cat_T_71)
node _state_r_c_cat_T_73 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _state_r_c_cat_T_74 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _state_r_c_cat_T_75 = or(_state_r_c_cat_T_73, _state_r_c_cat_T_74)
node _state_r_c_cat_T_76 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _state_r_c_cat_T_77 = or(_state_r_c_cat_T_75, _state_r_c_cat_T_76)
node _state_r_c_cat_T_78 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _state_r_c_cat_T_79 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _state_r_c_cat_T_80 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _state_r_c_cat_T_81 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _state_r_c_cat_T_82 = or(_state_r_c_cat_T_78, _state_r_c_cat_T_79)
node _state_r_c_cat_T_83 = or(_state_r_c_cat_T_82, _state_r_c_cat_T_80)
node _state_r_c_cat_T_84 = or(_state_r_c_cat_T_83, _state_r_c_cat_T_81)
node _state_r_c_cat_T_85 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _state_r_c_cat_T_86 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _state_r_c_cat_T_87 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _state_r_c_cat_T_88 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _state_r_c_cat_T_89 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _state_r_c_cat_T_90 = or(_state_r_c_cat_T_85, _state_r_c_cat_T_86)
node _state_r_c_cat_T_91 = or(_state_r_c_cat_T_90, _state_r_c_cat_T_87)
node _state_r_c_cat_T_92 = or(_state_r_c_cat_T_91, _state_r_c_cat_T_88)
node _state_r_c_cat_T_93 = or(_state_r_c_cat_T_92, _state_r_c_cat_T_89)
node _state_r_c_cat_T_94 = or(_state_r_c_cat_T_84, _state_r_c_cat_T_93)
node _state_r_c_cat_T_95 = or(_state_r_c_cat_T_77, _state_r_c_cat_T_94)
node _state_r_c_cat_T_96 = eq(io.req.uop.mem_cmd, UInt<2>(0h3))
node _state_r_c_cat_T_97 = or(_state_r_c_cat_T_95, _state_r_c_cat_T_96)
node _state_r_c_cat_T_98 = eq(io.req.uop.mem_cmd, UInt<3>(0h6))
node _state_r_c_cat_T_99 = or(_state_r_c_cat_T_97, _state_r_c_cat_T_98)
node state_r_c_1 = cat(_state_r_c_cat_T_72, _state_r_c_cat_T_99)
node _state_r_T_59 = cat(state_r_c_1, io.req.old_meta.coh.state)
node _state_r_T_60 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_61 = cat(_state_r_T_60, UInt<2>(0h3))
node _state_r_T_62 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_63 = cat(_state_r_T_62, UInt<2>(0h2))
node _state_r_T_64 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_65 = cat(_state_r_T_64, UInt<2>(0h1))
node _state_r_T_66 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_67 = cat(_state_r_T_66, UInt<2>(0h3))
node _state_r_T_68 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_69 = cat(_state_r_T_68, UInt<2>(0h2))
node _state_r_T_70 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_71 = cat(_state_r_T_70, UInt<2>(0h3))
node _state_r_T_72 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_73 = cat(_state_r_T_72, UInt<2>(0h2))
node _state_r_T_74 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_75 = cat(_state_r_T_74, UInt<2>(0h0))
node _state_r_T_76 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_77 = cat(_state_r_T_76, UInt<2>(0h1))
node _state_r_T_78 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_79 = cat(_state_r_T_78, UInt<2>(0h0))
node _state_r_T_80 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_81 = cat(_state_r_T_80, UInt<2>(0h1))
node _state_r_T_82 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_83 = cat(_state_r_T_82, UInt<2>(0h0))
node _state_r_T_84 = eq(_state_r_T_83, _state_r_T_59)
node _state_r_T_85 = mux(_state_r_T_84, UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_86 = mux(_state_r_T_84, UInt<2>(0h1), UInt<1>(0h0))
node _state_r_T_87 = eq(_state_r_T_81, _state_r_T_59)
node _state_r_T_88 = mux(_state_r_T_87, UInt<1>(0h0), _state_r_T_85)
node _state_r_T_89 = mux(_state_r_T_87, UInt<2>(0h2), _state_r_T_86)
node _state_r_T_90 = eq(_state_r_T_79, _state_r_T_59)
node _state_r_T_91 = mux(_state_r_T_90, UInt<1>(0h0), _state_r_T_88)
node _state_r_T_92 = mux(_state_r_T_90, UInt<2>(0h1), _state_r_T_89)
node _state_r_T_93 = eq(_state_r_T_77, _state_r_T_59)
node _state_r_T_94 = mux(_state_r_T_93, UInt<1>(0h0), _state_r_T_91)
node _state_r_T_95 = mux(_state_r_T_93, UInt<2>(0h2), _state_r_T_92)
node _state_r_T_96 = eq(_state_r_T_75, _state_r_T_59)
node _state_r_T_97 = mux(_state_r_T_96, UInt<1>(0h0), _state_r_T_94)
node _state_r_T_98 = mux(_state_r_T_96, UInt<2>(0h0), _state_r_T_95)
node _state_r_T_99 = eq(_state_r_T_73, _state_r_T_59)
node _state_r_T_100 = mux(_state_r_T_99, UInt<1>(0h1), _state_r_T_97)
node _state_r_T_101 = mux(_state_r_T_99, UInt<2>(0h3), _state_r_T_98)
node _state_r_T_102 = eq(_state_r_T_71, _state_r_T_59)
node _state_r_T_103 = mux(_state_r_T_102, UInt<1>(0h1), _state_r_T_100)
node _state_r_T_104 = mux(_state_r_T_102, UInt<2>(0h3), _state_r_T_101)
node _state_r_T_105 = eq(_state_r_T_69, _state_r_T_59)
node _state_r_T_106 = mux(_state_r_T_105, UInt<1>(0h1), _state_r_T_103)
node _state_r_T_107 = mux(_state_r_T_105, UInt<2>(0h2), _state_r_T_104)
node _state_r_T_108 = eq(_state_r_T_67, _state_r_T_59)
node _state_r_T_109 = mux(_state_r_T_108, UInt<1>(0h1), _state_r_T_106)
node _state_r_T_110 = mux(_state_r_T_108, UInt<2>(0h3), _state_r_T_107)
node _state_r_T_111 = eq(_state_r_T_65, _state_r_T_59)
node _state_r_T_112 = mux(_state_r_T_111, UInt<1>(0h1), _state_r_T_109)
node _state_r_T_113 = mux(_state_r_T_111, UInt<2>(0h1), _state_r_T_110)
node _state_r_T_114 = eq(_state_r_T_63, _state_r_T_59)
node _state_r_T_115 = mux(_state_r_T_114, UInt<1>(0h1), _state_r_T_112)
node _state_r_T_116 = mux(_state_r_T_114, UInt<2>(0h2), _state_r_T_113)
node _state_r_T_117 = eq(_state_r_T_61, _state_r_T_59)
node state_is_hit_1 = mux(_state_r_T_117, UInt<1>(0h1), _state_r_T_115)
node state_r_2_1 = mux(_state_r_T_117, UInt<2>(0h3), _state_r_T_116)
wire state_coh_on_hit_1 : { state : UInt<2>}
connect state_coh_on_hit_1.state, state_r_2_1
when state_is_hit_1 :
node _state_T_37 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _state_T_38 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _state_T_39 = or(_state_T_37, _state_T_38)
node _state_T_40 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _state_T_41 = or(_state_T_39, _state_T_40)
node _state_T_42 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _state_T_43 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _state_T_44 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _state_T_45 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _state_T_46 = or(_state_T_42, _state_T_43)
node _state_T_47 = or(_state_T_46, _state_T_44)
node _state_T_48 = or(_state_T_47, _state_T_45)
node _state_T_49 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _state_T_50 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _state_T_51 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _state_T_52 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _state_T_53 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _state_T_54 = or(_state_T_49, _state_T_50)
node _state_T_55 = or(_state_T_54, _state_T_51)
node _state_T_56 = or(_state_T_55, _state_T_52)
node _state_T_57 = or(_state_T_56, _state_T_53)
node _state_T_58 = or(_state_T_48, _state_T_57)
node _state_T_59 = or(_state_T_41, _state_T_58)
node _state_T_60 = asUInt(reset)
node _state_T_61 = eq(_state_T_60, UInt<1>(0h0))
when _state_T_61 :
node _state_T_62 = eq(_state_T_59, UInt<1>(0h0))
when _state_T_62 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:220 assert(isWrite(io.req.uop.mem_cmd))\n") : state_printf_3
assert(clock, _state_T_59, UInt<1>(0h1), "") : state_assert_3
connect new_coh, state_coh_on_hit_1
connect state_new_state_1, UInt<5>(0hc)
else :
connect new_coh, io.req.old_meta.coh
connect state_new_state_1, UInt<5>(0h1)
else :
wire state_new_coh_meta_1 : { state : UInt<2>}
connect state_new_coh_meta_1.state, UInt<2>(0h0)
connect new_coh, state_new_coh_meta_1
connect state_new_state_1, UInt<5>(0h1)
connect state, state_new_state_1 | module BoomMSHR_6( // @[mshrs.scala:36:7]
input clock, // @[mshrs.scala:36:7]
input reset, // @[mshrs.scala:36:7]
input io_req_pri_val, // @[mshrs.scala:39:14]
output io_req_pri_rdy, // @[mshrs.scala:39:14]
input io_req_sec_val, // @[mshrs.scala:39:14]
output io_req_sec_rdy, // @[mshrs.scala:39:14]
input io_clear_prefetch, // @[mshrs.scala:39:14]
input [4:0] io_rob_pnr_idx, // @[mshrs.scala:39:14]
input [4:0] io_rob_head_idx, // @[mshrs.scala:39:14]
input [31:0] io_req_uop_inst, // @[mshrs.scala:39:14]
input [31:0] io_req_uop_debug_inst, // @[mshrs.scala:39:14]
input io_req_uop_is_rvc, // @[mshrs.scala:39:14]
input [33:0] io_req_uop_debug_pc, // @[mshrs.scala:39:14]
input io_req_uop_iq_type_0, // @[mshrs.scala:39:14]
input io_req_uop_iq_type_1, // @[mshrs.scala:39:14]
input io_req_uop_iq_type_2, // @[mshrs.scala:39:14]
input io_req_uop_iq_type_3, // @[mshrs.scala:39:14]
input io_req_uop_fu_code_0, // @[mshrs.scala:39:14]
input io_req_uop_fu_code_1, // @[mshrs.scala:39:14]
input io_req_uop_fu_code_2, // @[mshrs.scala:39:14]
input io_req_uop_fu_code_3, // @[mshrs.scala:39:14]
input io_req_uop_fu_code_4, // @[mshrs.scala:39:14]
input io_req_uop_fu_code_5, // @[mshrs.scala:39:14]
input io_req_uop_fu_code_6, // @[mshrs.scala:39:14]
input io_req_uop_fu_code_7, // @[mshrs.scala:39:14]
input io_req_uop_fu_code_8, // @[mshrs.scala:39:14]
input io_req_uop_fu_code_9, // @[mshrs.scala:39:14]
input io_req_uop_iw_issued, // @[mshrs.scala:39:14]
input io_req_uop_iw_issued_partial_agen, // @[mshrs.scala:39:14]
input io_req_uop_iw_issued_partial_dgen, // @[mshrs.scala:39:14]
input io_req_uop_iw_p1_speculative_child, // @[mshrs.scala:39:14]
input io_req_uop_iw_p2_speculative_child, // @[mshrs.scala:39:14]
input io_req_uop_iw_p1_bypass_hint, // @[mshrs.scala:39:14]
input io_req_uop_iw_p2_bypass_hint, // @[mshrs.scala:39:14]
input io_req_uop_iw_p3_bypass_hint, // @[mshrs.scala:39:14]
input io_req_uop_dis_col_sel, // @[mshrs.scala:39:14]
input [3:0] io_req_uop_br_mask, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_br_tag, // @[mshrs.scala:39:14]
input [3:0] io_req_uop_br_type, // @[mshrs.scala:39:14]
input io_req_uop_is_sfb, // @[mshrs.scala:39:14]
input io_req_uop_is_fence, // @[mshrs.scala:39:14]
input io_req_uop_is_fencei, // @[mshrs.scala:39:14]
input io_req_uop_is_sfence, // @[mshrs.scala:39:14]
input io_req_uop_is_amo, // @[mshrs.scala:39:14]
input io_req_uop_is_eret, // @[mshrs.scala:39:14]
input io_req_uop_is_sys_pc2epc, // @[mshrs.scala:39:14]
input io_req_uop_is_rocc, // @[mshrs.scala:39:14]
input io_req_uop_is_mov, // @[mshrs.scala:39:14]
input [3:0] io_req_uop_ftq_idx, // @[mshrs.scala:39:14]
input io_req_uop_edge_inst, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_pc_lob, // @[mshrs.scala:39:14]
input io_req_uop_taken, // @[mshrs.scala:39:14]
input io_req_uop_imm_rename, // @[mshrs.scala:39:14]
input [2:0] io_req_uop_imm_sel, // @[mshrs.scala:39:14]
input [4:0] io_req_uop_pimm, // @[mshrs.scala:39:14]
input [19:0] io_req_uop_imm_packed, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_op1_sel, // @[mshrs.scala:39:14]
input [2:0] io_req_uop_op2_sel, // @[mshrs.scala:39:14]
input io_req_uop_fp_ctrl_ldst, // @[mshrs.scala:39:14]
input io_req_uop_fp_ctrl_wen, // @[mshrs.scala:39:14]
input io_req_uop_fp_ctrl_ren1, // @[mshrs.scala:39:14]
input io_req_uop_fp_ctrl_ren2, // @[mshrs.scala:39:14]
input io_req_uop_fp_ctrl_ren3, // @[mshrs.scala:39:14]
input io_req_uop_fp_ctrl_swap12, // @[mshrs.scala:39:14]
input io_req_uop_fp_ctrl_swap23, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_fp_ctrl_typeTagIn, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_fp_ctrl_typeTagOut, // @[mshrs.scala:39:14]
input io_req_uop_fp_ctrl_fromint, // @[mshrs.scala:39:14]
input io_req_uop_fp_ctrl_toint, // @[mshrs.scala:39:14]
input io_req_uop_fp_ctrl_fastpipe, // @[mshrs.scala:39:14]
input io_req_uop_fp_ctrl_fma, // @[mshrs.scala:39:14]
input io_req_uop_fp_ctrl_div, // @[mshrs.scala:39:14]
input io_req_uop_fp_ctrl_sqrt, // @[mshrs.scala:39:14]
input io_req_uop_fp_ctrl_wflags, // @[mshrs.scala:39:14]
input io_req_uop_fp_ctrl_vec, // @[mshrs.scala:39:14]
input [4:0] io_req_uop_rob_idx, // @[mshrs.scala:39:14]
input [3:0] io_req_uop_ldq_idx, // @[mshrs.scala:39:14]
input [3:0] io_req_uop_stq_idx, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_rxq_idx, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_pdst, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_prs1, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_prs2, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_prs3, // @[mshrs.scala:39:14]
input [3:0] io_req_uop_ppred, // @[mshrs.scala:39:14]
input io_req_uop_prs1_busy, // @[mshrs.scala:39:14]
input io_req_uop_prs2_busy, // @[mshrs.scala:39:14]
input io_req_uop_prs3_busy, // @[mshrs.scala:39:14]
input io_req_uop_ppred_busy, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_stale_pdst, // @[mshrs.scala:39:14]
input io_req_uop_exception, // @[mshrs.scala:39:14]
input [63:0] io_req_uop_exc_cause, // @[mshrs.scala:39:14]
input [4:0] io_req_uop_mem_cmd, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_mem_size, // @[mshrs.scala:39:14]
input io_req_uop_mem_signed, // @[mshrs.scala:39:14]
input io_req_uop_uses_ldq, // @[mshrs.scala:39:14]
input io_req_uop_uses_stq, // @[mshrs.scala:39:14]
input io_req_uop_is_unique, // @[mshrs.scala:39:14]
input io_req_uop_flush_on_commit, // @[mshrs.scala:39:14]
input [2:0] io_req_uop_csr_cmd, // @[mshrs.scala:39:14]
input io_req_uop_ldst_is_rs1, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_ldst, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_lrs1, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_lrs2, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_lrs3, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_dst_rtype, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_lrs1_rtype, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_lrs2_rtype, // @[mshrs.scala:39:14]
input io_req_uop_frs3_en, // @[mshrs.scala:39:14]
input io_req_uop_fcn_dw, // @[mshrs.scala:39:14]
input [4:0] io_req_uop_fcn_op, // @[mshrs.scala:39:14]
input io_req_uop_fp_val, // @[mshrs.scala:39:14]
input [2:0] io_req_uop_fp_rm, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_fp_typ, // @[mshrs.scala:39:14]
input io_req_uop_xcpt_pf_if, // @[mshrs.scala:39:14]
input io_req_uop_xcpt_ae_if, // @[mshrs.scala:39:14]
input io_req_uop_xcpt_ma_if, // @[mshrs.scala:39:14]
input io_req_uop_bp_debug_if, // @[mshrs.scala:39:14]
input io_req_uop_bp_xcpt_if, // @[mshrs.scala:39:14]
input [2:0] io_req_uop_debug_fsrc, // @[mshrs.scala:39:14]
input [2:0] io_req_uop_debug_tsrc, // @[mshrs.scala:39:14]
input [33:0] io_req_addr, // @[mshrs.scala:39:14]
input [63:0] io_req_data, // @[mshrs.scala:39:14]
input io_req_is_hella, // @[mshrs.scala:39:14]
input io_req_tag_match, // @[mshrs.scala:39:14]
input [1:0] io_req_old_meta_coh_state, // @[mshrs.scala:39:14]
input [21:0] io_req_old_meta_tag, // @[mshrs.scala:39:14]
input [1:0] io_req_way_en, // @[mshrs.scala:39:14]
input [4:0] io_req_sdq_id, // @[mshrs.scala:39:14]
input io_req_is_probe, // @[mshrs.scala:39:14]
output io_idx_valid, // @[mshrs.scala:39:14]
output [3:0] io_idx_bits, // @[mshrs.scala:39:14]
output io_way_valid, // @[mshrs.scala:39:14]
output [1:0] io_way_bits, // @[mshrs.scala:39:14]
output io_tag_valid, // @[mshrs.scala:39:14]
output [23:0] io_tag_bits, // @[mshrs.scala:39:14]
input io_mem_acquire_ready, // @[mshrs.scala:39:14]
output io_mem_acquire_valid, // @[mshrs.scala:39:14]
output [2:0] io_mem_acquire_bits_param, // @[mshrs.scala:39:14]
output [31:0] io_mem_acquire_bits_address, // @[mshrs.scala:39:14]
output io_mem_grant_ready, // @[mshrs.scala:39:14]
input io_mem_grant_valid, // @[mshrs.scala:39:14]
input [2:0] io_mem_grant_bits_opcode, // @[mshrs.scala:39:14]
input [1:0] io_mem_grant_bits_param, // @[mshrs.scala:39:14]
input [3:0] io_mem_grant_bits_size, // @[mshrs.scala:39:14]
input [3:0] io_mem_grant_bits_source, // @[mshrs.scala:39:14]
input [2:0] io_mem_grant_bits_sink, // @[mshrs.scala:39:14]
input io_mem_grant_bits_denied, // @[mshrs.scala:39:14]
input [63:0] io_mem_grant_bits_data, // @[mshrs.scala:39:14]
input io_mem_grant_bits_corrupt, // @[mshrs.scala:39:14]
input io_mem_finish_ready, // @[mshrs.scala:39:14]
output io_mem_finish_valid, // @[mshrs.scala:39:14]
output [2:0] io_mem_finish_bits_sink, // @[mshrs.scala:39:14]
input io_prober_state_valid, // @[mshrs.scala:39:14]
input [33:0] io_prober_state_bits, // @[mshrs.scala:39:14]
input io_refill_ready, // @[mshrs.scala:39:14]
output io_refill_valid, // @[mshrs.scala:39:14]
output [1:0] io_refill_bits_way_en, // @[mshrs.scala:39:14]
output [9:0] io_refill_bits_addr, // @[mshrs.scala:39:14]
output [63:0] io_refill_bits_data, // @[mshrs.scala:39:14]
input io_meta_write_ready, // @[mshrs.scala:39:14]
output io_meta_write_valid, // @[mshrs.scala:39:14]
output [3:0] io_meta_write_bits_idx, // @[mshrs.scala:39:14]
output [1:0] io_meta_write_bits_way_en, // @[mshrs.scala:39:14]
output [21:0] io_meta_write_bits_tag, // @[mshrs.scala:39:14]
output [1:0] io_meta_write_bits_data_coh_state, // @[mshrs.scala:39:14]
output [21:0] io_meta_write_bits_data_tag, // @[mshrs.scala:39:14]
input io_meta_read_ready, // @[mshrs.scala:39:14]
output io_meta_read_valid, // @[mshrs.scala:39:14]
output [3:0] io_meta_read_bits_idx, // @[mshrs.scala:39:14]
output [1:0] io_meta_read_bits_way_en, // @[mshrs.scala:39:14]
output [21:0] io_meta_read_bits_tag, // @[mshrs.scala:39:14]
input io_meta_resp_valid, // @[mshrs.scala:39:14]
input [1:0] io_meta_resp_bits_coh_state, // @[mshrs.scala:39:14]
input [21:0] io_meta_resp_bits_tag, // @[mshrs.scala:39:14]
input io_wb_req_ready, // @[mshrs.scala:39:14]
output io_wb_req_valid, // @[mshrs.scala:39:14]
output [21:0] io_wb_req_bits_tag, // @[mshrs.scala:39:14]
output [3:0] io_wb_req_bits_idx, // @[mshrs.scala:39:14]
output [2:0] io_wb_req_bits_param, // @[mshrs.scala:39:14]
output [1:0] io_wb_req_bits_way_en, // @[mshrs.scala:39:14]
output io_commit_val, // @[mshrs.scala:39:14]
output [33:0] io_commit_addr, // @[mshrs.scala:39:14]
output [1:0] io_commit_coh_state, // @[mshrs.scala:39:14]
output [2:0] io_lb_read_offset, // @[mshrs.scala:39:14]
input [63:0] io_lb_resp, // @[mshrs.scala:39:14]
output io_lb_write_valid, // @[mshrs.scala:39:14]
output [2:0] io_lb_write_bits_offset, // @[mshrs.scala:39:14]
output [63:0] io_lb_write_bits_data, // @[mshrs.scala:39:14]
input io_replay_ready, // @[mshrs.scala:39:14]
output io_replay_valid, // @[mshrs.scala:39:14]
output [31:0] io_replay_bits_uop_inst, // @[mshrs.scala:39:14]
output [31:0] io_replay_bits_uop_debug_inst, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_rvc, // @[mshrs.scala:39:14]
output [33:0] io_replay_bits_uop_debug_pc, // @[mshrs.scala:39:14]
output io_replay_bits_uop_iq_type_0, // @[mshrs.scala:39:14]
output io_replay_bits_uop_iq_type_1, // @[mshrs.scala:39:14]
output io_replay_bits_uop_iq_type_2, // @[mshrs.scala:39:14]
output io_replay_bits_uop_iq_type_3, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fu_code_0, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fu_code_1, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fu_code_2, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fu_code_3, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fu_code_4, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fu_code_5, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fu_code_6, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fu_code_7, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fu_code_8, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fu_code_9, // @[mshrs.scala:39:14]
output io_replay_bits_uop_iw_issued, // @[mshrs.scala:39:14]
output io_replay_bits_uop_iw_issued_partial_agen, // @[mshrs.scala:39:14]
output io_replay_bits_uop_iw_issued_partial_dgen, // @[mshrs.scala:39:14]
output io_replay_bits_uop_iw_p1_speculative_child, // @[mshrs.scala:39:14]
output io_replay_bits_uop_iw_p2_speculative_child, // @[mshrs.scala:39:14]
output io_replay_bits_uop_iw_p1_bypass_hint, // @[mshrs.scala:39:14]
output io_replay_bits_uop_iw_p2_bypass_hint, // @[mshrs.scala:39:14]
output io_replay_bits_uop_iw_p3_bypass_hint, // @[mshrs.scala:39:14]
output io_replay_bits_uop_dis_col_sel, // @[mshrs.scala:39:14]
output [3:0] io_replay_bits_uop_br_mask, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_br_tag, // @[mshrs.scala:39:14]
output [3:0] io_replay_bits_uop_br_type, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_sfb, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_fence, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_fencei, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_sfence, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_amo, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_eret, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_sys_pc2epc, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_rocc, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_mov, // @[mshrs.scala:39:14]
output [3:0] io_replay_bits_uop_ftq_idx, // @[mshrs.scala:39:14]
output io_replay_bits_uop_edge_inst, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_pc_lob, // @[mshrs.scala:39:14]
output io_replay_bits_uop_taken, // @[mshrs.scala:39:14]
output io_replay_bits_uop_imm_rename, // @[mshrs.scala:39:14]
output [2:0] io_replay_bits_uop_imm_sel, // @[mshrs.scala:39:14]
output [4:0] io_replay_bits_uop_pimm, // @[mshrs.scala:39:14]
output [19:0] io_replay_bits_uop_imm_packed, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_op1_sel, // @[mshrs.scala:39:14]
output [2:0] io_replay_bits_uop_op2_sel, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fp_ctrl_ldst, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fp_ctrl_wen, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fp_ctrl_ren1, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fp_ctrl_ren2, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fp_ctrl_ren3, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fp_ctrl_swap12, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fp_ctrl_swap23, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_fp_ctrl_typeTagIn, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_fp_ctrl_typeTagOut, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fp_ctrl_fromint, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fp_ctrl_toint, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fp_ctrl_fastpipe, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fp_ctrl_fma, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fp_ctrl_div, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fp_ctrl_sqrt, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fp_ctrl_wflags, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fp_ctrl_vec, // @[mshrs.scala:39:14]
output [4:0] io_replay_bits_uop_rob_idx, // @[mshrs.scala:39:14]
output [3:0] io_replay_bits_uop_ldq_idx, // @[mshrs.scala:39:14]
output [3:0] io_replay_bits_uop_stq_idx, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_rxq_idx, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_pdst, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_prs1, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_prs2, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_prs3, // @[mshrs.scala:39:14]
output [3:0] io_replay_bits_uop_ppred, // @[mshrs.scala:39:14]
output io_replay_bits_uop_prs1_busy, // @[mshrs.scala:39:14]
output io_replay_bits_uop_prs2_busy, // @[mshrs.scala:39:14]
output io_replay_bits_uop_prs3_busy, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ppred_busy, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_stale_pdst, // @[mshrs.scala:39:14]
output io_replay_bits_uop_exception, // @[mshrs.scala:39:14]
output [63:0] io_replay_bits_uop_exc_cause, // @[mshrs.scala:39:14]
output [4:0] io_replay_bits_uop_mem_cmd, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_mem_size, // @[mshrs.scala:39:14]
output io_replay_bits_uop_mem_signed, // @[mshrs.scala:39:14]
output io_replay_bits_uop_uses_ldq, // @[mshrs.scala:39:14]
output io_replay_bits_uop_uses_stq, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_unique, // @[mshrs.scala:39:14]
output io_replay_bits_uop_flush_on_commit, // @[mshrs.scala:39:14]
output [2:0] io_replay_bits_uop_csr_cmd, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ldst_is_rs1, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_ldst, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_lrs1, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_lrs2, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_lrs3, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_dst_rtype, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_lrs1_rtype, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_lrs2_rtype, // @[mshrs.scala:39:14]
output io_replay_bits_uop_frs3_en, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fcn_dw, // @[mshrs.scala:39:14]
output [4:0] io_replay_bits_uop_fcn_op, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fp_val, // @[mshrs.scala:39:14]
output [2:0] io_replay_bits_uop_fp_rm, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_fp_typ, // @[mshrs.scala:39:14]
output io_replay_bits_uop_xcpt_pf_if, // @[mshrs.scala:39:14]
output io_replay_bits_uop_xcpt_ae_if, // @[mshrs.scala:39:14]
output io_replay_bits_uop_xcpt_ma_if, // @[mshrs.scala:39:14]
output io_replay_bits_uop_bp_debug_if, // @[mshrs.scala:39:14]
output io_replay_bits_uop_bp_xcpt_if, // @[mshrs.scala:39:14]
output [2:0] io_replay_bits_uop_debug_fsrc, // @[mshrs.scala:39:14]
output [2:0] io_replay_bits_uop_debug_tsrc, // @[mshrs.scala:39:14]
output [33:0] io_replay_bits_addr, // @[mshrs.scala:39:14]
output [63:0] io_replay_bits_data, // @[mshrs.scala:39:14]
output io_replay_bits_is_hella, // @[mshrs.scala:39:14]
output io_replay_bits_tag_match, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_old_meta_coh_state, // @[mshrs.scala:39:14]
output [21:0] io_replay_bits_old_meta_tag, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_way_en, // @[mshrs.scala:39:14]
output [4:0] io_replay_bits_sdq_id, // @[mshrs.scala:39:14]
input io_resp_ready, // @[mshrs.scala:39:14]
output io_resp_valid, // @[mshrs.scala:39:14]
output [31:0] io_resp_bits_uop_inst, // @[mshrs.scala:39:14]
output [31:0] io_resp_bits_uop_debug_inst, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_rvc, // @[mshrs.scala:39:14]
output [33:0] io_resp_bits_uop_debug_pc, // @[mshrs.scala:39:14]
output io_resp_bits_uop_iq_type_0, // @[mshrs.scala:39:14]
output io_resp_bits_uop_iq_type_1, // @[mshrs.scala:39:14]
output io_resp_bits_uop_iq_type_2, // @[mshrs.scala:39:14]
output io_resp_bits_uop_iq_type_3, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fu_code_0, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fu_code_1, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fu_code_2, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fu_code_3, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fu_code_4, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fu_code_5, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fu_code_6, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fu_code_7, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fu_code_8, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fu_code_9, // @[mshrs.scala:39:14]
output io_resp_bits_uop_iw_issued, // @[mshrs.scala:39:14]
output io_resp_bits_uop_iw_issued_partial_agen, // @[mshrs.scala:39:14]
output io_resp_bits_uop_iw_issued_partial_dgen, // @[mshrs.scala:39:14]
output io_resp_bits_uop_iw_p1_speculative_child, // @[mshrs.scala:39:14]
output io_resp_bits_uop_iw_p2_speculative_child, // @[mshrs.scala:39:14]
output io_resp_bits_uop_iw_p1_bypass_hint, // @[mshrs.scala:39:14]
output io_resp_bits_uop_iw_p2_bypass_hint, // @[mshrs.scala:39:14]
output io_resp_bits_uop_iw_p3_bypass_hint, // @[mshrs.scala:39:14]
output io_resp_bits_uop_dis_col_sel, // @[mshrs.scala:39:14]
output [3:0] io_resp_bits_uop_br_mask, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_br_tag, // @[mshrs.scala:39:14]
output [3:0] io_resp_bits_uop_br_type, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_sfb, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_fence, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_fencei, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_sfence, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_amo, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_eret, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_sys_pc2epc, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_rocc, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_mov, // @[mshrs.scala:39:14]
output [3:0] io_resp_bits_uop_ftq_idx, // @[mshrs.scala:39:14]
output io_resp_bits_uop_edge_inst, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_pc_lob, // @[mshrs.scala:39:14]
output io_resp_bits_uop_taken, // @[mshrs.scala:39:14]
output io_resp_bits_uop_imm_rename, // @[mshrs.scala:39:14]
output [2:0] io_resp_bits_uop_imm_sel, // @[mshrs.scala:39:14]
output [4:0] io_resp_bits_uop_pimm, // @[mshrs.scala:39:14]
output [19:0] io_resp_bits_uop_imm_packed, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_op1_sel, // @[mshrs.scala:39:14]
output [2:0] io_resp_bits_uop_op2_sel, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fp_ctrl_ldst, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fp_ctrl_wen, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fp_ctrl_ren1, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fp_ctrl_ren2, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fp_ctrl_ren3, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fp_ctrl_swap12, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fp_ctrl_swap23, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_fp_ctrl_typeTagIn, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_fp_ctrl_typeTagOut, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fp_ctrl_fromint, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fp_ctrl_toint, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fp_ctrl_fastpipe, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fp_ctrl_fma, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fp_ctrl_div, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fp_ctrl_sqrt, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fp_ctrl_wflags, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fp_ctrl_vec, // @[mshrs.scala:39:14]
output [4:0] io_resp_bits_uop_rob_idx, // @[mshrs.scala:39:14]
output [3:0] io_resp_bits_uop_ldq_idx, // @[mshrs.scala:39:14]
output [3:0] io_resp_bits_uop_stq_idx, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_rxq_idx, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_pdst, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_prs1, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_prs2, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_prs3, // @[mshrs.scala:39:14]
output [3:0] io_resp_bits_uop_ppred, // @[mshrs.scala:39:14]
output io_resp_bits_uop_prs1_busy, // @[mshrs.scala:39:14]
output io_resp_bits_uop_prs2_busy, // @[mshrs.scala:39:14]
output io_resp_bits_uop_prs3_busy, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ppred_busy, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_stale_pdst, // @[mshrs.scala:39:14]
output io_resp_bits_uop_exception, // @[mshrs.scala:39:14]
output [63:0] io_resp_bits_uop_exc_cause, // @[mshrs.scala:39:14]
output [4:0] io_resp_bits_uop_mem_cmd, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_mem_size, // @[mshrs.scala:39:14]
output io_resp_bits_uop_mem_signed, // @[mshrs.scala:39:14]
output io_resp_bits_uop_uses_ldq, // @[mshrs.scala:39:14]
output io_resp_bits_uop_uses_stq, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_unique, // @[mshrs.scala:39:14]
output io_resp_bits_uop_flush_on_commit, // @[mshrs.scala:39:14]
output [2:0] io_resp_bits_uop_csr_cmd, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ldst_is_rs1, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_ldst, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_lrs1, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_lrs2, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_lrs3, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_dst_rtype, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_lrs1_rtype, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_lrs2_rtype, // @[mshrs.scala:39:14]
output io_resp_bits_uop_frs3_en, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fcn_dw, // @[mshrs.scala:39:14]
output [4:0] io_resp_bits_uop_fcn_op, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fp_val, // @[mshrs.scala:39:14]
output [2:0] io_resp_bits_uop_fp_rm, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_fp_typ, // @[mshrs.scala:39:14]
output io_resp_bits_uop_xcpt_pf_if, // @[mshrs.scala:39:14]
output io_resp_bits_uop_xcpt_ae_if, // @[mshrs.scala:39:14]
output io_resp_bits_uop_xcpt_ma_if, // @[mshrs.scala:39:14]
output io_resp_bits_uop_bp_debug_if, // @[mshrs.scala:39:14]
output io_resp_bits_uop_bp_xcpt_if, // @[mshrs.scala:39:14]
output [2:0] io_resp_bits_uop_debug_fsrc, // @[mshrs.scala:39:14]
output [2:0] io_resp_bits_uop_debug_tsrc, // @[mshrs.scala:39:14]
output [63:0] io_resp_bits_data, // @[mshrs.scala:39:14]
output io_resp_bits_is_hella, // @[mshrs.scala:39:14]
input io_wb_resp, // @[mshrs.scala:39:14]
output io_probe_rdy // @[mshrs.scala:39:14]
);
wire rpq_io_deq_ready; // @[mshrs.scala:135:20, :234:30, :241:40, :246:41, :266:45]
wire _rpq_io_enq_ready; // @[mshrs.scala:128:19]
wire _rpq_io_deq_valid; // @[mshrs.scala:128:19]
wire [31:0] _rpq_io_deq_bits_uop_inst; // @[mshrs.scala:128:19]
wire [31:0] _rpq_io_deq_bits_uop_debug_inst; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_rvc; // @[mshrs.scala:128:19]
wire [33:0] _rpq_io_deq_bits_uop_debug_pc; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_iq_type_0; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_iq_type_1; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_iq_type_2; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_iq_type_3; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fu_code_0; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fu_code_1; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fu_code_2; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fu_code_3; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fu_code_4; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fu_code_5; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fu_code_6; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fu_code_7; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fu_code_8; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fu_code_9; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_iw_issued; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_iw_issued_partial_agen; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_iw_issued_partial_dgen; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_iw_p1_speculative_child; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_iw_p2_speculative_child; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_iw_p1_bypass_hint; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_iw_p2_bypass_hint; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_iw_p3_bypass_hint; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_dis_col_sel; // @[mshrs.scala:128:19]
wire [3:0] _rpq_io_deq_bits_uop_br_mask; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_br_tag; // @[mshrs.scala:128:19]
wire [3:0] _rpq_io_deq_bits_uop_br_type; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_sfb; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_fence; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_fencei; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_sfence; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_amo; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_eret; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_sys_pc2epc; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_rocc; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_mov; // @[mshrs.scala:128:19]
wire [3:0] _rpq_io_deq_bits_uop_ftq_idx; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_edge_inst; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_pc_lob; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_taken; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_imm_rename; // @[mshrs.scala:128:19]
wire [2:0] _rpq_io_deq_bits_uop_imm_sel; // @[mshrs.scala:128:19]
wire [4:0] _rpq_io_deq_bits_uop_pimm; // @[mshrs.scala:128:19]
wire [19:0] _rpq_io_deq_bits_uop_imm_packed; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_op1_sel; // @[mshrs.scala:128:19]
wire [2:0] _rpq_io_deq_bits_uop_op2_sel; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fp_ctrl_ldst; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fp_ctrl_wen; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fp_ctrl_ren1; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fp_ctrl_ren2; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fp_ctrl_ren3; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fp_ctrl_swap12; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fp_ctrl_swap23; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_fp_ctrl_typeTagIn; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_fp_ctrl_typeTagOut; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fp_ctrl_fromint; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fp_ctrl_toint; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fp_ctrl_fastpipe; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fp_ctrl_fma; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fp_ctrl_div; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fp_ctrl_sqrt; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fp_ctrl_wflags; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fp_ctrl_vec; // @[mshrs.scala:128:19]
wire [4:0] _rpq_io_deq_bits_uop_rob_idx; // @[mshrs.scala:128:19]
wire [3:0] _rpq_io_deq_bits_uop_ldq_idx; // @[mshrs.scala:128:19]
wire [3:0] _rpq_io_deq_bits_uop_stq_idx; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_rxq_idx; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_pdst; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_prs1; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_prs2; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_prs3; // @[mshrs.scala:128:19]
wire [3:0] _rpq_io_deq_bits_uop_ppred; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_prs1_busy; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_prs2_busy; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_prs3_busy; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ppred_busy; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_stale_pdst; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_exception; // @[mshrs.scala:128:19]
wire [63:0] _rpq_io_deq_bits_uop_exc_cause; // @[mshrs.scala:128:19]
wire [4:0] _rpq_io_deq_bits_uop_mem_cmd; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_mem_size; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_mem_signed; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_uses_ldq; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_uses_stq; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_unique; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_flush_on_commit; // @[mshrs.scala:128:19]
wire [2:0] _rpq_io_deq_bits_uop_csr_cmd; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ldst_is_rs1; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_ldst; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_lrs1; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_lrs2; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_lrs3; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_dst_rtype; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_lrs1_rtype; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_lrs2_rtype; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_frs3_en; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fcn_dw; // @[mshrs.scala:128:19]
wire [4:0] _rpq_io_deq_bits_uop_fcn_op; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fp_val; // @[mshrs.scala:128:19]
wire [2:0] _rpq_io_deq_bits_uop_fp_rm; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_fp_typ; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_xcpt_pf_if; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_xcpt_ae_if; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_xcpt_ma_if; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_bp_debug_if; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_bp_xcpt_if; // @[mshrs.scala:128:19]
wire [2:0] _rpq_io_deq_bits_uop_debug_fsrc; // @[mshrs.scala:128:19]
wire [2:0] _rpq_io_deq_bits_uop_debug_tsrc; // @[mshrs.scala:128:19]
wire [33:0] _rpq_io_deq_bits_addr; // @[mshrs.scala:128:19]
wire [63:0] _rpq_io_deq_bits_data; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_is_hella; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_way_en; // @[mshrs.scala:128:19]
wire _rpq_io_empty; // @[mshrs.scala:128:19]
wire io_req_pri_val_0 = io_req_pri_val; // @[mshrs.scala:36:7]
wire io_req_sec_val_0 = io_req_sec_val; // @[mshrs.scala:36:7]
wire io_clear_prefetch_0 = io_clear_prefetch; // @[mshrs.scala:36:7]
wire [4:0] io_rob_pnr_idx_0 = io_rob_pnr_idx; // @[mshrs.scala:36:7]
wire [4:0] io_rob_head_idx_0 = io_rob_head_idx; // @[mshrs.scala:36:7]
wire [31:0] io_req_uop_inst_0 = io_req_uop_inst; // @[mshrs.scala:36:7]
wire [31:0] io_req_uop_debug_inst_0 = io_req_uop_debug_inst; // @[mshrs.scala:36:7]
wire io_req_uop_is_rvc_0 = io_req_uop_is_rvc; // @[mshrs.scala:36:7]
wire [33:0] io_req_uop_debug_pc_0 = io_req_uop_debug_pc; // @[mshrs.scala:36:7]
wire io_req_uop_iq_type_0_0 = io_req_uop_iq_type_0; // @[mshrs.scala:36:7]
wire io_req_uop_iq_type_1_0 = io_req_uop_iq_type_1; // @[mshrs.scala:36:7]
wire io_req_uop_iq_type_2_0 = io_req_uop_iq_type_2; // @[mshrs.scala:36:7]
wire io_req_uop_iq_type_3_0 = io_req_uop_iq_type_3; // @[mshrs.scala:36:7]
wire io_req_uop_fu_code_0_0 = io_req_uop_fu_code_0; // @[mshrs.scala:36:7]
wire io_req_uop_fu_code_1_0 = io_req_uop_fu_code_1; // @[mshrs.scala:36:7]
wire io_req_uop_fu_code_2_0 = io_req_uop_fu_code_2; // @[mshrs.scala:36:7]
wire io_req_uop_fu_code_3_0 = io_req_uop_fu_code_3; // @[mshrs.scala:36:7]
wire io_req_uop_fu_code_4_0 = io_req_uop_fu_code_4; // @[mshrs.scala:36:7]
wire io_req_uop_fu_code_5_0 = io_req_uop_fu_code_5; // @[mshrs.scala:36:7]
wire io_req_uop_fu_code_6_0 = io_req_uop_fu_code_6; // @[mshrs.scala:36:7]
wire io_req_uop_fu_code_7_0 = io_req_uop_fu_code_7; // @[mshrs.scala:36:7]
wire io_req_uop_fu_code_8_0 = io_req_uop_fu_code_8; // @[mshrs.scala:36:7]
wire io_req_uop_fu_code_9_0 = io_req_uop_fu_code_9; // @[mshrs.scala:36:7]
wire io_req_uop_iw_issued_0 = io_req_uop_iw_issued; // @[mshrs.scala:36:7]
wire io_req_uop_iw_issued_partial_agen_0 = io_req_uop_iw_issued_partial_agen; // @[mshrs.scala:36:7]
wire io_req_uop_iw_issued_partial_dgen_0 = io_req_uop_iw_issued_partial_dgen; // @[mshrs.scala:36:7]
wire io_req_uop_iw_p1_speculative_child_0 = io_req_uop_iw_p1_speculative_child; // @[mshrs.scala:36:7]
wire io_req_uop_iw_p2_speculative_child_0 = io_req_uop_iw_p2_speculative_child; // @[mshrs.scala:36:7]
wire io_req_uop_iw_p1_bypass_hint_0 = io_req_uop_iw_p1_bypass_hint; // @[mshrs.scala:36:7]
wire io_req_uop_iw_p2_bypass_hint_0 = io_req_uop_iw_p2_bypass_hint; // @[mshrs.scala:36:7]
wire io_req_uop_iw_p3_bypass_hint_0 = io_req_uop_iw_p3_bypass_hint; // @[mshrs.scala:36:7]
wire io_req_uop_dis_col_sel_0 = io_req_uop_dis_col_sel; // @[mshrs.scala:36:7]
wire [3:0] io_req_uop_br_mask_0 = io_req_uop_br_mask; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_br_tag_0 = io_req_uop_br_tag; // @[mshrs.scala:36:7]
wire [3:0] io_req_uop_br_type_0 = io_req_uop_br_type; // @[mshrs.scala:36:7]
wire io_req_uop_is_sfb_0 = io_req_uop_is_sfb; // @[mshrs.scala:36:7]
wire io_req_uop_is_fence_0 = io_req_uop_is_fence; // @[mshrs.scala:36:7]
wire io_req_uop_is_fencei_0 = io_req_uop_is_fencei; // @[mshrs.scala:36:7]
wire io_req_uop_is_sfence_0 = io_req_uop_is_sfence; // @[mshrs.scala:36:7]
wire io_req_uop_is_amo_0 = io_req_uop_is_amo; // @[mshrs.scala:36:7]
wire io_req_uop_is_eret_0 = io_req_uop_is_eret; // @[mshrs.scala:36:7]
wire io_req_uop_is_sys_pc2epc_0 = io_req_uop_is_sys_pc2epc; // @[mshrs.scala:36:7]
wire io_req_uop_is_rocc_0 = io_req_uop_is_rocc; // @[mshrs.scala:36:7]
wire io_req_uop_is_mov_0 = io_req_uop_is_mov; // @[mshrs.scala:36:7]
wire [3:0] io_req_uop_ftq_idx_0 = io_req_uop_ftq_idx; // @[mshrs.scala:36:7]
wire io_req_uop_edge_inst_0 = io_req_uop_edge_inst; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_pc_lob_0 = io_req_uop_pc_lob; // @[mshrs.scala:36:7]
wire io_req_uop_taken_0 = io_req_uop_taken; // @[mshrs.scala:36:7]
wire io_req_uop_imm_rename_0 = io_req_uop_imm_rename; // @[mshrs.scala:36:7]
wire [2:0] io_req_uop_imm_sel_0 = io_req_uop_imm_sel; // @[mshrs.scala:36:7]
wire [4:0] io_req_uop_pimm_0 = io_req_uop_pimm; // @[mshrs.scala:36:7]
wire [19:0] io_req_uop_imm_packed_0 = io_req_uop_imm_packed; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_op1_sel_0 = io_req_uop_op1_sel; // @[mshrs.scala:36:7]
wire [2:0] io_req_uop_op2_sel_0 = io_req_uop_op2_sel; // @[mshrs.scala:36:7]
wire io_req_uop_fp_ctrl_ldst_0 = io_req_uop_fp_ctrl_ldst; // @[mshrs.scala:36:7]
wire io_req_uop_fp_ctrl_wen_0 = io_req_uop_fp_ctrl_wen; // @[mshrs.scala:36:7]
wire io_req_uop_fp_ctrl_ren1_0 = io_req_uop_fp_ctrl_ren1; // @[mshrs.scala:36:7]
wire io_req_uop_fp_ctrl_ren2_0 = io_req_uop_fp_ctrl_ren2; // @[mshrs.scala:36:7]
wire io_req_uop_fp_ctrl_ren3_0 = io_req_uop_fp_ctrl_ren3; // @[mshrs.scala:36:7]
wire io_req_uop_fp_ctrl_swap12_0 = io_req_uop_fp_ctrl_swap12; // @[mshrs.scala:36:7]
wire io_req_uop_fp_ctrl_swap23_0 = io_req_uop_fp_ctrl_swap23; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_fp_ctrl_typeTagIn_0 = io_req_uop_fp_ctrl_typeTagIn; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_fp_ctrl_typeTagOut_0 = io_req_uop_fp_ctrl_typeTagOut; // @[mshrs.scala:36:7]
wire io_req_uop_fp_ctrl_fromint_0 = io_req_uop_fp_ctrl_fromint; // @[mshrs.scala:36:7]
wire io_req_uop_fp_ctrl_toint_0 = io_req_uop_fp_ctrl_toint; // @[mshrs.scala:36:7]
wire io_req_uop_fp_ctrl_fastpipe_0 = io_req_uop_fp_ctrl_fastpipe; // @[mshrs.scala:36:7]
wire io_req_uop_fp_ctrl_fma_0 = io_req_uop_fp_ctrl_fma; // @[mshrs.scala:36:7]
wire io_req_uop_fp_ctrl_div_0 = io_req_uop_fp_ctrl_div; // @[mshrs.scala:36:7]
wire io_req_uop_fp_ctrl_sqrt_0 = io_req_uop_fp_ctrl_sqrt; // @[mshrs.scala:36:7]
wire io_req_uop_fp_ctrl_wflags_0 = io_req_uop_fp_ctrl_wflags; // @[mshrs.scala:36:7]
wire io_req_uop_fp_ctrl_vec_0 = io_req_uop_fp_ctrl_vec; // @[mshrs.scala:36:7]
wire [4:0] io_req_uop_rob_idx_0 = io_req_uop_rob_idx; // @[mshrs.scala:36:7]
wire [3:0] io_req_uop_ldq_idx_0 = io_req_uop_ldq_idx; // @[mshrs.scala:36:7]
wire [3:0] io_req_uop_stq_idx_0 = io_req_uop_stq_idx; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_rxq_idx_0 = io_req_uop_rxq_idx; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_pdst_0 = io_req_uop_pdst; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_prs1_0 = io_req_uop_prs1; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_prs2_0 = io_req_uop_prs2; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_prs3_0 = io_req_uop_prs3; // @[mshrs.scala:36:7]
wire [3:0] io_req_uop_ppred_0 = io_req_uop_ppred; // @[mshrs.scala:36:7]
wire io_req_uop_prs1_busy_0 = io_req_uop_prs1_busy; // @[mshrs.scala:36:7]
wire io_req_uop_prs2_busy_0 = io_req_uop_prs2_busy; // @[mshrs.scala:36:7]
wire io_req_uop_prs3_busy_0 = io_req_uop_prs3_busy; // @[mshrs.scala:36:7]
wire io_req_uop_ppred_busy_0 = io_req_uop_ppred_busy; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_stale_pdst_0 = io_req_uop_stale_pdst; // @[mshrs.scala:36:7]
wire io_req_uop_exception_0 = io_req_uop_exception; // @[mshrs.scala:36:7]
wire [63:0] io_req_uop_exc_cause_0 = io_req_uop_exc_cause; // @[mshrs.scala:36:7]
wire [4:0] io_req_uop_mem_cmd_0 = io_req_uop_mem_cmd; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_mem_size_0 = io_req_uop_mem_size; // @[mshrs.scala:36:7]
wire io_req_uop_mem_signed_0 = io_req_uop_mem_signed; // @[mshrs.scala:36:7]
wire io_req_uop_uses_ldq_0 = io_req_uop_uses_ldq; // @[mshrs.scala:36:7]
wire io_req_uop_uses_stq_0 = io_req_uop_uses_stq; // @[mshrs.scala:36:7]
wire io_req_uop_is_unique_0 = io_req_uop_is_unique; // @[mshrs.scala:36:7]
wire io_req_uop_flush_on_commit_0 = io_req_uop_flush_on_commit; // @[mshrs.scala:36:7]
wire [2:0] io_req_uop_csr_cmd_0 = io_req_uop_csr_cmd; // @[mshrs.scala:36:7]
wire io_req_uop_ldst_is_rs1_0 = io_req_uop_ldst_is_rs1; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_ldst_0 = io_req_uop_ldst; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_lrs1_0 = io_req_uop_lrs1; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_lrs2_0 = io_req_uop_lrs2; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_lrs3_0 = io_req_uop_lrs3; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_dst_rtype_0 = io_req_uop_dst_rtype; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_lrs1_rtype_0 = io_req_uop_lrs1_rtype; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_lrs2_rtype_0 = io_req_uop_lrs2_rtype; // @[mshrs.scala:36:7]
wire io_req_uop_frs3_en_0 = io_req_uop_frs3_en; // @[mshrs.scala:36:7]
wire io_req_uop_fcn_dw_0 = io_req_uop_fcn_dw; // @[mshrs.scala:36:7]
wire [4:0] io_req_uop_fcn_op_0 = io_req_uop_fcn_op; // @[mshrs.scala:36:7]
wire io_req_uop_fp_val_0 = io_req_uop_fp_val; // @[mshrs.scala:36:7]
wire [2:0] io_req_uop_fp_rm_0 = io_req_uop_fp_rm; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_fp_typ_0 = io_req_uop_fp_typ; // @[mshrs.scala:36:7]
wire io_req_uop_xcpt_pf_if_0 = io_req_uop_xcpt_pf_if; // @[mshrs.scala:36:7]
wire io_req_uop_xcpt_ae_if_0 = io_req_uop_xcpt_ae_if; // @[mshrs.scala:36:7]
wire io_req_uop_xcpt_ma_if_0 = io_req_uop_xcpt_ma_if; // @[mshrs.scala:36:7]
wire io_req_uop_bp_debug_if_0 = io_req_uop_bp_debug_if; // @[mshrs.scala:36:7]
wire io_req_uop_bp_xcpt_if_0 = io_req_uop_bp_xcpt_if; // @[mshrs.scala:36:7]
wire [2:0] io_req_uop_debug_fsrc_0 = io_req_uop_debug_fsrc; // @[mshrs.scala:36:7]
wire [2:0] io_req_uop_debug_tsrc_0 = io_req_uop_debug_tsrc; // @[mshrs.scala:36:7]
wire [33:0] io_req_addr_0 = io_req_addr; // @[mshrs.scala:36:7]
wire [63:0] io_req_data_0 = io_req_data; // @[mshrs.scala:36:7]
wire io_req_is_hella_0 = io_req_is_hella; // @[mshrs.scala:36:7]
wire io_req_tag_match_0 = io_req_tag_match; // @[mshrs.scala:36:7]
wire [1:0] io_req_old_meta_coh_state_0 = io_req_old_meta_coh_state; // @[mshrs.scala:36:7]
wire [21:0] io_req_old_meta_tag_0 = io_req_old_meta_tag; // @[mshrs.scala:36:7]
wire [1:0] io_req_way_en_0 = io_req_way_en; // @[mshrs.scala:36:7]
wire [4:0] io_req_sdq_id_0 = io_req_sdq_id; // @[mshrs.scala:36:7]
wire io_req_is_probe_0 = io_req_is_probe; // @[mshrs.scala:36:7]
wire io_mem_acquire_ready_0 = io_mem_acquire_ready; // @[mshrs.scala:36:7]
wire io_mem_grant_valid_0 = io_mem_grant_valid; // @[mshrs.scala:36:7]
wire [2:0] io_mem_grant_bits_opcode_0 = io_mem_grant_bits_opcode; // @[mshrs.scala:36:7]
wire [1:0] io_mem_grant_bits_param_0 = io_mem_grant_bits_param; // @[mshrs.scala:36:7]
wire [3:0] io_mem_grant_bits_size_0 = io_mem_grant_bits_size; // @[mshrs.scala:36:7]
wire [3:0] io_mem_grant_bits_source_0 = io_mem_grant_bits_source; // @[mshrs.scala:36:7]
wire [2:0] io_mem_grant_bits_sink_0 = io_mem_grant_bits_sink; // @[mshrs.scala:36:7]
wire io_mem_grant_bits_denied_0 = io_mem_grant_bits_denied; // @[mshrs.scala:36:7]
wire [63:0] io_mem_grant_bits_data_0 = io_mem_grant_bits_data; // @[mshrs.scala:36:7]
wire io_mem_grant_bits_corrupt_0 = io_mem_grant_bits_corrupt; // @[mshrs.scala:36:7]
wire io_mem_finish_ready_0 = io_mem_finish_ready; // @[mshrs.scala:36:7]
wire io_prober_state_valid_0 = io_prober_state_valid; // @[mshrs.scala:36:7]
wire [33:0] io_prober_state_bits_0 = io_prober_state_bits; // @[mshrs.scala:36:7]
wire io_refill_ready_0 = io_refill_ready; // @[mshrs.scala:36:7]
wire io_meta_write_ready_0 = io_meta_write_ready; // @[mshrs.scala:36:7]
wire io_meta_read_ready_0 = io_meta_read_ready; // @[mshrs.scala:36:7]
wire io_meta_resp_valid_0 = io_meta_resp_valid; // @[mshrs.scala:36:7]
wire [1:0] io_meta_resp_bits_coh_state_0 = io_meta_resp_bits_coh_state; // @[mshrs.scala:36:7]
wire [21:0] io_meta_resp_bits_tag_0 = io_meta_resp_bits_tag; // @[mshrs.scala:36:7]
wire io_wb_req_ready_0 = io_wb_req_ready; // @[mshrs.scala:36:7]
wire [63:0] io_lb_resp_0 = io_lb_resp; // @[mshrs.scala:36:7]
wire io_replay_ready_0 = io_replay_ready; // @[mshrs.scala:36:7]
wire io_resp_ready_0 = io_resp_ready; // @[mshrs.scala:36:7]
wire io_wb_resp_0 = io_wb_resp; // @[mshrs.scala:36:7]
wire _state_T = reset; // @[mshrs.scala:213:11]
wire _state_T_26 = reset; // @[mshrs.scala:220:15]
wire _state_T_34 = reset; // @[mshrs.scala:213:11]
wire _state_T_60 = reset; // @[mshrs.scala:220:15]
wire [2:0] io_id = 3'h6; // @[mshrs.scala:36:7]
wire [2:0] io_mem_acquire_bits_opcode = 3'h6; // @[mshrs.scala:36:7]
wire [2:0] io_mem_acquire_bits_a_opcode = 3'h6; // @[Edges.scala:346:17]
wire [2:0] _io_mem_acquire_bits_a_mask_sizeOH_T = 3'h6; // @[Misc.scala:202:34]
wire [3:0] io_brupdate_b1_resolve_mask = 4'h0; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b1_mispredict_mask = 4'h0; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b2_uop_br_mask = 4'h0; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b2_uop_br_type = 4'h0; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b2_uop_ftq_idx = 4'h0; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b2_uop_ldq_idx = 4'h0; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b2_uop_stq_idx = 4'h0; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b2_uop_ppred = 4'h0; // @[mshrs.scala:36:7]
wire [3:0] _r_T_10 = 4'h0; // @[Metadata.scala:125:10]
wire [3:0] _grow_param_r_T_16 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _coh_on_grant_T_4 = 4'h0; // @[Metadata.scala:87:10]
wire [3:0] _r1_T_16 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _r2_T_16 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _state_req_needs_wb_r_T_10 = 4'h0; // @[Metadata.scala:125:10]
wire [3:0] _state_r_T_16 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _needs_wb_r_T_10 = 4'h0; // @[Metadata.scala:125:10]
wire [3:0] _r_T_80 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _r_T_139 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _state_req_needs_wb_r_T_74 = 4'h0; // @[Metadata.scala:125:10]
wire [3:0] _state_r_T_75 = 4'h0; // @[Metadata.scala:68:10]
wire [31:0] io_brupdate_b2_uop_inst = 32'h0; // @[mshrs.scala:36:7]
wire [31:0] io_brupdate_b2_uop_debug_inst = 32'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_rvc = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_iq_type_0 = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_iq_type_1 = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_iq_type_2 = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_iq_type_3 = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fu_code_0 = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fu_code_1 = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fu_code_2 = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fu_code_3 = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fu_code_4 = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fu_code_5 = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fu_code_6 = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fu_code_7 = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fu_code_8 = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fu_code_9 = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_iw_issued = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_iw_issued_partial_agen = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_iw_issued_partial_dgen = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_iw_p1_speculative_child = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_iw_p2_speculative_child = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_iw_p1_bypass_hint = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_iw_p2_bypass_hint = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_iw_p3_bypass_hint = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_dis_col_sel = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_sfb = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_fence = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_fencei = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_sfence = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_amo = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_eret = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_sys_pc2epc = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_rocc = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_mov = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_edge_inst = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_taken = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_imm_rename = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fp_ctrl_ldst = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fp_ctrl_wen = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fp_ctrl_ren1 = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fp_ctrl_ren2 = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fp_ctrl_ren3 = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fp_ctrl_swap12 = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fp_ctrl_swap23 = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fp_ctrl_fromint = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fp_ctrl_toint = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fp_ctrl_fastpipe = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fp_ctrl_fma = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fp_ctrl_div = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fp_ctrl_sqrt = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fp_ctrl_wflags = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fp_ctrl_vec = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_prs1_busy = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_prs2_busy = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_prs3_busy = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ppred_busy = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_exception = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_mem_signed = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_uses_ldq = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_uses_stq = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_unique = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_flush_on_commit = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ldst_is_rs1 = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_frs3_en = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fcn_dw = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fp_val = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_xcpt_pf_if = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_xcpt_ae_if = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_xcpt_ma_if = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_bp_debug_if = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_bp_xcpt_if = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_mispredict = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_taken = 1'h0; // @[mshrs.scala:36:7]
wire io_exception = 1'h0; // @[mshrs.scala:36:7]
wire io_mem_acquire_bits_corrupt = 1'h0; // @[mshrs.scala:36:7]
wire _r_T_2 = 1'h0; // @[Metadata.scala:140:24]
wire _r_T_4 = 1'h0; // @[Metadata.scala:140:24]
wire _r_T_20 = 1'h0; // @[Misc.scala:38:9]
wire _r_T_24 = 1'h0; // @[Misc.scala:38:9]
wire _r_T_28 = 1'h0; // @[Misc.scala:38:9]
wire _grow_param_r_T_26 = 1'h0; // @[Misc.scala:35:9]
wire _grow_param_r_T_29 = 1'h0; // @[Misc.scala:35:9]
wire _grow_param_r_T_32 = 1'h0; // @[Misc.scala:35:9]
wire _grow_param_r_T_35 = 1'h0; // @[Misc.scala:35:9]
wire _grow_param_r_T_38 = 1'h0; // @[Misc.scala:35:9]
wire _r1_T_26 = 1'h0; // @[Misc.scala:35:9]
wire _r1_T_29 = 1'h0; // @[Misc.scala:35:9]
wire _r1_T_32 = 1'h0; // @[Misc.scala:35:9]
wire _r1_T_35 = 1'h0; // @[Misc.scala:35:9]
wire _r1_T_38 = 1'h0; // @[Misc.scala:35:9]
wire _r2_T_26 = 1'h0; // @[Misc.scala:35:9]
wire _r2_T_29 = 1'h0; // @[Misc.scala:35:9]
wire _r2_T_32 = 1'h0; // @[Misc.scala:35:9]
wire _r2_T_35 = 1'h0; // @[Misc.scala:35:9]
wire _r2_T_38 = 1'h0; // @[Misc.scala:35:9]
wire _io_mem_acquire_bits_legal_T = 1'h0; // @[Parameters.scala:684:29]
wire _io_mem_acquire_bits_legal_T_6 = 1'h0; // @[Parameters.scala:684:54]
wire _io_mem_acquire_bits_legal_T_15 = 1'h0; // @[Parameters.scala:686:26]
wire io_mem_acquire_bits_a_corrupt = 1'h0; // @[Edges.scala:346:17]
wire io_mem_acquire_bits_a_mask_sub_size = 1'h0; // @[Misc.scala:209:26]
wire _io_mem_acquire_bits_a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38]
wire _io_mem_acquire_bits_a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38]
wire _io_mem_acquire_bits_a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38]
wire _io_mem_acquire_bits_a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38]
wire _state_req_needs_wb_r_T_2 = 1'h0; // @[Metadata.scala:140:24]
wire _state_req_needs_wb_r_T_4 = 1'h0; // @[Metadata.scala:140:24]
wire _state_req_needs_wb_r_T_20 = 1'h0; // @[Misc.scala:38:9]
wire _state_req_needs_wb_r_T_24 = 1'h0; // @[Misc.scala:38:9]
wire _state_req_needs_wb_r_T_28 = 1'h0; // @[Misc.scala:38:9]
wire _state_r_T_26 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_29 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_32 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_35 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_38 = 1'h0; // @[Misc.scala:35:9]
wire io_resp_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31]
wire io_resp_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31]
wire io_resp_bits_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31]
wire _needs_wb_r_T_2 = 1'h0; // @[Metadata.scala:140:24]
wire _needs_wb_r_T_4 = 1'h0; // @[Metadata.scala:140:24]
wire _needs_wb_r_T_20 = 1'h0; // @[Misc.scala:38:9]
wire _needs_wb_r_T_24 = 1'h0; // @[Misc.scala:38:9]
wire _needs_wb_r_T_28 = 1'h0; // @[Misc.scala:38:9]
wire _r_T_90 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_93 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_96 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_99 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_102 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_149 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_152 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_155 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_158 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_161 = 1'h0; // @[Misc.scala:35:9]
wire _state_req_needs_wb_r_T_66 = 1'h0; // @[Metadata.scala:140:24]
wire _state_req_needs_wb_r_T_68 = 1'h0; // @[Metadata.scala:140:24]
wire _state_req_needs_wb_r_T_84 = 1'h0; // @[Misc.scala:38:9]
wire _state_req_needs_wb_r_T_88 = 1'h0; // @[Misc.scala:38:9]
wire _state_req_needs_wb_r_T_92 = 1'h0; // @[Misc.scala:38:9]
wire _state_r_T_85 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_88 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_91 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_94 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_97 = 1'h0; // @[Misc.scala:35:9]
wire [33:0] io_brupdate_b2_uop_debug_pc = 34'h0; // @[mshrs.scala:36:7]
wire [33:0] io_brupdate_b2_jalr_target = 34'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_br_tag = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_op1_sel = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_mem_size = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_fp_typ = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_pc_sel = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] new_coh_meta_state = 2'h0; // @[Metadata.scala:160:20]
wire [1:0] _r_T_22 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_26 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_30 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_34 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_38 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _grow_param_r_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _grow_param_r_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _grow_param_r_T_5 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _grow_param_r_T_15 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _coh_on_grant_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _coh_on_grant_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r1_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r1_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r1_T_5 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r1_T_15 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r2_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r2_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r2_T_5 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r2_T_15 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_req_needs_wb_r_T_22 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_26 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_30 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_34 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_38 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_r_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_5 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_15 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] state_new_coh_meta_state = 2'h0; // @[Metadata.scala:160:20]
wire [1:0] _needs_wb_r_T_22 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _needs_wb_r_T_26 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _needs_wb_r_T_30 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _needs_wb_r_T_34 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _needs_wb_r_T_38 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_65 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_67 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_69 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_79 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_124 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_126 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_128 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_138 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] new_coh_meta_1_state = 2'h0; // @[Metadata.scala:160:20]
wire [1:0] _state_req_needs_wb_r_T_86 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_90 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_94 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_98 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_102 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_r_T_60 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_62 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_64 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_74 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] state_new_coh_meta_1_state = 2'h0; // @[Metadata.scala:160:20]
wire [5:0] io_brupdate_b2_uop_pc_lob = 6'h0; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_pdst = 6'h0; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_prs1 = 6'h0; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_prs2 = 6'h0; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_prs3 = 6'h0; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_stale_pdst = 6'h0; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_ldst = 6'h0; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_lrs1 = 6'h0; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_lrs2 = 6'h0; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_lrs3 = 6'h0; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_uop_imm_sel = 3'h0; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_uop_op2_sel = 3'h0; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_uop_csr_cmd = 3'h0; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_uop_fp_rm = 3'h0; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_uop_debug_fsrc = 3'h0; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_uop_debug_tsrc = 3'h0; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_cfi_type = 3'h0; // @[mshrs.scala:36:7]
wire [4:0] io_brupdate_b2_uop_pimm = 5'h0; // @[mshrs.scala:36:7]
wire [4:0] io_brupdate_b2_uop_rob_idx = 5'h0; // @[mshrs.scala:36:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd = 5'h0; // @[mshrs.scala:36:7]
wire [4:0] io_brupdate_b2_uop_fcn_op = 5'h0; // @[mshrs.scala:36:7]
wire [19:0] io_brupdate_b2_uop_imm_packed = 20'h0; // @[mshrs.scala:36:7]
wire [63:0] io_brupdate_b2_uop_exc_cause = 64'h0; // @[mshrs.scala:36:7]
wire [63:0] io_mem_acquire_bits_data = 64'h0; // @[mshrs.scala:36:7]
wire [63:0] io_mem_acquire_bits_a_data = 64'h0; // @[Edges.scala:346:17]
wire [20:0] io_brupdate_b2_target_offset = 21'h0; // @[mshrs.scala:36:7]
wire [3:0] io_mem_acquire_bits_size = 4'h6; // @[mshrs.scala:36:7]
wire [3:0] io_mem_acquire_bits_source = 4'h6; // @[mshrs.scala:36:7]
wire [3:0] io_wb_req_bits_source = 4'h6; // @[mshrs.scala:36:7]
wire [3:0] _r_T_12 = 4'h6; // @[Metadata.scala:127:10]
wire [3:0] _grow_param_r_T_10 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _r1_T_10 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _r2_T_10 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] io_mem_acquire_bits_a_size = 4'h6; // @[Edges.scala:346:17]
wire [3:0] io_mem_acquire_bits_a_source = 4'h6; // @[Edges.scala:346:17]
wire [3:0] _state_req_needs_wb_r_T_12 = 4'h6; // @[Metadata.scala:127:10]
wire [3:0] _state_r_T_10 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _needs_wb_r_T_12 = 4'h6; // @[Metadata.scala:127:10]
wire [3:0] _r_T_74 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _r_T_133 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _state_req_needs_wb_r_T_76 = 4'h6; // @[Metadata.scala:127:10]
wire [3:0] _state_r_T_69 = 4'h6; // @[Metadata.scala:64:10]
wire [7:0] io_mem_acquire_bits_mask = 8'hFF; // @[mshrs.scala:36:7]
wire [7:0] io_mem_acquire_bits_a_mask = 8'hFF; // @[Edges.scala:346:17]
wire [7:0] _io_mem_acquire_bits_a_mask_T = 8'hFF; // @[Misc.scala:222:10]
wire io_refill_bits_wmask = 1'h1; // @[mshrs.scala:36:7]
wire io_wb_req_bits_voluntary = 1'h1; // @[mshrs.scala:36:7]
wire _r_T = 1'h1; // @[Metadata.scala:140:24]
wire _io_mem_acquire_bits_legal_T_7 = 1'h1; // @[Parameters.scala:91:44]
wire _io_mem_acquire_bits_legal_T_8 = 1'h1; // @[Parameters.scala:684:29]
wire io_mem_acquire_bits_a_mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21]
wire io_mem_acquire_bits_a_mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26]
wire io_mem_acquire_bits_a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_size = 1'h1; // @[Misc.scala:209:26]
wire io_mem_acquire_bits_a_mask_acc = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_4 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_5 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_6 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_7 = 1'h1; // @[Misc.scala:215:29]
wire _io_refill_bits_wmask_T = 1'h1; // @[mshrs.scala:174:28]
wire _state_req_needs_wb_r_T = 1'h1; // @[Metadata.scala:140:24]
wire _needs_wb_r_T = 1'h1; // @[Metadata.scala:140:24]
wire _state_req_needs_wb_r_T_64 = 1'h1; // @[Metadata.scala:140:24]
wire [3:0] _grow_param_r_T_24 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _coh_on_grant_T_8 = 4'hC; // @[Metadata.scala:89:10]
wire [3:0] _r1_T_24 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _r2_T_24 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _state_r_T_24 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _r_T_88 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _r_T_147 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _state_r_T_83 = 4'hC; // @[Metadata.scala:72:10]
wire [1:0] _grow_param_r_T_11 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _grow_param_r_T_13 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _grow_param_r_T_21 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _grow_param_r_T_23 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _coh_on_grant_T_7 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r1_T_11 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r1_T_13 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r1_T_21 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r1_T_23 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r2_T_11 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r2_T_13 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r2_T_21 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r2_T_23 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _dirties_T = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] io_mem_acquire_bits_a_mask_lo_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] io_mem_acquire_bits_a_mask_lo_hi = 2'h3; // @[Misc.scala:222:10]
wire [1:0] io_mem_acquire_bits_a_mask_hi_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] io_mem_acquire_bits_a_mask_hi_hi = 2'h3; // @[Misc.scala:222:10]
wire [1:0] _state_r_T_11 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_13 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_21 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_23 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_75 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_77 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_85 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_87 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_134 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_136 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_144 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_146 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_70 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_72 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_80 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_82 = 2'h3; // @[Metadata.scala:24:15]
wire [3:0] _grow_param_r_T_22 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _r1_T_22 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _r2_T_22 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _state_r_T_22 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _r_T_86 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _r_T_145 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _state_r_T_81 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _r_T_14 = 4'h4; // @[Metadata.scala:129:10]
wire [3:0] _grow_param_r_T_20 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _coh_on_grant_T_6 = 4'h4; // @[Metadata.scala:88:10]
wire [3:0] _r1_T_20 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _r2_T_20 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _io_mem_acquire_bits_a_mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12]
wire [3:0] _state_req_needs_wb_r_T_14 = 4'h4; // @[Metadata.scala:129:10]
wire [3:0] _state_r_T_20 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _needs_wb_r_T_14 = 4'h4; // @[Metadata.scala:129:10]
wire [3:0] _r_T_84 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _r_T_143 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _state_req_needs_wb_r_T_78 = 4'h4; // @[Metadata.scala:129:10]
wire [3:0] _state_r_T_79 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _r_T_13 = 4'h5; // @[Metadata.scala:128:10]
wire [3:0] _grow_param_r_T_18 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _r1_T_18 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _r2_T_18 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _state_req_needs_wb_r_T_13 = 4'h5; // @[Metadata.scala:128:10]
wire [3:0] _state_r_T_18 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _needs_wb_r_T_13 = 4'h5; // @[Metadata.scala:128:10]
wire [3:0] _r_T_82 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _r_T_141 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _state_req_needs_wb_r_T_77 = 4'h5; // @[Metadata.scala:128:10]
wire [3:0] _state_r_T_77 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _grow_param_r_T_14 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _r1_T_14 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _r2_T_14 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _state_r_T_14 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _r_T_78 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _r_T_137 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _state_r_T_73 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _grow_param_r_T_12 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _r1_T_12 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _r2_T_12 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] io_mem_acquire_bits_a_mask_lo = 4'hF; // @[Misc.scala:222:10]
wire [3:0] io_mem_acquire_bits_a_mask_hi = 4'hF; // @[Misc.scala:222:10]
wire [3:0] _state_r_T_12 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _r_T_76 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _r_T_135 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _state_r_T_71 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _r_T_11 = 4'h7; // @[Metadata.scala:126:10]
wire [3:0] _grow_param_r_T_8 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _r1_T_8 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _r2_T_8 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _state_req_needs_wb_r_T_11 = 4'h7; // @[Metadata.scala:126:10]
wire [3:0] _state_r_T_8 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _needs_wb_r_T_11 = 4'h7; // @[Metadata.scala:126:10]
wire [3:0] _r_T_72 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _r_T_131 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _state_req_needs_wb_r_T_75 = 4'h7; // @[Metadata.scala:126:10]
wire [3:0] _state_r_T_67 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _r_T_9 = 4'h1; // @[Metadata.scala:124:10]
wire [3:0] _grow_param_r_T_6 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _coh_on_grant_T_2 = 4'h1; // @[Metadata.scala:86:10]
wire [3:0] _r1_T_6 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _r2_T_6 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _state_req_needs_wb_r_T_9 = 4'h1; // @[Metadata.scala:124:10]
wire [3:0] _state_r_T_6 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _needs_wb_r_T_9 = 4'h1; // @[Metadata.scala:124:10]
wire [3:0] _r_T_70 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _r_T_129 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _state_req_needs_wb_r_T_73 = 4'h1; // @[Metadata.scala:124:10]
wire [3:0] _state_r_T_65 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _r_T_8 = 4'h2; // @[Metadata.scala:123:10]
wire [3:0] _grow_param_r_T_4 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _r1_T_4 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _r2_T_4 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _state_req_needs_wb_r_T_8 = 4'h2; // @[Metadata.scala:123:10]
wire [3:0] _state_r_T_4 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _needs_wb_r_T_8 = 4'h2; // @[Metadata.scala:123:10]
wire [3:0] _r_T_68 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _r_T_127 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _state_req_needs_wb_r_T_72 = 4'h2; // @[Metadata.scala:123:10]
wire [3:0] _state_r_T_63 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _r_T_7 = 4'h3; // @[Metadata.scala:122:10]
wire [3:0] _grow_param_r_T_2 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _r1_T_2 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _r2_T_2 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _state_req_needs_wb_r_T_7 = 4'h3; // @[Metadata.scala:122:10]
wire [3:0] _state_r_T_2 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _needs_wb_r_T_7 = 4'h3; // @[Metadata.scala:122:10]
wire [3:0] _r_T_66 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _r_T_125 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _state_req_needs_wb_r_T_71 = 4'h3; // @[Metadata.scala:122:10]
wire [3:0] _state_r_T_61 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _r_T_18 = 4'h8; // @[Metadata.scala:133:10]
wire [3:0] _state_req_needs_wb_r_T_18 = 4'h8; // @[Metadata.scala:133:10]
wire [3:0] _needs_wb_r_T_18 = 4'h8; // @[Metadata.scala:133:10]
wire [3:0] _state_req_needs_wb_r_T_82 = 4'h8; // @[Metadata.scala:133:10]
wire [3:0] _r_T_17 = 4'h9; // @[Metadata.scala:132:10]
wire [3:0] _state_req_needs_wb_r_T_17 = 4'h9; // @[Metadata.scala:132:10]
wire [3:0] _needs_wb_r_T_17 = 4'h9; // @[Metadata.scala:132:10]
wire [3:0] _state_req_needs_wb_r_T_81 = 4'h9; // @[Metadata.scala:132:10]
wire [3:0] _r_T_16 = 4'hA; // @[Metadata.scala:131:10]
wire [3:0] _state_req_needs_wb_r_T_16 = 4'hA; // @[Metadata.scala:131:10]
wire [3:0] _needs_wb_r_T_16 = 4'hA; // @[Metadata.scala:131:10]
wire [3:0] _state_req_needs_wb_r_T_80 = 4'hA; // @[Metadata.scala:131:10]
wire [3:0] _r_T_15 = 4'hB; // @[Metadata.scala:130:10]
wire [3:0] _state_req_needs_wb_r_T_15 = 4'hB; // @[Metadata.scala:130:10]
wire [3:0] _needs_wb_r_T_15 = 4'hB; // @[Metadata.scala:130:10]
wire [3:0] _state_req_needs_wb_r_T_79 = 4'hB; // @[Metadata.scala:130:10]
wire [1:0] _r_T_1 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _r_T_3 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _r_T_5 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] io_mem_acquire_bits_a_mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49]
wire [1:0] _state_req_needs_wb_r_T_1 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _state_req_needs_wb_r_T_3 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _state_req_needs_wb_r_T_5 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _needs_wb_r_T_1 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _needs_wb_r_T_3 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _needs_wb_r_T_5 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _state_req_needs_wb_r_T_65 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _state_req_needs_wb_r_T_67 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _state_req_needs_wb_r_T_69 = 2'h2; // @[Metadata.scala:140:24]
wire [6:0] _data_word_T = 7'h0; // @[mshrs.scala:274:32]
wire [2:0] io_mem_acquire_bits_a_mask_sizeOH = 3'h5; // @[Misc.scala:202:81]
wire [2:0] _io_mem_acquire_bits_a_mask_sizeOH_T_2 = 3'h4; // @[OneHot.scala:65:27]
wire [1:0] _grow_param_r_T_7 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _grow_param_r_T_9 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _grow_param_r_T_17 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _grow_param_r_T_19 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _coh_on_grant_T_5 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r1_T_7 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r1_T_9 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r1_T_17 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r1_T_19 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r2_T_7 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r2_T_9 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r2_T_17 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r2_T_19 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_7 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_9 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_17 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_19 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_71 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_73 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_81 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_83 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_130 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_132 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_140 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_142 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_66 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_68 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_76 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_78 = 2'h1; // @[Metadata.scala:25:15]
wire _io_req_sec_rdy_T; // @[mshrs.scala:163:37]
wire _io_idx_valid_T; // @[mshrs.scala:149:25]
wire [3:0] req_idx; // @[mshrs.scala:110:25]
wire _io_way_valid_T_3; // @[mshrs.scala:151:19]
wire _io_tag_valid_T; // @[mshrs.scala:150:25]
wire [23:0] req_tag; // @[mshrs.scala:111:26]
wire [2:0] io_mem_acquire_bits_a_param; // @[Edges.scala:346:17]
wire [31:0] io_mem_acquire_bits_a_address; // @[Edges.scala:346:17]
wire [2:0] grantack_bits_e_sink = io_mem_grant_bits_sink_0; // @[Edges.scala:451:17]
wire [63:0] io_lb_write_bits_data_0 = io_mem_grant_bits_data_0; // @[mshrs.scala:36:7]
wire [2:0] shrink_param; // @[Misc.scala:38:36]
wire [1:0] coh_on_grant_state; // @[Metadata.scala:160:20]
wire [63:0] io_refill_bits_data_0 = io_lb_resp_0; // @[mshrs.scala:36:7]
wire [63:0] data_word = io_lb_resp_0; // @[mshrs.scala:36:7, :274:26]
wire _io_probe_rdy_T_11; // @[mshrs.scala:148:42]
wire io_idx_valid_0; // @[mshrs.scala:36:7]
wire [3:0] io_idx_bits_0; // @[mshrs.scala:36:7]
wire io_way_valid_0; // @[mshrs.scala:36:7]
wire [1:0] io_way_bits_0; // @[mshrs.scala:36:7]
wire io_tag_valid_0; // @[mshrs.scala:36:7]
wire [23:0] io_tag_bits_0; // @[mshrs.scala:36:7]
wire [2:0] io_mem_acquire_bits_param_0; // @[mshrs.scala:36:7]
wire [31:0] io_mem_acquire_bits_address_0; // @[mshrs.scala:36:7]
wire io_mem_acquire_valid_0; // @[mshrs.scala:36:7]
wire io_mem_grant_ready_0; // @[mshrs.scala:36:7]
wire [2:0] io_mem_finish_bits_sink_0; // @[mshrs.scala:36:7]
wire io_mem_finish_valid_0; // @[mshrs.scala:36:7]
wire [1:0] io_refill_bits_way_en_0; // @[mshrs.scala:36:7]
wire [9:0] io_refill_bits_addr_0; // @[mshrs.scala:36:7]
wire io_refill_valid_0; // @[mshrs.scala:36:7]
wire [1:0] io_meta_write_bits_data_coh_state_0; // @[mshrs.scala:36:7]
wire [21:0] io_meta_write_bits_data_tag_0; // @[mshrs.scala:36:7]
wire [3:0] io_meta_write_bits_idx_0; // @[mshrs.scala:36:7]
wire [1:0] io_meta_write_bits_way_en_0; // @[mshrs.scala:36:7]
wire [21:0] io_meta_write_bits_tag_0; // @[mshrs.scala:36:7]
wire io_meta_write_valid_0; // @[mshrs.scala:36:7]
wire [3:0] io_meta_read_bits_idx_0; // @[mshrs.scala:36:7]
wire [1:0] io_meta_read_bits_way_en_0; // @[mshrs.scala:36:7]
wire [21:0] io_meta_read_bits_tag_0; // @[mshrs.scala:36:7]
wire io_meta_read_valid_0; // @[mshrs.scala:36:7]
wire [21:0] io_wb_req_bits_tag_0; // @[mshrs.scala:36:7]
wire [3:0] io_wb_req_bits_idx_0; // @[mshrs.scala:36:7]
wire [2:0] io_wb_req_bits_param_0; // @[mshrs.scala:36:7]
wire [1:0] io_wb_req_bits_way_en_0; // @[mshrs.scala:36:7]
wire io_wb_req_valid_0; // @[mshrs.scala:36:7]
wire [1:0] io_commit_coh_state_0; // @[mshrs.scala:36:7]
wire [2:0] io_lb_read_offset_0; // @[mshrs.scala:36:7]
wire [2:0] io_lb_write_bits_offset_0; // @[mshrs.scala:36:7]
wire io_lb_write_valid_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_iq_type_0_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_iq_type_1_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_iq_type_2_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_iq_type_3_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fu_code_0_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fu_code_1_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fu_code_2_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fu_code_3_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fu_code_4_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fu_code_5_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fu_code_6_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fu_code_7_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fu_code_8_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fu_code_9_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fp_ctrl_ldst_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fp_ctrl_wen_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fp_ctrl_ren1_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fp_ctrl_ren2_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fp_ctrl_ren3_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fp_ctrl_swap12_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fp_ctrl_swap23_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_fp_ctrl_typeTagIn_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_fp_ctrl_typeTagOut_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fp_ctrl_fromint_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fp_ctrl_toint_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fp_ctrl_fastpipe_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fp_ctrl_fma_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fp_ctrl_div_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fp_ctrl_sqrt_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fp_ctrl_wflags_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fp_ctrl_vec_0; // @[mshrs.scala:36:7]
wire [31:0] io_replay_bits_uop_inst_0; // @[mshrs.scala:36:7]
wire [31:0] io_replay_bits_uop_debug_inst_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_rvc_0; // @[mshrs.scala:36:7]
wire [33:0] io_replay_bits_uop_debug_pc_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_iw_issued_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_iw_issued_partial_agen_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_iw_issued_partial_dgen_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_iw_p1_speculative_child_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_iw_p2_speculative_child_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_iw_p1_bypass_hint_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_iw_p2_bypass_hint_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_iw_p3_bypass_hint_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_dis_col_sel_0; // @[mshrs.scala:36:7]
wire [3:0] io_replay_bits_uop_br_mask_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_br_tag_0; // @[mshrs.scala:36:7]
wire [3:0] io_replay_bits_uop_br_type_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_sfb_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_fence_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_fencei_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_sfence_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_amo_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_eret_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_rocc_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_mov_0; // @[mshrs.scala:36:7]
wire [3:0] io_replay_bits_uop_ftq_idx_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_edge_inst_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_pc_lob_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_taken_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_imm_rename_0; // @[mshrs.scala:36:7]
wire [2:0] io_replay_bits_uop_imm_sel_0; // @[mshrs.scala:36:7]
wire [4:0] io_replay_bits_uop_pimm_0; // @[mshrs.scala:36:7]
wire [19:0] io_replay_bits_uop_imm_packed_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_op1_sel_0; // @[mshrs.scala:36:7]
wire [2:0] io_replay_bits_uop_op2_sel_0; // @[mshrs.scala:36:7]
wire [4:0] io_replay_bits_uop_rob_idx_0; // @[mshrs.scala:36:7]
wire [3:0] io_replay_bits_uop_ldq_idx_0; // @[mshrs.scala:36:7]
wire [3:0] io_replay_bits_uop_stq_idx_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_rxq_idx_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_pdst_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_prs1_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_prs2_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_prs3_0; // @[mshrs.scala:36:7]
wire [3:0] io_replay_bits_uop_ppred_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_prs1_busy_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_prs2_busy_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_prs3_busy_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ppred_busy_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_stale_pdst_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_exception_0; // @[mshrs.scala:36:7]
wire [63:0] io_replay_bits_uop_exc_cause_0; // @[mshrs.scala:36:7]
wire [4:0] io_replay_bits_uop_mem_cmd_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_mem_size_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_mem_signed_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_uses_ldq_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_uses_stq_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_unique_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_flush_on_commit_0; // @[mshrs.scala:36:7]
wire [2:0] io_replay_bits_uop_csr_cmd_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_ldst_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_lrs1_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_lrs2_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_lrs3_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_dst_rtype_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_lrs1_rtype_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_lrs2_rtype_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_frs3_en_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fcn_dw_0; // @[mshrs.scala:36:7]
wire [4:0] io_replay_bits_uop_fcn_op_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fp_val_0; // @[mshrs.scala:36:7]
wire [2:0] io_replay_bits_uop_fp_rm_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_fp_typ_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_bp_debug_if_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:36:7]
wire [2:0] io_replay_bits_uop_debug_fsrc_0; // @[mshrs.scala:36:7]
wire [2:0] io_replay_bits_uop_debug_tsrc_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_old_meta_coh_state_0; // @[mshrs.scala:36:7]
wire [21:0] io_replay_bits_old_meta_tag_0; // @[mshrs.scala:36:7]
wire [33:0] io_replay_bits_addr_0; // @[mshrs.scala:36:7]
wire [63:0] io_replay_bits_data_0; // @[mshrs.scala:36:7]
wire io_replay_bits_is_hella_0; // @[mshrs.scala:36:7]
wire io_replay_bits_tag_match_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_way_en_0; // @[mshrs.scala:36:7]
wire [4:0] io_replay_bits_sdq_id_0; // @[mshrs.scala:36:7]
wire io_replay_valid_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_iq_type_0_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_iq_type_1_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_iq_type_2_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_iq_type_3_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fu_code_0_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fu_code_1_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fu_code_2_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fu_code_3_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fu_code_4_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fu_code_5_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fu_code_6_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fu_code_7_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fu_code_8_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fu_code_9_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fp_ctrl_ldst_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fp_ctrl_wen_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fp_ctrl_ren1_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fp_ctrl_ren2_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fp_ctrl_ren3_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fp_ctrl_swap12_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fp_ctrl_swap23_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_fp_ctrl_typeTagIn_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_fp_ctrl_typeTagOut_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fp_ctrl_fromint_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fp_ctrl_toint_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fp_ctrl_fastpipe_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fp_ctrl_fma_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fp_ctrl_div_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fp_ctrl_sqrt_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fp_ctrl_wflags_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fp_ctrl_vec_0; // @[mshrs.scala:36:7]
wire [31:0] io_resp_bits_uop_inst_0; // @[mshrs.scala:36:7]
wire [31:0] io_resp_bits_uop_debug_inst_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_rvc_0; // @[mshrs.scala:36:7]
wire [33:0] io_resp_bits_uop_debug_pc_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_iw_issued_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_iw_issued_partial_agen_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_iw_issued_partial_dgen_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_iw_p1_speculative_child_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_iw_p2_speculative_child_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_iw_p1_bypass_hint_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_iw_p2_bypass_hint_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_iw_p3_bypass_hint_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_dis_col_sel_0; // @[mshrs.scala:36:7]
wire [3:0] io_resp_bits_uop_br_mask_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_br_tag_0; // @[mshrs.scala:36:7]
wire [3:0] io_resp_bits_uop_br_type_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_sfb_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_fence_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_fencei_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_sfence_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_amo_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_eret_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_rocc_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_mov_0; // @[mshrs.scala:36:7]
wire [3:0] io_resp_bits_uop_ftq_idx_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_edge_inst_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_pc_lob_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_taken_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_imm_rename_0; // @[mshrs.scala:36:7]
wire [2:0] io_resp_bits_uop_imm_sel_0; // @[mshrs.scala:36:7]
wire [4:0] io_resp_bits_uop_pimm_0; // @[mshrs.scala:36:7]
wire [19:0] io_resp_bits_uop_imm_packed_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_op1_sel_0; // @[mshrs.scala:36:7]
wire [2:0] io_resp_bits_uop_op2_sel_0; // @[mshrs.scala:36:7]
wire [4:0] io_resp_bits_uop_rob_idx_0; // @[mshrs.scala:36:7]
wire [3:0] io_resp_bits_uop_ldq_idx_0; // @[mshrs.scala:36:7]
wire [3:0] io_resp_bits_uop_stq_idx_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_rxq_idx_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_pdst_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_prs1_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_prs2_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_prs3_0; // @[mshrs.scala:36:7]
wire [3:0] io_resp_bits_uop_ppred_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_prs1_busy_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_prs2_busy_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_prs3_busy_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ppred_busy_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_stale_pdst_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_exception_0; // @[mshrs.scala:36:7]
wire [63:0] io_resp_bits_uop_exc_cause_0; // @[mshrs.scala:36:7]
wire [4:0] io_resp_bits_uop_mem_cmd_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_mem_size_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_mem_signed_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_uses_ldq_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_uses_stq_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_unique_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_flush_on_commit_0; // @[mshrs.scala:36:7]
wire [2:0] io_resp_bits_uop_csr_cmd_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_ldst_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_lrs1_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_lrs2_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_lrs3_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_dst_rtype_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_lrs1_rtype_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_lrs2_rtype_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_frs3_en_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fcn_dw_0; // @[mshrs.scala:36:7]
wire [4:0] io_resp_bits_uop_fcn_op_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fp_val_0; // @[mshrs.scala:36:7]
wire [2:0] io_resp_bits_uop_fp_rm_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_fp_typ_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_bp_debug_if_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:36:7]
wire [2:0] io_resp_bits_uop_debug_fsrc_0; // @[mshrs.scala:36:7]
wire [2:0] io_resp_bits_uop_debug_tsrc_0; // @[mshrs.scala:36:7]
wire [63:0] io_resp_bits_data_0; // @[mshrs.scala:36:7]
wire io_resp_bits_is_hella_0; // @[mshrs.scala:36:7]
wire io_resp_valid_0; // @[mshrs.scala:36:7]
wire io_req_pri_rdy_0; // @[mshrs.scala:36:7]
wire io_req_sec_rdy_0; // @[mshrs.scala:36:7]
wire io_commit_val_0; // @[mshrs.scala:36:7]
wire [33:0] io_commit_addr_0; // @[mshrs.scala:36:7]
wire io_probe_rdy_0; // @[mshrs.scala:36:7]
reg [4:0] state; // @[mshrs.scala:107:22]
reg [31:0] req_uop_inst; // @[mshrs.scala:109:20]
reg [31:0] req_uop_debug_inst; // @[mshrs.scala:109:20]
reg req_uop_is_rvc; // @[mshrs.scala:109:20]
reg [33:0] req_uop_debug_pc; // @[mshrs.scala:109:20]
reg req_uop_iq_type_0; // @[mshrs.scala:109:20]
reg req_uop_iq_type_1; // @[mshrs.scala:109:20]
reg req_uop_iq_type_2; // @[mshrs.scala:109:20]
reg req_uop_iq_type_3; // @[mshrs.scala:109:20]
reg req_uop_fu_code_0; // @[mshrs.scala:109:20]
reg req_uop_fu_code_1; // @[mshrs.scala:109:20]
reg req_uop_fu_code_2; // @[mshrs.scala:109:20]
reg req_uop_fu_code_3; // @[mshrs.scala:109:20]
reg req_uop_fu_code_4; // @[mshrs.scala:109:20]
reg req_uop_fu_code_5; // @[mshrs.scala:109:20]
reg req_uop_fu_code_6; // @[mshrs.scala:109:20]
reg req_uop_fu_code_7; // @[mshrs.scala:109:20]
reg req_uop_fu_code_8; // @[mshrs.scala:109:20]
reg req_uop_fu_code_9; // @[mshrs.scala:109:20]
reg req_uop_iw_issued; // @[mshrs.scala:109:20]
reg req_uop_iw_issued_partial_agen; // @[mshrs.scala:109:20]
reg req_uop_iw_issued_partial_dgen; // @[mshrs.scala:109:20]
reg req_uop_iw_p1_speculative_child; // @[mshrs.scala:109:20]
reg req_uop_iw_p2_speculative_child; // @[mshrs.scala:109:20]
reg req_uop_iw_p1_bypass_hint; // @[mshrs.scala:109:20]
reg req_uop_iw_p2_bypass_hint; // @[mshrs.scala:109:20]
reg req_uop_iw_p3_bypass_hint; // @[mshrs.scala:109:20]
reg req_uop_dis_col_sel; // @[mshrs.scala:109:20]
reg [3:0] req_uop_br_mask; // @[mshrs.scala:109:20]
reg [1:0] req_uop_br_tag; // @[mshrs.scala:109:20]
reg [3:0] req_uop_br_type; // @[mshrs.scala:109:20]
reg req_uop_is_sfb; // @[mshrs.scala:109:20]
reg req_uop_is_fence; // @[mshrs.scala:109:20]
reg req_uop_is_fencei; // @[mshrs.scala:109:20]
reg req_uop_is_sfence; // @[mshrs.scala:109:20]
reg req_uop_is_amo; // @[mshrs.scala:109:20]
reg req_uop_is_eret; // @[mshrs.scala:109:20]
reg req_uop_is_sys_pc2epc; // @[mshrs.scala:109:20]
reg req_uop_is_rocc; // @[mshrs.scala:109:20]
reg req_uop_is_mov; // @[mshrs.scala:109:20]
reg [3:0] req_uop_ftq_idx; // @[mshrs.scala:109:20]
reg req_uop_edge_inst; // @[mshrs.scala:109:20]
reg [5:0] req_uop_pc_lob; // @[mshrs.scala:109:20]
reg req_uop_taken; // @[mshrs.scala:109:20]
reg req_uop_imm_rename; // @[mshrs.scala:109:20]
reg [2:0] req_uop_imm_sel; // @[mshrs.scala:109:20]
reg [4:0] req_uop_pimm; // @[mshrs.scala:109:20]
reg [19:0] req_uop_imm_packed; // @[mshrs.scala:109:20]
reg [1:0] req_uop_op1_sel; // @[mshrs.scala:109:20]
reg [2:0] req_uop_op2_sel; // @[mshrs.scala:109:20]
reg req_uop_fp_ctrl_ldst; // @[mshrs.scala:109:20]
reg req_uop_fp_ctrl_wen; // @[mshrs.scala:109:20]
reg req_uop_fp_ctrl_ren1; // @[mshrs.scala:109:20]
reg req_uop_fp_ctrl_ren2; // @[mshrs.scala:109:20]
reg req_uop_fp_ctrl_ren3; // @[mshrs.scala:109:20]
reg req_uop_fp_ctrl_swap12; // @[mshrs.scala:109:20]
reg req_uop_fp_ctrl_swap23; // @[mshrs.scala:109:20]
reg [1:0] req_uop_fp_ctrl_typeTagIn; // @[mshrs.scala:109:20]
reg [1:0] req_uop_fp_ctrl_typeTagOut; // @[mshrs.scala:109:20]
reg req_uop_fp_ctrl_fromint; // @[mshrs.scala:109:20]
reg req_uop_fp_ctrl_toint; // @[mshrs.scala:109:20]
reg req_uop_fp_ctrl_fastpipe; // @[mshrs.scala:109:20]
reg req_uop_fp_ctrl_fma; // @[mshrs.scala:109:20]
reg req_uop_fp_ctrl_div; // @[mshrs.scala:109:20]
reg req_uop_fp_ctrl_sqrt; // @[mshrs.scala:109:20]
reg req_uop_fp_ctrl_wflags; // @[mshrs.scala:109:20]
reg req_uop_fp_ctrl_vec; // @[mshrs.scala:109:20]
reg [4:0] req_uop_rob_idx; // @[mshrs.scala:109:20]
reg [3:0] req_uop_ldq_idx; // @[mshrs.scala:109:20]
reg [3:0] req_uop_stq_idx; // @[mshrs.scala:109:20]
reg [1:0] req_uop_rxq_idx; // @[mshrs.scala:109:20]
reg [5:0] req_uop_pdst; // @[mshrs.scala:109:20]
reg [5:0] req_uop_prs1; // @[mshrs.scala:109:20]
reg [5:0] req_uop_prs2; // @[mshrs.scala:109:20]
reg [5:0] req_uop_prs3; // @[mshrs.scala:109:20]
reg [3:0] req_uop_ppred; // @[mshrs.scala:109:20]
reg req_uop_prs1_busy; // @[mshrs.scala:109:20]
reg req_uop_prs2_busy; // @[mshrs.scala:109:20]
reg req_uop_prs3_busy; // @[mshrs.scala:109:20]
reg req_uop_ppred_busy; // @[mshrs.scala:109:20]
reg [5:0] req_uop_stale_pdst; // @[mshrs.scala:109:20]
reg req_uop_exception; // @[mshrs.scala:109:20]
reg [63:0] req_uop_exc_cause; // @[mshrs.scala:109:20]
reg [4:0] req_uop_mem_cmd; // @[mshrs.scala:109:20]
reg [1:0] req_uop_mem_size; // @[mshrs.scala:109:20]
reg req_uop_mem_signed; // @[mshrs.scala:109:20]
reg req_uop_uses_ldq; // @[mshrs.scala:109:20]
reg req_uop_uses_stq; // @[mshrs.scala:109:20]
reg req_uop_is_unique; // @[mshrs.scala:109:20]
reg req_uop_flush_on_commit; // @[mshrs.scala:109:20]
reg [2:0] req_uop_csr_cmd; // @[mshrs.scala:109:20]
reg req_uop_ldst_is_rs1; // @[mshrs.scala:109:20]
reg [5:0] req_uop_ldst; // @[mshrs.scala:109:20]
reg [5:0] req_uop_lrs1; // @[mshrs.scala:109:20]
reg [5:0] req_uop_lrs2; // @[mshrs.scala:109:20]
reg [5:0] req_uop_lrs3; // @[mshrs.scala:109:20]
reg [1:0] req_uop_dst_rtype; // @[mshrs.scala:109:20]
reg [1:0] req_uop_lrs1_rtype; // @[mshrs.scala:109:20]
reg [1:0] req_uop_lrs2_rtype; // @[mshrs.scala:109:20]
reg req_uop_frs3_en; // @[mshrs.scala:109:20]
reg req_uop_fcn_dw; // @[mshrs.scala:109:20]
reg [4:0] req_uop_fcn_op; // @[mshrs.scala:109:20]
reg req_uop_fp_val; // @[mshrs.scala:109:20]
reg [2:0] req_uop_fp_rm; // @[mshrs.scala:109:20]
reg [1:0] req_uop_fp_typ; // @[mshrs.scala:109:20]
reg req_uop_xcpt_pf_if; // @[mshrs.scala:109:20]
reg req_uop_xcpt_ae_if; // @[mshrs.scala:109:20]
reg req_uop_xcpt_ma_if; // @[mshrs.scala:109:20]
reg req_uop_bp_debug_if; // @[mshrs.scala:109:20]
reg req_uop_bp_xcpt_if; // @[mshrs.scala:109:20]
reg [2:0] req_uop_debug_fsrc; // @[mshrs.scala:109:20]
reg [2:0] req_uop_debug_tsrc; // @[mshrs.scala:109:20]
reg [33:0] req_addr; // @[mshrs.scala:109:20]
assign io_commit_addr_0 = req_addr; // @[mshrs.scala:36:7, :109:20]
reg [63:0] req_data; // @[mshrs.scala:109:20]
reg req_is_hella; // @[mshrs.scala:109:20]
reg req_tag_match; // @[mshrs.scala:109:20]
reg [1:0] req_old_meta_coh_state; // @[mshrs.scala:109:20]
reg [21:0] req_old_meta_tag; // @[mshrs.scala:109:20]
assign io_wb_req_bits_tag_0 = req_old_meta_tag; // @[mshrs.scala:36:7, :109:20]
reg [1:0] req_way_en; // @[mshrs.scala:109:20]
assign io_way_bits_0 = req_way_en; // @[mshrs.scala:36:7, :109:20]
assign io_refill_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20]
assign io_meta_write_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20]
assign io_meta_read_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20]
assign io_wb_req_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20]
reg [4:0] req_sdq_id; // @[mshrs.scala:109:20]
assign req_idx = req_addr[9:6]; // @[mshrs.scala:109:20, :110:25]
assign io_idx_bits_0 = req_idx; // @[mshrs.scala:36:7, :110:25]
assign io_meta_write_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25]
assign io_meta_read_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25]
assign io_wb_req_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25]
assign req_tag = req_addr[33:10]; // @[mshrs.scala:109:20, :111:26]
assign io_tag_bits_0 = req_tag; // @[mshrs.scala:36:7, :111:26]
wire [27:0] _req_block_addr_T = req_addr[33:6]; // @[mshrs.scala:109:20, :112:34]
wire [33:0] req_block_addr = {_req_block_addr_T, 6'h0}; // @[mshrs.scala:112:{34,51}]
reg req_needs_wb; // @[mshrs.scala:113:29]
reg [1:0] new_coh_state; // @[mshrs.scala:115:24]
wire [3:0] _r_T_6 = {2'h2, req_old_meta_coh_state}; // @[Metadata.scala:120:19]
wire _r_T_19 = _r_T_6 == 4'h8; // @[Misc.scala:56:20]
wire [2:0] _r_T_21 = _r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20]
wire _r_T_23 = _r_T_6 == 4'h9; // @[Misc.scala:56:20]
wire [2:0] _r_T_25 = _r_T_23 ? 3'h2 : _r_T_21; // @[Misc.scala:38:36, :56:20]
wire _r_T_27 = _r_T_6 == 4'hA; // @[Misc.scala:56:20]
wire [2:0] _r_T_29 = _r_T_27 ? 3'h1 : _r_T_25; // @[Misc.scala:38:36, :56:20]
wire _r_T_31 = _r_T_6 == 4'hB; // @[Misc.scala:56:20]
wire _r_T_32 = _r_T_31; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_33 = _r_T_31 ? 3'h1 : _r_T_29; // @[Misc.scala:38:36, :56:20]
wire _r_T_35 = _r_T_6 == 4'h4; // @[Misc.scala:56:20]
wire _r_T_36 = ~_r_T_35 & _r_T_32; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_37 = _r_T_35 ? 3'h5 : _r_T_33; // @[Misc.scala:38:36, :56:20]
wire _r_T_39 = _r_T_6 == 4'h5; // @[Misc.scala:56:20]
wire _r_T_40 = ~_r_T_39 & _r_T_36; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_41 = _r_T_39 ? 3'h4 : _r_T_37; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_42 = {1'h0, _r_T_39}; // @[Misc.scala:38:63, :56:20]
wire _r_T_43 = _r_T_6 == 4'h6; // @[Misc.scala:56:20]
wire _r_T_44 = ~_r_T_43 & _r_T_40; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_45 = _r_T_43 ? 3'h0 : _r_T_41; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_46 = _r_T_43 ? 2'h1 : _r_T_42; // @[Misc.scala:38:63, :56:20]
wire _r_T_47 = _r_T_6 == 4'h7; // @[Misc.scala:56:20]
wire _r_T_48 = _r_T_47 | _r_T_44; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_49 = _r_T_47 ? 3'h0 : _r_T_45; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_50 = _r_T_47 ? 2'h1 : _r_T_46; // @[Misc.scala:38:63, :56:20]
wire _r_T_51 = _r_T_6 == 4'h0; // @[Misc.scala:56:20]
wire _r_T_52 = ~_r_T_51 & _r_T_48; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_53 = _r_T_51 ? 3'h5 : _r_T_49; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_54 = _r_T_51 ? 2'h0 : _r_T_50; // @[Misc.scala:38:63, :56:20]
wire _r_T_55 = _r_T_6 == 4'h1; // @[Misc.scala:56:20]
wire _r_T_56 = ~_r_T_55 & _r_T_52; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_57 = _r_T_55 ? 3'h4 : _r_T_53; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_58 = _r_T_55 ? 2'h1 : _r_T_54; // @[Misc.scala:38:63, :56:20]
wire _r_T_59 = _r_T_6 == 4'h2; // @[Misc.scala:56:20]
wire _r_T_60 = ~_r_T_59 & _r_T_56; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_61 = _r_T_59 ? 3'h3 : _r_T_57; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_62 = _r_T_59 ? 2'h2 : _r_T_58; // @[Misc.scala:38:63, :56:20]
wire _r_T_63 = _r_T_6 == 4'h3; // @[Misc.scala:56:20]
wire r_1 = _r_T_63 | _r_T_60; // @[Misc.scala:38:9, :56:20]
assign shrink_param = _r_T_63 ? 3'h3 : _r_T_61; // @[Misc.scala:38:36, :56:20]
assign io_wb_req_bits_param_0 = shrink_param; // @[Misc.scala:38:36]
wire [1:0] r_3 = _r_T_63 ? 2'h2 : _r_T_62; // @[Misc.scala:38:63, :56:20]
wire [1:0] coh_on_clear_state = r_3; // @[Misc.scala:38:63]
wire _GEN = req_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32]
wire _grow_param_r_c_cat_T; // @[Consts.scala:90:32]
assign _grow_param_r_c_cat_T = _GEN; // @[Consts.scala:90:32]
wire _grow_param_r_c_cat_T_23; // @[Consts.scala:90:32]
assign _grow_param_r_c_cat_T_23 = _GEN; // @[Consts.scala:90:32]
wire _coh_on_grant_c_cat_T; // @[Consts.scala:90:32]
assign _coh_on_grant_c_cat_T = _GEN; // @[Consts.scala:90:32]
wire _coh_on_grant_c_cat_T_23; // @[Consts.scala:90:32]
assign _coh_on_grant_c_cat_T_23 = _GEN; // @[Consts.scala:90:32]
wire _r1_c_cat_T; // @[Consts.scala:90:32]
assign _r1_c_cat_T = _GEN; // @[Consts.scala:90:32]
wire _r1_c_cat_T_23; // @[Consts.scala:90:32]
assign _r1_c_cat_T_23 = _GEN; // @[Consts.scala:90:32]
wire _needs_second_acq_T_27; // @[Consts.scala:90:32]
assign _needs_second_acq_T_27 = _GEN; // @[Consts.scala:90:32]
wire _GEN_0 = req_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49]
wire _grow_param_r_c_cat_T_1; // @[Consts.scala:90:49]
assign _grow_param_r_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49]
wire _grow_param_r_c_cat_T_24; // @[Consts.scala:90:49]
assign _grow_param_r_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49]
wire _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:49]
assign _coh_on_grant_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49]
wire _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:49]
assign _coh_on_grant_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49]
wire _r1_c_cat_T_1; // @[Consts.scala:90:49]
assign _r1_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49]
wire _r1_c_cat_T_24; // @[Consts.scala:90:49]
assign _r1_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49]
wire _needs_second_acq_T_28; // @[Consts.scala:90:49]
assign _needs_second_acq_T_28 = _GEN_0; // @[Consts.scala:90:49]
wire _grow_param_r_c_cat_T_2 = _grow_param_r_c_cat_T | _grow_param_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _GEN_1 = req_uop_mem_cmd == 5'h7; // @[Consts.scala:90:66]
wire _grow_param_r_c_cat_T_3; // @[Consts.scala:90:66]
assign _grow_param_r_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66]
wire _grow_param_r_c_cat_T_26; // @[Consts.scala:90:66]
assign _grow_param_r_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66]
wire _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:66]
assign _coh_on_grant_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66]
wire _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:66]
assign _coh_on_grant_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66]
wire _r1_c_cat_T_3; // @[Consts.scala:90:66]
assign _r1_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66]
wire _r1_c_cat_T_26; // @[Consts.scala:90:66]
assign _r1_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66]
wire _needs_second_acq_T_30; // @[Consts.scala:90:66]
assign _needs_second_acq_T_30 = _GEN_1; // @[Consts.scala:90:66]
wire _grow_param_r_c_cat_T_4 = _grow_param_r_c_cat_T_2 | _grow_param_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _GEN_2 = req_uop_mem_cmd == 5'h4; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_5; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_5 = _GEN_2; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_28; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_28 = _GEN_2; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_5; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_5 = _GEN_2; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_28; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_28 = _GEN_2; // @[package.scala:16:47]
wire _r1_c_cat_T_5; // @[package.scala:16:47]
assign _r1_c_cat_T_5 = _GEN_2; // @[package.scala:16:47]
wire _r1_c_cat_T_28; // @[package.scala:16:47]
assign _r1_c_cat_T_28 = _GEN_2; // @[package.scala:16:47]
wire _needs_second_acq_T_32; // @[package.scala:16:47]
assign _needs_second_acq_T_32 = _GEN_2; // @[package.scala:16:47]
wire _GEN_3 = req_uop_mem_cmd == 5'h9; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_6; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_6 = _GEN_3; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_29; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_29 = _GEN_3; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_6; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_6 = _GEN_3; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_29; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_29 = _GEN_3; // @[package.scala:16:47]
wire _r1_c_cat_T_6; // @[package.scala:16:47]
assign _r1_c_cat_T_6 = _GEN_3; // @[package.scala:16:47]
wire _r1_c_cat_T_29; // @[package.scala:16:47]
assign _r1_c_cat_T_29 = _GEN_3; // @[package.scala:16:47]
wire _needs_second_acq_T_33; // @[package.scala:16:47]
assign _needs_second_acq_T_33 = _GEN_3; // @[package.scala:16:47]
wire _GEN_4 = req_uop_mem_cmd == 5'hA; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_7; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_7 = _GEN_4; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_30; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_30 = _GEN_4; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_7; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_7 = _GEN_4; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_30; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_30 = _GEN_4; // @[package.scala:16:47]
wire _r1_c_cat_T_7; // @[package.scala:16:47]
assign _r1_c_cat_T_7 = _GEN_4; // @[package.scala:16:47]
wire _r1_c_cat_T_30; // @[package.scala:16:47]
assign _r1_c_cat_T_30 = _GEN_4; // @[package.scala:16:47]
wire _needs_second_acq_T_34; // @[package.scala:16:47]
assign _needs_second_acq_T_34 = _GEN_4; // @[package.scala:16:47]
wire _GEN_5 = req_uop_mem_cmd == 5'hB; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_8; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_8 = _GEN_5; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_31; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_31 = _GEN_5; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_8; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_8 = _GEN_5; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_31; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_31 = _GEN_5; // @[package.scala:16:47]
wire _r1_c_cat_T_8; // @[package.scala:16:47]
assign _r1_c_cat_T_8 = _GEN_5; // @[package.scala:16:47]
wire _r1_c_cat_T_31; // @[package.scala:16:47]
assign _r1_c_cat_T_31 = _GEN_5; // @[package.scala:16:47]
wire _needs_second_acq_T_35; // @[package.scala:16:47]
assign _needs_second_acq_T_35 = _GEN_5; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_9 = _grow_param_r_c_cat_T_5 | _grow_param_r_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_10 = _grow_param_r_c_cat_T_9 | _grow_param_r_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_11 = _grow_param_r_c_cat_T_10 | _grow_param_r_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _GEN_6 = req_uop_mem_cmd == 5'h8; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_12; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_12 = _GEN_6; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_35; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_35 = _GEN_6; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_12; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_12 = _GEN_6; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_35; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_35 = _GEN_6; // @[package.scala:16:47]
wire _r1_c_cat_T_12; // @[package.scala:16:47]
assign _r1_c_cat_T_12 = _GEN_6; // @[package.scala:16:47]
wire _r1_c_cat_T_35; // @[package.scala:16:47]
assign _r1_c_cat_T_35 = _GEN_6; // @[package.scala:16:47]
wire _needs_second_acq_T_39; // @[package.scala:16:47]
assign _needs_second_acq_T_39 = _GEN_6; // @[package.scala:16:47]
wire _GEN_7 = req_uop_mem_cmd == 5'hC; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_13; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_13 = _GEN_7; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_36; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_36 = _GEN_7; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_13; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_13 = _GEN_7; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_36; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_36 = _GEN_7; // @[package.scala:16:47]
wire _r1_c_cat_T_13; // @[package.scala:16:47]
assign _r1_c_cat_T_13 = _GEN_7; // @[package.scala:16:47]
wire _r1_c_cat_T_36; // @[package.scala:16:47]
assign _r1_c_cat_T_36 = _GEN_7; // @[package.scala:16:47]
wire _needs_second_acq_T_40; // @[package.scala:16:47]
assign _needs_second_acq_T_40 = _GEN_7; // @[package.scala:16:47]
wire _GEN_8 = req_uop_mem_cmd == 5'hD; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_14; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_14 = _GEN_8; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_37; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_37 = _GEN_8; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_14; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_14 = _GEN_8; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_37; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_37 = _GEN_8; // @[package.scala:16:47]
wire _r1_c_cat_T_14; // @[package.scala:16:47]
assign _r1_c_cat_T_14 = _GEN_8; // @[package.scala:16:47]
wire _r1_c_cat_T_37; // @[package.scala:16:47]
assign _r1_c_cat_T_37 = _GEN_8; // @[package.scala:16:47]
wire _needs_second_acq_T_41; // @[package.scala:16:47]
assign _needs_second_acq_T_41 = _GEN_8; // @[package.scala:16:47]
wire _GEN_9 = req_uop_mem_cmd == 5'hE; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_15; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_15 = _GEN_9; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_38; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_38 = _GEN_9; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_15; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_15 = _GEN_9; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_38; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_38 = _GEN_9; // @[package.scala:16:47]
wire _r1_c_cat_T_15; // @[package.scala:16:47]
assign _r1_c_cat_T_15 = _GEN_9; // @[package.scala:16:47]
wire _r1_c_cat_T_38; // @[package.scala:16:47]
assign _r1_c_cat_T_38 = _GEN_9; // @[package.scala:16:47]
wire _needs_second_acq_T_42; // @[package.scala:16:47]
assign _needs_second_acq_T_42 = _GEN_9; // @[package.scala:16:47]
wire _GEN_10 = req_uop_mem_cmd == 5'hF; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_16; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_16 = _GEN_10; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_39; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_39 = _GEN_10; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_16; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_16 = _GEN_10; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_39; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_39 = _GEN_10; // @[package.scala:16:47]
wire _r1_c_cat_T_16; // @[package.scala:16:47]
assign _r1_c_cat_T_16 = _GEN_10; // @[package.scala:16:47]
wire _r1_c_cat_T_39; // @[package.scala:16:47]
assign _r1_c_cat_T_39 = _GEN_10; // @[package.scala:16:47]
wire _needs_second_acq_T_43; // @[package.scala:16:47]
assign _needs_second_acq_T_43 = _GEN_10; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_17 = _grow_param_r_c_cat_T_12 | _grow_param_r_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_18 = _grow_param_r_c_cat_T_17 | _grow_param_r_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_19 = _grow_param_r_c_cat_T_18 | _grow_param_r_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_20 = _grow_param_r_c_cat_T_19 | _grow_param_r_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_21 = _grow_param_r_c_cat_T_11 | _grow_param_r_c_cat_T_20; // @[package.scala:81:59]
wire _grow_param_r_c_cat_T_22 = _grow_param_r_c_cat_T_4 | _grow_param_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _grow_param_r_c_cat_T_25 = _grow_param_r_c_cat_T_23 | _grow_param_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _grow_param_r_c_cat_T_27 = _grow_param_r_c_cat_T_25 | _grow_param_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _grow_param_r_c_cat_T_32 = _grow_param_r_c_cat_T_28 | _grow_param_r_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_33 = _grow_param_r_c_cat_T_32 | _grow_param_r_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_34 = _grow_param_r_c_cat_T_33 | _grow_param_r_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_40 = _grow_param_r_c_cat_T_35 | _grow_param_r_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_41 = _grow_param_r_c_cat_T_40 | _grow_param_r_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_42 = _grow_param_r_c_cat_T_41 | _grow_param_r_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_43 = _grow_param_r_c_cat_T_42 | _grow_param_r_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_44 = _grow_param_r_c_cat_T_34 | _grow_param_r_c_cat_T_43; // @[package.scala:81:59]
wire _grow_param_r_c_cat_T_45 = _grow_param_r_c_cat_T_27 | _grow_param_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _GEN_11 = req_uop_mem_cmd == 5'h3; // @[Consts.scala:91:54]
wire _grow_param_r_c_cat_T_46; // @[Consts.scala:91:54]
assign _grow_param_r_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54]
wire _coh_on_grant_c_cat_T_46; // @[Consts.scala:91:54]
assign _coh_on_grant_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54]
wire _r1_c_cat_T_46; // @[Consts.scala:91:54]
assign _r1_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54]
wire _needs_second_acq_T_50; // @[Consts.scala:91:54]
assign _needs_second_acq_T_50 = _GEN_11; // @[Consts.scala:91:54]
wire _grow_param_r_c_cat_T_47 = _grow_param_r_c_cat_T_45 | _grow_param_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _GEN_12 = req_uop_mem_cmd == 5'h6; // @[Consts.scala:91:71]
wire _grow_param_r_c_cat_T_48; // @[Consts.scala:91:71]
assign _grow_param_r_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71]
wire _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:71]
assign _coh_on_grant_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71]
wire _r1_c_cat_T_48; // @[Consts.scala:91:71]
assign _r1_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71]
wire _needs_second_acq_T_52; // @[Consts.scala:91:71]
assign _needs_second_acq_T_52 = _GEN_12; // @[Consts.scala:91:71]
wire _grow_param_r_c_cat_T_49 = _grow_param_r_c_cat_T_47 | _grow_param_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] grow_param_r_c = {_grow_param_r_c_cat_T_22, _grow_param_r_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _grow_param_r_T = {grow_param_r_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19]
wire _grow_param_r_T_25 = _grow_param_r_T == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _grow_param_r_T_27 = {1'h0, _grow_param_r_T_25}; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_28 = _grow_param_r_T == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _grow_param_r_T_30 = _grow_param_r_T_28 ? 2'h2 : _grow_param_r_T_27; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_31 = _grow_param_r_T == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _grow_param_r_T_33 = _grow_param_r_T_31 ? 2'h1 : _grow_param_r_T_30; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_34 = _grow_param_r_T == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _grow_param_r_T_36 = _grow_param_r_T_34 ? 2'h2 : _grow_param_r_T_33; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_37 = _grow_param_r_T == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _grow_param_r_T_39 = _grow_param_r_T_37 ? 2'h0 : _grow_param_r_T_36; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_40 = _grow_param_r_T == 4'hE; // @[Misc.scala:49:20]
wire _grow_param_r_T_41 = _grow_param_r_T_40; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_42 = _grow_param_r_T_40 ? 2'h3 : _grow_param_r_T_39; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_43 = &_grow_param_r_T; // @[Misc.scala:49:20]
wire _grow_param_r_T_44 = _grow_param_r_T_43 | _grow_param_r_T_41; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_45 = _grow_param_r_T_43 ? 2'h3 : _grow_param_r_T_42; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_46 = _grow_param_r_T == 4'h6; // @[Misc.scala:49:20]
wire _grow_param_r_T_47 = _grow_param_r_T_46 | _grow_param_r_T_44; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_48 = _grow_param_r_T_46 ? 2'h2 : _grow_param_r_T_45; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_49 = _grow_param_r_T == 4'h7; // @[Misc.scala:49:20]
wire _grow_param_r_T_50 = _grow_param_r_T_49 | _grow_param_r_T_47; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_51 = _grow_param_r_T_49 ? 2'h3 : _grow_param_r_T_48; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_52 = _grow_param_r_T == 4'h1; // @[Misc.scala:49:20]
wire _grow_param_r_T_53 = _grow_param_r_T_52 | _grow_param_r_T_50; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_54 = _grow_param_r_T_52 ? 2'h1 : _grow_param_r_T_51; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_55 = _grow_param_r_T == 4'h2; // @[Misc.scala:49:20]
wire _grow_param_r_T_56 = _grow_param_r_T_55 | _grow_param_r_T_53; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_57 = _grow_param_r_T_55 ? 2'h2 : _grow_param_r_T_54; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_58 = _grow_param_r_T == 4'h3; // @[Misc.scala:49:20]
wire grow_param_r_1 = _grow_param_r_T_58 | _grow_param_r_T_56; // @[Misc.scala:35:9, :49:20]
wire [1:0] grow_param = _grow_param_r_T_58 ? 2'h3 : _grow_param_r_T_57; // @[Misc.scala:35:36, :49:20]
wire [1:0] grow_param_meta_state = grow_param; // @[Misc.scala:35:36]
wire _coh_on_grant_c_cat_T_2 = _coh_on_grant_c_cat_T | _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _coh_on_grant_c_cat_T_4 = _coh_on_grant_c_cat_T_2 | _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _coh_on_grant_c_cat_T_9 = _coh_on_grant_c_cat_T_5 | _coh_on_grant_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_10 = _coh_on_grant_c_cat_T_9 | _coh_on_grant_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_11 = _coh_on_grant_c_cat_T_10 | _coh_on_grant_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_17 = _coh_on_grant_c_cat_T_12 | _coh_on_grant_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_18 = _coh_on_grant_c_cat_T_17 | _coh_on_grant_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_19 = _coh_on_grant_c_cat_T_18 | _coh_on_grant_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_20 = _coh_on_grant_c_cat_T_19 | _coh_on_grant_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_21 = _coh_on_grant_c_cat_T_11 | _coh_on_grant_c_cat_T_20; // @[package.scala:81:59]
wire _coh_on_grant_c_cat_T_22 = _coh_on_grant_c_cat_T_4 | _coh_on_grant_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _coh_on_grant_c_cat_T_25 = _coh_on_grant_c_cat_T_23 | _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _coh_on_grant_c_cat_T_27 = _coh_on_grant_c_cat_T_25 | _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _coh_on_grant_c_cat_T_32 = _coh_on_grant_c_cat_T_28 | _coh_on_grant_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_33 = _coh_on_grant_c_cat_T_32 | _coh_on_grant_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_34 = _coh_on_grant_c_cat_T_33 | _coh_on_grant_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_40 = _coh_on_grant_c_cat_T_35 | _coh_on_grant_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_41 = _coh_on_grant_c_cat_T_40 | _coh_on_grant_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_42 = _coh_on_grant_c_cat_T_41 | _coh_on_grant_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_43 = _coh_on_grant_c_cat_T_42 | _coh_on_grant_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_44 = _coh_on_grant_c_cat_T_34 | _coh_on_grant_c_cat_T_43; // @[package.scala:81:59]
wire _coh_on_grant_c_cat_T_45 = _coh_on_grant_c_cat_T_27 | _coh_on_grant_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _coh_on_grant_c_cat_T_47 = _coh_on_grant_c_cat_T_45 | _coh_on_grant_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _coh_on_grant_c_cat_T_49 = _coh_on_grant_c_cat_T_47 | _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] coh_on_grant_c = {_coh_on_grant_c_cat_T_22, _coh_on_grant_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _coh_on_grant_T = {coh_on_grant_c, io_mem_grant_bits_param_0}; // @[Metadata.scala:29:18, :84:18]
wire _coh_on_grant_T_9 = _coh_on_grant_T == 4'h1; // @[Metadata.scala:84:{18,38}]
wire [1:0] _coh_on_grant_T_10 = {1'h0, _coh_on_grant_T_9}; // @[Metadata.scala:84:38]
wire _coh_on_grant_T_11 = _coh_on_grant_T == 4'h0; // @[Metadata.scala:84:{18,38}]
wire [1:0] _coh_on_grant_T_12 = _coh_on_grant_T_11 ? 2'h2 : _coh_on_grant_T_10; // @[Metadata.scala:84:38]
wire _coh_on_grant_T_13 = _coh_on_grant_T == 4'h4; // @[Metadata.scala:84:{18,38}]
wire [1:0] _coh_on_grant_T_14 = _coh_on_grant_T_13 ? 2'h2 : _coh_on_grant_T_12; // @[Metadata.scala:84:38]
wire _coh_on_grant_T_15 = _coh_on_grant_T == 4'hC; // @[Metadata.scala:84:{18,38}]
wire [1:0] _coh_on_grant_T_16 = _coh_on_grant_T_15 ? 2'h3 : _coh_on_grant_T_14; // @[Metadata.scala:84:38]
assign coh_on_grant_state = _coh_on_grant_T_16; // @[Metadata.scala:84:38, :160:20]
assign io_commit_coh_state_0 = coh_on_grant_state; // @[Metadata.scala:160:20]
wire _r1_c_cat_T_2 = _r1_c_cat_T | _r1_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _r1_c_cat_T_4 = _r1_c_cat_T_2 | _r1_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _r1_c_cat_T_9 = _r1_c_cat_T_5 | _r1_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_10 = _r1_c_cat_T_9 | _r1_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_11 = _r1_c_cat_T_10 | _r1_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_17 = _r1_c_cat_T_12 | _r1_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_18 = _r1_c_cat_T_17 | _r1_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_19 = _r1_c_cat_T_18 | _r1_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_20 = _r1_c_cat_T_19 | _r1_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_21 = _r1_c_cat_T_11 | _r1_c_cat_T_20; // @[package.scala:81:59]
wire _r1_c_cat_T_22 = _r1_c_cat_T_4 | _r1_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _r1_c_cat_T_25 = _r1_c_cat_T_23 | _r1_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _r1_c_cat_T_27 = _r1_c_cat_T_25 | _r1_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _r1_c_cat_T_32 = _r1_c_cat_T_28 | _r1_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_33 = _r1_c_cat_T_32 | _r1_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_34 = _r1_c_cat_T_33 | _r1_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_40 = _r1_c_cat_T_35 | _r1_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_41 = _r1_c_cat_T_40 | _r1_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_42 = _r1_c_cat_T_41 | _r1_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_43 = _r1_c_cat_T_42 | _r1_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_44 = _r1_c_cat_T_34 | _r1_c_cat_T_43; // @[package.scala:81:59]
wire _r1_c_cat_T_45 = _r1_c_cat_T_27 | _r1_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _r1_c_cat_T_47 = _r1_c_cat_T_45 | _r1_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _r1_c_cat_T_49 = _r1_c_cat_T_47 | _r1_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] r1_c = {_r1_c_cat_T_22, _r1_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _r1_T = {r1_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19]
wire _r1_T_25 = _r1_T == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _r1_T_27 = {1'h0, _r1_T_25}; // @[Misc.scala:35:36, :49:20]
wire _r1_T_28 = _r1_T == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _r1_T_30 = _r1_T_28 ? 2'h2 : _r1_T_27; // @[Misc.scala:35:36, :49:20]
wire _r1_T_31 = _r1_T == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _r1_T_33 = _r1_T_31 ? 2'h1 : _r1_T_30; // @[Misc.scala:35:36, :49:20]
wire _r1_T_34 = _r1_T == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _r1_T_36 = _r1_T_34 ? 2'h2 : _r1_T_33; // @[Misc.scala:35:36, :49:20]
wire _r1_T_37 = _r1_T == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _r1_T_39 = _r1_T_37 ? 2'h0 : _r1_T_36; // @[Misc.scala:35:36, :49:20]
wire _r1_T_40 = _r1_T == 4'hE; // @[Misc.scala:49:20]
wire _r1_T_41 = _r1_T_40; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_42 = _r1_T_40 ? 2'h3 : _r1_T_39; // @[Misc.scala:35:36, :49:20]
wire _r1_T_43 = &_r1_T; // @[Misc.scala:49:20]
wire _r1_T_44 = _r1_T_43 | _r1_T_41; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_45 = _r1_T_43 ? 2'h3 : _r1_T_42; // @[Misc.scala:35:36, :49:20]
wire _r1_T_46 = _r1_T == 4'h6; // @[Misc.scala:49:20]
wire _r1_T_47 = _r1_T_46 | _r1_T_44; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_48 = _r1_T_46 ? 2'h2 : _r1_T_45; // @[Misc.scala:35:36, :49:20]
wire _r1_T_49 = _r1_T == 4'h7; // @[Misc.scala:49:20]
wire _r1_T_50 = _r1_T_49 | _r1_T_47; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_51 = _r1_T_49 ? 2'h3 : _r1_T_48; // @[Misc.scala:35:36, :49:20]
wire _r1_T_52 = _r1_T == 4'h1; // @[Misc.scala:49:20]
wire _r1_T_53 = _r1_T_52 | _r1_T_50; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_54 = _r1_T_52 ? 2'h1 : _r1_T_51; // @[Misc.scala:35:36, :49:20]
wire _r1_T_55 = _r1_T == 4'h2; // @[Misc.scala:49:20]
wire _r1_T_56 = _r1_T_55 | _r1_T_53; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_57 = _r1_T_55 ? 2'h2 : _r1_T_54; // @[Misc.scala:35:36, :49:20]
wire _r1_T_58 = _r1_T == 4'h3; // @[Misc.scala:49:20]
wire r1_1 = _r1_T_58 | _r1_T_56; // @[Misc.scala:35:9, :49:20]
wire [1:0] r1_2 = _r1_T_58 ? 2'h3 : _r1_T_57; // @[Misc.scala:35:36, :49:20]
wire _GEN_13 = io_req_uop_mem_cmd_0 == 5'h1; // @[Consts.scala:90:32]
wire _r2_c_cat_T; // @[Consts.scala:90:32]
assign _r2_c_cat_T = _GEN_13; // @[Consts.scala:90:32]
wire _r2_c_cat_T_23; // @[Consts.scala:90:32]
assign _r2_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32]
wire _needs_second_acq_T; // @[Consts.scala:90:32]
assign _needs_second_acq_T = _GEN_13; // @[Consts.scala:90:32]
wire _dirties_cat_T; // @[Consts.scala:90:32]
assign _dirties_cat_T = _GEN_13; // @[Consts.scala:90:32]
wire _dirties_cat_T_23; // @[Consts.scala:90:32]
assign _dirties_cat_T_23 = _GEN_13; // @[Consts.scala:90:32]
wire _state_r_c_cat_T; // @[Consts.scala:90:32]
assign _state_r_c_cat_T = _GEN_13; // @[Consts.scala:90:32]
wire _state_r_c_cat_T_23; // @[Consts.scala:90:32]
assign _state_r_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32]
wire _state_T_3; // @[Consts.scala:90:32]
assign _state_T_3 = _GEN_13; // @[Consts.scala:90:32]
wire _r_c_cat_T_50; // @[Consts.scala:90:32]
assign _r_c_cat_T_50 = _GEN_13; // @[Consts.scala:90:32]
wire _r_c_cat_T_73; // @[Consts.scala:90:32]
assign _r_c_cat_T_73 = _GEN_13; // @[Consts.scala:90:32]
wire _state_r_c_cat_T_50; // @[Consts.scala:90:32]
assign _state_r_c_cat_T_50 = _GEN_13; // @[Consts.scala:90:32]
wire _state_r_c_cat_T_73; // @[Consts.scala:90:32]
assign _state_r_c_cat_T_73 = _GEN_13; // @[Consts.scala:90:32]
wire _state_T_37; // @[Consts.scala:90:32]
assign _state_T_37 = _GEN_13; // @[Consts.scala:90:32]
wire _GEN_14 = io_req_uop_mem_cmd_0 == 5'h11; // @[Consts.scala:90:49]
wire _r2_c_cat_T_1; // @[Consts.scala:90:49]
assign _r2_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49]
wire _r2_c_cat_T_24; // @[Consts.scala:90:49]
assign _r2_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49]
wire _needs_second_acq_T_1; // @[Consts.scala:90:49]
assign _needs_second_acq_T_1 = _GEN_14; // @[Consts.scala:90:49]
wire _dirties_cat_T_1; // @[Consts.scala:90:49]
assign _dirties_cat_T_1 = _GEN_14; // @[Consts.scala:90:49]
wire _dirties_cat_T_24; // @[Consts.scala:90:49]
assign _dirties_cat_T_24 = _GEN_14; // @[Consts.scala:90:49]
wire _state_r_c_cat_T_1; // @[Consts.scala:90:49]
assign _state_r_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49]
wire _state_r_c_cat_T_24; // @[Consts.scala:90:49]
assign _state_r_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49]
wire _state_T_4; // @[Consts.scala:90:49]
assign _state_T_4 = _GEN_14; // @[Consts.scala:90:49]
wire _r_c_cat_T_51; // @[Consts.scala:90:49]
assign _r_c_cat_T_51 = _GEN_14; // @[Consts.scala:90:49]
wire _r_c_cat_T_74; // @[Consts.scala:90:49]
assign _r_c_cat_T_74 = _GEN_14; // @[Consts.scala:90:49]
wire _state_r_c_cat_T_51; // @[Consts.scala:90:49]
assign _state_r_c_cat_T_51 = _GEN_14; // @[Consts.scala:90:49]
wire _state_r_c_cat_T_74; // @[Consts.scala:90:49]
assign _state_r_c_cat_T_74 = _GEN_14; // @[Consts.scala:90:49]
wire _state_T_38; // @[Consts.scala:90:49]
assign _state_T_38 = _GEN_14; // @[Consts.scala:90:49]
wire _r2_c_cat_T_2 = _r2_c_cat_T | _r2_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _GEN_15 = io_req_uop_mem_cmd_0 == 5'h7; // @[Consts.scala:90:66]
wire _r2_c_cat_T_3; // @[Consts.scala:90:66]
assign _r2_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66]
wire _r2_c_cat_T_26; // @[Consts.scala:90:66]
assign _r2_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66]
wire _needs_second_acq_T_3; // @[Consts.scala:90:66]
assign _needs_second_acq_T_3 = _GEN_15; // @[Consts.scala:90:66]
wire _dirties_cat_T_3; // @[Consts.scala:90:66]
assign _dirties_cat_T_3 = _GEN_15; // @[Consts.scala:90:66]
wire _dirties_cat_T_26; // @[Consts.scala:90:66]
assign _dirties_cat_T_26 = _GEN_15; // @[Consts.scala:90:66]
wire _state_r_c_cat_T_3; // @[Consts.scala:90:66]
assign _state_r_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66]
wire _state_r_c_cat_T_26; // @[Consts.scala:90:66]
assign _state_r_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66]
wire _state_T_6; // @[Consts.scala:90:66]
assign _state_T_6 = _GEN_15; // @[Consts.scala:90:66]
wire _r_c_cat_T_53; // @[Consts.scala:90:66]
assign _r_c_cat_T_53 = _GEN_15; // @[Consts.scala:90:66]
wire _r_c_cat_T_76; // @[Consts.scala:90:66]
assign _r_c_cat_T_76 = _GEN_15; // @[Consts.scala:90:66]
wire _state_r_c_cat_T_53; // @[Consts.scala:90:66]
assign _state_r_c_cat_T_53 = _GEN_15; // @[Consts.scala:90:66]
wire _state_r_c_cat_T_76; // @[Consts.scala:90:66]
assign _state_r_c_cat_T_76 = _GEN_15; // @[Consts.scala:90:66]
wire _state_T_40; // @[Consts.scala:90:66]
assign _state_T_40 = _GEN_15; // @[Consts.scala:90:66]
wire _r2_c_cat_T_4 = _r2_c_cat_T_2 | _r2_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _GEN_16 = io_req_uop_mem_cmd_0 == 5'h4; // @[package.scala:16:47]
wire _r2_c_cat_T_5; // @[package.scala:16:47]
assign _r2_c_cat_T_5 = _GEN_16; // @[package.scala:16:47]
wire _r2_c_cat_T_28; // @[package.scala:16:47]
assign _r2_c_cat_T_28 = _GEN_16; // @[package.scala:16:47]
wire _needs_second_acq_T_5; // @[package.scala:16:47]
assign _needs_second_acq_T_5 = _GEN_16; // @[package.scala:16:47]
wire _dirties_cat_T_5; // @[package.scala:16:47]
assign _dirties_cat_T_5 = _GEN_16; // @[package.scala:16:47]
wire _dirties_cat_T_28; // @[package.scala:16:47]
assign _dirties_cat_T_28 = _GEN_16; // @[package.scala:16:47]
wire _state_r_c_cat_T_5; // @[package.scala:16:47]
assign _state_r_c_cat_T_5 = _GEN_16; // @[package.scala:16:47]
wire _state_r_c_cat_T_28; // @[package.scala:16:47]
assign _state_r_c_cat_T_28 = _GEN_16; // @[package.scala:16:47]
wire _state_T_8; // @[package.scala:16:47]
assign _state_T_8 = _GEN_16; // @[package.scala:16:47]
wire _r_c_cat_T_55; // @[package.scala:16:47]
assign _r_c_cat_T_55 = _GEN_16; // @[package.scala:16:47]
wire _r_c_cat_T_78; // @[package.scala:16:47]
assign _r_c_cat_T_78 = _GEN_16; // @[package.scala:16:47]
wire _state_r_c_cat_T_55; // @[package.scala:16:47]
assign _state_r_c_cat_T_55 = _GEN_16; // @[package.scala:16:47]
wire _state_r_c_cat_T_78; // @[package.scala:16:47]
assign _state_r_c_cat_T_78 = _GEN_16; // @[package.scala:16:47]
wire _state_T_42; // @[package.scala:16:47]
assign _state_T_42 = _GEN_16; // @[package.scala:16:47]
wire _GEN_17 = io_req_uop_mem_cmd_0 == 5'h9; // @[package.scala:16:47]
wire _r2_c_cat_T_6; // @[package.scala:16:47]
assign _r2_c_cat_T_6 = _GEN_17; // @[package.scala:16:47]
wire _r2_c_cat_T_29; // @[package.scala:16:47]
assign _r2_c_cat_T_29 = _GEN_17; // @[package.scala:16:47]
wire _needs_second_acq_T_6; // @[package.scala:16:47]
assign _needs_second_acq_T_6 = _GEN_17; // @[package.scala:16:47]
wire _dirties_cat_T_6; // @[package.scala:16:47]
assign _dirties_cat_T_6 = _GEN_17; // @[package.scala:16:47]
wire _dirties_cat_T_29; // @[package.scala:16:47]
assign _dirties_cat_T_29 = _GEN_17; // @[package.scala:16:47]
wire _state_r_c_cat_T_6; // @[package.scala:16:47]
assign _state_r_c_cat_T_6 = _GEN_17; // @[package.scala:16:47]
wire _state_r_c_cat_T_29; // @[package.scala:16:47]
assign _state_r_c_cat_T_29 = _GEN_17; // @[package.scala:16:47]
wire _state_T_9; // @[package.scala:16:47]
assign _state_T_9 = _GEN_17; // @[package.scala:16:47]
wire _r_c_cat_T_56; // @[package.scala:16:47]
assign _r_c_cat_T_56 = _GEN_17; // @[package.scala:16:47]
wire _r_c_cat_T_79; // @[package.scala:16:47]
assign _r_c_cat_T_79 = _GEN_17; // @[package.scala:16:47]
wire _state_r_c_cat_T_56; // @[package.scala:16:47]
assign _state_r_c_cat_T_56 = _GEN_17; // @[package.scala:16:47]
wire _state_r_c_cat_T_79; // @[package.scala:16:47]
assign _state_r_c_cat_T_79 = _GEN_17; // @[package.scala:16:47]
wire _state_T_43; // @[package.scala:16:47]
assign _state_T_43 = _GEN_17; // @[package.scala:16:47]
wire _GEN_18 = io_req_uop_mem_cmd_0 == 5'hA; // @[package.scala:16:47]
wire _r2_c_cat_T_7; // @[package.scala:16:47]
assign _r2_c_cat_T_7 = _GEN_18; // @[package.scala:16:47]
wire _r2_c_cat_T_30; // @[package.scala:16:47]
assign _r2_c_cat_T_30 = _GEN_18; // @[package.scala:16:47]
wire _needs_second_acq_T_7; // @[package.scala:16:47]
assign _needs_second_acq_T_7 = _GEN_18; // @[package.scala:16:47]
wire _dirties_cat_T_7; // @[package.scala:16:47]
assign _dirties_cat_T_7 = _GEN_18; // @[package.scala:16:47]
wire _dirties_cat_T_30; // @[package.scala:16:47]
assign _dirties_cat_T_30 = _GEN_18; // @[package.scala:16:47]
wire _state_r_c_cat_T_7; // @[package.scala:16:47]
assign _state_r_c_cat_T_7 = _GEN_18; // @[package.scala:16:47]
wire _state_r_c_cat_T_30; // @[package.scala:16:47]
assign _state_r_c_cat_T_30 = _GEN_18; // @[package.scala:16:47]
wire _state_T_10; // @[package.scala:16:47]
assign _state_T_10 = _GEN_18; // @[package.scala:16:47]
wire _r_c_cat_T_57; // @[package.scala:16:47]
assign _r_c_cat_T_57 = _GEN_18; // @[package.scala:16:47]
wire _r_c_cat_T_80; // @[package.scala:16:47]
assign _r_c_cat_T_80 = _GEN_18; // @[package.scala:16:47]
wire _state_r_c_cat_T_57; // @[package.scala:16:47]
assign _state_r_c_cat_T_57 = _GEN_18; // @[package.scala:16:47]
wire _state_r_c_cat_T_80; // @[package.scala:16:47]
assign _state_r_c_cat_T_80 = _GEN_18; // @[package.scala:16:47]
wire _state_T_44; // @[package.scala:16:47]
assign _state_T_44 = _GEN_18; // @[package.scala:16:47]
wire _GEN_19 = io_req_uop_mem_cmd_0 == 5'hB; // @[package.scala:16:47]
wire _r2_c_cat_T_8; // @[package.scala:16:47]
assign _r2_c_cat_T_8 = _GEN_19; // @[package.scala:16:47]
wire _r2_c_cat_T_31; // @[package.scala:16:47]
assign _r2_c_cat_T_31 = _GEN_19; // @[package.scala:16:47]
wire _needs_second_acq_T_8; // @[package.scala:16:47]
assign _needs_second_acq_T_8 = _GEN_19; // @[package.scala:16:47]
wire _dirties_cat_T_8; // @[package.scala:16:47]
assign _dirties_cat_T_8 = _GEN_19; // @[package.scala:16:47]
wire _dirties_cat_T_31; // @[package.scala:16:47]
assign _dirties_cat_T_31 = _GEN_19; // @[package.scala:16:47]
wire _state_r_c_cat_T_8; // @[package.scala:16:47]
assign _state_r_c_cat_T_8 = _GEN_19; // @[package.scala:16:47]
wire _state_r_c_cat_T_31; // @[package.scala:16:47]
assign _state_r_c_cat_T_31 = _GEN_19; // @[package.scala:16:47]
wire _state_T_11; // @[package.scala:16:47]
assign _state_T_11 = _GEN_19; // @[package.scala:16:47]
wire _r_c_cat_T_58; // @[package.scala:16:47]
assign _r_c_cat_T_58 = _GEN_19; // @[package.scala:16:47]
wire _r_c_cat_T_81; // @[package.scala:16:47]
assign _r_c_cat_T_81 = _GEN_19; // @[package.scala:16:47]
wire _state_r_c_cat_T_58; // @[package.scala:16:47]
assign _state_r_c_cat_T_58 = _GEN_19; // @[package.scala:16:47]
wire _state_r_c_cat_T_81; // @[package.scala:16:47]
assign _state_r_c_cat_T_81 = _GEN_19; // @[package.scala:16:47]
wire _state_T_45; // @[package.scala:16:47]
assign _state_T_45 = _GEN_19; // @[package.scala:16:47]
wire _r2_c_cat_T_9 = _r2_c_cat_T_5 | _r2_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_10 = _r2_c_cat_T_9 | _r2_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_11 = _r2_c_cat_T_10 | _r2_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _GEN_20 = io_req_uop_mem_cmd_0 == 5'h8; // @[package.scala:16:47]
wire _r2_c_cat_T_12; // @[package.scala:16:47]
assign _r2_c_cat_T_12 = _GEN_20; // @[package.scala:16:47]
wire _r2_c_cat_T_35; // @[package.scala:16:47]
assign _r2_c_cat_T_35 = _GEN_20; // @[package.scala:16:47]
wire _needs_second_acq_T_12; // @[package.scala:16:47]
assign _needs_second_acq_T_12 = _GEN_20; // @[package.scala:16:47]
wire _dirties_cat_T_12; // @[package.scala:16:47]
assign _dirties_cat_T_12 = _GEN_20; // @[package.scala:16:47]
wire _dirties_cat_T_35; // @[package.scala:16:47]
assign _dirties_cat_T_35 = _GEN_20; // @[package.scala:16:47]
wire _state_r_c_cat_T_12; // @[package.scala:16:47]
assign _state_r_c_cat_T_12 = _GEN_20; // @[package.scala:16:47]
wire _state_r_c_cat_T_35; // @[package.scala:16:47]
assign _state_r_c_cat_T_35 = _GEN_20; // @[package.scala:16:47]
wire _state_T_15; // @[package.scala:16:47]
assign _state_T_15 = _GEN_20; // @[package.scala:16:47]
wire _r_c_cat_T_62; // @[package.scala:16:47]
assign _r_c_cat_T_62 = _GEN_20; // @[package.scala:16:47]
wire _r_c_cat_T_85; // @[package.scala:16:47]
assign _r_c_cat_T_85 = _GEN_20; // @[package.scala:16:47]
wire _state_r_c_cat_T_62; // @[package.scala:16:47]
assign _state_r_c_cat_T_62 = _GEN_20; // @[package.scala:16:47]
wire _state_r_c_cat_T_85; // @[package.scala:16:47]
assign _state_r_c_cat_T_85 = _GEN_20; // @[package.scala:16:47]
wire _state_T_49; // @[package.scala:16:47]
assign _state_T_49 = _GEN_20; // @[package.scala:16:47]
wire _GEN_21 = io_req_uop_mem_cmd_0 == 5'hC; // @[package.scala:16:47]
wire _r2_c_cat_T_13; // @[package.scala:16:47]
assign _r2_c_cat_T_13 = _GEN_21; // @[package.scala:16:47]
wire _r2_c_cat_T_36; // @[package.scala:16:47]
assign _r2_c_cat_T_36 = _GEN_21; // @[package.scala:16:47]
wire _needs_second_acq_T_13; // @[package.scala:16:47]
assign _needs_second_acq_T_13 = _GEN_21; // @[package.scala:16:47]
wire _dirties_cat_T_13; // @[package.scala:16:47]
assign _dirties_cat_T_13 = _GEN_21; // @[package.scala:16:47]
wire _dirties_cat_T_36; // @[package.scala:16:47]
assign _dirties_cat_T_36 = _GEN_21; // @[package.scala:16:47]
wire _state_r_c_cat_T_13; // @[package.scala:16:47]
assign _state_r_c_cat_T_13 = _GEN_21; // @[package.scala:16:47]
wire _state_r_c_cat_T_36; // @[package.scala:16:47]
assign _state_r_c_cat_T_36 = _GEN_21; // @[package.scala:16:47]
wire _state_T_16; // @[package.scala:16:47]
assign _state_T_16 = _GEN_21; // @[package.scala:16:47]
wire _r_c_cat_T_63; // @[package.scala:16:47]
assign _r_c_cat_T_63 = _GEN_21; // @[package.scala:16:47]
wire _r_c_cat_T_86; // @[package.scala:16:47]
assign _r_c_cat_T_86 = _GEN_21; // @[package.scala:16:47]
wire _state_r_c_cat_T_63; // @[package.scala:16:47]
assign _state_r_c_cat_T_63 = _GEN_21; // @[package.scala:16:47]
wire _state_r_c_cat_T_86; // @[package.scala:16:47]
assign _state_r_c_cat_T_86 = _GEN_21; // @[package.scala:16:47]
wire _state_T_50; // @[package.scala:16:47]
assign _state_T_50 = _GEN_21; // @[package.scala:16:47]
wire _GEN_22 = io_req_uop_mem_cmd_0 == 5'hD; // @[package.scala:16:47]
wire _r2_c_cat_T_14; // @[package.scala:16:47]
assign _r2_c_cat_T_14 = _GEN_22; // @[package.scala:16:47]
wire _r2_c_cat_T_37; // @[package.scala:16:47]
assign _r2_c_cat_T_37 = _GEN_22; // @[package.scala:16:47]
wire _needs_second_acq_T_14; // @[package.scala:16:47]
assign _needs_second_acq_T_14 = _GEN_22; // @[package.scala:16:47]
wire _dirties_cat_T_14; // @[package.scala:16:47]
assign _dirties_cat_T_14 = _GEN_22; // @[package.scala:16:47]
wire _dirties_cat_T_37; // @[package.scala:16:47]
assign _dirties_cat_T_37 = _GEN_22; // @[package.scala:16:47]
wire _state_r_c_cat_T_14; // @[package.scala:16:47]
assign _state_r_c_cat_T_14 = _GEN_22; // @[package.scala:16:47]
wire _state_r_c_cat_T_37; // @[package.scala:16:47]
assign _state_r_c_cat_T_37 = _GEN_22; // @[package.scala:16:47]
wire _state_T_17; // @[package.scala:16:47]
assign _state_T_17 = _GEN_22; // @[package.scala:16:47]
wire _r_c_cat_T_64; // @[package.scala:16:47]
assign _r_c_cat_T_64 = _GEN_22; // @[package.scala:16:47]
wire _r_c_cat_T_87; // @[package.scala:16:47]
assign _r_c_cat_T_87 = _GEN_22; // @[package.scala:16:47]
wire _state_r_c_cat_T_64; // @[package.scala:16:47]
assign _state_r_c_cat_T_64 = _GEN_22; // @[package.scala:16:47]
wire _state_r_c_cat_T_87; // @[package.scala:16:47]
assign _state_r_c_cat_T_87 = _GEN_22; // @[package.scala:16:47]
wire _state_T_51; // @[package.scala:16:47]
assign _state_T_51 = _GEN_22; // @[package.scala:16:47]
wire _GEN_23 = io_req_uop_mem_cmd_0 == 5'hE; // @[package.scala:16:47]
wire _r2_c_cat_T_15; // @[package.scala:16:47]
assign _r2_c_cat_T_15 = _GEN_23; // @[package.scala:16:47]
wire _r2_c_cat_T_38; // @[package.scala:16:47]
assign _r2_c_cat_T_38 = _GEN_23; // @[package.scala:16:47]
wire _needs_second_acq_T_15; // @[package.scala:16:47]
assign _needs_second_acq_T_15 = _GEN_23; // @[package.scala:16:47]
wire _dirties_cat_T_15; // @[package.scala:16:47]
assign _dirties_cat_T_15 = _GEN_23; // @[package.scala:16:47]
wire _dirties_cat_T_38; // @[package.scala:16:47]
assign _dirties_cat_T_38 = _GEN_23; // @[package.scala:16:47]
wire _state_r_c_cat_T_15; // @[package.scala:16:47]
assign _state_r_c_cat_T_15 = _GEN_23; // @[package.scala:16:47]
wire _state_r_c_cat_T_38; // @[package.scala:16:47]
assign _state_r_c_cat_T_38 = _GEN_23; // @[package.scala:16:47]
wire _state_T_18; // @[package.scala:16:47]
assign _state_T_18 = _GEN_23; // @[package.scala:16:47]
wire _r_c_cat_T_65; // @[package.scala:16:47]
assign _r_c_cat_T_65 = _GEN_23; // @[package.scala:16:47]
wire _r_c_cat_T_88; // @[package.scala:16:47]
assign _r_c_cat_T_88 = _GEN_23; // @[package.scala:16:47]
wire _state_r_c_cat_T_65; // @[package.scala:16:47]
assign _state_r_c_cat_T_65 = _GEN_23; // @[package.scala:16:47]
wire _state_r_c_cat_T_88; // @[package.scala:16:47]
assign _state_r_c_cat_T_88 = _GEN_23; // @[package.scala:16:47]
wire _state_T_52; // @[package.scala:16:47]
assign _state_T_52 = _GEN_23; // @[package.scala:16:47]
wire _GEN_24 = io_req_uop_mem_cmd_0 == 5'hF; // @[package.scala:16:47]
wire _r2_c_cat_T_16; // @[package.scala:16:47]
assign _r2_c_cat_T_16 = _GEN_24; // @[package.scala:16:47]
wire _r2_c_cat_T_39; // @[package.scala:16:47]
assign _r2_c_cat_T_39 = _GEN_24; // @[package.scala:16:47]
wire _needs_second_acq_T_16; // @[package.scala:16:47]
assign _needs_second_acq_T_16 = _GEN_24; // @[package.scala:16:47]
wire _dirties_cat_T_16; // @[package.scala:16:47]
assign _dirties_cat_T_16 = _GEN_24; // @[package.scala:16:47]
wire _dirties_cat_T_39; // @[package.scala:16:47]
assign _dirties_cat_T_39 = _GEN_24; // @[package.scala:16:47]
wire _state_r_c_cat_T_16; // @[package.scala:16:47]
assign _state_r_c_cat_T_16 = _GEN_24; // @[package.scala:16:47]
wire _state_r_c_cat_T_39; // @[package.scala:16:47]
assign _state_r_c_cat_T_39 = _GEN_24; // @[package.scala:16:47]
wire _state_T_19; // @[package.scala:16:47]
assign _state_T_19 = _GEN_24; // @[package.scala:16:47]
wire _r_c_cat_T_66; // @[package.scala:16:47]
assign _r_c_cat_T_66 = _GEN_24; // @[package.scala:16:47]
wire _r_c_cat_T_89; // @[package.scala:16:47]
assign _r_c_cat_T_89 = _GEN_24; // @[package.scala:16:47]
wire _state_r_c_cat_T_66; // @[package.scala:16:47]
assign _state_r_c_cat_T_66 = _GEN_24; // @[package.scala:16:47]
wire _state_r_c_cat_T_89; // @[package.scala:16:47]
assign _state_r_c_cat_T_89 = _GEN_24; // @[package.scala:16:47]
wire _state_T_53; // @[package.scala:16:47]
assign _state_T_53 = _GEN_24; // @[package.scala:16:47]
wire _r2_c_cat_T_17 = _r2_c_cat_T_12 | _r2_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_18 = _r2_c_cat_T_17 | _r2_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_19 = _r2_c_cat_T_18 | _r2_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_20 = _r2_c_cat_T_19 | _r2_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_21 = _r2_c_cat_T_11 | _r2_c_cat_T_20; // @[package.scala:81:59]
wire _r2_c_cat_T_22 = _r2_c_cat_T_4 | _r2_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _r2_c_cat_T_25 = _r2_c_cat_T_23 | _r2_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _r2_c_cat_T_27 = _r2_c_cat_T_25 | _r2_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _r2_c_cat_T_32 = _r2_c_cat_T_28 | _r2_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_33 = _r2_c_cat_T_32 | _r2_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_34 = _r2_c_cat_T_33 | _r2_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_40 = _r2_c_cat_T_35 | _r2_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_41 = _r2_c_cat_T_40 | _r2_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_42 = _r2_c_cat_T_41 | _r2_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_43 = _r2_c_cat_T_42 | _r2_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_44 = _r2_c_cat_T_34 | _r2_c_cat_T_43; // @[package.scala:81:59]
wire _r2_c_cat_T_45 = _r2_c_cat_T_27 | _r2_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _GEN_25 = io_req_uop_mem_cmd_0 == 5'h3; // @[Consts.scala:91:54]
wire _r2_c_cat_T_46; // @[Consts.scala:91:54]
assign _r2_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54]
wire _needs_second_acq_T_23; // @[Consts.scala:91:54]
assign _needs_second_acq_T_23 = _GEN_25; // @[Consts.scala:91:54]
wire _dirties_cat_T_46; // @[Consts.scala:91:54]
assign _dirties_cat_T_46 = _GEN_25; // @[Consts.scala:91:54]
wire _rpq_io_enq_valid_T_4; // @[Consts.scala:88:52]
assign _rpq_io_enq_valid_T_4 = _GEN_25; // @[Consts.scala:88:52, :91:54]
wire _state_r_c_cat_T_46; // @[Consts.scala:91:54]
assign _state_r_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54]
wire _r_c_cat_T_96; // @[Consts.scala:91:54]
assign _r_c_cat_T_96 = _GEN_25; // @[Consts.scala:91:54]
wire _state_r_c_cat_T_96; // @[Consts.scala:91:54]
assign _state_r_c_cat_T_96 = _GEN_25; // @[Consts.scala:91:54]
wire _r2_c_cat_T_47 = _r2_c_cat_T_45 | _r2_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _GEN_26 = io_req_uop_mem_cmd_0 == 5'h6; // @[Consts.scala:91:71]
wire _r2_c_cat_T_48; // @[Consts.scala:91:71]
assign _r2_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71]
wire _needs_second_acq_T_25; // @[Consts.scala:91:71]
assign _needs_second_acq_T_25 = _GEN_26; // @[Consts.scala:91:71]
wire _dirties_cat_T_48; // @[Consts.scala:91:71]
assign _dirties_cat_T_48 = _GEN_26; // @[Consts.scala:91:71]
wire _state_r_c_cat_T_48; // @[Consts.scala:91:71]
assign _state_r_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71]
wire _r_c_cat_T_98; // @[Consts.scala:91:71]
assign _r_c_cat_T_98 = _GEN_26; // @[Consts.scala:91:71]
wire _state_r_c_cat_T_98; // @[Consts.scala:91:71]
assign _state_r_c_cat_T_98 = _GEN_26; // @[Consts.scala:91:71]
wire _r2_c_cat_T_49 = _r2_c_cat_T_47 | _r2_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] r2_c = {_r2_c_cat_T_22, _r2_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _r2_T = {r2_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19]
wire _r2_T_25 = _r2_T == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _r2_T_27 = {1'h0, _r2_T_25}; // @[Misc.scala:35:36, :49:20]
wire _r2_T_28 = _r2_T == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _r2_T_30 = _r2_T_28 ? 2'h2 : _r2_T_27; // @[Misc.scala:35:36, :49:20]
wire _r2_T_31 = _r2_T == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _r2_T_33 = _r2_T_31 ? 2'h1 : _r2_T_30; // @[Misc.scala:35:36, :49:20]
wire _r2_T_34 = _r2_T == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _r2_T_36 = _r2_T_34 ? 2'h2 : _r2_T_33; // @[Misc.scala:35:36, :49:20]
wire _r2_T_37 = _r2_T == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _r2_T_39 = _r2_T_37 ? 2'h0 : _r2_T_36; // @[Misc.scala:35:36, :49:20]
wire _r2_T_40 = _r2_T == 4'hE; // @[Misc.scala:49:20]
wire _r2_T_41 = _r2_T_40; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_42 = _r2_T_40 ? 2'h3 : _r2_T_39; // @[Misc.scala:35:36, :49:20]
wire _r2_T_43 = &_r2_T; // @[Misc.scala:49:20]
wire _r2_T_44 = _r2_T_43 | _r2_T_41; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_45 = _r2_T_43 ? 2'h3 : _r2_T_42; // @[Misc.scala:35:36, :49:20]
wire _r2_T_46 = _r2_T == 4'h6; // @[Misc.scala:49:20]
wire _r2_T_47 = _r2_T_46 | _r2_T_44; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_48 = _r2_T_46 ? 2'h2 : _r2_T_45; // @[Misc.scala:35:36, :49:20]
wire _r2_T_49 = _r2_T == 4'h7; // @[Misc.scala:49:20]
wire _r2_T_50 = _r2_T_49 | _r2_T_47; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_51 = _r2_T_49 ? 2'h3 : _r2_T_48; // @[Misc.scala:35:36, :49:20]
wire _r2_T_52 = _r2_T == 4'h1; // @[Misc.scala:49:20]
wire _r2_T_53 = _r2_T_52 | _r2_T_50; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_54 = _r2_T_52 ? 2'h1 : _r2_T_51; // @[Misc.scala:35:36, :49:20]
wire _r2_T_55 = _r2_T == 4'h2; // @[Misc.scala:49:20]
wire _r2_T_56 = _r2_T_55 | _r2_T_53; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_57 = _r2_T_55 ? 2'h2 : _r2_T_54; // @[Misc.scala:35:36, :49:20]
wire _r2_T_58 = _r2_T == 4'h3; // @[Misc.scala:49:20]
wire r2_1 = _r2_T_58 | _r2_T_56; // @[Misc.scala:35:9, :49:20]
wire [1:0] r2_2 = _r2_T_58 ? 2'h3 : _r2_T_57; // @[Misc.scala:35:36, :49:20]
wire _needs_second_acq_T_2 = _needs_second_acq_T | _needs_second_acq_T_1; // @[Consts.scala:90:{32,42,49}]
wire _needs_second_acq_T_4 = _needs_second_acq_T_2 | _needs_second_acq_T_3; // @[Consts.scala:90:{42,59,66}]
wire _needs_second_acq_T_9 = _needs_second_acq_T_5 | _needs_second_acq_T_6; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_10 = _needs_second_acq_T_9 | _needs_second_acq_T_7; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_11 = _needs_second_acq_T_10 | _needs_second_acq_T_8; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_17 = _needs_second_acq_T_12 | _needs_second_acq_T_13; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_18 = _needs_second_acq_T_17 | _needs_second_acq_T_14; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_19 = _needs_second_acq_T_18 | _needs_second_acq_T_15; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_20 = _needs_second_acq_T_19 | _needs_second_acq_T_16; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_21 = _needs_second_acq_T_11 | _needs_second_acq_T_20; // @[package.scala:81:59]
wire _needs_second_acq_T_22 = _needs_second_acq_T_4 | _needs_second_acq_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _needs_second_acq_T_24 = _needs_second_acq_T_22 | _needs_second_acq_T_23; // @[Consts.scala:90:76, :91:{47,54}]
wire _needs_second_acq_T_26 = _needs_second_acq_T_24 | _needs_second_acq_T_25; // @[Consts.scala:91:{47,64,71}]
wire _needs_second_acq_T_29 = _needs_second_acq_T_27 | _needs_second_acq_T_28; // @[Consts.scala:90:{32,42,49}]
wire _needs_second_acq_T_31 = _needs_second_acq_T_29 | _needs_second_acq_T_30; // @[Consts.scala:90:{42,59,66}]
wire _needs_second_acq_T_36 = _needs_second_acq_T_32 | _needs_second_acq_T_33; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_37 = _needs_second_acq_T_36 | _needs_second_acq_T_34; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_38 = _needs_second_acq_T_37 | _needs_second_acq_T_35; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_44 = _needs_second_acq_T_39 | _needs_second_acq_T_40; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_45 = _needs_second_acq_T_44 | _needs_second_acq_T_41; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_46 = _needs_second_acq_T_45 | _needs_second_acq_T_42; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_47 = _needs_second_acq_T_46 | _needs_second_acq_T_43; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_48 = _needs_second_acq_T_38 | _needs_second_acq_T_47; // @[package.scala:81:59]
wire _needs_second_acq_T_49 = _needs_second_acq_T_31 | _needs_second_acq_T_48; // @[Consts.scala:87:44, :90:{59,76}]
wire _needs_second_acq_T_51 = _needs_second_acq_T_49 | _needs_second_acq_T_50; // @[Consts.scala:90:76, :91:{47,54}]
wire _needs_second_acq_T_53 = _needs_second_acq_T_51 | _needs_second_acq_T_52; // @[Consts.scala:91:{47,64,71}]
wire _needs_second_acq_T_54 = ~_needs_second_acq_T_53; // @[Metadata.scala:104:57]
wire cmd_requires_second_acquire = _needs_second_acq_T_26 & _needs_second_acq_T_54; // @[Metadata.scala:104:{54,57}]
wire is_hit_again = r1_1 & r2_1; // @[Misc.scala:35:9]
wire _dirties_cat_T_2 = _dirties_cat_T | _dirties_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _dirties_cat_T_4 = _dirties_cat_T_2 | _dirties_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _dirties_cat_T_9 = _dirties_cat_T_5 | _dirties_cat_T_6; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_10 = _dirties_cat_T_9 | _dirties_cat_T_7; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_11 = _dirties_cat_T_10 | _dirties_cat_T_8; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_17 = _dirties_cat_T_12 | _dirties_cat_T_13; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_18 = _dirties_cat_T_17 | _dirties_cat_T_14; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_19 = _dirties_cat_T_18 | _dirties_cat_T_15; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_20 = _dirties_cat_T_19 | _dirties_cat_T_16; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_21 = _dirties_cat_T_11 | _dirties_cat_T_20; // @[package.scala:81:59]
wire _dirties_cat_T_22 = _dirties_cat_T_4 | _dirties_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _dirties_cat_T_25 = _dirties_cat_T_23 | _dirties_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _dirties_cat_T_27 = _dirties_cat_T_25 | _dirties_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _dirties_cat_T_32 = _dirties_cat_T_28 | _dirties_cat_T_29; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_33 = _dirties_cat_T_32 | _dirties_cat_T_30; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_34 = _dirties_cat_T_33 | _dirties_cat_T_31; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_40 = _dirties_cat_T_35 | _dirties_cat_T_36; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_41 = _dirties_cat_T_40 | _dirties_cat_T_37; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_42 = _dirties_cat_T_41 | _dirties_cat_T_38; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_43 = _dirties_cat_T_42 | _dirties_cat_T_39; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_44 = _dirties_cat_T_34 | _dirties_cat_T_43; // @[package.scala:81:59]
wire _dirties_cat_T_45 = _dirties_cat_T_27 | _dirties_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _dirties_cat_T_47 = _dirties_cat_T_45 | _dirties_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _dirties_cat_T_49 = _dirties_cat_T_47 | _dirties_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] dirties_cat = {_dirties_cat_T_22, _dirties_cat_T_49}; // @[Metadata.scala:29:18]
wire dirties = &dirties_cat; // @[Metadata.scala:29:18, :106:42]
wire [1:0] biggest_grow_param = dirties ? r2_2 : r1_2; // @[Misc.scala:35:36]
wire [1:0] dirtier_coh_state = biggest_grow_param; // @[Metadata.scala:107:33, :160:20]
wire [4:0] dirtier_cmd = dirties ? io_req_uop_mem_cmd_0 : req_uop_mem_cmd; // @[Metadata.scala:106:42, :109:27]
wire _T_16 = io_mem_grant_ready_0 & io_mem_grant_valid_0; // @[Decoupled.scala:51:35]
wire [26:0] _r_beats1_decode_T = 27'hFFF << io_mem_grant_bits_size_0; // @[package.scala:243:71]
wire [11:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] r_beats1_decode = _r_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire r_beats1_opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36]
wire opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36]
wire grant_had_data_opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36]
wire [8:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] r_counter; // @[Edges.scala:229:27]
wire [9:0] _r_counter1_T = {1'h0, r_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] r_counter1 = _r_counter1_T[8:0]; // @[Edges.scala:230:28]
wire r_1_1 = r_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _r_last_T = r_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _r_last_T_1 = r_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire r_2 = _r_last_T | _r_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire refill_done = r_2 & _T_16; // @[Decoupled.scala:51:35]
wire [8:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] r_4 = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _r_counter_T = r_1_1 ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] refill_address_inc = {r_4, 3'h0}; // @[Edges.scala:234:25, :269:29]
wire _sec_rdy_T = ~cmd_requires_second_acquire; // @[Metadata.scala:104:54]
wire _sec_rdy_T_1 = ~io_req_is_probe_0; // @[mshrs.scala:36:7, :125:50]
wire _sec_rdy_T_2 = _sec_rdy_T & _sec_rdy_T_1; // @[mshrs.scala:125:{18,47,50}]
wire _sec_rdy_T_3 = ~(|state); // @[package.scala:16:47]
wire _sec_rdy_T_4 = state == 5'hD; // @[package.scala:16:47]
wire _sec_rdy_T_5 = state == 5'hE; // @[package.scala:16:47]
wire _sec_rdy_T_6 = state == 5'hF; // @[package.scala:16:47]
wire _sec_rdy_T_7 = _sec_rdy_T_3 | _sec_rdy_T_4; // @[package.scala:16:47, :81:59]
wire _sec_rdy_T_8 = _sec_rdy_T_7 | _sec_rdy_T_5; // @[package.scala:16:47, :81:59]
wire _sec_rdy_T_9 = _sec_rdy_T_8 | _sec_rdy_T_6; // @[package.scala:16:47, :81:59]
wire _sec_rdy_T_10 = ~_sec_rdy_T_9; // @[package.scala:81:59]
wire sec_rdy = _sec_rdy_T_2 & _sec_rdy_T_10; // @[mshrs.scala:125:{47,67}, :126:18]
wire _rpq_io_enq_valid_T = io_req_pri_val_0 & io_req_pri_rdy_0; // @[mshrs.scala:36:7, :133:40]
wire _rpq_io_enq_valid_T_1 = io_req_sec_val_0 & io_req_sec_rdy_0; // @[mshrs.scala:36:7, :133:78]
wire _rpq_io_enq_valid_T_2 = _rpq_io_enq_valid_T | _rpq_io_enq_valid_T_1; // @[mshrs.scala:133:{40,59,78}]
wire _rpq_io_enq_valid_T_3 = io_req_uop_mem_cmd_0 == 5'h2; // @[Consts.scala:88:35]
wire _rpq_io_enq_valid_T_5 = _rpq_io_enq_valid_T_3 | _rpq_io_enq_valid_T_4; // @[Consts.scala:88:{35,45,52}]
wire _rpq_io_enq_valid_T_6 = ~_rpq_io_enq_valid_T_5; // @[Consts.scala:88:45]
wire _rpq_io_enq_valid_T_7 = _rpq_io_enq_valid_T_2 & _rpq_io_enq_valid_T_6; // @[mshrs.scala:133:{59,98,101}]
reg grantack_valid; // @[mshrs.scala:138:21]
reg [2:0] grantack_bits_sink; // @[mshrs.scala:138:21]
assign io_mem_finish_bits_sink_0 = grantack_bits_sink; // @[mshrs.scala:36:7, :138:21]
reg [2:0] refill_ctr; // @[mshrs.scala:139:24]
reg commit_line; // @[mshrs.scala:140:24]
reg grant_had_data; // @[mshrs.scala:141:27]
reg finish_to_prefetch; // @[mshrs.scala:142:31]
reg [1:0] meta_hazard; // @[mshrs.scala:145:28]
wire [2:0] _meta_hazard_T = {1'h0, meta_hazard} + 3'h1; // @[mshrs.scala:145:28, :146:59]
wire [1:0] _meta_hazard_T_1 = _meta_hazard_T[1:0]; // @[mshrs.scala:146:59]
wire _io_probe_rdy_T = meta_hazard == 2'h0; // @[mshrs.scala:145:28, :148:34]
wire _io_probe_rdy_T_1 = ~(|state); // @[package.scala:16:47]
wire _io_probe_rdy_T_2 = state == 5'h1; // @[package.scala:16:47]
wire _io_probe_rdy_T_3 = state == 5'h2; // @[package.scala:16:47]
wire _io_probe_rdy_T_4 = state == 5'h3; // @[package.scala:16:47]
wire _io_probe_rdy_T_5 = _io_probe_rdy_T_1 | _io_probe_rdy_T_2; // @[package.scala:16:47, :81:59]
wire _io_probe_rdy_T_6 = _io_probe_rdy_T_5 | _io_probe_rdy_T_3; // @[package.scala:16:47, :81:59]
wire _io_probe_rdy_T_7 = _io_probe_rdy_T_6 | _io_probe_rdy_T_4; // @[package.scala:16:47, :81:59]
wire _io_probe_rdy_T_8 = state == 5'h4; // @[mshrs.scala:107:22, :148:129]
wire _io_probe_rdy_T_9 = _io_probe_rdy_T_8 & grantack_valid; // @[mshrs.scala:138:21, :148:{129,145}]
wire _io_probe_rdy_T_10 = _io_probe_rdy_T_7 | _io_probe_rdy_T_9; // @[package.scala:81:59]
assign _io_probe_rdy_T_11 = _io_probe_rdy_T & _io_probe_rdy_T_10; // @[mshrs.scala:148:{34,42,119}]
assign io_probe_rdy_0 = _io_probe_rdy_T_11; // @[mshrs.scala:36:7, :148:42]
assign _io_idx_valid_T = |state; // @[package.scala:16:47]
assign io_idx_valid_0 = _io_idx_valid_T; // @[mshrs.scala:36:7, :149:25]
assign _io_tag_valid_T = |state; // @[package.scala:16:47]
assign io_tag_valid_0 = _io_tag_valid_T; // @[mshrs.scala:36:7, :150:25]
wire _io_way_valid_T = ~(|state); // @[package.scala:16:47]
wire _io_way_valid_T_1 = state == 5'h11; // @[package.scala:16:47]
wire _io_way_valid_T_2 = _io_way_valid_T | _io_way_valid_T_1; // @[package.scala:16:47, :81:59]
assign _io_way_valid_T_3 = ~_io_way_valid_T_2; // @[package.scala:81:59]
assign io_way_valid_0 = _io_way_valid_T_3; // @[mshrs.scala:36:7, :151:19]
assign io_meta_write_bits_tag_0 = req_tag[21:0]; // @[mshrs.scala:36:7, :111:26, :159:31]
assign io_meta_write_bits_data_tag_0 = req_tag[21:0]; // @[mshrs.scala:36:7, :111:26, :159:31]
assign io_meta_read_bits_tag_0 = req_tag[21:0]; // @[mshrs.scala:36:7, :111:26, :159:31]
assign _io_req_sec_rdy_T = sec_rdy & _rpq_io_enq_ready; // @[mshrs.scala:125:67, :128:19, :163:37]
assign io_req_sec_rdy_0 = _io_req_sec_rdy_T; // @[mshrs.scala:36:7, :163:37]
wire [27:0] _GEN_27 = {req_tag, req_idx}; // @[mshrs.scala:110:25, :111:26, :168:26]
wire [27:0] _io_mem_acquire_bits_T; // @[mshrs.scala:168:26]
assign _io_mem_acquire_bits_T = _GEN_27; // @[mshrs.scala:168:26]
wire [27:0] rp_addr_hi; // @[mshrs.scala:271:22]
assign rp_addr_hi = _GEN_27; // @[mshrs.scala:168:26, :271:22]
wire [27:0] hi; // @[mshrs.scala:276:10]
assign hi = _GEN_27; // @[mshrs.scala:168:26, :276:10]
wire [27:0] io_replay_bits_addr_hi; // @[mshrs.scala:341:31]
assign io_replay_bits_addr_hi = _GEN_27; // @[mshrs.scala:168:26, :341:31]
wire [33:0] _io_mem_acquire_bits_T_1 = {_io_mem_acquire_bits_T, 6'h0}; // @[mshrs.scala:168:{26,45}]
wire [33:0] _io_mem_acquire_bits_legal_T_1 = _io_mem_acquire_bits_T_1; // @[Parameters.scala:137:31]
wire [34:0] _io_mem_acquire_bits_legal_T_2 = {1'h0, _io_mem_acquire_bits_legal_T_1}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _io_mem_acquire_bits_legal_T_3 = _io_mem_acquire_bits_legal_T_2 & 35'h80000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _io_mem_acquire_bits_legal_T_4 = _io_mem_acquire_bits_legal_T_3; // @[Parameters.scala:137:46]
wire _io_mem_acquire_bits_legal_T_5 = _io_mem_acquire_bits_legal_T_4 == 35'h0; // @[Parameters.scala:137:{46,59}]
assign io_mem_acquire_bits_a_address = _io_mem_acquire_bits_T_1[31:0]; // @[Edges.scala:346:17]
wire [33:0] _io_mem_acquire_bits_legal_T_9 = {_io_mem_acquire_bits_T_1[33:32], io_mem_acquire_bits_a_address ^ 32'h80000000}; // @[Edges.scala:346:17]
wire [34:0] _io_mem_acquire_bits_legal_T_10 = {1'h0, _io_mem_acquire_bits_legal_T_9}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _io_mem_acquire_bits_legal_T_11 = _io_mem_acquire_bits_legal_T_10 & 35'h80000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _io_mem_acquire_bits_legal_T_12 = _io_mem_acquire_bits_legal_T_11; // @[Parameters.scala:137:46]
wire _io_mem_acquire_bits_legal_T_13 = _io_mem_acquire_bits_legal_T_12 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _io_mem_acquire_bits_legal_T_14 = _io_mem_acquire_bits_legal_T_13; // @[Parameters.scala:684:54]
wire io_mem_acquire_bits_legal = _io_mem_acquire_bits_legal_T_14; // @[Parameters.scala:684:54, :686:26]
assign io_mem_acquire_bits_param_0 = io_mem_acquire_bits_a_param; // @[Edges.scala:346:17]
assign io_mem_acquire_bits_address_0 = io_mem_acquire_bits_a_address; // @[Edges.scala:346:17]
assign io_mem_acquire_bits_a_param = {1'h0, grow_param}; // @[Misc.scala:35:36]
wire io_mem_acquire_bits_a_mask_sub_sub_bit = _io_mem_acquire_bits_T_1[2]; // @[Misc.scala:210:26]
wire io_mem_acquire_bits_a_mask_sub_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire io_mem_acquire_bits_a_mask_sub_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire io_mem_acquire_bits_a_mask_sub_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T = io_mem_acquire_bits_a_mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38]
wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1 = io_mem_acquire_bits_a_mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_sub_bit = _io_mem_acquire_bits_T_1[1]; // @[Misc.scala:210:26]
wire io_mem_acquire_bits_a_mask_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire io_mem_acquire_bits_a_mask_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire io_mem_acquire_bits_a_mask_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire io_mem_acquire_bits_a_mask_sub_2_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire io_mem_acquire_bits_a_mask_sub_3_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire io_mem_acquire_bits_a_mask_bit = _io_mem_acquire_bits_T_1[0]; // @[Misc.scala:210:26]
wire io_mem_acquire_bits_a_mask_nbit = ~io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :211:20]
wire io_mem_acquire_bits_a_mask_eq = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T = io_mem_acquire_bits_a_mask_eq; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_1 = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_1 = io_mem_acquire_bits_a_mask_eq_1; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_2 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_2 = io_mem_acquire_bits_a_mask_eq_2; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_3 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_3 = io_mem_acquire_bits_a_mask_eq_3; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_4 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_4 = io_mem_acquire_bits_a_mask_eq_4; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_5 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_5 = io_mem_acquire_bits_a_mask_eq_5; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_6 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_6 = io_mem_acquire_bits_a_mask_eq_6; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_7 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_7 = io_mem_acquire_bits_a_mask_eq_7; // @[Misc.scala:214:27, :215:38]
wire [5:0] _io_refill_bits_addr_T = {refill_ctr, 3'h0}; // @[mshrs.scala:139:24, :172:57]
wire [33:0] _io_refill_bits_addr_T_1 = {req_block_addr[33:6], req_block_addr[5:0] | _io_refill_bits_addr_T}; // @[mshrs.scala:112:51, :172:{43,57}]
assign io_refill_bits_addr_0 = _io_refill_bits_addr_T_1[9:0]; // @[mshrs.scala:36:7, :172:{25,43}]
wire [8:0] _io_lb_write_bits_offset_T = refill_address_inc[11:3]; // @[Edges.scala:269:29]
assign io_lb_write_bits_offset_0 = _io_lb_write_bits_offset_T[2:0]; // @[mshrs.scala:36:7, :197:{27,49}]
wire [30:0] _io_lb_read_offset_T = _rpq_io_deq_bits_addr[33:3]; // @[mshrs.scala:128:19, :200:45]
wire [30:0] _io_lb_read_offset_T_1 = _rpq_io_deq_bits_addr[33:3]; // @[mshrs.scala:128:19, :200:45, :282:47]
wire [4:0] state_new_state; // @[mshrs.scala:210:29]
wire _state_T_1 = ~_state_T; // @[mshrs.scala:213:11]
wire _state_T_2 = ~_rpq_io_enq_ready; // @[mshrs.scala:128:19, :213:11]
wire [3:0] _GEN_28 = {2'h2, io_req_old_meta_coh_state_0}; // @[Metadata.scala:120:19]
wire [3:0] _state_req_needs_wb_r_T_6; // @[Metadata.scala:120:19]
assign _state_req_needs_wb_r_T_6 = _GEN_28; // @[Metadata.scala:120:19]
wire [3:0] _state_req_needs_wb_r_T_70; // @[Metadata.scala:120:19]
assign _state_req_needs_wb_r_T_70 = _GEN_28; // @[Metadata.scala:120:19]
wire _state_req_needs_wb_r_T_19 = _state_req_needs_wb_r_T_6 == 4'h8; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_21 = _state_req_needs_wb_r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_23 = _state_req_needs_wb_r_T_6 == 4'h9; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_25 = _state_req_needs_wb_r_T_23 ? 3'h2 : _state_req_needs_wb_r_T_21; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_27 = _state_req_needs_wb_r_T_6 == 4'hA; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_29 = _state_req_needs_wb_r_T_27 ? 3'h1 : _state_req_needs_wb_r_T_25; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_31 = _state_req_needs_wb_r_T_6 == 4'hB; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_32 = _state_req_needs_wb_r_T_31; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_33 = _state_req_needs_wb_r_T_31 ? 3'h1 : _state_req_needs_wb_r_T_29; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_35 = _state_req_needs_wb_r_T_6 == 4'h4; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_36 = ~_state_req_needs_wb_r_T_35 & _state_req_needs_wb_r_T_32; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_37 = _state_req_needs_wb_r_T_35 ? 3'h5 : _state_req_needs_wb_r_T_33; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_39 = _state_req_needs_wb_r_T_6 == 4'h5; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_40 = ~_state_req_needs_wb_r_T_39 & _state_req_needs_wb_r_T_36; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_41 = _state_req_needs_wb_r_T_39 ? 3'h4 : _state_req_needs_wb_r_T_37; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_42 = {1'h0, _state_req_needs_wb_r_T_39}; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_43 = _state_req_needs_wb_r_T_6 == 4'h6; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_44 = ~_state_req_needs_wb_r_T_43 & _state_req_needs_wb_r_T_40; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_45 = _state_req_needs_wb_r_T_43 ? 3'h0 : _state_req_needs_wb_r_T_41; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_46 = _state_req_needs_wb_r_T_43 ? 2'h1 : _state_req_needs_wb_r_T_42; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_47 = _state_req_needs_wb_r_T_6 == 4'h7; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_48 = _state_req_needs_wb_r_T_47 | _state_req_needs_wb_r_T_44; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_49 = _state_req_needs_wb_r_T_47 ? 3'h0 : _state_req_needs_wb_r_T_45; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_50 = _state_req_needs_wb_r_T_47 ? 2'h1 : _state_req_needs_wb_r_T_46; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_51 = _state_req_needs_wb_r_T_6 == 4'h0; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_52 = ~_state_req_needs_wb_r_T_51 & _state_req_needs_wb_r_T_48; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_53 = _state_req_needs_wb_r_T_51 ? 3'h5 : _state_req_needs_wb_r_T_49; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_54 = _state_req_needs_wb_r_T_51 ? 2'h0 : _state_req_needs_wb_r_T_50; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_55 = _state_req_needs_wb_r_T_6 == 4'h1; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_56 = ~_state_req_needs_wb_r_T_55 & _state_req_needs_wb_r_T_52; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_57 = _state_req_needs_wb_r_T_55 ? 3'h4 : _state_req_needs_wb_r_T_53; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_58 = _state_req_needs_wb_r_T_55 ? 2'h1 : _state_req_needs_wb_r_T_54; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_59 = _state_req_needs_wb_r_T_6 == 4'h2; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_60 = ~_state_req_needs_wb_r_T_59 & _state_req_needs_wb_r_T_56; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_61 = _state_req_needs_wb_r_T_59 ? 3'h3 : _state_req_needs_wb_r_T_57; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_62 = _state_req_needs_wb_r_T_59 ? 2'h2 : _state_req_needs_wb_r_T_58; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_63 = _state_req_needs_wb_r_T_6 == 4'h3; // @[Misc.scala:56:20]
wire state_req_needs_wb_r_1 = _state_req_needs_wb_r_T_63 | _state_req_needs_wb_r_T_60; // @[Misc.scala:38:9, :56:20]
wire [2:0] state_req_needs_wb_r_2 = _state_req_needs_wb_r_T_63 ? 3'h3 : _state_req_needs_wb_r_T_61; // @[Misc.scala:38:36, :56:20]
wire [1:0] state_req_needs_wb_r_3 = _state_req_needs_wb_r_T_63 ? 2'h2 : _state_req_needs_wb_r_T_62; // @[Misc.scala:38:63, :56:20]
wire [1:0] state_req_needs_wb_meta_state = state_req_needs_wb_r_3; // @[Misc.scala:38:63]
wire _state_r_c_cat_T_2 = _state_r_c_cat_T | _state_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _state_r_c_cat_T_4 = _state_r_c_cat_T_2 | _state_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _state_r_c_cat_T_9 = _state_r_c_cat_T_5 | _state_r_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_10 = _state_r_c_cat_T_9 | _state_r_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_11 = _state_r_c_cat_T_10 | _state_r_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_17 = _state_r_c_cat_T_12 | _state_r_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_18 = _state_r_c_cat_T_17 | _state_r_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_19 = _state_r_c_cat_T_18 | _state_r_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_20 = _state_r_c_cat_T_19 | _state_r_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_21 = _state_r_c_cat_T_11 | _state_r_c_cat_T_20; // @[package.scala:81:59]
wire _state_r_c_cat_T_22 = _state_r_c_cat_T_4 | _state_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_r_c_cat_T_25 = _state_r_c_cat_T_23 | _state_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _state_r_c_cat_T_27 = _state_r_c_cat_T_25 | _state_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _state_r_c_cat_T_32 = _state_r_c_cat_T_28 | _state_r_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_33 = _state_r_c_cat_T_32 | _state_r_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_34 = _state_r_c_cat_T_33 | _state_r_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_40 = _state_r_c_cat_T_35 | _state_r_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_41 = _state_r_c_cat_T_40 | _state_r_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_42 = _state_r_c_cat_T_41 | _state_r_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_43 = _state_r_c_cat_T_42 | _state_r_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_44 = _state_r_c_cat_T_34 | _state_r_c_cat_T_43; // @[package.scala:81:59]
wire _state_r_c_cat_T_45 = _state_r_c_cat_T_27 | _state_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_r_c_cat_T_47 = _state_r_c_cat_T_45 | _state_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _state_r_c_cat_T_49 = _state_r_c_cat_T_47 | _state_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] state_r_c = {_state_r_c_cat_T_22, _state_r_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _state_r_T = {state_r_c, io_req_old_meta_coh_state_0}; // @[Metadata.scala:29:18, :58:19]
wire _state_r_T_25 = _state_r_T == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_27 = {1'h0, _state_r_T_25}; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_28 = _state_r_T == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_30 = _state_r_T_28 ? 2'h2 : _state_r_T_27; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_31 = _state_r_T == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_33 = _state_r_T_31 ? 2'h1 : _state_r_T_30; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_34 = _state_r_T == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_36 = _state_r_T_34 ? 2'h2 : _state_r_T_33; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_37 = _state_r_T == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_39 = _state_r_T_37 ? 2'h0 : _state_r_T_36; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_40 = _state_r_T == 4'hE; // @[Misc.scala:49:20]
wire _state_r_T_41 = _state_r_T_40; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_42 = _state_r_T_40 ? 2'h3 : _state_r_T_39; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_43 = &_state_r_T; // @[Misc.scala:49:20]
wire _state_r_T_44 = _state_r_T_43 | _state_r_T_41; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_45 = _state_r_T_43 ? 2'h3 : _state_r_T_42; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_46 = _state_r_T == 4'h6; // @[Misc.scala:49:20]
wire _state_r_T_47 = _state_r_T_46 | _state_r_T_44; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_48 = _state_r_T_46 ? 2'h2 : _state_r_T_45; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_49 = _state_r_T == 4'h7; // @[Misc.scala:49:20]
wire _state_r_T_50 = _state_r_T_49 | _state_r_T_47; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_51 = _state_r_T_49 ? 2'h3 : _state_r_T_48; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_52 = _state_r_T == 4'h1; // @[Misc.scala:49:20]
wire _state_r_T_53 = _state_r_T_52 | _state_r_T_50; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_54 = _state_r_T_52 ? 2'h1 : _state_r_T_51; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_55 = _state_r_T == 4'h2; // @[Misc.scala:49:20]
wire _state_r_T_56 = _state_r_T_55 | _state_r_T_53; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_57 = _state_r_T_55 ? 2'h2 : _state_r_T_54; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_58 = _state_r_T == 4'h3; // @[Misc.scala:49:20]
wire state_is_hit = _state_r_T_58 | _state_r_T_56; // @[Misc.scala:35:9, :49:20]
wire [1:0] state_r_2 = _state_r_T_58 ? 2'h3 : _state_r_T_57; // @[Misc.scala:35:36, :49:20]
wire [1:0] state_coh_on_hit_state = state_r_2; // @[Misc.scala:35:36]
wire _state_T_5 = _state_T_3 | _state_T_4; // @[Consts.scala:90:{32,42,49}]
wire _state_T_7 = _state_T_5 | _state_T_6; // @[Consts.scala:90:{42,59,66}]
wire _state_T_12 = _state_T_8 | _state_T_9; // @[package.scala:16:47, :81:59]
wire _state_T_13 = _state_T_12 | _state_T_10; // @[package.scala:16:47, :81:59]
wire _state_T_14 = _state_T_13 | _state_T_11; // @[package.scala:16:47, :81:59]
wire _state_T_20 = _state_T_15 | _state_T_16; // @[package.scala:16:47, :81:59]
wire _state_T_21 = _state_T_20 | _state_T_17; // @[package.scala:16:47, :81:59]
wire _state_T_22 = _state_T_21 | _state_T_18; // @[package.scala:16:47, :81:59]
wire _state_T_23 = _state_T_22 | _state_T_19; // @[package.scala:16:47, :81:59]
wire _state_T_24 = _state_T_14 | _state_T_23; // @[package.scala:81:59]
wire _state_T_25 = _state_T_7 | _state_T_24; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_T_27 = ~_state_T_26; // @[mshrs.scala:220:15]
wire _state_T_28 = ~_state_T_25; // @[Consts.scala:90:76]
assign state_new_state = io_req_tag_match_0 & state_is_hit ? 5'hC : 5'h1; // @[Misc.scala:35:9]
assign io_mem_acquire_valid_0 = (|state) & _io_probe_rdy_T_2; // @[package.scala:16:47]
wire _GEN_29 = ~(|state) | _io_probe_rdy_T_2; // @[package.scala:16:47]
assign io_lb_write_valid_0 = ~_GEN_29 & _io_probe_rdy_T_3 & opdata & io_mem_grant_valid_0; // @[package.scala:16:47]
assign io_mem_grant_ready_0 = ~_GEN_29 & _io_probe_rdy_T_3; // @[package.scala:16:47]
wire _grantack_valid_T = io_mem_grant_bits_opcode_0[2]; // @[Edges.scala:71:36]
wire _grantack_valid_T_1 = io_mem_grant_bits_opcode_0[1]; // @[Edges.scala:71:52]
wire _grantack_valid_T_2 = ~_grantack_valid_T_1; // @[Edges.scala:71:{43,52}]
wire _grantack_valid_T_3 = _grantack_valid_T & _grantack_valid_T_2; // @[Edges.scala:71:{36,40,43}]
wire [4:0] _state_T_29 = grant_had_data ? 5'h3 : 5'hC; // @[mshrs.scala:141:27, :260:19]
wire _drain_load_T = _rpq_io_deq_bits_uop_mem_cmd == 5'h0; // @[package.scala:16:47]
wire _drain_load_T_1 = _rpq_io_deq_bits_uop_mem_cmd == 5'h10; // @[package.scala:16:47]
wire _GEN_30 = _rpq_io_deq_bits_uop_mem_cmd == 5'h6; // @[package.scala:16:47]
wire _drain_load_T_2; // @[package.scala:16:47]
assign _drain_load_T_2 = _GEN_30; // @[package.scala:16:47]
wire _r_c_cat_T_48; // @[Consts.scala:91:71]
assign _r_c_cat_T_48 = _GEN_30; // @[package.scala:16:47]
wire _GEN_31 = _rpq_io_deq_bits_uop_mem_cmd == 5'h7; // @[package.scala:16:47]
wire _drain_load_T_3; // @[package.scala:16:47]
assign _drain_load_T_3 = _GEN_31; // @[package.scala:16:47]
wire _drain_load_T_28; // @[Consts.scala:90:66]
assign _drain_load_T_28 = _GEN_31; // @[package.scala:16:47]
wire _drain_load_T_4 = _drain_load_T | _drain_load_T_1; // @[package.scala:16:47, :81:59]
wire _drain_load_T_5 = _drain_load_T_4 | _drain_load_T_2; // @[package.scala:16:47, :81:59]
wire _drain_load_T_6 = _drain_load_T_5 | _drain_load_T_3; // @[package.scala:16:47, :81:59]
wire _GEN_32 = _rpq_io_deq_bits_uop_mem_cmd == 5'h4; // @[package.scala:16:47]
wire _drain_load_T_7; // @[package.scala:16:47]
assign _drain_load_T_7 = _GEN_32; // @[package.scala:16:47]
wire _drain_load_T_30; // @[package.scala:16:47]
assign _drain_load_T_30 = _GEN_32; // @[package.scala:16:47]
wire _GEN_33 = _rpq_io_deq_bits_uop_mem_cmd == 5'h9; // @[package.scala:16:47]
wire _drain_load_T_8; // @[package.scala:16:47]
assign _drain_load_T_8 = _GEN_33; // @[package.scala:16:47]
wire _drain_load_T_31; // @[package.scala:16:47]
assign _drain_load_T_31 = _GEN_33; // @[package.scala:16:47]
wire _GEN_34 = _rpq_io_deq_bits_uop_mem_cmd == 5'hA; // @[package.scala:16:47]
wire _drain_load_T_9; // @[package.scala:16:47]
assign _drain_load_T_9 = _GEN_34; // @[package.scala:16:47]
wire _drain_load_T_32; // @[package.scala:16:47]
assign _drain_load_T_32 = _GEN_34; // @[package.scala:16:47]
wire _GEN_35 = _rpq_io_deq_bits_uop_mem_cmd == 5'hB; // @[package.scala:16:47]
wire _drain_load_T_10; // @[package.scala:16:47]
assign _drain_load_T_10 = _GEN_35; // @[package.scala:16:47]
wire _drain_load_T_33; // @[package.scala:16:47]
assign _drain_load_T_33 = _GEN_35; // @[package.scala:16:47]
wire _drain_load_T_11 = _drain_load_T_7 | _drain_load_T_8; // @[package.scala:16:47, :81:59]
wire _drain_load_T_12 = _drain_load_T_11 | _drain_load_T_9; // @[package.scala:16:47, :81:59]
wire _drain_load_T_13 = _drain_load_T_12 | _drain_load_T_10; // @[package.scala:16:47, :81:59]
wire _GEN_36 = _rpq_io_deq_bits_uop_mem_cmd == 5'h8; // @[package.scala:16:47]
wire _drain_load_T_14; // @[package.scala:16:47]
assign _drain_load_T_14 = _GEN_36; // @[package.scala:16:47]
wire _drain_load_T_37; // @[package.scala:16:47]
assign _drain_load_T_37 = _GEN_36; // @[package.scala:16:47]
wire _GEN_37 = _rpq_io_deq_bits_uop_mem_cmd == 5'hC; // @[package.scala:16:47]
wire _drain_load_T_15; // @[package.scala:16:47]
assign _drain_load_T_15 = _GEN_37; // @[package.scala:16:47]
wire _drain_load_T_38; // @[package.scala:16:47]
assign _drain_load_T_38 = _GEN_37; // @[package.scala:16:47]
wire _GEN_38 = _rpq_io_deq_bits_uop_mem_cmd == 5'hD; // @[package.scala:16:47]
wire _drain_load_T_16; // @[package.scala:16:47]
assign _drain_load_T_16 = _GEN_38; // @[package.scala:16:47]
wire _drain_load_T_39; // @[package.scala:16:47]
assign _drain_load_T_39 = _GEN_38; // @[package.scala:16:47]
wire _GEN_39 = _rpq_io_deq_bits_uop_mem_cmd == 5'hE; // @[package.scala:16:47]
wire _drain_load_T_17; // @[package.scala:16:47]
assign _drain_load_T_17 = _GEN_39; // @[package.scala:16:47]
wire _drain_load_T_40; // @[package.scala:16:47]
assign _drain_load_T_40 = _GEN_39; // @[package.scala:16:47]
wire _GEN_40 = _rpq_io_deq_bits_uop_mem_cmd == 5'hF; // @[package.scala:16:47]
wire _drain_load_T_18; // @[package.scala:16:47]
assign _drain_load_T_18 = _GEN_40; // @[package.scala:16:47]
wire _drain_load_T_41; // @[package.scala:16:47]
assign _drain_load_T_41 = _GEN_40; // @[package.scala:16:47]
wire _drain_load_T_19 = _drain_load_T_14 | _drain_load_T_15; // @[package.scala:16:47, :81:59]
wire _drain_load_T_20 = _drain_load_T_19 | _drain_load_T_16; // @[package.scala:16:47, :81:59]
wire _drain_load_T_21 = _drain_load_T_20 | _drain_load_T_17; // @[package.scala:16:47, :81:59]
wire _drain_load_T_22 = _drain_load_T_21 | _drain_load_T_18; // @[package.scala:16:47, :81:59]
wire _drain_load_T_23 = _drain_load_T_13 | _drain_load_T_22; // @[package.scala:81:59]
wire _drain_load_T_24 = _drain_load_T_6 | _drain_load_T_23; // @[package.scala:81:59]
wire _drain_load_T_25 = _rpq_io_deq_bits_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32]
wire _drain_load_T_26 = _rpq_io_deq_bits_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49]
wire _drain_load_T_27 = _drain_load_T_25 | _drain_load_T_26; // @[Consts.scala:90:{32,42,49}]
wire _drain_load_T_29 = _drain_load_T_27 | _drain_load_T_28; // @[Consts.scala:90:{42,59,66}]
wire _drain_load_T_34 = _drain_load_T_30 | _drain_load_T_31; // @[package.scala:16:47, :81:59]
wire _drain_load_T_35 = _drain_load_T_34 | _drain_load_T_32; // @[package.scala:16:47, :81:59]
wire _drain_load_T_36 = _drain_load_T_35 | _drain_load_T_33; // @[package.scala:16:47, :81:59]
wire _drain_load_T_42 = _drain_load_T_37 | _drain_load_T_38; // @[package.scala:16:47, :81:59]
wire _drain_load_T_43 = _drain_load_T_42 | _drain_load_T_39; // @[package.scala:16:47, :81:59]
wire _drain_load_T_44 = _drain_load_T_43 | _drain_load_T_40; // @[package.scala:16:47, :81:59]
wire _drain_load_T_45 = _drain_load_T_44 | _drain_load_T_41; // @[package.scala:16:47, :81:59]
wire _drain_load_T_46 = _drain_load_T_36 | _drain_load_T_45; // @[package.scala:81:59]
wire _drain_load_T_47 = _drain_load_T_29 | _drain_load_T_46; // @[Consts.scala:87:44, :90:{59,76}]
wire _drain_load_T_48 = ~_drain_load_T_47; // @[Consts.scala:90:76]
wire _drain_load_T_49 = _drain_load_T_24 & _drain_load_T_48; // @[Consts.scala:89:68]
wire _drain_load_T_50 = _rpq_io_deq_bits_uop_mem_cmd != 5'h6; // @[mshrs.scala:128:19, :269:51]
wire drain_load = _drain_load_T_49 & _drain_load_T_50; // @[mshrs.scala:267:59, :268:60, :269:51]
wire [5:0] _rp_addr_T = _rpq_io_deq_bits_addr[5:0]; // @[mshrs.scala:128:19, :271:61]
wire [33:0] rp_addr = {rp_addr_hi, _rp_addr_T}; // @[mshrs.scala:271:{22,61}]
wire [1:0] size; // @[AMOALU.scala:11:18]
wire _rpq_io_deq_ready_T = io_resp_ready_0 & drain_load; // @[mshrs.scala:36:7, :268:60, :280:40]
wire _io_resp_valid_T = _rpq_io_deq_valid & drain_load; // @[mshrs.scala:128:19, :268:60, :284:43]
wire _GEN_41 = ~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3; // @[package.scala:16:47]
assign io_resp_valid_0 = ~_GEN_41 & _io_probe_rdy_T_4 & _io_resp_valid_T; // @[package.scala:16:47]
wire _io_resp_bits_data_shifted_T = _rpq_io_deq_bits_addr[2]; // @[AMOALU.scala:42:29]
wire [31:0] _io_resp_bits_data_shifted_T_1 = data_word[63:32]; // @[AMOALU.scala:42:37]
wire [31:0] _io_resp_bits_data_T_5 = data_word[63:32]; // @[AMOALU.scala:42:37, :45:94]
wire [31:0] _io_resp_bits_data_shifted_T_2 = data_word[31:0]; // @[AMOALU.scala:42:55]
wire [31:0] io_resp_bits_data_shifted = _io_resp_bits_data_shifted_T ? _io_resp_bits_data_shifted_T_1 : _io_resp_bits_data_shifted_T_2; // @[AMOALU.scala:42:{24,29,37,55}]
wire [31:0] io_resp_bits_data_zeroed = io_resp_bits_data_shifted; // @[AMOALU.scala:42:24, :44:23]
wire _io_resp_bits_data_T = size == 2'h2; // @[AMOALU.scala:11:18, :45:26]
wire _io_resp_bits_data_T_1 = _io_resp_bits_data_T; // @[AMOALU.scala:45:{26,34}]
wire _io_resp_bits_data_T_2 = io_resp_bits_data_zeroed[31]; // @[AMOALU.scala:44:23, :45:81]
wire _io_resp_bits_data_T_3 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_2; // @[AMOALU.scala:45:{72,81}]
wire [31:0] _io_resp_bits_data_T_4 = {32{_io_resp_bits_data_T_3}}; // @[AMOALU.scala:45:{49,72}]
wire [31:0] _io_resp_bits_data_T_6 = _io_resp_bits_data_T_1 ? _io_resp_bits_data_T_4 : _io_resp_bits_data_T_5; // @[AMOALU.scala:45:{20,34,49,94}]
wire [63:0] _io_resp_bits_data_T_7 = {_io_resp_bits_data_T_6, io_resp_bits_data_zeroed}; // @[AMOALU.scala:44:23, :45:{16,20}]
wire _io_resp_bits_data_shifted_T_3 = _rpq_io_deq_bits_addr[1]; // @[AMOALU.scala:42:29]
wire [15:0] _io_resp_bits_data_shifted_T_4 = _io_resp_bits_data_T_7[31:16]; // @[AMOALU.scala:42:37, :45:16]
wire [15:0] _io_resp_bits_data_shifted_T_5 = _io_resp_bits_data_T_7[15:0]; // @[AMOALU.scala:42:55, :45:16]
wire [15:0] io_resp_bits_data_shifted_1 = _io_resp_bits_data_shifted_T_3 ? _io_resp_bits_data_shifted_T_4 : _io_resp_bits_data_shifted_T_5; // @[AMOALU.scala:42:{24,29,37,55}]
wire [15:0] io_resp_bits_data_zeroed_1 = io_resp_bits_data_shifted_1; // @[AMOALU.scala:42:24, :44:23]
wire _io_resp_bits_data_T_8 = size == 2'h1; // @[AMOALU.scala:11:18, :45:26]
wire _io_resp_bits_data_T_9 = _io_resp_bits_data_T_8; // @[AMOALU.scala:45:{26,34}]
wire _io_resp_bits_data_T_10 = io_resp_bits_data_zeroed_1[15]; // @[AMOALU.scala:44:23, :45:81]
wire _io_resp_bits_data_T_11 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_10; // @[AMOALU.scala:45:{72,81}]
wire [47:0] _io_resp_bits_data_T_12 = {48{_io_resp_bits_data_T_11}}; // @[AMOALU.scala:45:{49,72}]
wire [47:0] _io_resp_bits_data_T_13 = _io_resp_bits_data_T_7[63:16]; // @[AMOALU.scala:45:{16,94}]
wire [47:0] _io_resp_bits_data_T_14 = _io_resp_bits_data_T_9 ? _io_resp_bits_data_T_12 : _io_resp_bits_data_T_13; // @[AMOALU.scala:45:{20,34,49,94}]
wire [63:0] _io_resp_bits_data_T_15 = {_io_resp_bits_data_T_14, io_resp_bits_data_zeroed_1}; // @[AMOALU.scala:44:23, :45:{16,20}]
wire _io_resp_bits_data_shifted_T_6 = _rpq_io_deq_bits_addr[0]; // @[AMOALU.scala:42:29]
wire [7:0] _io_resp_bits_data_shifted_T_7 = _io_resp_bits_data_T_15[15:8]; // @[AMOALU.scala:42:37, :45:16]
wire [7:0] _io_resp_bits_data_shifted_T_8 = _io_resp_bits_data_T_15[7:0]; // @[AMOALU.scala:42:55, :45:16]
wire [7:0] io_resp_bits_data_shifted_2 = _io_resp_bits_data_shifted_T_6 ? _io_resp_bits_data_shifted_T_7 : _io_resp_bits_data_shifted_T_8; // @[AMOALU.scala:42:{24,29,37,55}]
wire [7:0] io_resp_bits_data_zeroed_2 = io_resp_bits_data_shifted_2; // @[AMOALU.scala:42:24, :44:23]
wire _io_resp_bits_data_T_16 = size == 2'h0; // @[AMOALU.scala:11:18, :45:26]
wire _io_resp_bits_data_T_17 = _io_resp_bits_data_T_16; // @[AMOALU.scala:45:{26,34}]
wire _io_resp_bits_data_T_18 = io_resp_bits_data_zeroed_2[7]; // @[AMOALU.scala:44:23, :45:81]
wire _io_resp_bits_data_T_19 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_18; // @[AMOALU.scala:45:{72,81}]
wire [55:0] _io_resp_bits_data_T_20 = {56{_io_resp_bits_data_T_19}}; // @[AMOALU.scala:45:{49,72}]
wire [55:0] _io_resp_bits_data_T_21 = _io_resp_bits_data_T_15[63:8]; // @[AMOALU.scala:45:{16,94}]
wire [55:0] _io_resp_bits_data_T_22 = _io_resp_bits_data_T_17 ? _io_resp_bits_data_T_20 : _io_resp_bits_data_T_21; // @[AMOALU.scala:45:{20,34,49,94}]
wire [63:0] _io_resp_bits_data_T_23 = {_io_resp_bits_data_T_22, io_resp_bits_data_zeroed_2}; // @[AMOALU.scala:44:23, :45:{16,20}]
assign io_resp_bits_data_0 = _GEN_41 | ~_io_probe_rdy_T_4 ? _rpq_io_deq_bits_data : _io_resp_bits_data_T_23; // @[package.scala:16:47]
wire _T_26 = rpq_io_deq_ready & _rpq_io_deq_valid; // @[Decoupled.scala:51:35]
wire _T_28 = _rpq_io_empty & ~commit_line; // @[mshrs.scala:128:19, :140:24, :290:{31,34}]
wire _T_33 = _rpq_io_empty | _rpq_io_deq_valid & ~drain_load; // @[mshrs.scala:128:19, :268:60, :296:{31,52,55}]
assign io_commit_val_0 = ~_GEN_41 & _io_probe_rdy_T_4 & ~(_T_26 | _T_28) & _T_33; // @[Decoupled.scala:51:35]
wire _io_meta_read_valid_T = ~io_prober_state_valid_0; // @[mshrs.scala:36:7, :303:27]
wire _io_meta_read_valid_T_1 = ~grantack_valid; // @[mshrs.scala:138:21, :303:53]
wire _io_meta_read_valid_T_2 = _io_meta_read_valid_T | _io_meta_read_valid_T_1; // @[mshrs.scala:303:{27,50,53}]
wire [3:0] _io_meta_read_valid_T_3 = io_prober_state_bits_0[9:6]; // @[mshrs.scala:36:7, :303:93]
wire _io_meta_read_valid_T_4 = _io_meta_read_valid_T_3 != req_idx; // @[mshrs.scala:110:25, :303:{93,120}]
wire _io_meta_read_valid_T_5 = _io_meta_read_valid_T_2 | _io_meta_read_valid_T_4; // @[mshrs.scala:303:{50,69,120}]
assign io_meta_read_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4) & _io_probe_rdy_T_8 & _io_meta_read_valid_T_5; // @[package.scala:16:47]
wire _T_36 = state == 5'h5; // @[mshrs.scala:107:22, :307:22]
wire _T_37 = state == 5'h6; // @[mshrs.scala:107:22, :309:22]
wire [3:0] _needs_wb_r_T_6 = {2'h2, io_meta_resp_bits_coh_state_0}; // @[Metadata.scala:120:19]
wire _needs_wb_r_T_19 = _needs_wb_r_T_6 == 4'h8; // @[Misc.scala:56:20]
wire [2:0] _needs_wb_r_T_21 = _needs_wb_r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20]
wire _needs_wb_r_T_23 = _needs_wb_r_T_6 == 4'h9; // @[Misc.scala:56:20]
wire [2:0] _needs_wb_r_T_25 = _needs_wb_r_T_23 ? 3'h2 : _needs_wb_r_T_21; // @[Misc.scala:38:36, :56:20]
wire _needs_wb_r_T_27 = _needs_wb_r_T_6 == 4'hA; // @[Misc.scala:56:20]
wire [2:0] _needs_wb_r_T_29 = _needs_wb_r_T_27 ? 3'h1 : _needs_wb_r_T_25; // @[Misc.scala:38:36, :56:20]
wire _needs_wb_r_T_31 = _needs_wb_r_T_6 == 4'hB; // @[Misc.scala:56:20]
wire _needs_wb_r_T_32 = _needs_wb_r_T_31; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_33 = _needs_wb_r_T_31 ? 3'h1 : _needs_wb_r_T_29; // @[Misc.scala:38:36, :56:20]
wire _needs_wb_r_T_35 = _needs_wb_r_T_6 == 4'h4; // @[Misc.scala:56:20]
wire _needs_wb_r_T_36 = ~_needs_wb_r_T_35 & _needs_wb_r_T_32; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_37 = _needs_wb_r_T_35 ? 3'h5 : _needs_wb_r_T_33; // @[Misc.scala:38:36, :56:20]
wire _needs_wb_r_T_39 = _needs_wb_r_T_6 == 4'h5; // @[Misc.scala:56:20]
wire _needs_wb_r_T_40 = ~_needs_wb_r_T_39 & _needs_wb_r_T_36; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_41 = _needs_wb_r_T_39 ? 3'h4 : _needs_wb_r_T_37; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_42 = {1'h0, _needs_wb_r_T_39}; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_43 = _needs_wb_r_T_6 == 4'h6; // @[Misc.scala:56:20]
wire _needs_wb_r_T_44 = ~_needs_wb_r_T_43 & _needs_wb_r_T_40; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_45 = _needs_wb_r_T_43 ? 3'h0 : _needs_wb_r_T_41; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_46 = _needs_wb_r_T_43 ? 2'h1 : _needs_wb_r_T_42; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_47 = _needs_wb_r_T_6 == 4'h7; // @[Misc.scala:56:20]
wire _needs_wb_r_T_48 = _needs_wb_r_T_47 | _needs_wb_r_T_44; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_49 = _needs_wb_r_T_47 ? 3'h0 : _needs_wb_r_T_45; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_50 = _needs_wb_r_T_47 ? 2'h1 : _needs_wb_r_T_46; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_51 = _needs_wb_r_T_6 == 4'h0; // @[Misc.scala:56:20]
wire _needs_wb_r_T_52 = ~_needs_wb_r_T_51 & _needs_wb_r_T_48; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_53 = _needs_wb_r_T_51 ? 3'h5 : _needs_wb_r_T_49; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_54 = _needs_wb_r_T_51 ? 2'h0 : _needs_wb_r_T_50; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_55 = _needs_wb_r_T_6 == 4'h1; // @[Misc.scala:56:20]
wire _needs_wb_r_T_56 = ~_needs_wb_r_T_55 & _needs_wb_r_T_52; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_57 = _needs_wb_r_T_55 ? 3'h4 : _needs_wb_r_T_53; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_58 = _needs_wb_r_T_55 ? 2'h1 : _needs_wb_r_T_54; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_59 = _needs_wb_r_T_6 == 4'h2; // @[Misc.scala:56:20]
wire _needs_wb_r_T_60 = ~_needs_wb_r_T_59 & _needs_wb_r_T_56; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_61 = _needs_wb_r_T_59 ? 3'h3 : _needs_wb_r_T_57; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_62 = _needs_wb_r_T_59 ? 2'h2 : _needs_wb_r_T_58; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_63 = _needs_wb_r_T_6 == 4'h3; // @[Misc.scala:56:20]
wire needs_wb = _needs_wb_r_T_63 | _needs_wb_r_T_60; // @[Misc.scala:38:9, :56:20]
wire [2:0] needs_wb_r_2 = _needs_wb_r_T_63 ? 3'h3 : _needs_wb_r_T_61; // @[Misc.scala:38:36, :56:20]
wire [1:0] needs_wb_r_3 = _needs_wb_r_T_63 ? 2'h2 : _needs_wb_r_T_62; // @[Misc.scala:38:63, :56:20]
wire [1:0] needs_wb_meta_state = needs_wb_r_3; // @[Misc.scala:38:63]
wire _state_T_30 = ~io_meta_resp_valid_0; // @[mshrs.scala:36:7, :311:18]
wire [4:0] _state_T_31 = needs_wb ? 5'h7 : 5'hB; // @[Misc.scala:38:9]
wire [4:0] _state_T_32 = _state_T_30 ? 5'h4 : _state_T_31; // @[mshrs.scala:311:{17,18}, :312:17]
wire _T_38 = state == 5'h7; // @[mshrs.scala:107:22, :313:22]
wire _T_40 = state == 5'h9; // @[mshrs.scala:107:22, :319:22]
assign io_wb_req_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38) & _T_40; // @[package.scala:16:47]
wire _T_42 = state == 5'hA; // @[mshrs.scala:107:22, :324:22]
wire _T_43 = state == 5'hB; // @[mshrs.scala:107:22, :328:22]
wire _GEN_42 = _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42; // @[mshrs.scala:148:129, :200:21, :302:39, :307:{22,41}, :309:{22,41}, :313:{22,40}, :319:{22,36}, :324:{22,37}, :328:41]
assign io_lb_read_offset_0 = _GEN_41 ? _io_lb_read_offset_T[2:0] : _io_probe_rdy_T_4 ? _io_lb_read_offset_T_1[2:0] : _GEN_42 | ~_T_43 ? _io_lb_read_offset_T[2:0] : refill_ctr; // @[package.scala:16:47]
wire _GEN_43 = _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4 | _GEN_42; // @[package.scala:16:47]
assign io_refill_valid_0 = ~(~(|state) | _GEN_43) & _T_43; // @[package.scala:16:47]
wire [3:0] _refill_ctr_T = {1'h0, refill_ctr} + 4'h1; // @[mshrs.scala:139:24, :333:32]
wire [2:0] _refill_ctr_T_1 = _refill_ctr_T[2:0]; // @[mshrs.scala:333:32]
wire _T_46 = state == 5'hC; // @[mshrs.scala:107:22, :338:22]
wire _GEN_44 = _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42 | _T_43; // @[mshrs.scala:148:129, :176:26, :302:39, :307:{22,41}, :309:{22,41}, :313:{22,40}, :319:{22,36}, :324:{22,37}, :328:{22,41}, :338:39]
wire _GEN_45 = _io_probe_rdy_T_4 | _GEN_44; // @[package.scala:16:47]
wire _GEN_46 = ~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _GEN_45; // @[package.scala:16:47]
assign io_replay_valid_0 = ~_GEN_46 & _T_46 & _rpq_io_deq_valid; // @[mshrs.scala:36:7, :128:19, :176:26, :234:30, :241:40, :246:41, :266:45, :302:39, :307:41, :309:41, :313:40, :319:36, :324:37, :328:41, :338:{22,39}, :339:15]
assign rpq_io_deq_ready = ~_GEN_41 & (_io_probe_rdy_T_4 ? _rpq_io_deq_ready_T : ~_GEN_44 & _T_46 & io_replay_ready_0); // @[package.scala:16:47]
wire _GEN_47 = _GEN_46 | ~_T_46; // @[mshrs.scala:176:26, :177:26, :234:30, :241:40, :246:41, :266:45, :302:39, :307:41, :309:41, :313:40, :319:36, :324:37, :328:41, :338:{22,39}]
assign io_replay_bits_way_en_0 = _GEN_47 ? _rpq_io_deq_bits_way_en : req_way_en; // @[mshrs.scala:36:7, :109:20, :128:19, :177:26, :234:30, :241:40, :246:41, :266:45, :302:39, :307:41, :309:41, :313:40, :319:36, :324:37, :328:41, :338:39]
wire [5:0] _io_replay_bits_addr_T = _rpq_io_deq_bits_addr[5:0]; // @[mshrs.scala:128:19, :341:70]
wire [33:0] _io_replay_bits_addr_T_1 = {io_replay_bits_addr_hi, _io_replay_bits_addr_T}; // @[mshrs.scala:341:{31,70}]
assign io_replay_bits_addr_0 = _GEN_47 ? _rpq_io_deq_bits_addr : _io_replay_bits_addr_T_1; // @[mshrs.scala:36:7, :128:19, :177:26, :234:30, :241:40, :246:41, :266:45, :302:39, :307:41, :309:41, :313:40, :319:36, :324:37, :328:41, :338:39, :341:31]
wire _T_48 = _rpq_io_deq_bits_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32]
wire _r_c_cat_T; // @[Consts.scala:90:32]
assign _r_c_cat_T = _T_48; // @[Consts.scala:90:32]
wire _r_c_cat_T_23; // @[Consts.scala:90:32]
assign _r_c_cat_T_23 = _T_48; // @[Consts.scala:90:32]
wire _T_49 = _rpq_io_deq_bits_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49]
wire _r_c_cat_T_1; // @[Consts.scala:90:49]
assign _r_c_cat_T_1 = _T_49; // @[Consts.scala:90:49]
wire _r_c_cat_T_24; // @[Consts.scala:90:49]
assign _r_c_cat_T_24 = _T_49; // @[Consts.scala:90:49]
wire _T_51 = _rpq_io_deq_bits_uop_mem_cmd == 5'h7; // @[Consts.scala:90:66]
wire _r_c_cat_T_3; // @[Consts.scala:90:66]
assign _r_c_cat_T_3 = _T_51; // @[Consts.scala:90:66]
wire _r_c_cat_T_26; // @[Consts.scala:90:66]
assign _r_c_cat_T_26 = _T_51; // @[Consts.scala:90:66]
wire _T_53 = _rpq_io_deq_bits_uop_mem_cmd == 5'h4; // @[package.scala:16:47]
wire _r_c_cat_T_5; // @[package.scala:16:47]
assign _r_c_cat_T_5 = _T_53; // @[package.scala:16:47]
wire _r_c_cat_T_28; // @[package.scala:16:47]
assign _r_c_cat_T_28 = _T_53; // @[package.scala:16:47]
wire _T_54 = _rpq_io_deq_bits_uop_mem_cmd == 5'h9; // @[package.scala:16:47]
wire _r_c_cat_T_6; // @[package.scala:16:47]
assign _r_c_cat_T_6 = _T_54; // @[package.scala:16:47]
wire _r_c_cat_T_29; // @[package.scala:16:47]
assign _r_c_cat_T_29 = _T_54; // @[package.scala:16:47]
wire _T_55 = _rpq_io_deq_bits_uop_mem_cmd == 5'hA; // @[package.scala:16:47]
wire _r_c_cat_T_7; // @[package.scala:16:47]
assign _r_c_cat_T_7 = _T_55; // @[package.scala:16:47]
wire _r_c_cat_T_30; // @[package.scala:16:47]
assign _r_c_cat_T_30 = _T_55; // @[package.scala:16:47]
wire _T_56 = _rpq_io_deq_bits_uop_mem_cmd == 5'hB; // @[package.scala:16:47]
wire _r_c_cat_T_8; // @[package.scala:16:47]
assign _r_c_cat_T_8 = _T_56; // @[package.scala:16:47]
wire _r_c_cat_T_31; // @[package.scala:16:47]
assign _r_c_cat_T_31 = _T_56; // @[package.scala:16:47]
wire _T_60 = _rpq_io_deq_bits_uop_mem_cmd == 5'h8; // @[package.scala:16:47]
wire _r_c_cat_T_12; // @[package.scala:16:47]
assign _r_c_cat_T_12 = _T_60; // @[package.scala:16:47]
wire _r_c_cat_T_35; // @[package.scala:16:47]
assign _r_c_cat_T_35 = _T_60; // @[package.scala:16:47]
wire _T_61 = _rpq_io_deq_bits_uop_mem_cmd == 5'hC; // @[package.scala:16:47]
wire _r_c_cat_T_13; // @[package.scala:16:47]
assign _r_c_cat_T_13 = _T_61; // @[package.scala:16:47]
wire _r_c_cat_T_36; // @[package.scala:16:47]
assign _r_c_cat_T_36 = _T_61; // @[package.scala:16:47]
wire _T_62 = _rpq_io_deq_bits_uop_mem_cmd == 5'hD; // @[package.scala:16:47]
wire _r_c_cat_T_14; // @[package.scala:16:47]
assign _r_c_cat_T_14 = _T_62; // @[package.scala:16:47]
wire _r_c_cat_T_37; // @[package.scala:16:47]
assign _r_c_cat_T_37 = _T_62; // @[package.scala:16:47]
wire _T_63 = _rpq_io_deq_bits_uop_mem_cmd == 5'hE; // @[package.scala:16:47]
wire _r_c_cat_T_15; // @[package.scala:16:47]
assign _r_c_cat_T_15 = _T_63; // @[package.scala:16:47]
wire _r_c_cat_T_38; // @[package.scala:16:47]
assign _r_c_cat_T_38 = _T_63; // @[package.scala:16:47]
wire _T_64 = _rpq_io_deq_bits_uop_mem_cmd == 5'hF; // @[package.scala:16:47]
wire _r_c_cat_T_16; // @[package.scala:16:47]
assign _r_c_cat_T_16 = _T_64; // @[package.scala:16:47]
wire _r_c_cat_T_39; // @[package.scala:16:47]
assign _r_c_cat_T_39 = _T_64; // @[package.scala:16:47]
wire _T_71 = io_replay_ready_0 & io_replay_valid_0 & (_T_48 | _T_49 | _T_51 | _T_53 | _T_54 | _T_55 | _T_56 | _T_60 | _T_61 | _T_62 | _T_63 | _T_64); // @[Decoupled.scala:51:35]
wire _r_c_cat_T_2 = _r_c_cat_T | _r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _r_c_cat_T_4 = _r_c_cat_T_2 | _r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _r_c_cat_T_9 = _r_c_cat_T_5 | _r_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_10 = _r_c_cat_T_9 | _r_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_11 = _r_c_cat_T_10 | _r_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_17 = _r_c_cat_T_12 | _r_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_18 = _r_c_cat_T_17 | _r_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_19 = _r_c_cat_T_18 | _r_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_20 = _r_c_cat_T_19 | _r_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_21 = _r_c_cat_T_11 | _r_c_cat_T_20; // @[package.scala:81:59]
wire _r_c_cat_T_22 = _r_c_cat_T_4 | _r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _r_c_cat_T_25 = _r_c_cat_T_23 | _r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _r_c_cat_T_27 = _r_c_cat_T_25 | _r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _r_c_cat_T_32 = _r_c_cat_T_28 | _r_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_33 = _r_c_cat_T_32 | _r_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_34 = _r_c_cat_T_33 | _r_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_40 = _r_c_cat_T_35 | _r_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_41 = _r_c_cat_T_40 | _r_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_42 = _r_c_cat_T_41 | _r_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_43 = _r_c_cat_T_42 | _r_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_44 = _r_c_cat_T_34 | _r_c_cat_T_43; // @[package.scala:81:59]
wire _r_c_cat_T_45 = _r_c_cat_T_27 | _r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _r_c_cat_T_46 = _rpq_io_deq_bits_uop_mem_cmd == 5'h3; // @[Consts.scala:91:54]
wire _r_c_cat_T_47 = _r_c_cat_T_45 | _r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _r_c_cat_T_49 = _r_c_cat_T_47 | _r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] r_c = {_r_c_cat_T_22, _r_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _r_T_64 = {r_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19]
wire _r_T_89 = _r_T_64 == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _r_T_91 = {1'h0, _r_T_89}; // @[Misc.scala:35:36, :49:20]
wire _r_T_92 = _r_T_64 == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _r_T_94 = _r_T_92 ? 2'h2 : _r_T_91; // @[Misc.scala:35:36, :49:20]
wire _r_T_95 = _r_T_64 == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _r_T_97 = _r_T_95 ? 2'h1 : _r_T_94; // @[Misc.scala:35:36, :49:20]
wire _r_T_98 = _r_T_64 == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _r_T_100 = _r_T_98 ? 2'h2 : _r_T_97; // @[Misc.scala:35:36, :49:20]
wire _r_T_101 = _r_T_64 == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _r_T_103 = _r_T_101 ? 2'h0 : _r_T_100; // @[Misc.scala:35:36, :49:20]
wire _r_T_104 = _r_T_64 == 4'hE; // @[Misc.scala:49:20]
wire _r_T_105 = _r_T_104; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_106 = _r_T_104 ? 2'h3 : _r_T_103; // @[Misc.scala:35:36, :49:20]
wire _r_T_107 = &_r_T_64; // @[Misc.scala:49:20]
wire _r_T_108 = _r_T_107 | _r_T_105; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_109 = _r_T_107 ? 2'h3 : _r_T_106; // @[Misc.scala:35:36, :49:20]
wire _r_T_110 = _r_T_64 == 4'h6; // @[Misc.scala:49:20]
wire _r_T_111 = _r_T_110 | _r_T_108; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_112 = _r_T_110 ? 2'h2 : _r_T_109; // @[Misc.scala:35:36, :49:20]
wire _r_T_113 = _r_T_64 == 4'h7; // @[Misc.scala:49:20]
wire _r_T_114 = _r_T_113 | _r_T_111; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_115 = _r_T_113 ? 2'h3 : _r_T_112; // @[Misc.scala:35:36, :49:20]
wire _r_T_116 = _r_T_64 == 4'h1; // @[Misc.scala:49:20]
wire _r_T_117 = _r_T_116 | _r_T_114; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_118 = _r_T_116 ? 2'h1 : _r_T_115; // @[Misc.scala:35:36, :49:20]
wire _r_T_119 = _r_T_64 == 4'h2; // @[Misc.scala:49:20]
wire _r_T_120 = _r_T_119 | _r_T_117; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_121 = _r_T_119 ? 2'h2 : _r_T_118; // @[Misc.scala:35:36, :49:20]
wire _r_T_122 = _r_T_64 == 4'h3; // @[Misc.scala:49:20]
wire is_hit = _r_T_122 | _r_T_120; // @[Misc.scala:35:9, :49:20]
wire [1:0] r_2_1 = _r_T_122 ? 2'h3 : _r_T_121; // @[Misc.scala:35:36, :49:20]
wire [1:0] coh_on_hit_state = r_2_1; // @[Misc.scala:35:36]
wire _GEN_48 = _T_40 | _T_42 | _T_43 | _T_46; // @[mshrs.scala:156:26, :319:{22,36}, :324:{22,37}, :328:{22,41}, :338:{22,39}, :351:44]
assign io_meta_write_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37) & (_T_38 | ~_GEN_48 & _sec_rdy_T_4); // @[package.scala:16:47]
wire _GEN_49 = _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _GEN_48; // @[mshrs.scala:148:129, :156:26, :158:31, :302:39, :307:{22,41}, :309:{22,41}, :313:{22,40}, :319:36, :324:37, :328:41, :338:39, :351:44]
assign io_meta_write_bits_data_coh_state_0 = ~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4 | _GEN_49 | ~_sec_rdy_T_4 ? coh_on_clear_state : new_coh_state; // @[package.scala:16:47]
wire _GEN_50 = _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42 | _T_43 | _T_46 | _sec_rdy_T_4; // @[package.scala:16:47]
assign io_mem_finish_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _GEN_50) & _sec_rdy_T_5 & grantack_valid; // @[package.scala:16:47]
wire [4:0] _state_T_33 = finish_to_prefetch ? 5'h11 : 5'h0; // @[mshrs.scala:142:31, :368:17]
wire _GEN_51 = _sec_rdy_T_4 | _sec_rdy_T_5 | _sec_rdy_T_6; // @[package.scala:16:47]
wire _GEN_52 = _T_46 | _GEN_51; // @[mshrs.scala:162:26, :338:{22,39}, :351:44, :361:42, :367:42, :369:38]
wire _GEN_53 = _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42 | _T_43 | _GEN_52; // @[package.scala:16:47]
wire _GEN_54 = _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _GEN_53; // @[package.scala:16:47]
assign io_req_pri_rdy_0 = ~(|state) | ~_GEN_54 & _io_way_valid_T_1; // @[package.scala:16:47]
wire _T_87 = io_req_sec_val_0 & ~io_req_sec_rdy_0 | io_clear_prefetch_0; // @[mshrs.scala:36:7, :371:{27,30,47}]
wire _r_c_cat_T_52 = _r_c_cat_T_50 | _r_c_cat_T_51; // @[Consts.scala:90:{32,42,49}]
wire _r_c_cat_T_54 = _r_c_cat_T_52 | _r_c_cat_T_53; // @[Consts.scala:90:{42,59,66}]
wire _r_c_cat_T_59 = _r_c_cat_T_55 | _r_c_cat_T_56; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_60 = _r_c_cat_T_59 | _r_c_cat_T_57; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_61 = _r_c_cat_T_60 | _r_c_cat_T_58; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_67 = _r_c_cat_T_62 | _r_c_cat_T_63; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_68 = _r_c_cat_T_67 | _r_c_cat_T_64; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_69 = _r_c_cat_T_68 | _r_c_cat_T_65; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_70 = _r_c_cat_T_69 | _r_c_cat_T_66; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_71 = _r_c_cat_T_61 | _r_c_cat_T_70; // @[package.scala:81:59]
wire _r_c_cat_T_72 = _r_c_cat_T_54 | _r_c_cat_T_71; // @[Consts.scala:87:44, :90:{59,76}]
wire _r_c_cat_T_75 = _r_c_cat_T_73 | _r_c_cat_T_74; // @[Consts.scala:90:{32,42,49}]
wire _r_c_cat_T_77 = _r_c_cat_T_75 | _r_c_cat_T_76; // @[Consts.scala:90:{42,59,66}]
wire _r_c_cat_T_82 = _r_c_cat_T_78 | _r_c_cat_T_79; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_83 = _r_c_cat_T_82 | _r_c_cat_T_80; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_84 = _r_c_cat_T_83 | _r_c_cat_T_81; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_90 = _r_c_cat_T_85 | _r_c_cat_T_86; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_91 = _r_c_cat_T_90 | _r_c_cat_T_87; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_92 = _r_c_cat_T_91 | _r_c_cat_T_88; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_93 = _r_c_cat_T_92 | _r_c_cat_T_89; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_94 = _r_c_cat_T_84 | _r_c_cat_T_93; // @[package.scala:81:59]
wire _r_c_cat_T_95 = _r_c_cat_T_77 | _r_c_cat_T_94; // @[Consts.scala:87:44, :90:{59,76}]
wire _r_c_cat_T_97 = _r_c_cat_T_95 | _r_c_cat_T_96; // @[Consts.scala:90:76, :91:{47,54}]
wire _r_c_cat_T_99 = _r_c_cat_T_97 | _r_c_cat_T_98; // @[Consts.scala:91:{47,64,71}]
wire [1:0] r_c_1 = {_r_c_cat_T_72, _r_c_cat_T_99}; // @[Metadata.scala:29:18]
wire [3:0] _r_T_123 = {r_c_1, new_coh_state}; // @[Metadata.scala:29:18, :58:19]
wire _r_T_148 = _r_T_123 == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _r_T_150 = {1'h0, _r_T_148}; // @[Misc.scala:35:36, :49:20]
wire _r_T_151 = _r_T_123 == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _r_T_153 = _r_T_151 ? 2'h2 : _r_T_150; // @[Misc.scala:35:36, :49:20]
wire _r_T_154 = _r_T_123 == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _r_T_156 = _r_T_154 ? 2'h1 : _r_T_153; // @[Misc.scala:35:36, :49:20]
wire _r_T_157 = _r_T_123 == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _r_T_159 = _r_T_157 ? 2'h2 : _r_T_156; // @[Misc.scala:35:36, :49:20]
wire _r_T_160 = _r_T_123 == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _r_T_162 = _r_T_160 ? 2'h0 : _r_T_159; // @[Misc.scala:35:36, :49:20]
wire _r_T_163 = _r_T_123 == 4'hE; // @[Misc.scala:49:20]
wire _r_T_164 = _r_T_163; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_165 = _r_T_163 ? 2'h3 : _r_T_162; // @[Misc.scala:35:36, :49:20]
wire _r_T_166 = &_r_T_123; // @[Misc.scala:49:20]
wire _r_T_167 = _r_T_166 | _r_T_164; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_168 = _r_T_166 ? 2'h3 : _r_T_165; // @[Misc.scala:35:36, :49:20]
wire _r_T_169 = _r_T_123 == 4'h6; // @[Misc.scala:49:20]
wire _r_T_170 = _r_T_169 | _r_T_167; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_171 = _r_T_169 ? 2'h2 : _r_T_168; // @[Misc.scala:35:36, :49:20]
wire _r_T_172 = _r_T_123 == 4'h7; // @[Misc.scala:49:20]
wire _r_T_173 = _r_T_172 | _r_T_170; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_174 = _r_T_172 ? 2'h3 : _r_T_171; // @[Misc.scala:35:36, :49:20]
wire _r_T_175 = _r_T_123 == 4'h1; // @[Misc.scala:49:20]
wire _r_T_176 = _r_T_175 | _r_T_173; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_177 = _r_T_175 ? 2'h1 : _r_T_174; // @[Misc.scala:35:36, :49:20]
wire _r_T_178 = _r_T_123 == 4'h2; // @[Misc.scala:49:20]
wire _r_T_179 = _r_T_178 | _r_T_176; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_180 = _r_T_178 ? 2'h2 : _r_T_177; // @[Misc.scala:35:36, :49:20]
wire _r_T_181 = _r_T_123 == 4'h3; // @[Misc.scala:49:20]
wire is_hit_1 = _r_T_181 | _r_T_179; // @[Misc.scala:35:9, :49:20]
wire [1:0] r_2_2 = _r_T_181 ? 2'h3 : _r_T_180; // @[Misc.scala:35:36, :49:20]
wire [1:0] coh_on_hit_1_state = r_2_2; // @[Misc.scala:35:36]
wire [4:0] state_new_state_1; // @[mshrs.scala:210:29]
wire _state_T_35 = ~_state_T_34; // @[mshrs.scala:213:11]
wire _state_T_36 = ~_rpq_io_enq_ready; // @[mshrs.scala:128:19, :213:11]
wire _state_req_needs_wb_r_T_83 = _state_req_needs_wb_r_T_70 == 4'h8; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_85 = _state_req_needs_wb_r_T_83 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_87 = _state_req_needs_wb_r_T_70 == 4'h9; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_89 = _state_req_needs_wb_r_T_87 ? 3'h2 : _state_req_needs_wb_r_T_85; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_91 = _state_req_needs_wb_r_T_70 == 4'hA; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_93 = _state_req_needs_wb_r_T_91 ? 3'h1 : _state_req_needs_wb_r_T_89; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_95 = _state_req_needs_wb_r_T_70 == 4'hB; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_96 = _state_req_needs_wb_r_T_95; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_97 = _state_req_needs_wb_r_T_95 ? 3'h1 : _state_req_needs_wb_r_T_93; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_99 = _state_req_needs_wb_r_T_70 == 4'h4; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_100 = ~_state_req_needs_wb_r_T_99 & _state_req_needs_wb_r_T_96; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_101 = _state_req_needs_wb_r_T_99 ? 3'h5 : _state_req_needs_wb_r_T_97; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_103 = _state_req_needs_wb_r_T_70 == 4'h5; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_104 = ~_state_req_needs_wb_r_T_103 & _state_req_needs_wb_r_T_100; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_105 = _state_req_needs_wb_r_T_103 ? 3'h4 : _state_req_needs_wb_r_T_101; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_106 = {1'h0, _state_req_needs_wb_r_T_103}; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_107 = _state_req_needs_wb_r_T_70 == 4'h6; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_108 = ~_state_req_needs_wb_r_T_107 & _state_req_needs_wb_r_T_104; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_109 = _state_req_needs_wb_r_T_107 ? 3'h0 : _state_req_needs_wb_r_T_105; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_110 = _state_req_needs_wb_r_T_107 ? 2'h1 : _state_req_needs_wb_r_T_106; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_111 = _state_req_needs_wb_r_T_70 == 4'h7; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_112 = _state_req_needs_wb_r_T_111 | _state_req_needs_wb_r_T_108; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_113 = _state_req_needs_wb_r_T_111 ? 3'h0 : _state_req_needs_wb_r_T_109; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_114 = _state_req_needs_wb_r_T_111 ? 2'h1 : _state_req_needs_wb_r_T_110; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_115 = _state_req_needs_wb_r_T_70 == 4'h0; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_116 = ~_state_req_needs_wb_r_T_115 & _state_req_needs_wb_r_T_112; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_117 = _state_req_needs_wb_r_T_115 ? 3'h5 : _state_req_needs_wb_r_T_113; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_118 = _state_req_needs_wb_r_T_115 ? 2'h0 : _state_req_needs_wb_r_T_114; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_119 = _state_req_needs_wb_r_T_70 == 4'h1; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_120 = ~_state_req_needs_wb_r_T_119 & _state_req_needs_wb_r_T_116; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_121 = _state_req_needs_wb_r_T_119 ? 3'h4 : _state_req_needs_wb_r_T_117; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_122 = _state_req_needs_wb_r_T_119 ? 2'h1 : _state_req_needs_wb_r_T_118; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_123 = _state_req_needs_wb_r_T_70 == 4'h2; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_124 = ~_state_req_needs_wb_r_T_123 & _state_req_needs_wb_r_T_120; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_125 = _state_req_needs_wb_r_T_123 ? 3'h3 : _state_req_needs_wb_r_T_121; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_126 = _state_req_needs_wb_r_T_123 ? 2'h2 : _state_req_needs_wb_r_T_122; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_127 = _state_req_needs_wb_r_T_70 == 4'h3; // @[Misc.scala:56:20]
wire state_req_needs_wb_r_1_1 = _state_req_needs_wb_r_T_127 | _state_req_needs_wb_r_T_124; // @[Misc.scala:38:9, :56:20]
wire [2:0] state_req_needs_wb_r_2_1 = _state_req_needs_wb_r_T_127 ? 3'h3 : _state_req_needs_wb_r_T_125; // @[Misc.scala:38:36, :56:20]
wire [1:0] state_req_needs_wb_r_3_1 = _state_req_needs_wb_r_T_127 ? 2'h2 : _state_req_needs_wb_r_T_126; // @[Misc.scala:38:63, :56:20]
wire [1:0] state_req_needs_wb_meta_1_state = state_req_needs_wb_r_3_1; // @[Misc.scala:38:63]
wire _state_r_c_cat_T_52 = _state_r_c_cat_T_50 | _state_r_c_cat_T_51; // @[Consts.scala:90:{32,42,49}]
wire _state_r_c_cat_T_54 = _state_r_c_cat_T_52 | _state_r_c_cat_T_53; // @[Consts.scala:90:{42,59,66}]
wire _state_r_c_cat_T_59 = _state_r_c_cat_T_55 | _state_r_c_cat_T_56; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_60 = _state_r_c_cat_T_59 | _state_r_c_cat_T_57; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_61 = _state_r_c_cat_T_60 | _state_r_c_cat_T_58; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_67 = _state_r_c_cat_T_62 | _state_r_c_cat_T_63; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_68 = _state_r_c_cat_T_67 | _state_r_c_cat_T_64; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_69 = _state_r_c_cat_T_68 | _state_r_c_cat_T_65; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_70 = _state_r_c_cat_T_69 | _state_r_c_cat_T_66; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_71 = _state_r_c_cat_T_61 | _state_r_c_cat_T_70; // @[package.scala:81:59]
wire _state_r_c_cat_T_72 = _state_r_c_cat_T_54 | _state_r_c_cat_T_71; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_r_c_cat_T_75 = _state_r_c_cat_T_73 | _state_r_c_cat_T_74; // @[Consts.scala:90:{32,42,49}]
wire _state_r_c_cat_T_77 = _state_r_c_cat_T_75 | _state_r_c_cat_T_76; // @[Consts.scala:90:{42,59,66}]
wire _state_r_c_cat_T_82 = _state_r_c_cat_T_78 | _state_r_c_cat_T_79; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_83 = _state_r_c_cat_T_82 | _state_r_c_cat_T_80; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_84 = _state_r_c_cat_T_83 | _state_r_c_cat_T_81; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_90 = _state_r_c_cat_T_85 | _state_r_c_cat_T_86; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_91 = _state_r_c_cat_T_90 | _state_r_c_cat_T_87; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_92 = _state_r_c_cat_T_91 | _state_r_c_cat_T_88; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_93 = _state_r_c_cat_T_92 | _state_r_c_cat_T_89; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_94 = _state_r_c_cat_T_84 | _state_r_c_cat_T_93; // @[package.scala:81:59]
wire _state_r_c_cat_T_95 = _state_r_c_cat_T_77 | _state_r_c_cat_T_94; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_r_c_cat_T_97 = _state_r_c_cat_T_95 | _state_r_c_cat_T_96; // @[Consts.scala:90:76, :91:{47,54}]
wire _state_r_c_cat_T_99 = _state_r_c_cat_T_97 | _state_r_c_cat_T_98; // @[Consts.scala:91:{47,64,71}]
wire [1:0] state_r_c_1 = {_state_r_c_cat_T_72, _state_r_c_cat_T_99}; // @[Metadata.scala:29:18]
wire [3:0] _state_r_T_59 = {state_r_c_1, io_req_old_meta_coh_state_0}; // @[Metadata.scala:29:18, :58:19]
wire _state_r_T_84 = _state_r_T_59 == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_86 = {1'h0, _state_r_T_84}; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_87 = _state_r_T_59 == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_89 = _state_r_T_87 ? 2'h2 : _state_r_T_86; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_90 = _state_r_T_59 == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_92 = _state_r_T_90 ? 2'h1 : _state_r_T_89; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_93 = _state_r_T_59 == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_95 = _state_r_T_93 ? 2'h2 : _state_r_T_92; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_96 = _state_r_T_59 == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_98 = _state_r_T_96 ? 2'h0 : _state_r_T_95; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_99 = _state_r_T_59 == 4'hE; // @[Misc.scala:49:20]
wire _state_r_T_100 = _state_r_T_99; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_101 = _state_r_T_99 ? 2'h3 : _state_r_T_98; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_102 = &_state_r_T_59; // @[Misc.scala:49:20]
wire _state_r_T_103 = _state_r_T_102 | _state_r_T_100; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_104 = _state_r_T_102 ? 2'h3 : _state_r_T_101; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_105 = _state_r_T_59 == 4'h6; // @[Misc.scala:49:20]
wire _state_r_T_106 = _state_r_T_105 | _state_r_T_103; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_107 = _state_r_T_105 ? 2'h2 : _state_r_T_104; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_108 = _state_r_T_59 == 4'h7; // @[Misc.scala:49:20]
wire _state_r_T_109 = _state_r_T_108 | _state_r_T_106; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_110 = _state_r_T_108 ? 2'h3 : _state_r_T_107; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_111 = _state_r_T_59 == 4'h1; // @[Misc.scala:49:20]
wire _state_r_T_112 = _state_r_T_111 | _state_r_T_109; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_113 = _state_r_T_111 ? 2'h1 : _state_r_T_110; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_114 = _state_r_T_59 == 4'h2; // @[Misc.scala:49:20]
wire _state_r_T_115 = _state_r_T_114 | _state_r_T_112; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_116 = _state_r_T_114 ? 2'h2 : _state_r_T_113; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_117 = _state_r_T_59 == 4'h3; // @[Misc.scala:49:20]
wire state_is_hit_1 = _state_r_T_117 | _state_r_T_115; // @[Misc.scala:35:9, :49:20]
wire [1:0] state_r_2_1 = _state_r_T_117 ? 2'h3 : _state_r_T_116; // @[Misc.scala:35:36, :49:20]
wire [1:0] state_coh_on_hit_1_state = state_r_2_1; // @[Misc.scala:35:36]
wire _state_T_39 = _state_T_37 | _state_T_38; // @[Consts.scala:90:{32,42,49}]
wire _state_T_41 = _state_T_39 | _state_T_40; // @[Consts.scala:90:{42,59,66}]
wire _state_T_46 = _state_T_42 | _state_T_43; // @[package.scala:16:47, :81:59]
wire _state_T_47 = _state_T_46 | _state_T_44; // @[package.scala:16:47, :81:59]
wire _state_T_48 = _state_T_47 | _state_T_45; // @[package.scala:16:47, :81:59]
wire _state_T_54 = _state_T_49 | _state_T_50; // @[package.scala:16:47, :81:59]
wire _state_T_55 = _state_T_54 | _state_T_51; // @[package.scala:16:47, :81:59]
wire _state_T_56 = _state_T_55 | _state_T_52; // @[package.scala:16:47, :81:59]
wire _state_T_57 = _state_T_56 | _state_T_53; // @[package.scala:16:47, :81:59]
wire _state_T_58 = _state_T_48 | _state_T_57; // @[package.scala:81:59]
wire _state_T_59 = _state_T_41 | _state_T_58; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_T_61 = ~_state_T_60; // @[mshrs.scala:220:15]
wire _state_T_62 = ~_state_T_59; // @[Consts.scala:90:76] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_85 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 3, 0)
node _source_ok_T = shr(io.in.a.bits.source, 4)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<4>(0h9))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits = bits(_uncommonBits_T, 3, 0)
node _T_4 = shr(io.in.a.bits.source, 4)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<4>(0h9))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 3, 0)
node _T_24 = shr(io.in.a.bits.source, 4)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<4>(0h9))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_33 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = and(_T_32, _T_37)
node _T_39 = or(UInt<1>(0h0), _T_38)
node _T_40 = and(_T_31, _T_39)
node _T_41 = asUInt(reset)
node _T_42 = eq(_T_41, UInt<1>(0h0))
when _T_42 :
node _T_43 = eq(_T_40, UInt<1>(0h0))
when _T_43 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_40, UInt<1>(0h1), "") : assert_2
node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_46 = and(_T_44, _T_45)
node _T_47 = or(UInt<1>(0h0), _T_46)
node _T_48 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_49 = cvt(_T_48)
node _T_50 = and(_T_49, asSInt(UInt<17>(0h10000)))
node _T_51 = asSInt(_T_50)
node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = and(_T_47, _T_52)
node _T_54 = or(UInt<1>(0h0), _T_53)
node _T_55 = and(UInt<1>(0h0), _T_54)
node _T_56 = asUInt(reset)
node _T_57 = eq(_T_56, UInt<1>(0h0))
when _T_57 :
node _T_58 = eq(_T_55, UInt<1>(0h0))
when _T_58 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_55, UInt<1>(0h1), "") : assert_3
node _T_59 = asUInt(reset)
node _T_60 = eq(_T_59, UInt<1>(0h0))
when _T_60 :
node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_61 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_63 = asUInt(reset)
node _T_64 = eq(_T_63, UInt<1>(0h0))
when _T_64 :
node _T_65 = eq(_T_62, UInt<1>(0h0))
when _T_65 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_62, UInt<1>(0h1), "") : assert_5
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(is_aligned, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_70 = asUInt(reset)
node _T_71 = eq(_T_70, UInt<1>(0h0))
when _T_71 :
node _T_72 = eq(_T_69, UInt<1>(0h0))
when _T_72 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_69, UInt<1>(0h1), "") : assert_7
node _T_73 = not(io.in.a.bits.mask)
node _T_74 = eq(_T_73, UInt<1>(0h0))
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_T_74, UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_74, UInt<1>(0h1), "") : assert_8
node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_79 = asUInt(reset)
node _T_80 = eq(_T_79, UInt<1>(0h0))
when _T_80 :
node _T_81 = eq(_T_78, UInt<1>(0h0))
when _T_81 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_78, UInt<1>(0h1), "") : assert_9
node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_82 :
node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_85 = and(_T_83, _T_84)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 3, 0)
node _T_86 = shr(io.in.a.bits.source, 4)
node _T_87 = eq(_T_86, UInt<1>(0h0))
node _T_88 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_89 = and(_T_87, _T_88)
node _T_90 = leq(uncommonBits_2, UInt<4>(0h9))
node _T_91 = and(_T_89, _T_90)
node _T_92 = and(_T_85, _T_91)
node _T_93 = or(UInt<1>(0h0), _T_92)
node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_95 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = and(_T_94, _T_99)
node _T_101 = or(UInt<1>(0h0), _T_100)
node _T_102 = and(_T_93, _T_101)
node _T_103 = asUInt(reset)
node _T_104 = eq(_T_103, UInt<1>(0h0))
when _T_104 :
node _T_105 = eq(_T_102, UInt<1>(0h0))
when _T_105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_102, UInt<1>(0h1), "") : assert_10
node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_108 = and(_T_106, _T_107)
node _T_109 = or(UInt<1>(0h0), _T_108)
node _T_110 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_111 = cvt(_T_110)
node _T_112 = and(_T_111, asSInt(UInt<17>(0h10000)))
node _T_113 = asSInt(_T_112)
node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0)))
node _T_115 = and(_T_109, _T_114)
node _T_116 = or(UInt<1>(0h0), _T_115)
node _T_117 = and(UInt<1>(0h0), _T_116)
node _T_118 = asUInt(reset)
node _T_119 = eq(_T_118, UInt<1>(0h0))
when _T_119 :
node _T_120 = eq(_T_117, UInt<1>(0h0))
when _T_120 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_117, UInt<1>(0h1), "") : assert_11
node _T_121 = asUInt(reset)
node _T_122 = eq(_T_121, UInt<1>(0h0))
when _T_122 :
node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_125 = asUInt(reset)
node _T_126 = eq(_T_125, UInt<1>(0h0))
when _T_126 :
node _T_127 = eq(_T_124, UInt<1>(0h0))
when _T_127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_124, UInt<1>(0h1), "") : assert_13
node _T_128 = asUInt(reset)
node _T_129 = eq(_T_128, UInt<1>(0h0))
when _T_129 :
node _T_130 = eq(is_aligned, UInt<1>(0h0))
when _T_130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_131, UInt<1>(0h1), "") : assert_15
node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_136 = asUInt(reset)
node _T_137 = eq(_T_136, UInt<1>(0h0))
when _T_137 :
node _T_138 = eq(_T_135, UInt<1>(0h0))
when _T_138 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_135, UInt<1>(0h1), "") : assert_16
node _T_139 = not(io.in.a.bits.mask)
node _T_140 = eq(_T_139, UInt<1>(0h0))
node _T_141 = asUInt(reset)
node _T_142 = eq(_T_141, UInt<1>(0h0))
when _T_142 :
node _T_143 = eq(_T_140, UInt<1>(0h0))
when _T_143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_140, UInt<1>(0h1), "") : assert_17
node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_145 = asUInt(reset)
node _T_146 = eq(_T_145, UInt<1>(0h0))
when _T_146 :
node _T_147 = eq(_T_144, UInt<1>(0h0))
when _T_147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_144, UInt<1>(0h1), "") : assert_18
node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_148 :
node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_151 = and(_T_149, _T_150)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 3, 0)
node _T_152 = shr(io.in.a.bits.source, 4)
node _T_153 = eq(_T_152, UInt<1>(0h0))
node _T_154 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_155 = and(_T_153, _T_154)
node _T_156 = leq(uncommonBits_3, UInt<4>(0h9))
node _T_157 = and(_T_155, _T_156)
node _T_158 = and(_T_151, _T_157)
node _T_159 = or(UInt<1>(0h0), _T_158)
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_T_159, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_159, UInt<1>(0h1), "") : assert_19
node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_164 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_165 = and(_T_163, _T_164)
node _T_166 = or(UInt<1>(0h0), _T_165)
node _T_167 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_168 = cvt(_T_167)
node _T_169 = and(_T_168, asSInt(UInt<17>(0h10000)))
node _T_170 = asSInt(_T_169)
node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0)))
node _T_172 = and(_T_166, _T_171)
node _T_173 = or(UInt<1>(0h0), _T_172)
node _T_174 = asUInt(reset)
node _T_175 = eq(_T_174, UInt<1>(0h0))
when _T_175 :
node _T_176 = eq(_T_173, UInt<1>(0h0))
when _T_176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_173, UInt<1>(0h1), "") : assert_20
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_180 = asUInt(reset)
node _T_181 = eq(_T_180, UInt<1>(0h0))
when _T_181 :
node _T_182 = eq(is_aligned, UInt<1>(0h0))
when _T_182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(io.in.a.bits.mask, mask)
node _T_188 = asUInt(reset)
node _T_189 = eq(_T_188, UInt<1>(0h0))
when _T_189 :
node _T_190 = eq(_T_187, UInt<1>(0h0))
when _T_190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_187, UInt<1>(0h1), "") : assert_24
node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_192 = asUInt(reset)
node _T_193 = eq(_T_192, UInt<1>(0h0))
when _T_193 :
node _T_194 = eq(_T_191, UInt<1>(0h0))
when _T_194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_191, UInt<1>(0h1), "") : assert_25
node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_195 :
node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_198 = and(_T_196, _T_197)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0)
node _T_199 = shr(io.in.a.bits.source, 4)
node _T_200 = eq(_T_199, UInt<1>(0h0))
node _T_201 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_202 = and(_T_200, _T_201)
node _T_203 = leq(uncommonBits_4, UInt<4>(0h9))
node _T_204 = and(_T_202, _T_203)
node _T_205 = and(_T_198, _T_204)
node _T_206 = or(UInt<1>(0h0), _T_205)
node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_208 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_209 = and(_T_207, _T_208)
node _T_210 = or(UInt<1>(0h0), _T_209)
node _T_211 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_212 = cvt(_T_211)
node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000)))
node _T_214 = asSInt(_T_213)
node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0)))
node _T_216 = and(_T_210, _T_215)
node _T_217 = or(UInt<1>(0h0), _T_216)
node _T_218 = and(_T_206, _T_217)
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_218, UInt<1>(0h1), "") : assert_26
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_225 = asUInt(reset)
node _T_226 = eq(_T_225, UInt<1>(0h0))
when _T_226 :
node _T_227 = eq(is_aligned, UInt<1>(0h0))
when _T_227 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_229 = asUInt(reset)
node _T_230 = eq(_T_229, UInt<1>(0h0))
when _T_230 :
node _T_231 = eq(_T_228, UInt<1>(0h0))
when _T_231 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_228, UInt<1>(0h1), "") : assert_29
node _T_232 = eq(io.in.a.bits.mask, mask)
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_232, UInt<1>(0h1), "") : assert_30
node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_236 :
node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_239 = and(_T_237, _T_238)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0)
node _T_240 = shr(io.in.a.bits.source, 4)
node _T_241 = eq(_T_240, UInt<1>(0h0))
node _T_242 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_243 = and(_T_241, _T_242)
node _T_244 = leq(uncommonBits_5, UInt<4>(0h9))
node _T_245 = and(_T_243, _T_244)
node _T_246 = and(_T_239, _T_245)
node _T_247 = or(UInt<1>(0h0), _T_246)
node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_249 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_250 = and(_T_248, _T_249)
node _T_251 = or(UInt<1>(0h0), _T_250)
node _T_252 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_253 = cvt(_T_252)
node _T_254 = and(_T_253, asSInt(UInt<17>(0h10000)))
node _T_255 = asSInt(_T_254)
node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0)))
node _T_257 = and(_T_251, _T_256)
node _T_258 = or(UInt<1>(0h0), _T_257)
node _T_259 = and(_T_247, _T_258)
node _T_260 = asUInt(reset)
node _T_261 = eq(_T_260, UInt<1>(0h0))
when _T_261 :
node _T_262 = eq(_T_259, UInt<1>(0h0))
when _T_262 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_259, UInt<1>(0h1), "") : assert_31
node _T_263 = asUInt(reset)
node _T_264 = eq(_T_263, UInt<1>(0h0))
when _T_264 :
node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_265 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_266 = asUInt(reset)
node _T_267 = eq(_T_266, UInt<1>(0h0))
when _T_267 :
node _T_268 = eq(is_aligned, UInt<1>(0h0))
when _T_268 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_270 = asUInt(reset)
node _T_271 = eq(_T_270, UInt<1>(0h0))
when _T_271 :
node _T_272 = eq(_T_269, UInt<1>(0h0))
when _T_272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_269, UInt<1>(0h1), "") : assert_34
node _T_273 = not(mask)
node _T_274 = and(io.in.a.bits.mask, _T_273)
node _T_275 = eq(_T_274, UInt<1>(0h0))
node _T_276 = asUInt(reset)
node _T_277 = eq(_T_276, UInt<1>(0h0))
when _T_277 :
node _T_278 = eq(_T_275, UInt<1>(0h0))
when _T_278 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_275, UInt<1>(0h1), "") : assert_35
node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_279 :
node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_282 = and(_T_280, _T_281)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 3, 0)
node _T_283 = shr(io.in.a.bits.source, 4)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_286 = and(_T_284, _T_285)
node _T_287 = leq(uncommonBits_6, UInt<4>(0h9))
node _T_288 = and(_T_286, _T_287)
node _T_289 = and(_T_282, _T_288)
node _T_290 = or(UInt<1>(0h0), _T_289)
node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_292 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_293 = cvt(_T_292)
node _T_294 = and(_T_293, asSInt(UInt<17>(0h10000)))
node _T_295 = asSInt(_T_294)
node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0)))
node _T_297 = and(_T_291, _T_296)
node _T_298 = or(UInt<1>(0h0), _T_297)
node _T_299 = and(_T_290, _T_298)
node _T_300 = asUInt(reset)
node _T_301 = eq(_T_300, UInt<1>(0h0))
when _T_301 :
node _T_302 = eq(_T_299, UInt<1>(0h0))
when _T_302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_299, UInt<1>(0h1), "") : assert_36
node _T_303 = asUInt(reset)
node _T_304 = eq(_T_303, UInt<1>(0h0))
when _T_304 :
node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_305 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_306 = asUInt(reset)
node _T_307 = eq(_T_306, UInt<1>(0h0))
when _T_307 :
node _T_308 = eq(is_aligned, UInt<1>(0h0))
when _T_308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_310 = asUInt(reset)
node _T_311 = eq(_T_310, UInt<1>(0h0))
when _T_311 :
node _T_312 = eq(_T_309, UInt<1>(0h0))
when _T_312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_309, UInt<1>(0h1), "") : assert_39
node _T_313 = eq(io.in.a.bits.mask, mask)
node _T_314 = asUInt(reset)
node _T_315 = eq(_T_314, UInt<1>(0h0))
when _T_315 :
node _T_316 = eq(_T_313, UInt<1>(0h0))
when _T_316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_313, UInt<1>(0h1), "") : assert_40
node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_317 :
node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_320 = and(_T_318, _T_319)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 3, 0)
node _T_321 = shr(io.in.a.bits.source, 4)
node _T_322 = eq(_T_321, UInt<1>(0h0))
node _T_323 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_324 = and(_T_322, _T_323)
node _T_325 = leq(uncommonBits_7, UInt<4>(0h9))
node _T_326 = and(_T_324, _T_325)
node _T_327 = and(_T_320, _T_326)
node _T_328 = or(UInt<1>(0h0), _T_327)
node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_330 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_331 = cvt(_T_330)
node _T_332 = and(_T_331, asSInt(UInt<17>(0h10000)))
node _T_333 = asSInt(_T_332)
node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0)))
node _T_335 = and(_T_329, _T_334)
node _T_336 = or(UInt<1>(0h0), _T_335)
node _T_337 = and(_T_328, _T_336)
node _T_338 = asUInt(reset)
node _T_339 = eq(_T_338, UInt<1>(0h0))
when _T_339 :
node _T_340 = eq(_T_337, UInt<1>(0h0))
when _T_340 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_337, UInt<1>(0h1), "") : assert_41
node _T_341 = asUInt(reset)
node _T_342 = eq(_T_341, UInt<1>(0h0))
when _T_342 :
node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_343 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_344 = asUInt(reset)
node _T_345 = eq(_T_344, UInt<1>(0h0))
when _T_345 :
node _T_346 = eq(is_aligned, UInt<1>(0h0))
when _T_346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_347, UInt<1>(0h1), "") : assert_44
node _T_351 = eq(io.in.a.bits.mask, mask)
node _T_352 = asUInt(reset)
node _T_353 = eq(_T_352, UInt<1>(0h0))
when _T_353 :
node _T_354 = eq(_T_351, UInt<1>(0h0))
when _T_354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_351, UInt<1>(0h1), "") : assert_45
node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_355 :
node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_358 = and(_T_356, _T_357)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 3, 0)
node _T_359 = shr(io.in.a.bits.source, 4)
node _T_360 = eq(_T_359, UInt<1>(0h0))
node _T_361 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_362 = and(_T_360, _T_361)
node _T_363 = leq(uncommonBits_8, UInt<4>(0h9))
node _T_364 = and(_T_362, _T_363)
node _T_365 = and(_T_358, _T_364)
node _T_366 = or(UInt<1>(0h0), _T_365)
node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_368 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_369 = cvt(_T_368)
node _T_370 = and(_T_369, asSInt(UInt<17>(0h10000)))
node _T_371 = asSInt(_T_370)
node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0)))
node _T_373 = and(_T_367, _T_372)
node _T_374 = or(UInt<1>(0h0), _T_373)
node _T_375 = and(_T_366, _T_374)
node _T_376 = asUInt(reset)
node _T_377 = eq(_T_376, UInt<1>(0h0))
when _T_377 :
node _T_378 = eq(_T_375, UInt<1>(0h0))
when _T_378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_375, UInt<1>(0h1), "") : assert_46
node _T_379 = asUInt(reset)
node _T_380 = eq(_T_379, UInt<1>(0h0))
when _T_380 :
node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_382 = asUInt(reset)
node _T_383 = eq(_T_382, UInt<1>(0h0))
when _T_383 :
node _T_384 = eq(is_aligned, UInt<1>(0h0))
when _T_384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_386 = asUInt(reset)
node _T_387 = eq(_T_386, UInt<1>(0h0))
when _T_387 :
node _T_388 = eq(_T_385, UInt<1>(0h0))
when _T_388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_385, UInt<1>(0h1), "") : assert_49
node _T_389 = eq(io.in.a.bits.mask, mask)
node _T_390 = asUInt(reset)
node _T_391 = eq(_T_390, UInt<1>(0h0))
when _T_391 :
node _T_392 = eq(_T_389, UInt<1>(0h0))
when _T_392 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_389, UInt<1>(0h1), "") : assert_50
node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_394 = asUInt(reset)
node _T_395 = eq(_T_394, UInt<1>(0h0))
when _T_395 :
node _T_396 = eq(_T_393, UInt<1>(0h0))
when _T_396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_393, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_397, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 3, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 4)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<4>(0h9))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_401 :
node _T_402 = asUInt(reset)
node _T_403 = eq(_T_402, UInt<1>(0h0))
when _T_403 :
node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_404 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_406 = asUInt(reset)
node _T_407 = eq(_T_406, UInt<1>(0h0))
when _T_407 :
node _T_408 = eq(_T_405, UInt<1>(0h0))
when _T_408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_405, UInt<1>(0h1), "") : assert_54
node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_410 = asUInt(reset)
node _T_411 = eq(_T_410, UInt<1>(0h0))
when _T_411 :
node _T_412 = eq(_T_409, UInt<1>(0h0))
when _T_412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_409, UInt<1>(0h1), "") : assert_55
node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_414 = asUInt(reset)
node _T_415 = eq(_T_414, UInt<1>(0h0))
when _T_415 :
node _T_416 = eq(_T_413, UInt<1>(0h0))
when _T_416 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_413, UInt<1>(0h1), "") : assert_56
node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_418 = asUInt(reset)
node _T_419 = eq(_T_418, UInt<1>(0h0))
when _T_419 :
node _T_420 = eq(_T_417, UInt<1>(0h0))
when _T_420 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_417, UInt<1>(0h1), "") : assert_57
node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_421 :
node _T_422 = asUInt(reset)
node _T_423 = eq(_T_422, UInt<1>(0h0))
when _T_423 :
node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_424 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_425 = asUInt(reset)
node _T_426 = eq(_T_425, UInt<1>(0h0))
when _T_426 :
node _T_427 = eq(sink_ok, UInt<1>(0h0))
when _T_427 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_429 = asUInt(reset)
node _T_430 = eq(_T_429, UInt<1>(0h0))
when _T_430 :
node _T_431 = eq(_T_428, UInt<1>(0h0))
when _T_431 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_428, UInt<1>(0h1), "") : assert_60
node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_433 = asUInt(reset)
node _T_434 = eq(_T_433, UInt<1>(0h0))
when _T_434 :
node _T_435 = eq(_T_432, UInt<1>(0h0))
when _T_435 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_432, UInt<1>(0h1), "") : assert_61
node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_437 = asUInt(reset)
node _T_438 = eq(_T_437, UInt<1>(0h0))
when _T_438 :
node _T_439 = eq(_T_436, UInt<1>(0h0))
when _T_439 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_436, UInt<1>(0h1), "") : assert_62
node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_441 = asUInt(reset)
node _T_442 = eq(_T_441, UInt<1>(0h0))
when _T_442 :
node _T_443 = eq(_T_440, UInt<1>(0h0))
when _T_443 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_440, UInt<1>(0h1), "") : assert_63
node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_445 = or(UInt<1>(0h0), _T_444)
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_445, UInt<1>(0h1), "") : assert_64
node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_449 :
node _T_450 = asUInt(reset)
node _T_451 = eq(_T_450, UInt<1>(0h0))
when _T_451 :
node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(sink_ok, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_457 = asUInt(reset)
node _T_458 = eq(_T_457, UInt<1>(0h0))
when _T_458 :
node _T_459 = eq(_T_456, UInt<1>(0h0))
when _T_459 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_456, UInt<1>(0h1), "") : assert_67
node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_461 = asUInt(reset)
node _T_462 = eq(_T_461, UInt<1>(0h0))
when _T_462 :
node _T_463 = eq(_T_460, UInt<1>(0h0))
when _T_463 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_460, UInt<1>(0h1), "") : assert_68
node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_465 = asUInt(reset)
node _T_466 = eq(_T_465, UInt<1>(0h0))
when _T_466 :
node _T_467 = eq(_T_464, UInt<1>(0h0))
when _T_467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_464, UInt<1>(0h1), "") : assert_69
node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_469 = or(_T_468, io.in.d.bits.corrupt)
node _T_470 = asUInt(reset)
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(_T_469, UInt<1>(0h0))
when _T_472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_469, UInt<1>(0h1), "") : assert_70
node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_474 = or(UInt<1>(0h0), _T_473)
node _T_475 = asUInt(reset)
node _T_476 = eq(_T_475, UInt<1>(0h0))
when _T_476 :
node _T_477 = eq(_T_474, UInt<1>(0h0))
when _T_477 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_474, UInt<1>(0h1), "") : assert_71
node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_478 :
node _T_479 = asUInt(reset)
node _T_480 = eq(_T_479, UInt<1>(0h0))
when _T_480 :
node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_481 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_483 = asUInt(reset)
node _T_484 = eq(_T_483, UInt<1>(0h0))
when _T_484 :
node _T_485 = eq(_T_482, UInt<1>(0h0))
when _T_485 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_482, UInt<1>(0h1), "") : assert_73
node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_487 = asUInt(reset)
node _T_488 = eq(_T_487, UInt<1>(0h0))
when _T_488 :
node _T_489 = eq(_T_486, UInt<1>(0h0))
when _T_489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_486, UInt<1>(0h1), "") : assert_74
node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_491 = or(UInt<1>(0h0), _T_490)
node _T_492 = asUInt(reset)
node _T_493 = eq(_T_492, UInt<1>(0h0))
when _T_493 :
node _T_494 = eq(_T_491, UInt<1>(0h0))
when _T_494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_491, UInt<1>(0h1), "") : assert_75
node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_495 :
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_500 = asUInt(reset)
node _T_501 = eq(_T_500, UInt<1>(0h0))
when _T_501 :
node _T_502 = eq(_T_499, UInt<1>(0h0))
when _T_502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_499, UInt<1>(0h1), "") : assert_77
node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_504 = or(_T_503, io.in.d.bits.corrupt)
node _T_505 = asUInt(reset)
node _T_506 = eq(_T_505, UInt<1>(0h0))
when _T_506 :
node _T_507 = eq(_T_504, UInt<1>(0h0))
when _T_507 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_504, UInt<1>(0h1), "") : assert_78
node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_509 = or(UInt<1>(0h0), _T_508)
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_509, UInt<1>(0h1), "") : assert_79
node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_513 :
node _T_514 = asUInt(reset)
node _T_515 = eq(_T_514, UInt<1>(0h0))
when _T_515 :
node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_516 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_518 = asUInt(reset)
node _T_519 = eq(_T_518, UInt<1>(0h0))
when _T_519 :
node _T_520 = eq(_T_517, UInt<1>(0h0))
when _T_520 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_517, UInt<1>(0h1), "") : assert_81
node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_522 = asUInt(reset)
node _T_523 = eq(_T_522, UInt<1>(0h0))
when _T_523 :
node _T_524 = eq(_T_521, UInt<1>(0h0))
when _T_524 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_521, UInt<1>(0h1), "") : assert_82
node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_526 = or(UInt<1>(0h0), _T_525)
node _T_527 = asUInt(reset)
node _T_528 = eq(_T_527, UInt<1>(0h0))
when _T_528 :
node _T_529 = eq(_T_526, UInt<1>(0h0))
when _T_529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_526, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<28>(0h0)
connect _WIRE.bits.source, UInt<4>(0h0)
connect _WIRE.bits.size, UInt<3>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_531 = asUInt(reset)
node _T_532 = eq(_T_531, UInt<1>(0h0))
when _T_532 :
node _T_533 = eq(_T_530, UInt<1>(0h0))
when _T_533 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_530, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<28>(0h0)
connect _WIRE_2.bits.source, UInt<4>(0h0)
connect _WIRE_2.bits.size, UInt<3>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_535 = asUInt(reset)
node _T_536 = eq(_T_535, UInt<1>(0h0))
when _T_536 :
node _T_537 = eq(_T_534, UInt<1>(0h0))
when _T_537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_534, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_T_538, UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_538, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_542 = eq(a_first, UInt<1>(0h0))
node _T_543 = and(io.in.a.valid, _T_542)
when _T_543 :
node _T_544 = eq(io.in.a.bits.opcode, opcode)
node _T_545 = asUInt(reset)
node _T_546 = eq(_T_545, UInt<1>(0h0))
when _T_546 :
node _T_547 = eq(_T_544, UInt<1>(0h0))
when _T_547 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_544, UInt<1>(0h1), "") : assert_87
node _T_548 = eq(io.in.a.bits.param, param)
node _T_549 = asUInt(reset)
node _T_550 = eq(_T_549, UInt<1>(0h0))
when _T_550 :
node _T_551 = eq(_T_548, UInt<1>(0h0))
when _T_551 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_548, UInt<1>(0h1), "") : assert_88
node _T_552 = eq(io.in.a.bits.size, size)
node _T_553 = asUInt(reset)
node _T_554 = eq(_T_553, UInt<1>(0h0))
when _T_554 :
node _T_555 = eq(_T_552, UInt<1>(0h0))
when _T_555 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_552, UInt<1>(0h1), "") : assert_89
node _T_556 = eq(io.in.a.bits.source, source)
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_556, UInt<1>(0h1), "") : assert_90
node _T_560 = eq(io.in.a.bits.address, address)
node _T_561 = asUInt(reset)
node _T_562 = eq(_T_561, UInt<1>(0h0))
when _T_562 :
node _T_563 = eq(_T_560, UInt<1>(0h0))
when _T_563 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_560, UInt<1>(0h1), "") : assert_91
node _T_564 = and(io.in.a.ready, io.in.a.valid)
node _T_565 = and(_T_564, a_first)
when _T_565 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_566 = eq(d_first, UInt<1>(0h0))
node _T_567 = and(io.in.d.valid, _T_566)
when _T_567 :
node _T_568 = eq(io.in.d.bits.opcode, opcode_1)
node _T_569 = asUInt(reset)
node _T_570 = eq(_T_569, UInt<1>(0h0))
when _T_570 :
node _T_571 = eq(_T_568, UInt<1>(0h0))
when _T_571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_568, UInt<1>(0h1), "") : assert_92
node _T_572 = eq(io.in.d.bits.param, param_1)
node _T_573 = asUInt(reset)
node _T_574 = eq(_T_573, UInt<1>(0h0))
when _T_574 :
node _T_575 = eq(_T_572, UInt<1>(0h0))
when _T_575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_572, UInt<1>(0h1), "") : assert_93
node _T_576 = eq(io.in.d.bits.size, size_1)
node _T_577 = asUInt(reset)
node _T_578 = eq(_T_577, UInt<1>(0h0))
when _T_578 :
node _T_579 = eq(_T_576, UInt<1>(0h0))
when _T_579 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_576, UInt<1>(0h1), "") : assert_94
node _T_580 = eq(io.in.d.bits.source, source_1)
node _T_581 = asUInt(reset)
node _T_582 = eq(_T_581, UInt<1>(0h0))
when _T_582 :
node _T_583 = eq(_T_580, UInt<1>(0h0))
when _T_583 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_580, UInt<1>(0h1), "") : assert_95
node _T_584 = eq(io.in.d.bits.sink, sink)
node _T_585 = asUInt(reset)
node _T_586 = eq(_T_585, UInt<1>(0h0))
when _T_586 :
node _T_587 = eq(_T_584, UInt<1>(0h0))
when _T_587 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_584, UInt<1>(0h1), "") : assert_96
node _T_588 = eq(io.in.d.bits.denied, denied)
node _T_589 = asUInt(reset)
node _T_590 = eq(_T_589, UInt<1>(0h0))
when _T_590 :
node _T_591 = eq(_T_588, UInt<1>(0h0))
when _T_591 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_588, UInt<1>(0h1), "") : assert_97
node _T_592 = and(io.in.d.ready, io.in.d.valid)
node _T_593 = and(_T_592, d_first)
when _T_593 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<10>, clock, reset, UInt<10>(0h0)
regreset inflight_opcodes : UInt<40>, clock, reset, UInt<40>(0h0)
regreset inflight_sizes : UInt<40>, clock, reset, UInt<40>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<10>
connect a_set, UInt<10>(0h0)
wire a_set_wo_ready : UInt<10>
connect a_set_wo_ready, UInt<10>(0h0)
wire a_opcodes_set : UInt<40>
connect a_opcodes_set, UInt<40>(0h0)
wire a_sizes_set : UInt<40>
connect a_sizes_set, UInt<40>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_594 = and(io.in.a.valid, a_first_1)
node _T_595 = and(_T_594, UInt<1>(0h1))
when _T_595 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_596 = and(io.in.a.ready, io.in.a.valid)
node _T_597 = and(_T_596, a_first_1)
node _T_598 = and(_T_597, UInt<1>(0h1))
when _T_598 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_599 = dshr(inflight, io.in.a.bits.source)
node _T_600 = bits(_T_599, 0, 0)
node _T_601 = eq(_T_600, UInt<1>(0h0))
node _T_602 = asUInt(reset)
node _T_603 = eq(_T_602, UInt<1>(0h0))
when _T_603 :
node _T_604 = eq(_T_601, UInt<1>(0h0))
when _T_604 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_601, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<10>
connect d_clr, UInt<10>(0h0)
wire d_clr_wo_ready : UInt<10>
connect d_clr_wo_ready, UInt<10>(0h0)
wire d_opcodes_clr : UInt<40>
connect d_opcodes_clr, UInt<40>(0h0)
wire d_sizes_clr : UInt<40>
connect d_sizes_clr, UInt<40>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_605 = and(io.in.d.valid, d_first_1)
node _T_606 = and(_T_605, UInt<1>(0h1))
node _T_607 = eq(d_release_ack, UInt<1>(0h0))
node _T_608 = and(_T_606, _T_607)
when _T_608 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_609 = and(io.in.d.ready, io.in.d.valid)
node _T_610 = and(_T_609, d_first_1)
node _T_611 = and(_T_610, UInt<1>(0h1))
node _T_612 = eq(d_release_ack, UInt<1>(0h0))
node _T_613 = and(_T_611, _T_612)
when _T_613 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_614 = and(io.in.d.valid, d_first_1)
node _T_615 = and(_T_614, UInt<1>(0h1))
node _T_616 = eq(d_release_ack, UInt<1>(0h0))
node _T_617 = and(_T_615, _T_616)
when _T_617 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_618 = dshr(inflight, io.in.d.bits.source)
node _T_619 = bits(_T_618, 0, 0)
node _T_620 = or(_T_619, same_cycle_resp)
node _T_621 = asUInt(reset)
node _T_622 = eq(_T_621, UInt<1>(0h0))
when _T_622 :
node _T_623 = eq(_T_620, UInt<1>(0h0))
when _T_623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_620, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_626 = or(_T_624, _T_625)
node _T_627 = asUInt(reset)
node _T_628 = eq(_T_627, UInt<1>(0h0))
when _T_628 :
node _T_629 = eq(_T_626, UInt<1>(0h0))
when _T_629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_626, UInt<1>(0h1), "") : assert_100
node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_630, UInt<1>(0h1), "") : assert_101
else :
node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_636 = or(_T_634, _T_635)
node _T_637 = asUInt(reset)
node _T_638 = eq(_T_637, UInt<1>(0h0))
when _T_638 :
node _T_639 = eq(_T_636, UInt<1>(0h0))
when _T_639 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_636, UInt<1>(0h1), "") : assert_102
node _T_640 = eq(io.in.d.bits.size, a_size_lookup)
node _T_641 = asUInt(reset)
node _T_642 = eq(_T_641, UInt<1>(0h0))
when _T_642 :
node _T_643 = eq(_T_640, UInt<1>(0h0))
when _T_643 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_640, UInt<1>(0h1), "") : assert_103
node _T_644 = and(io.in.d.valid, d_first_1)
node _T_645 = and(_T_644, a_first_1)
node _T_646 = and(_T_645, io.in.a.valid)
node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_648 = and(_T_646, _T_647)
node _T_649 = eq(d_release_ack, UInt<1>(0h0))
node _T_650 = and(_T_648, _T_649)
when _T_650 :
node _T_651 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_652 = or(_T_651, io.in.a.ready)
node _T_653 = asUInt(reset)
node _T_654 = eq(_T_653, UInt<1>(0h0))
when _T_654 :
node _T_655 = eq(_T_652, UInt<1>(0h0))
when _T_655 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_652, UInt<1>(0h1), "") : assert_104
node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_657 = orr(a_set_wo_ready)
node _T_658 = eq(_T_657, UInt<1>(0h0))
node _T_659 = or(_T_656, _T_658)
node _T_660 = asUInt(reset)
node _T_661 = eq(_T_660, UInt<1>(0h0))
when _T_661 :
node _T_662 = eq(_T_659, UInt<1>(0h0))
when _T_662 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_659, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_178
node _T_663 = orr(inflight)
node _T_664 = eq(_T_663, UInt<1>(0h0))
node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_666 = or(_T_664, _T_665)
node _T_667 = lt(watchdog, plusarg_reader.out)
node _T_668 = or(_T_666, _T_667)
node _T_669 = asUInt(reset)
node _T_670 = eq(_T_669, UInt<1>(0h0))
when _T_670 :
node _T_671 = eq(_T_668, UInt<1>(0h0))
when _T_671 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_668, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_672 = and(io.in.a.ready, io.in.a.valid)
node _T_673 = and(io.in.d.ready, io.in.d.valid)
node _T_674 = or(_T_672, _T_673)
when _T_674 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<10>, clock, reset, UInt<10>(0h0)
regreset inflight_opcodes_1 : UInt<40>, clock, reset, UInt<40>(0h0)
regreset inflight_sizes_1 : UInt<40>, clock, reset, UInt<40>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<28>(0h0)
connect _c_first_WIRE.bits.source, UInt<4>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<28>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<10>
connect c_set, UInt<10>(0h0)
wire c_set_wo_ready : UInt<10>
connect c_set_wo_ready, UInt<10>(0h0)
wire c_opcodes_set : UInt<40>
connect c_opcodes_set, UInt<40>(0h0)
wire c_sizes_set : UInt<40>
connect c_sizes_set, UInt<40>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<28>(0h0)
connect _WIRE_6.bits.source, UInt<4>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_675 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<28>(0h0)
connect _WIRE_8.bits.source, UInt<4>(0h0)
connect _WIRE_8.bits.size, UInt<3>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_678 = and(_T_676, _T_677)
node _T_679 = and(_T_675, _T_678)
when _T_679 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<28>(0h0)
connect _WIRE_10.bits.source, UInt<4>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_681 = and(_T_680, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<28>(0h0)
connect _WIRE_12.bits.source, UInt<4>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_684 = and(_T_682, _T_683)
node _T_685 = and(_T_681, _T_684)
when _T_685 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<28>(0h0)
connect _WIRE_14.bits.source, UInt<4>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_686 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_687 = bits(_T_686, 0, 0)
node _T_688 = eq(_T_687, UInt<1>(0h0))
node _T_689 = asUInt(reset)
node _T_690 = eq(_T_689, UInt<1>(0h0))
when _T_690 :
node _T_691 = eq(_T_688, UInt<1>(0h0))
when _T_691 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_688, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<10>
connect d_clr_1, UInt<10>(0h0)
wire d_clr_wo_ready_1 : UInt<10>
connect d_clr_wo_ready_1, UInt<10>(0h0)
wire d_opcodes_clr_1 : UInt<40>
connect d_opcodes_clr_1, UInt<40>(0h0)
wire d_sizes_clr_1 : UInt<40>
connect d_sizes_clr_1, UInt<40>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_692 = and(io.in.d.valid, d_first_2)
node _T_693 = and(_T_692, UInt<1>(0h1))
node _T_694 = and(_T_693, d_release_ack_1)
when _T_694 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_695 = and(io.in.d.ready, io.in.d.valid)
node _T_696 = and(_T_695, d_first_2)
node _T_697 = and(_T_696, UInt<1>(0h1))
node _T_698 = and(_T_697, d_release_ack_1)
when _T_698 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_699 = and(io.in.d.valid, d_first_2)
node _T_700 = and(_T_699, UInt<1>(0h1))
node _T_701 = and(_T_700, d_release_ack_1)
when _T_701 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_702 = dshr(inflight_1, io.in.d.bits.source)
node _T_703 = bits(_T_702, 0, 0)
node _T_704 = or(_T_703, same_cycle_resp_1)
node _T_705 = asUInt(reset)
node _T_706 = eq(_T_705, UInt<1>(0h0))
when _T_706 :
node _T_707 = eq(_T_704, UInt<1>(0h0))
when _T_707 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_704, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<28>(0h0)
connect _WIRE_16.bits.source, UInt<4>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_709 = asUInt(reset)
node _T_710 = eq(_T_709, UInt<1>(0h0))
when _T_710 :
node _T_711 = eq(_T_708, UInt<1>(0h0))
when _T_711 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_708, UInt<1>(0h1), "") : assert_109
else :
node _T_712 = eq(io.in.d.bits.size, c_size_lookup)
node _T_713 = asUInt(reset)
node _T_714 = eq(_T_713, UInt<1>(0h0))
when _T_714 :
node _T_715 = eq(_T_712, UInt<1>(0h0))
when _T_715 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_712, UInt<1>(0h1), "") : assert_110
node _T_716 = and(io.in.d.valid, d_first_2)
node _T_717 = and(_T_716, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<28>(0h0)
connect _WIRE_18.bits.source, UInt<4>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_718 = and(_T_717, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<28>(0h0)
connect _WIRE_20.bits.source, UInt<4>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_720 = and(_T_718, _T_719)
node _T_721 = and(_T_720, d_release_ack_1)
node _T_722 = eq(c_probe_ack, UInt<1>(0h0))
node _T_723 = and(_T_721, _T_722)
when _T_723 :
node _T_724 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<28>(0h0)
connect _WIRE_22.bits.source, UInt<4>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_725 = or(_T_724, _WIRE_23.ready)
node _T_726 = asUInt(reset)
node _T_727 = eq(_T_726, UInt<1>(0h0))
when _T_727 :
node _T_728 = eq(_T_725, UInt<1>(0h0))
when _T_728 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_725, UInt<1>(0h1), "") : assert_111
node _T_729 = orr(c_set_wo_ready)
when _T_729 :
node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_731 = asUInt(reset)
node _T_732 = eq(_T_731, UInt<1>(0h0))
when _T_732 :
node _T_733 = eq(_T_730, UInt<1>(0h0))
when _T_733 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_730, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_179
node _T_734 = orr(inflight_1)
node _T_735 = eq(_T_734, UInt<1>(0h0))
node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_737 = or(_T_735, _T_736)
node _T_738 = lt(watchdog_1, plusarg_reader_1.out)
node _T_739 = or(_T_737, _T_738)
node _T_740 = asUInt(reset)
node _T_741 = eq(_T_740, UInt<1>(0h0))
when _T_741 :
node _T_742 = eq(_T_739, UInt<1>(0h0))
when _T_742 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_739, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<28>(0h0)
connect _WIRE_24.bits.source, UInt<4>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_744 = and(io.in.d.ready, io.in.d.valid)
node _T_745 = or(_T_743, _T_744)
when _T_745 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_85( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_first_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_first_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_first_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_first_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [130:0] _c_opcodes_set_T_1 = 131'h0; // @[Monitor.scala:767:54]
wire [130:0] _c_sizes_set_T_1 = 131'h0; // @[Monitor.scala:768:52]
wire [6:0] _c_opcodes_set_T = 7'h0; // @[Monitor.scala:767:79]
wire [6:0] _c_sizes_set_T = 7'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [15:0] _c_set_wo_ready_T = 16'h1; // @[OneHot.scala:58:35]
wire [15:0] _c_set_T = 16'h1; // @[OneHot.scala:58:35]
wire [39:0] c_opcodes_set = 40'h0; // @[Monitor.scala:740:34]
wire [39:0] c_sizes_set = 40'h0; // @[Monitor.scala:741:34]
wire [9:0] c_set = 10'h0; // @[Monitor.scala:738:34]
wire [9:0] c_set_wo_ready = 10'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_4 = source_ok_uncommonBits < 4'hA; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [27:0] _is_aligned_T = {22'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [3:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}]
wire [3:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_10 = source_ok_uncommonBits_1 < 4'hA; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_672; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [3:0] source; // @[Monitor.scala:390:22]
reg [27:0] address; // @[Monitor.scala:391:22]
wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_745; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [3:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [9:0] inflight; // @[Monitor.scala:614:27]
reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [39:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [9:0] a_set; // @[Monitor.scala:626:34]
wire [9:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [39:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [39:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [6:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [39:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [39:0] _a_opcode_lookup_T_6 = {36'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [39:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [39:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [39:0] _a_size_lookup_T_6 = {36'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [39:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[39:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [15:0] _GEN_2 = 16'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [15:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_598 ? _a_set_T[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [6:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [6:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [6:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [130:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [9:0] d_clr; // @[Monitor.scala:664:34]
wire [9:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [39:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [39:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [15:0] _GEN_5 = 16'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_613 ? _d_clr_T[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [142:0] _d_sizes_clr_T_5 = 143'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [9:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [9:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [9:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [39:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [39:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [39:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [39:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [39:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [39:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [9:0] inflight_1; // @[Monitor.scala:726:35]
wire [9:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [39:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [39:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [39:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [39:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [39:0] _c_opcode_lookup_T_6 = {36'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [39:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [39:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [39:0] _c_size_lookup_T_6 = {36'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [39:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[39:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [9:0] d_clr_1; // @[Monitor.scala:774:34]
wire [9:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [39:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [39:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_698 ? _d_clr_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [142:0] _d_sizes_clr_T_11 = 143'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 4'h0; // @[Monitor.scala:36:7, :795:113]
wire [9:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [9:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [39:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [39:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [39:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [39:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module MSHR_3 :
input clock : Clock
input reset : Reset
output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}}, status : { valid : UInt<1>, bits : { set : UInt<10>, tag : UInt<13>, way : UInt<3>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<13>, set : UInt<10>, param : UInt<3>, source : UInt<3>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<13>, set : UInt<10>, clients : UInt<1>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<3>, tag : UInt<13>, set : UInt<10>, way : UInt<3>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<10>, way : UInt<3>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<10>, tag : UInt<13>, source : UInt<6>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<3>}}, flip nestedwb : { set : UInt<10>, tag : UInt<13>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}}
regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}, clock
regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}, clock
when meta_valid :
node _T = eq(meta.state, UInt<2>(0h0))
when _T :
node _T_1 = orr(meta.clients)
node _T_2 = eq(_T_1, UInt<1>(0h0))
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
node _T_6 = eq(meta.dirty, UInt<1>(0h0))
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1
assert(clock, _T_6, UInt<1>(0h1), "") : assert_1
node _T_10 = eq(meta.state, UInt<2>(0h1))
when _T_10 :
node _T_11 = eq(meta.dirty, UInt<1>(0h0))
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2
assert(clock, _T_11, UInt<1>(0h1), "") : assert_2
node _T_15 = eq(meta.state, UInt<2>(0h2))
when _T_15 :
node _T_16 = orr(meta.clients)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3
assert(clock, _T_16, UInt<1>(0h1), "") : assert_3
node _T_20 = sub(meta.clients, UInt<1>(0h1))
node _T_21 = tail(_T_20, 1)
node _T_22 = and(meta.clients, _T_21)
node _T_23 = eq(_T_22, UInt<1>(0h0))
node _T_24 = asUInt(reset)
node _T_25 = eq(_T_24, UInt<1>(0h0))
when _T_25 :
node _T_26 = eq(_T_23, UInt<1>(0h0))
when _T_26 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4
assert(clock, _T_23, UInt<1>(0h1), "") : assert_4
node _T_27 = eq(meta.state, UInt<2>(0h3))
when _T_27 :
skip
regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1)
reg sink : UInt<3>, clock
reg gotT : UInt<1>, clock
reg bad_grant : UInt<1>, clock
reg probes_done : UInt<1>, clock
reg probes_toN : UInt<1>, clock
reg probes_noT : UInt<1>, clock
node _T_28 = neq(meta.state, UInt<2>(0h0))
node _T_29 = and(meta_valid, _T_28)
node _T_30 = eq(io.nestedwb.set, request.set)
node _T_31 = and(_T_29, _T_30)
node _T_32 = eq(io.nestedwb.tag, meta.tag)
node _T_33 = and(_T_31, _T_32)
when _T_33 :
when io.nestedwb.b_clr_dirty :
connect meta.dirty, UInt<1>(0h0)
when io.nestedwb.c_set_dirty :
connect meta.dirty, UInt<1>(0h1)
when io.nestedwb.b_toB :
connect meta.state, UInt<2>(0h1)
when io.nestedwb.b_toN :
connect meta.hit, UInt<1>(0h0)
connect io.status.valid, request_valid
connect io.status.bits.set, request.set
connect io.status.bits.tag, request.tag
connect io.status.bits.way, meta.way
node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0))
node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0))
node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0))
node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2)
node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0))
node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4)
node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6)
node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7)
connect io.status.bits.blockB, _io_status_bits_blockB_T_8
node _io_status_bits_nestB_T = and(meta_valid, w_releaseack)
node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast)
node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast)
node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3)
connect io.status.bits.nestB, _io_status_bits_nestB_T_4
node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0))
connect io.status.bits.blockC, _io_status_bits_blockC_T
node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1)
node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3)
node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4)
connect io.status.bits.nestC, _io_status_bits_nestC_T_5
node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0))
node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0))
node _T_36 = or(_T_34, _T_35)
node _T_37 = asUInt(reset)
node _T_38 = eq(_T_37, UInt<1>(0h0))
when _T_38 :
node _T_39 = eq(_T_36, UInt<1>(0h0))
when _T_39 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB || !io.status.bits.blockB)\n") : printf_5
assert(clock, _T_36, UInt<1>(0h1), "") : assert_5
node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0))
node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0))
node _T_42 = or(_T_40, _T_41)
node _T_43 = asUInt(reset)
node _T_44 = eq(_T_43, UInt<1>(0h0))
when _T_44 :
node _T_45 = eq(_T_42, UInt<1>(0h0))
when _T_45 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC || !io.status.bits.blockC)\n") : printf_6
assert(clock, _T_42, UInt<1>(0h1), "") : assert_6
node _no_wait_T = and(w_rprobeacklast, w_releaseack)
node _no_wait_T_1 = and(_no_wait_T, w_grantlast)
node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast)
node no_wait = and(_no_wait_T_2, w_grantack)
node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0))
node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release)
node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe)
connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2
node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0))
node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1)
connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2
node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0))
node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst)
node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0))
node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst)
node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3)
connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4
node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0))
node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack)
node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant)
connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2
node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0))
node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst)
connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1
node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0))
node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack)
connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1
node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0))
node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst)
node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0))
node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait)
node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3)
connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4
connect io.schedule.bits.reload, no_wait
node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid)
node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid)
node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid)
node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid)
node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid)
node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid)
connect io.schedule.valid, _io_schedule_valid_T_5
when io.schedule.ready :
connect s_rprobe, UInt<1>(0h1)
when w_rprobeackfirst :
connect s_release, UInt<1>(0h1)
connect s_pprobe, UInt<1>(0h1)
node _T_46 = and(s_release, s_pprobe)
when _T_46 :
connect s_acquire, UInt<1>(0h1)
when w_releaseack :
connect s_flush, UInt<1>(0h1)
when w_pprobeackfirst :
connect s_probeack, UInt<1>(0h1)
when w_grantfirst :
connect s_grantack, UInt<1>(0h1)
node _T_47 = and(w_pprobeack, w_grant)
when _T_47 :
connect s_execute, UInt<1>(0h1)
when no_wait :
connect s_writeback, UInt<1>(0h1)
when no_wait :
connect request_valid, UInt<1>(0h0)
connect meta_valid, UInt<1>(0h0)
wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}
connect final_meta_writeback, meta
node req_clientBit = eq(request.source, UInt<6>(0h21))
node _req_needT_T = bits(request.opcode, 2, 2)
node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0))
node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5))
node _req_needT_T_3 = eq(request.param, UInt<1>(0h1))
node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3)
node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4)
node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6))
node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7))
node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7)
node _req_needT_T_9 = neq(request.param, UInt<2>(0h0))
node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9)
node req_needT = or(_req_needT_T_5, _req_needT_T_10)
node _req_acquire_T = eq(request.opcode, UInt<3>(0h6))
node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7))
node req_acquire = or(_req_acquire_T, _req_acquire_T_1)
node _meta_no_clients_T = orr(meta.clients)
node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0))
node _req_promoteT_T = eq(meta.state, UInt<2>(0h3))
node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T)
node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT)
node req_promoteT = and(req_acquire, _req_promoteT_T_2)
node _T_48 = and(request.prio[2], UInt<1>(0h1))
when _T_48 :
node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0)
node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T)
connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1
node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3))
node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2))
node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1)
node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state)
connect final_meta_writeback.state, _final_meta_writeback_state_T_3
node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1))
node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2))
node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1)
node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5))
node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3)
node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0))
node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5)
node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7
connect final_meta_writeback.hit, UInt<1>(0h1)
else :
node _T_49 = and(request.control, UInt<1>(0h1))
when _T_49 :
when meta.hit :
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h0)
node _final_meta_writeback_clients_T_8 = not(probes_toN)
node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9
connect final_meta_writeback.hit, UInt<1>(0h0)
else :
node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty)
node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2)
node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0))
node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4)
connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5
node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0))
node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1))
node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire)
node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state)
node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1))
node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state)
node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11)
node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state)
node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13)
node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15)
node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16)
connect final_meta_writeback.state, _final_meta_writeback_state_T_17
node _final_meta_writeback_clients_T_10 = not(probes_toN)
node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10)
node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0))
node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0))
node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14
connect final_meta_writeback.tag, request.tag
connect final_meta_writeback.hit, UInt<1>(0h1)
when bad_grant :
when meta.hit :
node _T_50 = eq(meta_valid, UInt<1>(0h0))
node _T_51 = eq(meta.state, UInt<2>(0h1))
node _T_52 = or(_T_50, _T_51)
node _T_53 = asUInt(reset)
node _T_54 = eq(_T_53, UInt<1>(0h0))
when _T_54 :
node _T_55 = eq(_T_52, UInt<1>(0h0))
when _T_55 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid || meta.state === BRANCH)\n") : printf_7
assert(clock, _T_52, UInt<1>(0h1), "") : assert_7
connect final_meta_writeback.hit, UInt<1>(0h1)
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h1)
node _final_meta_writeback_clients_T_15 = not(probes_toN)
node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16
else :
connect final_meta_writeback.hit, UInt<1>(0h0)
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h0)
connect final_meta_writeback.clients, UInt<1>(0h0)
wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>}
connect invalid.dirty, UInt<1>(0h0)
connect invalid.state, UInt<2>(0h0)
connect invalid.clients, UInt<1>(0h0)
connect invalid.tag, UInt<1>(0h0)
node _honour_BtoT_T = and(meta.clients, req_clientBit)
node _honour_BtoT_T_1 = orr(_honour_BtoT_T)
node honour_BtoT = and(meta.hit, _honour_BtoT_T_1)
node _excluded_client_T = and(meta.hit, request.prio[0])
node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6))
node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7))
node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2)
node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4))
node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4)
node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5))
node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0))
node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7)
node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8)
node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0))
connect io.schedule.bits.a.bits.tag, request.tag
connect io.schedule.bits.a.bits.set, request.set
node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0))
connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1
node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6))
node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0))
node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7))
node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2)
node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0))
node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4)
connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5
connect io.schedule.bits.a.bits.source, UInt<1>(0h0)
node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1)
node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2)
connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3
node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag)
connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1
connect io.schedule.bits.b.bits.set, request.set
node _io_schedule_bits_b_bits_clients_T = not(excluded_client)
node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T)
connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1
node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6))
connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T
node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1))
node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1))
connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1
connect io.schedule.bits.c.bits.source, UInt<1>(0h0)
connect io.schedule.bits.c.bits.tag, meta.tag
connect io.schedule.bits.c.bits.set, request.set
connect io.schedule.bits.c.bits.way, meta.way
connect io.schedule.bits.c.bits.dirty, meta.dirty
connect io.schedule.bits.d.bits.set, request.set
connect io.schedule.bits.d.bits.put, request.put
connect io.schedule.bits.d.bits.offset, request.offset
connect io.schedule.bits.d.bits.tag, request.tag
connect io.schedule.bits.d.bits.source, request.source
connect io.schedule.bits.d.bits.size, request.size
connect io.schedule.bits.d.bits.param, request.param
connect io.schedule.bits.d.bits.opcode, request.opcode
connect io.schedule.bits.d.bits.control, request.control
connect io.schedule.bits.d.bits.prio, request.prio
node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0))
node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0))
node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param)
node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param)
node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param)
node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4)
node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param)
node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6)
node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8)
connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9
connect io.schedule.bits.d.bits.sink, UInt<1>(0h0)
connect io.schedule.bits.d.bits.way, meta.way
connect io.schedule.bits.d.bits.bad, bad_grant
connect io.schedule.bits.e.bits.sink, sink
connect io.schedule.bits.x.bits.fail, UInt<1>(0h0)
connect io.schedule.bits.dir.bits.set, request.set
connect io.schedule.bits.dir.bits.way, meta.way
node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0))
wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>}
connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag
connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients
connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state
connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty
node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE)
connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1
node _evict_T = eq(meta.hit, UInt<1>(0h0))
wire evict : UInt
connect evict, UInt<1>(0h0)
node evict_c = orr(meta.clients)
node _evict_T_1 = eq(UInt<2>(0h1), meta.state)
when _evict_T_1 :
node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1))
connect evict, _evict_out_T
else :
node _evict_T_2 = eq(UInt<2>(0h2), meta.state)
when _evict_T_2 :
node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect evict, _evict_out_T_1
else :
node _evict_T_3 = eq(UInt<2>(0h3), meta.state)
when _evict_T_3 :
node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3)
connect evict, _evict_out_T_4
else :
node _evict_T_4 = eq(UInt<2>(0h0), meta.state)
when _evict_T_4 :
connect evict, UInt<4>(0h8)
node _evict_T_5 = eq(_evict_T, UInt<1>(0h0))
when _evict_T_5 :
connect evict, UInt<4>(0h8)
wire before : UInt
connect before, UInt<1>(0h0)
node before_c = orr(meta.clients)
node _before_T = eq(UInt<2>(0h1), meta.state)
when _before_T :
node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1))
connect before, _before_out_T
else :
node _before_T_1 = eq(UInt<2>(0h2), meta.state)
when _before_T_1 :
node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect before, _before_out_T_1
else :
node _before_T_2 = eq(UInt<2>(0h3), meta.state)
when _before_T_2 :
node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3)
connect before, _before_out_T_4
else :
node _before_T_3 = eq(UInt<2>(0h0), meta.state)
when _before_T_3 :
connect before, UInt<4>(0h8)
node _before_T_4 = eq(meta.hit, UInt<1>(0h0))
when _before_T_4 :
connect before, UInt<4>(0h8)
wire after : UInt
connect after, UInt<1>(0h0)
node after_c = orr(final_meta_writeback.clients)
node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state)
when _after_T :
node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1))
connect after, _after_out_T
else :
node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state)
when _after_T_1 :
node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect after, _after_out_T_1
else :
node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state)
when _after_T_2 :
node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3)
connect after, _after_out_T_4
else :
node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state)
when _after_T_3 :
connect after, UInt<4>(0h8)
node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0))
when _after_T_4 :
connect after, UInt<4>(0h8)
node _T_56 = eq(s_release, UInt<1>(0h0))
node _T_57 = and(_T_56, w_rprobeackfirst)
node _T_58 = and(_T_57, io.schedule.ready)
when _T_58 :
node _T_59 = eq(evict, UInt<1>(0h1))
node _T_60 = eq(_T_59, UInt<1>(0h0))
node _T_61 = asUInt(reset)
node _T_62 = eq(_T_61, UInt<1>(0h0))
when _T_62 :
node _T_63 = eq(_T_60, UInt<1>(0h0))
when _T_63 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8
assert(clock, _T_60, UInt<1>(0h1), "") : assert_8
node _T_64 = eq(before, UInt<1>(0h1))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(_T_65, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9
assert(clock, _T_65, UInt<1>(0h1), "") : assert_9
node _T_69 = eq(evict, UInt<1>(0h0))
node _T_70 = eq(_T_69, UInt<1>(0h0))
node _T_71 = asUInt(reset)
node _T_72 = eq(_T_71, UInt<1>(0h0))
when _T_72 :
node _T_73 = eq(_T_70, UInt<1>(0h0))
when _T_73 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10
assert(clock, _T_70, UInt<1>(0h1), "") : assert_10
node _T_74 = eq(before, UInt<1>(0h0))
node _T_75 = eq(_T_74, UInt<1>(0h0))
node _T_76 = asUInt(reset)
node _T_77 = eq(_T_76, UInt<1>(0h0))
when _T_77 :
node _T_78 = eq(_T_75, UInt<1>(0h0))
when _T_78 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11
assert(clock, _T_75, UInt<1>(0h1), "") : assert_11
node _T_79 = eq(evict, UInt<3>(0h7))
node _T_80 = eq(before, UInt<3>(0h7))
node _T_81 = eq(evict, UInt<3>(0h5))
node _T_82 = eq(before, UInt<3>(0h5))
node _T_83 = eq(evict, UInt<3>(0h4))
node _T_84 = eq(before, UInt<3>(0h4))
node _T_85 = eq(evict, UInt<3>(0h6))
node _T_86 = eq(before, UInt<3>(0h6))
node _T_87 = eq(evict, UInt<2>(0h3))
node _T_88 = eq(before, UInt<2>(0h3))
node _T_89 = eq(evict, UInt<2>(0h2))
node _T_90 = eq(before, UInt<2>(0h2))
node _T_91 = eq(s_writeback, UInt<1>(0h0))
node _T_92 = and(_T_91, no_wait)
node _T_93 = and(_T_92, io.schedule.ready)
when _T_93 :
node _T_94 = eq(before, UInt<4>(0h8))
node _T_95 = eq(after, UInt<1>(0h1))
node _T_96 = and(_T_94, _T_95)
node _T_97 = eq(_T_96, UInt<1>(0h0))
node _T_98 = asUInt(reset)
node _T_99 = eq(_T_98, UInt<1>(0h0))
when _T_99 :
node _T_100 = eq(_T_97, UInt<1>(0h0))
when _T_100 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12
assert(clock, _T_97, UInt<1>(0h1), "") : assert_12
node _T_101 = eq(before, UInt<4>(0h8))
node _T_102 = eq(after, UInt<1>(0h0))
node _T_103 = and(_T_101, _T_102)
node _T_104 = eq(_T_103, UInt<1>(0h0))
node _T_105 = asUInt(reset)
node _T_106 = eq(_T_105, UInt<1>(0h0))
when _T_106 :
node _T_107 = eq(_T_104, UInt<1>(0h0))
when _T_107 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13
assert(clock, _T_104, UInt<1>(0h1), "") : assert_13
node _T_108 = eq(before, UInt<4>(0h8))
node _T_109 = eq(after, UInt<3>(0h7))
node _T_110 = and(_T_108, _T_109)
node _T_111 = eq(before, UInt<4>(0h8))
node _T_112 = eq(after, UInt<3>(0h5))
node _T_113 = and(_T_111, _T_112)
node _T_114 = eq(_T_113, UInt<1>(0h0))
node _T_115 = asUInt(reset)
node _T_116 = eq(_T_115, UInt<1>(0h0))
when _T_116 :
node _T_117 = eq(_T_114, UInt<1>(0h0))
when _T_117 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14
assert(clock, _T_114, UInt<1>(0h1), "") : assert_14
node _T_118 = eq(before, UInt<4>(0h8))
node _T_119 = eq(after, UInt<3>(0h4))
node _T_120 = and(_T_118, _T_119)
node _T_121 = eq(_T_120, UInt<1>(0h0))
node _T_122 = asUInt(reset)
node _T_123 = eq(_T_122, UInt<1>(0h0))
when _T_123 :
node _T_124 = eq(_T_121, UInt<1>(0h0))
when _T_124 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15
assert(clock, _T_121, UInt<1>(0h1), "") : assert_15
node _T_125 = eq(before, UInt<4>(0h8))
node _T_126 = eq(after, UInt<3>(0h6))
node _T_127 = and(_T_125, _T_126)
node _T_128 = eq(before, UInt<4>(0h8))
node _T_129 = eq(after, UInt<2>(0h3))
node _T_130 = and(_T_128, _T_129)
node _T_131 = eq(before, UInt<4>(0h8))
node _T_132 = eq(after, UInt<2>(0h2))
node _T_133 = and(_T_131, _T_132)
node _T_134 = eq(_T_133, UInt<1>(0h0))
node _T_135 = asUInt(reset)
node _T_136 = eq(_T_135, UInt<1>(0h0))
when _T_136 :
node _T_137 = eq(_T_134, UInt<1>(0h0))
when _T_137 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16
assert(clock, _T_134, UInt<1>(0h1), "") : assert_16
node _T_138 = eq(before, UInt<1>(0h1))
node _T_139 = eq(after, UInt<4>(0h8))
node _T_140 = and(_T_138, _T_139)
node _T_141 = eq(_T_140, UInt<1>(0h0))
node _T_142 = asUInt(reset)
node _T_143 = eq(_T_142, UInt<1>(0h0))
when _T_143 :
node _T_144 = eq(_T_141, UInt<1>(0h0))
when _T_144 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17
assert(clock, _T_141, UInt<1>(0h1), "") : assert_17
node _T_145 = eq(before, UInt<1>(0h1))
node _T_146 = eq(after, UInt<1>(0h0))
node _T_147 = and(_T_145, _T_146)
node _T_148 = eq(_T_147, UInt<1>(0h0))
node _T_149 = asUInt(reset)
node _T_150 = eq(_T_149, UInt<1>(0h0))
when _T_150 :
node _T_151 = eq(_T_148, UInt<1>(0h0))
when _T_151 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18
assert(clock, _T_148, UInt<1>(0h1), "") : assert_18
node _T_152 = eq(before, UInt<1>(0h1))
node _T_153 = eq(after, UInt<3>(0h7))
node _T_154 = and(_T_152, _T_153)
node _T_155 = eq(_T_154, UInt<1>(0h0))
node _T_156 = asUInt(reset)
node _T_157 = eq(_T_156, UInt<1>(0h0))
when _T_157 :
node _T_158 = eq(_T_155, UInt<1>(0h0))
when _T_158 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19
assert(clock, _T_155, UInt<1>(0h1), "") : assert_19
node _T_159 = eq(before, UInt<1>(0h1))
node _T_160 = eq(after, UInt<3>(0h5))
node _T_161 = and(_T_159, _T_160)
node _T_162 = eq(_T_161, UInt<1>(0h0))
node _T_163 = asUInt(reset)
node _T_164 = eq(_T_163, UInt<1>(0h0))
when _T_164 :
node _T_165 = eq(_T_162, UInt<1>(0h0))
when _T_165 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20
assert(clock, _T_162, UInt<1>(0h1), "") : assert_20
node _T_166 = eq(before, UInt<1>(0h1))
node _T_167 = eq(after, UInt<3>(0h4))
node _T_168 = and(_T_166, _T_167)
node _T_169 = eq(_T_168, UInt<1>(0h0))
node _T_170 = asUInt(reset)
node _T_171 = eq(_T_170, UInt<1>(0h0))
when _T_171 :
node _T_172 = eq(_T_169, UInt<1>(0h0))
when _T_172 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21
assert(clock, _T_169, UInt<1>(0h1), "") : assert_21
node _T_173 = eq(before, UInt<1>(0h1))
node _T_174 = eq(after, UInt<3>(0h6))
node _T_175 = and(_T_173, _T_174)
node _T_176 = eq(_T_175, UInt<1>(0h0))
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_T_176, UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22
assert(clock, _T_176, UInt<1>(0h1), "") : assert_22
node _T_180 = eq(before, UInt<1>(0h1))
node _T_181 = eq(after, UInt<2>(0h3))
node _T_182 = and(_T_180, _T_181)
node _T_183 = eq(_T_182, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(before, UInt<1>(0h1))
node _T_188 = eq(after, UInt<2>(0h2))
node _T_189 = and(_T_187, _T_188)
node _T_190 = eq(_T_189, UInt<1>(0h0))
node _T_191 = asUInt(reset)
node _T_192 = eq(_T_191, UInt<1>(0h0))
when _T_192 :
node _T_193 = eq(_T_190, UInt<1>(0h0))
when _T_193 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24
assert(clock, _T_190, UInt<1>(0h1), "") : assert_24
node _T_194 = eq(before, UInt<1>(0h0))
node _T_195 = eq(after, UInt<4>(0h8))
node _T_196 = and(_T_194, _T_195)
node _T_197 = eq(_T_196, UInt<1>(0h0))
node _T_198 = asUInt(reset)
node _T_199 = eq(_T_198, UInt<1>(0h0))
when _T_199 :
node _T_200 = eq(_T_197, UInt<1>(0h0))
when _T_200 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25
assert(clock, _T_197, UInt<1>(0h1), "") : assert_25
node _T_201 = eq(before, UInt<1>(0h0))
node _T_202 = eq(after, UInt<1>(0h1))
node _T_203 = and(_T_201, _T_202)
node _T_204 = eq(_T_203, UInt<1>(0h0))
node _T_205 = asUInt(reset)
node _T_206 = eq(_T_205, UInt<1>(0h0))
when _T_206 :
node _T_207 = eq(_T_204, UInt<1>(0h0))
when _T_207 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26
assert(clock, _T_204, UInt<1>(0h1), "") : assert_26
node _T_208 = eq(before, UInt<1>(0h0))
node _T_209 = eq(after, UInt<3>(0h7))
node _T_210 = and(_T_208, _T_209)
node _T_211 = eq(_T_210, UInt<1>(0h0))
node _T_212 = asUInt(reset)
node _T_213 = eq(_T_212, UInt<1>(0h0))
when _T_213 :
node _T_214 = eq(_T_211, UInt<1>(0h0))
when _T_214 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27
assert(clock, _T_211, UInt<1>(0h1), "") : assert_27
node _T_215 = eq(before, UInt<1>(0h0))
node _T_216 = eq(after, UInt<3>(0h5))
node _T_217 = and(_T_215, _T_216)
node _T_218 = eq(_T_217, UInt<1>(0h0))
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28
assert(clock, _T_218, UInt<1>(0h1), "") : assert_28
node _T_222 = eq(before, UInt<1>(0h0))
node _T_223 = eq(after, UInt<3>(0h6))
node _T_224 = and(_T_222, _T_223)
node _T_225 = eq(_T_224, UInt<1>(0h0))
node _T_226 = asUInt(reset)
node _T_227 = eq(_T_226, UInt<1>(0h0))
when _T_227 :
node _T_228 = eq(_T_225, UInt<1>(0h0))
when _T_228 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29
assert(clock, _T_225, UInt<1>(0h1), "") : assert_29
node _T_229 = eq(before, UInt<1>(0h0))
node _T_230 = eq(after, UInt<3>(0h4))
node _T_231 = and(_T_229, _T_230)
node _T_232 = eq(_T_231, UInt<1>(0h0))
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30
assert(clock, _T_232, UInt<1>(0h1), "") : assert_30
node _T_236 = eq(before, UInt<1>(0h0))
node _T_237 = eq(after, UInt<2>(0h3))
node _T_238 = and(_T_236, _T_237)
node _T_239 = eq(_T_238, UInt<1>(0h0))
node _T_240 = asUInt(reset)
node _T_241 = eq(_T_240, UInt<1>(0h0))
when _T_241 :
node _T_242 = eq(_T_239, UInt<1>(0h0))
when _T_242 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31
assert(clock, _T_239, UInt<1>(0h1), "") : assert_31
node _T_243 = eq(before, UInt<1>(0h0))
node _T_244 = eq(after, UInt<2>(0h2))
node _T_245 = and(_T_243, _T_244)
node _T_246 = eq(_T_245, UInt<1>(0h0))
node _T_247 = asUInt(reset)
node _T_248 = eq(_T_247, UInt<1>(0h0))
when _T_248 :
node _T_249 = eq(_T_246, UInt<1>(0h0))
when _T_249 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32
assert(clock, _T_246, UInt<1>(0h1), "") : assert_32
node _T_250 = eq(before, UInt<3>(0h7))
node _T_251 = eq(after, UInt<4>(0h8))
node _T_252 = and(_T_250, _T_251)
node _T_253 = eq(_T_252, UInt<1>(0h0))
node _T_254 = asUInt(reset)
node _T_255 = eq(_T_254, UInt<1>(0h0))
when _T_255 :
node _T_256 = eq(_T_253, UInt<1>(0h0))
when _T_256 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33
assert(clock, _T_253, UInt<1>(0h1), "") : assert_33
node _T_257 = eq(before, UInt<3>(0h7))
node _T_258 = eq(after, UInt<1>(0h1))
node _T_259 = and(_T_257, _T_258)
node _T_260 = eq(_T_259, UInt<1>(0h0))
node _T_261 = asUInt(reset)
node _T_262 = eq(_T_261, UInt<1>(0h0))
when _T_262 :
node _T_263 = eq(_T_260, UInt<1>(0h0))
when _T_263 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34
assert(clock, _T_260, UInt<1>(0h1), "") : assert_34
node _T_264 = eq(before, UInt<3>(0h7))
node _T_265 = eq(after, UInt<1>(0h0))
node _T_266 = and(_T_264, _T_265)
node _T_267 = eq(_T_266, UInt<1>(0h0))
node _T_268 = asUInt(reset)
node _T_269 = eq(_T_268, UInt<1>(0h0))
when _T_269 :
node _T_270 = eq(_T_267, UInt<1>(0h0))
when _T_270 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35
assert(clock, _T_267, UInt<1>(0h1), "") : assert_35
node _T_271 = eq(before, UInt<3>(0h7))
node _T_272 = eq(after, UInt<3>(0h5))
node _T_273 = and(_T_271, _T_272)
node _T_274 = eq(_T_273, UInt<1>(0h0))
node _T_275 = asUInt(reset)
node _T_276 = eq(_T_275, UInt<1>(0h0))
when _T_276 :
node _T_277 = eq(_T_274, UInt<1>(0h0))
when _T_277 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36
assert(clock, _T_274, UInt<1>(0h1), "") : assert_36
node _T_278 = eq(before, UInt<3>(0h7))
node _T_279 = eq(after, UInt<3>(0h6))
node _T_280 = and(_T_278, _T_279)
node _T_281 = eq(before, UInt<3>(0h7))
node _T_282 = eq(after, UInt<3>(0h4))
node _T_283 = and(_T_281, _T_282)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = asUInt(reset)
node _T_286 = eq(_T_285, UInt<1>(0h0))
when _T_286 :
node _T_287 = eq(_T_284, UInt<1>(0h0))
when _T_287 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37
assert(clock, _T_284, UInt<1>(0h1), "") : assert_37
node _T_288 = eq(before, UInt<3>(0h7))
node _T_289 = eq(after, UInt<2>(0h3))
node _T_290 = and(_T_288, _T_289)
node _T_291 = eq(before, UInt<3>(0h7))
node _T_292 = eq(after, UInt<2>(0h2))
node _T_293 = and(_T_291, _T_292)
node _T_294 = eq(_T_293, UInt<1>(0h0))
node _T_295 = asUInt(reset)
node _T_296 = eq(_T_295, UInt<1>(0h0))
when _T_296 :
node _T_297 = eq(_T_294, UInt<1>(0h0))
when _T_297 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38
assert(clock, _T_294, UInt<1>(0h1), "") : assert_38
node _T_298 = eq(before, UInt<3>(0h5))
node _T_299 = eq(after, UInt<4>(0h8))
node _T_300 = and(_T_298, _T_299)
node _T_301 = eq(_T_300, UInt<1>(0h0))
node _T_302 = asUInt(reset)
node _T_303 = eq(_T_302, UInt<1>(0h0))
when _T_303 :
node _T_304 = eq(_T_301, UInt<1>(0h0))
when _T_304 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39
assert(clock, _T_301, UInt<1>(0h1), "") : assert_39
node _T_305 = eq(before, UInt<3>(0h5))
node _T_306 = eq(after, UInt<1>(0h1))
node _T_307 = and(_T_305, _T_306)
node _T_308 = eq(_T_307, UInt<1>(0h0))
node _T_309 = asUInt(reset)
node _T_310 = eq(_T_309, UInt<1>(0h0))
when _T_310 :
node _T_311 = eq(_T_308, UInt<1>(0h0))
when _T_311 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40
assert(clock, _T_308, UInt<1>(0h1), "") : assert_40
node _T_312 = eq(before, UInt<3>(0h5))
node _T_313 = eq(after, UInt<1>(0h0))
node _T_314 = and(_T_312, _T_313)
node _T_315 = eq(_T_314, UInt<1>(0h0))
node _T_316 = asUInt(reset)
node _T_317 = eq(_T_316, UInt<1>(0h0))
when _T_317 :
node _T_318 = eq(_T_315, UInt<1>(0h0))
when _T_318 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41
assert(clock, _T_315, UInt<1>(0h1), "") : assert_41
node _T_319 = eq(before, UInt<3>(0h5))
node _T_320 = eq(after, UInt<3>(0h7))
node _T_321 = and(_T_319, _T_320)
node _T_322 = eq(before, UInt<3>(0h5))
node _T_323 = eq(after, UInt<3>(0h6))
node _T_324 = and(_T_322, _T_323)
node _T_325 = eq(before, UInt<3>(0h5))
node _T_326 = eq(after, UInt<3>(0h4))
node _T_327 = and(_T_325, _T_326)
node _T_328 = eq(_T_327, UInt<1>(0h0))
node _T_329 = asUInt(reset)
node _T_330 = eq(_T_329, UInt<1>(0h0))
when _T_330 :
node _T_331 = eq(_T_328, UInt<1>(0h0))
when _T_331 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42
assert(clock, _T_328, UInt<1>(0h1), "") : assert_42
node _T_332 = eq(before, UInt<3>(0h5))
node _T_333 = eq(after, UInt<2>(0h3))
node _T_334 = and(_T_332, _T_333)
node _T_335 = eq(before, UInt<3>(0h5))
node _T_336 = eq(after, UInt<2>(0h2))
node _T_337 = and(_T_335, _T_336)
node _T_338 = eq(_T_337, UInt<1>(0h0))
node _T_339 = asUInt(reset)
node _T_340 = eq(_T_339, UInt<1>(0h0))
when _T_340 :
node _T_341 = eq(_T_338, UInt<1>(0h0))
when _T_341 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43
assert(clock, _T_338, UInt<1>(0h1), "") : assert_43
node _T_342 = eq(before, UInt<3>(0h6))
node _T_343 = eq(after, UInt<4>(0h8))
node _T_344 = and(_T_342, _T_343)
node _T_345 = eq(_T_344, UInt<1>(0h0))
node _T_346 = asUInt(reset)
node _T_347 = eq(_T_346, UInt<1>(0h0))
when _T_347 :
node _T_348 = eq(_T_345, UInt<1>(0h0))
when _T_348 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44
assert(clock, _T_345, UInt<1>(0h1), "") : assert_44
node _T_349 = eq(before, UInt<3>(0h6))
node _T_350 = eq(after, UInt<1>(0h1))
node _T_351 = and(_T_349, _T_350)
node _T_352 = eq(_T_351, UInt<1>(0h0))
node _T_353 = asUInt(reset)
node _T_354 = eq(_T_353, UInt<1>(0h0))
when _T_354 :
node _T_355 = eq(_T_352, UInt<1>(0h0))
when _T_355 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45
assert(clock, _T_352, UInt<1>(0h1), "") : assert_45
node _T_356 = eq(before, UInt<3>(0h6))
node _T_357 = eq(after, UInt<1>(0h0))
node _T_358 = and(_T_356, _T_357)
node _T_359 = eq(_T_358, UInt<1>(0h0))
node _T_360 = asUInt(reset)
node _T_361 = eq(_T_360, UInt<1>(0h0))
when _T_361 :
node _T_362 = eq(_T_359, UInt<1>(0h0))
when _T_362 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46
assert(clock, _T_359, UInt<1>(0h1), "") : assert_46
node _T_363 = eq(before, UInt<3>(0h6))
node _T_364 = eq(after, UInt<3>(0h7))
node _T_365 = and(_T_363, _T_364)
node _T_366 = eq(_T_365, UInt<1>(0h0))
node _T_367 = asUInt(reset)
node _T_368 = eq(_T_367, UInt<1>(0h0))
when _T_368 :
node _T_369 = eq(_T_366, UInt<1>(0h0))
when _T_369 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47
assert(clock, _T_366, UInt<1>(0h1), "") : assert_47
node _T_370 = eq(before, UInt<3>(0h6))
node _T_371 = eq(after, UInt<3>(0h5))
node _T_372 = and(_T_370, _T_371)
node _T_373 = eq(_T_372, UInt<1>(0h0))
node _T_374 = asUInt(reset)
node _T_375 = eq(_T_374, UInt<1>(0h0))
when _T_375 :
node _T_376 = eq(_T_373, UInt<1>(0h0))
when _T_376 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48
assert(clock, _T_373, UInt<1>(0h1), "") : assert_48
node _T_377 = eq(before, UInt<3>(0h6))
node _T_378 = eq(after, UInt<3>(0h4))
node _T_379 = and(_T_377, _T_378)
node _T_380 = eq(_T_379, UInt<1>(0h0))
node _T_381 = asUInt(reset)
node _T_382 = eq(_T_381, UInt<1>(0h0))
when _T_382 :
node _T_383 = eq(_T_380, UInt<1>(0h0))
when _T_383 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49
assert(clock, _T_380, UInt<1>(0h1), "") : assert_49
node _T_384 = eq(before, UInt<3>(0h6))
node _T_385 = eq(after, UInt<2>(0h3))
node _T_386 = and(_T_384, _T_385)
node _T_387 = eq(_T_386, UInt<1>(0h0))
node _T_388 = asUInt(reset)
node _T_389 = eq(_T_388, UInt<1>(0h0))
when _T_389 :
node _T_390 = eq(_T_387, UInt<1>(0h0))
when _T_390 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50
assert(clock, _T_387, UInt<1>(0h1), "") : assert_50
node _T_391 = eq(before, UInt<3>(0h6))
node _T_392 = eq(after, UInt<2>(0h2))
node _T_393 = and(_T_391, _T_392)
node _T_394 = eq(before, UInt<3>(0h4))
node _T_395 = eq(after, UInt<4>(0h8))
node _T_396 = and(_T_394, _T_395)
node _T_397 = eq(_T_396, UInt<1>(0h0))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51
assert(clock, _T_397, UInt<1>(0h1), "") : assert_51
node _T_401 = eq(before, UInt<3>(0h4))
node _T_402 = eq(after, UInt<1>(0h1))
node _T_403 = and(_T_401, _T_402)
node _T_404 = eq(_T_403, UInt<1>(0h0))
node _T_405 = asUInt(reset)
node _T_406 = eq(_T_405, UInt<1>(0h0))
when _T_406 :
node _T_407 = eq(_T_404, UInt<1>(0h0))
when _T_407 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52
assert(clock, _T_404, UInt<1>(0h1), "") : assert_52
node _T_408 = eq(before, UInt<3>(0h4))
node _T_409 = eq(after, UInt<1>(0h0))
node _T_410 = and(_T_408, _T_409)
node _T_411 = eq(_T_410, UInt<1>(0h0))
node _T_412 = asUInt(reset)
node _T_413 = eq(_T_412, UInt<1>(0h0))
when _T_413 :
node _T_414 = eq(_T_411, UInt<1>(0h0))
when _T_414 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53
assert(clock, _T_411, UInt<1>(0h1), "") : assert_53
node _T_415 = eq(before, UInt<3>(0h4))
node _T_416 = eq(after, UInt<3>(0h7))
node _T_417 = and(_T_415, _T_416)
node _T_418 = eq(_T_417, UInt<1>(0h0))
node _T_419 = asUInt(reset)
node _T_420 = eq(_T_419, UInt<1>(0h0))
when _T_420 :
node _T_421 = eq(_T_418, UInt<1>(0h0))
when _T_421 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54
assert(clock, _T_418, UInt<1>(0h1), "") : assert_54
node _T_422 = eq(before, UInt<3>(0h4))
node _T_423 = eq(after, UInt<3>(0h5))
node _T_424 = and(_T_422, _T_423)
node _T_425 = eq(_T_424, UInt<1>(0h0))
node _T_426 = asUInt(reset)
node _T_427 = eq(_T_426, UInt<1>(0h0))
when _T_427 :
node _T_428 = eq(_T_425, UInt<1>(0h0))
when _T_428 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55
assert(clock, _T_425, UInt<1>(0h1), "") : assert_55
node _T_429 = eq(before, UInt<3>(0h4))
node _T_430 = eq(after, UInt<3>(0h6))
node _T_431 = and(_T_429, _T_430)
node _T_432 = eq(before, UInt<3>(0h4))
node _T_433 = eq(after, UInt<2>(0h3))
node _T_434 = and(_T_432, _T_433)
node _T_435 = eq(_T_434, UInt<1>(0h0))
node _T_436 = asUInt(reset)
node _T_437 = eq(_T_436, UInt<1>(0h0))
when _T_437 :
node _T_438 = eq(_T_435, UInt<1>(0h0))
when _T_438 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56
assert(clock, _T_435, UInt<1>(0h1), "") : assert_56
node _T_439 = eq(before, UInt<3>(0h4))
node _T_440 = eq(after, UInt<2>(0h2))
node _T_441 = and(_T_439, _T_440)
node _T_442 = eq(before, UInt<2>(0h3))
node _T_443 = eq(after, UInt<4>(0h8))
node _T_444 = and(_T_442, _T_443)
node _T_445 = eq(_T_444, UInt<1>(0h0))
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57
assert(clock, _T_445, UInt<1>(0h1), "") : assert_57
node _T_449 = eq(before, UInt<2>(0h3))
node _T_450 = eq(after, UInt<1>(0h1))
node _T_451 = and(_T_449, _T_450)
node _T_452 = eq(_T_451, UInt<1>(0h0))
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(_T_452, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58
assert(clock, _T_452, UInt<1>(0h1), "") : assert_58
node _T_456 = eq(before, UInt<2>(0h3))
node _T_457 = eq(after, UInt<1>(0h0))
node _T_458 = and(_T_456, _T_457)
node _T_459 = eq(_T_458, UInt<1>(0h0))
node _T_460 = asUInt(reset)
node _T_461 = eq(_T_460, UInt<1>(0h0))
when _T_461 :
node _T_462 = eq(_T_459, UInt<1>(0h0))
when _T_462 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59
assert(clock, _T_459, UInt<1>(0h1), "") : assert_59
node _T_463 = eq(before, UInt<2>(0h3))
node _T_464 = eq(after, UInt<3>(0h7))
node _T_465 = and(_T_463, _T_464)
node _T_466 = eq(before, UInt<2>(0h3))
node _T_467 = eq(after, UInt<3>(0h5))
node _T_468 = and(_T_466, _T_467)
node _T_469 = eq(before, UInt<2>(0h3))
node _T_470 = eq(after, UInt<3>(0h6))
node _T_471 = and(_T_469, _T_470)
node _T_472 = eq(before, UInt<2>(0h3))
node _T_473 = eq(after, UInt<3>(0h4))
node _T_474 = and(_T_472, _T_473)
node _T_475 = eq(before, UInt<2>(0h3))
node _T_476 = eq(after, UInt<2>(0h2))
node _T_477 = and(_T_475, _T_476)
node _T_478 = eq(before, UInt<2>(0h2))
node _T_479 = eq(after, UInt<4>(0h8))
node _T_480 = and(_T_478, _T_479)
node _T_481 = eq(_T_480, UInt<1>(0h0))
node _T_482 = asUInt(reset)
node _T_483 = eq(_T_482, UInt<1>(0h0))
when _T_483 :
node _T_484 = eq(_T_481, UInt<1>(0h0))
when _T_484 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60
assert(clock, _T_481, UInt<1>(0h1), "") : assert_60
node _T_485 = eq(before, UInt<2>(0h2))
node _T_486 = eq(after, UInt<1>(0h1))
node _T_487 = and(_T_485, _T_486)
node _T_488 = eq(_T_487, UInt<1>(0h0))
node _T_489 = asUInt(reset)
node _T_490 = eq(_T_489, UInt<1>(0h0))
when _T_490 :
node _T_491 = eq(_T_488, UInt<1>(0h0))
when _T_491 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61
assert(clock, _T_488, UInt<1>(0h1), "") : assert_61
node _T_492 = eq(before, UInt<2>(0h2))
node _T_493 = eq(after, UInt<1>(0h0))
node _T_494 = and(_T_492, _T_493)
node _T_495 = eq(_T_494, UInt<1>(0h0))
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_T_495, UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62
assert(clock, _T_495, UInt<1>(0h1), "") : assert_62
node _T_499 = eq(before, UInt<2>(0h2))
node _T_500 = eq(after, UInt<3>(0h7))
node _T_501 = and(_T_499, _T_500)
node _T_502 = eq(_T_501, UInt<1>(0h0))
node _T_503 = asUInt(reset)
node _T_504 = eq(_T_503, UInt<1>(0h0))
when _T_504 :
node _T_505 = eq(_T_502, UInt<1>(0h0))
when _T_505 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63
assert(clock, _T_502, UInt<1>(0h1), "") : assert_63
node _T_506 = eq(before, UInt<2>(0h2))
node _T_507 = eq(after, UInt<3>(0h5))
node _T_508 = and(_T_506, _T_507)
node _T_509 = eq(_T_508, UInt<1>(0h0))
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64
assert(clock, _T_509, UInt<1>(0h1), "") : assert_64
node _T_513 = eq(before, UInt<2>(0h2))
node _T_514 = eq(after, UInt<3>(0h6))
node _T_515 = and(_T_513, _T_514)
node _T_516 = eq(before, UInt<2>(0h2))
node _T_517 = eq(after, UInt<3>(0h4))
node _T_518 = and(_T_516, _T_517)
node _T_519 = eq(before, UInt<2>(0h2))
node _T_520 = eq(after, UInt<2>(0h3))
node _T_521 = and(_T_519, _T_520)
node _T_522 = eq(_T_521, UInt<1>(0h0))
node _T_523 = asUInt(reset)
node _T_524 = eq(_T_523, UInt<1>(0h0))
when _T_524 :
node _T_525 = eq(_T_522, UInt<1>(0h0))
when _T_525 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65
assert(clock, _T_522, UInt<1>(0h1), "") : assert_65
node probe_bit = eq(io.sinkc.bits.source, UInt<6>(0h21))
node _last_probe_T = or(probes_done, probe_bit)
node _last_probe_T_1 = not(excluded_client)
node _last_probe_T_2 = and(meta.clients, _last_probe_T_1)
node last_probe = eq(_last_probe_T, _last_probe_T_2)
node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1))
node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2))
node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1)
node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5))
node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3)
when io.sinkc.valid :
node _T_526 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1))
node _T_527 = and(probe_toN, _T_526)
node _T_528 = eq(probe_toN, UInt<1>(0h0))
node _T_529 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1))
node _T_530 = and(_T_528, _T_529)
node _probes_done_T = or(probes_done, probe_bit)
connect probes_done, _probes_done_T
node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0))
node _probes_toN_T_1 = or(probes_toN, _probes_toN_T)
connect probes_toN, _probes_toN_T_1
node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3))
node _probes_noT_T_1 = or(probes_noT, _probes_noT_T)
connect probes_noT, _probes_noT_T_1
node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe)
connect w_rprobeackfirst, _w_rprobeackfirst_T
node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last)
node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T)
connect w_rprobeacklast, _w_rprobeacklast_T_1
node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe)
connect w_pprobeackfirst, _w_pprobeackfirst_T
node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last)
node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T)
connect w_pprobeacklast, _w_pprobeacklast_T_1
node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0))
node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T)
node set_pprobeack = and(last_probe, _set_pprobeack_T_1)
node _w_pprobeack_T = or(w_pprobeack, set_pprobeack)
connect w_pprobeack, _w_pprobeack_T
node _T_531 = eq(set_pprobeack, UInt<1>(0h0))
node _T_532 = and(_T_531, w_rprobeackfirst)
node _T_533 = and(set_pprobeack, w_rprobeackfirst)
node _T_534 = neq(meta.state, UInt<2>(0h0))
node _T_535 = eq(io.sinkc.bits.tag, meta.tag)
node _T_536 = and(_T_534, _T_535)
node _T_537 = and(_T_536, io.sinkc.bits.data)
when _T_537 :
connect meta.dirty, UInt<1>(0h1)
when io.sinkd.valid :
node _T_538 = eq(io.sinkd.bits.opcode, UInt<3>(0h4))
node _T_539 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_540 = or(_T_538, _T_539)
when _T_540 :
connect sink, io.sinkd.bits.sink
connect w_grantfirst, UInt<1>(0h1)
connect w_grantlast, io.sinkd.bits.last
connect bad_grant, io.sinkd.bits.denied
node _w_grant_T = eq(request.offset, UInt<1>(0h0))
node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last)
connect w_grant, _w_grant_T_1
node _T_541 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_542 = eq(request.offset, UInt<1>(0h0))
node _T_543 = and(_T_541, _T_542)
node _T_544 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_545 = neq(request.offset, UInt<1>(0h0))
node _T_546 = and(_T_544, _T_545)
node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0))
connect gotT, _gotT_T
else :
node _T_547 = eq(io.sinkd.bits.opcode, UInt<3>(0h6))
when _T_547 :
connect w_releaseack, UInt<1>(0h1)
when io.sinke.valid :
connect w_grantack, UInt<1>(0h1)
wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}
connect allocate_as_full.set, io.allocate.bits.set
connect allocate_as_full.put, io.allocate.bits.put
connect allocate_as_full.offset, io.allocate.bits.offset
connect allocate_as_full.tag, io.allocate.bits.tag
connect allocate_as_full.source, io.allocate.bits.source
connect allocate_as_full.size, io.allocate.bits.size
connect allocate_as_full.param, io.allocate.bits.param
connect allocate_as_full.opcode, io.allocate.bits.opcode
connect allocate_as_full.control, io.allocate.bits.control
connect allocate_as_full.prio, io.allocate.bits.prio
node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat)
node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits)
node new_request = mux(io.allocate.valid, allocate_as_full, request)
node _new_needT_T = bits(new_request.opcode, 2, 2)
node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0))
node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5))
node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1))
node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3)
node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4)
node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6))
node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7))
node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7)
node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0))
node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9)
node new_needT = or(_new_needT_T_5, _new_needT_T_10)
node new_clientBit = eq(new_request.source, UInt<6>(0h21))
node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6))
node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7))
node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1)
node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4))
node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3)
node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5))
node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0))
node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6)
node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0))
wire prior : UInt
connect prior, UInt<1>(0h0)
node prior_c = orr(final_meta_writeback.clients)
node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state)
when _prior_T :
node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1))
connect prior, _prior_out_T
else :
node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state)
when _prior_T_1 :
node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect prior, _prior_out_T_1
else :
node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state)
when _prior_T_2 :
node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3)
connect prior, _prior_out_T_4
else :
node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state)
when _prior_T_3 :
connect prior, UInt<4>(0h8)
node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0))
when _prior_T_4 :
connect prior, UInt<4>(0h8)
node _T_548 = and(io.allocate.valid, io.allocate.bits.repeat)
when _T_548 :
node _T_549 = eq(prior, UInt<4>(0h8))
node _T_550 = eq(prior, UInt<1>(0h1))
node _T_551 = eq(_T_550, UInt<1>(0h0))
node _T_552 = asUInt(reset)
node _T_553 = eq(_T_552, UInt<1>(0h0))
when _T_553 :
node _T_554 = eq(_T_551, UInt<1>(0h0))
when _T_554 :
printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_66
assert(clock, _T_551, UInt<1>(0h1), "") : assert_66
node _T_555 = eq(prior, UInt<1>(0h0))
node _T_556 = eq(_T_555, UInt<1>(0h0))
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_67
assert(clock, _T_556, UInt<1>(0h1), "") : assert_67
node _T_560 = eq(prior, UInt<3>(0h7))
node _T_561 = eq(prior, UInt<3>(0h5))
node _T_562 = eq(prior, UInt<3>(0h4))
node _T_563 = eq(prior, UInt<3>(0h6))
node _T_564 = eq(prior, UInt<2>(0h3))
node _T_565 = eq(prior, UInt<2>(0h2))
when io.allocate.valid :
node _T_566 = eq(request_valid, UInt<1>(0h0))
node _T_567 = and(io.schedule.ready, io.schedule.valid)
node _T_568 = and(no_wait, _T_567)
node _T_569 = or(_T_566, _T_568)
node _T_570 = asUInt(reset)
node _T_571 = eq(_T_570, UInt<1>(0h0))
when _T_571 :
node _T_572 = eq(_T_569, UInt<1>(0h0))
when _T_572 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid || (no_wait && io.schedule.fire))\n") : printf_68
assert(clock, _T_569, UInt<1>(0h1), "") : assert_68
connect request_valid, UInt<1>(0h1)
connect request.set, io.allocate.bits.set
connect request.put, io.allocate.bits.put
connect request.offset, io.allocate.bits.offset
connect request.tag, io.allocate.bits.tag
connect request.source, io.allocate.bits.source
connect request.size, io.allocate.bits.size
connect request.param, io.allocate.bits.param
connect request.opcode, io.allocate.bits.opcode
connect request.control, io.allocate.bits.control
connect request.prio, io.allocate.bits.prio
node _T_573 = and(io.allocate.valid, io.allocate.bits.repeat)
node _T_574 = or(io.directory.valid, _T_573)
when _T_574 :
connect meta_valid, UInt<1>(0h1)
connect meta, new_meta
connect probes_done, UInt<1>(0h0)
connect probes_toN, UInt<1>(0h0)
connect probes_noT, UInt<1>(0h0)
connect gotT, UInt<1>(0h0)
connect bad_grant, UInt<1>(0h0)
connect s_rprobe, UInt<1>(0h1)
connect w_rprobeackfirst, UInt<1>(0h1)
connect w_rprobeacklast, UInt<1>(0h1)
connect s_release, UInt<1>(0h1)
connect w_releaseack, UInt<1>(0h1)
connect s_pprobe, UInt<1>(0h1)
connect s_acquire, UInt<1>(0h1)
connect s_flush, UInt<1>(0h1)
connect w_grantfirst, UInt<1>(0h1)
connect w_grantlast, UInt<1>(0h1)
connect w_grant, UInt<1>(0h1)
connect w_pprobeackfirst, UInt<1>(0h1)
connect w_pprobeacklast, UInt<1>(0h1)
connect w_pprobeack, UInt<1>(0h1)
connect s_probeack, UInt<1>(0h1)
connect s_grantack, UInt<1>(0h1)
connect s_execute, UInt<1>(0h1)
connect w_grantack, UInt<1>(0h1)
connect s_writeback, UInt<1>(0h1)
node _T_575 = and(new_request.prio[2], UInt<1>(0h1))
when _T_575 :
connect s_execute, UInt<1>(0h0)
node _T_576 = bits(new_request.opcode, 0, 0)
node _T_577 = eq(new_meta.dirty, UInt<1>(0h0))
node _T_578 = and(_T_576, _T_577)
when _T_578 :
connect s_writeback, UInt<1>(0h0)
node _T_579 = eq(new_request.param, UInt<3>(0h0))
node _T_580 = eq(new_request.param, UInt<3>(0h4))
node _T_581 = or(_T_579, _T_580)
node _T_582 = eq(new_meta.state, UInt<2>(0h2))
node _T_583 = and(_T_581, _T_582)
when _T_583 :
connect s_writeback, UInt<1>(0h0)
node _T_584 = eq(new_request.param, UInt<3>(0h1))
node _T_585 = eq(new_request.param, UInt<3>(0h2))
node _T_586 = or(_T_584, _T_585)
node _T_587 = eq(new_request.param, UInt<3>(0h5))
node _T_588 = or(_T_586, _T_587)
node _T_589 = and(new_meta.clients, new_clientBit)
node _T_590 = neq(_T_589, UInt<1>(0h0))
node _T_591 = and(_T_588, _T_590)
when _T_591 :
connect s_writeback, UInt<1>(0h0)
node _T_592 = asUInt(reset)
node _T_593 = eq(_T_592, UInt<1>(0h0))
when _T_593 :
node _T_594 = eq(new_meta.hit, UInt<1>(0h0))
when _T_594 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_69
assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_69
else :
node _T_595 = and(new_request.control, UInt<1>(0h1))
when _T_595 :
connect s_flush, UInt<1>(0h0)
when new_meta.hit :
connect s_release, UInt<1>(0h0)
connect w_releaseack, UInt<1>(0h0)
node _T_596 = neq(new_meta.clients, UInt<1>(0h0))
node _T_597 = and(UInt<1>(0h1), _T_596)
when _T_597 :
connect s_rprobe, UInt<1>(0h0)
connect w_rprobeackfirst, UInt<1>(0h0)
connect w_rprobeacklast, UInt<1>(0h0)
else :
connect s_execute, UInt<1>(0h0)
node _T_598 = eq(new_meta.hit, UInt<1>(0h0))
node _T_599 = neq(new_meta.state, UInt<2>(0h0))
node _T_600 = and(_T_598, _T_599)
when _T_600 :
connect s_release, UInt<1>(0h0)
connect w_releaseack, UInt<1>(0h0)
node _T_601 = neq(new_meta.clients, UInt<1>(0h0))
node _T_602 = and(UInt<1>(0h1), _T_601)
when _T_602 :
connect s_rprobe, UInt<1>(0h0)
connect w_rprobeackfirst, UInt<1>(0h0)
connect w_rprobeacklast, UInt<1>(0h0)
node _T_603 = eq(new_meta.hit, UInt<1>(0h0))
node _T_604 = eq(new_meta.state, UInt<2>(0h1))
node _T_605 = and(_T_604, new_needT)
node _T_606 = or(_T_603, _T_605)
when _T_606 :
connect s_acquire, UInt<1>(0h0)
connect w_grantfirst, UInt<1>(0h0)
connect w_grantlast, UInt<1>(0h0)
connect w_grant, UInt<1>(0h0)
connect s_grantack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_607 = eq(new_meta.state, UInt<2>(0h2))
node _T_608 = or(new_needT, _T_607)
node _T_609 = and(new_meta.hit, _T_608)
node _T_610 = not(new_skipProbe)
node _T_611 = and(new_meta.clients, _T_610)
node _T_612 = neq(_T_611, UInt<1>(0h0))
node _T_613 = and(_T_609, _T_612)
node _T_614 = and(UInt<1>(0h1), _T_613)
when _T_614 :
connect s_pprobe, UInt<1>(0h0)
connect w_pprobeackfirst, UInt<1>(0h0)
connect w_pprobeacklast, UInt<1>(0h0)
connect w_pprobeack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_615 = eq(new_request.opcode, UInt<3>(0h6))
node _T_616 = eq(new_request.opcode, UInt<3>(0h7))
node _T_617 = or(_T_615, _T_616)
when _T_617 :
connect w_grantack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_618 = bits(new_request.opcode, 2, 2)
node _T_619 = eq(_T_618, UInt<1>(0h0))
node _T_620 = and(_T_619, new_meta.hit)
node _T_621 = eq(new_meta.dirty, UInt<1>(0h0))
node _T_622 = and(_T_620, _T_621)
when _T_622 :
connect s_writeback, UInt<1>(0h0) | module MSHR_3( // @[MSHR.scala:84:7]
input clock, // @[MSHR.scala:84:7]
input reset, // @[MSHR.scala:84:7]
input io_allocate_valid, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_0, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_1, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_2, // @[MSHR.scala:86:14]
input io_allocate_bits_control, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14]
input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14]
input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14]
input io_allocate_bits_repeat, // @[MSHR.scala:86:14]
input io_directory_valid, // @[MSHR.scala:86:14]
input io_directory_bits_dirty, // @[MSHR.scala:86:14]
input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14]
input io_directory_bits_clients, // @[MSHR.scala:86:14]
input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14]
input io_directory_bits_hit, // @[MSHR.scala:86:14]
input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14]
output io_status_valid, // @[MSHR.scala:86:14]
output [9:0] io_status_bits_set, // @[MSHR.scala:86:14]
output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14]
output [2:0] io_status_bits_way, // @[MSHR.scala:86:14]
output io_status_bits_blockB, // @[MSHR.scala:86:14]
output io_status_bits_nestB, // @[MSHR.scala:86:14]
output io_status_bits_blockC, // @[MSHR.scala:86:14]
output io_status_bits_nestC, // @[MSHR.scala:86:14]
input io_schedule_ready, // @[MSHR.scala:86:14]
output io_schedule_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_a_valid, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14]
output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14]
output io_schedule_bits_b_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14]
output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14]
output io_schedule_bits_c_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14]
output io_schedule_bits_d_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14]
output io_schedule_bits_e_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14]
output io_schedule_bits_x_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14]
output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14]
output io_schedule_bits_reload, // @[MSHR.scala:86:14]
input io_sinkc_valid, // @[MSHR.scala:86:14]
input io_sinkc_bits_last, // @[MSHR.scala:86:14]
input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14]
input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14]
input io_sinkc_bits_data, // @[MSHR.scala:86:14]
input io_sinkd_valid, // @[MSHR.scala:86:14]
input io_sinkd_bits_last, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14]
input io_sinkd_bits_denied, // @[MSHR.scala:86:14]
input io_sinke_valid, // @[MSHR.scala:86:14]
input [2:0] io_sinke_bits_sink, // @[MSHR.scala:86:14]
input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14]
input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14]
input io_nestedwb_b_toN, // @[MSHR.scala:86:14]
input io_nestedwb_b_toB, // @[MSHR.scala:86:14]
input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14]
input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14]
);
wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38]
wire final_meta_writeback_clients; // @[MSHR.scala:215:38]
wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38]
wire final_meta_writeback_dirty; // @[MSHR.scala:215:38]
wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7]
wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7]
wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7]
wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7]
wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7]
wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7]
wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7]
wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7]
wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7]
wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7]
wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7]
wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7]
wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7]
wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7]
wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7]
wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7]
wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7]
wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7]
wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7]
wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7]
wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7]
wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7]
wire [2:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7]
wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7]
wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7]
wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7]
wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_a_bits_source = 3'h0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_source = 3'h0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_sink = 3'h0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7]
wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68]
wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80]
wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21]
wire invalid_clients = 1'h0; // @[MSHR.scala:268:21]
wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137]
wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137]
wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21]
wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21]
wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70]
wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34]
wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34]
wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34]
wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40]
wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93]
wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28]
wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39]
wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105]
wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55]
wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91]
wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41]
wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41]
wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41]
wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51]
wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64]
wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41]
wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41]
wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57]
wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41]
wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43]
wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40]
wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66]
wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41]
wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41]
wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41]
wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41]
wire no_wait; // @[MSHR.scala:183:83]
wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7]
wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7]
wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockB_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestB_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockC_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestC_0; // @[MSHR.scala:84:7]
wire io_status_valid_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7]
wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7]
wire io_schedule_valid_0; // @[MSHR.scala:84:7]
reg request_valid; // @[MSHR.scala:97:30]
assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30]
reg request_prio_0; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20]
reg request_prio_1; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20]
reg request_prio_2; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20]
reg request_control; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_opcode; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_param; // @[MSHR.scala:98:20]
reg [2:0] request_size; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_source; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20]
reg [12:0] request_tag; // @[MSHR.scala:98:20]
assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_offset; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_put; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20]
reg [9:0] request_set; // @[MSHR.scala:98:20]
assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
reg meta_valid; // @[MSHR.scala:99:27]
reg meta_dirty; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17]
reg [1:0] meta_state; // @[MSHR.scala:100:17]
reg meta_clients; // @[MSHR.scala:100:17]
wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39]
wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
reg [12:0] meta_tag; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17]
reg meta_hit; // @[MSHR.scala:100:17]
reg [2:0] meta_way; // @[MSHR.scala:100:17]
assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38]
reg s_rprobe; // @[MSHR.scala:121:33]
reg w_rprobeackfirst; // @[MSHR.scala:122:33]
reg w_rprobeacklast; // @[MSHR.scala:123:33]
reg s_release; // @[MSHR.scala:124:33]
reg w_releaseack; // @[MSHR.scala:125:33]
reg s_pprobe; // @[MSHR.scala:126:33]
reg s_acquire; // @[MSHR.scala:127:33]
reg s_flush; // @[MSHR.scala:128:33]
reg w_grantfirst; // @[MSHR.scala:129:33]
reg w_grantlast; // @[MSHR.scala:130:33]
reg w_grant; // @[MSHR.scala:131:33]
reg w_pprobeackfirst; // @[MSHR.scala:132:33]
reg w_pprobeacklast; // @[MSHR.scala:133:33]
reg w_pprobeack; // @[MSHR.scala:134:33]
reg s_grantack; // @[MSHR.scala:136:33]
reg s_execute; // @[MSHR.scala:137:33]
reg w_grantack; // @[MSHR.scala:138:33]
reg s_writeback; // @[MSHR.scala:139:33]
reg [2:0] sink; // @[MSHR.scala:147:17]
assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17]
reg gotT; // @[MSHR.scala:148:17]
reg bad_grant; // @[MSHR.scala:149:22]
assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22]
reg probes_done; // @[MSHR.scala:150:24]
reg probes_toN; // @[MSHR.scala:151:23]
reg probes_noT; // @[MSHR.scala:152:23]
wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28]
wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45]
wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62]
wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}]
wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82]
wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}]
wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103]
wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}]
assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}]
assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40]
wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39]
wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}]
wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}]
wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96]
assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}]
assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93]
assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28]
assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28]
wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43]
wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64]
wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}]
wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85]
wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}]
assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}]
assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39]
wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33]
wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}]
wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}]
assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}]
assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83]
wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31]
wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}]
assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}]
assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55]
wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31]
wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44]
assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}]
assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41]
wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32]
wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}]
assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}]
assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64]
wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31]
wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}]
assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}]
assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57]
wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31]
assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}]
assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43]
wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31]
assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}]
assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40]
wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34]
wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}]
wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70]
wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}]
assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}]
assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66]
wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49]
wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}]
wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}]
wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49]
wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}]
assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}]
assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105]
wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71]
wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71]
wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71]
wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71]
wire final_meta_writeback_hit; // @[MSHR.scala:215:38]
wire req_clientBit = request_source == 6'h21; // @[Parameters.scala:46:9]
wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12]
wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12]
wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _req_needT_T_2; // @[Parameters.scala:270:13]
assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13]
wire _excluded_client_T_6; // @[Parameters.scala:279:117]
assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117]
wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42]
wire _req_needT_T_3; // @[Parameters.scala:270:42]
assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42]
wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11]
assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11]
wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42]
wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _req_needT_T_6; // @[Parameters.scala:271:14]
assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14]
wire _req_acquire_T; // @[MSHR.scala:219:36]
assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14]
wire _excluded_client_T_1; // @[Parameters.scala:279:12]
assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12]
wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52]
wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89]
wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52]
wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}]
wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}]
wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81]
wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}]
wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}]
wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}]
wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65]
wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}]
wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55]
wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78]
wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78]
assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78]
wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70]
wire _evict_T_2; // @[MSHR.scala:317:26]
assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _before_T_1; // @[MSHR.scala:317:26]
assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}]
wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}]
wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43]
assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43]
wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75]
wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}]
wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9]
wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}]
wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}]
wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54]
wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}]
wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45]
wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}]
wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}]
wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40]
wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40]
assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40]
wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65]
assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65]
wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41]
wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}]
wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72]
wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}]
wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70]
wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70]
wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53]
assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53]
wire _evict_T_1; // @[MSHR.scala:317:26]
assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire _before_T; // @[MSHR.scala:317:26]
assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70]
wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70]
wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55]
wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70]
wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70]
wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66]
wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}]
wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}]
wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9]
wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40]
assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30]
wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54]
wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}]
assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21]
assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21]
assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36]
assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36]
wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9]
wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}]
wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}]
wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38]
wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}]
wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}]
wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}]
wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106]
wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:46:9]
wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56]
wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70]
assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}]
wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51]
wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55]
wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52]
wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}]
wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}]
assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38]
assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91]
wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42]
wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70]
wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}]
assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}]
assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41]
wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42]
assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}]
assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41]
wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53]
assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}]
assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51]
assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41]
assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41]
assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}]
assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41]
wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42]
wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53]
wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53]
wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89]
wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79]
assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41]
wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42]
assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}]
assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41]
wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32]
wire [3:0] evict; // @[MSHR.scala:314:26]
wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32]
wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32]
wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32]
assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32]
assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39]
wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39]
assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39]
assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76]
wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76]
assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76]
assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32]
assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] before_0; // @[MSHR.scala:314:26]
wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32]
wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11]
assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] after; // @[MSHR.scala:314:26]
wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26]
wire _after_T; // @[MSHR.scala:317:26]
assign _after_T = _GEN_9; // @[MSHR.scala:317:26]
wire _prior_T; // @[MSHR.scala:317:26]
assign _prior_T = _GEN_9; // @[MSHR.scala:317:26]
wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32]
wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26]
wire _after_T_1; // @[MSHR.scala:317:26]
assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire _prior_T_1; // @[MSHR.scala:317:26]
assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32]
wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32]
assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32]
assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39]
wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39]
assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39]
assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76]
wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76]
assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76]
assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26]
wire _after_T_3; // @[MSHR.scala:317:26]
assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26]
wire _prior_T_3; // @[MSHR.scala:317:26]
assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26]
assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire probe_bit = io_sinkc_bits_source_0 == 6'h21; // @[Parameters.scala:46:9]
wire _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:46:9]
wire _last_probe_T; // @[MSHR.scala:459:33]
assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33]
wire _probes_done_T; // @[MSHR.scala:467:32]
assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32]
wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66]
wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}]
wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}]
wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11]
wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43]
wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75]
wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}]
wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9]
wire _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}]
wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53]
wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}]
wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42]
wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55]
wire _w_rprobeacklast_T; // @[MSHR.scala:471:55]
assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55]
wire _w_pprobeacklast_T; // @[MSHR.scala:473:55]
assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55]
wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}]
wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42]
wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}]
wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77]
wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}]
wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}]
wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32]
wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33]
wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}]
wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35]
wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40]
wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12]
wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _new_needT_T_2; // @[Parameters.scala:270:13]
assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13]
wire _new_skipProbe_T_5; // @[Parameters.scala:279:117]
assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117]
wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42]
wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _new_needT_T_6; // @[Parameters.scala:271:14]
assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14]
wire _new_skipProbe_T; // @[Parameters.scala:279:12]
assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12]
wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52]
wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89]
wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire new_clientBit = new_request_source == 6'h21; // @[Parameters.scala:46:9]
wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}]
wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}]
wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}]
wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9]
wire [3:0] prior; // @[MSHR.scala:314:26]
wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32]
wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28] |
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_preMul_e8_s24_41 :
output io : { flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, mulAddA : UInt<24>, mulAddB : UInt<24>, mulAddC : UInt<48>, toPostMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}}
node rawA_exp = bits(io.a, 31, 23)
node _rawA_isZero_T = bits(rawA_exp, 8, 6)
node rawA_isZero = eq(_rawA_isZero_T, UInt<1>(0h0))
node _rawA_isSpecial_T = bits(rawA_exp, 8, 7)
node rawA_isSpecial = eq(_rawA_isSpecial_T, UInt<2>(0h3))
wire rawA : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawA_out_isNaN_T = bits(rawA_exp, 6, 6)
node _rawA_out_isNaN_T_1 = and(rawA_isSpecial, _rawA_out_isNaN_T)
connect rawA.isNaN, _rawA_out_isNaN_T_1
node _rawA_out_isInf_T = bits(rawA_exp, 6, 6)
node _rawA_out_isInf_T_1 = eq(_rawA_out_isInf_T, UInt<1>(0h0))
node _rawA_out_isInf_T_2 = and(rawA_isSpecial, _rawA_out_isInf_T_1)
connect rawA.isInf, _rawA_out_isInf_T_2
connect rawA.isZero, rawA_isZero
node _rawA_out_sign_T = bits(io.a, 32, 32)
connect rawA.sign, _rawA_out_sign_T
node _rawA_out_sExp_T = cvt(rawA_exp)
connect rawA.sExp, _rawA_out_sExp_T
node _rawA_out_sig_T = eq(rawA_isZero, UInt<1>(0h0))
node _rawA_out_sig_T_1 = cat(UInt<1>(0h0), _rawA_out_sig_T)
node _rawA_out_sig_T_2 = bits(io.a, 22, 0)
node _rawA_out_sig_T_3 = cat(_rawA_out_sig_T_1, _rawA_out_sig_T_2)
connect rawA.sig, _rawA_out_sig_T_3
node rawB_exp = bits(io.b, 31, 23)
node _rawB_isZero_T = bits(rawB_exp, 8, 6)
node rawB_isZero = eq(_rawB_isZero_T, UInt<1>(0h0))
node _rawB_isSpecial_T = bits(rawB_exp, 8, 7)
node rawB_isSpecial = eq(_rawB_isSpecial_T, UInt<2>(0h3))
wire rawB : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawB_out_isNaN_T = bits(rawB_exp, 6, 6)
node _rawB_out_isNaN_T_1 = and(rawB_isSpecial, _rawB_out_isNaN_T)
connect rawB.isNaN, _rawB_out_isNaN_T_1
node _rawB_out_isInf_T = bits(rawB_exp, 6, 6)
node _rawB_out_isInf_T_1 = eq(_rawB_out_isInf_T, UInt<1>(0h0))
node _rawB_out_isInf_T_2 = and(rawB_isSpecial, _rawB_out_isInf_T_1)
connect rawB.isInf, _rawB_out_isInf_T_2
connect rawB.isZero, rawB_isZero
node _rawB_out_sign_T = bits(io.b, 32, 32)
connect rawB.sign, _rawB_out_sign_T
node _rawB_out_sExp_T = cvt(rawB_exp)
connect rawB.sExp, _rawB_out_sExp_T
node _rawB_out_sig_T = eq(rawB_isZero, UInt<1>(0h0))
node _rawB_out_sig_T_1 = cat(UInt<1>(0h0), _rawB_out_sig_T)
node _rawB_out_sig_T_2 = bits(io.b, 22, 0)
node _rawB_out_sig_T_3 = cat(_rawB_out_sig_T_1, _rawB_out_sig_T_2)
connect rawB.sig, _rawB_out_sig_T_3
node rawC_exp = bits(io.c, 31, 23)
node _rawC_isZero_T = bits(rawC_exp, 8, 6)
node rawC_isZero = eq(_rawC_isZero_T, UInt<1>(0h0))
node _rawC_isSpecial_T = bits(rawC_exp, 8, 7)
node rawC_isSpecial = eq(_rawC_isSpecial_T, UInt<2>(0h3))
wire rawC : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawC_out_isNaN_T = bits(rawC_exp, 6, 6)
node _rawC_out_isNaN_T_1 = and(rawC_isSpecial, _rawC_out_isNaN_T)
connect rawC.isNaN, _rawC_out_isNaN_T_1
node _rawC_out_isInf_T = bits(rawC_exp, 6, 6)
node _rawC_out_isInf_T_1 = eq(_rawC_out_isInf_T, UInt<1>(0h0))
node _rawC_out_isInf_T_2 = and(rawC_isSpecial, _rawC_out_isInf_T_1)
connect rawC.isInf, _rawC_out_isInf_T_2
connect rawC.isZero, rawC_isZero
node _rawC_out_sign_T = bits(io.c, 32, 32)
connect rawC.sign, _rawC_out_sign_T
node _rawC_out_sExp_T = cvt(rawC_exp)
connect rawC.sExp, _rawC_out_sExp_T
node _rawC_out_sig_T = eq(rawC_isZero, UInt<1>(0h0))
node _rawC_out_sig_T_1 = cat(UInt<1>(0h0), _rawC_out_sig_T)
node _rawC_out_sig_T_2 = bits(io.c, 22, 0)
node _rawC_out_sig_T_3 = cat(_rawC_out_sig_T_1, _rawC_out_sig_T_2)
connect rawC.sig, _rawC_out_sig_T_3
node _signProd_T = xor(rawA.sign, rawB.sign)
node _signProd_T_1 = bits(io.op, 1, 1)
node signProd = xor(_signProd_T, _signProd_T_1)
node _sExpAlignedProd_T = add(rawA.sExp, rawB.sExp)
node _sExpAlignedProd_T_1 = add(_sExpAlignedProd_T, asSInt(UInt<9>(0h11b)))
node _sExpAlignedProd_T_2 = tail(_sExpAlignedProd_T_1, 1)
node sExpAlignedProd = asSInt(_sExpAlignedProd_T_2)
node _doSubMags_T = xor(signProd, rawC.sign)
node _doSubMags_T_1 = bits(io.op, 0, 0)
node doSubMags = xor(_doSubMags_T, _doSubMags_T_1)
node _sNatCAlignDist_T = sub(sExpAlignedProd, rawC.sExp)
node _sNatCAlignDist_T_1 = tail(_sNatCAlignDist_T, 1)
node sNatCAlignDist = asSInt(_sNatCAlignDist_T_1)
node posNatCAlignDist = bits(sNatCAlignDist, 9, 0)
node _isMinCAlign_T = or(rawA.isZero, rawB.isZero)
node _isMinCAlign_T_1 = lt(sNatCAlignDist, asSInt(UInt<1>(0h0)))
node isMinCAlign = or(_isMinCAlign_T, _isMinCAlign_T_1)
node _CIsDominant_T = eq(rawC.isZero, UInt<1>(0h0))
node _CIsDominant_T_1 = leq(posNatCAlignDist, UInt<5>(0h18))
node _CIsDominant_T_2 = or(isMinCAlign, _CIsDominant_T_1)
node CIsDominant = and(_CIsDominant_T, _CIsDominant_T_2)
node _CAlignDist_T = lt(posNatCAlignDist, UInt<7>(0h4a))
node _CAlignDist_T_1 = bits(posNatCAlignDist, 6, 0)
node _CAlignDist_T_2 = mux(_CAlignDist_T, _CAlignDist_T_1, UInt<7>(0h4a))
node CAlignDist = mux(isMinCAlign, UInt<1>(0h0), _CAlignDist_T_2)
node _mainAlignedSigC_T = not(rawC.sig)
node _mainAlignedSigC_T_1 = mux(doSubMags, _mainAlignedSigC_T, rawC.sig)
node _mainAlignedSigC_T_2 = mux(doSubMags, UInt<53>(0h1fffffffffffff), UInt<53>(0h0))
node _mainAlignedSigC_T_3 = cat(_mainAlignedSigC_T_1, _mainAlignedSigC_T_2)
node _mainAlignedSigC_T_4 = asSInt(_mainAlignedSigC_T_3)
node mainAlignedSigC = dshr(_mainAlignedSigC_T_4, CAlignDist)
node _reduced4CExtra_T = shl(rawC.sig, 2)
wire reduced4CExtra_reducedVec : UInt<1>[7]
node _reduced4CExtra_reducedVec_0_T = bits(_reduced4CExtra_T, 3, 0)
node _reduced4CExtra_reducedVec_0_T_1 = orr(_reduced4CExtra_reducedVec_0_T)
connect reduced4CExtra_reducedVec[0], _reduced4CExtra_reducedVec_0_T_1
node _reduced4CExtra_reducedVec_1_T = bits(_reduced4CExtra_T, 7, 4)
node _reduced4CExtra_reducedVec_1_T_1 = orr(_reduced4CExtra_reducedVec_1_T)
connect reduced4CExtra_reducedVec[1], _reduced4CExtra_reducedVec_1_T_1
node _reduced4CExtra_reducedVec_2_T = bits(_reduced4CExtra_T, 11, 8)
node _reduced4CExtra_reducedVec_2_T_1 = orr(_reduced4CExtra_reducedVec_2_T)
connect reduced4CExtra_reducedVec[2], _reduced4CExtra_reducedVec_2_T_1
node _reduced4CExtra_reducedVec_3_T = bits(_reduced4CExtra_T, 15, 12)
node _reduced4CExtra_reducedVec_3_T_1 = orr(_reduced4CExtra_reducedVec_3_T)
connect reduced4CExtra_reducedVec[3], _reduced4CExtra_reducedVec_3_T_1
node _reduced4CExtra_reducedVec_4_T = bits(_reduced4CExtra_T, 19, 16)
node _reduced4CExtra_reducedVec_4_T_1 = orr(_reduced4CExtra_reducedVec_4_T)
connect reduced4CExtra_reducedVec[4], _reduced4CExtra_reducedVec_4_T_1
node _reduced4CExtra_reducedVec_5_T = bits(_reduced4CExtra_T, 23, 20)
node _reduced4CExtra_reducedVec_5_T_1 = orr(_reduced4CExtra_reducedVec_5_T)
connect reduced4CExtra_reducedVec[5], _reduced4CExtra_reducedVec_5_T_1
node _reduced4CExtra_reducedVec_6_T = bits(_reduced4CExtra_T, 26, 24)
node _reduced4CExtra_reducedVec_6_T_1 = orr(_reduced4CExtra_reducedVec_6_T)
connect reduced4CExtra_reducedVec[6], _reduced4CExtra_reducedVec_6_T_1
node reduced4CExtra_lo_hi = cat(reduced4CExtra_reducedVec[2], reduced4CExtra_reducedVec[1])
node reduced4CExtra_lo = cat(reduced4CExtra_lo_hi, reduced4CExtra_reducedVec[0])
node reduced4CExtra_hi_lo = cat(reduced4CExtra_reducedVec[4], reduced4CExtra_reducedVec[3])
node reduced4CExtra_hi_hi = cat(reduced4CExtra_reducedVec[6], reduced4CExtra_reducedVec[5])
node reduced4CExtra_hi = cat(reduced4CExtra_hi_hi, reduced4CExtra_hi_lo)
node _reduced4CExtra_T_1 = cat(reduced4CExtra_hi, reduced4CExtra_lo)
node _reduced4CExtra_T_2 = shr(CAlignDist, 2)
node reduced4CExtra_shift = dshr(asSInt(UInt<33>(0h100000000)), _reduced4CExtra_T_2)
node _reduced4CExtra_T_3 = bits(reduced4CExtra_shift, 19, 14)
node _reduced4CExtra_T_4 = bits(_reduced4CExtra_T_3, 3, 0)
node _reduced4CExtra_T_5 = bits(_reduced4CExtra_T_4, 1, 0)
node _reduced4CExtra_T_6 = bits(_reduced4CExtra_T_5, 0, 0)
node _reduced4CExtra_T_7 = bits(_reduced4CExtra_T_5, 1, 1)
node _reduced4CExtra_T_8 = cat(_reduced4CExtra_T_6, _reduced4CExtra_T_7)
node _reduced4CExtra_T_9 = bits(_reduced4CExtra_T_4, 3, 2)
node _reduced4CExtra_T_10 = bits(_reduced4CExtra_T_9, 0, 0)
node _reduced4CExtra_T_11 = bits(_reduced4CExtra_T_9, 1, 1)
node _reduced4CExtra_T_12 = cat(_reduced4CExtra_T_10, _reduced4CExtra_T_11)
node _reduced4CExtra_T_13 = cat(_reduced4CExtra_T_8, _reduced4CExtra_T_12)
node _reduced4CExtra_T_14 = bits(_reduced4CExtra_T_3, 5, 4)
node _reduced4CExtra_T_15 = bits(_reduced4CExtra_T_14, 0, 0)
node _reduced4CExtra_T_16 = bits(_reduced4CExtra_T_14, 1, 1)
node _reduced4CExtra_T_17 = cat(_reduced4CExtra_T_15, _reduced4CExtra_T_16)
node _reduced4CExtra_T_18 = cat(_reduced4CExtra_T_13, _reduced4CExtra_T_17)
node _reduced4CExtra_T_19 = and(_reduced4CExtra_T_1, _reduced4CExtra_T_18)
node reduced4CExtra = orr(_reduced4CExtra_T_19)
node _alignedSigC_T = shr(mainAlignedSigC, 3)
node _alignedSigC_T_1 = bits(mainAlignedSigC, 2, 0)
node _alignedSigC_T_2 = andr(_alignedSigC_T_1)
node _alignedSigC_T_3 = eq(reduced4CExtra, UInt<1>(0h0))
node _alignedSigC_T_4 = and(_alignedSigC_T_2, _alignedSigC_T_3)
node _alignedSigC_T_5 = bits(mainAlignedSigC, 2, 0)
node _alignedSigC_T_6 = orr(_alignedSigC_T_5)
node _alignedSigC_T_7 = or(_alignedSigC_T_6, reduced4CExtra)
node _alignedSigC_T_8 = mux(doSubMags, _alignedSigC_T_4, _alignedSigC_T_7)
node alignedSigC_hi = asUInt(_alignedSigC_T)
node alignedSigC = cat(alignedSigC_hi, _alignedSigC_T_8)
connect io.mulAddA, rawA.sig
connect io.mulAddB, rawB.sig
node _io_mulAddC_T = bits(alignedSigC, 48, 1)
connect io.mulAddC, _io_mulAddC_T
node _io_toPostMul_isSigNaNAny_T = bits(rawA.sig, 22, 22)
node _io_toPostMul_isSigNaNAny_T_1 = eq(_io_toPostMul_isSigNaNAny_T, UInt<1>(0h0))
node _io_toPostMul_isSigNaNAny_T_2 = and(rawA.isNaN, _io_toPostMul_isSigNaNAny_T_1)
node _io_toPostMul_isSigNaNAny_T_3 = bits(rawB.sig, 22, 22)
node _io_toPostMul_isSigNaNAny_T_4 = eq(_io_toPostMul_isSigNaNAny_T_3, UInt<1>(0h0))
node _io_toPostMul_isSigNaNAny_T_5 = and(rawB.isNaN, _io_toPostMul_isSigNaNAny_T_4)
node _io_toPostMul_isSigNaNAny_T_6 = or(_io_toPostMul_isSigNaNAny_T_2, _io_toPostMul_isSigNaNAny_T_5)
node _io_toPostMul_isSigNaNAny_T_7 = bits(rawC.sig, 22, 22)
node _io_toPostMul_isSigNaNAny_T_8 = eq(_io_toPostMul_isSigNaNAny_T_7, UInt<1>(0h0))
node _io_toPostMul_isSigNaNAny_T_9 = and(rawC.isNaN, _io_toPostMul_isSigNaNAny_T_8)
node _io_toPostMul_isSigNaNAny_T_10 = or(_io_toPostMul_isSigNaNAny_T_6, _io_toPostMul_isSigNaNAny_T_9)
connect io.toPostMul.isSigNaNAny, _io_toPostMul_isSigNaNAny_T_10
node _io_toPostMul_isNaNAOrB_T = or(rawA.isNaN, rawB.isNaN)
connect io.toPostMul.isNaNAOrB, _io_toPostMul_isNaNAOrB_T
connect io.toPostMul.isInfA, rawA.isInf
connect io.toPostMul.isZeroA, rawA.isZero
connect io.toPostMul.isInfB, rawB.isInf
connect io.toPostMul.isZeroB, rawB.isZero
connect io.toPostMul.signProd, signProd
connect io.toPostMul.isNaNC, rawC.isNaN
connect io.toPostMul.isInfC, rawC.isInf
connect io.toPostMul.isZeroC, rawC.isZero
node _io_toPostMul_sExpSum_T = sub(sExpAlignedProd, asSInt(UInt<6>(0h18)))
node _io_toPostMul_sExpSum_T_1 = tail(_io_toPostMul_sExpSum_T, 1)
node _io_toPostMul_sExpSum_T_2 = asSInt(_io_toPostMul_sExpSum_T_1)
node _io_toPostMul_sExpSum_T_3 = mux(CIsDominant, rawC.sExp, _io_toPostMul_sExpSum_T_2)
connect io.toPostMul.sExpSum, _io_toPostMul_sExpSum_T_3
connect io.toPostMul.doSubMags, doSubMags
connect io.toPostMul.CIsDominant, CIsDominant
node _io_toPostMul_CDom_CAlignDist_T = bits(CAlignDist, 4, 0)
connect io.toPostMul.CDom_CAlignDist, _io_toPostMul_CDom_CAlignDist_T
node _io_toPostMul_highAlignedSigC_T = bits(alignedSigC, 74, 49)
connect io.toPostMul.highAlignedSigC, _io_toPostMul_highAlignedSigC_T
node _io_toPostMul_bit0AlignedSigC_T = bits(alignedSigC, 0, 0)
connect io.toPostMul.bit0AlignedSigC, _io_toPostMul_bit0AlignedSigC_T | module MulAddRecFNToRaw_preMul_e8_s24_41( // @[MulAddRecFN.scala:71:7]
input [32:0] io_a, // @[MulAddRecFN.scala:74:16]
input [32:0] io_b, // @[MulAddRecFN.scala:74:16]
input [32:0] io_c, // @[MulAddRecFN.scala:74:16]
output [23:0] io_mulAddA, // @[MulAddRecFN.scala:74:16]
output [23:0] io_mulAddB, // @[MulAddRecFN.scala:74:16]
output [47:0] io_mulAddC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isNaNAOrB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfA, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroA, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_signProd, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isNaNC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroC, // @[MulAddRecFN.scala:74:16]
output [9:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_CIsDominant, // @[MulAddRecFN.scala:74:16]
output [4:0] io_toPostMul_CDom_CAlignDist, // @[MulAddRecFN.scala:74:16]
output [25:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16]
);
wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:71:7]
wire [32:0] io_b_0 = io_b; // @[MulAddRecFN.scala:71:7]
wire [32:0] io_c_0 = io_c; // @[MulAddRecFN.scala:71:7]
wire _signProd_T_1 = 1'h0; // @[MulAddRecFN.scala:97:49]
wire _doSubMags_T_1 = 1'h0; // @[MulAddRecFN.scala:102:49]
wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:71:7, :74:16]
wire [47:0] _io_mulAddC_T; // @[MulAddRecFN.scala:143:30]
wire _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:146:58]
wire _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:148:42]
wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawA_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire signProd; // @[MulAddRecFN.scala:97:42]
wire rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawC_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire doSubMags; // @[MulAddRecFN.scala:102:42]
wire CIsDominant; // @[MulAddRecFN.scala:110:23]
wire [4:0] _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:161:47]
wire [25:0] _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:163:20]
wire _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:164:48]
wire io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7]
wire [9:0] io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7]
wire [4:0] io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7]
wire [25:0] io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7]
wire [23:0] io_mulAddA_0; // @[MulAddRecFN.scala:71:7]
wire [23:0] io_mulAddB_0; // @[MulAddRecFN.scala:71:7]
wire [47:0] io_mulAddC_0; // @[MulAddRecFN.scala:71:7]
wire [8:0] rawA_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawA_isZero_T = rawA_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawA_isZero_0 = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawA_isZero = rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawA_isSpecial_T = rawA_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign io_toPostMul_isInfA_0 = rawA_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroA_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawA_out_isNaN_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawA_out_isInf_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawA_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawA_out_sig_T = ~rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawA_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [8:0] rawB_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawB_isZero_T = rawB_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawB_isZero_0 = _rawB_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawB_isZero = rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawB_isSpecial_T = rawB_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawB_isSpecial = &_rawB_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign io_toPostMul_isInfB_0 = rawB_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroB_0 = rawB_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawB_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawB_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawB_out_isNaN_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawB_out_isInf_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawB_out_isNaN_T_1 = rawB_isSpecial & _rawB_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawB_isNaN = _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawB_out_isInf_T_1 = ~_rawB_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawB_out_isInf_T_2 = rawB_isSpecial & _rawB_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawB_isInf = _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawB_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawB_sign = _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawB_out_sExp_T = {1'h0, rawB_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawB_sExp = _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawB_out_sig_T = ~rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawB_out_sig_T_1 = {1'h0, _rawB_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawB_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawB_out_sig_T_3 = {_rawB_out_sig_T_1, _rawB_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawB_sig = _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [8:0] rawC_exp = io_c_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawC_isZero_T = rawC_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawC_isZero_0 = _rawC_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawC_isZero = rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawC_isSpecial_T = rawC_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawC_isSpecial = &_rawC_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
assign io_toPostMul_isNaNC_0 = rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign io_toPostMul_isInfC_0 = rawC_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroC_0 = rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawC_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawC_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_isNaN_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawC_out_isInf_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawC_out_isNaN_T_1 = rawC_isSpecial & _rawC_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawC_isNaN = _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawC_out_isInf_T_1 = ~_rawC_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawC_out_isInf_T_2 = rawC_isSpecial & _rawC_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawC_isInf = _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawC_out_sign_T = io_c_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawC_sign = _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawC_out_sExp_T = {1'h0, rawC_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawC_sExp = _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawC_out_sig_T = ~rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawC_out_sig_T_1 = {1'h0, _rawC_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawC_out_sig_T_2 = io_c_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawC_out_sig_T_3 = {_rawC_out_sig_T_1, _rawC_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawC_sig = _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire _signProd_T = rawA_sign ^ rawB_sign; // @[rawFloatFromRecFN.scala:55:23]
assign signProd = _signProd_T; // @[MulAddRecFN.scala:97:{30,42}]
assign io_toPostMul_signProd_0 = signProd; // @[MulAddRecFN.scala:71:7, :97:42]
wire [10:0] _sExpAlignedProd_T = {rawA_sExp[9], rawA_sExp} + {rawB_sExp[9], rawB_sExp}; // @[rawFloatFromRecFN.scala:55:23]
wire [11:0] _sExpAlignedProd_T_1 = {_sExpAlignedProd_T[10], _sExpAlignedProd_T} - 12'hE5; // @[MulAddRecFN.scala:100:{19,32}]
wire [10:0] _sExpAlignedProd_T_2 = _sExpAlignedProd_T_1[10:0]; // @[MulAddRecFN.scala:100:32]
wire [10:0] sExpAlignedProd = _sExpAlignedProd_T_2; // @[MulAddRecFN.scala:100:32]
wire _doSubMags_T = signProd ^ rawC_sign; // @[rawFloatFromRecFN.scala:55:23]
assign doSubMags = _doSubMags_T; // @[MulAddRecFN.scala:102:{30,42}]
assign io_toPostMul_doSubMags_0 = doSubMags; // @[MulAddRecFN.scala:71:7, :102:42]
wire [11:0] _GEN = {sExpAlignedProd[10], sExpAlignedProd}; // @[MulAddRecFN.scala:100:32, :106:42]
wire [11:0] _sNatCAlignDist_T = _GEN - {{2{rawC_sExp[9]}}, rawC_sExp}; // @[rawFloatFromRecFN.scala:55:23]
wire [10:0] _sNatCAlignDist_T_1 = _sNatCAlignDist_T[10:0]; // @[MulAddRecFN.scala:106:42]
wire [10:0] sNatCAlignDist = _sNatCAlignDist_T_1; // @[MulAddRecFN.scala:106:42]
wire [9:0] posNatCAlignDist = sNatCAlignDist[9:0]; // @[MulAddRecFN.scala:106:42, :107:42]
wire _isMinCAlign_T = rawA_isZero | rawB_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _isMinCAlign_T_1 = $signed(sNatCAlignDist) < 11'sh0; // @[MulAddRecFN.scala:106:42, :108:69]
wire isMinCAlign = _isMinCAlign_T | _isMinCAlign_T_1; // @[MulAddRecFN.scala:108:{35,50,69}]
wire _CIsDominant_T = ~rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _CIsDominant_T_1 = posNatCAlignDist < 10'h19; // @[MulAddRecFN.scala:107:42, :110:60]
wire _CIsDominant_T_2 = isMinCAlign | _CIsDominant_T_1; // @[MulAddRecFN.scala:108:50, :110:{39,60}]
assign CIsDominant = _CIsDominant_T & _CIsDominant_T_2; // @[MulAddRecFN.scala:110:{9,23,39}]
assign io_toPostMul_CIsDominant_0 = CIsDominant; // @[MulAddRecFN.scala:71:7, :110:23]
wire _CAlignDist_T = posNatCAlignDist < 10'h4A; // @[MulAddRecFN.scala:107:42, :114:34]
wire [6:0] _CAlignDist_T_1 = posNatCAlignDist[6:0]; // @[MulAddRecFN.scala:107:42, :115:33]
wire [6:0] _CAlignDist_T_2 = _CAlignDist_T ? _CAlignDist_T_1 : 7'h4A; // @[MulAddRecFN.scala:114:{16,34}, :115:33]
wire [6:0] CAlignDist = isMinCAlign ? 7'h0 : _CAlignDist_T_2; // @[MulAddRecFN.scala:108:50, :112:12, :114:16]
wire [24:0] _mainAlignedSigC_T = ~rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] _mainAlignedSigC_T_1 = doSubMags ? _mainAlignedSigC_T : rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire [52:0] _mainAlignedSigC_T_2 = {53{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:53]
wire [77:0] _mainAlignedSigC_T_3 = {_mainAlignedSigC_T_1, _mainAlignedSigC_T_2}; // @[MulAddRecFN.scala:120:{13,46,53}]
wire [77:0] _mainAlignedSigC_T_4 = _mainAlignedSigC_T_3; // @[MulAddRecFN.scala:120:{46,94}]
wire [77:0] mainAlignedSigC = $signed($signed(_mainAlignedSigC_T_4) >>> CAlignDist); // @[MulAddRecFN.scala:112:12, :120:{94,100}]
wire [26:0] _reduced4CExtra_T = {rawC_sig, 2'h0}; // @[rawFloatFromRecFN.scala:55:23]
wire _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:123:57]
wire reduced4CExtra_reducedVec_0; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_1; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_2; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_3; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_4; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_5; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_6; // @[primitives.scala:118:30]
wire [3:0] _reduced4CExtra_reducedVec_0_T = _reduced4CExtra_T[3:0]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_0_T_1 = |_reduced4CExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_0 = _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_1_T = _reduced4CExtra_T[7:4]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_1_T_1 = |_reduced4CExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_1 = _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_2_T = _reduced4CExtra_T[11:8]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_2_T_1 = |_reduced4CExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_2 = _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_3_T = _reduced4CExtra_T[15:12]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_3_T_1 = |_reduced4CExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_3 = _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_4_T = _reduced4CExtra_T[19:16]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_4_T_1 = |_reduced4CExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_4 = _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_5_T = _reduced4CExtra_T[23:20]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_5_T_1 = |_reduced4CExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_5 = _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54]
wire [2:0] _reduced4CExtra_reducedVec_6_T = _reduced4CExtra_T[26:24]; // @[primitives.scala:123:15]
assign _reduced4CExtra_reducedVec_6_T_1 = |_reduced4CExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}]
assign reduced4CExtra_reducedVec_6 = _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57]
wire [1:0] reduced4CExtra_lo_hi = {reduced4CExtra_reducedVec_2, reduced4CExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20]
wire [2:0] reduced4CExtra_lo = {reduced4CExtra_lo_hi, reduced4CExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20]
wire [1:0] reduced4CExtra_hi_lo = {reduced4CExtra_reducedVec_4, reduced4CExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20]
wire [1:0] reduced4CExtra_hi_hi = {reduced4CExtra_reducedVec_6, reduced4CExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20]
wire [3:0] reduced4CExtra_hi = {reduced4CExtra_hi_hi, reduced4CExtra_hi_lo}; // @[primitives.scala:124:20]
wire [6:0] _reduced4CExtra_T_1 = {reduced4CExtra_hi, reduced4CExtra_lo}; // @[primitives.scala:124:20]
wire [4:0] _reduced4CExtra_T_2 = CAlignDist[6:2]; // @[MulAddRecFN.scala:112:12, :124:28]
wire [32:0] reduced4CExtra_shift = $signed(33'sh100000000 >>> _reduced4CExtra_T_2); // @[primitives.scala:76:56]
wire [5:0] _reduced4CExtra_T_3 = reduced4CExtra_shift[19:14]; // @[primitives.scala:76:56, :78:22]
wire [3:0] _reduced4CExtra_T_4 = _reduced4CExtra_T_3[3:0]; // @[primitives.scala:77:20, :78:22]
wire [1:0] _reduced4CExtra_T_5 = _reduced4CExtra_T_4[1:0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_6 = _reduced4CExtra_T_5[0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_7 = _reduced4CExtra_T_5[1]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_8 = {_reduced4CExtra_T_6, _reduced4CExtra_T_7}; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_9 = _reduced4CExtra_T_4[3:2]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_10 = _reduced4CExtra_T_9[0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_11 = _reduced4CExtra_T_9[1]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_12 = {_reduced4CExtra_T_10, _reduced4CExtra_T_11}; // @[primitives.scala:77:20]
wire [3:0] _reduced4CExtra_T_13 = {_reduced4CExtra_T_8, _reduced4CExtra_T_12}; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_14 = _reduced4CExtra_T_3[5:4]; // @[primitives.scala:77:20, :78:22]
wire _reduced4CExtra_T_15 = _reduced4CExtra_T_14[0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_16 = _reduced4CExtra_T_14[1]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_17 = {_reduced4CExtra_T_15, _reduced4CExtra_T_16}; // @[primitives.scala:77:20]
wire [5:0] _reduced4CExtra_T_18 = {_reduced4CExtra_T_13, _reduced4CExtra_T_17}; // @[primitives.scala:77:20]
wire [6:0] _reduced4CExtra_T_19 = {1'h0, _reduced4CExtra_T_1[5:0] & _reduced4CExtra_T_18}; // @[primitives.scala:77:20, :124:20]
wire reduced4CExtra = |_reduced4CExtra_T_19; // @[MulAddRecFN.scala:122:68, :130:11]
wire [74:0] _alignedSigC_T = mainAlignedSigC[77:3]; // @[MulAddRecFN.scala:120:100, :132:28]
wire [74:0] alignedSigC_hi = _alignedSigC_T; // @[MulAddRecFN.scala:132:{12,28}]
wire [2:0] _alignedSigC_T_1 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32]
wire [2:0] _alignedSigC_T_5 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32, :135:32]
wire _alignedSigC_T_2 = &_alignedSigC_T_1; // @[MulAddRecFN.scala:134:{32,39}]
wire _alignedSigC_T_3 = ~reduced4CExtra; // @[MulAddRecFN.scala:130:11, :134:47]
wire _alignedSigC_T_4 = _alignedSigC_T_2 & _alignedSigC_T_3; // @[MulAddRecFN.scala:134:{39,44,47}]
wire _alignedSigC_T_6 = |_alignedSigC_T_5; // @[MulAddRecFN.scala:135:{32,39}]
wire _alignedSigC_T_7 = _alignedSigC_T_6 | reduced4CExtra; // @[MulAddRecFN.scala:130:11, :135:{39,44}]
wire _alignedSigC_T_8 = doSubMags ? _alignedSigC_T_4 : _alignedSigC_T_7; // @[MulAddRecFN.scala:102:42, :133:16, :134:44, :135:44]
wire [75:0] alignedSigC = {alignedSigC_hi, _alignedSigC_T_8}; // @[MulAddRecFN.scala:132:12, :133:16]
assign io_mulAddA_0 = rawA_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23]
assign io_mulAddB_0 = rawB_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23]
assign _io_mulAddC_T = alignedSigC[48:1]; // @[MulAddRecFN.scala:132:12, :143:30]
assign io_mulAddC_0 = _io_mulAddC_T; // @[MulAddRecFN.scala:71:7, :143:30]
wire _io_toPostMul_isSigNaNAny_T = rawA_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_1 = ~_io_toPostMul_isSigNaNAny_T; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_2 = rawA_isNaN & _io_toPostMul_isSigNaNAny_T_1; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_3 = rawB_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_4 = ~_io_toPostMul_isSigNaNAny_T_3; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_5 = rawB_isNaN & _io_toPostMul_isSigNaNAny_T_4; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_6 = _io_toPostMul_isSigNaNAny_T_2 | _io_toPostMul_isSigNaNAny_T_5; // @[common.scala:82:46]
wire _io_toPostMul_isSigNaNAny_T_7 = rawC_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_8 = ~_io_toPostMul_isSigNaNAny_T_7; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_9 = rawC_isNaN & _io_toPostMul_isSigNaNAny_T_8; // @[rawFloatFromRecFN.scala:55:23]
assign _io_toPostMul_isSigNaNAny_T_10 = _io_toPostMul_isSigNaNAny_T_6 | _io_toPostMul_isSigNaNAny_T_9; // @[common.scala:82:46]
assign io_toPostMul_isSigNaNAny_0 = _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:71:7, :146:58]
assign _io_toPostMul_isNaNAOrB_T = rawA_isNaN | rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isNaNAOrB_0 = _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:71:7, :148:42]
wire [11:0] _io_toPostMul_sExpSum_T = _GEN - 12'h18; // @[MulAddRecFN.scala:106:42, :158:53]
wire [10:0] _io_toPostMul_sExpSum_T_1 = _io_toPostMul_sExpSum_T[10:0]; // @[MulAddRecFN.scala:158:53]
wire [10:0] _io_toPostMul_sExpSum_T_2 = _io_toPostMul_sExpSum_T_1; // @[MulAddRecFN.scala:158:53]
wire [10:0] _io_toPostMul_sExpSum_T_3 = CIsDominant ? {rawC_sExp[9], rawC_sExp} : _io_toPostMul_sExpSum_T_2; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_sExpSum_0 = _io_toPostMul_sExpSum_T_3[9:0]; // @[MulAddRecFN.scala:71:7, :157:28, :158:12]
assign _io_toPostMul_CDom_CAlignDist_T = CAlignDist[4:0]; // @[MulAddRecFN.scala:112:12, :161:47]
assign io_toPostMul_CDom_CAlignDist_0 = _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:71:7, :161:47]
assign _io_toPostMul_highAlignedSigC_T = alignedSigC[74:49]; // @[MulAddRecFN.scala:132:12, :163:20]
assign io_toPostMul_highAlignedSigC_0 = _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:71:7, :163:20]
assign _io_toPostMul_bit0AlignedSigC_T = alignedSigC[0]; // @[MulAddRecFN.scala:132:12, :164:48]
assign io_toPostMul_bit0AlignedSigC_0 = _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:71:7, :164:48]
assign io_mulAddA = io_mulAddA_0; // @[MulAddRecFN.scala:71:7]
assign io_mulAddB = io_mulAddB_0; // @[MulAddRecFN.scala:71:7]
assign io_mulAddC = io_mulAddC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isSigNaNAny = io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isNaNAOrB = io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfA = io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroA = io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfB = io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroB = io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_signProd = io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isNaNC = io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfC = io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroC = io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_sExpSum = io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_doSubMags = io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_CIsDominant = io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_CDom_CAlignDist = io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_highAlignedSigC = io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_bit0AlignedSigC = io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_69 :
input clock : Clock
input reset : Reset
output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], credit_return : UInt<2>, vc_free : UInt<2>}}
wire _in_flight_WIRE : UInt<1>[2]
connect _in_flight_WIRE[0], UInt<1>(0h0)
connect _in_flight_WIRE[1], UInt<1>(0h0)
regreset in_flight : UInt<1>[2], clock, reset, _in_flight_WIRE
when io.in.flit[0].valid :
when io.in.flit[0].bits.head :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1)
node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
when io.in.flit[0].bits.tail :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)
node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T_4 :
node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0))
node _T_6 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_7 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_8 = and(_T_6, _T_7)
node _T_9 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_10 = and(_T_8, _T_9)
node _T_11 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_12 = and(_T_10, _T_11)
node _T_13 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_14 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_15 = and(_T_13, _T_14)
node _T_16 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_19 = and(_T_17, _T_18)
node _T_20 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_21 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_22 = and(_T_20, _T_21)
node _T_23 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_24 = and(_T_22, _T_23)
node _T_25 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_26 = and(_T_24, _T_25)
node _T_27 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_28 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_29 = and(_T_27, _T_28)
node _T_30 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_31 = and(_T_29, _T_30)
node _T_32 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_33 = and(_T_31, _T_32)
node _T_34 = or(_T_12, _T_19)
node _T_35 = or(_T_34, _T_26)
node _T_36 = or(_T_35, _T_33)
node _T_37 = or(_T_5, _T_36)
node _T_38 = asUInt(reset)
node _T_39 = eq(_T_38, UInt<1>(0h0))
when _T_39 :
node _T_40 = eq(_T_37, UInt<1>(0h0))
when _T_40 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1
assert(clock, _T_37, UInt<1>(0h1), "") : assert_1
node _T_41 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1))
node _T_42 = or(_T_41, UInt<1>(0h0))
node _T_43 = asUInt(reset)
node _T_44 = eq(_T_43, UInt<1>(0h0))
when _T_44 :
node _T_45 = eq(_T_42, UInt<1>(0h0))
when _T_45 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2
assert(clock, _T_42, UInt<1>(0h1), "") : assert_2 | module NoCMonitor_69( // @[Monitor.scala:11:7]
input clock, // @[Monitor.scala:11:7]
input reset, // @[Monitor.scala:11:7]
input io_in_flit_0_valid, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_head, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14]
input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14]
input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14]
);
reg in_flight_0; // @[Monitor.scala:16:26]
reg in_flight_1; // @[Monitor.scala:16:26] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_456 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_456( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_65 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h11))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE : UInt<1>[10]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_25
connect _source_ok_WIRE[6], _source_ok_T_26
connect _source_ok_WIRE[7], _source_ok_T_27
connect _source_ok_WIRE[8], _source_ok_T_28
connect _source_ok_WIRE[9], _source_ok_T_29
node _source_ok_T_30 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[2])
node _source_ok_T_32 = or(_source_ok_T_31, _source_ok_WIRE[3])
node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[4])
node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[5])
node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[6])
node _source_ok_T_36 = or(_source_ok_T_35, _source_ok_WIRE[7])
node _source_ok_T_37 = or(_source_ok_T_36, _source_ok_WIRE[8])
node source_ok = or(_source_ok_T_37, _source_ok_WIRE[9])
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h11))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<1>(0h1))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<2>(0h2))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<2>(0h3))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _T_64 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_67 = cvt(_T_66)
node _T_68 = and(_T_67, asSInt(UInt<1>(0h0)))
node _T_69 = asSInt(_T_68)
node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0)))
node _T_71 = or(_T_65, _T_70)
node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_73 = eq(_T_72, UInt<1>(0h0))
node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_75 = cvt(_T_74)
node _T_76 = and(_T_75, asSInt(UInt<1>(0h0)))
node _T_77 = asSInt(_T_76)
node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0)))
node _T_79 = or(_T_73, _T_78)
node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_81 = eq(_T_80, UInt<1>(0h0))
node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_83 = cvt(_T_82)
node _T_84 = and(_T_83, asSInt(UInt<1>(0h0)))
node _T_85 = asSInt(_T_84)
node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0)))
node _T_87 = or(_T_81, _T_86)
node _T_88 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_89 = eq(_T_88, UInt<1>(0h0))
node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_91 = cvt(_T_90)
node _T_92 = and(_T_91, asSInt(UInt<1>(0h0)))
node _T_93 = asSInt(_T_92)
node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = or(_T_89, _T_94)
node _T_96 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_97 = eq(_T_96, UInt<1>(0h0))
node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_99 = cvt(_T_98)
node _T_100 = and(_T_99, asSInt(UInt<1>(0h0)))
node _T_101 = asSInt(_T_100)
node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0)))
node _T_103 = or(_T_97, _T_102)
node _T_104 = and(_T_11, _T_24)
node _T_105 = and(_T_104, _T_37)
node _T_106 = and(_T_105, _T_50)
node _T_107 = and(_T_106, _T_63)
node _T_108 = and(_T_107, _T_71)
node _T_109 = and(_T_108, _T_79)
node _T_110 = and(_T_109, _T_87)
node _T_111 = and(_T_110, _T_95)
node _T_112 = and(_T_111, _T_103)
node _T_113 = asUInt(reset)
node _T_114 = eq(_T_113, UInt<1>(0h0))
when _T_114 :
node _T_115 = eq(_T_112, UInt<1>(0h0))
when _T_115 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_112, UInt<1>(0h1), "") : assert_1
node _T_116 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_116 :
node _T_117 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_118 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_119 = and(_T_117, _T_118)
node _T_120 = eq(io.in.a.bits.source, UInt<5>(0h11))
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0)
node _T_121 = shr(io.in.a.bits.source, 2)
node _T_122 = eq(_T_121, UInt<1>(0h0))
node _T_123 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_124 = and(_T_122, _T_123)
node _T_125 = leq(uncommonBits_4, UInt<2>(0h3))
node _T_126 = and(_T_124, _T_125)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_127 = shr(io.in.a.bits.source, 2)
node _T_128 = eq(_T_127, UInt<1>(0h1))
node _T_129 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_130 = and(_T_128, _T_129)
node _T_131 = leq(uncommonBits_5, UInt<2>(0h3))
node _T_132 = and(_T_130, _T_131)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_133 = shr(io.in.a.bits.source, 2)
node _T_134 = eq(_T_133, UInt<2>(0h2))
node _T_135 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_136 = and(_T_134, _T_135)
node _T_137 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_138 = and(_T_136, _T_137)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_139 = shr(io.in.a.bits.source, 2)
node _T_140 = eq(_T_139, UInt<2>(0h3))
node _T_141 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_142 = and(_T_140, _T_141)
node _T_143 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_144 = and(_T_142, _T_143)
node _T_145 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_146 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_147 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_148 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_149 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_150 = or(_T_120, _T_126)
node _T_151 = or(_T_150, _T_132)
node _T_152 = or(_T_151, _T_138)
node _T_153 = or(_T_152, _T_144)
node _T_154 = or(_T_153, _T_145)
node _T_155 = or(_T_154, _T_146)
node _T_156 = or(_T_155, _T_147)
node _T_157 = or(_T_156, _T_148)
node _T_158 = or(_T_157, _T_149)
node _T_159 = and(_T_119, _T_158)
node _T_160 = or(UInt<1>(0h0), _T_159)
node _T_161 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_162 = xor(io.in.a.bits.address, UInt<14>(0h2200))
node _T_163 = cvt(_T_162)
node _T_164 = and(_T_163, asSInt(UInt<10>(0h200)))
node _T_165 = asSInt(_T_164)
node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0)))
node _T_167 = and(_T_161, _T_166)
node _T_168 = or(UInt<1>(0h0), _T_167)
node _T_169 = and(_T_160, _T_168)
node _T_170 = asUInt(reset)
node _T_171 = eq(_T_170, UInt<1>(0h0))
when _T_171 :
node _T_172 = eq(_T_169, UInt<1>(0h0))
when _T_172 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_169, UInt<1>(0h1), "") : assert_2
node _T_173 = eq(io.in.a.bits.source, UInt<5>(0h11))
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_174 = shr(io.in.a.bits.source, 2)
node _T_175 = eq(_T_174, UInt<1>(0h0))
node _T_176 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_177 = and(_T_175, _T_176)
node _T_178 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_179 = and(_T_177, _T_178)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_180 = shr(io.in.a.bits.source, 2)
node _T_181 = eq(_T_180, UInt<1>(0h1))
node _T_182 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_183 = and(_T_181, _T_182)
node _T_184 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_185 = and(_T_183, _T_184)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_186 = shr(io.in.a.bits.source, 2)
node _T_187 = eq(_T_186, UInt<2>(0h2))
node _T_188 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_189 = and(_T_187, _T_188)
node _T_190 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_191 = and(_T_189, _T_190)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0)
node _T_192 = shr(io.in.a.bits.source, 2)
node _T_193 = eq(_T_192, UInt<2>(0h3))
node _T_194 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_195 = and(_T_193, _T_194)
node _T_196 = leq(uncommonBits_11, UInt<2>(0h3))
node _T_197 = and(_T_195, _T_196)
node _T_198 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_199 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_200 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_201 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_202 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE : UInt<1>[10]
connect _WIRE[0], _T_173
connect _WIRE[1], _T_179
connect _WIRE[2], _T_185
connect _WIRE[3], _T_191
connect _WIRE[4], _T_197
connect _WIRE[5], _T_198
connect _WIRE[6], _T_199
connect _WIRE[7], _T_200
connect _WIRE[8], _T_201
connect _WIRE[9], _T_202
node _T_203 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_204 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_205 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_206 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_207 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_208 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_209 = mux(_WIRE[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_210 = mux(_WIRE[6], _T_203, UInt<1>(0h0))
node _T_211 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_212 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_213 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_214 = or(_T_204, _T_205)
node _T_215 = or(_T_214, _T_206)
node _T_216 = or(_T_215, _T_207)
node _T_217 = or(_T_216, _T_208)
node _T_218 = or(_T_217, _T_209)
node _T_219 = or(_T_218, _T_210)
node _T_220 = or(_T_219, _T_211)
node _T_221 = or(_T_220, _T_212)
node _T_222 = or(_T_221, _T_213)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_222
node _T_223 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_224 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_225 = and(_T_223, _T_224)
node _T_226 = or(UInt<1>(0h0), _T_225)
node _T_227 = xor(io.in.a.bits.address, UInt<14>(0h2200))
node _T_228 = cvt(_T_227)
node _T_229 = and(_T_228, asSInt(UInt<10>(0h200)))
node _T_230 = asSInt(_T_229)
node _T_231 = eq(_T_230, asSInt(UInt<1>(0h0)))
node _T_232 = and(_T_226, _T_231)
node _T_233 = or(UInt<1>(0h0), _T_232)
node _T_234 = and(_WIRE_1, _T_233)
node _T_235 = asUInt(reset)
node _T_236 = eq(_T_235, UInt<1>(0h0))
when _T_236 :
node _T_237 = eq(_T_234, UInt<1>(0h0))
when _T_237 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_234, UInt<1>(0h1), "") : assert_3
node _T_238 = asUInt(reset)
node _T_239 = eq(_T_238, UInt<1>(0h0))
when _T_239 :
node _T_240 = eq(source_ok, UInt<1>(0h0))
when _T_240 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_241 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_242 = asUInt(reset)
node _T_243 = eq(_T_242, UInt<1>(0h0))
when _T_243 :
node _T_244 = eq(_T_241, UInt<1>(0h0))
when _T_244 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_241, UInt<1>(0h1), "") : assert_5
node _T_245 = asUInt(reset)
node _T_246 = eq(_T_245, UInt<1>(0h0))
when _T_246 :
node _T_247 = eq(is_aligned, UInt<1>(0h0))
when _T_247 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_248 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_249 = asUInt(reset)
node _T_250 = eq(_T_249, UInt<1>(0h0))
when _T_250 :
node _T_251 = eq(_T_248, UInt<1>(0h0))
when _T_251 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_248, UInt<1>(0h1), "") : assert_7
node _T_252 = not(io.in.a.bits.mask)
node _T_253 = eq(_T_252, UInt<1>(0h0))
node _T_254 = asUInt(reset)
node _T_255 = eq(_T_254, UInt<1>(0h0))
when _T_255 :
node _T_256 = eq(_T_253, UInt<1>(0h0))
when _T_256 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_253, UInt<1>(0h1), "") : assert_8
node _T_257 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_258 = asUInt(reset)
node _T_259 = eq(_T_258, UInt<1>(0h0))
when _T_259 :
node _T_260 = eq(_T_257, UInt<1>(0h0))
when _T_260 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_257, UInt<1>(0h1), "") : assert_9
node _T_261 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_261 :
node _T_262 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_263 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_264 = and(_T_262, _T_263)
node _T_265 = eq(io.in.a.bits.source, UInt<5>(0h11))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_266 = shr(io.in.a.bits.source, 2)
node _T_267 = eq(_T_266, UInt<1>(0h0))
node _T_268 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_269 = and(_T_267, _T_268)
node _T_270 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_271 = and(_T_269, _T_270)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_272 = shr(io.in.a.bits.source, 2)
node _T_273 = eq(_T_272, UInt<1>(0h1))
node _T_274 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_275 = and(_T_273, _T_274)
node _T_276 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_277 = and(_T_275, _T_276)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_278 = shr(io.in.a.bits.source, 2)
node _T_279 = eq(_T_278, UInt<2>(0h2))
node _T_280 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_281 = and(_T_279, _T_280)
node _T_282 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_283 = and(_T_281, _T_282)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_284 = shr(io.in.a.bits.source, 2)
node _T_285 = eq(_T_284, UInt<2>(0h3))
node _T_286 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_287 = and(_T_285, _T_286)
node _T_288 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_289 = and(_T_287, _T_288)
node _T_290 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_291 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_292 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_293 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_294 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_295 = or(_T_265, _T_271)
node _T_296 = or(_T_295, _T_277)
node _T_297 = or(_T_296, _T_283)
node _T_298 = or(_T_297, _T_289)
node _T_299 = or(_T_298, _T_290)
node _T_300 = or(_T_299, _T_291)
node _T_301 = or(_T_300, _T_292)
node _T_302 = or(_T_301, _T_293)
node _T_303 = or(_T_302, _T_294)
node _T_304 = and(_T_264, _T_303)
node _T_305 = or(UInt<1>(0h0), _T_304)
node _T_306 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_307 = xor(io.in.a.bits.address, UInt<14>(0h2200))
node _T_308 = cvt(_T_307)
node _T_309 = and(_T_308, asSInt(UInt<10>(0h200)))
node _T_310 = asSInt(_T_309)
node _T_311 = eq(_T_310, asSInt(UInt<1>(0h0)))
node _T_312 = and(_T_306, _T_311)
node _T_313 = or(UInt<1>(0h0), _T_312)
node _T_314 = and(_T_305, _T_313)
node _T_315 = asUInt(reset)
node _T_316 = eq(_T_315, UInt<1>(0h0))
when _T_316 :
node _T_317 = eq(_T_314, UInt<1>(0h0))
when _T_317 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_314, UInt<1>(0h1), "") : assert_10
node _T_318 = eq(io.in.a.bits.source, UInt<5>(0h11))
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_319 = shr(io.in.a.bits.source, 2)
node _T_320 = eq(_T_319, UInt<1>(0h0))
node _T_321 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_322 = and(_T_320, _T_321)
node _T_323 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_324 = and(_T_322, _T_323)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_325 = shr(io.in.a.bits.source, 2)
node _T_326 = eq(_T_325, UInt<1>(0h1))
node _T_327 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_328 = and(_T_326, _T_327)
node _T_329 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_330 = and(_T_328, _T_329)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_331 = shr(io.in.a.bits.source, 2)
node _T_332 = eq(_T_331, UInt<2>(0h2))
node _T_333 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_334 = and(_T_332, _T_333)
node _T_335 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_336 = and(_T_334, _T_335)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_337 = shr(io.in.a.bits.source, 2)
node _T_338 = eq(_T_337, UInt<2>(0h3))
node _T_339 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_340 = and(_T_338, _T_339)
node _T_341 = leq(uncommonBits_19, UInt<2>(0h3))
node _T_342 = and(_T_340, _T_341)
node _T_343 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_344 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_345 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_346 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_347 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE_2 : UInt<1>[10]
connect _WIRE_2[0], _T_318
connect _WIRE_2[1], _T_324
connect _WIRE_2[2], _T_330
connect _WIRE_2[3], _T_336
connect _WIRE_2[4], _T_342
connect _WIRE_2[5], _T_343
connect _WIRE_2[6], _T_344
connect _WIRE_2[7], _T_345
connect _WIRE_2[8], _T_346
connect _WIRE_2[9], _T_347
node _T_348 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_349 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_350 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_351 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_352 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_353 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_354 = mux(_WIRE_2[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_355 = mux(_WIRE_2[6], _T_348, UInt<1>(0h0))
node _T_356 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_357 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_358 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_359 = or(_T_349, _T_350)
node _T_360 = or(_T_359, _T_351)
node _T_361 = or(_T_360, _T_352)
node _T_362 = or(_T_361, _T_353)
node _T_363 = or(_T_362, _T_354)
node _T_364 = or(_T_363, _T_355)
node _T_365 = or(_T_364, _T_356)
node _T_366 = or(_T_365, _T_357)
node _T_367 = or(_T_366, _T_358)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_367
node _T_368 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_369 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_370 = and(_T_368, _T_369)
node _T_371 = or(UInt<1>(0h0), _T_370)
node _T_372 = xor(io.in.a.bits.address, UInt<14>(0h2200))
node _T_373 = cvt(_T_372)
node _T_374 = and(_T_373, asSInt(UInt<10>(0h200)))
node _T_375 = asSInt(_T_374)
node _T_376 = eq(_T_375, asSInt(UInt<1>(0h0)))
node _T_377 = and(_T_371, _T_376)
node _T_378 = or(UInt<1>(0h0), _T_377)
node _T_379 = and(_WIRE_3, _T_378)
node _T_380 = asUInt(reset)
node _T_381 = eq(_T_380, UInt<1>(0h0))
when _T_381 :
node _T_382 = eq(_T_379, UInt<1>(0h0))
when _T_382 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_379, UInt<1>(0h1), "") : assert_11
node _T_383 = asUInt(reset)
node _T_384 = eq(_T_383, UInt<1>(0h0))
when _T_384 :
node _T_385 = eq(source_ok, UInt<1>(0h0))
when _T_385 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_386 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_387 = asUInt(reset)
node _T_388 = eq(_T_387, UInt<1>(0h0))
when _T_388 :
node _T_389 = eq(_T_386, UInt<1>(0h0))
when _T_389 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_386, UInt<1>(0h1), "") : assert_13
node _T_390 = asUInt(reset)
node _T_391 = eq(_T_390, UInt<1>(0h0))
when _T_391 :
node _T_392 = eq(is_aligned, UInt<1>(0h0))
when _T_392 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_393 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_394 = asUInt(reset)
node _T_395 = eq(_T_394, UInt<1>(0h0))
when _T_395 :
node _T_396 = eq(_T_393, UInt<1>(0h0))
when _T_396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_393, UInt<1>(0h1), "") : assert_15
node _T_397 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_397, UInt<1>(0h1), "") : assert_16
node _T_401 = not(io.in.a.bits.mask)
node _T_402 = eq(_T_401, UInt<1>(0h0))
node _T_403 = asUInt(reset)
node _T_404 = eq(_T_403, UInt<1>(0h0))
when _T_404 :
node _T_405 = eq(_T_402, UInt<1>(0h0))
when _T_405 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_402, UInt<1>(0h1), "") : assert_17
node _T_406 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_407 = asUInt(reset)
node _T_408 = eq(_T_407, UInt<1>(0h0))
when _T_408 :
node _T_409 = eq(_T_406, UInt<1>(0h0))
when _T_409 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_406, UInt<1>(0h1), "") : assert_18
node _T_410 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_410 :
node _T_411 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_412 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_413 = and(_T_411, _T_412)
node _T_414 = eq(io.in.a.bits.source, UInt<5>(0h11))
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_415 = shr(io.in.a.bits.source, 2)
node _T_416 = eq(_T_415, UInt<1>(0h0))
node _T_417 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_418 = and(_T_416, _T_417)
node _T_419 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_420 = and(_T_418, _T_419)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_421 = shr(io.in.a.bits.source, 2)
node _T_422 = eq(_T_421, UInt<1>(0h1))
node _T_423 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_424 = and(_T_422, _T_423)
node _T_425 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_426 = and(_T_424, _T_425)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_427 = shr(io.in.a.bits.source, 2)
node _T_428 = eq(_T_427, UInt<2>(0h2))
node _T_429 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_430 = and(_T_428, _T_429)
node _T_431 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_432 = and(_T_430, _T_431)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_433 = shr(io.in.a.bits.source, 2)
node _T_434 = eq(_T_433, UInt<2>(0h3))
node _T_435 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_436 = and(_T_434, _T_435)
node _T_437 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_438 = and(_T_436, _T_437)
node _T_439 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_440 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_441 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_442 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_443 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_444 = or(_T_414, _T_420)
node _T_445 = or(_T_444, _T_426)
node _T_446 = or(_T_445, _T_432)
node _T_447 = or(_T_446, _T_438)
node _T_448 = or(_T_447, _T_439)
node _T_449 = or(_T_448, _T_440)
node _T_450 = or(_T_449, _T_441)
node _T_451 = or(_T_450, _T_442)
node _T_452 = or(_T_451, _T_443)
node _T_453 = and(_T_413, _T_452)
node _T_454 = or(UInt<1>(0h0), _T_453)
node _T_455 = asUInt(reset)
node _T_456 = eq(_T_455, UInt<1>(0h0))
when _T_456 :
node _T_457 = eq(_T_454, UInt<1>(0h0))
when _T_457 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_454, UInt<1>(0h1), "") : assert_19
node _T_458 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_459 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_460 = and(_T_458, _T_459)
node _T_461 = or(UInt<1>(0h0), _T_460)
node _T_462 = xor(io.in.a.bits.address, UInt<14>(0h2200))
node _T_463 = cvt(_T_462)
node _T_464 = and(_T_463, asSInt(UInt<10>(0h200)))
node _T_465 = asSInt(_T_464)
node _T_466 = eq(_T_465, asSInt(UInt<1>(0h0)))
node _T_467 = and(_T_461, _T_466)
node _T_468 = or(UInt<1>(0h0), _T_467)
node _T_469 = asUInt(reset)
node _T_470 = eq(_T_469, UInt<1>(0h0))
when _T_470 :
node _T_471 = eq(_T_468, UInt<1>(0h0))
when _T_471 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_468, UInt<1>(0h1), "") : assert_20
node _T_472 = asUInt(reset)
node _T_473 = eq(_T_472, UInt<1>(0h0))
when _T_473 :
node _T_474 = eq(source_ok, UInt<1>(0h0))
when _T_474 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_475 = asUInt(reset)
node _T_476 = eq(_T_475, UInt<1>(0h0))
when _T_476 :
node _T_477 = eq(is_aligned, UInt<1>(0h0))
when _T_477 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_478 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_479 = asUInt(reset)
node _T_480 = eq(_T_479, UInt<1>(0h0))
when _T_480 :
node _T_481 = eq(_T_478, UInt<1>(0h0))
when _T_481 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_478, UInt<1>(0h1), "") : assert_23
node _T_482 = eq(io.in.a.bits.mask, mask)
node _T_483 = asUInt(reset)
node _T_484 = eq(_T_483, UInt<1>(0h0))
when _T_484 :
node _T_485 = eq(_T_482, UInt<1>(0h0))
when _T_485 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_482, UInt<1>(0h1), "") : assert_24
node _T_486 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_487 = asUInt(reset)
node _T_488 = eq(_T_487, UInt<1>(0h0))
when _T_488 :
node _T_489 = eq(_T_486, UInt<1>(0h0))
when _T_489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_486, UInt<1>(0h1), "") : assert_25
node _T_490 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_490 :
node _T_491 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_492 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_493 = and(_T_491, _T_492)
node _T_494 = eq(io.in.a.bits.source, UInt<5>(0h11))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_495 = shr(io.in.a.bits.source, 2)
node _T_496 = eq(_T_495, UInt<1>(0h0))
node _T_497 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_498 = and(_T_496, _T_497)
node _T_499 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_500 = and(_T_498, _T_499)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_501 = shr(io.in.a.bits.source, 2)
node _T_502 = eq(_T_501, UInt<1>(0h1))
node _T_503 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_504 = and(_T_502, _T_503)
node _T_505 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_506 = and(_T_504, _T_505)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_507 = shr(io.in.a.bits.source, 2)
node _T_508 = eq(_T_507, UInt<2>(0h2))
node _T_509 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_510 = and(_T_508, _T_509)
node _T_511 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_512 = and(_T_510, _T_511)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_513 = shr(io.in.a.bits.source, 2)
node _T_514 = eq(_T_513, UInt<2>(0h3))
node _T_515 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_516 = and(_T_514, _T_515)
node _T_517 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_518 = and(_T_516, _T_517)
node _T_519 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_520 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_521 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_522 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_523 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_524 = or(_T_494, _T_500)
node _T_525 = or(_T_524, _T_506)
node _T_526 = or(_T_525, _T_512)
node _T_527 = or(_T_526, _T_518)
node _T_528 = or(_T_527, _T_519)
node _T_529 = or(_T_528, _T_520)
node _T_530 = or(_T_529, _T_521)
node _T_531 = or(_T_530, _T_522)
node _T_532 = or(_T_531, _T_523)
node _T_533 = and(_T_493, _T_532)
node _T_534 = or(UInt<1>(0h0), _T_533)
node _T_535 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_536 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_537 = and(_T_535, _T_536)
node _T_538 = or(UInt<1>(0h0), _T_537)
node _T_539 = xor(io.in.a.bits.address, UInt<14>(0h2200))
node _T_540 = cvt(_T_539)
node _T_541 = and(_T_540, asSInt(UInt<10>(0h200)))
node _T_542 = asSInt(_T_541)
node _T_543 = eq(_T_542, asSInt(UInt<1>(0h0)))
node _T_544 = and(_T_538, _T_543)
node _T_545 = or(UInt<1>(0h0), _T_544)
node _T_546 = and(_T_534, _T_545)
node _T_547 = asUInt(reset)
node _T_548 = eq(_T_547, UInt<1>(0h0))
when _T_548 :
node _T_549 = eq(_T_546, UInt<1>(0h0))
when _T_549 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_546, UInt<1>(0h1), "") : assert_26
node _T_550 = asUInt(reset)
node _T_551 = eq(_T_550, UInt<1>(0h0))
when _T_551 :
node _T_552 = eq(source_ok, UInt<1>(0h0))
when _T_552 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_553 = asUInt(reset)
node _T_554 = eq(_T_553, UInt<1>(0h0))
when _T_554 :
node _T_555 = eq(is_aligned, UInt<1>(0h0))
when _T_555 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_556 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_556, UInt<1>(0h1), "") : assert_29
node _T_560 = eq(io.in.a.bits.mask, mask)
node _T_561 = asUInt(reset)
node _T_562 = eq(_T_561, UInt<1>(0h0))
when _T_562 :
node _T_563 = eq(_T_560, UInt<1>(0h0))
when _T_563 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_560, UInt<1>(0h1), "") : assert_30
node _T_564 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_564 :
node _T_565 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_566 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_567 = and(_T_565, _T_566)
node _T_568 = eq(io.in.a.bits.source, UInt<5>(0h11))
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_569 = shr(io.in.a.bits.source, 2)
node _T_570 = eq(_T_569, UInt<1>(0h0))
node _T_571 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_572 = and(_T_570, _T_571)
node _T_573 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_574 = and(_T_572, _T_573)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0)
node _T_575 = shr(io.in.a.bits.source, 2)
node _T_576 = eq(_T_575, UInt<1>(0h1))
node _T_577 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_578 = and(_T_576, _T_577)
node _T_579 = leq(uncommonBits_29, UInt<2>(0h3))
node _T_580 = and(_T_578, _T_579)
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_581 = shr(io.in.a.bits.source, 2)
node _T_582 = eq(_T_581, UInt<2>(0h2))
node _T_583 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_584 = and(_T_582, _T_583)
node _T_585 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_586 = and(_T_584, _T_585)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_587 = shr(io.in.a.bits.source, 2)
node _T_588 = eq(_T_587, UInt<2>(0h3))
node _T_589 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_590 = and(_T_588, _T_589)
node _T_591 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_592 = and(_T_590, _T_591)
node _T_593 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_594 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_595 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_596 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_597 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_598 = or(_T_568, _T_574)
node _T_599 = or(_T_598, _T_580)
node _T_600 = or(_T_599, _T_586)
node _T_601 = or(_T_600, _T_592)
node _T_602 = or(_T_601, _T_593)
node _T_603 = or(_T_602, _T_594)
node _T_604 = or(_T_603, _T_595)
node _T_605 = or(_T_604, _T_596)
node _T_606 = or(_T_605, _T_597)
node _T_607 = and(_T_567, _T_606)
node _T_608 = or(UInt<1>(0h0), _T_607)
node _T_609 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_610 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_611 = and(_T_609, _T_610)
node _T_612 = or(UInt<1>(0h0), _T_611)
node _T_613 = xor(io.in.a.bits.address, UInt<14>(0h2200))
node _T_614 = cvt(_T_613)
node _T_615 = and(_T_614, asSInt(UInt<10>(0h200)))
node _T_616 = asSInt(_T_615)
node _T_617 = eq(_T_616, asSInt(UInt<1>(0h0)))
node _T_618 = and(_T_612, _T_617)
node _T_619 = or(UInt<1>(0h0), _T_618)
node _T_620 = and(_T_608, _T_619)
node _T_621 = asUInt(reset)
node _T_622 = eq(_T_621, UInt<1>(0h0))
when _T_622 :
node _T_623 = eq(_T_620, UInt<1>(0h0))
when _T_623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_620, UInt<1>(0h1), "") : assert_31
node _T_624 = asUInt(reset)
node _T_625 = eq(_T_624, UInt<1>(0h0))
when _T_625 :
node _T_626 = eq(source_ok, UInt<1>(0h0))
when _T_626 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_627 = asUInt(reset)
node _T_628 = eq(_T_627, UInt<1>(0h0))
when _T_628 :
node _T_629 = eq(is_aligned, UInt<1>(0h0))
when _T_629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_630 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_630, UInt<1>(0h1), "") : assert_34
node _T_634 = not(mask)
node _T_635 = and(io.in.a.bits.mask, _T_634)
node _T_636 = eq(_T_635, UInt<1>(0h0))
node _T_637 = asUInt(reset)
node _T_638 = eq(_T_637, UInt<1>(0h0))
when _T_638 :
node _T_639 = eq(_T_636, UInt<1>(0h0))
when _T_639 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_636, UInt<1>(0h1), "") : assert_35
node _T_640 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_640 :
node _T_641 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_642 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_643 = and(_T_641, _T_642)
node _T_644 = eq(io.in.a.bits.source, UInt<5>(0h11))
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_645 = shr(io.in.a.bits.source, 2)
node _T_646 = eq(_T_645, UInt<1>(0h0))
node _T_647 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_648 = and(_T_646, _T_647)
node _T_649 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_650 = and(_T_648, _T_649)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_651 = shr(io.in.a.bits.source, 2)
node _T_652 = eq(_T_651, UInt<1>(0h1))
node _T_653 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_654 = and(_T_652, _T_653)
node _T_655 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_656 = and(_T_654, _T_655)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0)
node _T_657 = shr(io.in.a.bits.source, 2)
node _T_658 = eq(_T_657, UInt<2>(0h2))
node _T_659 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_660 = and(_T_658, _T_659)
node _T_661 = leq(uncommonBits_34, UInt<2>(0h3))
node _T_662 = and(_T_660, _T_661)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_663 = shr(io.in.a.bits.source, 2)
node _T_664 = eq(_T_663, UInt<2>(0h3))
node _T_665 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_666 = and(_T_664, _T_665)
node _T_667 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_668 = and(_T_666, _T_667)
node _T_669 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_670 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_671 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_672 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_673 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_674 = or(_T_644, _T_650)
node _T_675 = or(_T_674, _T_656)
node _T_676 = or(_T_675, _T_662)
node _T_677 = or(_T_676, _T_668)
node _T_678 = or(_T_677, _T_669)
node _T_679 = or(_T_678, _T_670)
node _T_680 = or(_T_679, _T_671)
node _T_681 = or(_T_680, _T_672)
node _T_682 = or(_T_681, _T_673)
node _T_683 = and(_T_643, _T_682)
node _T_684 = or(UInt<1>(0h0), _T_683)
node _T_685 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_686 = xor(io.in.a.bits.address, UInt<14>(0h2200))
node _T_687 = cvt(_T_686)
node _T_688 = and(_T_687, asSInt(UInt<10>(0h200)))
node _T_689 = asSInt(_T_688)
node _T_690 = eq(_T_689, asSInt(UInt<1>(0h0)))
node _T_691 = and(_T_685, _T_690)
node _T_692 = or(UInt<1>(0h0), _T_691)
node _T_693 = and(_T_684, _T_692)
node _T_694 = asUInt(reset)
node _T_695 = eq(_T_694, UInt<1>(0h0))
when _T_695 :
node _T_696 = eq(_T_693, UInt<1>(0h0))
when _T_696 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_693, UInt<1>(0h1), "") : assert_36
node _T_697 = asUInt(reset)
node _T_698 = eq(_T_697, UInt<1>(0h0))
when _T_698 :
node _T_699 = eq(source_ok, UInt<1>(0h0))
when _T_699 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_700 = asUInt(reset)
node _T_701 = eq(_T_700, UInt<1>(0h0))
when _T_701 :
node _T_702 = eq(is_aligned, UInt<1>(0h0))
when _T_702 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_703 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_704 = asUInt(reset)
node _T_705 = eq(_T_704, UInt<1>(0h0))
when _T_705 :
node _T_706 = eq(_T_703, UInt<1>(0h0))
when _T_706 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_703, UInt<1>(0h1), "") : assert_39
node _T_707 = eq(io.in.a.bits.mask, mask)
node _T_708 = asUInt(reset)
node _T_709 = eq(_T_708, UInt<1>(0h0))
when _T_709 :
node _T_710 = eq(_T_707, UInt<1>(0h0))
when _T_710 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_707, UInt<1>(0h1), "") : assert_40
node _T_711 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_711 :
node _T_712 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_713 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_714 = and(_T_712, _T_713)
node _T_715 = eq(io.in.a.bits.source, UInt<5>(0h11))
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_716 = shr(io.in.a.bits.source, 2)
node _T_717 = eq(_T_716, UInt<1>(0h0))
node _T_718 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_719 = and(_T_717, _T_718)
node _T_720 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_721 = and(_T_719, _T_720)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_722 = shr(io.in.a.bits.source, 2)
node _T_723 = eq(_T_722, UInt<1>(0h1))
node _T_724 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_725 = and(_T_723, _T_724)
node _T_726 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_727 = and(_T_725, _T_726)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_728 = shr(io.in.a.bits.source, 2)
node _T_729 = eq(_T_728, UInt<2>(0h2))
node _T_730 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_731 = and(_T_729, _T_730)
node _T_732 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_733 = and(_T_731, _T_732)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0)
node _T_734 = shr(io.in.a.bits.source, 2)
node _T_735 = eq(_T_734, UInt<2>(0h3))
node _T_736 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_737 = and(_T_735, _T_736)
node _T_738 = leq(uncommonBits_39, UInt<2>(0h3))
node _T_739 = and(_T_737, _T_738)
node _T_740 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_741 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_742 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_743 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_744 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_745 = or(_T_715, _T_721)
node _T_746 = or(_T_745, _T_727)
node _T_747 = or(_T_746, _T_733)
node _T_748 = or(_T_747, _T_739)
node _T_749 = or(_T_748, _T_740)
node _T_750 = or(_T_749, _T_741)
node _T_751 = or(_T_750, _T_742)
node _T_752 = or(_T_751, _T_743)
node _T_753 = or(_T_752, _T_744)
node _T_754 = and(_T_714, _T_753)
node _T_755 = or(UInt<1>(0h0), _T_754)
node _T_756 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_757 = xor(io.in.a.bits.address, UInt<14>(0h2200))
node _T_758 = cvt(_T_757)
node _T_759 = and(_T_758, asSInt(UInt<10>(0h200)))
node _T_760 = asSInt(_T_759)
node _T_761 = eq(_T_760, asSInt(UInt<1>(0h0)))
node _T_762 = and(_T_756, _T_761)
node _T_763 = or(UInt<1>(0h0), _T_762)
node _T_764 = and(_T_755, _T_763)
node _T_765 = asUInt(reset)
node _T_766 = eq(_T_765, UInt<1>(0h0))
when _T_766 :
node _T_767 = eq(_T_764, UInt<1>(0h0))
when _T_767 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_764, UInt<1>(0h1), "") : assert_41
node _T_768 = asUInt(reset)
node _T_769 = eq(_T_768, UInt<1>(0h0))
when _T_769 :
node _T_770 = eq(source_ok, UInt<1>(0h0))
when _T_770 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_771 = asUInt(reset)
node _T_772 = eq(_T_771, UInt<1>(0h0))
when _T_772 :
node _T_773 = eq(is_aligned, UInt<1>(0h0))
when _T_773 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_774 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_775 = asUInt(reset)
node _T_776 = eq(_T_775, UInt<1>(0h0))
when _T_776 :
node _T_777 = eq(_T_774, UInt<1>(0h0))
when _T_777 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_774, UInt<1>(0h1), "") : assert_44
node _T_778 = eq(io.in.a.bits.mask, mask)
node _T_779 = asUInt(reset)
node _T_780 = eq(_T_779, UInt<1>(0h0))
when _T_780 :
node _T_781 = eq(_T_778, UInt<1>(0h0))
when _T_781 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_778, UInt<1>(0h1), "") : assert_45
node _T_782 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_782 :
node _T_783 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_784 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_785 = and(_T_783, _T_784)
node _T_786 = eq(io.in.a.bits.source, UInt<5>(0h11))
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0)
node _T_787 = shr(io.in.a.bits.source, 2)
node _T_788 = eq(_T_787, UInt<1>(0h0))
node _T_789 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_790 = and(_T_788, _T_789)
node _T_791 = leq(uncommonBits_40, UInt<2>(0h3))
node _T_792 = and(_T_790, _T_791)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0)
node _T_793 = shr(io.in.a.bits.source, 2)
node _T_794 = eq(_T_793, UInt<1>(0h1))
node _T_795 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_796 = and(_T_794, _T_795)
node _T_797 = leq(uncommonBits_41, UInt<2>(0h3))
node _T_798 = and(_T_796, _T_797)
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0)
node _T_799 = shr(io.in.a.bits.source, 2)
node _T_800 = eq(_T_799, UInt<2>(0h2))
node _T_801 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_802 = and(_T_800, _T_801)
node _T_803 = leq(uncommonBits_42, UInt<2>(0h3))
node _T_804 = and(_T_802, _T_803)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0)
node _T_805 = shr(io.in.a.bits.source, 2)
node _T_806 = eq(_T_805, UInt<2>(0h3))
node _T_807 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_808 = and(_T_806, _T_807)
node _T_809 = leq(uncommonBits_43, UInt<2>(0h3))
node _T_810 = and(_T_808, _T_809)
node _T_811 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_812 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_813 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_814 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_815 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_816 = or(_T_786, _T_792)
node _T_817 = or(_T_816, _T_798)
node _T_818 = or(_T_817, _T_804)
node _T_819 = or(_T_818, _T_810)
node _T_820 = or(_T_819, _T_811)
node _T_821 = or(_T_820, _T_812)
node _T_822 = or(_T_821, _T_813)
node _T_823 = or(_T_822, _T_814)
node _T_824 = or(_T_823, _T_815)
node _T_825 = and(_T_785, _T_824)
node _T_826 = or(UInt<1>(0h0), _T_825)
node _T_827 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_828 = xor(io.in.a.bits.address, UInt<14>(0h2200))
node _T_829 = cvt(_T_828)
node _T_830 = and(_T_829, asSInt(UInt<10>(0h200)))
node _T_831 = asSInt(_T_830)
node _T_832 = eq(_T_831, asSInt(UInt<1>(0h0)))
node _T_833 = and(_T_827, _T_832)
node _T_834 = or(UInt<1>(0h0), _T_833)
node _T_835 = and(_T_826, _T_834)
node _T_836 = asUInt(reset)
node _T_837 = eq(_T_836, UInt<1>(0h0))
when _T_837 :
node _T_838 = eq(_T_835, UInt<1>(0h0))
when _T_838 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_835, UInt<1>(0h1), "") : assert_46
node _T_839 = asUInt(reset)
node _T_840 = eq(_T_839, UInt<1>(0h0))
when _T_840 :
node _T_841 = eq(source_ok, UInt<1>(0h0))
when _T_841 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_842 = asUInt(reset)
node _T_843 = eq(_T_842, UInt<1>(0h0))
when _T_843 :
node _T_844 = eq(is_aligned, UInt<1>(0h0))
when _T_844 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_845 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_846 = asUInt(reset)
node _T_847 = eq(_T_846, UInt<1>(0h0))
when _T_847 :
node _T_848 = eq(_T_845, UInt<1>(0h0))
when _T_848 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_845, UInt<1>(0h1), "") : assert_49
node _T_849 = eq(io.in.a.bits.mask, mask)
node _T_850 = asUInt(reset)
node _T_851 = eq(_T_850, UInt<1>(0h0))
when _T_851 :
node _T_852 = eq(_T_849, UInt<1>(0h0))
when _T_852 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_849, UInt<1>(0h1), "") : assert_50
node _T_853 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_854 = asUInt(reset)
node _T_855 = eq(_T_854, UInt<1>(0h0))
when _T_855 :
node _T_856 = eq(_T_853, UInt<1>(0h0))
when _T_856 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_853, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_857 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_858 = asUInt(reset)
node _T_859 = eq(_T_858, UInt<1>(0h0))
when _T_859 :
node _T_860 = eq(_T_857, UInt<1>(0h0))
when _T_860 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_857, UInt<1>(0h1), "") : assert_52
node _source_ok_T_38 = eq(io.in.d.bits.source, UInt<5>(0h11))
node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0)
node _source_ok_T_39 = shr(io.in.d.bits.source, 2)
node _source_ok_T_40 = eq(_source_ok_T_39, UInt<1>(0h0))
node _source_ok_T_41 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41)
node _source_ok_T_43 = leq(source_ok_uncommonBits_4, UInt<2>(0h3))
node _source_ok_T_44 = and(_source_ok_T_42, _source_ok_T_43)
node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0)
node _source_ok_T_45 = shr(io.in.d.bits.source, 2)
node _source_ok_T_46 = eq(_source_ok_T_45, UInt<1>(0h1))
node _source_ok_T_47 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47)
node _source_ok_T_49 = leq(source_ok_uncommonBits_5, UInt<2>(0h3))
node _source_ok_T_50 = and(_source_ok_T_48, _source_ok_T_49)
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_51 = shr(io.in.d.bits.source, 2)
node _source_ok_T_52 = eq(_source_ok_T_51, UInt<2>(0h2))
node _source_ok_T_53 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53)
node _source_ok_T_55 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_57 = shr(io.in.d.bits.source, 2)
node _source_ok_T_58 = eq(_source_ok_T_57, UInt<2>(0h3))
node _source_ok_T_59 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59)
node _source_ok_T_61 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_62 = and(_source_ok_T_60, _source_ok_T_61)
node _source_ok_T_63 = eq(io.in.d.bits.source, UInt<5>(0h10))
node _source_ok_T_64 = eq(io.in.d.bits.source, UInt<6>(0h20))
node _source_ok_T_65 = eq(io.in.d.bits.source, UInt<6>(0h21))
node _source_ok_T_66 = eq(io.in.d.bits.source, UInt<6>(0h22))
node _source_ok_T_67 = eq(io.in.d.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE_1 : UInt<1>[10]
connect _source_ok_WIRE_1[0], _source_ok_T_38
connect _source_ok_WIRE_1[1], _source_ok_T_44
connect _source_ok_WIRE_1[2], _source_ok_T_50
connect _source_ok_WIRE_1[3], _source_ok_T_56
connect _source_ok_WIRE_1[4], _source_ok_T_62
connect _source_ok_WIRE_1[5], _source_ok_T_63
connect _source_ok_WIRE_1[6], _source_ok_T_64
connect _source_ok_WIRE_1[7], _source_ok_T_65
connect _source_ok_WIRE_1[8], _source_ok_T_66
connect _source_ok_WIRE_1[9], _source_ok_T_67
node _source_ok_T_68 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE_1[2])
node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE_1[3])
node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE_1[4])
node _source_ok_T_72 = or(_source_ok_T_71, _source_ok_WIRE_1[5])
node _source_ok_T_73 = or(_source_ok_T_72, _source_ok_WIRE_1[6])
node _source_ok_T_74 = or(_source_ok_T_73, _source_ok_WIRE_1[7])
node _source_ok_T_75 = or(_source_ok_T_74, _source_ok_WIRE_1[8])
node source_ok_1 = or(_source_ok_T_75, _source_ok_WIRE_1[9])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_861 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_861 :
node _T_862 = asUInt(reset)
node _T_863 = eq(_T_862, UInt<1>(0h0))
when _T_863 :
node _T_864 = eq(source_ok_1, UInt<1>(0h0))
when _T_864 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_865 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_866 = asUInt(reset)
node _T_867 = eq(_T_866, UInt<1>(0h0))
when _T_867 :
node _T_868 = eq(_T_865, UInt<1>(0h0))
when _T_868 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_865, UInt<1>(0h1), "") : assert_54
node _T_869 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_870 = asUInt(reset)
node _T_871 = eq(_T_870, UInt<1>(0h0))
when _T_871 :
node _T_872 = eq(_T_869, UInt<1>(0h0))
when _T_872 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_869, UInt<1>(0h1), "") : assert_55
node _T_873 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_874 = asUInt(reset)
node _T_875 = eq(_T_874, UInt<1>(0h0))
when _T_875 :
node _T_876 = eq(_T_873, UInt<1>(0h0))
when _T_876 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_873, UInt<1>(0h1), "") : assert_56
node _T_877 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_878 = asUInt(reset)
node _T_879 = eq(_T_878, UInt<1>(0h0))
when _T_879 :
node _T_880 = eq(_T_877, UInt<1>(0h0))
when _T_880 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_877, UInt<1>(0h1), "") : assert_57
node _T_881 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_881 :
node _T_882 = asUInt(reset)
node _T_883 = eq(_T_882, UInt<1>(0h0))
when _T_883 :
node _T_884 = eq(source_ok_1, UInt<1>(0h0))
when _T_884 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_885 = asUInt(reset)
node _T_886 = eq(_T_885, UInt<1>(0h0))
when _T_886 :
node _T_887 = eq(sink_ok, UInt<1>(0h0))
when _T_887 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_888 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_889 = asUInt(reset)
node _T_890 = eq(_T_889, UInt<1>(0h0))
when _T_890 :
node _T_891 = eq(_T_888, UInt<1>(0h0))
when _T_891 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_888, UInt<1>(0h1), "") : assert_60
node _T_892 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_893 = asUInt(reset)
node _T_894 = eq(_T_893, UInt<1>(0h0))
when _T_894 :
node _T_895 = eq(_T_892, UInt<1>(0h0))
when _T_895 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_892, UInt<1>(0h1), "") : assert_61
node _T_896 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_897 = asUInt(reset)
node _T_898 = eq(_T_897, UInt<1>(0h0))
when _T_898 :
node _T_899 = eq(_T_896, UInt<1>(0h0))
when _T_899 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_896, UInt<1>(0h1), "") : assert_62
node _T_900 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_901 = asUInt(reset)
node _T_902 = eq(_T_901, UInt<1>(0h0))
when _T_902 :
node _T_903 = eq(_T_900, UInt<1>(0h0))
when _T_903 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_900, UInt<1>(0h1), "") : assert_63
node _T_904 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_905 = or(UInt<1>(0h0), _T_904)
node _T_906 = asUInt(reset)
node _T_907 = eq(_T_906, UInt<1>(0h0))
when _T_907 :
node _T_908 = eq(_T_905, UInt<1>(0h0))
when _T_908 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_905, UInt<1>(0h1), "") : assert_64
node _T_909 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_909 :
node _T_910 = asUInt(reset)
node _T_911 = eq(_T_910, UInt<1>(0h0))
when _T_911 :
node _T_912 = eq(source_ok_1, UInt<1>(0h0))
when _T_912 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_913 = asUInt(reset)
node _T_914 = eq(_T_913, UInt<1>(0h0))
when _T_914 :
node _T_915 = eq(sink_ok, UInt<1>(0h0))
when _T_915 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_916 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_917 = asUInt(reset)
node _T_918 = eq(_T_917, UInt<1>(0h0))
when _T_918 :
node _T_919 = eq(_T_916, UInt<1>(0h0))
when _T_919 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_916, UInt<1>(0h1), "") : assert_67
node _T_920 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_921 = asUInt(reset)
node _T_922 = eq(_T_921, UInt<1>(0h0))
when _T_922 :
node _T_923 = eq(_T_920, UInt<1>(0h0))
when _T_923 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_920, UInt<1>(0h1), "") : assert_68
node _T_924 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_925 = asUInt(reset)
node _T_926 = eq(_T_925, UInt<1>(0h0))
when _T_926 :
node _T_927 = eq(_T_924, UInt<1>(0h0))
when _T_927 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_924, UInt<1>(0h1), "") : assert_69
node _T_928 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_929 = or(_T_928, io.in.d.bits.corrupt)
node _T_930 = asUInt(reset)
node _T_931 = eq(_T_930, UInt<1>(0h0))
when _T_931 :
node _T_932 = eq(_T_929, UInt<1>(0h0))
when _T_932 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_929, UInt<1>(0h1), "") : assert_70
node _T_933 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_934 = or(UInt<1>(0h0), _T_933)
node _T_935 = asUInt(reset)
node _T_936 = eq(_T_935, UInt<1>(0h0))
when _T_936 :
node _T_937 = eq(_T_934, UInt<1>(0h0))
when _T_937 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_934, UInt<1>(0h1), "") : assert_71
node _T_938 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_938 :
node _T_939 = asUInt(reset)
node _T_940 = eq(_T_939, UInt<1>(0h0))
when _T_940 :
node _T_941 = eq(source_ok_1, UInt<1>(0h0))
when _T_941 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_942 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_943 = asUInt(reset)
node _T_944 = eq(_T_943, UInt<1>(0h0))
when _T_944 :
node _T_945 = eq(_T_942, UInt<1>(0h0))
when _T_945 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_942, UInt<1>(0h1), "") : assert_73
node _T_946 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_947 = asUInt(reset)
node _T_948 = eq(_T_947, UInt<1>(0h0))
when _T_948 :
node _T_949 = eq(_T_946, UInt<1>(0h0))
when _T_949 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_946, UInt<1>(0h1), "") : assert_74
node _T_950 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_951 = or(UInt<1>(0h0), _T_950)
node _T_952 = asUInt(reset)
node _T_953 = eq(_T_952, UInt<1>(0h0))
when _T_953 :
node _T_954 = eq(_T_951, UInt<1>(0h0))
when _T_954 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_951, UInt<1>(0h1), "") : assert_75
node _T_955 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_955 :
node _T_956 = asUInt(reset)
node _T_957 = eq(_T_956, UInt<1>(0h0))
when _T_957 :
node _T_958 = eq(source_ok_1, UInt<1>(0h0))
when _T_958 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_959 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_960 = asUInt(reset)
node _T_961 = eq(_T_960, UInt<1>(0h0))
when _T_961 :
node _T_962 = eq(_T_959, UInt<1>(0h0))
when _T_962 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_959, UInt<1>(0h1), "") : assert_77
node _T_963 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_964 = or(_T_963, io.in.d.bits.corrupt)
node _T_965 = asUInt(reset)
node _T_966 = eq(_T_965, UInt<1>(0h0))
when _T_966 :
node _T_967 = eq(_T_964, UInt<1>(0h0))
when _T_967 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_964, UInt<1>(0h1), "") : assert_78
node _T_968 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_969 = or(UInt<1>(0h0), _T_968)
node _T_970 = asUInt(reset)
node _T_971 = eq(_T_970, UInt<1>(0h0))
when _T_971 :
node _T_972 = eq(_T_969, UInt<1>(0h0))
when _T_972 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_969, UInt<1>(0h1), "") : assert_79
node _T_973 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_973 :
node _T_974 = asUInt(reset)
node _T_975 = eq(_T_974, UInt<1>(0h0))
when _T_975 :
node _T_976 = eq(source_ok_1, UInt<1>(0h0))
when _T_976 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_977 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_978 = asUInt(reset)
node _T_979 = eq(_T_978, UInt<1>(0h0))
when _T_979 :
node _T_980 = eq(_T_977, UInt<1>(0h0))
when _T_980 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_977, UInt<1>(0h1), "") : assert_81
node _T_981 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_982 = asUInt(reset)
node _T_983 = eq(_T_982, UInt<1>(0h0))
when _T_983 :
node _T_984 = eq(_T_981, UInt<1>(0h0))
when _T_984 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_981, UInt<1>(0h1), "") : assert_82
node _T_985 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_986 = or(UInt<1>(0h0), _T_985)
node _T_987 = asUInt(reset)
node _T_988 = eq(_T_987, UInt<1>(0h0))
when _T_988 :
node _T_989 = eq(_T_986, UInt<1>(0h0))
when _T_989 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_986, UInt<1>(0h1), "") : assert_83
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<14>(0h0)
connect _WIRE_4.bits.source, UInt<7>(0h0)
connect _WIRE_4.bits.size, UInt<3>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_990 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_991 = asUInt(reset)
node _T_992 = eq(_T_991, UInt<1>(0h0))
when _T_992 :
node _T_993 = eq(_T_990, UInt<1>(0h0))
when _T_993 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_990, UInt<1>(0h1), "") : assert_84
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<14>(0h0)
connect _WIRE_6.bits.source, UInt<7>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_994 = eq(_WIRE_7.valid, UInt<1>(0h0))
node _T_995 = asUInt(reset)
node _T_996 = eq(_T_995, UInt<1>(0h0))
when _T_996 :
node _T_997 = eq(_T_994, UInt<1>(0h0))
when _T_997 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_994, UInt<1>(0h1), "") : assert_85
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_8.bits.sink, UInt<1>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_998 = eq(_WIRE_9.valid, UInt<1>(0h0))
node _T_999 = asUInt(reset)
node _T_1000 = eq(_T_999, UInt<1>(0h0))
when _T_1000 :
node _T_1001 = eq(_T_998, UInt<1>(0h0))
when _T_1001 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_998, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1002 = eq(a_first, UInt<1>(0h0))
node _T_1003 = and(io.in.a.valid, _T_1002)
when _T_1003 :
node _T_1004 = eq(io.in.a.bits.opcode, opcode)
node _T_1005 = asUInt(reset)
node _T_1006 = eq(_T_1005, UInt<1>(0h0))
when _T_1006 :
node _T_1007 = eq(_T_1004, UInt<1>(0h0))
when _T_1007 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1004, UInt<1>(0h1), "") : assert_87
node _T_1008 = eq(io.in.a.bits.param, param)
node _T_1009 = asUInt(reset)
node _T_1010 = eq(_T_1009, UInt<1>(0h0))
when _T_1010 :
node _T_1011 = eq(_T_1008, UInt<1>(0h0))
when _T_1011 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1008, UInt<1>(0h1), "") : assert_88
node _T_1012 = eq(io.in.a.bits.size, size)
node _T_1013 = asUInt(reset)
node _T_1014 = eq(_T_1013, UInt<1>(0h0))
when _T_1014 :
node _T_1015 = eq(_T_1012, UInt<1>(0h0))
when _T_1015 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1012, UInt<1>(0h1), "") : assert_89
node _T_1016 = eq(io.in.a.bits.source, source)
node _T_1017 = asUInt(reset)
node _T_1018 = eq(_T_1017, UInt<1>(0h0))
when _T_1018 :
node _T_1019 = eq(_T_1016, UInt<1>(0h0))
when _T_1019 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1016, UInt<1>(0h1), "") : assert_90
node _T_1020 = eq(io.in.a.bits.address, address)
node _T_1021 = asUInt(reset)
node _T_1022 = eq(_T_1021, UInt<1>(0h0))
when _T_1022 :
node _T_1023 = eq(_T_1020, UInt<1>(0h0))
when _T_1023 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1020, UInt<1>(0h1), "") : assert_91
node _T_1024 = and(io.in.a.ready, io.in.a.valid)
node _T_1025 = and(_T_1024, a_first)
when _T_1025 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1026 = eq(d_first, UInt<1>(0h0))
node _T_1027 = and(io.in.d.valid, _T_1026)
when _T_1027 :
node _T_1028 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1029 = asUInt(reset)
node _T_1030 = eq(_T_1029, UInt<1>(0h0))
when _T_1030 :
node _T_1031 = eq(_T_1028, UInt<1>(0h0))
when _T_1031 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1028, UInt<1>(0h1), "") : assert_92
node _T_1032 = eq(io.in.d.bits.param, param_1)
node _T_1033 = asUInt(reset)
node _T_1034 = eq(_T_1033, UInt<1>(0h0))
when _T_1034 :
node _T_1035 = eq(_T_1032, UInt<1>(0h0))
when _T_1035 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1032, UInt<1>(0h1), "") : assert_93
node _T_1036 = eq(io.in.d.bits.size, size_1)
node _T_1037 = asUInt(reset)
node _T_1038 = eq(_T_1037, UInt<1>(0h0))
when _T_1038 :
node _T_1039 = eq(_T_1036, UInt<1>(0h0))
when _T_1039 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1036, UInt<1>(0h1), "") : assert_94
node _T_1040 = eq(io.in.d.bits.source, source_1)
node _T_1041 = asUInt(reset)
node _T_1042 = eq(_T_1041, UInt<1>(0h0))
when _T_1042 :
node _T_1043 = eq(_T_1040, UInt<1>(0h0))
when _T_1043 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1040, UInt<1>(0h1), "") : assert_95
node _T_1044 = eq(io.in.d.bits.sink, sink)
node _T_1045 = asUInt(reset)
node _T_1046 = eq(_T_1045, UInt<1>(0h0))
when _T_1046 :
node _T_1047 = eq(_T_1044, UInt<1>(0h0))
when _T_1047 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1044, UInt<1>(0h1), "") : assert_96
node _T_1048 = eq(io.in.d.bits.denied, denied)
node _T_1049 = asUInt(reset)
node _T_1050 = eq(_T_1049, UInt<1>(0h0))
when _T_1050 :
node _T_1051 = eq(_T_1048, UInt<1>(0h0))
when _T_1051 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1048, UInt<1>(0h1), "") : assert_97
node _T_1052 = and(io.in.d.ready, io.in.d.valid)
node _T_1053 = and(_T_1052, d_first)
when _T_1053 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<65>
connect a_set, UInt<65>(0h0)
wire a_set_wo_ready : UInt<65>
connect a_set_wo_ready, UInt<65>(0h0)
wire a_opcodes_set : UInt<260>
connect a_opcodes_set, UInt<260>(0h0)
wire a_sizes_set : UInt<260>
connect a_sizes_set, UInt<260>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_1054 = and(io.in.a.valid, a_first_1)
node _T_1055 = and(_T_1054, UInt<1>(0h1))
when _T_1055 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1056 = and(io.in.a.ready, io.in.a.valid)
node _T_1057 = and(_T_1056, a_first_1)
node _T_1058 = and(_T_1057, UInt<1>(0h1))
when _T_1058 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1059 = dshr(inflight, io.in.a.bits.source)
node _T_1060 = bits(_T_1059, 0, 0)
node _T_1061 = eq(_T_1060, UInt<1>(0h0))
node _T_1062 = asUInt(reset)
node _T_1063 = eq(_T_1062, UInt<1>(0h0))
when _T_1063 :
node _T_1064 = eq(_T_1061, UInt<1>(0h0))
when _T_1064 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1061, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<65>
connect d_clr, UInt<65>(0h0)
wire d_clr_wo_ready : UInt<65>
connect d_clr_wo_ready, UInt<65>(0h0)
wire d_opcodes_clr : UInt<260>
connect d_opcodes_clr, UInt<260>(0h0)
wire d_sizes_clr : UInt<260>
connect d_sizes_clr, UInt<260>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1065 = and(io.in.d.valid, d_first_1)
node _T_1066 = and(_T_1065, UInt<1>(0h1))
node _T_1067 = eq(d_release_ack, UInt<1>(0h0))
node _T_1068 = and(_T_1066, _T_1067)
when _T_1068 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1069 = and(io.in.d.ready, io.in.d.valid)
node _T_1070 = and(_T_1069, d_first_1)
node _T_1071 = and(_T_1070, UInt<1>(0h1))
node _T_1072 = eq(d_release_ack, UInt<1>(0h0))
node _T_1073 = and(_T_1071, _T_1072)
when _T_1073 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1074 = and(io.in.d.valid, d_first_1)
node _T_1075 = and(_T_1074, UInt<1>(0h1))
node _T_1076 = eq(d_release_ack, UInt<1>(0h0))
node _T_1077 = and(_T_1075, _T_1076)
when _T_1077 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1078 = dshr(inflight, io.in.d.bits.source)
node _T_1079 = bits(_T_1078, 0, 0)
node _T_1080 = or(_T_1079, same_cycle_resp)
node _T_1081 = asUInt(reset)
node _T_1082 = eq(_T_1081, UInt<1>(0h0))
when _T_1082 :
node _T_1083 = eq(_T_1080, UInt<1>(0h0))
when _T_1083 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1080, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1084 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1085 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1086 = or(_T_1084, _T_1085)
node _T_1087 = asUInt(reset)
node _T_1088 = eq(_T_1087, UInt<1>(0h0))
when _T_1088 :
node _T_1089 = eq(_T_1086, UInt<1>(0h0))
when _T_1089 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1086, UInt<1>(0h1), "") : assert_100
node _T_1090 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1091 = asUInt(reset)
node _T_1092 = eq(_T_1091, UInt<1>(0h0))
when _T_1092 :
node _T_1093 = eq(_T_1090, UInt<1>(0h0))
when _T_1093 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1090, UInt<1>(0h1), "") : assert_101
else :
node _T_1094 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1095 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1096 = or(_T_1094, _T_1095)
node _T_1097 = asUInt(reset)
node _T_1098 = eq(_T_1097, UInt<1>(0h0))
when _T_1098 :
node _T_1099 = eq(_T_1096, UInt<1>(0h0))
when _T_1099 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1096, UInt<1>(0h1), "") : assert_102
node _T_1100 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1101 = asUInt(reset)
node _T_1102 = eq(_T_1101, UInt<1>(0h0))
when _T_1102 :
node _T_1103 = eq(_T_1100, UInt<1>(0h0))
when _T_1103 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1100, UInt<1>(0h1), "") : assert_103
node _T_1104 = and(io.in.d.valid, d_first_1)
node _T_1105 = and(_T_1104, a_first_1)
node _T_1106 = and(_T_1105, io.in.a.valid)
node _T_1107 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1108 = and(_T_1106, _T_1107)
node _T_1109 = eq(d_release_ack, UInt<1>(0h0))
node _T_1110 = and(_T_1108, _T_1109)
when _T_1110 :
node _T_1111 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1112 = or(_T_1111, io.in.a.ready)
node _T_1113 = asUInt(reset)
node _T_1114 = eq(_T_1113, UInt<1>(0h0))
when _T_1114 :
node _T_1115 = eq(_T_1112, UInt<1>(0h0))
when _T_1115 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1112, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_133
node _T_1116 = orr(inflight)
node _T_1117 = eq(_T_1116, UInt<1>(0h0))
node _T_1118 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1119 = or(_T_1117, _T_1118)
node _T_1120 = lt(watchdog, plusarg_reader.out)
node _T_1121 = or(_T_1119, _T_1120)
node _T_1122 = asUInt(reset)
node _T_1123 = eq(_T_1122, UInt<1>(0h0))
when _T_1123 :
node _T_1124 = eq(_T_1121, UInt<1>(0h0))
when _T_1124 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_1121, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1125 = and(io.in.a.ready, io.in.a.valid)
node _T_1126 = and(io.in.d.ready, io.in.d.valid)
node _T_1127 = or(_T_1125, _T_1126)
when _T_1127 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<14>(0h0)
connect _c_first_WIRE.bits.source, UInt<7>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<14>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<65>
connect c_set, UInt<65>(0h0)
wire c_set_wo_ready : UInt<65>
connect c_set_wo_ready, UInt<65>(0h0)
wire c_opcodes_set : UInt<260>
connect c_opcodes_set, UInt<260>(0h0)
wire c_sizes_set : UInt<260>
connect c_sizes_set, UInt<260>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<14>(0h0)
connect _WIRE_10.bits.source, UInt<7>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1128 = and(_WIRE_11.valid, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<14>(0h0)
connect _WIRE_12.bits.source, UInt<7>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1129 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1130 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1131 = and(_T_1129, _T_1130)
node _T_1132 = and(_T_1128, _T_1131)
when _T_1132 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<14>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<14>(0h0)
connect _WIRE_14.bits.source, UInt<7>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1133 = and(_WIRE_15.ready, _WIRE_15.valid)
node _T_1134 = and(_T_1133, c_first)
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<14>(0h0)
connect _WIRE_16.bits.source, UInt<7>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1135 = bits(_WIRE_17.bits.opcode, 2, 2)
node _T_1136 = bits(_WIRE_17.bits.opcode, 1, 1)
node _T_1137 = and(_T_1135, _T_1136)
node _T_1138 = and(_T_1134, _T_1137)
when _T_1138 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<14>(0h0)
connect _c_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<14>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<14>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<14>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<14>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<14>(0h0)
connect _WIRE_18.bits.source, UInt<7>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1139 = dshr(inflight_1, _WIRE_19.bits.source)
node _T_1140 = bits(_T_1139, 0, 0)
node _T_1141 = eq(_T_1140, UInt<1>(0h0))
node _T_1142 = asUInt(reset)
node _T_1143 = eq(_T_1142, UInt<1>(0h0))
when _T_1143 :
node _T_1144 = eq(_T_1141, UInt<1>(0h0))
when _T_1144 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1141, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<14>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<14>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<65>
connect d_clr_1, UInt<65>(0h0)
wire d_clr_wo_ready_1 : UInt<65>
connect d_clr_wo_ready_1, UInt<65>(0h0)
wire d_opcodes_clr_1 : UInt<260>
connect d_opcodes_clr_1, UInt<260>(0h0)
wire d_sizes_clr_1 : UInt<260>
connect d_sizes_clr_1, UInt<260>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1145 = and(io.in.d.valid, d_first_2)
node _T_1146 = and(_T_1145, UInt<1>(0h1))
node _T_1147 = and(_T_1146, d_release_ack_1)
when _T_1147 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1148 = and(io.in.d.ready, io.in.d.valid)
node _T_1149 = and(_T_1148, d_first_2)
node _T_1150 = and(_T_1149, UInt<1>(0h1))
node _T_1151 = and(_T_1150, d_release_ack_1)
when _T_1151 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1152 = and(io.in.d.valid, d_first_2)
node _T_1153 = and(_T_1152, UInt<1>(0h1))
node _T_1154 = and(_T_1153, d_release_ack_1)
when _T_1154 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<14>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<14>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<14>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1155 = dshr(inflight_1, io.in.d.bits.source)
node _T_1156 = bits(_T_1155, 0, 0)
node _T_1157 = or(_T_1156, same_cycle_resp_1)
node _T_1158 = asUInt(reset)
node _T_1159 = eq(_T_1158, UInt<1>(0h0))
when _T_1159 :
node _T_1160 = eq(_T_1157, UInt<1>(0h0))
when _T_1160 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_1157, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<14>(0h0)
connect _WIRE_20.bits.source, UInt<7>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1161 = eq(io.in.d.bits.size, _WIRE_21.bits.size)
node _T_1162 = asUInt(reset)
node _T_1163 = eq(_T_1162, UInt<1>(0h0))
when _T_1163 :
node _T_1164 = eq(_T_1161, UInt<1>(0h0))
when _T_1164 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1161, UInt<1>(0h1), "") : assert_108
else :
node _T_1165 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1166 = asUInt(reset)
node _T_1167 = eq(_T_1166, UInt<1>(0h0))
when _T_1167 :
node _T_1168 = eq(_T_1165, UInt<1>(0h0))
when _T_1168 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1165, UInt<1>(0h1), "") : assert_109
node _T_1169 = and(io.in.d.valid, d_first_2)
node _T_1170 = and(_T_1169, c_first)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<14>(0h0)
connect _WIRE_22.bits.source, UInt<7>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1171 = and(_T_1170, _WIRE_23.valid)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<14>(0h0)
connect _WIRE_24.bits.source, UInt<7>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1172 = eq(_WIRE_25.bits.source, io.in.d.bits.source)
node _T_1173 = and(_T_1171, _T_1172)
node _T_1174 = and(_T_1173, d_release_ack_1)
node _T_1175 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1176 = and(_T_1174, _T_1175)
when _T_1176 :
node _T_1177 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.address, UInt<14>(0h0)
connect _WIRE_26.bits.source, UInt<7>(0h0)
connect _WIRE_26.bits.size, UInt<3>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
node _T_1178 = or(_T_1177, _WIRE_27.ready)
node _T_1179 = asUInt(reset)
node _T_1180 = eq(_T_1179, UInt<1>(0h0))
when _T_1180 :
node _T_1181 = eq(_T_1178, UInt<1>(0h0))
when _T_1181 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1178, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_134
node _T_1182 = orr(inflight_1)
node _T_1183 = eq(_T_1182, UInt<1>(0h0))
node _T_1184 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1185 = or(_T_1183, _T_1184)
node _T_1186 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1187 = or(_T_1185, _T_1186)
node _T_1188 = asUInt(reset)
node _T_1189 = eq(_T_1188, UInt<1>(0h0))
when _T_1189 :
node _T_1190 = eq(_T_1187, UInt<1>(0h0))
when _T_1190 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala:137:157)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_1187, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.address, UInt<14>(0h0)
connect _WIRE_28.bits.source, UInt<7>(0h0)
connect _WIRE_28.bits.size, UInt<3>(0h0)
connect _WIRE_28.bits.param, UInt<3>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
node _T_1191 = and(_WIRE_29.ready, _WIRE_29.valid)
node _T_1192 = and(io.in.d.ready, io.in.d.valid)
node _T_1193 = or(_T_1191, _T_1192)
when _T_1193 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_65( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [13:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [13:0] address; // @[Monitor.scala:391:22]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg [64:0] inflight; // @[Monitor.scala:614:27]
reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [259:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _GEN_0 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [64:0] inflight_1; // @[Monitor.scala:726:35]
reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module PE_324 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>}
inst mac_unit of MacUnit_68
connect mac_unit.clock, clock
connect mac_unit.reset, reset
reg c1 : SInt<8>, clock
reg c2 : SInt<8>, clock
connect io.out_a, io.in_a
connect io.out_control.dataflow, io.in_control.dataflow
connect io.out_control.propagate, io.in_control.propagate
connect io.out_control.shift, io.in_control.shift
connect io.out_id, io.in_id
connect io.out_last, io.in_last
connect io.out_valid, io.in_valid
connect mac_unit.io.in_a, io.in_a
reg last_s : UInt<1>, clock
when io.in_valid :
connect last_s, io.in_control.propagate
node flip = neq(last_s, io.in_control.propagate)
node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0))
connect io.bad_dataflow, UInt<1>(0h0)
node _T = eq(io.in_control.dataflow, UInt<1>(0h0))
node _T_1 = and(UInt<1>(0h0), _T)
node _T_2 = or(UInt<1>(0h0), _T_1)
when _T_2 :
node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_3 :
node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1)
node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2)
node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0)
node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4)
node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_1 = asUInt(c1)
node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1)
node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3)
node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1))
node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1)
node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6)
node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7)
node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0))
node _io_out_c_ones_digit_T = dshr(c1, shift_offset)
node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0)
node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit)
node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T)
node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0)
node _io_out_c_T = dshr(c1, shift_offset)
node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1)
node _io_out_c_T_3 = tail(_io_out_c_T_2, 1)
node _io_out_c_T_4 = asSInt(_io_out_c_T_3)
node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4)
node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7)
node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0)
node _io_out_c_T_10 = asSInt(_io_out_c_T_9)
connect io.out_c, _io_out_c_T_10
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE : SInt<8>
node _mac_unit_io_in_b_T = asUInt(io.in_b)
node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T)
connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE
connect mac_unit.io.in_c, c2
connect c2, mac_unit.io.out_d
node _c1_T = bits(io.in_d, 7, 0)
node _c1_T_1 = asSInt(_c1_T)
connect c1, _c1_T_1
else :
node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1)
node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7)
node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0)
node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9)
node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_10 = asUInt(c2)
node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1)
node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12)
node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1))
node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1)
node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15)
node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16)
node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0))
node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset)
node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0)
node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1)
node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2)
node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0)
node _io_out_c_T_11 = dshr(c2, shift_offset)
node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12)
node _io_out_c_T_14 = tail(_io_out_c_T_13, 1)
node _io_out_c_T_15 = asSInt(_io_out_c_T_14)
node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15)
node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18)
node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0)
node _io_out_c_T_21 = asSInt(_io_out_c_T_20)
connect io.out_c, _io_out_c_T_21
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE_1 : SInt<8>
node _mac_unit_io_in_b_T_2 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2)
connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1
connect mac_unit.io.in_c, c1
connect c1, mac_unit.io.out_d
node _c2_T = bits(io.in_d, 7, 0)
node _c2_T_1 = asSInt(_c2_T)
connect c2, _c2_T_1
else :
node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1))
node _T_5 = and(UInt<1>(0h0), _T_4)
node _T_6 = or(UInt<1>(0h1), _T_5)
when _T_6 :
node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_7 :
connect io.out_c, c1
wire _mac_unit_io_in_b_WIRE_2 : SInt<8>
node _mac_unit_io_in_b_T_4 = asUInt(c2)
node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4)
connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c1, io.in_d
else :
connect io.out_c, c2
wire _mac_unit_io_in_b_WIRE_3 : SInt<8>
node _mac_unit_io_in_b_T_6 = asUInt(c1)
node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6)
connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c2, io.in_d
else :
connect io.bad_dataflow, UInt<1>(0h1)
invalidate io.out_c
invalidate io.out_b
wire _mac_unit_io_in_b_WIRE_4 : SInt<8>
node _mac_unit_io_in_b_T_8 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8)
connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4
connect mac_unit.io.in_c, c2
node _T_8 = eq(io.in_valid, UInt<1>(0h0))
when _T_8 :
connect c1, c1
connect c2, c2
invalidate mac_unit.io.in_b
invalidate mac_unit.io.in_c | module PE_324( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid // @[PE.scala:35:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7]
wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60]
wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [7:0] c1; // @[PE.scala:70:15]
wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [7:0] c2; // @[PE.scala:71:15]
wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25]
wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}]
wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16]
wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8]
c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15]
if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8]
c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15]
if (io_in_valid_0) // @[PE.scala:31:7]
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
always @(posedge)
MacUnit_68 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_b_0), // @[PE.scala:31:7]
.io_out_d (io_out_b_0)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_8 :
input clock : Clock
input reset : Reset
output auto : { }
skip | module TLBuffer_8( // @[Buffer.scala:40:9]
input clock, // @[Buffer.scala:40:9]
input reset // @[Buffer.scala:40:9]
);
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_130 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_sink_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_145
connect io_out_sink_extend.clock, clock
connect io_out_sink_extend.reset, reset
connect io_out_sink_extend.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_sink_extend.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_130( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_145 io_out_sink_extend ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_35 :
output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0))
node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1))
node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2))
node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3))
node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4))
node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6))
node _roundMagUp_T = and(roundingMode_min, io.in.sign)
node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0))
node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1)
node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2)
node adjustedSig = shl(io.in.sig, 0)
node doShiftSigDown1 = bits(adjustedSig, 26, 26)
wire common_expOut : UInt<9>
wire common_fractOut : UInt<23>
wire common_overflow : UInt<1>
wire common_totalUnderflow : UInt<1>
wire common_underflow : UInt<1>
wire common_inexact : UInt<1>
node _roundMask_T = bits(io.in.sExp, 8, 0)
node _roundMask_T_1 = not(_roundMask_T)
node roundMask_msb = bits(_roundMask_T_1, 8, 8)
node roundMask_lsbs = bits(_roundMask_T_1, 7, 0)
node roundMask_msb_1 = bits(roundMask_lsbs, 7, 7)
node roundMask_lsbs_1 = bits(roundMask_lsbs, 6, 0)
node roundMask_msb_2 = bits(roundMask_lsbs_1, 6, 6)
node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 5, 0)
node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_2)
node _roundMask_T_2 = bits(roundMask_shift, 63, 42)
node _roundMask_T_3 = bits(_roundMask_T_2, 15, 0)
node _roundMask_T_4 = shl(UInt<8>(0hff), 8)
node _roundMask_T_5 = xor(UInt<16>(0hffff), _roundMask_T_4)
node _roundMask_T_6 = shr(_roundMask_T_3, 8)
node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5)
node _roundMask_T_8 = bits(_roundMask_T_3, 7, 0)
node _roundMask_T_9 = shl(_roundMask_T_8, 8)
node _roundMask_T_10 = not(_roundMask_T_5)
node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10)
node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11)
node _roundMask_T_13 = bits(_roundMask_T_5, 11, 0)
node _roundMask_T_14 = shl(_roundMask_T_13, 4)
node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14)
node _roundMask_T_16 = shr(_roundMask_T_12, 4)
node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15)
node _roundMask_T_18 = bits(_roundMask_T_12, 11, 0)
node _roundMask_T_19 = shl(_roundMask_T_18, 4)
node _roundMask_T_20 = not(_roundMask_T_15)
node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20)
node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21)
node _roundMask_T_23 = bits(_roundMask_T_15, 13, 0)
node _roundMask_T_24 = shl(_roundMask_T_23, 2)
node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24)
node _roundMask_T_26 = shr(_roundMask_T_22, 2)
node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25)
node _roundMask_T_28 = bits(_roundMask_T_22, 13, 0)
node _roundMask_T_29 = shl(_roundMask_T_28, 2)
node _roundMask_T_30 = not(_roundMask_T_25)
node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30)
node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31)
node _roundMask_T_33 = bits(_roundMask_T_25, 14, 0)
node _roundMask_T_34 = shl(_roundMask_T_33, 1)
node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34)
node _roundMask_T_36 = shr(_roundMask_T_32, 1)
node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35)
node _roundMask_T_38 = bits(_roundMask_T_32, 14, 0)
node _roundMask_T_39 = shl(_roundMask_T_38, 1)
node _roundMask_T_40 = not(_roundMask_T_35)
node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40)
node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41)
node _roundMask_T_43 = bits(_roundMask_T_2, 21, 16)
node _roundMask_T_44 = bits(_roundMask_T_43, 3, 0)
node _roundMask_T_45 = bits(_roundMask_T_44, 1, 0)
node _roundMask_T_46 = bits(_roundMask_T_45, 0, 0)
node _roundMask_T_47 = bits(_roundMask_T_45, 1, 1)
node _roundMask_T_48 = cat(_roundMask_T_46, _roundMask_T_47)
node _roundMask_T_49 = bits(_roundMask_T_44, 3, 2)
node _roundMask_T_50 = bits(_roundMask_T_49, 0, 0)
node _roundMask_T_51 = bits(_roundMask_T_49, 1, 1)
node _roundMask_T_52 = cat(_roundMask_T_50, _roundMask_T_51)
node _roundMask_T_53 = cat(_roundMask_T_48, _roundMask_T_52)
node _roundMask_T_54 = bits(_roundMask_T_43, 5, 4)
node _roundMask_T_55 = bits(_roundMask_T_54, 0, 0)
node _roundMask_T_56 = bits(_roundMask_T_54, 1, 1)
node _roundMask_T_57 = cat(_roundMask_T_55, _roundMask_T_56)
node _roundMask_T_58 = cat(_roundMask_T_53, _roundMask_T_57)
node _roundMask_T_59 = cat(_roundMask_T_42, _roundMask_T_58)
node _roundMask_T_60 = not(_roundMask_T_59)
node _roundMask_T_61 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_60)
node _roundMask_T_62 = not(_roundMask_T_61)
node _roundMask_T_63 = cat(_roundMask_T_62, UInt<3>(0h7))
node roundMask_msb_3 = bits(roundMask_lsbs_1, 6, 6)
node roundMask_lsbs_3 = bits(roundMask_lsbs_1, 5, 0)
node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_3)
node _roundMask_T_64 = bits(roundMask_shift_1, 2, 0)
node _roundMask_T_65 = bits(_roundMask_T_64, 1, 0)
node _roundMask_T_66 = bits(_roundMask_T_65, 0, 0)
node _roundMask_T_67 = bits(_roundMask_T_65, 1, 1)
node _roundMask_T_68 = cat(_roundMask_T_66, _roundMask_T_67)
node _roundMask_T_69 = bits(_roundMask_T_64, 2, 2)
node _roundMask_T_70 = cat(_roundMask_T_68, _roundMask_T_69)
node _roundMask_T_71 = mux(roundMask_msb_3, _roundMask_T_70, UInt<1>(0h0))
node _roundMask_T_72 = mux(roundMask_msb_1, _roundMask_T_63, _roundMask_T_71)
node _roundMask_T_73 = mux(roundMask_msb, _roundMask_T_72, UInt<1>(0h0))
node _roundMask_T_74 = or(_roundMask_T_73, doShiftSigDown1)
node roundMask = cat(_roundMask_T_74, UInt<2>(0h3))
node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask)
node shiftedRoundMask = shr(_shiftedRoundMask_T, 1)
node _roundPosMask_T = not(shiftedRoundMask)
node roundPosMask = and(_roundPosMask_T, roundMask)
node _roundPosBit_T = and(adjustedSig, roundPosMask)
node roundPosBit = orr(_roundPosBit_T)
node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask)
node anyRoundExtra = orr(_anyRoundExtra_T)
node anyRound = or(roundPosBit, anyRoundExtra)
node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit)
node _roundIncr_T_2 = and(roundMagUp, anyRound)
node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2)
node _roundedSig_T = or(adjustedSig, roundMask)
node _roundedSig_T_1 = shr(_roundedSig_T, 2)
node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1))
node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit)
node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0))
node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4)
node _roundedSig_T_6 = shr(roundMask, 1)
node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0))
node _roundedSig_T_8 = not(_roundedSig_T_7)
node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8)
node _roundedSig_T_10 = not(roundMask)
node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10)
node _roundedSig_T_12 = shr(_roundedSig_T_11, 2)
node _roundedSig_T_13 = and(roundingMode_odd, anyRound)
node _roundedSig_T_14 = shr(roundPosMask, 1)
node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0))
node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15)
node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16)
node _sRoundedExp_T = shr(roundedSig, 24)
node _sRoundedExp_T_1 = cvt(_sRoundedExp_T)
node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1)
node _common_expOut_T = bits(sRoundedExp, 8, 0)
connect common_expOut, _common_expOut_T
node _common_fractOut_T = bits(roundedSig, 23, 1)
node _common_fractOut_T_1 = bits(roundedSig, 22, 0)
node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1)
connect common_fractOut, _common_fractOut_T_2
node _common_overflow_T = shr(sRoundedExp, 7)
node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3)))
connect common_overflow, _common_overflow_T_1
node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<8>(0h6b)))
connect common_totalUnderflow, _common_totalUnderflow_T
node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2)
node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1)
node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1)
node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2)
node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T)
node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0)
node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2)
node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3)
node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit)
node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound)
node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2)
node _roundCarry_T = bits(roundedSig, 25, 25)
node _roundCarry_T_1 = bits(roundedSig, 24, 24)
node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1)
node _common_underflow_T = shr(io.in.sExp, 8)
node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0)))
node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1)
node _common_underflow_T_3 = bits(roundMask, 3, 3)
node _common_underflow_T_4 = bits(roundMask, 2, 2)
node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4)
node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5)
node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1))
node _common_underflow_T_8 = bits(roundMask, 4, 4)
node _common_underflow_T_9 = bits(roundMask, 3, 3)
node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9)
node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0))
node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11)
node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry)
node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit)
node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr)
node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0))
node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16)
node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17)
connect common_underflow, _common_underflow_T_18
node _common_inexact_T = or(common_totalUnderflow, anyRound)
connect common_inexact, _common_inexact_T
node isNaNOut = or(io.invalidExc, io.in.isNaN)
node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf)
node _commonCase_T = eq(isNaNOut, UInt<1>(0h0))
node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0))
node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1)
node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0))
node commonCase = and(_commonCase_T_2, _commonCase_T_3)
node overflow = and(commonCase, common_overflow)
node underflow = and(commonCase, common_underflow)
node _inexact_T = and(commonCase, common_inexact)
node inexact = or(overflow, _inexact_T)
node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp)
node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow)
node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd)
node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1)
node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0))
node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T)
node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp)
node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T)
node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign)
node _expOut_T = or(io.in.isZero, common_totalUnderflow)
node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0))
node _expOut_T_2 = not(_expOut_T_1)
node _expOut_T_3 = and(common_expOut, _expOut_T_2)
node _expOut_T_4 = not(UInt<9>(0h6b))
node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0))
node _expOut_T_6 = not(_expOut_T_5)
node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6)
node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0))
node _expOut_T_9 = not(_expOut_T_8)
node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9)
node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0))
node _expOut_T_12 = not(_expOut_T_11)
node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12)
node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0))
node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14)
node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0))
node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16)
node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0))
node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18)
node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0))
node expOut = or(_expOut_T_19, _expOut_T_20)
node _fractOut_T = or(isNaNOut, io.in.isZero)
node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow)
node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0))
node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut)
node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0))
node fractOut = or(_fractOut_T_3, _fractOut_T_4)
node _io_out_T = cat(signOut, expOut)
node _io_out_T_1 = cat(_io_out_T, fractOut)
connect io.out, _io_out_T_1
node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc)
node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow)
node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact)
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_35( // @[RoundAnyRawFNToRecFN.scala:48:5]
input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16]
);
wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19]
wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20]
wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24]
wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14]
wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14]
wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18]
wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18]
wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16]
wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16]
wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:284:13]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53]
wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38]
wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38]
wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49]
wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32]
wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60]
wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53]
wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53]
wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53]
wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53]
wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53]
wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27]
wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63]
wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42]
wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29]
wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42]
wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29]
wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60]
wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45]
wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42]
wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39]
wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49]
wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22]
wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33]
wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66]
wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66]
wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57]
wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37]
wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31]
wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16]
wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31]
wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50]
wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37]
wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31]
wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37]
wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40]
wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37]
wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49]
wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37]
wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37]
wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21]
wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25]
wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26]
wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26]
wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26]
wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26]
wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26]
wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26]
wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26]
wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56]
wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22]
wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22]
wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_42 = _roundMask_T_37 | _roundMask_T_41; // @[primitives.scala:77:20]
wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22]
wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20]
wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20]
wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20]
wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20]
wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20]
wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20]
wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20]
wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20]
wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20]
wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20]
wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20]
wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}]
wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}]
wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17]
wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56]
wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22]
wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22]
wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20]
wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20]
wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22]
wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20]
wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20]
wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58]
wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24]
wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] | doShiftSigDown1}; // @[primitives.scala:62:24]
wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}]
wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41]
wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}]
wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28]
wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}]
wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40]
wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}]
wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67]
wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49]
wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42]
wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}]
wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36]
wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31]
wire [26:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32]
wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}]
wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}]
wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30]
wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30]
wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35]
wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35]
wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}]
wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21]
wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32]
wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}]
wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}]
wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67]
wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}]
wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47]
wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54]
wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}]
wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}]
assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37]
assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37]
wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27]
wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27]
assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27]
assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16]
wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30]
assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}]
assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50]
assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31]
assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31]
wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45]
wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44]
wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61]
wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}]
wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67]
wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}]
wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63]
wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}]
wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 | _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}]
wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46]
wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27]
wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27]
wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27]
wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49]
wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}]
wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}]
wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57]
wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49]
wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71]
wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}]
wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30]
wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49]
wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49]
wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}]
wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34]
wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38]
wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45]
wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}]
wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60]
wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27]
assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76]
assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40]
assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49]
assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49]
wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34]
wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22]
wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36]
wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}]
wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64]
wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}]
wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32]
wire _notNaN_isInfOut_T = overflow; // @[RoundAnyRawFNToRecFN.scala:238:32, :248:45]
wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32]
wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43]
wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}]
wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20]
wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}]
wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22]
wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32]
wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}]
wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}]
wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14]
wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17]
wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17]
wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18]
wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}]
wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14]
wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18]
wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15]
wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16]
wire [8:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16]
wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16]
wire [8:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16]
wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22]
wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}]
wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16]
wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16]
wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11]
wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23]
assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}]
assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33]
wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23]
wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}]
wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}]
assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PE_111 :
input clock : Clock
input reset : Reset
output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>}
node _reg_T = eq(io.dir, UInt<1>(0h0))
node _reg_T_1 = mux(_reg_T, io.inR, io.inD)
reg reg : SInt<8>, clock
when io.en :
connect reg, _reg_T_1
connect io.outU, reg
connect io.outL, reg | module PE_111( // @[Transposer.scala:100:9]
input clock, // @[Transposer.scala:100:9]
input reset, // @[Transposer.scala:100:9]
input [7:0] io_inR, // @[Transposer.scala:101:16]
input [7:0] io_inD, // @[Transposer.scala:101:16]
output [7:0] io_outL, // @[Transposer.scala:101:16]
output [7:0] io_outU, // @[Transposer.scala:101:16]
input io_dir, // @[Transposer.scala:101:16]
input io_en // @[Transposer.scala:101:16]
);
wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9]
wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9]
wire io_dir_0 = io_dir; // @[Transposer.scala:100:9]
wire io_en_0 = io_en; // @[Transposer.scala:100:9]
wire [7:0] io_outL_0; // @[Transposer.scala:100:9]
wire [7:0] io_outU_0; // @[Transposer.scala:100:9]
wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36]
wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}]
reg [7:0] reg_0; // @[Transposer.scala:110:24]
assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
always @(posedge clock) begin // @[Transposer.scala:100:9]
if (io_en_0) // @[Transposer.scala:100:9]
reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}]
always @(posedge)
assign io_outL = io_outL_0; // @[Transposer.scala:100:9]
assign io_outU = io_outU_0; // @[Transposer.scala:100:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLInterconnectCoupler_cbus_to_prci_ctrl :
input clock : Clock
input reset : Reset
output auto : { fixer_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip tl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
inst fixer of TLFIFOFixer_4
connect fixer.clock, clock
connect fixer.reset, reset
inst buffer of TLBuffer_a21d64s8k1z3u
connect buffer.clock, clock
connect buffer.reset, reset
wire tlOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate tlOut.d.bits.corrupt
invalidate tlOut.d.bits.data
invalidate tlOut.d.bits.denied
invalidate tlOut.d.bits.sink
invalidate tlOut.d.bits.source
invalidate tlOut.d.bits.size
invalidate tlOut.d.bits.param
invalidate tlOut.d.bits.opcode
invalidate tlOut.d.valid
invalidate tlOut.d.ready
invalidate tlOut.a.bits.corrupt
invalidate tlOut.a.bits.data
invalidate tlOut.a.bits.mask
invalidate tlOut.a.bits.address
invalidate tlOut.a.bits.source
invalidate tlOut.a.bits.size
invalidate tlOut.a.bits.param
invalidate tlOut.a.bits.opcode
invalidate tlOut.a.valid
invalidate tlOut.a.ready
wire tlIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate tlIn.d.bits.corrupt
invalidate tlIn.d.bits.data
invalidate tlIn.d.bits.denied
invalidate tlIn.d.bits.sink
invalidate tlIn.d.bits.source
invalidate tlIn.d.bits.size
invalidate tlIn.d.bits.param
invalidate tlIn.d.bits.opcode
invalidate tlIn.d.valid
invalidate tlIn.d.ready
invalidate tlIn.a.bits.corrupt
invalidate tlIn.a.bits.data
invalidate tlIn.a.bits.mask
invalidate tlIn.a.bits.address
invalidate tlIn.a.bits.source
invalidate tlIn.a.bits.size
invalidate tlIn.a.bits.param
invalidate tlIn.a.bits.opcode
invalidate tlIn.a.valid
invalidate tlIn.a.ready
connect tlOut, tlIn
connect buffer.auto.in, tlOut
connect fixer.auto.anon_in, buffer.auto.out
connect tlIn, auto.tl_in
connect fixer.auto.anon_out.d, auto.fixer_anon_out.d
connect auto.fixer_anon_out.a.bits, fixer.auto.anon_out.a.bits
connect auto.fixer_anon_out.a.valid, fixer.auto.anon_out.a.valid
connect fixer.auto.anon_out.a.ready, auto.fixer_anon_out.a.ready | module TLInterconnectCoupler_cbus_to_prci_ctrl( // @[LazyModuleImp.scala:138:7]
input clock, // @[LazyModuleImp.scala:138:7]
input reset, // @[LazyModuleImp.scala:138:7]
input auto_fixer_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_fixer_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_fixer_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_fixer_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_fixer_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_fixer_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [20:0] auto_fixer_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_fixer_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_fixer_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_fixer_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_fixer_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_fixer_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_fixer_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_fixer_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_fixer_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_fixer_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [20:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_tl_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_tl_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_tl_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_tl_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_tl_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_tl_in_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire tlOut_d_valid; // @[MixedNode.scala:542:17]
wire tlOut_d_bits_corrupt; // @[MixedNode.scala:542:17]
wire [63:0] tlOut_d_bits_data; // @[MixedNode.scala:542:17]
wire tlOut_d_bits_denied; // @[MixedNode.scala:542:17]
wire tlOut_d_bits_sink; // @[MixedNode.scala:542:17]
wire [7:0] tlOut_d_bits_source; // @[MixedNode.scala:542:17]
wire [2:0] tlOut_d_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] tlOut_d_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] tlOut_d_bits_opcode; // @[MixedNode.scala:542:17]
wire tlOut_a_ready; // @[MixedNode.scala:542:17]
wire _buffer_auto_out_a_valid; // @[Buffer.scala:75:28]
wire [2:0] _buffer_auto_out_a_bits_opcode; // @[Buffer.scala:75:28]
wire [2:0] _buffer_auto_out_a_bits_param; // @[Buffer.scala:75:28]
wire [2:0] _buffer_auto_out_a_bits_size; // @[Buffer.scala:75:28]
wire [7:0] _buffer_auto_out_a_bits_source; // @[Buffer.scala:75:28]
wire [20:0] _buffer_auto_out_a_bits_address; // @[Buffer.scala:75:28]
wire [7:0] _buffer_auto_out_a_bits_mask; // @[Buffer.scala:75:28]
wire [63:0] _buffer_auto_out_a_bits_data; // @[Buffer.scala:75:28]
wire _buffer_auto_out_a_bits_corrupt; // @[Buffer.scala:75:28]
wire _buffer_auto_out_d_ready; // @[Buffer.scala:75:28]
wire _fixer_auto_anon_in_a_ready; // @[FIFOFixer.scala:152:27]
wire _fixer_auto_anon_in_d_valid; // @[FIFOFixer.scala:152:27]
wire [2:0] _fixer_auto_anon_in_d_bits_opcode; // @[FIFOFixer.scala:152:27]
wire [2:0] _fixer_auto_anon_in_d_bits_size; // @[FIFOFixer.scala:152:27]
wire [7:0] _fixer_auto_anon_in_d_bits_source; // @[FIFOFixer.scala:152:27]
wire [63:0] _fixer_auto_anon_in_d_bits_data; // @[FIFOFixer.scala:152:27]
wire auto_fixer_anon_out_a_ready_0 = auto_fixer_anon_out_a_ready; // @[LazyModuleImp.scala:138:7]
wire auto_fixer_anon_out_d_valid_0 = auto_fixer_anon_out_d_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_fixer_anon_out_d_bits_opcode_0 = auto_fixer_anon_out_d_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_fixer_anon_out_d_bits_size_0 = auto_fixer_anon_out_d_bits_size; // @[LazyModuleImp.scala:138:7]
wire [7:0] auto_fixer_anon_out_d_bits_source_0 = auto_fixer_anon_out_d_bits_source; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_fixer_anon_out_d_bits_data_0 = auto_fixer_anon_out_d_bits_data; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_a_valid_0 = auto_tl_in_a_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_in_a_bits_opcode_0 = auto_tl_in_a_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_in_a_bits_param_0 = auto_tl_in_a_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_in_a_bits_size_0 = auto_tl_in_a_bits_size; // @[LazyModuleImp.scala:138:7]
wire [7:0] auto_tl_in_a_bits_source_0 = auto_tl_in_a_bits_source; // @[LazyModuleImp.scala:138:7]
wire [20:0] auto_tl_in_a_bits_address_0 = auto_tl_in_a_bits_address; // @[LazyModuleImp.scala:138:7]
wire [7:0] auto_tl_in_a_bits_mask_0 = auto_tl_in_a_bits_mask; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_tl_in_a_bits_data_0 = auto_tl_in_a_bits_data; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_a_bits_corrupt_0 = auto_tl_in_a_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_d_ready_0 = auto_tl_in_d_ready; // @[LazyModuleImp.scala:138:7]
wire auto_fixer_anon_out_d_bits_sink = 1'h0; // @[FIFOFixer.scala:152:27]
wire auto_fixer_anon_out_d_bits_denied = 1'h0; // @[FIFOFixer.scala:152:27]
wire auto_fixer_anon_out_d_bits_corrupt = 1'h0; // @[FIFOFixer.scala:152:27]
wire [1:0] auto_fixer_anon_out_d_bits_param = 2'h0; // @[FIFOFixer.scala:152:27]
wire tlIn_a_ready; // @[MixedNode.scala:551:17]
wire tlIn_a_valid = auto_tl_in_a_valid_0; // @[MixedNode.scala:551:17]
wire [2:0] tlIn_a_bits_opcode = auto_tl_in_a_bits_opcode_0; // @[MixedNode.scala:551:17]
wire [2:0] tlIn_a_bits_param = auto_tl_in_a_bits_param_0; // @[MixedNode.scala:551:17]
wire [2:0] tlIn_a_bits_size = auto_tl_in_a_bits_size_0; // @[MixedNode.scala:551:17]
wire [7:0] tlIn_a_bits_source = auto_tl_in_a_bits_source_0; // @[MixedNode.scala:551:17]
wire [20:0] tlIn_a_bits_address = auto_tl_in_a_bits_address_0; // @[MixedNode.scala:551:17]
wire [7:0] tlIn_a_bits_mask = auto_tl_in_a_bits_mask_0; // @[MixedNode.scala:551:17]
wire [63:0] tlIn_a_bits_data = auto_tl_in_a_bits_data_0; // @[MixedNode.scala:551:17]
wire tlIn_a_bits_corrupt = auto_tl_in_a_bits_corrupt_0; // @[MixedNode.scala:551:17]
wire tlIn_d_ready = auto_tl_in_d_ready_0; // @[MixedNode.scala:551:17]
wire tlIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] tlIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] tlIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] tlIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [7:0] tlIn_d_bits_source; // @[MixedNode.scala:551:17]
wire tlIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire tlIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] tlIn_d_bits_data; // @[MixedNode.scala:551:17]
wire tlIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire [2:0] auto_fixer_anon_out_a_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_fixer_anon_out_a_bits_param_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_fixer_anon_out_a_bits_size_0; // @[LazyModuleImp.scala:138:7]
wire [7:0] auto_fixer_anon_out_a_bits_source_0; // @[LazyModuleImp.scala:138:7]
wire [20:0] auto_fixer_anon_out_a_bits_address_0; // @[LazyModuleImp.scala:138:7]
wire [7:0] auto_fixer_anon_out_a_bits_mask_0; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_fixer_anon_out_a_bits_data_0; // @[LazyModuleImp.scala:138:7]
wire auto_fixer_anon_out_a_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
wire auto_fixer_anon_out_a_valid_0; // @[LazyModuleImp.scala:138:7]
wire auto_fixer_anon_out_d_ready_0; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_a_ready_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
wire [1:0] auto_tl_in_d_bits_param_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7]
wire [7:0] auto_tl_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_d_bits_sink_0; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_d_bits_denied_0; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_tl_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_d_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_d_valid_0; // @[LazyModuleImp.scala:138:7]
assign tlIn_a_ready = tlOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign tlIn_d_valid = tlOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlIn_d_bits_opcode = tlOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign tlIn_d_bits_param = tlOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign tlIn_d_bits_size = tlOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign tlIn_d_bits_source = tlOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign tlIn_d_bits_sink = tlOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign tlIn_d_bits_denied = tlOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign tlIn_d_bits_data = tlOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] tlOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] tlOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] tlOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [7:0] tlOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [20:0] tlOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] tlOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] tlOut_a_bits_data; // @[MixedNode.scala:542:17]
wire tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign tlIn_d_bits_corrupt = tlOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire tlOut_a_valid; // @[MixedNode.scala:542:17]
wire tlOut_d_ready; // @[MixedNode.scala:542:17]
assign auto_tl_in_a_ready_0 = tlIn_a_ready; // @[MixedNode.scala:551:17]
assign tlOut_a_valid = tlIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_opcode = tlIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_param = tlIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_size = tlIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_source = tlIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_address = tlIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_mask = tlIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_data = tlIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_corrupt = tlIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_d_ready = tlIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_tl_in_d_valid_0 = tlIn_d_valid; // @[MixedNode.scala:551:17]
assign auto_tl_in_d_bits_opcode_0 = tlIn_d_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_tl_in_d_bits_param_0 = tlIn_d_bits_param; // @[MixedNode.scala:551:17]
assign auto_tl_in_d_bits_size_0 = tlIn_d_bits_size; // @[MixedNode.scala:551:17]
assign auto_tl_in_d_bits_source_0 = tlIn_d_bits_source; // @[MixedNode.scala:551:17]
assign auto_tl_in_d_bits_sink_0 = tlIn_d_bits_sink; // @[MixedNode.scala:551:17]
assign auto_tl_in_d_bits_denied_0 = tlIn_d_bits_denied; // @[MixedNode.scala:551:17]
assign auto_tl_in_d_bits_data_0 = tlIn_d_bits_data; // @[MixedNode.scala:551:17]
assign auto_tl_in_d_bits_corrupt_0 = tlIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
TLFIFOFixer_4 fixer ( // @[FIFOFixer.scala:152:27]
.clock (clock),
.reset (reset),
.auto_anon_in_a_ready (_fixer_auto_anon_in_a_ready),
.auto_anon_in_a_valid (_buffer_auto_out_a_valid), // @[Buffer.scala:75:28]
.auto_anon_in_a_bits_opcode (_buffer_auto_out_a_bits_opcode), // @[Buffer.scala:75:28]
.auto_anon_in_a_bits_param (_buffer_auto_out_a_bits_param), // @[Buffer.scala:75:28]
.auto_anon_in_a_bits_size (_buffer_auto_out_a_bits_size), // @[Buffer.scala:75:28]
.auto_anon_in_a_bits_source (_buffer_auto_out_a_bits_source), // @[Buffer.scala:75:28]
.auto_anon_in_a_bits_address (_buffer_auto_out_a_bits_address), // @[Buffer.scala:75:28]
.auto_anon_in_a_bits_mask (_buffer_auto_out_a_bits_mask), // @[Buffer.scala:75:28]
.auto_anon_in_a_bits_data (_buffer_auto_out_a_bits_data), // @[Buffer.scala:75:28]
.auto_anon_in_a_bits_corrupt (_buffer_auto_out_a_bits_corrupt), // @[Buffer.scala:75:28]
.auto_anon_in_d_ready (_buffer_auto_out_d_ready), // @[Buffer.scala:75:28]
.auto_anon_in_d_valid (_fixer_auto_anon_in_d_valid),
.auto_anon_in_d_bits_opcode (_fixer_auto_anon_in_d_bits_opcode),
.auto_anon_in_d_bits_size (_fixer_auto_anon_in_d_bits_size),
.auto_anon_in_d_bits_source (_fixer_auto_anon_in_d_bits_source),
.auto_anon_in_d_bits_data (_fixer_auto_anon_in_d_bits_data),
.auto_anon_out_a_ready (auto_fixer_anon_out_a_ready_0), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_a_valid (auto_fixer_anon_out_a_valid_0),
.auto_anon_out_a_bits_opcode (auto_fixer_anon_out_a_bits_opcode_0),
.auto_anon_out_a_bits_param (auto_fixer_anon_out_a_bits_param_0),
.auto_anon_out_a_bits_size (auto_fixer_anon_out_a_bits_size_0),
.auto_anon_out_a_bits_source (auto_fixer_anon_out_a_bits_source_0),
.auto_anon_out_a_bits_address (auto_fixer_anon_out_a_bits_address_0),
.auto_anon_out_a_bits_mask (auto_fixer_anon_out_a_bits_mask_0),
.auto_anon_out_a_bits_data (auto_fixer_anon_out_a_bits_data_0),
.auto_anon_out_a_bits_corrupt (auto_fixer_anon_out_a_bits_corrupt_0),
.auto_anon_out_d_ready (auto_fixer_anon_out_d_ready_0),
.auto_anon_out_d_valid (auto_fixer_anon_out_d_valid_0), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_d_bits_opcode (auto_fixer_anon_out_d_bits_opcode_0), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_d_bits_size (auto_fixer_anon_out_d_bits_size_0), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_d_bits_source (auto_fixer_anon_out_d_bits_source_0), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_d_bits_data (auto_fixer_anon_out_d_bits_data_0) // @[LazyModuleImp.scala:138:7]
); // @[FIFOFixer.scala:152:27]
TLBuffer_a21d64s8k1z3u buffer ( // @[Buffer.scala:75:28]
.clock (clock),
.reset (reset),
.auto_in_a_ready (tlOut_a_ready),
.auto_in_a_valid (tlOut_a_valid), // @[MixedNode.scala:542:17]
.auto_in_a_bits_opcode (tlOut_a_bits_opcode), // @[MixedNode.scala:542:17]
.auto_in_a_bits_param (tlOut_a_bits_param), // @[MixedNode.scala:542:17]
.auto_in_a_bits_size (tlOut_a_bits_size), // @[MixedNode.scala:542:17]
.auto_in_a_bits_source (tlOut_a_bits_source), // @[MixedNode.scala:542:17]
.auto_in_a_bits_address (tlOut_a_bits_address), // @[MixedNode.scala:542:17]
.auto_in_a_bits_mask (tlOut_a_bits_mask), // @[MixedNode.scala:542:17]
.auto_in_a_bits_data (tlOut_a_bits_data), // @[MixedNode.scala:542:17]
.auto_in_a_bits_corrupt (tlOut_a_bits_corrupt), // @[MixedNode.scala:542:17]
.auto_in_d_ready (tlOut_d_ready), // @[MixedNode.scala:542:17]
.auto_in_d_valid (tlOut_d_valid),
.auto_in_d_bits_opcode (tlOut_d_bits_opcode),
.auto_in_d_bits_param (tlOut_d_bits_param),
.auto_in_d_bits_size (tlOut_d_bits_size),
.auto_in_d_bits_source (tlOut_d_bits_source),
.auto_in_d_bits_sink (tlOut_d_bits_sink),
.auto_in_d_bits_denied (tlOut_d_bits_denied),
.auto_in_d_bits_data (tlOut_d_bits_data),
.auto_in_d_bits_corrupt (tlOut_d_bits_corrupt),
.auto_out_a_ready (_fixer_auto_anon_in_a_ready), // @[FIFOFixer.scala:152:27]
.auto_out_a_valid (_buffer_auto_out_a_valid),
.auto_out_a_bits_opcode (_buffer_auto_out_a_bits_opcode),
.auto_out_a_bits_param (_buffer_auto_out_a_bits_param),
.auto_out_a_bits_size (_buffer_auto_out_a_bits_size),
.auto_out_a_bits_source (_buffer_auto_out_a_bits_source),
.auto_out_a_bits_address (_buffer_auto_out_a_bits_address),
.auto_out_a_bits_mask (_buffer_auto_out_a_bits_mask),
.auto_out_a_bits_data (_buffer_auto_out_a_bits_data),
.auto_out_a_bits_corrupt (_buffer_auto_out_a_bits_corrupt),
.auto_out_d_ready (_buffer_auto_out_d_ready),
.auto_out_d_valid (_fixer_auto_anon_in_d_valid), // @[FIFOFixer.scala:152:27]
.auto_out_d_bits_opcode (_fixer_auto_anon_in_d_bits_opcode), // @[FIFOFixer.scala:152:27]
.auto_out_d_bits_size (_fixer_auto_anon_in_d_bits_size), // @[FIFOFixer.scala:152:27]
.auto_out_d_bits_source (_fixer_auto_anon_in_d_bits_source), // @[FIFOFixer.scala:152:27]
.auto_out_d_bits_data (_fixer_auto_anon_in_d_bits_data) // @[FIFOFixer.scala:152:27]
); // @[Buffer.scala:75:28]
assign auto_fixer_anon_out_a_valid = auto_fixer_anon_out_a_valid_0; // @[LazyModuleImp.scala:138:7]
assign auto_fixer_anon_out_a_bits_opcode = auto_fixer_anon_out_a_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
assign auto_fixer_anon_out_a_bits_param = auto_fixer_anon_out_a_bits_param_0; // @[LazyModuleImp.scala:138:7]
assign auto_fixer_anon_out_a_bits_size = auto_fixer_anon_out_a_bits_size_0; // @[LazyModuleImp.scala:138:7]
assign auto_fixer_anon_out_a_bits_source = auto_fixer_anon_out_a_bits_source_0; // @[LazyModuleImp.scala:138:7]
assign auto_fixer_anon_out_a_bits_address = auto_fixer_anon_out_a_bits_address_0; // @[LazyModuleImp.scala:138:7]
assign auto_fixer_anon_out_a_bits_mask = auto_fixer_anon_out_a_bits_mask_0; // @[LazyModuleImp.scala:138:7]
assign auto_fixer_anon_out_a_bits_data = auto_fixer_anon_out_a_bits_data_0; // @[LazyModuleImp.scala:138:7]
assign auto_fixer_anon_out_a_bits_corrupt = auto_fixer_anon_out_a_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
assign auto_fixer_anon_out_d_ready = auto_fixer_anon_out_d_ready_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_a_ready = auto_tl_in_a_ready_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_valid = auto_tl_in_d_valid_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_bits_opcode = auto_tl_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_bits_param = auto_tl_in_d_bits_param_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_bits_size = auto_tl_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_bits_source = auto_tl_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_bits_sink = auto_tl_in_d_bits_sink_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_bits_denied = auto_tl_in_d_bits_denied_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_bits_data = auto_tl_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_bits_corrupt = auto_tl_in_d_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module DivSqrtRecFMToRaw_small_e11_s53_5 :
input clock : Clock
input reset : Reset
output io : { inReady : UInt<1>, flip inValid : UInt<1>, flip sqrtOp : UInt<1>, flip a : UInt<65>, flip b : UInt<65>, flip roundingMode : UInt<3>, rawOutValid_div : UInt<1>, rawOutValid_sqrt : UInt<1>, roundingModeOut : UInt<3>, invalidExc : UInt<1>, infiniteExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<56>}}
inst divSqrtRawFN of DivSqrtRawFN_small_e11_s53_5
connect divSqrtRawFN.clock, clock
connect divSqrtRawFN.reset, reset
connect io.inReady, divSqrtRawFN.io.inReady
connect divSqrtRawFN.io.inValid, io.inValid
connect divSqrtRawFN.io.sqrtOp, io.sqrtOp
node divSqrtRawFN_io_a_exp = bits(io.a, 63, 52)
node _divSqrtRawFN_io_a_isZero_T = bits(divSqrtRawFN_io_a_exp, 11, 9)
node divSqrtRawFN_io_a_isZero = eq(_divSqrtRawFN_io_a_isZero_T, UInt<1>(0h0))
node _divSqrtRawFN_io_a_isSpecial_T = bits(divSqrtRawFN_io_a_exp, 11, 10)
node divSqrtRawFN_io_a_isSpecial = eq(_divSqrtRawFN_io_a_isSpecial_T, UInt<2>(0h3))
wire divSqrtRawFN_io_a_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>}
node _divSqrtRawFN_io_a_out_isNaN_T = bits(divSqrtRawFN_io_a_exp, 9, 9)
node _divSqrtRawFN_io_a_out_isNaN_T_1 = and(divSqrtRawFN_io_a_isSpecial, _divSqrtRawFN_io_a_out_isNaN_T)
connect divSqrtRawFN_io_a_out.isNaN, _divSqrtRawFN_io_a_out_isNaN_T_1
node _divSqrtRawFN_io_a_out_isInf_T = bits(divSqrtRawFN_io_a_exp, 9, 9)
node _divSqrtRawFN_io_a_out_isInf_T_1 = eq(_divSqrtRawFN_io_a_out_isInf_T, UInt<1>(0h0))
node _divSqrtRawFN_io_a_out_isInf_T_2 = and(divSqrtRawFN_io_a_isSpecial, _divSqrtRawFN_io_a_out_isInf_T_1)
connect divSqrtRawFN_io_a_out.isInf, _divSqrtRawFN_io_a_out_isInf_T_2
connect divSqrtRawFN_io_a_out.isZero, divSqrtRawFN_io_a_isZero
node _divSqrtRawFN_io_a_out_sign_T = bits(io.a, 64, 64)
connect divSqrtRawFN_io_a_out.sign, _divSqrtRawFN_io_a_out_sign_T
node _divSqrtRawFN_io_a_out_sExp_T = cvt(divSqrtRawFN_io_a_exp)
connect divSqrtRawFN_io_a_out.sExp, _divSqrtRawFN_io_a_out_sExp_T
node _divSqrtRawFN_io_a_out_sig_T = eq(divSqrtRawFN_io_a_isZero, UInt<1>(0h0))
node _divSqrtRawFN_io_a_out_sig_T_1 = cat(UInt<1>(0h0), _divSqrtRawFN_io_a_out_sig_T)
node _divSqrtRawFN_io_a_out_sig_T_2 = bits(io.a, 51, 0)
node _divSqrtRawFN_io_a_out_sig_T_3 = cat(_divSqrtRawFN_io_a_out_sig_T_1, _divSqrtRawFN_io_a_out_sig_T_2)
connect divSqrtRawFN_io_a_out.sig, _divSqrtRawFN_io_a_out_sig_T_3
connect divSqrtRawFN.io.a.sig, divSqrtRawFN_io_a_out.sig
connect divSqrtRawFN.io.a.sExp, divSqrtRawFN_io_a_out.sExp
connect divSqrtRawFN.io.a.sign, divSqrtRawFN_io_a_out.sign
connect divSqrtRawFN.io.a.isZero, divSqrtRawFN_io_a_out.isZero
connect divSqrtRawFN.io.a.isInf, divSqrtRawFN_io_a_out.isInf
connect divSqrtRawFN.io.a.isNaN, divSqrtRawFN_io_a_out.isNaN
node divSqrtRawFN_io_b_exp = bits(io.b, 63, 52)
node _divSqrtRawFN_io_b_isZero_T = bits(divSqrtRawFN_io_b_exp, 11, 9)
node divSqrtRawFN_io_b_isZero = eq(_divSqrtRawFN_io_b_isZero_T, UInt<1>(0h0))
node _divSqrtRawFN_io_b_isSpecial_T = bits(divSqrtRawFN_io_b_exp, 11, 10)
node divSqrtRawFN_io_b_isSpecial = eq(_divSqrtRawFN_io_b_isSpecial_T, UInt<2>(0h3))
wire divSqrtRawFN_io_b_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>}
node _divSqrtRawFN_io_b_out_isNaN_T = bits(divSqrtRawFN_io_b_exp, 9, 9)
node _divSqrtRawFN_io_b_out_isNaN_T_1 = and(divSqrtRawFN_io_b_isSpecial, _divSqrtRawFN_io_b_out_isNaN_T)
connect divSqrtRawFN_io_b_out.isNaN, _divSqrtRawFN_io_b_out_isNaN_T_1
node _divSqrtRawFN_io_b_out_isInf_T = bits(divSqrtRawFN_io_b_exp, 9, 9)
node _divSqrtRawFN_io_b_out_isInf_T_1 = eq(_divSqrtRawFN_io_b_out_isInf_T, UInt<1>(0h0))
node _divSqrtRawFN_io_b_out_isInf_T_2 = and(divSqrtRawFN_io_b_isSpecial, _divSqrtRawFN_io_b_out_isInf_T_1)
connect divSqrtRawFN_io_b_out.isInf, _divSqrtRawFN_io_b_out_isInf_T_2
connect divSqrtRawFN_io_b_out.isZero, divSqrtRawFN_io_b_isZero
node _divSqrtRawFN_io_b_out_sign_T = bits(io.b, 64, 64)
connect divSqrtRawFN_io_b_out.sign, _divSqrtRawFN_io_b_out_sign_T
node _divSqrtRawFN_io_b_out_sExp_T = cvt(divSqrtRawFN_io_b_exp)
connect divSqrtRawFN_io_b_out.sExp, _divSqrtRawFN_io_b_out_sExp_T
node _divSqrtRawFN_io_b_out_sig_T = eq(divSqrtRawFN_io_b_isZero, UInt<1>(0h0))
node _divSqrtRawFN_io_b_out_sig_T_1 = cat(UInt<1>(0h0), _divSqrtRawFN_io_b_out_sig_T)
node _divSqrtRawFN_io_b_out_sig_T_2 = bits(io.b, 51, 0)
node _divSqrtRawFN_io_b_out_sig_T_3 = cat(_divSqrtRawFN_io_b_out_sig_T_1, _divSqrtRawFN_io_b_out_sig_T_2)
connect divSqrtRawFN_io_b_out.sig, _divSqrtRawFN_io_b_out_sig_T_3
connect divSqrtRawFN.io.b.sig, divSqrtRawFN_io_b_out.sig
connect divSqrtRawFN.io.b.sExp, divSqrtRawFN_io_b_out.sExp
connect divSqrtRawFN.io.b.sign, divSqrtRawFN_io_b_out.sign
connect divSqrtRawFN.io.b.isZero, divSqrtRawFN_io_b_out.isZero
connect divSqrtRawFN.io.b.isInf, divSqrtRawFN_io_b_out.isInf
connect divSqrtRawFN.io.b.isNaN, divSqrtRawFN_io_b_out.isNaN
connect divSqrtRawFN.io.roundingMode, io.roundingMode
connect io.rawOutValid_div, divSqrtRawFN.io.rawOutValid_div
connect io.rawOutValid_sqrt, divSqrtRawFN.io.rawOutValid_sqrt
connect io.roundingModeOut, divSqrtRawFN.io.roundingModeOut
connect io.invalidExc, divSqrtRawFN.io.invalidExc
connect io.infiniteExc, divSqrtRawFN.io.infiniteExc
connect io.rawOut, divSqrtRawFN.io.rawOut | module DivSqrtRecFMToRaw_small_e11_s53_5( // @[DivSqrtRecFN_small.scala:422:5]
input clock, // @[DivSqrtRecFN_small.scala:422:5]
input reset, // @[DivSqrtRecFN_small.scala:422:5]
output io_inReady, // @[DivSqrtRecFN_small.scala:426:16]
input io_inValid, // @[DivSqrtRecFN_small.scala:426:16]
input io_sqrtOp, // @[DivSqrtRecFN_small.scala:426:16]
input [64:0] io_a, // @[DivSqrtRecFN_small.scala:426:16]
input [64:0] io_b, // @[DivSqrtRecFN_small.scala:426:16]
input [2:0] io_roundingMode, // @[DivSqrtRecFN_small.scala:426:16]
output io_rawOutValid_div, // @[DivSqrtRecFN_small.scala:426:16]
output io_rawOutValid_sqrt, // @[DivSqrtRecFN_small.scala:426:16]
output [2:0] io_roundingModeOut, // @[DivSqrtRecFN_small.scala:426:16]
output io_invalidExc, // @[DivSqrtRecFN_small.scala:426:16]
output io_infiniteExc, // @[DivSqrtRecFN_small.scala:426:16]
output io_rawOut_isNaN, // @[DivSqrtRecFN_small.scala:426:16]
output io_rawOut_isInf, // @[DivSqrtRecFN_small.scala:426:16]
output io_rawOut_isZero, // @[DivSqrtRecFN_small.scala:426:16]
output io_rawOut_sign, // @[DivSqrtRecFN_small.scala:426:16]
output [12:0] io_rawOut_sExp, // @[DivSqrtRecFN_small.scala:426:16]
output [55:0] io_rawOut_sig // @[DivSqrtRecFN_small.scala:426:16]
);
wire io_inValid_0 = io_inValid; // @[DivSqrtRecFN_small.scala:422:5]
wire io_sqrtOp_0 = io_sqrtOp; // @[DivSqrtRecFN_small.scala:422:5]
wire [64:0] io_a_0 = io_a; // @[DivSqrtRecFN_small.scala:422:5]
wire [64:0] io_b_0 = io_b; // @[DivSqrtRecFN_small.scala:422:5]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[DivSqrtRecFN_small.scala:422:5]
wire io_rawOut_isNaN_0; // @[DivSqrtRecFN_small.scala:422:5]
wire io_rawOut_isInf_0; // @[DivSqrtRecFN_small.scala:422:5]
wire io_rawOut_isZero_0; // @[DivSqrtRecFN_small.scala:422:5]
wire io_rawOut_sign_0; // @[DivSqrtRecFN_small.scala:422:5]
wire [12:0] io_rawOut_sExp_0; // @[DivSqrtRecFN_small.scala:422:5]
wire [55:0] io_rawOut_sig_0; // @[DivSqrtRecFN_small.scala:422:5]
wire io_inReady_0; // @[DivSqrtRecFN_small.scala:422:5]
wire io_rawOutValid_div_0; // @[DivSqrtRecFN_small.scala:422:5]
wire io_rawOutValid_sqrt_0; // @[DivSqrtRecFN_small.scala:422:5]
wire [2:0] io_roundingModeOut_0; // @[DivSqrtRecFN_small.scala:422:5]
wire io_invalidExc_0; // @[DivSqrtRecFN_small.scala:422:5]
wire io_infiniteExc_0; // @[DivSqrtRecFN_small.scala:422:5]
wire [11:0] divSqrtRawFN_io_a_exp = io_a_0[63:52]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _divSqrtRawFN_io_a_isZero_T = divSqrtRawFN_io_a_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire divSqrtRawFN_io_a_isZero = _divSqrtRawFN_io_a_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire divSqrtRawFN_io_a_out_isZero = divSqrtRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _divSqrtRawFN_io_a_isSpecial_T = divSqrtRawFN_io_a_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire divSqrtRawFN_io_a_isSpecial = &_divSqrtRawFN_io_a_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _divSqrtRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _divSqrtRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _divSqrtRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [12:0] _divSqrtRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [53:0] _divSqrtRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire divSqrtRawFN_io_a_out_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire divSqrtRawFN_io_a_out_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire divSqrtRawFN_io_a_out_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [12:0] divSqrtRawFN_io_a_out_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [53:0] divSqrtRawFN_io_a_out_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _divSqrtRawFN_io_a_out_isNaN_T = divSqrtRawFN_io_a_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _divSqrtRawFN_io_a_out_isInf_T = divSqrtRawFN_io_a_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _divSqrtRawFN_io_a_out_isNaN_T_1 = divSqrtRawFN_io_a_isSpecial & _divSqrtRawFN_io_a_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign divSqrtRawFN_io_a_out_isNaN = _divSqrtRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _divSqrtRawFN_io_a_out_isInf_T_1 = ~_divSqrtRawFN_io_a_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _divSqrtRawFN_io_a_out_isInf_T_2 = divSqrtRawFN_io_a_isSpecial & _divSqrtRawFN_io_a_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign divSqrtRawFN_io_a_out_isInf = _divSqrtRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _divSqrtRawFN_io_a_out_sign_T = io_a_0[64]; // @[rawFloatFromRecFN.scala:59:25]
assign divSqrtRawFN_io_a_out_sign = _divSqrtRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _divSqrtRawFN_io_a_out_sExp_T = {1'h0, divSqrtRawFN_io_a_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign divSqrtRawFN_io_a_out_sExp = _divSqrtRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _divSqrtRawFN_io_a_out_sig_T = ~divSqrtRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _divSqrtRawFN_io_a_out_sig_T_1 = {1'h0, _divSqrtRawFN_io_a_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [51:0] _divSqrtRawFN_io_a_out_sig_T_2 = io_a_0[51:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _divSqrtRawFN_io_a_out_sig_T_3 = {_divSqrtRawFN_io_a_out_sig_T_1, _divSqrtRawFN_io_a_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign divSqrtRawFN_io_a_out_sig = _divSqrtRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [11:0] divSqrtRawFN_io_b_exp = io_b_0[63:52]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _divSqrtRawFN_io_b_isZero_T = divSqrtRawFN_io_b_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire divSqrtRawFN_io_b_isZero = _divSqrtRawFN_io_b_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire divSqrtRawFN_io_b_out_isZero = divSqrtRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _divSqrtRawFN_io_b_isSpecial_T = divSqrtRawFN_io_b_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire divSqrtRawFN_io_b_isSpecial = &_divSqrtRawFN_io_b_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _divSqrtRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _divSqrtRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _divSqrtRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [12:0] _divSqrtRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [53:0] _divSqrtRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire divSqrtRawFN_io_b_out_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire divSqrtRawFN_io_b_out_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire divSqrtRawFN_io_b_out_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [12:0] divSqrtRawFN_io_b_out_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [53:0] divSqrtRawFN_io_b_out_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _divSqrtRawFN_io_b_out_isNaN_T = divSqrtRawFN_io_b_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _divSqrtRawFN_io_b_out_isInf_T = divSqrtRawFN_io_b_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _divSqrtRawFN_io_b_out_isNaN_T_1 = divSqrtRawFN_io_b_isSpecial & _divSqrtRawFN_io_b_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign divSqrtRawFN_io_b_out_isNaN = _divSqrtRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _divSqrtRawFN_io_b_out_isInf_T_1 = ~_divSqrtRawFN_io_b_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _divSqrtRawFN_io_b_out_isInf_T_2 = divSqrtRawFN_io_b_isSpecial & _divSqrtRawFN_io_b_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign divSqrtRawFN_io_b_out_isInf = _divSqrtRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _divSqrtRawFN_io_b_out_sign_T = io_b_0[64]; // @[rawFloatFromRecFN.scala:59:25]
assign divSqrtRawFN_io_b_out_sign = _divSqrtRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _divSqrtRawFN_io_b_out_sExp_T = {1'h0, divSqrtRawFN_io_b_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign divSqrtRawFN_io_b_out_sExp = _divSqrtRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _divSqrtRawFN_io_b_out_sig_T = ~divSqrtRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _divSqrtRawFN_io_b_out_sig_T_1 = {1'h0, _divSqrtRawFN_io_b_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [51:0] _divSqrtRawFN_io_b_out_sig_T_2 = io_b_0[51:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _divSqrtRawFN_io_b_out_sig_T_3 = {_divSqrtRawFN_io_b_out_sig_T_1, _divSqrtRawFN_io_b_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign divSqrtRawFN_io_b_out_sig = _divSqrtRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
DivSqrtRawFN_small_e11_s53_5 divSqrtRawFN ( // @[DivSqrtRecFN_small.scala:446:15]
.clock (clock),
.reset (reset),
.io_inReady (io_inReady_0),
.io_inValid (io_inValid_0), // @[DivSqrtRecFN_small.scala:422:5]
.io_sqrtOp (io_sqrtOp_0), // @[DivSqrtRecFN_small.scala:422:5]
.io_a_isNaN (divSqrtRawFN_io_a_out_isNaN), // @[rawFloatFromRecFN.scala:55:23]
.io_a_isInf (divSqrtRawFN_io_a_out_isInf), // @[rawFloatFromRecFN.scala:55:23]
.io_a_isZero (divSqrtRawFN_io_a_out_isZero), // @[rawFloatFromRecFN.scala:55:23]
.io_a_sign (divSqrtRawFN_io_a_out_sign), // @[rawFloatFromRecFN.scala:55:23]
.io_a_sExp (divSqrtRawFN_io_a_out_sExp), // @[rawFloatFromRecFN.scala:55:23]
.io_a_sig (divSqrtRawFN_io_a_out_sig), // @[rawFloatFromRecFN.scala:55:23]
.io_b_isNaN (divSqrtRawFN_io_b_out_isNaN), // @[rawFloatFromRecFN.scala:55:23]
.io_b_isInf (divSqrtRawFN_io_b_out_isInf), // @[rawFloatFromRecFN.scala:55:23]
.io_b_isZero (divSqrtRawFN_io_b_out_isZero), // @[rawFloatFromRecFN.scala:55:23]
.io_b_sign (divSqrtRawFN_io_b_out_sign), // @[rawFloatFromRecFN.scala:55:23]
.io_b_sExp (divSqrtRawFN_io_b_out_sExp), // @[rawFloatFromRecFN.scala:55:23]
.io_b_sig (divSqrtRawFN_io_b_out_sig), // @[rawFloatFromRecFN.scala:55:23]
.io_roundingMode (io_roundingMode_0), // @[DivSqrtRecFN_small.scala:422:5]
.io_rawOutValid_div (io_rawOutValid_div_0),
.io_rawOutValid_sqrt (io_rawOutValid_sqrt_0),
.io_roundingModeOut (io_roundingModeOut_0),
.io_invalidExc (io_invalidExc_0),
.io_infiniteExc (io_infiniteExc_0),
.io_rawOut_isNaN (io_rawOut_isNaN_0),
.io_rawOut_isInf (io_rawOut_isInf_0),
.io_rawOut_isZero (io_rawOut_isZero_0),
.io_rawOut_sign (io_rawOut_sign_0),
.io_rawOut_sExp (io_rawOut_sExp_0),
.io_rawOut_sig (io_rawOut_sig_0)
); // @[DivSqrtRecFN_small.scala:446:15]
assign io_inReady = io_inReady_0; // @[DivSqrtRecFN_small.scala:422:5]
assign io_rawOutValid_div = io_rawOutValid_div_0; // @[DivSqrtRecFN_small.scala:422:5]
assign io_rawOutValid_sqrt = io_rawOutValid_sqrt_0; // @[DivSqrtRecFN_small.scala:422:5]
assign io_roundingModeOut = io_roundingModeOut_0; // @[DivSqrtRecFN_small.scala:422:5]
assign io_invalidExc = io_invalidExc_0; // @[DivSqrtRecFN_small.scala:422:5]
assign io_infiniteExc = io_infiniteExc_0; // @[DivSqrtRecFN_small.scala:422:5]
assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[DivSqrtRecFN_small.scala:422:5]
assign io_rawOut_isInf = io_rawOut_isInf_0; // @[DivSqrtRecFN_small.scala:422:5]
assign io_rawOut_isZero = io_rawOut_isZero_0; // @[DivSqrtRecFN_small.scala:422:5]
assign io_rawOut_sign = io_rawOut_sign_0; // @[DivSqrtRecFN_small.scala:422:5]
assign io_rawOut_sExp = io_rawOut_sExp_0; // @[DivSqrtRecFN_small.scala:422:5]
assign io_rawOut_sig = io_rawOut_sig_0; // @[DivSqrtRecFN_small.scala:422:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MSHR_23 :
input clock : Clock
input reset : Reset
output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}}, status : { valid : UInt<1>, bits : { set : UInt<11>, tag : UInt<9>, way : UInt<4>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<9>, set : UInt<11>, param : UInt<3>, source : UInt<4>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<9>, set : UInt<11>, clients : UInt<1>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<9>, set : UInt<11>, way : UInt<4>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<11>, way : UInt<4>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<11>, tag : UInt<9>, source : UInt<6>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<4>}}, flip nestedwb : { set : UInt<11>, tag : UInt<9>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}}
regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>}, clock
regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}, clock
when meta_valid :
node _T = eq(meta.state, UInt<2>(0h0))
when _T :
node _T_1 = orr(meta.clients)
node _T_2 = eq(_T_1, UInt<1>(0h0))
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
node _T_6 = eq(meta.dirty, UInt<1>(0h0))
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1
assert(clock, _T_6, UInt<1>(0h1), "") : assert_1
node _T_10 = eq(meta.state, UInt<2>(0h1))
when _T_10 :
node _T_11 = eq(meta.dirty, UInt<1>(0h0))
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2
assert(clock, _T_11, UInt<1>(0h1), "") : assert_2
node _T_15 = eq(meta.state, UInt<2>(0h2))
when _T_15 :
node _T_16 = orr(meta.clients)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3
assert(clock, _T_16, UInt<1>(0h1), "") : assert_3
node _T_20 = sub(meta.clients, UInt<1>(0h1))
node _T_21 = tail(_T_20, 1)
node _T_22 = and(meta.clients, _T_21)
node _T_23 = eq(_T_22, UInt<1>(0h0))
node _T_24 = asUInt(reset)
node _T_25 = eq(_T_24, UInt<1>(0h0))
when _T_25 :
node _T_26 = eq(_T_23, UInt<1>(0h0))
when _T_26 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4
assert(clock, _T_23, UInt<1>(0h1), "") : assert_4
node _T_27 = eq(meta.state, UInt<2>(0h3))
when _T_27 :
skip
regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1)
reg sink : UInt<3>, clock
reg gotT : UInt<1>, clock
reg bad_grant : UInt<1>, clock
reg probes_done : UInt<1>, clock
reg probes_toN : UInt<1>, clock
reg probes_noT : UInt<1>, clock
node _T_28 = neq(meta.state, UInt<2>(0h0))
node _T_29 = and(meta_valid, _T_28)
node _T_30 = eq(io.nestedwb.set, request.set)
node _T_31 = and(_T_29, _T_30)
node _T_32 = eq(io.nestedwb.tag, meta.tag)
node _T_33 = and(_T_31, _T_32)
when _T_33 :
when io.nestedwb.b_clr_dirty :
connect meta.dirty, UInt<1>(0h0)
when io.nestedwb.c_set_dirty :
connect meta.dirty, UInt<1>(0h1)
when io.nestedwb.b_toB :
connect meta.state, UInt<2>(0h1)
when io.nestedwb.b_toN :
connect meta.hit, UInt<1>(0h0)
connect io.status.valid, request_valid
connect io.status.bits.set, request.set
connect io.status.bits.tag, request.tag
connect io.status.bits.way, meta.way
node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0))
node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0))
node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0))
node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2)
node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0))
node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4)
node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6)
node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7)
connect io.status.bits.blockB, _io_status_bits_blockB_T_8
node _io_status_bits_nestB_T = and(meta_valid, w_releaseack)
node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast)
node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast)
node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3)
connect io.status.bits.nestB, _io_status_bits_nestB_T_4
node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0))
connect io.status.bits.blockC, _io_status_bits_blockC_T
node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1)
node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3)
node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4)
connect io.status.bits.nestC, _io_status_bits_nestC_T_5
node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0))
node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0))
node _T_36 = or(_T_34, _T_35)
node _T_37 = asUInt(reset)
node _T_38 = eq(_T_37, UInt<1>(0h0))
when _T_38 :
node _T_39 = eq(_T_36, UInt<1>(0h0))
when _T_39 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB || !io.status.bits.blockB)\n") : printf_5
assert(clock, _T_36, UInt<1>(0h1), "") : assert_5
node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0))
node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0))
node _T_42 = or(_T_40, _T_41)
node _T_43 = asUInt(reset)
node _T_44 = eq(_T_43, UInt<1>(0h0))
when _T_44 :
node _T_45 = eq(_T_42, UInt<1>(0h0))
when _T_45 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC || !io.status.bits.blockC)\n") : printf_6
assert(clock, _T_42, UInt<1>(0h1), "") : assert_6
node _no_wait_T = and(w_rprobeacklast, w_releaseack)
node _no_wait_T_1 = and(_no_wait_T, w_grantlast)
node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast)
node no_wait = and(_no_wait_T_2, w_grantack)
node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0))
node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release)
node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe)
connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2
node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0))
node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1)
connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2
node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0))
node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst)
node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0))
node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst)
node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3)
connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4
node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0))
node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack)
node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant)
connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2
node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0))
node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst)
connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1
node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0))
node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack)
connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1
node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0))
node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst)
node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0))
node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait)
node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3)
connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4
connect io.schedule.bits.reload, no_wait
node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid)
node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid)
node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid)
node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid)
node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid)
node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid)
connect io.schedule.valid, _io_schedule_valid_T_5
when io.schedule.ready :
connect s_rprobe, UInt<1>(0h1)
when w_rprobeackfirst :
connect s_release, UInt<1>(0h1)
connect s_pprobe, UInt<1>(0h1)
node _T_46 = and(s_release, s_pprobe)
when _T_46 :
connect s_acquire, UInt<1>(0h1)
when w_releaseack :
connect s_flush, UInt<1>(0h1)
when w_pprobeackfirst :
connect s_probeack, UInt<1>(0h1)
when w_grantfirst :
connect s_grantack, UInt<1>(0h1)
node _T_47 = and(w_pprobeack, w_grant)
when _T_47 :
connect s_execute, UInt<1>(0h1)
when no_wait :
connect s_writeback, UInt<1>(0h1)
when no_wait :
connect request_valid, UInt<1>(0h0)
connect meta_valid, UInt<1>(0h0)
wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}
connect final_meta_writeback, meta
node req_clientBit = eq(request.source, UInt<6>(0h28))
node _req_needT_T = bits(request.opcode, 2, 2)
node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0))
node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5))
node _req_needT_T_3 = eq(request.param, UInt<1>(0h1))
node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3)
node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4)
node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6))
node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7))
node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7)
node _req_needT_T_9 = neq(request.param, UInt<2>(0h0))
node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9)
node req_needT = or(_req_needT_T_5, _req_needT_T_10)
node _req_acquire_T = eq(request.opcode, UInt<3>(0h6))
node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7))
node req_acquire = or(_req_acquire_T, _req_acquire_T_1)
node _meta_no_clients_T = orr(meta.clients)
node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0))
node _req_promoteT_T = eq(meta.state, UInt<2>(0h3))
node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T)
node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT)
node req_promoteT = and(req_acquire, _req_promoteT_T_2)
node _T_48 = and(request.prio[2], UInt<1>(0h1))
when _T_48 :
node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0)
node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T)
connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1
node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3))
node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2))
node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1)
node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state)
connect final_meta_writeback.state, _final_meta_writeback_state_T_3
node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1))
node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2))
node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1)
node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5))
node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3)
node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0))
node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5)
node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7
connect final_meta_writeback.hit, UInt<1>(0h1)
else :
node _T_49 = and(request.control, UInt<1>(0h1))
when _T_49 :
when meta.hit :
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h0)
node _final_meta_writeback_clients_T_8 = not(probes_toN)
node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9
connect final_meta_writeback.hit, UInt<1>(0h0)
else :
node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty)
node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2)
node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0))
node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4)
connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5
node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0))
node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1))
node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire)
node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state)
node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1))
node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state)
node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11)
node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state)
node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13)
node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15)
node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16)
connect final_meta_writeback.state, _final_meta_writeback_state_T_17
node _final_meta_writeback_clients_T_10 = not(probes_toN)
node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10)
node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0))
node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0))
node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14
connect final_meta_writeback.tag, request.tag
connect final_meta_writeback.hit, UInt<1>(0h1)
when bad_grant :
when meta.hit :
node _T_50 = eq(meta_valid, UInt<1>(0h0))
node _T_51 = eq(meta.state, UInt<2>(0h1))
node _T_52 = or(_T_50, _T_51)
node _T_53 = asUInt(reset)
node _T_54 = eq(_T_53, UInt<1>(0h0))
when _T_54 :
node _T_55 = eq(_T_52, UInt<1>(0h0))
when _T_55 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid || meta.state === BRANCH)\n") : printf_7
assert(clock, _T_52, UInt<1>(0h1), "") : assert_7
connect final_meta_writeback.hit, UInt<1>(0h1)
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h1)
node _final_meta_writeback_clients_T_15 = not(probes_toN)
node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16
else :
connect final_meta_writeback.hit, UInt<1>(0h0)
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h0)
connect final_meta_writeback.clients, UInt<1>(0h0)
wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}
connect invalid.dirty, UInt<1>(0h0)
connect invalid.state, UInt<2>(0h0)
connect invalid.clients, UInt<1>(0h0)
connect invalid.tag, UInt<1>(0h0)
node _honour_BtoT_T = and(meta.clients, req_clientBit)
node _honour_BtoT_T_1 = orr(_honour_BtoT_T)
node honour_BtoT = and(meta.hit, _honour_BtoT_T_1)
node _excluded_client_T = and(meta.hit, request.prio[0])
node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6))
node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7))
node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2)
node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4))
node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4)
node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5))
node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0))
node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7)
node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8)
node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0))
connect io.schedule.bits.a.bits.tag, request.tag
connect io.schedule.bits.a.bits.set, request.set
node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0))
connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1
node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6))
node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0))
node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7))
node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2)
node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0))
node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4)
connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5
connect io.schedule.bits.a.bits.source, UInt<1>(0h0)
node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1)
node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2)
connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3
node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag)
connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1
connect io.schedule.bits.b.bits.set, request.set
node _io_schedule_bits_b_bits_clients_T = not(excluded_client)
node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T)
connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1
node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6))
connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T
node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1))
node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1))
connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1
connect io.schedule.bits.c.bits.source, UInt<1>(0h0)
connect io.schedule.bits.c.bits.tag, meta.tag
connect io.schedule.bits.c.bits.set, request.set
connect io.schedule.bits.c.bits.way, meta.way
connect io.schedule.bits.c.bits.dirty, meta.dirty
connect io.schedule.bits.d.bits.set, request.set
connect io.schedule.bits.d.bits.put, request.put
connect io.schedule.bits.d.bits.offset, request.offset
connect io.schedule.bits.d.bits.tag, request.tag
connect io.schedule.bits.d.bits.source, request.source
connect io.schedule.bits.d.bits.size, request.size
connect io.schedule.bits.d.bits.param, request.param
connect io.schedule.bits.d.bits.opcode, request.opcode
connect io.schedule.bits.d.bits.control, request.control
connect io.schedule.bits.d.bits.prio, request.prio
node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0))
node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0))
node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param)
node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param)
node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param)
node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4)
node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param)
node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6)
node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8)
connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9
connect io.schedule.bits.d.bits.sink, UInt<1>(0h0)
connect io.schedule.bits.d.bits.way, meta.way
connect io.schedule.bits.d.bits.bad, bad_grant
connect io.schedule.bits.e.bits.sink, sink
connect io.schedule.bits.x.bits.fail, UInt<1>(0h0)
connect io.schedule.bits.dir.bits.set, request.set
connect io.schedule.bits.dir.bits.way, meta.way
node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0))
wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}
connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag
connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients
connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state
connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty
node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE)
connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1
node _evict_T = eq(meta.hit, UInt<1>(0h0))
wire evict : UInt
connect evict, UInt<1>(0h0)
node evict_c = orr(meta.clients)
node _evict_T_1 = eq(UInt<2>(0h1), meta.state)
when _evict_T_1 :
node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1))
connect evict, _evict_out_T
else :
node _evict_T_2 = eq(UInt<2>(0h2), meta.state)
when _evict_T_2 :
node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect evict, _evict_out_T_1
else :
node _evict_T_3 = eq(UInt<2>(0h3), meta.state)
when _evict_T_3 :
node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3)
connect evict, _evict_out_T_4
else :
node _evict_T_4 = eq(UInt<2>(0h0), meta.state)
when _evict_T_4 :
connect evict, UInt<4>(0h8)
node _evict_T_5 = eq(_evict_T, UInt<1>(0h0))
when _evict_T_5 :
connect evict, UInt<4>(0h8)
wire before : UInt
connect before, UInt<1>(0h0)
node before_c = orr(meta.clients)
node _before_T = eq(UInt<2>(0h1), meta.state)
when _before_T :
node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1))
connect before, _before_out_T
else :
node _before_T_1 = eq(UInt<2>(0h2), meta.state)
when _before_T_1 :
node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect before, _before_out_T_1
else :
node _before_T_2 = eq(UInt<2>(0h3), meta.state)
when _before_T_2 :
node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3)
connect before, _before_out_T_4
else :
node _before_T_3 = eq(UInt<2>(0h0), meta.state)
when _before_T_3 :
connect before, UInt<4>(0h8)
node _before_T_4 = eq(meta.hit, UInt<1>(0h0))
when _before_T_4 :
connect before, UInt<4>(0h8)
wire after : UInt
connect after, UInt<1>(0h0)
node after_c = orr(final_meta_writeback.clients)
node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state)
when _after_T :
node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1))
connect after, _after_out_T
else :
node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state)
when _after_T_1 :
node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect after, _after_out_T_1
else :
node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state)
when _after_T_2 :
node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3)
connect after, _after_out_T_4
else :
node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state)
when _after_T_3 :
connect after, UInt<4>(0h8)
node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0))
when _after_T_4 :
connect after, UInt<4>(0h8)
node _T_56 = eq(s_release, UInt<1>(0h0))
node _T_57 = and(_T_56, w_rprobeackfirst)
node _T_58 = and(_T_57, io.schedule.ready)
when _T_58 :
node _T_59 = eq(evict, UInt<1>(0h1))
node _T_60 = eq(_T_59, UInt<1>(0h0))
node _T_61 = asUInt(reset)
node _T_62 = eq(_T_61, UInt<1>(0h0))
when _T_62 :
node _T_63 = eq(_T_60, UInt<1>(0h0))
when _T_63 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8
assert(clock, _T_60, UInt<1>(0h1), "") : assert_8
node _T_64 = eq(before, UInt<1>(0h1))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(_T_65, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9
assert(clock, _T_65, UInt<1>(0h1), "") : assert_9
node _T_69 = eq(evict, UInt<1>(0h0))
node _T_70 = eq(_T_69, UInt<1>(0h0))
node _T_71 = asUInt(reset)
node _T_72 = eq(_T_71, UInt<1>(0h0))
when _T_72 :
node _T_73 = eq(_T_70, UInt<1>(0h0))
when _T_73 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10
assert(clock, _T_70, UInt<1>(0h1), "") : assert_10
node _T_74 = eq(before, UInt<1>(0h0))
node _T_75 = eq(_T_74, UInt<1>(0h0))
node _T_76 = asUInt(reset)
node _T_77 = eq(_T_76, UInt<1>(0h0))
when _T_77 :
node _T_78 = eq(_T_75, UInt<1>(0h0))
when _T_78 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11
assert(clock, _T_75, UInt<1>(0h1), "") : assert_11
node _T_79 = eq(evict, UInt<3>(0h7))
node _T_80 = eq(before, UInt<3>(0h7))
node _T_81 = eq(evict, UInt<3>(0h5))
node _T_82 = eq(before, UInt<3>(0h5))
node _T_83 = eq(evict, UInt<3>(0h4))
node _T_84 = eq(before, UInt<3>(0h4))
node _T_85 = eq(evict, UInt<3>(0h6))
node _T_86 = eq(before, UInt<3>(0h6))
node _T_87 = eq(evict, UInt<2>(0h3))
node _T_88 = eq(before, UInt<2>(0h3))
node _T_89 = eq(evict, UInt<2>(0h2))
node _T_90 = eq(before, UInt<2>(0h2))
node _T_91 = eq(s_writeback, UInt<1>(0h0))
node _T_92 = and(_T_91, no_wait)
node _T_93 = and(_T_92, io.schedule.ready)
when _T_93 :
node _T_94 = eq(before, UInt<4>(0h8))
node _T_95 = eq(after, UInt<1>(0h1))
node _T_96 = and(_T_94, _T_95)
node _T_97 = eq(_T_96, UInt<1>(0h0))
node _T_98 = asUInt(reset)
node _T_99 = eq(_T_98, UInt<1>(0h0))
when _T_99 :
node _T_100 = eq(_T_97, UInt<1>(0h0))
when _T_100 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12
assert(clock, _T_97, UInt<1>(0h1), "") : assert_12
node _T_101 = eq(before, UInt<4>(0h8))
node _T_102 = eq(after, UInt<1>(0h0))
node _T_103 = and(_T_101, _T_102)
node _T_104 = eq(_T_103, UInt<1>(0h0))
node _T_105 = asUInt(reset)
node _T_106 = eq(_T_105, UInt<1>(0h0))
when _T_106 :
node _T_107 = eq(_T_104, UInt<1>(0h0))
when _T_107 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13
assert(clock, _T_104, UInt<1>(0h1), "") : assert_13
node _T_108 = eq(before, UInt<4>(0h8))
node _T_109 = eq(after, UInt<3>(0h7))
node _T_110 = and(_T_108, _T_109)
node _T_111 = eq(before, UInt<4>(0h8))
node _T_112 = eq(after, UInt<3>(0h5))
node _T_113 = and(_T_111, _T_112)
node _T_114 = eq(_T_113, UInt<1>(0h0))
node _T_115 = asUInt(reset)
node _T_116 = eq(_T_115, UInt<1>(0h0))
when _T_116 :
node _T_117 = eq(_T_114, UInt<1>(0h0))
when _T_117 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14
assert(clock, _T_114, UInt<1>(0h1), "") : assert_14
node _T_118 = eq(before, UInt<4>(0h8))
node _T_119 = eq(after, UInt<3>(0h4))
node _T_120 = and(_T_118, _T_119)
node _T_121 = eq(_T_120, UInt<1>(0h0))
node _T_122 = asUInt(reset)
node _T_123 = eq(_T_122, UInt<1>(0h0))
when _T_123 :
node _T_124 = eq(_T_121, UInt<1>(0h0))
when _T_124 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15
assert(clock, _T_121, UInt<1>(0h1), "") : assert_15
node _T_125 = eq(before, UInt<4>(0h8))
node _T_126 = eq(after, UInt<3>(0h6))
node _T_127 = and(_T_125, _T_126)
node _T_128 = eq(before, UInt<4>(0h8))
node _T_129 = eq(after, UInt<2>(0h3))
node _T_130 = and(_T_128, _T_129)
node _T_131 = eq(before, UInt<4>(0h8))
node _T_132 = eq(after, UInt<2>(0h2))
node _T_133 = and(_T_131, _T_132)
node _T_134 = eq(_T_133, UInt<1>(0h0))
node _T_135 = asUInt(reset)
node _T_136 = eq(_T_135, UInt<1>(0h0))
when _T_136 :
node _T_137 = eq(_T_134, UInt<1>(0h0))
when _T_137 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16
assert(clock, _T_134, UInt<1>(0h1), "") : assert_16
node _T_138 = eq(before, UInt<1>(0h1))
node _T_139 = eq(after, UInt<4>(0h8))
node _T_140 = and(_T_138, _T_139)
node _T_141 = eq(_T_140, UInt<1>(0h0))
node _T_142 = asUInt(reset)
node _T_143 = eq(_T_142, UInt<1>(0h0))
when _T_143 :
node _T_144 = eq(_T_141, UInt<1>(0h0))
when _T_144 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17
assert(clock, _T_141, UInt<1>(0h1), "") : assert_17
node _T_145 = eq(before, UInt<1>(0h1))
node _T_146 = eq(after, UInt<1>(0h0))
node _T_147 = and(_T_145, _T_146)
node _T_148 = eq(_T_147, UInt<1>(0h0))
node _T_149 = asUInt(reset)
node _T_150 = eq(_T_149, UInt<1>(0h0))
when _T_150 :
node _T_151 = eq(_T_148, UInt<1>(0h0))
when _T_151 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18
assert(clock, _T_148, UInt<1>(0h1), "") : assert_18
node _T_152 = eq(before, UInt<1>(0h1))
node _T_153 = eq(after, UInt<3>(0h7))
node _T_154 = and(_T_152, _T_153)
node _T_155 = eq(_T_154, UInt<1>(0h0))
node _T_156 = asUInt(reset)
node _T_157 = eq(_T_156, UInt<1>(0h0))
when _T_157 :
node _T_158 = eq(_T_155, UInt<1>(0h0))
when _T_158 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19
assert(clock, _T_155, UInt<1>(0h1), "") : assert_19
node _T_159 = eq(before, UInt<1>(0h1))
node _T_160 = eq(after, UInt<3>(0h5))
node _T_161 = and(_T_159, _T_160)
node _T_162 = eq(_T_161, UInt<1>(0h0))
node _T_163 = asUInt(reset)
node _T_164 = eq(_T_163, UInt<1>(0h0))
when _T_164 :
node _T_165 = eq(_T_162, UInt<1>(0h0))
when _T_165 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20
assert(clock, _T_162, UInt<1>(0h1), "") : assert_20
node _T_166 = eq(before, UInt<1>(0h1))
node _T_167 = eq(after, UInt<3>(0h4))
node _T_168 = and(_T_166, _T_167)
node _T_169 = eq(_T_168, UInt<1>(0h0))
node _T_170 = asUInt(reset)
node _T_171 = eq(_T_170, UInt<1>(0h0))
when _T_171 :
node _T_172 = eq(_T_169, UInt<1>(0h0))
when _T_172 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21
assert(clock, _T_169, UInt<1>(0h1), "") : assert_21
node _T_173 = eq(before, UInt<1>(0h1))
node _T_174 = eq(after, UInt<3>(0h6))
node _T_175 = and(_T_173, _T_174)
node _T_176 = eq(_T_175, UInt<1>(0h0))
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_T_176, UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22
assert(clock, _T_176, UInt<1>(0h1), "") : assert_22
node _T_180 = eq(before, UInt<1>(0h1))
node _T_181 = eq(after, UInt<2>(0h3))
node _T_182 = and(_T_180, _T_181)
node _T_183 = eq(_T_182, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(before, UInt<1>(0h1))
node _T_188 = eq(after, UInt<2>(0h2))
node _T_189 = and(_T_187, _T_188)
node _T_190 = eq(_T_189, UInt<1>(0h0))
node _T_191 = asUInt(reset)
node _T_192 = eq(_T_191, UInt<1>(0h0))
when _T_192 :
node _T_193 = eq(_T_190, UInt<1>(0h0))
when _T_193 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24
assert(clock, _T_190, UInt<1>(0h1), "") : assert_24
node _T_194 = eq(before, UInt<1>(0h0))
node _T_195 = eq(after, UInt<4>(0h8))
node _T_196 = and(_T_194, _T_195)
node _T_197 = eq(_T_196, UInt<1>(0h0))
node _T_198 = asUInt(reset)
node _T_199 = eq(_T_198, UInt<1>(0h0))
when _T_199 :
node _T_200 = eq(_T_197, UInt<1>(0h0))
when _T_200 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25
assert(clock, _T_197, UInt<1>(0h1), "") : assert_25
node _T_201 = eq(before, UInt<1>(0h0))
node _T_202 = eq(after, UInt<1>(0h1))
node _T_203 = and(_T_201, _T_202)
node _T_204 = eq(_T_203, UInt<1>(0h0))
node _T_205 = asUInt(reset)
node _T_206 = eq(_T_205, UInt<1>(0h0))
when _T_206 :
node _T_207 = eq(_T_204, UInt<1>(0h0))
when _T_207 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26
assert(clock, _T_204, UInt<1>(0h1), "") : assert_26
node _T_208 = eq(before, UInt<1>(0h0))
node _T_209 = eq(after, UInt<3>(0h7))
node _T_210 = and(_T_208, _T_209)
node _T_211 = eq(_T_210, UInt<1>(0h0))
node _T_212 = asUInt(reset)
node _T_213 = eq(_T_212, UInt<1>(0h0))
when _T_213 :
node _T_214 = eq(_T_211, UInt<1>(0h0))
when _T_214 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27
assert(clock, _T_211, UInt<1>(0h1), "") : assert_27
node _T_215 = eq(before, UInt<1>(0h0))
node _T_216 = eq(after, UInt<3>(0h5))
node _T_217 = and(_T_215, _T_216)
node _T_218 = eq(_T_217, UInt<1>(0h0))
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28
assert(clock, _T_218, UInt<1>(0h1), "") : assert_28
node _T_222 = eq(before, UInt<1>(0h0))
node _T_223 = eq(after, UInt<3>(0h6))
node _T_224 = and(_T_222, _T_223)
node _T_225 = eq(_T_224, UInt<1>(0h0))
node _T_226 = asUInt(reset)
node _T_227 = eq(_T_226, UInt<1>(0h0))
when _T_227 :
node _T_228 = eq(_T_225, UInt<1>(0h0))
when _T_228 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29
assert(clock, _T_225, UInt<1>(0h1), "") : assert_29
node _T_229 = eq(before, UInt<1>(0h0))
node _T_230 = eq(after, UInt<3>(0h4))
node _T_231 = and(_T_229, _T_230)
node _T_232 = eq(_T_231, UInt<1>(0h0))
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30
assert(clock, _T_232, UInt<1>(0h1), "") : assert_30
node _T_236 = eq(before, UInt<1>(0h0))
node _T_237 = eq(after, UInt<2>(0h3))
node _T_238 = and(_T_236, _T_237)
node _T_239 = eq(_T_238, UInt<1>(0h0))
node _T_240 = asUInt(reset)
node _T_241 = eq(_T_240, UInt<1>(0h0))
when _T_241 :
node _T_242 = eq(_T_239, UInt<1>(0h0))
when _T_242 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31
assert(clock, _T_239, UInt<1>(0h1), "") : assert_31
node _T_243 = eq(before, UInt<1>(0h0))
node _T_244 = eq(after, UInt<2>(0h2))
node _T_245 = and(_T_243, _T_244)
node _T_246 = eq(_T_245, UInt<1>(0h0))
node _T_247 = asUInt(reset)
node _T_248 = eq(_T_247, UInt<1>(0h0))
when _T_248 :
node _T_249 = eq(_T_246, UInt<1>(0h0))
when _T_249 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32
assert(clock, _T_246, UInt<1>(0h1), "") : assert_32
node _T_250 = eq(before, UInt<3>(0h7))
node _T_251 = eq(after, UInt<4>(0h8))
node _T_252 = and(_T_250, _T_251)
node _T_253 = eq(_T_252, UInt<1>(0h0))
node _T_254 = asUInt(reset)
node _T_255 = eq(_T_254, UInt<1>(0h0))
when _T_255 :
node _T_256 = eq(_T_253, UInt<1>(0h0))
when _T_256 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33
assert(clock, _T_253, UInt<1>(0h1), "") : assert_33
node _T_257 = eq(before, UInt<3>(0h7))
node _T_258 = eq(after, UInt<1>(0h1))
node _T_259 = and(_T_257, _T_258)
node _T_260 = eq(_T_259, UInt<1>(0h0))
node _T_261 = asUInt(reset)
node _T_262 = eq(_T_261, UInt<1>(0h0))
when _T_262 :
node _T_263 = eq(_T_260, UInt<1>(0h0))
when _T_263 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34
assert(clock, _T_260, UInt<1>(0h1), "") : assert_34
node _T_264 = eq(before, UInt<3>(0h7))
node _T_265 = eq(after, UInt<1>(0h0))
node _T_266 = and(_T_264, _T_265)
node _T_267 = eq(_T_266, UInt<1>(0h0))
node _T_268 = asUInt(reset)
node _T_269 = eq(_T_268, UInt<1>(0h0))
when _T_269 :
node _T_270 = eq(_T_267, UInt<1>(0h0))
when _T_270 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35
assert(clock, _T_267, UInt<1>(0h1), "") : assert_35
node _T_271 = eq(before, UInt<3>(0h7))
node _T_272 = eq(after, UInt<3>(0h5))
node _T_273 = and(_T_271, _T_272)
node _T_274 = eq(_T_273, UInt<1>(0h0))
node _T_275 = asUInt(reset)
node _T_276 = eq(_T_275, UInt<1>(0h0))
when _T_276 :
node _T_277 = eq(_T_274, UInt<1>(0h0))
when _T_277 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36
assert(clock, _T_274, UInt<1>(0h1), "") : assert_36
node _T_278 = eq(before, UInt<3>(0h7))
node _T_279 = eq(after, UInt<3>(0h6))
node _T_280 = and(_T_278, _T_279)
node _T_281 = eq(before, UInt<3>(0h7))
node _T_282 = eq(after, UInt<3>(0h4))
node _T_283 = and(_T_281, _T_282)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = asUInt(reset)
node _T_286 = eq(_T_285, UInt<1>(0h0))
when _T_286 :
node _T_287 = eq(_T_284, UInt<1>(0h0))
when _T_287 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37
assert(clock, _T_284, UInt<1>(0h1), "") : assert_37
node _T_288 = eq(before, UInt<3>(0h7))
node _T_289 = eq(after, UInt<2>(0h3))
node _T_290 = and(_T_288, _T_289)
node _T_291 = eq(before, UInt<3>(0h7))
node _T_292 = eq(after, UInt<2>(0h2))
node _T_293 = and(_T_291, _T_292)
node _T_294 = eq(_T_293, UInt<1>(0h0))
node _T_295 = asUInt(reset)
node _T_296 = eq(_T_295, UInt<1>(0h0))
when _T_296 :
node _T_297 = eq(_T_294, UInt<1>(0h0))
when _T_297 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38
assert(clock, _T_294, UInt<1>(0h1), "") : assert_38
node _T_298 = eq(before, UInt<3>(0h5))
node _T_299 = eq(after, UInt<4>(0h8))
node _T_300 = and(_T_298, _T_299)
node _T_301 = eq(_T_300, UInt<1>(0h0))
node _T_302 = asUInt(reset)
node _T_303 = eq(_T_302, UInt<1>(0h0))
when _T_303 :
node _T_304 = eq(_T_301, UInt<1>(0h0))
when _T_304 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39
assert(clock, _T_301, UInt<1>(0h1), "") : assert_39
node _T_305 = eq(before, UInt<3>(0h5))
node _T_306 = eq(after, UInt<1>(0h1))
node _T_307 = and(_T_305, _T_306)
node _T_308 = eq(_T_307, UInt<1>(0h0))
node _T_309 = asUInt(reset)
node _T_310 = eq(_T_309, UInt<1>(0h0))
when _T_310 :
node _T_311 = eq(_T_308, UInt<1>(0h0))
when _T_311 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40
assert(clock, _T_308, UInt<1>(0h1), "") : assert_40
node _T_312 = eq(before, UInt<3>(0h5))
node _T_313 = eq(after, UInt<1>(0h0))
node _T_314 = and(_T_312, _T_313)
node _T_315 = eq(_T_314, UInt<1>(0h0))
node _T_316 = asUInt(reset)
node _T_317 = eq(_T_316, UInt<1>(0h0))
when _T_317 :
node _T_318 = eq(_T_315, UInt<1>(0h0))
when _T_318 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41
assert(clock, _T_315, UInt<1>(0h1), "") : assert_41
node _T_319 = eq(before, UInt<3>(0h5))
node _T_320 = eq(after, UInt<3>(0h7))
node _T_321 = and(_T_319, _T_320)
node _T_322 = eq(before, UInt<3>(0h5))
node _T_323 = eq(after, UInt<3>(0h6))
node _T_324 = and(_T_322, _T_323)
node _T_325 = eq(before, UInt<3>(0h5))
node _T_326 = eq(after, UInt<3>(0h4))
node _T_327 = and(_T_325, _T_326)
node _T_328 = eq(_T_327, UInt<1>(0h0))
node _T_329 = asUInt(reset)
node _T_330 = eq(_T_329, UInt<1>(0h0))
when _T_330 :
node _T_331 = eq(_T_328, UInt<1>(0h0))
when _T_331 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42
assert(clock, _T_328, UInt<1>(0h1), "") : assert_42
node _T_332 = eq(before, UInt<3>(0h5))
node _T_333 = eq(after, UInt<2>(0h3))
node _T_334 = and(_T_332, _T_333)
node _T_335 = eq(before, UInt<3>(0h5))
node _T_336 = eq(after, UInt<2>(0h2))
node _T_337 = and(_T_335, _T_336)
node _T_338 = eq(_T_337, UInt<1>(0h0))
node _T_339 = asUInt(reset)
node _T_340 = eq(_T_339, UInt<1>(0h0))
when _T_340 :
node _T_341 = eq(_T_338, UInt<1>(0h0))
when _T_341 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43
assert(clock, _T_338, UInt<1>(0h1), "") : assert_43
node _T_342 = eq(before, UInt<3>(0h6))
node _T_343 = eq(after, UInt<4>(0h8))
node _T_344 = and(_T_342, _T_343)
node _T_345 = eq(_T_344, UInt<1>(0h0))
node _T_346 = asUInt(reset)
node _T_347 = eq(_T_346, UInt<1>(0h0))
when _T_347 :
node _T_348 = eq(_T_345, UInt<1>(0h0))
when _T_348 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44
assert(clock, _T_345, UInt<1>(0h1), "") : assert_44
node _T_349 = eq(before, UInt<3>(0h6))
node _T_350 = eq(after, UInt<1>(0h1))
node _T_351 = and(_T_349, _T_350)
node _T_352 = eq(_T_351, UInt<1>(0h0))
node _T_353 = asUInt(reset)
node _T_354 = eq(_T_353, UInt<1>(0h0))
when _T_354 :
node _T_355 = eq(_T_352, UInt<1>(0h0))
when _T_355 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45
assert(clock, _T_352, UInt<1>(0h1), "") : assert_45
node _T_356 = eq(before, UInt<3>(0h6))
node _T_357 = eq(after, UInt<1>(0h0))
node _T_358 = and(_T_356, _T_357)
node _T_359 = eq(_T_358, UInt<1>(0h0))
node _T_360 = asUInt(reset)
node _T_361 = eq(_T_360, UInt<1>(0h0))
when _T_361 :
node _T_362 = eq(_T_359, UInt<1>(0h0))
when _T_362 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46
assert(clock, _T_359, UInt<1>(0h1), "") : assert_46
node _T_363 = eq(before, UInt<3>(0h6))
node _T_364 = eq(after, UInt<3>(0h7))
node _T_365 = and(_T_363, _T_364)
node _T_366 = eq(_T_365, UInt<1>(0h0))
node _T_367 = asUInt(reset)
node _T_368 = eq(_T_367, UInt<1>(0h0))
when _T_368 :
node _T_369 = eq(_T_366, UInt<1>(0h0))
when _T_369 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47
assert(clock, _T_366, UInt<1>(0h1), "") : assert_47
node _T_370 = eq(before, UInt<3>(0h6))
node _T_371 = eq(after, UInt<3>(0h5))
node _T_372 = and(_T_370, _T_371)
node _T_373 = eq(_T_372, UInt<1>(0h0))
node _T_374 = asUInt(reset)
node _T_375 = eq(_T_374, UInt<1>(0h0))
when _T_375 :
node _T_376 = eq(_T_373, UInt<1>(0h0))
when _T_376 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48
assert(clock, _T_373, UInt<1>(0h1), "") : assert_48
node _T_377 = eq(before, UInt<3>(0h6))
node _T_378 = eq(after, UInt<3>(0h4))
node _T_379 = and(_T_377, _T_378)
node _T_380 = eq(_T_379, UInt<1>(0h0))
node _T_381 = asUInt(reset)
node _T_382 = eq(_T_381, UInt<1>(0h0))
when _T_382 :
node _T_383 = eq(_T_380, UInt<1>(0h0))
when _T_383 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49
assert(clock, _T_380, UInt<1>(0h1), "") : assert_49
node _T_384 = eq(before, UInt<3>(0h6))
node _T_385 = eq(after, UInt<2>(0h3))
node _T_386 = and(_T_384, _T_385)
node _T_387 = eq(_T_386, UInt<1>(0h0))
node _T_388 = asUInt(reset)
node _T_389 = eq(_T_388, UInt<1>(0h0))
when _T_389 :
node _T_390 = eq(_T_387, UInt<1>(0h0))
when _T_390 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50
assert(clock, _T_387, UInt<1>(0h1), "") : assert_50
node _T_391 = eq(before, UInt<3>(0h6))
node _T_392 = eq(after, UInt<2>(0h2))
node _T_393 = and(_T_391, _T_392)
node _T_394 = eq(before, UInt<3>(0h4))
node _T_395 = eq(after, UInt<4>(0h8))
node _T_396 = and(_T_394, _T_395)
node _T_397 = eq(_T_396, UInt<1>(0h0))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51
assert(clock, _T_397, UInt<1>(0h1), "") : assert_51
node _T_401 = eq(before, UInt<3>(0h4))
node _T_402 = eq(after, UInt<1>(0h1))
node _T_403 = and(_T_401, _T_402)
node _T_404 = eq(_T_403, UInt<1>(0h0))
node _T_405 = asUInt(reset)
node _T_406 = eq(_T_405, UInt<1>(0h0))
when _T_406 :
node _T_407 = eq(_T_404, UInt<1>(0h0))
when _T_407 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52
assert(clock, _T_404, UInt<1>(0h1), "") : assert_52
node _T_408 = eq(before, UInt<3>(0h4))
node _T_409 = eq(after, UInt<1>(0h0))
node _T_410 = and(_T_408, _T_409)
node _T_411 = eq(_T_410, UInt<1>(0h0))
node _T_412 = asUInt(reset)
node _T_413 = eq(_T_412, UInt<1>(0h0))
when _T_413 :
node _T_414 = eq(_T_411, UInt<1>(0h0))
when _T_414 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53
assert(clock, _T_411, UInt<1>(0h1), "") : assert_53
node _T_415 = eq(before, UInt<3>(0h4))
node _T_416 = eq(after, UInt<3>(0h7))
node _T_417 = and(_T_415, _T_416)
node _T_418 = eq(_T_417, UInt<1>(0h0))
node _T_419 = asUInt(reset)
node _T_420 = eq(_T_419, UInt<1>(0h0))
when _T_420 :
node _T_421 = eq(_T_418, UInt<1>(0h0))
when _T_421 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54
assert(clock, _T_418, UInt<1>(0h1), "") : assert_54
node _T_422 = eq(before, UInt<3>(0h4))
node _T_423 = eq(after, UInt<3>(0h5))
node _T_424 = and(_T_422, _T_423)
node _T_425 = eq(_T_424, UInt<1>(0h0))
node _T_426 = asUInt(reset)
node _T_427 = eq(_T_426, UInt<1>(0h0))
when _T_427 :
node _T_428 = eq(_T_425, UInt<1>(0h0))
when _T_428 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55
assert(clock, _T_425, UInt<1>(0h1), "") : assert_55
node _T_429 = eq(before, UInt<3>(0h4))
node _T_430 = eq(after, UInt<3>(0h6))
node _T_431 = and(_T_429, _T_430)
node _T_432 = eq(before, UInt<3>(0h4))
node _T_433 = eq(after, UInt<2>(0h3))
node _T_434 = and(_T_432, _T_433)
node _T_435 = eq(_T_434, UInt<1>(0h0))
node _T_436 = asUInt(reset)
node _T_437 = eq(_T_436, UInt<1>(0h0))
when _T_437 :
node _T_438 = eq(_T_435, UInt<1>(0h0))
when _T_438 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56
assert(clock, _T_435, UInt<1>(0h1), "") : assert_56
node _T_439 = eq(before, UInt<3>(0h4))
node _T_440 = eq(after, UInt<2>(0h2))
node _T_441 = and(_T_439, _T_440)
node _T_442 = eq(before, UInt<2>(0h3))
node _T_443 = eq(after, UInt<4>(0h8))
node _T_444 = and(_T_442, _T_443)
node _T_445 = eq(_T_444, UInt<1>(0h0))
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57
assert(clock, _T_445, UInt<1>(0h1), "") : assert_57
node _T_449 = eq(before, UInt<2>(0h3))
node _T_450 = eq(after, UInt<1>(0h1))
node _T_451 = and(_T_449, _T_450)
node _T_452 = eq(_T_451, UInt<1>(0h0))
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(_T_452, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58
assert(clock, _T_452, UInt<1>(0h1), "") : assert_58
node _T_456 = eq(before, UInt<2>(0h3))
node _T_457 = eq(after, UInt<1>(0h0))
node _T_458 = and(_T_456, _T_457)
node _T_459 = eq(_T_458, UInt<1>(0h0))
node _T_460 = asUInt(reset)
node _T_461 = eq(_T_460, UInt<1>(0h0))
when _T_461 :
node _T_462 = eq(_T_459, UInt<1>(0h0))
when _T_462 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59
assert(clock, _T_459, UInt<1>(0h1), "") : assert_59
node _T_463 = eq(before, UInt<2>(0h3))
node _T_464 = eq(after, UInt<3>(0h7))
node _T_465 = and(_T_463, _T_464)
node _T_466 = eq(before, UInt<2>(0h3))
node _T_467 = eq(after, UInt<3>(0h5))
node _T_468 = and(_T_466, _T_467)
node _T_469 = eq(before, UInt<2>(0h3))
node _T_470 = eq(after, UInt<3>(0h6))
node _T_471 = and(_T_469, _T_470)
node _T_472 = eq(before, UInt<2>(0h3))
node _T_473 = eq(after, UInt<3>(0h4))
node _T_474 = and(_T_472, _T_473)
node _T_475 = eq(before, UInt<2>(0h3))
node _T_476 = eq(after, UInt<2>(0h2))
node _T_477 = and(_T_475, _T_476)
node _T_478 = eq(before, UInt<2>(0h2))
node _T_479 = eq(after, UInt<4>(0h8))
node _T_480 = and(_T_478, _T_479)
node _T_481 = eq(_T_480, UInt<1>(0h0))
node _T_482 = asUInt(reset)
node _T_483 = eq(_T_482, UInt<1>(0h0))
when _T_483 :
node _T_484 = eq(_T_481, UInt<1>(0h0))
when _T_484 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60
assert(clock, _T_481, UInt<1>(0h1), "") : assert_60
node _T_485 = eq(before, UInt<2>(0h2))
node _T_486 = eq(after, UInt<1>(0h1))
node _T_487 = and(_T_485, _T_486)
node _T_488 = eq(_T_487, UInt<1>(0h0))
node _T_489 = asUInt(reset)
node _T_490 = eq(_T_489, UInt<1>(0h0))
when _T_490 :
node _T_491 = eq(_T_488, UInt<1>(0h0))
when _T_491 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61
assert(clock, _T_488, UInt<1>(0h1), "") : assert_61
node _T_492 = eq(before, UInt<2>(0h2))
node _T_493 = eq(after, UInt<1>(0h0))
node _T_494 = and(_T_492, _T_493)
node _T_495 = eq(_T_494, UInt<1>(0h0))
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_T_495, UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62
assert(clock, _T_495, UInt<1>(0h1), "") : assert_62
node _T_499 = eq(before, UInt<2>(0h2))
node _T_500 = eq(after, UInt<3>(0h7))
node _T_501 = and(_T_499, _T_500)
node _T_502 = eq(_T_501, UInt<1>(0h0))
node _T_503 = asUInt(reset)
node _T_504 = eq(_T_503, UInt<1>(0h0))
when _T_504 :
node _T_505 = eq(_T_502, UInt<1>(0h0))
when _T_505 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63
assert(clock, _T_502, UInt<1>(0h1), "") : assert_63
node _T_506 = eq(before, UInt<2>(0h2))
node _T_507 = eq(after, UInt<3>(0h5))
node _T_508 = and(_T_506, _T_507)
node _T_509 = eq(_T_508, UInt<1>(0h0))
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64
assert(clock, _T_509, UInt<1>(0h1), "") : assert_64
node _T_513 = eq(before, UInt<2>(0h2))
node _T_514 = eq(after, UInt<3>(0h6))
node _T_515 = and(_T_513, _T_514)
node _T_516 = eq(before, UInt<2>(0h2))
node _T_517 = eq(after, UInt<3>(0h4))
node _T_518 = and(_T_516, _T_517)
node _T_519 = eq(before, UInt<2>(0h2))
node _T_520 = eq(after, UInt<2>(0h3))
node _T_521 = and(_T_519, _T_520)
node _T_522 = eq(_T_521, UInt<1>(0h0))
node _T_523 = asUInt(reset)
node _T_524 = eq(_T_523, UInt<1>(0h0))
when _T_524 :
node _T_525 = eq(_T_522, UInt<1>(0h0))
when _T_525 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65
assert(clock, _T_522, UInt<1>(0h1), "") : assert_65
node probe_bit = eq(io.sinkc.bits.source, UInt<6>(0h28))
node _last_probe_T = or(probes_done, probe_bit)
node _last_probe_T_1 = not(excluded_client)
node _last_probe_T_2 = and(meta.clients, _last_probe_T_1)
node last_probe = eq(_last_probe_T, _last_probe_T_2)
node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1))
node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2))
node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1)
node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5))
node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3)
when io.sinkc.valid :
node _T_526 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1))
node _T_527 = and(probe_toN, _T_526)
node _T_528 = eq(probe_toN, UInt<1>(0h0))
node _T_529 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1))
node _T_530 = and(_T_528, _T_529)
node _probes_done_T = or(probes_done, probe_bit)
connect probes_done, _probes_done_T
node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0))
node _probes_toN_T_1 = or(probes_toN, _probes_toN_T)
connect probes_toN, _probes_toN_T_1
node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3))
node _probes_noT_T_1 = or(probes_noT, _probes_noT_T)
connect probes_noT, _probes_noT_T_1
node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe)
connect w_rprobeackfirst, _w_rprobeackfirst_T
node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last)
node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T)
connect w_rprobeacklast, _w_rprobeacklast_T_1
node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe)
connect w_pprobeackfirst, _w_pprobeackfirst_T
node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last)
node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T)
connect w_pprobeacklast, _w_pprobeacklast_T_1
node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0))
node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T)
node set_pprobeack = and(last_probe, _set_pprobeack_T_1)
node _w_pprobeack_T = or(w_pprobeack, set_pprobeack)
connect w_pprobeack, _w_pprobeack_T
node _T_531 = eq(set_pprobeack, UInt<1>(0h0))
node _T_532 = and(_T_531, w_rprobeackfirst)
node _T_533 = and(set_pprobeack, w_rprobeackfirst)
node _T_534 = neq(meta.state, UInt<2>(0h0))
node _T_535 = eq(io.sinkc.bits.tag, meta.tag)
node _T_536 = and(_T_534, _T_535)
node _T_537 = and(_T_536, io.sinkc.bits.data)
when _T_537 :
connect meta.dirty, UInt<1>(0h1)
when io.sinkd.valid :
node _T_538 = eq(io.sinkd.bits.opcode, UInt<3>(0h4))
node _T_539 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_540 = or(_T_538, _T_539)
when _T_540 :
connect sink, io.sinkd.bits.sink
connect w_grantfirst, UInt<1>(0h1)
connect w_grantlast, io.sinkd.bits.last
connect bad_grant, io.sinkd.bits.denied
node _w_grant_T = eq(request.offset, UInt<1>(0h0))
node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last)
connect w_grant, _w_grant_T_1
node _T_541 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_542 = eq(request.offset, UInt<1>(0h0))
node _T_543 = and(_T_541, _T_542)
node _T_544 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_545 = neq(request.offset, UInt<1>(0h0))
node _T_546 = and(_T_544, _T_545)
node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0))
connect gotT, _gotT_T
else :
node _T_547 = eq(io.sinkd.bits.opcode, UInt<3>(0h6))
when _T_547 :
connect w_releaseack, UInt<1>(0h1)
when io.sinke.valid :
connect w_grantack, UInt<1>(0h1)
wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>}
connect allocate_as_full.set, io.allocate.bits.set
connect allocate_as_full.put, io.allocate.bits.put
connect allocate_as_full.offset, io.allocate.bits.offset
connect allocate_as_full.tag, io.allocate.bits.tag
connect allocate_as_full.source, io.allocate.bits.source
connect allocate_as_full.size, io.allocate.bits.size
connect allocate_as_full.param, io.allocate.bits.param
connect allocate_as_full.opcode, io.allocate.bits.opcode
connect allocate_as_full.control, io.allocate.bits.control
connect allocate_as_full.prio, io.allocate.bits.prio
node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat)
node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits)
node new_request = mux(io.allocate.valid, allocate_as_full, request)
node _new_needT_T = bits(new_request.opcode, 2, 2)
node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0))
node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5))
node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1))
node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3)
node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4)
node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6))
node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7))
node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7)
node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0))
node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9)
node new_needT = or(_new_needT_T_5, _new_needT_T_10)
node new_clientBit = eq(new_request.source, UInt<6>(0h28))
node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6))
node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7))
node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1)
node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4))
node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3)
node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5))
node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0))
node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6)
node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0))
wire prior : UInt
connect prior, UInt<1>(0h0)
node prior_c = orr(final_meta_writeback.clients)
node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state)
when _prior_T :
node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1))
connect prior, _prior_out_T
else :
node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state)
when _prior_T_1 :
node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect prior, _prior_out_T_1
else :
node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state)
when _prior_T_2 :
node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3)
connect prior, _prior_out_T_4
else :
node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state)
when _prior_T_3 :
connect prior, UInt<4>(0h8)
node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0))
when _prior_T_4 :
connect prior, UInt<4>(0h8)
node _T_548 = and(io.allocate.valid, io.allocate.bits.repeat)
when _T_548 :
node _T_549 = eq(prior, UInt<4>(0h8))
node _T_550 = eq(prior, UInt<1>(0h1))
node _T_551 = eq(_T_550, UInt<1>(0h0))
node _T_552 = asUInt(reset)
node _T_553 = eq(_T_552, UInt<1>(0h0))
when _T_553 :
node _T_554 = eq(_T_551, UInt<1>(0h0))
when _T_554 :
printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_66
assert(clock, _T_551, UInt<1>(0h1), "") : assert_66
node _T_555 = eq(prior, UInt<1>(0h0))
node _T_556 = eq(_T_555, UInt<1>(0h0))
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_67
assert(clock, _T_556, UInt<1>(0h1), "") : assert_67
node _T_560 = eq(prior, UInt<3>(0h7))
node _T_561 = eq(prior, UInt<3>(0h5))
node _T_562 = eq(prior, UInt<3>(0h4))
node _T_563 = eq(prior, UInt<3>(0h6))
node _T_564 = eq(prior, UInt<2>(0h3))
node _T_565 = eq(prior, UInt<2>(0h2))
when io.allocate.valid :
node _T_566 = eq(request_valid, UInt<1>(0h0))
node _T_567 = and(io.schedule.ready, io.schedule.valid)
node _T_568 = and(no_wait, _T_567)
node _T_569 = or(_T_566, _T_568)
node _T_570 = asUInt(reset)
node _T_571 = eq(_T_570, UInt<1>(0h0))
when _T_571 :
node _T_572 = eq(_T_569, UInt<1>(0h0))
when _T_572 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid || (no_wait && io.schedule.fire))\n") : printf_68
assert(clock, _T_569, UInt<1>(0h1), "") : assert_68
connect request_valid, UInt<1>(0h1)
connect request.set, io.allocate.bits.set
connect request.put, io.allocate.bits.put
connect request.offset, io.allocate.bits.offset
connect request.tag, io.allocate.bits.tag
connect request.source, io.allocate.bits.source
connect request.size, io.allocate.bits.size
connect request.param, io.allocate.bits.param
connect request.opcode, io.allocate.bits.opcode
connect request.control, io.allocate.bits.control
connect request.prio, io.allocate.bits.prio
node _T_573 = and(io.allocate.valid, io.allocate.bits.repeat)
node _T_574 = or(io.directory.valid, _T_573)
when _T_574 :
connect meta_valid, UInt<1>(0h1)
connect meta, new_meta
connect probes_done, UInt<1>(0h0)
connect probes_toN, UInt<1>(0h0)
connect probes_noT, UInt<1>(0h0)
connect gotT, UInt<1>(0h0)
connect bad_grant, UInt<1>(0h0)
connect s_rprobe, UInt<1>(0h1)
connect w_rprobeackfirst, UInt<1>(0h1)
connect w_rprobeacklast, UInt<1>(0h1)
connect s_release, UInt<1>(0h1)
connect w_releaseack, UInt<1>(0h1)
connect s_pprobe, UInt<1>(0h1)
connect s_acquire, UInt<1>(0h1)
connect s_flush, UInt<1>(0h1)
connect w_grantfirst, UInt<1>(0h1)
connect w_grantlast, UInt<1>(0h1)
connect w_grant, UInt<1>(0h1)
connect w_pprobeackfirst, UInt<1>(0h1)
connect w_pprobeacklast, UInt<1>(0h1)
connect w_pprobeack, UInt<1>(0h1)
connect s_probeack, UInt<1>(0h1)
connect s_grantack, UInt<1>(0h1)
connect s_execute, UInt<1>(0h1)
connect w_grantack, UInt<1>(0h1)
connect s_writeback, UInt<1>(0h1)
node _T_575 = and(new_request.prio[2], UInt<1>(0h1))
when _T_575 :
connect s_execute, UInt<1>(0h0)
node _T_576 = bits(new_request.opcode, 0, 0)
node _T_577 = eq(new_meta.dirty, UInt<1>(0h0))
node _T_578 = and(_T_576, _T_577)
when _T_578 :
connect s_writeback, UInt<1>(0h0)
node _T_579 = eq(new_request.param, UInt<3>(0h0))
node _T_580 = eq(new_request.param, UInt<3>(0h4))
node _T_581 = or(_T_579, _T_580)
node _T_582 = eq(new_meta.state, UInt<2>(0h2))
node _T_583 = and(_T_581, _T_582)
when _T_583 :
connect s_writeback, UInt<1>(0h0)
node _T_584 = eq(new_request.param, UInt<3>(0h1))
node _T_585 = eq(new_request.param, UInt<3>(0h2))
node _T_586 = or(_T_584, _T_585)
node _T_587 = eq(new_request.param, UInt<3>(0h5))
node _T_588 = or(_T_586, _T_587)
node _T_589 = and(new_meta.clients, new_clientBit)
node _T_590 = neq(_T_589, UInt<1>(0h0))
node _T_591 = and(_T_588, _T_590)
when _T_591 :
connect s_writeback, UInt<1>(0h0)
node _T_592 = asUInt(reset)
node _T_593 = eq(_T_592, UInt<1>(0h0))
when _T_593 :
node _T_594 = eq(new_meta.hit, UInt<1>(0h0))
when _T_594 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_69
assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_69
else :
node _T_595 = and(new_request.control, UInt<1>(0h1))
when _T_595 :
connect s_flush, UInt<1>(0h0)
when new_meta.hit :
connect s_release, UInt<1>(0h0)
connect w_releaseack, UInt<1>(0h0)
node _T_596 = neq(new_meta.clients, UInt<1>(0h0))
node _T_597 = and(UInt<1>(0h1), _T_596)
when _T_597 :
connect s_rprobe, UInt<1>(0h0)
connect w_rprobeackfirst, UInt<1>(0h0)
connect w_rprobeacklast, UInt<1>(0h0)
else :
connect s_execute, UInt<1>(0h0)
node _T_598 = eq(new_meta.hit, UInt<1>(0h0))
node _T_599 = neq(new_meta.state, UInt<2>(0h0))
node _T_600 = and(_T_598, _T_599)
when _T_600 :
connect s_release, UInt<1>(0h0)
connect w_releaseack, UInt<1>(0h0)
node _T_601 = neq(new_meta.clients, UInt<1>(0h0))
node _T_602 = and(UInt<1>(0h1), _T_601)
when _T_602 :
connect s_rprobe, UInt<1>(0h0)
connect w_rprobeackfirst, UInt<1>(0h0)
connect w_rprobeacklast, UInt<1>(0h0)
node _T_603 = eq(new_meta.hit, UInt<1>(0h0))
node _T_604 = eq(new_meta.state, UInt<2>(0h1))
node _T_605 = and(_T_604, new_needT)
node _T_606 = or(_T_603, _T_605)
when _T_606 :
connect s_acquire, UInt<1>(0h0)
connect w_grantfirst, UInt<1>(0h0)
connect w_grantlast, UInt<1>(0h0)
connect w_grant, UInt<1>(0h0)
connect s_grantack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_607 = eq(new_meta.state, UInt<2>(0h2))
node _T_608 = or(new_needT, _T_607)
node _T_609 = and(new_meta.hit, _T_608)
node _T_610 = not(new_skipProbe)
node _T_611 = and(new_meta.clients, _T_610)
node _T_612 = neq(_T_611, UInt<1>(0h0))
node _T_613 = and(_T_609, _T_612)
node _T_614 = and(UInt<1>(0h1), _T_613)
when _T_614 :
connect s_pprobe, UInt<1>(0h0)
connect w_pprobeackfirst, UInt<1>(0h0)
connect w_pprobeacklast, UInt<1>(0h0)
connect w_pprobeack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_615 = eq(new_request.opcode, UInt<3>(0h6))
node _T_616 = eq(new_request.opcode, UInt<3>(0h7))
node _T_617 = or(_T_615, _T_616)
when _T_617 :
connect w_grantack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_618 = bits(new_request.opcode, 2, 2)
node _T_619 = eq(_T_618, UInt<1>(0h0))
node _T_620 = and(_T_619, new_meta.hit)
node _T_621 = eq(new_meta.dirty, UInt<1>(0h0))
node _T_622 = and(_T_620, _T_621)
when _T_622 :
connect s_writeback, UInt<1>(0h0) | module MSHR_23( // @[MSHR.scala:84:7]
input clock, // @[MSHR.scala:84:7]
input reset, // @[MSHR.scala:84:7]
input io_allocate_valid, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_2, // @[MSHR.scala:86:14]
input io_allocate_bits_control, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14]
input [8:0] io_allocate_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14]
input [10:0] io_allocate_bits_set, // @[MSHR.scala:86:14]
input io_allocate_bits_repeat, // @[MSHR.scala:86:14]
input io_directory_valid, // @[MSHR.scala:86:14]
input io_directory_bits_dirty, // @[MSHR.scala:86:14]
input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14]
input io_directory_bits_clients, // @[MSHR.scala:86:14]
input [8:0] io_directory_bits_tag, // @[MSHR.scala:86:14]
input io_directory_bits_hit, // @[MSHR.scala:86:14]
input [3:0] io_directory_bits_way, // @[MSHR.scala:86:14]
output io_status_valid, // @[MSHR.scala:86:14]
output [10:0] io_status_bits_set, // @[MSHR.scala:86:14]
output [8:0] io_status_bits_tag, // @[MSHR.scala:86:14]
output [3:0] io_status_bits_way, // @[MSHR.scala:86:14]
output io_status_bits_blockB, // @[MSHR.scala:86:14]
output io_status_bits_nestB, // @[MSHR.scala:86:14]
output io_status_bits_blockC, // @[MSHR.scala:86:14]
output io_status_bits_nestC, // @[MSHR.scala:86:14]
input io_schedule_ready, // @[MSHR.scala:86:14]
output io_schedule_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_a_valid, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14]
output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14]
output io_schedule_bits_b_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14]
output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14]
output io_schedule_bits_c_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14]
output [3:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14]
output io_schedule_bits_d_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14]
output [3:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14]
output io_schedule_bits_e_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14]
output io_schedule_bits_x_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14]
output [3:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14]
output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14]
output io_schedule_bits_reload, // @[MSHR.scala:86:14]
input io_sinkc_valid, // @[MSHR.scala:86:14]
input io_sinkc_bits_last, // @[MSHR.scala:86:14]
input [10:0] io_sinkc_bits_set, // @[MSHR.scala:86:14]
input [8:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14]
input io_sinkc_bits_data, // @[MSHR.scala:86:14]
input io_sinkd_valid, // @[MSHR.scala:86:14]
input io_sinkd_bits_last, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14]
input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14]
input io_sinkd_bits_denied, // @[MSHR.scala:86:14]
input io_sinke_valid, // @[MSHR.scala:86:14]
input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14]
input [10:0] io_nestedwb_set, // @[MSHR.scala:86:14]
input [8:0] io_nestedwb_tag, // @[MSHR.scala:86:14]
input io_nestedwb_b_toN, // @[MSHR.scala:86:14]
input io_nestedwb_b_toB, // @[MSHR.scala:86:14]
input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14]
input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14]
);
wire [8:0] final_meta_writeback_tag; // @[MSHR.scala:215:38]
wire final_meta_writeback_clients; // @[MSHR.scala:215:38]
wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38]
wire final_meta_writeback_dirty; // @[MSHR.scala:215:38]
wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7]
wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7]
wire [8:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7]
wire [10:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7]
wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7]
wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7]
wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7]
wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7]
wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7]
wire [8:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7]
wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7]
wire [3:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7]
wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7]
wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7]
wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7]
wire [10:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7]
wire [8:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7]
wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7]
wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7]
wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7]
wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7]
wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7]
wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7]
wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7]
wire [10:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7]
wire [8:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7]
wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7]
wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_0 = 1'h0; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_1 = 1'h0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_0 = 1'h0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_1 = 1'h0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7]
wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68]
wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80]
wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21]
wire invalid_clients = 1'h0; // @[MSHR.scala:268:21]
wire _excluded_client_T = 1'h0; // @[MSHR.scala:279:38]
wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137]
wire _excluded_client_T_9 = 1'h0; // @[MSHR.scala:279:57]
wire excluded_client = 1'h0; // @[MSHR.scala:279:28]
wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire allocate_as_full_prio_0 = 1'h0; // @[MSHR.scala:504:34]
wire allocate_as_full_prio_1 = 1'h0; // @[MSHR.scala:504:34]
wire new_request_prio_0 = 1'h0; // @[MSHR.scala:506:24]
wire new_request_prio_1 = 1'h0; // @[MSHR.scala:506:24]
wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137]
wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire _io_schedule_bits_b_bits_clients_T = 1'h1; // @[MSHR.scala:289:53]
wire _last_probe_T_1 = 1'h1; // @[MSHR.scala:459:66]
wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7]
wire [8:0] invalid_tag = 9'h0; // @[MSHR.scala:268:21]
wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21]
wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70]
wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34]
wire [8:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34]
wire [10:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34]
wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40]
wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93]
wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28]
wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39]
wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105]
wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55]
wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91]
wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41]
wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41]
wire [8:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41]
wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51]
wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64]
wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41]
wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41]
wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57]
wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41]
wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43]
wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40]
wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66]
wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41]
wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41]
wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41]
wire [8:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41]
wire no_wait; // @[MSHR.scala:183:83]
wire [10:0] io_status_bits_set_0; // @[MSHR.scala:84:7]
wire [8:0] io_status_bits_tag_0; // @[MSHR.scala:84:7]
wire [3:0] io_status_bits_way_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockB_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestB_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockC_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestC_0; // @[MSHR.scala:84:7]
wire io_status_valid_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7]
wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7]
wire io_schedule_valid_0; // @[MSHR.scala:84:7]
reg request_valid; // @[MSHR.scala:97:30]
assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30]
reg request_prio_2; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20]
reg request_control; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_opcode; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_param; // @[MSHR.scala:98:20]
reg [2:0] request_size; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_source; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20]
reg [8:0] request_tag; // @[MSHR.scala:98:20]
assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_offset; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_put; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20]
reg [10:0] request_set; // @[MSHR.scala:98:20]
assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
reg meta_valid; // @[MSHR.scala:99:27]
reg meta_dirty; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17]
reg [1:0] meta_state; // @[MSHR.scala:100:17]
reg meta_clients; // @[MSHR.scala:100:17]
wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39]
assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients; // @[MSHR.scala:100:17, :289:51]
wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
wire _last_probe_T_2 = meta_clients; // @[MSHR.scala:100:17, :459:64]
reg [8:0] meta_tag; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17]
reg meta_hit; // @[MSHR.scala:100:17]
reg [3:0] meta_way; // @[MSHR.scala:100:17]
assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
wire [3:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38]
reg s_rprobe; // @[MSHR.scala:121:33]
reg w_rprobeackfirst; // @[MSHR.scala:122:33]
reg w_rprobeacklast; // @[MSHR.scala:123:33]
reg s_release; // @[MSHR.scala:124:33]
reg w_releaseack; // @[MSHR.scala:125:33]
reg s_pprobe; // @[MSHR.scala:126:33]
reg s_acquire; // @[MSHR.scala:127:33]
reg s_flush; // @[MSHR.scala:128:33]
reg w_grantfirst; // @[MSHR.scala:129:33]
reg w_grantlast; // @[MSHR.scala:130:33]
reg w_grant; // @[MSHR.scala:131:33]
reg w_pprobeackfirst; // @[MSHR.scala:132:33]
reg w_pprobeacklast; // @[MSHR.scala:133:33]
reg w_pprobeack; // @[MSHR.scala:134:33]
reg s_grantack; // @[MSHR.scala:136:33]
reg s_execute; // @[MSHR.scala:137:33]
reg w_grantack; // @[MSHR.scala:138:33]
reg s_writeback; // @[MSHR.scala:139:33]
reg [2:0] sink; // @[MSHR.scala:147:17]
assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17]
reg gotT; // @[MSHR.scala:148:17]
reg bad_grant; // @[MSHR.scala:149:22]
assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22]
reg probes_done; // @[MSHR.scala:150:24]
reg probes_toN; // @[MSHR.scala:151:23]
reg probes_noT; // @[MSHR.scala:152:23]
wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28]
wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45]
wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62]
wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}]
wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82]
wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}]
wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103]
wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}]
assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}]
assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40]
wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39]
wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}]
wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}]
wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96]
assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}]
assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93]
assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28]
assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28]
wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43]
wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64]
wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}]
wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85]
wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}]
assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}]
assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39]
wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33]
wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}]
wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}]
assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}]
assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83]
wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31]
wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}]
assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}]
assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55]
wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31]
wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44]
assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}]
assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41]
wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32]
wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}]
assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}]
assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64]
wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31]
wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}]
assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}]
assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57]
wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31]
assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}]
assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43]
wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31]
assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}]
assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40]
wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34]
wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}]
wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70]
wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}]
assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}]
assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66]
wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49]
wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}]
wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}]
wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49]
wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}]
assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}]
assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105]
wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71]
wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71]
wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71]
wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire [8:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71]
wire final_meta_writeback_hit; // @[MSHR.scala:215:38]
wire req_clientBit = request_source == 6'h28; // @[Parameters.scala:46:9]
wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12]
wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12]
wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _req_needT_T_2; // @[Parameters.scala:270:13]
assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13]
wire _excluded_client_T_6; // @[Parameters.scala:279:117]
assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117]
wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42]
wire _req_needT_T_3; // @[Parameters.scala:270:42]
assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42]
wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11]
assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11]
wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42]
wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _req_needT_T_6; // @[Parameters.scala:271:14]
assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14]
wire _req_acquire_T; // @[MSHR.scala:219:36]
assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14]
wire _excluded_client_T_1; // @[Parameters.scala:279:12]
assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12]
wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52]
wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89]
wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52]
wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}]
wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}]
wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81]
wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}]
wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}]
wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}]
wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65]
wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}]
wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55]
wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78]
wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78]
assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78]
wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70]
wire _evict_T_2; // @[MSHR.scala:317:26]
assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _before_T_1; // @[MSHR.scala:317:26]
assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}]
wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}]
wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43]
assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43]
wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75]
wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}]
wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9]
wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}]
wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}]
wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54]
wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}]
wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45]
wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}]
wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}]
wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40]
wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40]
assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40]
wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65]
assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65]
wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41]
wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}]
wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72]
wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}]
wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70]
wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70]
wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53]
assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53]
wire _evict_T_1; // @[MSHR.scala:317:26]
assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire _before_T; // @[MSHR.scala:317:26]
assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70]
wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70]
wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55]
wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70]
wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70]
wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66]
wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}]
wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}]
wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9]
wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40]
assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30]
wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54]
wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}]
assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21]
assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21]
assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36]
assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36]
wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9]
wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}]
wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}]
wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}]
wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}]
wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}]
wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56]
wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70]
assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}]
wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51]
wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55]
wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52]
wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}]
wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}]
assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38]
assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91]
wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42]
wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70]
wire [2:0] _io_schedule_bits_b_bits_param_T_2 = {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:286:{61,97}]
assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}]
assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41]
wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42]
assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}]
assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41]
assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51]
assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41]
assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41]
assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}]
assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41]
wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42]
wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53]
wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53]
wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89]
wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79]
assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41]
wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42]
assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 9'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}]
assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41]
wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32]
wire [3:0] evict; // @[MSHR.scala:314:26]
wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32]
wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32]
wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32]
assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32]
assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39]
wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39]
assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39]
assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76]
wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76]
assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76]
assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32]
assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] before_0; // @[MSHR.scala:314:26]
wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32]
wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11]
assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] after; // @[MSHR.scala:314:26]
wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26]
wire _after_T; // @[MSHR.scala:317:26]
assign _after_T = _GEN_9; // @[MSHR.scala:317:26]
wire _prior_T; // @[MSHR.scala:317:26]
assign _prior_T = _GEN_9; // @[MSHR.scala:317:26]
wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32]
wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26]
wire _after_T_1; // @[MSHR.scala:317:26]
assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire _prior_T_1; // @[MSHR.scala:317:26]
assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32]
wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32]
assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32]
assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39]
wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39]
assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39]
assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76]
wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76]
assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76]
assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26]
wire _after_T_3; // @[MSHR.scala:317:26]
assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26]
wire _prior_T_3; // @[MSHR.scala:317:26]
assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26]
assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire probe_bit = io_sinkc_bits_source_0 == 6'h28; // @[Parameters.scala:46:9]
wire _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:46:9]
wire _last_probe_T; // @[MSHR.scala:459:33]
assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33]
wire _probes_done_T; // @[MSHR.scala:467:32]
assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32]
wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}]
wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11]
wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43]
wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75]
wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}]
wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9]
wire _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}]
wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53]
wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}]
wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42]
wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55]
wire _w_rprobeacklast_T; // @[MSHR.scala:471:55]
assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55]
wire _w_pprobeacklast_T; // @[MSHR.scala:473:55]
assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55]
wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}]
wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42]
wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}]
wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77]
wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}]
wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}]
wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32]
wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33]
wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}]
wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35]
wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40]
wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [8:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [3:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [8:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [10:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12]
wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _new_needT_T_2; // @[Parameters.scala:270:13]
assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13]
wire _new_skipProbe_T_5; // @[Parameters.scala:279:117]
assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117]
wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42]
wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _new_needT_T_6; // @[Parameters.scala:271:14]
assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14]
wire _new_skipProbe_T; // @[Parameters.scala:279:12]
assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12]
wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52]
wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89]
wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire new_clientBit = new_request_source == 6'h28; // @[Parameters.scala:46:9]
wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}]
wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}]
wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}]
wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9]
wire [3:0] prior; // @[MSHR.scala:314:26]
wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32]
wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_57 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_117
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_57( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_117 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_51 :
input clock : Clock
input reset : Reset
output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], credit_return : UInt<8>, vc_free : UInt<8>}}
wire _in_flight_WIRE : UInt<1>[8]
connect _in_flight_WIRE[0], UInt<1>(0h0)
connect _in_flight_WIRE[1], UInt<1>(0h0)
connect _in_flight_WIRE[2], UInt<1>(0h0)
connect _in_flight_WIRE[3], UInt<1>(0h0)
connect _in_flight_WIRE[4], UInt<1>(0h0)
connect _in_flight_WIRE[5], UInt<1>(0h0)
connect _in_flight_WIRE[6], UInt<1>(0h0)
connect _in_flight_WIRE[7], UInt<1>(0h0)
regreset in_flight : UInt<1>[8], clock, reset, _in_flight_WIRE
when io.in.flit[0].valid :
when io.in.flit[0].bits.head :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1)
node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
when io.in.flit[0].bits.tail :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)
node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T_4 :
node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0))
node _T_6 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_7 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_8 = and(_T_6, _T_7)
node _T_9 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_10 = and(_T_8, _T_9)
node _T_11 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_12 = and(_T_10, _T_11)
node _T_13 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_14 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_15 = and(_T_13, _T_14)
node _T_16 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_19 = and(_T_17, _T_18)
node _T_20 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_21 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_22 = and(_T_20, _T_21)
node _T_23 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_24 = and(_T_22, _T_23)
node _T_25 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_26 = and(_T_24, _T_25)
node _T_27 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_28 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_29 = and(_T_27, _T_28)
node _T_30 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_31 = and(_T_29, _T_30)
node _T_32 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_33 = and(_T_31, _T_32)
node _T_34 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_35 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_36 = and(_T_34, _T_35)
node _T_37 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_38 = and(_T_36, _T_37)
node _T_39 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_40 = and(_T_38, _T_39)
node _T_41 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_42 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_45 = and(_T_43, _T_44)
node _T_46 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_47 = and(_T_45, _T_46)
node _T_48 = or(_T_12, _T_19)
node _T_49 = or(_T_48, _T_26)
node _T_50 = or(_T_49, _T_33)
node _T_51 = or(_T_50, _T_40)
node _T_52 = or(_T_51, _T_47)
node _T_53 = or(_T_5, _T_52)
node _T_54 = asUInt(reset)
node _T_55 = eq(_T_54, UInt<1>(0h0))
when _T_55 :
node _T_56 = eq(_T_53, UInt<1>(0h0))
when _T_56 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1
assert(clock, _T_53, UInt<1>(0h1), "") : assert_1
node _T_57 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1))
node _T_58 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_59 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_60 = and(_T_58, _T_59)
node _T_61 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_62 = and(_T_60, _T_61)
node _T_63 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_64 = and(_T_62, _T_63)
node _T_65 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_66 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_67 = and(_T_65, _T_66)
node _T_68 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_69 = and(_T_67, _T_68)
node _T_70 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_71 = and(_T_69, _T_70)
node _T_72 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_73 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_74 = and(_T_72, _T_73)
node _T_75 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_76 = and(_T_74, _T_75)
node _T_77 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_78 = and(_T_76, _T_77)
node _T_79 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_80 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_81 = and(_T_79, _T_80)
node _T_82 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_83 = and(_T_81, _T_82)
node _T_84 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_85 = and(_T_83, _T_84)
node _T_86 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_87 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_88 = and(_T_86, _T_87)
node _T_89 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_90 = and(_T_88, _T_89)
node _T_91 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_92 = and(_T_90, _T_91)
node _T_93 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_94 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_95 = and(_T_93, _T_94)
node _T_96 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_97 = and(_T_95, _T_96)
node _T_98 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_99 = and(_T_97, _T_98)
node _T_100 = or(_T_64, _T_71)
node _T_101 = or(_T_100, _T_78)
node _T_102 = or(_T_101, _T_85)
node _T_103 = or(_T_102, _T_92)
node _T_104 = or(_T_103, _T_99)
node _T_105 = or(_T_57, _T_104)
node _T_106 = asUInt(reset)
node _T_107 = eq(_T_106, UInt<1>(0h0))
when _T_107 :
node _T_108 = eq(_T_105, UInt<1>(0h0))
when _T_108 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2
assert(clock, _T_105, UInt<1>(0h1), "") : assert_2
node _T_109 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2))
node _T_110 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_111 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_112 = and(_T_110, _T_111)
node _T_113 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_114 = and(_T_112, _T_113)
node _T_115 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_116 = and(_T_114, _T_115)
node _T_117 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_118 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_119 = and(_T_117, _T_118)
node _T_120 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_121 = and(_T_119, _T_120)
node _T_122 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_123 = and(_T_121, _T_122)
node _T_124 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_125 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_126 = and(_T_124, _T_125)
node _T_127 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_128 = and(_T_126, _T_127)
node _T_129 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_130 = and(_T_128, _T_129)
node _T_131 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_132 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_133 = and(_T_131, _T_132)
node _T_134 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_135 = and(_T_133, _T_134)
node _T_136 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_137 = and(_T_135, _T_136)
node _T_138 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_139 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_140 = and(_T_138, _T_139)
node _T_141 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_142 = and(_T_140, _T_141)
node _T_143 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_144 = and(_T_142, _T_143)
node _T_145 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_146 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_147 = and(_T_145, _T_146)
node _T_148 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_149 = and(_T_147, _T_148)
node _T_150 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_151 = and(_T_149, _T_150)
node _T_152 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_153 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_154 = and(_T_152, _T_153)
node _T_155 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_156 = and(_T_154, _T_155)
node _T_157 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_158 = and(_T_156, _T_157)
node _T_159 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_160 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_161 = and(_T_159, _T_160)
node _T_162 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_163 = and(_T_161, _T_162)
node _T_164 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_165 = and(_T_163, _T_164)
node _T_166 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_167 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_168 = and(_T_166, _T_167)
node _T_169 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_170 = and(_T_168, _T_169)
node _T_171 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_172 = and(_T_170, _T_171)
node _T_173 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_174 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_175 = and(_T_173, _T_174)
node _T_176 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_177 = and(_T_175, _T_176)
node _T_178 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_179 = and(_T_177, _T_178)
node _T_180 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_181 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_182 = and(_T_180, _T_181)
node _T_183 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_184 = and(_T_182, _T_183)
node _T_185 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_186 = and(_T_184, _T_185)
node _T_187 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_188 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_189 = and(_T_187, _T_188)
node _T_190 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_191 = and(_T_189, _T_190)
node _T_192 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_193 = and(_T_191, _T_192)
node _T_194 = or(_T_116, _T_123)
node _T_195 = or(_T_194, _T_130)
node _T_196 = or(_T_195, _T_137)
node _T_197 = or(_T_196, _T_144)
node _T_198 = or(_T_197, _T_151)
node _T_199 = or(_T_198, _T_158)
node _T_200 = or(_T_199, _T_165)
node _T_201 = or(_T_200, _T_172)
node _T_202 = or(_T_201, _T_179)
node _T_203 = or(_T_202, _T_186)
node _T_204 = or(_T_203, _T_193)
node _T_205 = or(_T_109, _T_204)
node _T_206 = asUInt(reset)
node _T_207 = eq(_T_206, UInt<1>(0h0))
when _T_207 :
node _T_208 = eq(_T_205, UInt<1>(0h0))
when _T_208 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3
assert(clock, _T_205, UInt<1>(0h1), "") : assert_3
node _T_209 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3))
node _T_210 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_211 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_212 = and(_T_210, _T_211)
node _T_213 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_214 = and(_T_212, _T_213)
node _T_215 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_216 = and(_T_214, _T_215)
node _T_217 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_218 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_219 = and(_T_217, _T_218)
node _T_220 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_221 = and(_T_219, _T_220)
node _T_222 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_223 = and(_T_221, _T_222)
node _T_224 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_225 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_226 = and(_T_224, _T_225)
node _T_227 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_228 = and(_T_226, _T_227)
node _T_229 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_230 = and(_T_228, _T_229)
node _T_231 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_232 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_233 = and(_T_231, _T_232)
node _T_234 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_235 = and(_T_233, _T_234)
node _T_236 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_237 = and(_T_235, _T_236)
node _T_238 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_239 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_240 = and(_T_238, _T_239)
node _T_241 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_242 = and(_T_240, _T_241)
node _T_243 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_244 = and(_T_242, _T_243)
node _T_245 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_246 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_247 = and(_T_245, _T_246)
node _T_248 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_249 = and(_T_247, _T_248)
node _T_250 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_251 = and(_T_249, _T_250)
node _T_252 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_253 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_254 = and(_T_252, _T_253)
node _T_255 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_256 = and(_T_254, _T_255)
node _T_257 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_258 = and(_T_256, _T_257)
node _T_259 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_260 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_261 = and(_T_259, _T_260)
node _T_262 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_263 = and(_T_261, _T_262)
node _T_264 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_265 = and(_T_263, _T_264)
node _T_266 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_267 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_268 = and(_T_266, _T_267)
node _T_269 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_270 = and(_T_268, _T_269)
node _T_271 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_272 = and(_T_270, _T_271)
node _T_273 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_274 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_275 = and(_T_273, _T_274)
node _T_276 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_277 = and(_T_275, _T_276)
node _T_278 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_279 = and(_T_277, _T_278)
node _T_280 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_281 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_282 = and(_T_280, _T_281)
node _T_283 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_284 = and(_T_282, _T_283)
node _T_285 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_286 = and(_T_284, _T_285)
node _T_287 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_288 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_289 = and(_T_287, _T_288)
node _T_290 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_291 = and(_T_289, _T_290)
node _T_292 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_293 = and(_T_291, _T_292)
node _T_294 = or(_T_216, _T_223)
node _T_295 = or(_T_294, _T_230)
node _T_296 = or(_T_295, _T_237)
node _T_297 = or(_T_296, _T_244)
node _T_298 = or(_T_297, _T_251)
node _T_299 = or(_T_298, _T_258)
node _T_300 = or(_T_299, _T_265)
node _T_301 = or(_T_300, _T_272)
node _T_302 = or(_T_301, _T_279)
node _T_303 = or(_T_302, _T_286)
node _T_304 = or(_T_303, _T_293)
node _T_305 = or(_T_209, _T_304)
node _T_306 = asUInt(reset)
node _T_307 = eq(_T_306, UInt<1>(0h0))
when _T_307 :
node _T_308 = eq(_T_305, UInt<1>(0h0))
when _T_308 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_4
assert(clock, _T_305, UInt<1>(0h1), "") : assert_4
node _T_309 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h4))
node _T_310 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_311 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_312 = and(_T_310, _T_311)
node _T_313 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_314 = and(_T_312, _T_313)
node _T_315 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_316 = and(_T_314, _T_315)
node _T_317 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_318 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_319 = and(_T_317, _T_318)
node _T_320 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_321 = and(_T_319, _T_320)
node _T_322 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_323 = and(_T_321, _T_322)
node _T_324 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_325 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_326 = and(_T_324, _T_325)
node _T_327 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_328 = and(_T_326, _T_327)
node _T_329 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_330 = and(_T_328, _T_329)
node _T_331 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_332 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_333 = and(_T_331, _T_332)
node _T_334 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_335 = and(_T_333, _T_334)
node _T_336 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_337 = and(_T_335, _T_336)
node _T_338 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_339 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_340 = and(_T_338, _T_339)
node _T_341 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_342 = and(_T_340, _T_341)
node _T_343 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_344 = and(_T_342, _T_343)
node _T_345 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_346 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_347 = and(_T_345, _T_346)
node _T_348 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_349 = and(_T_347, _T_348)
node _T_350 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_351 = and(_T_349, _T_350)
node _T_352 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_353 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_354 = and(_T_352, _T_353)
node _T_355 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_356 = and(_T_354, _T_355)
node _T_357 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_358 = and(_T_356, _T_357)
node _T_359 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_360 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_361 = and(_T_359, _T_360)
node _T_362 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_363 = and(_T_361, _T_362)
node _T_364 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_365 = and(_T_363, _T_364)
node _T_366 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_367 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_368 = and(_T_366, _T_367)
node _T_369 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_370 = and(_T_368, _T_369)
node _T_371 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_372 = and(_T_370, _T_371)
node _T_373 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_374 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_375 = and(_T_373, _T_374)
node _T_376 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_377 = and(_T_375, _T_376)
node _T_378 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_379 = and(_T_377, _T_378)
node _T_380 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_381 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_382 = and(_T_380, _T_381)
node _T_383 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_384 = and(_T_382, _T_383)
node _T_385 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_386 = and(_T_384, _T_385)
node _T_387 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_388 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_389 = and(_T_387, _T_388)
node _T_390 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_391 = and(_T_389, _T_390)
node _T_392 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_393 = and(_T_391, _T_392)
node _T_394 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_395 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3))
node _T_396 = and(_T_394, _T_395)
node _T_397 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_398 = and(_T_396, _T_397)
node _T_399 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_400 = and(_T_398, _T_399)
node _T_401 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_402 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_403 = and(_T_401, _T_402)
node _T_404 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_405 = and(_T_403, _T_404)
node _T_406 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_407 = and(_T_405, _T_406)
node _T_408 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_409 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_410 = and(_T_408, _T_409)
node _T_411 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_412 = and(_T_410, _T_411)
node _T_413 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_414 = and(_T_412, _T_413)
node _T_415 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_416 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_417 = and(_T_415, _T_416)
node _T_418 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_419 = and(_T_417, _T_418)
node _T_420 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_421 = and(_T_419, _T_420)
node _T_422 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_423 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_424 = and(_T_422, _T_423)
node _T_425 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_426 = and(_T_424, _T_425)
node _T_427 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_428 = and(_T_426, _T_427)
node _T_429 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_430 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_431 = and(_T_429, _T_430)
node _T_432 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_433 = and(_T_431, _T_432)
node _T_434 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_435 = and(_T_433, _T_434)
node _T_436 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_437 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_438 = and(_T_436, _T_437)
node _T_439 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_440 = and(_T_438, _T_439)
node _T_441 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_442 = and(_T_440, _T_441)
node _T_443 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_444 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_445 = and(_T_443, _T_444)
node _T_446 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_447 = and(_T_445, _T_446)
node _T_448 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_449 = and(_T_447, _T_448)
node _T_450 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_451 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_452 = and(_T_450, _T_451)
node _T_453 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_454 = and(_T_452, _T_453)
node _T_455 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_456 = and(_T_454, _T_455)
node _T_457 = or(_T_316, _T_323)
node _T_458 = or(_T_457, _T_330)
node _T_459 = or(_T_458, _T_337)
node _T_460 = or(_T_459, _T_344)
node _T_461 = or(_T_460, _T_351)
node _T_462 = or(_T_461, _T_358)
node _T_463 = or(_T_462, _T_365)
node _T_464 = or(_T_463, _T_372)
node _T_465 = or(_T_464, _T_379)
node _T_466 = or(_T_465, _T_386)
node _T_467 = or(_T_466, _T_393)
node _T_468 = or(_T_467, _T_400)
node _T_469 = or(_T_468, _T_407)
node _T_470 = or(_T_469, _T_414)
node _T_471 = or(_T_470, _T_421)
node _T_472 = or(_T_471, _T_428)
node _T_473 = or(_T_472, _T_435)
node _T_474 = or(_T_473, _T_442)
node _T_475 = or(_T_474, _T_449)
node _T_476 = or(_T_475, _T_456)
node _T_477 = or(_T_309, _T_476)
node _T_478 = asUInt(reset)
node _T_479 = eq(_T_478, UInt<1>(0h0))
when _T_479 :
node _T_480 = eq(_T_477, UInt<1>(0h0))
when _T_480 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_5
assert(clock, _T_477, UInt<1>(0h1), "") : assert_5
node _T_481 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h5))
node _T_482 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_483 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_484 = and(_T_482, _T_483)
node _T_485 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_486 = and(_T_484, _T_485)
node _T_487 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_488 = and(_T_486, _T_487)
node _T_489 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_490 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_491 = and(_T_489, _T_490)
node _T_492 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_493 = and(_T_491, _T_492)
node _T_494 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_495 = and(_T_493, _T_494)
node _T_496 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_497 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_498 = and(_T_496, _T_497)
node _T_499 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_500 = and(_T_498, _T_499)
node _T_501 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_502 = and(_T_500, _T_501)
node _T_503 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_504 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_505 = and(_T_503, _T_504)
node _T_506 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_507 = and(_T_505, _T_506)
node _T_508 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_509 = and(_T_507, _T_508)
node _T_510 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_511 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_512 = and(_T_510, _T_511)
node _T_513 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_514 = and(_T_512, _T_513)
node _T_515 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_516 = and(_T_514, _T_515)
node _T_517 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_518 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_519 = and(_T_517, _T_518)
node _T_520 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_521 = and(_T_519, _T_520)
node _T_522 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_523 = and(_T_521, _T_522)
node _T_524 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_525 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_526 = and(_T_524, _T_525)
node _T_527 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_528 = and(_T_526, _T_527)
node _T_529 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_530 = and(_T_528, _T_529)
node _T_531 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_532 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_533 = and(_T_531, _T_532)
node _T_534 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_535 = and(_T_533, _T_534)
node _T_536 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_537 = and(_T_535, _T_536)
node _T_538 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_539 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_540 = and(_T_538, _T_539)
node _T_541 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_542 = and(_T_540, _T_541)
node _T_543 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_544 = and(_T_542, _T_543)
node _T_545 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_546 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_547 = and(_T_545, _T_546)
node _T_548 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_549 = and(_T_547, _T_548)
node _T_550 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_551 = and(_T_549, _T_550)
node _T_552 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_553 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_554 = and(_T_552, _T_553)
node _T_555 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_556 = and(_T_554, _T_555)
node _T_557 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_558 = and(_T_556, _T_557)
node _T_559 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_560 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_561 = and(_T_559, _T_560)
node _T_562 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_563 = and(_T_561, _T_562)
node _T_564 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_565 = and(_T_563, _T_564)
node _T_566 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_567 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3))
node _T_568 = and(_T_566, _T_567)
node _T_569 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_570 = and(_T_568, _T_569)
node _T_571 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_572 = and(_T_570, _T_571)
node _T_573 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_574 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_575 = and(_T_573, _T_574)
node _T_576 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_577 = and(_T_575, _T_576)
node _T_578 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_579 = and(_T_577, _T_578)
node _T_580 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_581 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_582 = and(_T_580, _T_581)
node _T_583 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_584 = and(_T_582, _T_583)
node _T_585 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_586 = and(_T_584, _T_585)
node _T_587 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_588 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_589 = and(_T_587, _T_588)
node _T_590 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_591 = and(_T_589, _T_590)
node _T_592 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_593 = and(_T_591, _T_592)
node _T_594 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_595 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_596 = and(_T_594, _T_595)
node _T_597 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_598 = and(_T_596, _T_597)
node _T_599 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_600 = and(_T_598, _T_599)
node _T_601 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_602 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_603 = and(_T_601, _T_602)
node _T_604 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_605 = and(_T_603, _T_604)
node _T_606 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_607 = and(_T_605, _T_606)
node _T_608 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_609 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_610 = and(_T_608, _T_609)
node _T_611 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_612 = and(_T_610, _T_611)
node _T_613 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_614 = and(_T_612, _T_613)
node _T_615 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_616 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_617 = and(_T_615, _T_616)
node _T_618 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_619 = and(_T_617, _T_618)
node _T_620 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_621 = and(_T_619, _T_620)
node _T_622 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_623 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_624 = and(_T_622, _T_623)
node _T_625 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_626 = and(_T_624, _T_625)
node _T_627 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_628 = and(_T_626, _T_627)
node _T_629 = or(_T_488, _T_495)
node _T_630 = or(_T_629, _T_502)
node _T_631 = or(_T_630, _T_509)
node _T_632 = or(_T_631, _T_516)
node _T_633 = or(_T_632, _T_523)
node _T_634 = or(_T_633, _T_530)
node _T_635 = or(_T_634, _T_537)
node _T_636 = or(_T_635, _T_544)
node _T_637 = or(_T_636, _T_551)
node _T_638 = or(_T_637, _T_558)
node _T_639 = or(_T_638, _T_565)
node _T_640 = or(_T_639, _T_572)
node _T_641 = or(_T_640, _T_579)
node _T_642 = or(_T_641, _T_586)
node _T_643 = or(_T_642, _T_593)
node _T_644 = or(_T_643, _T_600)
node _T_645 = or(_T_644, _T_607)
node _T_646 = or(_T_645, _T_614)
node _T_647 = or(_T_646, _T_621)
node _T_648 = or(_T_647, _T_628)
node _T_649 = or(_T_481, _T_648)
node _T_650 = asUInt(reset)
node _T_651 = eq(_T_650, UInt<1>(0h0))
when _T_651 :
node _T_652 = eq(_T_649, UInt<1>(0h0))
when _T_652 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_6
assert(clock, _T_649, UInt<1>(0h1), "") : assert_6
node _T_653 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h6))
node _T_654 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_655 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_656 = and(_T_654, _T_655)
node _T_657 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_658 = and(_T_656, _T_657)
node _T_659 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_660 = and(_T_658, _T_659)
node _T_661 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_662 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_663 = and(_T_661, _T_662)
node _T_664 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_665 = and(_T_663, _T_664)
node _T_666 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_667 = and(_T_665, _T_666)
node _T_668 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_669 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_670 = and(_T_668, _T_669)
node _T_671 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_672 = and(_T_670, _T_671)
node _T_673 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_674 = and(_T_672, _T_673)
node _T_675 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_676 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_677 = and(_T_675, _T_676)
node _T_678 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_679 = and(_T_677, _T_678)
node _T_680 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_681 = and(_T_679, _T_680)
node _T_682 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_683 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_684 = and(_T_682, _T_683)
node _T_685 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_686 = and(_T_684, _T_685)
node _T_687 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_688 = and(_T_686, _T_687)
node _T_689 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_690 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_691 = and(_T_689, _T_690)
node _T_692 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_693 = and(_T_691, _T_692)
node _T_694 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_695 = and(_T_693, _T_694)
node _T_696 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_697 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_698 = and(_T_696, _T_697)
node _T_699 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_700 = and(_T_698, _T_699)
node _T_701 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_702 = and(_T_700, _T_701)
node _T_703 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_704 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_705 = and(_T_703, _T_704)
node _T_706 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_707 = and(_T_705, _T_706)
node _T_708 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_709 = and(_T_707, _T_708)
node _T_710 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_711 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_712 = and(_T_710, _T_711)
node _T_713 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_714 = and(_T_712, _T_713)
node _T_715 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_716 = and(_T_714, _T_715)
node _T_717 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_718 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_719 = and(_T_717, _T_718)
node _T_720 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_721 = and(_T_719, _T_720)
node _T_722 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_723 = and(_T_721, _T_722)
node _T_724 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_725 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_726 = and(_T_724, _T_725)
node _T_727 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_728 = and(_T_726, _T_727)
node _T_729 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_730 = and(_T_728, _T_729)
node _T_731 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_732 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_733 = and(_T_731, _T_732)
node _T_734 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_735 = and(_T_733, _T_734)
node _T_736 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_737 = and(_T_735, _T_736)
node _T_738 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_739 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3))
node _T_740 = and(_T_738, _T_739)
node _T_741 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_742 = and(_T_740, _T_741)
node _T_743 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_744 = and(_T_742, _T_743)
node _T_745 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_746 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_747 = and(_T_745, _T_746)
node _T_748 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_749 = and(_T_747, _T_748)
node _T_750 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_751 = and(_T_749, _T_750)
node _T_752 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_753 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_754 = and(_T_752, _T_753)
node _T_755 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_756 = and(_T_754, _T_755)
node _T_757 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_758 = and(_T_756, _T_757)
node _T_759 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_760 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_761 = and(_T_759, _T_760)
node _T_762 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_763 = and(_T_761, _T_762)
node _T_764 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_765 = and(_T_763, _T_764)
node _T_766 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_767 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_768 = and(_T_766, _T_767)
node _T_769 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_770 = and(_T_768, _T_769)
node _T_771 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_772 = and(_T_770, _T_771)
node _T_773 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_774 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_775 = and(_T_773, _T_774)
node _T_776 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_777 = and(_T_775, _T_776)
node _T_778 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_779 = and(_T_777, _T_778)
node _T_780 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_781 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_782 = and(_T_780, _T_781)
node _T_783 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_784 = and(_T_782, _T_783)
node _T_785 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_786 = and(_T_784, _T_785)
node _T_787 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_788 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_789 = and(_T_787, _T_788)
node _T_790 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_791 = and(_T_789, _T_790)
node _T_792 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_793 = and(_T_791, _T_792)
node _T_794 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_795 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_796 = and(_T_794, _T_795)
node _T_797 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_798 = and(_T_796, _T_797)
node _T_799 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_800 = and(_T_798, _T_799)
node _T_801 = or(_T_660, _T_667)
node _T_802 = or(_T_801, _T_674)
node _T_803 = or(_T_802, _T_681)
node _T_804 = or(_T_803, _T_688)
node _T_805 = or(_T_804, _T_695)
node _T_806 = or(_T_805, _T_702)
node _T_807 = or(_T_806, _T_709)
node _T_808 = or(_T_807, _T_716)
node _T_809 = or(_T_808, _T_723)
node _T_810 = or(_T_809, _T_730)
node _T_811 = or(_T_810, _T_737)
node _T_812 = or(_T_811, _T_744)
node _T_813 = or(_T_812, _T_751)
node _T_814 = or(_T_813, _T_758)
node _T_815 = or(_T_814, _T_765)
node _T_816 = or(_T_815, _T_772)
node _T_817 = or(_T_816, _T_779)
node _T_818 = or(_T_817, _T_786)
node _T_819 = or(_T_818, _T_793)
node _T_820 = or(_T_819, _T_800)
node _T_821 = or(_T_653, _T_820)
node _T_822 = asUInt(reset)
node _T_823 = eq(_T_822, UInt<1>(0h0))
when _T_823 :
node _T_824 = eq(_T_821, UInt<1>(0h0))
when _T_824 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_7
assert(clock, _T_821, UInt<1>(0h1), "") : assert_7
node _T_825 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h7))
node _T_826 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_827 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_828 = and(_T_826, _T_827)
node _T_829 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_830 = and(_T_828, _T_829)
node _T_831 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_832 = and(_T_830, _T_831)
node _T_833 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_834 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_835 = and(_T_833, _T_834)
node _T_836 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_837 = and(_T_835, _T_836)
node _T_838 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_839 = and(_T_837, _T_838)
node _T_840 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_841 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_842 = and(_T_840, _T_841)
node _T_843 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_844 = and(_T_842, _T_843)
node _T_845 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_846 = and(_T_844, _T_845)
node _T_847 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_848 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_849 = and(_T_847, _T_848)
node _T_850 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_851 = and(_T_849, _T_850)
node _T_852 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_853 = and(_T_851, _T_852)
node _T_854 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_855 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_856 = and(_T_854, _T_855)
node _T_857 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_858 = and(_T_856, _T_857)
node _T_859 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_860 = and(_T_858, _T_859)
node _T_861 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_862 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_863 = and(_T_861, _T_862)
node _T_864 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_865 = and(_T_863, _T_864)
node _T_866 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_867 = and(_T_865, _T_866)
node _T_868 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_869 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_870 = and(_T_868, _T_869)
node _T_871 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_872 = and(_T_870, _T_871)
node _T_873 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_874 = and(_T_872, _T_873)
node _T_875 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_876 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_877 = and(_T_875, _T_876)
node _T_878 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_879 = and(_T_877, _T_878)
node _T_880 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_881 = and(_T_879, _T_880)
node _T_882 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_883 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_884 = and(_T_882, _T_883)
node _T_885 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_886 = and(_T_884, _T_885)
node _T_887 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_888 = and(_T_886, _T_887)
node _T_889 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_890 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_891 = and(_T_889, _T_890)
node _T_892 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_893 = and(_T_891, _T_892)
node _T_894 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_895 = and(_T_893, _T_894)
node _T_896 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_897 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_898 = and(_T_896, _T_897)
node _T_899 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_900 = and(_T_898, _T_899)
node _T_901 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_902 = and(_T_900, _T_901)
node _T_903 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_904 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_905 = and(_T_903, _T_904)
node _T_906 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_907 = and(_T_905, _T_906)
node _T_908 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_909 = and(_T_907, _T_908)
node _T_910 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_911 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3))
node _T_912 = and(_T_910, _T_911)
node _T_913 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_914 = and(_T_912, _T_913)
node _T_915 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_916 = and(_T_914, _T_915)
node _T_917 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_918 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_919 = and(_T_917, _T_918)
node _T_920 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_921 = and(_T_919, _T_920)
node _T_922 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_923 = and(_T_921, _T_922)
node _T_924 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_925 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_926 = and(_T_924, _T_925)
node _T_927 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_928 = and(_T_926, _T_927)
node _T_929 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_930 = and(_T_928, _T_929)
node _T_931 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_932 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_933 = and(_T_931, _T_932)
node _T_934 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_935 = and(_T_933, _T_934)
node _T_936 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_937 = and(_T_935, _T_936)
node _T_938 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_939 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_940 = and(_T_938, _T_939)
node _T_941 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_942 = and(_T_940, _T_941)
node _T_943 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_944 = and(_T_942, _T_943)
node _T_945 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_946 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_947 = and(_T_945, _T_946)
node _T_948 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_949 = and(_T_947, _T_948)
node _T_950 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_951 = and(_T_949, _T_950)
node _T_952 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_953 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_954 = and(_T_952, _T_953)
node _T_955 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_956 = and(_T_954, _T_955)
node _T_957 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_958 = and(_T_956, _T_957)
node _T_959 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_960 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_961 = and(_T_959, _T_960)
node _T_962 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_963 = and(_T_961, _T_962)
node _T_964 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_965 = and(_T_963, _T_964)
node _T_966 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_967 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_968 = and(_T_966, _T_967)
node _T_969 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_970 = and(_T_968, _T_969)
node _T_971 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_972 = and(_T_970, _T_971)
node _T_973 = or(_T_832, _T_839)
node _T_974 = or(_T_973, _T_846)
node _T_975 = or(_T_974, _T_853)
node _T_976 = or(_T_975, _T_860)
node _T_977 = or(_T_976, _T_867)
node _T_978 = or(_T_977, _T_874)
node _T_979 = or(_T_978, _T_881)
node _T_980 = or(_T_979, _T_888)
node _T_981 = or(_T_980, _T_895)
node _T_982 = or(_T_981, _T_902)
node _T_983 = or(_T_982, _T_909)
node _T_984 = or(_T_983, _T_916)
node _T_985 = or(_T_984, _T_923)
node _T_986 = or(_T_985, _T_930)
node _T_987 = or(_T_986, _T_937)
node _T_988 = or(_T_987, _T_944)
node _T_989 = or(_T_988, _T_951)
node _T_990 = or(_T_989, _T_958)
node _T_991 = or(_T_990, _T_965)
node _T_992 = or(_T_991, _T_972)
node _T_993 = or(_T_825, _T_992)
node _T_994 = asUInt(reset)
node _T_995 = eq(_T_994, UInt<1>(0h0))
when _T_995 :
node _T_996 = eq(_T_993, UInt<1>(0h0))
when _T_996 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_8
assert(clock, _T_993, UInt<1>(0h1), "") : assert_8 | module NoCMonitor_51( // @[Monitor.scala:11:7]
input clock, // @[Monitor.scala:11:7]
input reset, // @[Monitor.scala:11:7]
input io_in_flit_0_valid, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_head, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14]
input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14]
input [4:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14]
input [2:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14]
);
reg in_flight_0; // @[Monitor.scala:16:26]
reg in_flight_1; // @[Monitor.scala:16:26]
reg in_flight_2; // @[Monitor.scala:16:26]
reg in_flight_3; // @[Monitor.scala:16:26]
reg in_flight_4; // @[Monitor.scala:16:26]
reg in_flight_5; // @[Monitor.scala:16:26]
reg in_flight_6; // @[Monitor.scala:16:26]
reg in_flight_7; // @[Monitor.scala:16:26] |
Generate the Verilog code corresponding to this FIRRTL code module TLNoC_2_router_0ClockSinkDomain :
output auto : { routers_debug_out : { va_stall : UInt[5], sa_stall : UInt[5]}, routers_egress_nodes_out_5 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, routers_egress_nodes_out_4 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, routers_egress_nodes_out_3 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, routers_egress_nodes_out_2 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, routers_egress_nodes_out_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, routers_egress_nodes_out_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, flip routers_ingress_nodes_in_3 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip routers_ingress_nodes_in_2 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip routers_ingress_nodes_in_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip routers_ingress_nodes_in_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, routers_source_nodes_out : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}, flip routers_dest_nodes_in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}, flip clock_in : { clock : Clock, reset : Reset}}
output clock : Clock
output reset : Reset
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
inst routers of Router_47
connect routers.clock, childClock
connect routers.reset, childReset
wire clockNodeIn : { clock : Clock, reset : Reset}
invalidate clockNodeIn.reset
invalidate clockNodeIn.clock
connect clockNodeIn, auto.clock_in
connect routers.auto.dest_nodes_in, auto.routers_dest_nodes_in
connect routers.auto.source_nodes_out.vc_free, auto.routers_source_nodes_out.vc_free
connect routers.auto.source_nodes_out.credit_return, auto.routers_source_nodes_out.credit_return
connect auto.routers_source_nodes_out.flit, routers.auto.source_nodes_out.flit
connect routers.auto.ingress_nodes_in_0, auto.routers_ingress_nodes_in_0
connect routers.auto.ingress_nodes_in_1, auto.routers_ingress_nodes_in_1
connect routers.auto.ingress_nodes_in_2, auto.routers_ingress_nodes_in_2
connect routers.auto.ingress_nodes_in_3, auto.routers_ingress_nodes_in_3
connect auto.routers_egress_nodes_out_0.flit.bits, routers.auto.egress_nodes_out_0.flit.bits
connect auto.routers_egress_nodes_out_0.flit.valid, routers.auto.egress_nodes_out_0.flit.valid
connect routers.auto.egress_nodes_out_0.flit.ready, auto.routers_egress_nodes_out_0.flit.ready
connect auto.routers_egress_nodes_out_1.flit.bits, routers.auto.egress_nodes_out_1.flit.bits
connect auto.routers_egress_nodes_out_1.flit.valid, routers.auto.egress_nodes_out_1.flit.valid
connect routers.auto.egress_nodes_out_1.flit.ready, auto.routers_egress_nodes_out_1.flit.ready
connect auto.routers_egress_nodes_out_2.flit.bits, routers.auto.egress_nodes_out_2.flit.bits
connect auto.routers_egress_nodes_out_2.flit.valid, routers.auto.egress_nodes_out_2.flit.valid
connect routers.auto.egress_nodes_out_2.flit.ready, auto.routers_egress_nodes_out_2.flit.ready
connect auto.routers_egress_nodes_out_3.flit.bits, routers.auto.egress_nodes_out_3.flit.bits
connect auto.routers_egress_nodes_out_3.flit.valid, routers.auto.egress_nodes_out_3.flit.valid
connect routers.auto.egress_nodes_out_3.flit.ready, auto.routers_egress_nodes_out_3.flit.ready
connect auto.routers_egress_nodes_out_4.flit.bits, routers.auto.egress_nodes_out_4.flit.bits
connect auto.routers_egress_nodes_out_4.flit.valid, routers.auto.egress_nodes_out_4.flit.valid
connect routers.auto.egress_nodes_out_4.flit.ready, auto.routers_egress_nodes_out_4.flit.ready
connect auto.routers_egress_nodes_out_5.flit.bits, routers.auto.egress_nodes_out_5.flit.bits
connect auto.routers_egress_nodes_out_5.flit.valid, routers.auto.egress_nodes_out_5.flit.valid
connect routers.auto.egress_nodes_out_5.flit.ready, auto.routers_egress_nodes_out_5.flit.ready
connect auto.routers_debug_out, routers.auto.debug_out
connect childClock, clockNodeIn.clock
connect childReset, clockNodeIn.reset
connect clock, clockNodeIn.clock
connect reset, clockNodeIn.reset | module TLNoC_2_router_0ClockSinkDomain( // @[ClockDomain.scala:14:9]
output [3:0] auto_routers_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_debug_out_va_stall_4, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_debug_out_sa_stall_4, // @[LazyModuleImp.scala:107:25]
input auto_routers_egress_nodes_out_5_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_5_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_5_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_5_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input auto_routers_egress_nodes_out_4_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_4_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_4_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_4_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input auto_routers_egress_nodes_out_3_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_3_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_3_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_3_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_routers_egress_nodes_out_3_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input auto_routers_egress_nodes_out_2_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_2_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_2_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_2_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input auto_routers_egress_nodes_out_1_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_1_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_1_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input auto_routers_egress_nodes_out_0_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_0_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_0_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_routers_egress_nodes_out_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
output auto_routers_ingress_nodes_in_3_flit_ready, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_3_flit_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_3_flit_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_3_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_routers_ingress_nodes_in_3_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_ingress_nodes_in_3_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25]
output auto_routers_ingress_nodes_in_1_flit_ready, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_1_flit_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_1_flit_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_routers_ingress_nodes_in_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_ingress_nodes_in_1_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_routers_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [9:0] auto_routers_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25]
input [9:0] auto_routers_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_routers_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [9:0] auto_routers_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25]
output [9:0] auto_routers_dest_nodes_in_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_reset // @[LazyModuleImp.scala:107:25]
);
Router_47 routers ( // @[NoC.scala:67:22]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_debug_out_va_stall_0 (auto_routers_debug_out_va_stall_0),
.auto_debug_out_va_stall_2 (auto_routers_debug_out_va_stall_2),
.auto_debug_out_va_stall_4 (auto_routers_debug_out_va_stall_4),
.auto_debug_out_sa_stall_0 (auto_routers_debug_out_sa_stall_0),
.auto_debug_out_sa_stall_2 (auto_routers_debug_out_sa_stall_2),
.auto_debug_out_sa_stall_4 (auto_routers_debug_out_sa_stall_4),
.auto_egress_nodes_out_5_flit_ready (auto_routers_egress_nodes_out_5_flit_ready),
.auto_egress_nodes_out_5_flit_valid (auto_routers_egress_nodes_out_5_flit_valid),
.auto_egress_nodes_out_5_flit_bits_head (auto_routers_egress_nodes_out_5_flit_bits_head),
.auto_egress_nodes_out_5_flit_bits_tail (auto_routers_egress_nodes_out_5_flit_bits_tail),
.auto_egress_nodes_out_4_flit_ready (auto_routers_egress_nodes_out_4_flit_ready),
.auto_egress_nodes_out_4_flit_valid (auto_routers_egress_nodes_out_4_flit_valid),
.auto_egress_nodes_out_4_flit_bits_head (auto_routers_egress_nodes_out_4_flit_bits_head),
.auto_egress_nodes_out_4_flit_bits_tail (auto_routers_egress_nodes_out_4_flit_bits_tail),
.auto_egress_nodes_out_3_flit_ready (auto_routers_egress_nodes_out_3_flit_ready),
.auto_egress_nodes_out_3_flit_valid (auto_routers_egress_nodes_out_3_flit_valid),
.auto_egress_nodes_out_3_flit_bits_head (auto_routers_egress_nodes_out_3_flit_bits_head),
.auto_egress_nodes_out_3_flit_bits_tail (auto_routers_egress_nodes_out_3_flit_bits_tail),
.auto_egress_nodes_out_3_flit_bits_payload (auto_routers_egress_nodes_out_3_flit_bits_payload),
.auto_egress_nodes_out_2_flit_ready (auto_routers_egress_nodes_out_2_flit_ready),
.auto_egress_nodes_out_2_flit_valid (auto_routers_egress_nodes_out_2_flit_valid),
.auto_egress_nodes_out_2_flit_bits_head (auto_routers_egress_nodes_out_2_flit_bits_head),
.auto_egress_nodes_out_2_flit_bits_tail (auto_routers_egress_nodes_out_2_flit_bits_tail),
.auto_egress_nodes_out_1_flit_ready (auto_routers_egress_nodes_out_1_flit_ready),
.auto_egress_nodes_out_1_flit_valid (auto_routers_egress_nodes_out_1_flit_valid),
.auto_egress_nodes_out_1_flit_bits_head (auto_routers_egress_nodes_out_1_flit_bits_head),
.auto_egress_nodes_out_1_flit_bits_tail (auto_routers_egress_nodes_out_1_flit_bits_tail),
.auto_egress_nodes_out_0_flit_ready (auto_routers_egress_nodes_out_0_flit_ready),
.auto_egress_nodes_out_0_flit_valid (auto_routers_egress_nodes_out_0_flit_valid),
.auto_egress_nodes_out_0_flit_bits_head (auto_routers_egress_nodes_out_0_flit_bits_head),
.auto_egress_nodes_out_0_flit_bits_tail (auto_routers_egress_nodes_out_0_flit_bits_tail),
.auto_egress_nodes_out_0_flit_bits_payload (auto_routers_egress_nodes_out_0_flit_bits_payload),
.auto_ingress_nodes_in_3_flit_ready (auto_routers_ingress_nodes_in_3_flit_ready),
.auto_ingress_nodes_in_3_flit_valid (auto_routers_ingress_nodes_in_3_flit_valid),
.auto_ingress_nodes_in_3_flit_bits_head (auto_routers_ingress_nodes_in_3_flit_bits_head),
.auto_ingress_nodes_in_3_flit_bits_tail (auto_routers_ingress_nodes_in_3_flit_bits_tail),
.auto_ingress_nodes_in_3_flit_bits_payload (auto_routers_ingress_nodes_in_3_flit_bits_payload),
.auto_ingress_nodes_in_3_flit_bits_egress_id (auto_routers_ingress_nodes_in_3_flit_bits_egress_id),
.auto_ingress_nodes_in_1_flit_ready (auto_routers_ingress_nodes_in_1_flit_ready),
.auto_ingress_nodes_in_1_flit_valid (auto_routers_ingress_nodes_in_1_flit_valid),
.auto_ingress_nodes_in_1_flit_bits_head (auto_routers_ingress_nodes_in_1_flit_bits_head),
.auto_ingress_nodes_in_1_flit_bits_tail (auto_routers_ingress_nodes_in_1_flit_bits_tail),
.auto_ingress_nodes_in_1_flit_bits_payload (auto_routers_ingress_nodes_in_1_flit_bits_payload),
.auto_ingress_nodes_in_1_flit_bits_egress_id (auto_routers_ingress_nodes_in_1_flit_bits_egress_id),
.auto_source_nodes_out_flit_0_valid (auto_routers_source_nodes_out_flit_0_valid),
.auto_source_nodes_out_flit_0_bits_head (auto_routers_source_nodes_out_flit_0_bits_head),
.auto_source_nodes_out_flit_0_bits_tail (auto_routers_source_nodes_out_flit_0_bits_tail),
.auto_source_nodes_out_flit_0_bits_payload (auto_routers_source_nodes_out_flit_0_bits_payload),
.auto_source_nodes_out_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id),
.auto_source_nodes_out_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node),
.auto_source_nodes_out_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id),
.auto_source_nodes_out_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node),
.auto_source_nodes_out_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id),
.auto_source_nodes_out_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_flit_0_bits_virt_channel_id),
.auto_source_nodes_out_credit_return (auto_routers_source_nodes_out_credit_return),
.auto_source_nodes_out_vc_free (auto_routers_source_nodes_out_vc_free),
.auto_dest_nodes_in_flit_0_valid (auto_routers_dest_nodes_in_flit_0_valid),
.auto_dest_nodes_in_flit_0_bits_head (auto_routers_dest_nodes_in_flit_0_bits_head),
.auto_dest_nodes_in_flit_0_bits_tail (auto_routers_dest_nodes_in_flit_0_bits_tail),
.auto_dest_nodes_in_flit_0_bits_payload (auto_routers_dest_nodes_in_flit_0_bits_payload),
.auto_dest_nodes_in_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id),
.auto_dest_nodes_in_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node),
.auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id),
.auto_dest_nodes_in_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node),
.auto_dest_nodes_in_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id),
.auto_dest_nodes_in_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id),
.auto_dest_nodes_in_credit_return (auto_routers_dest_nodes_in_credit_return),
.auto_dest_nodes_in_vc_free (auto_routers_dest_nodes_in_vc_free)
); // @[NoC.scala:67:22]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module SinkA_4 :
input clock : Clock
input reset : Reset
output io : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>}}, flip a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip pb_pop : { flip ready : UInt<1>, valid : UInt<1>, bits : { index : UInt<6>, last : UInt<1>}}, pb_beat : { data : UInt<128>, mask : UInt<16>, corrupt : UInt<1>}}
inst putbuffer of ListBuffer_PutBufferAEntry_q40_e40_4
connect putbuffer.clock, clock
connect putbuffer.reset, reset
regreset lists : UInt<40>, clock, reset, UInt<40>(0h0)
wire lists_set : UInt<40>
connect lists_set, UInt<40>(0h0)
wire lists_clr : UInt<40>
connect lists_clr, UInt<40>(0h0)
node _lists_T = or(lists, lists_set)
node _lists_T_1 = not(lists_clr)
node _lists_T_2 = and(_lists_T, _lists_T_1)
connect lists, _lists_T_2
node _free_T = andr(lists)
node free = eq(_free_T, UInt<1>(0h0))
node _freeOH_T = not(lists)
node _freeOH_T_1 = shl(_freeOH_T, 1)
node _freeOH_T_2 = bits(_freeOH_T_1, 39, 0)
node _freeOH_T_3 = or(_freeOH_T, _freeOH_T_2)
node _freeOH_T_4 = shl(_freeOH_T_3, 2)
node _freeOH_T_5 = bits(_freeOH_T_4, 39, 0)
node _freeOH_T_6 = or(_freeOH_T_3, _freeOH_T_5)
node _freeOH_T_7 = shl(_freeOH_T_6, 4)
node _freeOH_T_8 = bits(_freeOH_T_7, 39, 0)
node _freeOH_T_9 = or(_freeOH_T_6, _freeOH_T_8)
node _freeOH_T_10 = shl(_freeOH_T_9, 8)
node _freeOH_T_11 = bits(_freeOH_T_10, 39, 0)
node _freeOH_T_12 = or(_freeOH_T_9, _freeOH_T_11)
node _freeOH_T_13 = shl(_freeOH_T_12, 16)
node _freeOH_T_14 = bits(_freeOH_T_13, 39, 0)
node _freeOH_T_15 = or(_freeOH_T_12, _freeOH_T_14)
node _freeOH_T_16 = shl(_freeOH_T_15, 32)
node _freeOH_T_17 = bits(_freeOH_T_16, 39, 0)
node _freeOH_T_18 = or(_freeOH_T_15, _freeOH_T_17)
node _freeOH_T_19 = bits(_freeOH_T_18, 39, 0)
node _freeOH_T_20 = shl(_freeOH_T_19, 1)
node _freeOH_T_21 = not(_freeOH_T_20)
node _freeOH_T_22 = not(lists)
node freeOH = and(_freeOH_T_21, _freeOH_T_22)
node freeIdx_hi = bits(freeOH, 40, 32)
node freeIdx_lo = bits(freeOH, 31, 0)
node _freeIdx_T = orr(freeIdx_hi)
node _freeIdx_T_1 = or(freeIdx_hi, freeIdx_lo)
node freeIdx_hi_1 = bits(_freeIdx_T_1, 31, 16)
node freeIdx_lo_1 = bits(_freeIdx_T_1, 15, 0)
node _freeIdx_T_2 = orr(freeIdx_hi_1)
node _freeIdx_T_3 = or(freeIdx_hi_1, freeIdx_lo_1)
node freeIdx_hi_2 = bits(_freeIdx_T_3, 15, 8)
node freeIdx_lo_2 = bits(_freeIdx_T_3, 7, 0)
node _freeIdx_T_4 = orr(freeIdx_hi_2)
node _freeIdx_T_5 = or(freeIdx_hi_2, freeIdx_lo_2)
node freeIdx_hi_3 = bits(_freeIdx_T_5, 7, 4)
node freeIdx_lo_3 = bits(_freeIdx_T_5, 3, 0)
node _freeIdx_T_6 = orr(freeIdx_hi_3)
node _freeIdx_T_7 = or(freeIdx_hi_3, freeIdx_lo_3)
node freeIdx_hi_4 = bits(_freeIdx_T_7, 3, 2)
node freeIdx_lo_4 = bits(_freeIdx_T_7, 1, 0)
node _freeIdx_T_8 = orr(freeIdx_hi_4)
node _freeIdx_T_9 = or(freeIdx_hi_4, freeIdx_lo_4)
node _freeIdx_T_10 = bits(_freeIdx_T_9, 1, 1)
node _freeIdx_T_11 = cat(_freeIdx_T_8, _freeIdx_T_10)
node _freeIdx_T_12 = cat(_freeIdx_T_6, _freeIdx_T_11)
node _freeIdx_T_13 = cat(_freeIdx_T_4, _freeIdx_T_12)
node _freeIdx_T_14 = cat(_freeIdx_T_2, _freeIdx_T_13)
node freeIdx = cat(_freeIdx_T, _freeIdx_T_14)
node _first_T = and(io.a.ready, io.a.valid)
node _first_beats1_decode_T = dshl(UInt<6>(0h3f), io.a.bits.size)
node _first_beats1_decode_T_1 = bits(_first_beats1_decode_T, 5, 0)
node _first_beats1_decode_T_2 = not(_first_beats1_decode_T_1)
node first_beats1_decode = shr(_first_beats1_decode_T_2, 4)
node _first_beats1_opdata_T = bits(io.a.bits.opcode, 2, 2)
node first_beats1_opdata = eq(_first_beats1_opdata_T, UInt<1>(0h0))
node first_beats1 = mux(first_beats1_opdata, first_beats1_decode, UInt<1>(0h0))
regreset first_counter : UInt<2>, clock, reset, UInt<2>(0h0)
node _first_counter1_T = sub(first_counter, UInt<1>(0h1))
node first_counter1 = tail(_first_counter1_T, 1)
node first = eq(first_counter, UInt<1>(0h0))
node _first_last_T = eq(first_counter, UInt<1>(0h1))
node _first_last_T_1 = eq(first_beats1, UInt<1>(0h0))
node first_last = or(_first_last_T, _first_last_T_1)
node first_done = and(first_last, _first_T)
node _first_count_T = not(first_counter1)
node first_count = and(first_beats1, _first_count_T)
when _first_T :
node _first_counter_T = mux(first, first_beats1, first_counter1)
connect first_counter, _first_counter_T
node _hasData_opdata_T = bits(io.a.bits.opcode, 2, 2)
node hasData = eq(_hasData_opdata_T, UInt<1>(0h0))
node _req_block_T = eq(io.req.ready, UInt<1>(0h0))
node req_block = and(first, _req_block_T)
node _buf_block_T = eq(putbuffer.io.push.ready, UInt<1>(0h0))
node buf_block = and(hasData, _buf_block_T)
node _set_block_T = and(hasData, first)
node _set_block_T_1 = eq(free, UInt<1>(0h0))
node set_block = and(_set_block_T, _set_block_T_1)
node _T = and(io.a.valid, req_block)
node _T_1 = and(io.a.valid, buf_block)
node _T_2 = and(io.a.valid, set_block)
node _io_a_ready_T = eq(req_block, UInt<1>(0h0))
node _io_a_ready_T_1 = eq(buf_block, UInt<1>(0h0))
node _io_a_ready_T_2 = and(_io_a_ready_T, _io_a_ready_T_1)
node _io_a_ready_T_3 = eq(set_block, UInt<1>(0h0))
node _io_a_ready_T_4 = and(_io_a_ready_T_2, _io_a_ready_T_3)
connect io.a.ready, _io_a_ready_T_4
node _io_req_valid_T = and(io.a.valid, first)
node _io_req_valid_T_1 = eq(buf_block, UInt<1>(0h0))
node _io_req_valid_T_2 = and(_io_req_valid_T, _io_req_valid_T_1)
node _io_req_valid_T_3 = eq(set_block, UInt<1>(0h0))
node _io_req_valid_T_4 = and(_io_req_valid_T_2, _io_req_valid_T_3)
connect io.req.valid, _io_req_valid_T_4
node _putbuffer_io_push_valid_T = and(io.a.valid, hasData)
node _putbuffer_io_push_valid_T_1 = eq(req_block, UInt<1>(0h0))
node _putbuffer_io_push_valid_T_2 = and(_putbuffer_io_push_valid_T, _putbuffer_io_push_valid_T_1)
node _putbuffer_io_push_valid_T_3 = eq(set_block, UInt<1>(0h0))
node _putbuffer_io_push_valid_T_4 = and(_putbuffer_io_push_valid_T_2, _putbuffer_io_push_valid_T_3)
connect putbuffer.io.push.valid, _putbuffer_io_push_valid_T_4
node _T_3 = and(io.a.valid, first)
node _T_4 = and(_T_3, hasData)
node _T_5 = eq(req_block, UInt<1>(0h0))
node _T_6 = and(_T_4, _T_5)
node _T_7 = eq(buf_block, UInt<1>(0h0))
node _T_8 = and(_T_6, _T_7)
when _T_8 :
connect lists_set, freeOH
node _offset_T = bits(io.a.bits.address, 0, 0)
node _offset_T_1 = bits(io.a.bits.address, 1, 1)
node _offset_T_2 = bits(io.a.bits.address, 2, 2)
node _offset_T_3 = bits(io.a.bits.address, 3, 3)
node _offset_T_4 = bits(io.a.bits.address, 4, 4)
node _offset_T_5 = bits(io.a.bits.address, 5, 5)
node _offset_T_6 = bits(io.a.bits.address, 9, 9)
node _offset_T_7 = bits(io.a.bits.address, 10, 10)
node _offset_T_8 = bits(io.a.bits.address, 11, 11)
node _offset_T_9 = bits(io.a.bits.address, 12, 12)
node _offset_T_10 = bits(io.a.bits.address, 13, 13)
node _offset_T_11 = bits(io.a.bits.address, 14, 14)
node _offset_T_12 = bits(io.a.bits.address, 15, 15)
node _offset_T_13 = bits(io.a.bits.address, 16, 16)
node _offset_T_14 = bits(io.a.bits.address, 17, 17)
node _offset_T_15 = bits(io.a.bits.address, 18, 18)
node _offset_T_16 = bits(io.a.bits.address, 19, 19)
node _offset_T_17 = bits(io.a.bits.address, 20, 20)
node _offset_T_18 = bits(io.a.bits.address, 21, 21)
node _offset_T_19 = bits(io.a.bits.address, 22, 22)
node _offset_T_20 = bits(io.a.bits.address, 23, 23)
node _offset_T_21 = bits(io.a.bits.address, 24, 24)
node _offset_T_22 = bits(io.a.bits.address, 25, 25)
node _offset_T_23 = bits(io.a.bits.address, 26, 26)
node _offset_T_24 = bits(io.a.bits.address, 27, 27)
node _offset_T_25 = bits(io.a.bits.address, 31, 31)
node offset_lo_lo_lo_hi = cat(_offset_T_2, _offset_T_1)
node offset_lo_lo_lo = cat(offset_lo_lo_lo_hi, _offset_T)
node offset_lo_lo_hi_hi = cat(_offset_T_5, _offset_T_4)
node offset_lo_lo_hi = cat(offset_lo_lo_hi_hi, _offset_T_3)
node offset_lo_lo = cat(offset_lo_lo_hi, offset_lo_lo_lo)
node offset_lo_hi_lo_hi = cat(_offset_T_8, _offset_T_7)
node offset_lo_hi_lo = cat(offset_lo_hi_lo_hi, _offset_T_6)
node offset_lo_hi_hi_lo = cat(_offset_T_10, _offset_T_9)
node offset_lo_hi_hi_hi = cat(_offset_T_12, _offset_T_11)
node offset_lo_hi_hi = cat(offset_lo_hi_hi_hi, offset_lo_hi_hi_lo)
node offset_lo_hi = cat(offset_lo_hi_hi, offset_lo_hi_lo)
node offset_lo = cat(offset_lo_hi, offset_lo_lo)
node offset_hi_lo_lo_hi = cat(_offset_T_15, _offset_T_14)
node offset_hi_lo_lo = cat(offset_hi_lo_lo_hi, _offset_T_13)
node offset_hi_lo_hi_hi = cat(_offset_T_18, _offset_T_17)
node offset_hi_lo_hi = cat(offset_hi_lo_hi_hi, _offset_T_16)
node offset_hi_lo = cat(offset_hi_lo_hi, offset_hi_lo_lo)
node offset_hi_hi_lo_hi = cat(_offset_T_21, _offset_T_20)
node offset_hi_hi_lo = cat(offset_hi_hi_lo_hi, _offset_T_19)
node offset_hi_hi_hi_lo = cat(_offset_T_23, _offset_T_22)
node offset_hi_hi_hi_hi = cat(_offset_T_25, _offset_T_24)
node offset_hi_hi_hi = cat(offset_hi_hi_hi_hi, offset_hi_hi_hi_lo)
node offset_hi_hi = cat(offset_hi_hi_hi, offset_hi_hi_lo)
node offset_hi = cat(offset_hi_hi, offset_hi_lo)
node offset = cat(offset_hi, offset_lo)
node set = shr(offset, 6)
node tag = shr(set, 11)
node tag_1 = bits(tag, 8, 0)
node set_1 = bits(set, 10, 0)
node offset_1 = bits(offset, 5, 0)
reg put_r : UInt<6>, clock
when first :
connect put_r, freeIdx
node put = mux(first, freeIdx, put_r)
wire _WIRE : UInt<1>[3]
connect _WIRE[0], UInt<1>(0h1)
connect _WIRE[1], UInt<1>(0h0)
connect _WIRE[2], UInt<1>(0h0)
connect io.req.bits.prio, _WIRE
connect io.req.bits.control, UInt<1>(0h0)
connect io.req.bits.opcode, io.a.bits.opcode
connect io.req.bits.param, io.a.bits.param
connect io.req.bits.size, io.a.bits.size
connect io.req.bits.source, io.a.bits.source
connect io.req.bits.offset, offset_1
connect io.req.bits.set, set_1
connect io.req.bits.tag, tag_1
connect io.req.bits.put, put
connect putbuffer.io.push.bits.index, put
connect putbuffer.io.push.bits.data.data, io.a.bits.data
connect putbuffer.io.push.bits.data.mask, io.a.bits.mask
connect putbuffer.io.push.bits.data.corrupt, io.a.bits.corrupt
connect putbuffer.io.pop.bits, io.pb_pop.bits.index
node _putbuffer_io_pop_valid_T = and(io.pb_pop.ready, io.pb_pop.valid)
connect putbuffer.io.pop.valid, _putbuffer_io_pop_valid_T
node _io_pb_pop_ready_T = dshr(putbuffer.io.valid, io.pb_pop.bits.index)
node _io_pb_pop_ready_T_1 = bits(_io_pb_pop_ready_T, 0, 0)
connect io.pb_pop.ready, _io_pb_pop_ready_T_1
connect io.pb_beat, putbuffer.io.data
node _T_9 = and(io.pb_pop.ready, io.pb_pop.valid)
node _T_10 = and(_T_9, io.pb_pop.bits.last)
when _T_10 :
node lists_clr_shiftAmount = bits(io.pb_pop.bits.index, 5, 0)
node _lists_clr_T = dshl(UInt<1>(0h1), lists_clr_shiftAmount)
node _lists_clr_T_1 = bits(_lists_clr_T, 39, 0)
connect lists_clr, _lists_clr_T_1 | module SinkA_4( // @[SinkA.scala:38:7]
input clock, // @[SinkA.scala:38:7]
input reset, // @[SinkA.scala:38:7]
input io_req_ready, // @[SinkA.scala:40:14]
output io_req_valid, // @[SinkA.scala:40:14]
output [2:0] io_req_bits_opcode, // @[SinkA.scala:40:14]
output [2:0] io_req_bits_param, // @[SinkA.scala:40:14]
output [2:0] io_req_bits_size, // @[SinkA.scala:40:14]
output [5:0] io_req_bits_source, // @[SinkA.scala:40:14]
output [8:0] io_req_bits_tag, // @[SinkA.scala:40:14]
output [5:0] io_req_bits_offset, // @[SinkA.scala:40:14]
output [5:0] io_req_bits_put, // @[SinkA.scala:40:14]
output [10:0] io_req_bits_set, // @[SinkA.scala:40:14]
output io_a_ready, // @[SinkA.scala:40:14]
input io_a_valid, // @[SinkA.scala:40:14]
input [2:0] io_a_bits_opcode, // @[SinkA.scala:40:14]
input [2:0] io_a_bits_param, // @[SinkA.scala:40:14]
input [2:0] io_a_bits_size, // @[SinkA.scala:40:14]
input [5:0] io_a_bits_source, // @[SinkA.scala:40:14]
input [31:0] io_a_bits_address, // @[SinkA.scala:40:14]
input [15:0] io_a_bits_mask, // @[SinkA.scala:40:14]
input [127:0] io_a_bits_data, // @[SinkA.scala:40:14]
input io_a_bits_corrupt, // @[SinkA.scala:40:14]
output io_pb_pop_ready, // @[SinkA.scala:40:14]
input io_pb_pop_valid, // @[SinkA.scala:40:14]
input [5:0] io_pb_pop_bits_index, // @[SinkA.scala:40:14]
input io_pb_pop_bits_last, // @[SinkA.scala:40:14]
output [127:0] io_pb_beat_data, // @[SinkA.scala:40:14]
output [15:0] io_pb_beat_mask, // @[SinkA.scala:40:14]
output io_pb_beat_corrupt // @[SinkA.scala:40:14]
);
wire _putbuffer_io_push_ready; // @[SinkA.scala:51:25]
wire [39:0] _putbuffer_io_valid; // @[SinkA.scala:51:25]
wire io_req_ready_0 = io_req_ready; // @[SinkA.scala:38:7]
wire io_a_valid_0 = io_a_valid; // @[SinkA.scala:38:7]
wire [2:0] io_a_bits_opcode_0 = io_a_bits_opcode; // @[SinkA.scala:38:7]
wire [2:0] io_a_bits_param_0 = io_a_bits_param; // @[SinkA.scala:38:7]
wire [2:0] io_a_bits_size_0 = io_a_bits_size; // @[SinkA.scala:38:7]
wire [5:0] io_a_bits_source_0 = io_a_bits_source; // @[SinkA.scala:38:7]
wire [31:0] io_a_bits_address_0 = io_a_bits_address; // @[SinkA.scala:38:7]
wire [15:0] io_a_bits_mask_0 = io_a_bits_mask; // @[SinkA.scala:38:7]
wire [127:0] io_a_bits_data_0 = io_a_bits_data; // @[SinkA.scala:38:7]
wire io_a_bits_corrupt_0 = io_a_bits_corrupt; // @[SinkA.scala:38:7]
wire io_pb_pop_valid_0 = io_pb_pop_valid; // @[SinkA.scala:38:7]
wire [5:0] io_pb_pop_bits_index_0 = io_pb_pop_bits_index; // @[SinkA.scala:38:7]
wire io_pb_pop_bits_last_0 = io_pb_pop_bits_last; // @[SinkA.scala:38:7]
wire io_req_bits_prio_1 = 1'h0; // @[SinkA.scala:38:7]
wire io_req_bits_prio_2 = 1'h0; // @[SinkA.scala:38:7]
wire io_req_bits_control = 1'h0; // @[SinkA.scala:38:7]
wire io_req_bits_prio_0 = 1'h1; // @[SinkA.scala:38:7]
wire _io_req_valid_T_4; // @[SinkA.scala:79:50]
wire [8:0] tag_1; // @[Parameters.scala:217:9]
wire [5:0] offset_1; // @[Parameters.scala:217:50]
wire [5:0] put; // @[SinkA.scala:84:16]
wire [10:0] set_1; // @[Parameters.scala:217:28]
wire _io_a_ready_T_4; // @[SinkA.scala:78:39]
wire [2:0] io_req_bits_opcode_0 = io_a_bits_opcode_0; // @[SinkA.scala:38:7]
wire [2:0] io_req_bits_param_0 = io_a_bits_param_0; // @[SinkA.scala:38:7]
wire [2:0] io_req_bits_size_0 = io_a_bits_size_0; // @[SinkA.scala:38:7]
wire [5:0] io_req_bits_source_0 = io_a_bits_source_0; // @[SinkA.scala:38:7]
wire _io_pb_pop_ready_T_1; // @[SinkA.scala:105:40]
wire [5:0] lists_clr_shiftAmount = io_pb_pop_bits_index_0; // @[OneHot.scala:64:49]
wire [8:0] io_req_bits_tag_0; // @[SinkA.scala:38:7]
wire [5:0] io_req_bits_offset_0; // @[SinkA.scala:38:7]
wire [5:0] io_req_bits_put_0; // @[SinkA.scala:38:7]
wire [10:0] io_req_bits_set_0; // @[SinkA.scala:38:7]
wire io_req_valid_0; // @[SinkA.scala:38:7]
wire io_a_ready_0; // @[SinkA.scala:38:7]
wire io_pb_pop_ready_0; // @[SinkA.scala:38:7]
wire [127:0] io_pb_beat_data_0; // @[SinkA.scala:38:7]
wire [15:0] io_pb_beat_mask_0; // @[SinkA.scala:38:7]
wire io_pb_beat_corrupt_0; // @[SinkA.scala:38:7]
reg [39:0] lists; // @[SinkA.scala:52:22]
wire [39:0] lists_set; // @[SinkA.scala:54:27]
wire [39:0] lists_clr; // @[SinkA.scala:55:27]
wire [39:0] _lists_T = lists | lists_set; // @[SinkA.scala:52:22, :54:27, :56:19]
wire [39:0] _lists_T_1 = ~lists_clr; // @[SinkA.scala:55:27, :56:34]
wire [39:0] _lists_T_2 = _lists_T & _lists_T_1; // @[SinkA.scala:56:{19,32,34}]
wire _free_T = &lists; // @[SinkA.scala:52:22, :58:21]
wire free = ~_free_T; // @[SinkA.scala:58:{14,21}]
wire [39:0] _freeOH_T = ~lists; // @[SinkA.scala:52:22, :59:25]
wire [40:0] _freeOH_T_1 = {_freeOH_T, 1'h0}; // @[package.scala:253:48]
wire [39:0] _freeOH_T_2 = _freeOH_T_1[39:0]; // @[package.scala:253:{48,53}]
wire [39:0] _freeOH_T_3 = _freeOH_T | _freeOH_T_2; // @[package.scala:253:{43,53}]
wire [41:0] _freeOH_T_4 = {_freeOH_T_3, 2'h0}; // @[package.scala:253:{43,48}]
wire [39:0] _freeOH_T_5 = _freeOH_T_4[39:0]; // @[package.scala:253:{48,53}]
wire [39:0] _freeOH_T_6 = _freeOH_T_3 | _freeOH_T_5; // @[package.scala:253:{43,53}]
wire [43:0] _freeOH_T_7 = {_freeOH_T_6, 4'h0}; // @[package.scala:253:{43,48}]
wire [39:0] _freeOH_T_8 = _freeOH_T_7[39:0]; // @[package.scala:253:{48,53}]
wire [39:0] _freeOH_T_9 = _freeOH_T_6 | _freeOH_T_8; // @[package.scala:253:{43,53}]
wire [47:0] _freeOH_T_10 = {_freeOH_T_9, 8'h0}; // @[package.scala:253:{43,48}]
wire [39:0] _freeOH_T_11 = _freeOH_T_10[39:0]; // @[package.scala:253:{48,53}]
wire [39:0] _freeOH_T_12 = _freeOH_T_9 | _freeOH_T_11; // @[package.scala:253:{43,53}]
wire [55:0] _freeOH_T_13 = {_freeOH_T_12, 16'h0}; // @[package.scala:253:{43,48}]
wire [39:0] _freeOH_T_14 = _freeOH_T_13[39:0]; // @[package.scala:253:{48,53}]
wire [39:0] _freeOH_T_15 = _freeOH_T_12 | _freeOH_T_14; // @[package.scala:253:{43,53}]
wire [71:0] _freeOH_T_16 = {_freeOH_T_15, 32'h0}; // @[package.scala:253:{43,48}]
wire [39:0] _freeOH_T_17 = _freeOH_T_16[39:0]; // @[package.scala:253:{48,53}]
wire [39:0] _freeOH_T_18 = _freeOH_T_15 | _freeOH_T_17; // @[package.scala:253:{43,53}]
wire [39:0] _freeOH_T_19 = _freeOH_T_18; // @[package.scala:253:43, :254:17]
wire [40:0] _freeOH_T_20 = {_freeOH_T_19, 1'h0}; // @[package.scala:254:17]
wire [40:0] _freeOH_T_21 = ~_freeOH_T_20; // @[SinkA.scala:59:{16,33}]
wire [39:0] _freeOH_T_22 = ~lists; // @[SinkA.scala:52:22, :59:{25,41}]
wire [40:0] freeOH = {1'h0, _freeOH_T_21[39:0] & _freeOH_T_22}; // @[SinkA.scala:59:{16,39,41}]
wire [8:0] freeIdx_hi = freeOH[40:32]; // @[OneHot.scala:30:18]
wire [31:0] freeIdx_lo = freeOH[31:0]; // @[OneHot.scala:31:18]
wire _freeIdx_T = |freeIdx_hi; // @[OneHot.scala:30:18, :32:14]
wire [31:0] _freeIdx_T_1 = {23'h0, freeIdx_hi} | freeIdx_lo; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [15:0] freeIdx_hi_1 = _freeIdx_T_1[31:16]; // @[OneHot.scala:30:18, :32:28]
wire [15:0] freeIdx_lo_1 = _freeIdx_T_1[15:0]; // @[OneHot.scala:31:18, :32:28]
wire _freeIdx_T_2 = |freeIdx_hi_1; // @[OneHot.scala:30:18, :32:14]
wire [15:0] _freeIdx_T_3 = freeIdx_hi_1 | freeIdx_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [7:0] freeIdx_hi_2 = _freeIdx_T_3[15:8]; // @[OneHot.scala:30:18, :32:28]
wire [7:0] freeIdx_lo_2 = _freeIdx_T_3[7:0]; // @[OneHot.scala:31:18, :32:28]
wire _freeIdx_T_4 = |freeIdx_hi_2; // @[OneHot.scala:30:18, :32:14]
wire [7:0] _freeIdx_T_5 = freeIdx_hi_2 | freeIdx_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [3:0] freeIdx_hi_3 = _freeIdx_T_5[7:4]; // @[OneHot.scala:30:18, :32:28]
wire [3:0] freeIdx_lo_3 = _freeIdx_T_5[3:0]; // @[OneHot.scala:31:18, :32:28]
wire _freeIdx_T_6 = |freeIdx_hi_3; // @[OneHot.scala:30:18, :32:14]
wire [3:0] _freeIdx_T_7 = freeIdx_hi_3 | freeIdx_lo_3; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] freeIdx_hi_4 = _freeIdx_T_7[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] freeIdx_lo_4 = _freeIdx_T_7[1:0]; // @[OneHot.scala:31:18, :32:28]
wire _freeIdx_T_8 = |freeIdx_hi_4; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _freeIdx_T_9 = freeIdx_hi_4 | freeIdx_lo_4; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _freeIdx_T_10 = _freeIdx_T_9[1]; // @[OneHot.scala:32:28]
wire [1:0] _freeIdx_T_11 = {_freeIdx_T_8, _freeIdx_T_10}; // @[OneHot.scala:32:{10,14}]
wire [2:0] _freeIdx_T_12 = {_freeIdx_T_6, _freeIdx_T_11}; // @[OneHot.scala:32:{10,14}]
wire [3:0] _freeIdx_T_13 = {_freeIdx_T_4, _freeIdx_T_12}; // @[OneHot.scala:32:{10,14}]
wire [4:0] _freeIdx_T_14 = {_freeIdx_T_2, _freeIdx_T_13}; // @[OneHot.scala:32:{10,14}]
wire [5:0] freeIdx = {_freeIdx_T, _freeIdx_T_14}; // @[OneHot.scala:32:{10,14}]
wire _first_T = io_a_ready_0 & io_a_valid_0; // @[Decoupled.scala:51:35]
wire [12:0] _first_beats1_decode_T = 13'h3F << io_a_bits_size_0; // @[package.scala:243:71]
wire [5:0] _first_beats1_decode_T_1 = _first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _first_beats1_decode_T_2 = ~_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [1:0] first_beats1_decode = _first_beats1_decode_T_2[5:4]; // @[package.scala:243:46]
wire _first_beats1_opdata_T = io_a_bits_opcode_0[2]; // @[Edges.scala:92:37]
wire _hasData_opdata_T = io_a_bits_opcode_0[2]; // @[Edges.scala:92:37]
wire first_beats1_opdata = ~_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [1:0] first_beats1 = first_beats1_opdata ? first_beats1_decode : 2'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [1:0] first_counter; // @[Edges.scala:229:27]
wire [2:0] _first_counter1_T = {1'h0, first_counter} - 3'h1; // @[Edges.scala:229:27, :230:28]
wire [1:0] first_counter1 = _first_counter1_T[1:0]; // @[Edges.scala:230:28]
wire first = first_counter == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _first_last_T = first_counter == 2'h1; // @[Edges.scala:229:27, :232:25]
wire _first_last_T_1 = first_beats1 == 2'h0; // @[Edges.scala:221:14, :232:43]
wire first_last = _first_last_T | _first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire first_done = first_last & _first_T; // @[Decoupled.scala:51:35]
wire [1:0] _first_count_T = ~first_counter1; // @[Edges.scala:230:28, :234:27]
wire [1:0] first_count = first_beats1 & _first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [1:0] _first_counter_T = first ? first_beats1 : first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire hasData = ~_hasData_opdata_T; // @[Edges.scala:92:{28,37}]
wire _req_block_T = ~io_req_ready_0; // @[SinkA.scala:38:7, :70:28]
wire req_block = first & _req_block_T; // @[Edges.scala:231:25]
wire _buf_block_T = ~_putbuffer_io_push_ready; // @[SinkA.scala:51:25, :71:30]
wire buf_block = hasData & _buf_block_T; // @[Edges.scala:92:28]
wire _set_block_T = hasData & first; // @[Edges.scala:92:28, :231:25]
wire _set_block_T_1 = ~free; // @[SinkA.scala:58:14, :72:39]
wire set_block = _set_block_T & _set_block_T_1; // @[SinkA.scala:72:{27,36,39}]
wire _io_a_ready_T = ~req_block; // @[SinkA.scala:70:25, :78:14]
wire _io_a_ready_T_1 = ~buf_block; // @[SinkA.scala:71:27, :78:28]
wire _io_a_ready_T_2 = _io_a_ready_T & _io_a_ready_T_1; // @[SinkA.scala:78:{14,25,28}]
wire _io_a_ready_T_3 = ~set_block; // @[SinkA.scala:72:36, :78:42]
assign _io_a_ready_T_4 = _io_a_ready_T_2 & _io_a_ready_T_3; // @[SinkA.scala:78:{25,39,42}]
assign io_a_ready_0 = _io_a_ready_T_4; // @[SinkA.scala:38:7, :78:39]
wire _io_req_valid_T = io_a_valid_0 & first; // @[Edges.scala:231:25]
wire _io_req_valid_T_1 = ~buf_block; // @[SinkA.scala:71:27, :78:28, :79:39]
wire _io_req_valid_T_2 = _io_req_valid_T & _io_req_valid_T_1; // @[SinkA.scala:79:{27,36,39}]
wire _io_req_valid_T_3 = ~set_block; // @[SinkA.scala:72:36, :78:42, :79:53]
assign _io_req_valid_T_4 = _io_req_valid_T_2 & _io_req_valid_T_3; // @[SinkA.scala:79:{36,50,53}]
assign io_req_valid_0 = _io_req_valid_T_4; // @[SinkA.scala:38:7, :79:50]
wire _putbuffer_io_push_valid_T = io_a_valid_0 & hasData; // @[Edges.scala:92:28]
wire _putbuffer_io_push_valid_T_1 = ~req_block; // @[SinkA.scala:70:25, :78:14, :80:52]
wire _putbuffer_io_push_valid_T_2 = _putbuffer_io_push_valid_T & _putbuffer_io_push_valid_T_1; // @[SinkA.scala:80:{38,49,52}]
wire _putbuffer_io_push_valid_T_3 = ~set_block; // @[SinkA.scala:72:36, :78:42, :80:66]
wire _putbuffer_io_push_valid_T_4 = _putbuffer_io_push_valid_T_2 & _putbuffer_io_push_valid_T_3; // @[SinkA.scala:80:{49,63,66}]
assign lists_set = _io_req_valid_T & hasData & ~req_block & ~buf_block ? freeOH[39:0] : 40'h0; // @[Edges.scala:92:28]
wire _offset_T = io_a_bits_address_0[0]; // @[SinkA.scala:38:7]
wire _offset_T_1 = io_a_bits_address_0[1]; // @[SinkA.scala:38:7]
wire _offset_T_2 = io_a_bits_address_0[2]; // @[SinkA.scala:38:7]
wire _offset_T_3 = io_a_bits_address_0[3]; // @[SinkA.scala:38:7]
wire _offset_T_4 = io_a_bits_address_0[4]; // @[SinkA.scala:38:7]
wire _offset_T_5 = io_a_bits_address_0[5]; // @[SinkA.scala:38:7]
wire _offset_T_6 = io_a_bits_address_0[9]; // @[SinkA.scala:38:7]
wire _offset_T_7 = io_a_bits_address_0[10]; // @[SinkA.scala:38:7]
wire _offset_T_8 = io_a_bits_address_0[11]; // @[SinkA.scala:38:7]
wire _offset_T_9 = io_a_bits_address_0[12]; // @[SinkA.scala:38:7]
wire _offset_T_10 = io_a_bits_address_0[13]; // @[SinkA.scala:38:7]
wire _offset_T_11 = io_a_bits_address_0[14]; // @[SinkA.scala:38:7]
wire _offset_T_12 = io_a_bits_address_0[15]; // @[SinkA.scala:38:7]
wire _offset_T_13 = io_a_bits_address_0[16]; // @[SinkA.scala:38:7]
wire _offset_T_14 = io_a_bits_address_0[17]; // @[SinkA.scala:38:7]
wire _offset_T_15 = io_a_bits_address_0[18]; // @[SinkA.scala:38:7]
wire _offset_T_16 = io_a_bits_address_0[19]; // @[SinkA.scala:38:7]
wire _offset_T_17 = io_a_bits_address_0[20]; // @[SinkA.scala:38:7]
wire _offset_T_18 = io_a_bits_address_0[21]; // @[SinkA.scala:38:7]
wire _offset_T_19 = io_a_bits_address_0[22]; // @[SinkA.scala:38:7]
wire _offset_T_20 = io_a_bits_address_0[23]; // @[SinkA.scala:38:7]
wire _offset_T_21 = io_a_bits_address_0[24]; // @[SinkA.scala:38:7]
wire _offset_T_22 = io_a_bits_address_0[25]; // @[SinkA.scala:38:7]
wire _offset_T_23 = io_a_bits_address_0[26]; // @[SinkA.scala:38:7]
wire _offset_T_24 = io_a_bits_address_0[27]; // @[SinkA.scala:38:7]
wire _offset_T_25 = io_a_bits_address_0[31]; // @[SinkA.scala:38:7]
wire [1:0] offset_lo_lo_lo_hi = {_offset_T_2, _offset_T_1}; // @[Parameters.scala:214:{21,47}]
wire [2:0] offset_lo_lo_lo = {offset_lo_lo_lo_hi, _offset_T}; // @[Parameters.scala:214:{21,47}]
wire [1:0] offset_lo_lo_hi_hi = {_offset_T_5, _offset_T_4}; // @[Parameters.scala:214:{21,47}]
wire [2:0] offset_lo_lo_hi = {offset_lo_lo_hi_hi, _offset_T_3}; // @[Parameters.scala:214:{21,47}]
wire [5:0] offset_lo_lo = {offset_lo_lo_hi, offset_lo_lo_lo}; // @[Parameters.scala:214:21]
wire [1:0] offset_lo_hi_lo_hi = {_offset_T_8, _offset_T_7}; // @[Parameters.scala:214:{21,47}]
wire [2:0] offset_lo_hi_lo = {offset_lo_hi_lo_hi, _offset_T_6}; // @[Parameters.scala:214:{21,47}]
wire [1:0] offset_lo_hi_hi_lo = {_offset_T_10, _offset_T_9}; // @[Parameters.scala:214:{21,47}]
wire [1:0] offset_lo_hi_hi_hi = {_offset_T_12, _offset_T_11}; // @[Parameters.scala:214:{21,47}]
wire [3:0] offset_lo_hi_hi = {offset_lo_hi_hi_hi, offset_lo_hi_hi_lo}; // @[Parameters.scala:214:21]
wire [6:0] offset_lo_hi = {offset_lo_hi_hi, offset_lo_hi_lo}; // @[Parameters.scala:214:21]
wire [12:0] offset_lo = {offset_lo_hi, offset_lo_lo}; // @[Parameters.scala:214:21]
wire [1:0] offset_hi_lo_lo_hi = {_offset_T_15, _offset_T_14}; // @[Parameters.scala:214:{21,47}]
wire [2:0] offset_hi_lo_lo = {offset_hi_lo_lo_hi, _offset_T_13}; // @[Parameters.scala:214:{21,47}]
wire [1:0] offset_hi_lo_hi_hi = {_offset_T_18, _offset_T_17}; // @[Parameters.scala:214:{21,47}]
wire [2:0] offset_hi_lo_hi = {offset_hi_lo_hi_hi, _offset_T_16}; // @[Parameters.scala:214:{21,47}]
wire [5:0] offset_hi_lo = {offset_hi_lo_hi, offset_hi_lo_lo}; // @[Parameters.scala:214:21]
wire [1:0] offset_hi_hi_lo_hi = {_offset_T_21, _offset_T_20}; // @[Parameters.scala:214:{21,47}]
wire [2:0] offset_hi_hi_lo = {offset_hi_hi_lo_hi, _offset_T_19}; // @[Parameters.scala:214:{21,47}]
wire [1:0] offset_hi_hi_hi_lo = {_offset_T_23, _offset_T_22}; // @[Parameters.scala:214:{21,47}]
wire [1:0] offset_hi_hi_hi_hi = {_offset_T_25, _offset_T_24}; // @[Parameters.scala:214:{21,47}]
wire [3:0] offset_hi_hi_hi = {offset_hi_hi_hi_hi, offset_hi_hi_hi_lo}; // @[Parameters.scala:214:21]
wire [6:0] offset_hi_hi = {offset_hi_hi_hi, offset_hi_hi_lo}; // @[Parameters.scala:214:21]
wire [12:0] offset_hi = {offset_hi_hi, offset_hi_lo}; // @[Parameters.scala:214:21]
wire [25:0] offset = {offset_hi, offset_lo}; // @[Parameters.scala:214:21]
wire [19:0] set = offset[25:6]; // @[Parameters.scala:214:21, :215:22]
wire [8:0] tag = set[19:11]; // @[Parameters.scala:215:22, :216:19]
assign tag_1 = tag; // @[Parameters.scala:216:19, :217:9]
assign io_req_bits_tag_0 = tag_1; // @[SinkA.scala:38:7]
assign set_1 = set[10:0]; // @[Parameters.scala:215:22, :217:28]
assign io_req_bits_set_0 = set_1; // @[SinkA.scala:38:7]
assign offset_1 = offset[5:0]; // @[Parameters.scala:214:21, :217:50]
assign io_req_bits_offset_0 = offset_1; // @[SinkA.scala:38:7]
reg [5:0] put_r; // @[SinkA.scala:84:42]
assign put = first ? freeIdx : put_r; // @[OneHot.scala:32:10]
assign io_req_bits_put_0 = put; // @[SinkA.scala:38:7, :84:16]
wire _putbuffer_io_pop_valid_T = io_pb_pop_ready_0 & io_pb_pop_valid_0; // @[Decoupled.scala:51:35]
wire [39:0] _io_pb_pop_ready_T = _putbuffer_io_valid >> io_pb_pop_bits_index_0; // @[SinkA.scala:38:7, :51:25, :105:40]
assign _io_pb_pop_ready_T_1 = _io_pb_pop_ready_T[0]; // @[SinkA.scala:105:40]
assign io_pb_pop_ready_0 = _io_pb_pop_ready_T_1; // @[SinkA.scala:38:7, :105:40]
wire [63:0] _lists_clr_T = 64'h1 << lists_clr_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [39:0] _lists_clr_T_1 = _lists_clr_T[39:0]; // @[OneHot.scala:65:{12,27}]
assign lists_clr = _putbuffer_io_pop_valid_T & io_pb_pop_bits_last_0 ? _lists_clr_T_1 : 40'h0; // @[OneHot.scala:65:27]
always @(posedge clock) begin // @[SinkA.scala:38:7]
if (reset) begin // @[SinkA.scala:38:7]
lists <= 40'h0; // @[SinkA.scala:52:22]
first_counter <= 2'h0; // @[Edges.scala:229:27]
end
else begin // @[SinkA.scala:38:7]
lists <= _lists_T_2; // @[SinkA.scala:52:22, :56:32]
if (_first_T) // @[Decoupled.scala:51:35]
first_counter <= _first_counter_T; // @[Edges.scala:229:27, :236:21]
end
if (first) // @[Edges.scala:231:25]
put_r <= freeIdx; // @[OneHot.scala:32:10]
always @(posedge)
ListBuffer_PutBufferAEntry_q40_e40_4 putbuffer ( // @[SinkA.scala:51:25]
.clock (clock),
.reset (reset),
.io_push_ready (_putbuffer_io_push_ready),
.io_push_valid (_putbuffer_io_push_valid_T_4), // @[SinkA.scala:80:63]
.io_push_bits_index (put), // @[SinkA.scala:84:16]
.io_push_bits_data_data (io_a_bits_data_0), // @[SinkA.scala:38:7]
.io_push_bits_data_mask (io_a_bits_mask_0), // @[SinkA.scala:38:7]
.io_push_bits_data_corrupt (io_a_bits_corrupt_0), // @[SinkA.scala:38:7]
.io_valid (_putbuffer_io_valid),
.io_pop_valid (_putbuffer_io_pop_valid_T), // @[Decoupled.scala:51:35]
.io_pop_bits (io_pb_pop_bits_index_0), // @[SinkA.scala:38:7]
.io_data_data (io_pb_beat_data_0),
.io_data_mask (io_pb_beat_mask_0),
.io_data_corrupt (io_pb_beat_corrupt_0)
); // @[SinkA.scala:51:25]
assign io_req_valid = io_req_valid_0; // @[SinkA.scala:38:7]
assign io_req_bits_opcode = io_req_bits_opcode_0; // @[SinkA.scala:38:7]
assign io_req_bits_param = io_req_bits_param_0; // @[SinkA.scala:38:7]
assign io_req_bits_size = io_req_bits_size_0; // @[SinkA.scala:38:7]
assign io_req_bits_source = io_req_bits_source_0; // @[SinkA.scala:38:7]
assign io_req_bits_tag = io_req_bits_tag_0; // @[SinkA.scala:38:7]
assign io_req_bits_offset = io_req_bits_offset_0; // @[SinkA.scala:38:7]
assign io_req_bits_put = io_req_bits_put_0; // @[SinkA.scala:38:7]
assign io_req_bits_set = io_req_bits_set_0; // @[SinkA.scala:38:7]
assign io_a_ready = io_a_ready_0; // @[SinkA.scala:38:7]
assign io_pb_pop_ready = io_pb_pop_ready_0; // @[SinkA.scala:38:7]
assign io_pb_beat_data = io_pb_beat_data_0; // @[SinkA.scala:38:7]
assign io_pb_beat_mask = io_pb_beat_mask_0; // @[SinkA.scala:38:7]
assign io_pb_beat_corrupt = io_pb_beat_corrupt_0; // @[SinkA.scala:38:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a14d64s7k1z4u :
input clock : Clock
input reset : Reset
output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
inst monitor of TLMonitor_30
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
connect auto.out, nodeOut
connect nodeIn, auto.in
inst nodeOut_a_q of Queue2_TLBundleA_a14d64s7k1z4u
connect nodeOut_a_q.clock, clock
connect nodeOut_a_q.reset, reset
connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid
connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt
connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data
connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask
connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address
connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source
connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size
connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param
connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode
connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready
connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits
connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid
connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready
inst nodeIn_d_q of Queue2_TLBundleD_a14d64s7k1z4u
connect nodeIn_d_q.clock, clock
connect nodeIn_d_q.reset, reset
connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid
connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt
connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data
connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied
connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink
connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source
connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size
connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param
connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode
connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready
connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits
connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid
connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<14>(0h0)
connect _WIRE.bits.source, UInt<7>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.valid, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<14>(0h0)
connect _WIRE_2.bits.source, UInt<7>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.ready, UInt<1>(0h1)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.mask, UInt<8>(0h0)
connect _WIRE_6.bits.address, UInt<14>(0h0)
connect _WIRE_6.bits.source, UInt<7>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<2>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
connect _WIRE_7.ready, UInt<1>(0h1)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<14>(0h0)
connect _WIRE_8.bits.source, UInt<7>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
connect _WIRE_9.valid, UInt<1>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_10.bits.sink, UInt<1>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
connect _WIRE_11.valid, UInt<1>(0h0) | module TLBuffer_a14d64s7k1z4u( // @[Buffer.scala:40:9]
input clock, // @[Buffer.scala:40:9]
input reset, // @[Buffer.scala:40:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [13:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [13:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [6:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [13:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9]
wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9]
wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire [6:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9]
wire [63:0] auto_out_d_bits_data = 64'h0; // @[Decoupled.scala:362:21]
wire [63:0] nodeOut_d_bits_data = 64'h0; // @[Decoupled.scala:362:21]
wire auto_out_d_bits_denied = 1'h1; // @[Decoupled.scala:362:21]
wire nodeOut_d_bits_denied = 1'h1; // @[Decoupled.scala:362:21]
wire auto_out_d_bits_sink = 1'h0; // @[Decoupled.scala:362:21]
wire nodeOut_d_bits_sink = 1'h0; // @[Decoupled.scala:362:21]
wire [1:0] auto_out_d_bits_param = 2'h0; // @[Decoupled.scala:362:21]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire [1:0] nodeOut_d_bits_param = 2'h0; // @[Decoupled.scala:362:21]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9]
wire [6:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9]
wire [13:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9]
wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [6:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [6:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [13:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9]
wire [6:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_a_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
wire [6:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
wire [6:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
wire [13:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_out_a_valid_0; // @[Buffer.scala:40:9]
wire auto_out_d_ready_0; // @[Buffer.scala:40:9]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9]
TLMonitor_30 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
Queue2_TLBundleA_a14d64s7k1z4u nodeOut_a_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_a_ready),
.io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_a_valid),
.io_deq_bits_opcode (nodeOut_a_bits_opcode),
.io_deq_bits_param (nodeOut_a_bits_param),
.io_deq_bits_size (nodeOut_a_bits_size),
.io_deq_bits_source (nodeOut_a_bits_source),
.io_deq_bits_address (nodeOut_a_bits_address),
.io_deq_bits_mask (nodeOut_a_bits_mask),
.io_deq_bits_data (nodeOut_a_bits_data),
.io_deq_bits_corrupt (nodeOut_a_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleD_a14d64s7k1z4u nodeIn_d_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeOut_d_ready),
.io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17]
.io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17]
.io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17]
.io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17]
.io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_d_valid),
.io_deq_bits_opcode (nodeIn_d_bits_opcode),
.io_deq_bits_param (nodeIn_d_bits_param),
.io_deq_bits_size (nodeIn_d_bits_size),
.io_deq_bits_source (nodeIn_d_bits_source),
.io_deq_bits_sink (nodeIn_d_bits_sink),
.io_deq_bits_denied (nodeIn_d_bits_denied),
.io_deq_bits_data (nodeIn_d_bits_data),
.io_deq_bits_corrupt (nodeIn_d_bits_corrupt)
); // @[Decoupled.scala:362:21]
assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9]
assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetRegVec_w1_i0_5 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>}
node _reg_T = asAsyncReset(reset)
regreset reg : UInt<1>, clock, _reg_T, UInt<1>(0h0)
when io.en :
connect reg, io.d
connect io.q, reg | module AsyncResetRegVec_w1_i0_5( // @[AsyncResetReg.scala:56:7]
input clock, // @[AsyncResetReg.scala:56:7]
input reset // @[AsyncResetReg.scala:56:7]
);
wire _reg_T = reset; // @[AsyncResetReg.scala:61:29]
wire io_en = 1'h1; // @[AsyncResetReg.scala:56:7, :59:14]
wire io_d = 1'h0; // @[AsyncResetReg.scala:56:7]
wire io_q = 1'h0; // @[AsyncResetReg.scala:56:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PE_116 :
input clock : Clock
input reset : Reset
output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>}
node _reg_T = eq(io.dir, UInt<1>(0h0))
node _reg_T_1 = mux(_reg_T, io.inR, io.inD)
reg reg : SInt<8>, clock
when io.en :
connect reg, _reg_T_1
connect io.outU, reg
connect io.outL, reg | module PE_116( // @[Transposer.scala:100:9]
input clock, // @[Transposer.scala:100:9]
input reset, // @[Transposer.scala:100:9]
input [7:0] io_inR, // @[Transposer.scala:101:16]
input [7:0] io_inD, // @[Transposer.scala:101:16]
output [7:0] io_outL, // @[Transposer.scala:101:16]
output [7:0] io_outU, // @[Transposer.scala:101:16]
input io_dir, // @[Transposer.scala:101:16]
input io_en // @[Transposer.scala:101:16]
);
wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9]
wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9]
wire io_dir_0 = io_dir; // @[Transposer.scala:100:9]
wire io_en_0 = io_en; // @[Transposer.scala:100:9]
wire [7:0] io_outL_0; // @[Transposer.scala:100:9]
wire [7:0] io_outU_0; // @[Transposer.scala:100:9]
wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36]
wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}]
reg [7:0] reg_0; // @[Transposer.scala:110:24]
assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
always @(posedge clock) begin // @[Transposer.scala:100:9]
if (io_en_0) // @[Transposer.scala:100:9]
reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}]
always @(posedge)
assign io_outL = io_outL_0; // @[Transposer.scala:100:9]
assign io_outU = io_outU_0; // @[Transposer.scala:100:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_40 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_40
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_40( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
output io_q // @[ShiftReg.scala:36:14]
);
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_40 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLAToNoC_7 :
input clock : Clock
input reset : Reset
output io : { flip protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, egress_id : UInt}}}
inst q of Queue1_TLBundleA_a32d128s7k6z4c_7
connect q.clock, clock
connect q.reset, reset
wire has_body : UInt<1>
node _head_T = and(q.io.deq.ready, q.io.deq.valid)
node _head_beats1_decode_T = dshl(UInt<12>(0hfff), q.io.deq.bits.size)
node _head_beats1_decode_T_1 = bits(_head_beats1_decode_T, 11, 0)
node _head_beats1_decode_T_2 = not(_head_beats1_decode_T_1)
node head_beats1_decode = shr(_head_beats1_decode_T_2, 4)
node _head_beats1_opdata_T = bits(q.io.deq.bits.opcode, 2, 2)
node head_beats1_opdata = eq(_head_beats1_opdata_T, UInt<1>(0h0))
node head_beats1 = mux(head_beats1_opdata, head_beats1_decode, UInt<1>(0h0))
regreset head_counter : UInt<8>, clock, reset, UInt<8>(0h0)
node _head_counter1_T = sub(head_counter, UInt<1>(0h1))
node head_counter1 = tail(_head_counter1_T, 1)
node head = eq(head_counter, UInt<1>(0h0))
node _head_last_T = eq(head_counter, UInt<1>(0h1))
node _head_last_T_1 = eq(head_beats1, UInt<1>(0h0))
node head_last = or(_head_last_T, _head_last_T_1)
node head_done = and(head_last, _head_T)
node _head_count_T = not(head_counter1)
node head_count = and(head_beats1, _head_count_T)
when _head_T :
node _head_counter_T = mux(head, head_beats1, head_counter1)
connect head_counter, _head_counter_T
node _tail_T = and(q.io.deq.ready, q.io.deq.valid)
node _tail_beats1_decode_T = dshl(UInt<12>(0hfff), q.io.deq.bits.size)
node _tail_beats1_decode_T_1 = bits(_tail_beats1_decode_T, 11, 0)
node _tail_beats1_decode_T_2 = not(_tail_beats1_decode_T_1)
node tail_beats1_decode = shr(_tail_beats1_decode_T_2, 4)
node _tail_beats1_opdata_T = bits(q.io.deq.bits.opcode, 2, 2)
node tail_beats1_opdata = eq(_tail_beats1_opdata_T, UInt<1>(0h0))
node tail_beats1 = mux(tail_beats1_opdata, tail_beats1_decode, UInt<1>(0h0))
regreset tail_counter : UInt<8>, clock, reset, UInt<8>(0h0)
node _tail_counter1_T = sub(tail_counter, UInt<1>(0h1))
node tail_counter1 = tail(_tail_counter1_T, 1)
node tail_first = eq(tail_counter, UInt<1>(0h0))
node _tail_last_T = eq(tail_counter, UInt<1>(0h1))
node _tail_last_T_1 = eq(tail_beats1, UInt<1>(0h0))
node tail = or(_tail_last_T, _tail_last_T_1)
node tail_done = and(tail, _tail_T)
node _tail_count_T = not(tail_counter1)
node tail_count = and(tail_beats1, _tail_count_T)
when _tail_T :
node _tail_counter_T = mux(tail_first, tail_beats1, tail_counter1)
connect tail_counter, _tail_counter_T
node body_hi = cat(q.io.deq.bits.mask, q.io.deq.bits.data)
node body = cat(body_hi, q.io.deq.bits.corrupt)
node const_lo = cat(q.io.deq.bits.source, q.io.deq.bits.address)
node const_hi_hi = cat(q.io.deq.bits.opcode, q.io.deq.bits.param)
node const_hi = cat(const_hi_hi, q.io.deq.bits.size)
node const = cat(const_hi, const_lo)
regreset is_body : UInt<1>, clock, reset, UInt<1>(0h0)
connect io.flit.valid, q.io.deq.valid
node _q_io_deq_ready_T = eq(has_body, UInt<1>(0h0))
node _q_io_deq_ready_T_1 = or(is_body, _q_io_deq_ready_T)
node _q_io_deq_ready_T_2 = and(io.flit.ready, _q_io_deq_ready_T_1)
connect q.io.deq.ready, _q_io_deq_ready_T_2
node _io_flit_bits_head_T = eq(is_body, UInt<1>(0h0))
node _io_flit_bits_head_T_1 = and(head, _io_flit_bits_head_T)
connect io.flit.bits.head, _io_flit_bits_head_T_1
node _io_flit_bits_tail_T = eq(has_body, UInt<1>(0h0))
node _io_flit_bits_tail_T_1 = or(is_body, _io_flit_bits_tail_T)
node _io_flit_bits_tail_T_2 = and(tail, _io_flit_bits_tail_T_1)
connect io.flit.bits.tail, _io_flit_bits_tail_T_2
node _io_flit_bits_egress_id_requestOH_T = xor(q.io.deq.bits.address, UInt<1>(0h0))
node _io_flit_bits_egress_id_requestOH_T_1 = cvt(_io_flit_bits_egress_id_requestOH_T)
node _io_flit_bits_egress_id_requestOH_T_2 = and(_io_flit_bits_egress_id_requestOH_T_1, asSInt(UInt<33>(0h8c000000)))
node _io_flit_bits_egress_id_requestOH_T_3 = asSInt(_io_flit_bits_egress_id_requestOH_T_2)
node _io_flit_bits_egress_id_requestOH_T_4 = eq(_io_flit_bits_egress_id_requestOH_T_3, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_5 = xor(q.io.deq.bits.address, UInt<17>(0h10000))
node _io_flit_bits_egress_id_requestOH_T_6 = cvt(_io_flit_bits_egress_id_requestOH_T_5)
node _io_flit_bits_egress_id_requestOH_T_7 = and(_io_flit_bits_egress_id_requestOH_T_6, asSInt(UInt<33>(0h8c011000)))
node _io_flit_bits_egress_id_requestOH_T_8 = asSInt(_io_flit_bits_egress_id_requestOH_T_7)
node _io_flit_bits_egress_id_requestOH_T_9 = eq(_io_flit_bits_egress_id_requestOH_T_8, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_10 = xor(q.io.deq.bits.address, UInt<28>(0hc000000))
node _io_flit_bits_egress_id_requestOH_T_11 = cvt(_io_flit_bits_egress_id_requestOH_T_10)
node _io_flit_bits_egress_id_requestOH_T_12 = and(_io_flit_bits_egress_id_requestOH_T_11, asSInt(UInt<33>(0h8c000000)))
node _io_flit_bits_egress_id_requestOH_T_13 = asSInt(_io_flit_bits_egress_id_requestOH_T_12)
node _io_flit_bits_egress_id_requestOH_T_14 = eq(_io_flit_bits_egress_id_requestOH_T_13, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_15 = or(_io_flit_bits_egress_id_requestOH_T_4, _io_flit_bits_egress_id_requestOH_T_9)
node _io_flit_bits_egress_id_requestOH_T_16 = or(_io_flit_bits_egress_id_requestOH_T_15, _io_flit_bits_egress_id_requestOH_T_14)
node _io_flit_bits_egress_id_requestOH_T_17 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_16)
node io_flit_bits_egress_id_requestOH_0 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_17)
node _io_flit_bits_egress_id_requestOH_T_18 = xor(q.io.deq.bits.address, UInt<28>(0h8000000))
node _io_flit_bits_egress_id_requestOH_T_19 = cvt(_io_flit_bits_egress_id_requestOH_T_18)
node _io_flit_bits_egress_id_requestOH_T_20 = and(_io_flit_bits_egress_id_requestOH_T_19, asSInt(UInt<33>(0h8c0100c0)))
node _io_flit_bits_egress_id_requestOH_T_21 = asSInt(_io_flit_bits_egress_id_requestOH_T_20)
node _io_flit_bits_egress_id_requestOH_T_22 = eq(_io_flit_bits_egress_id_requestOH_T_21, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_23 = xor(q.io.deq.bits.address, UInt<32>(0h80000000))
node _io_flit_bits_egress_id_requestOH_T_24 = cvt(_io_flit_bits_egress_id_requestOH_T_23)
node _io_flit_bits_egress_id_requestOH_T_25 = and(_io_flit_bits_egress_id_requestOH_T_24, asSInt(UInt<33>(0h800000c0)))
node _io_flit_bits_egress_id_requestOH_T_26 = asSInt(_io_flit_bits_egress_id_requestOH_T_25)
node _io_flit_bits_egress_id_requestOH_T_27 = eq(_io_flit_bits_egress_id_requestOH_T_26, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_28 = or(_io_flit_bits_egress_id_requestOH_T_22, _io_flit_bits_egress_id_requestOH_T_27)
node _io_flit_bits_egress_id_requestOH_T_29 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_28)
node io_flit_bits_egress_id_requestOH_1 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_29)
node _io_flit_bits_egress_id_requestOH_T_30 = xor(q.io.deq.bits.address, UInt<28>(0h8000040))
node _io_flit_bits_egress_id_requestOH_T_31 = cvt(_io_flit_bits_egress_id_requestOH_T_30)
node _io_flit_bits_egress_id_requestOH_T_32 = and(_io_flit_bits_egress_id_requestOH_T_31, asSInt(UInt<33>(0h8c0100c0)))
node _io_flit_bits_egress_id_requestOH_T_33 = asSInt(_io_flit_bits_egress_id_requestOH_T_32)
node _io_flit_bits_egress_id_requestOH_T_34 = eq(_io_flit_bits_egress_id_requestOH_T_33, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_35 = xor(q.io.deq.bits.address, UInt<32>(0h80000040))
node _io_flit_bits_egress_id_requestOH_T_36 = cvt(_io_flit_bits_egress_id_requestOH_T_35)
node _io_flit_bits_egress_id_requestOH_T_37 = and(_io_flit_bits_egress_id_requestOH_T_36, asSInt(UInt<33>(0h800000c0)))
node _io_flit_bits_egress_id_requestOH_T_38 = asSInt(_io_flit_bits_egress_id_requestOH_T_37)
node _io_flit_bits_egress_id_requestOH_T_39 = eq(_io_flit_bits_egress_id_requestOH_T_38, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_40 = or(_io_flit_bits_egress_id_requestOH_T_34, _io_flit_bits_egress_id_requestOH_T_39)
node _io_flit_bits_egress_id_requestOH_T_41 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_40)
node io_flit_bits_egress_id_requestOH_2 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_41)
node _io_flit_bits_egress_id_requestOH_T_42 = xor(q.io.deq.bits.address, UInt<28>(0h8000080))
node _io_flit_bits_egress_id_requestOH_T_43 = cvt(_io_flit_bits_egress_id_requestOH_T_42)
node _io_flit_bits_egress_id_requestOH_T_44 = and(_io_flit_bits_egress_id_requestOH_T_43, asSInt(UInt<33>(0h8c0100c0)))
node _io_flit_bits_egress_id_requestOH_T_45 = asSInt(_io_flit_bits_egress_id_requestOH_T_44)
node _io_flit_bits_egress_id_requestOH_T_46 = eq(_io_flit_bits_egress_id_requestOH_T_45, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_47 = xor(q.io.deq.bits.address, UInt<32>(0h80000080))
node _io_flit_bits_egress_id_requestOH_T_48 = cvt(_io_flit_bits_egress_id_requestOH_T_47)
node _io_flit_bits_egress_id_requestOH_T_49 = and(_io_flit_bits_egress_id_requestOH_T_48, asSInt(UInt<33>(0h800000c0)))
node _io_flit_bits_egress_id_requestOH_T_50 = asSInt(_io_flit_bits_egress_id_requestOH_T_49)
node _io_flit_bits_egress_id_requestOH_T_51 = eq(_io_flit_bits_egress_id_requestOH_T_50, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_52 = or(_io_flit_bits_egress_id_requestOH_T_46, _io_flit_bits_egress_id_requestOH_T_51)
node _io_flit_bits_egress_id_requestOH_T_53 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_52)
node io_flit_bits_egress_id_requestOH_3 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_53)
node _io_flit_bits_egress_id_requestOH_T_54 = xor(q.io.deq.bits.address, UInt<28>(0h80000c0))
node _io_flit_bits_egress_id_requestOH_T_55 = cvt(_io_flit_bits_egress_id_requestOH_T_54)
node _io_flit_bits_egress_id_requestOH_T_56 = and(_io_flit_bits_egress_id_requestOH_T_55, asSInt(UInt<33>(0h8c0100c0)))
node _io_flit_bits_egress_id_requestOH_T_57 = asSInt(_io_flit_bits_egress_id_requestOH_T_56)
node _io_flit_bits_egress_id_requestOH_T_58 = eq(_io_flit_bits_egress_id_requestOH_T_57, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_59 = xor(q.io.deq.bits.address, UInt<32>(0h800000c0))
node _io_flit_bits_egress_id_requestOH_T_60 = cvt(_io_flit_bits_egress_id_requestOH_T_59)
node _io_flit_bits_egress_id_requestOH_T_61 = and(_io_flit_bits_egress_id_requestOH_T_60, asSInt(UInt<33>(0h800000c0)))
node _io_flit_bits_egress_id_requestOH_T_62 = asSInt(_io_flit_bits_egress_id_requestOH_T_61)
node _io_flit_bits_egress_id_requestOH_T_63 = eq(_io_flit_bits_egress_id_requestOH_T_62, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_64 = or(_io_flit_bits_egress_id_requestOH_T_58, _io_flit_bits_egress_id_requestOH_T_63)
node _io_flit_bits_egress_id_requestOH_T_65 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_64)
node io_flit_bits_egress_id_requestOH_4 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_65)
node _io_flit_bits_egress_id_T = mux(io_flit_bits_egress_id_requestOH_0, UInt<4>(0hd), UInt<1>(0h0))
node _io_flit_bits_egress_id_T_1 = mux(io_flit_bits_egress_id_requestOH_1, UInt<4>(0hf), UInt<1>(0h0))
node _io_flit_bits_egress_id_T_2 = mux(io_flit_bits_egress_id_requestOH_2, UInt<5>(0h11), UInt<1>(0h0))
node _io_flit_bits_egress_id_T_3 = mux(io_flit_bits_egress_id_requestOH_3, UInt<5>(0h13), UInt<1>(0h0))
node _io_flit_bits_egress_id_T_4 = mux(io_flit_bits_egress_id_requestOH_4, UInt<5>(0h15), UInt<1>(0h0))
node _io_flit_bits_egress_id_T_5 = or(_io_flit_bits_egress_id_T, _io_flit_bits_egress_id_T_1)
node _io_flit_bits_egress_id_T_6 = or(_io_flit_bits_egress_id_T_5, _io_flit_bits_egress_id_T_2)
node _io_flit_bits_egress_id_T_7 = or(_io_flit_bits_egress_id_T_6, _io_flit_bits_egress_id_T_3)
node _io_flit_bits_egress_id_T_8 = or(_io_flit_bits_egress_id_T_7, _io_flit_bits_egress_id_T_4)
wire _io_flit_bits_egress_id_WIRE : UInt<5>
connect _io_flit_bits_egress_id_WIRE, _io_flit_bits_egress_id_T_8
connect io.flit.bits.egress_id, _io_flit_bits_egress_id_WIRE
node _io_flit_bits_payload_T = mux(is_body, body, const)
connect io.flit.bits.payload, _io_flit_bits_payload_T
node _T = and(io.flit.ready, io.flit.valid)
node _T_1 = and(_T, io.flit.bits.head)
when _T_1 :
connect is_body, UInt<1>(0h1)
node _T_2 = and(io.flit.ready, io.flit.valid)
node _T_3 = and(_T_2, io.flit.bits.tail)
when _T_3 :
connect is_body, UInt<1>(0h0)
node _has_body_opdata_T = bits(q.io.deq.bits.opcode, 2, 2)
node has_body_opdata = eq(_has_body_opdata_T, UInt<1>(0h0))
node _has_body_T = not(q.io.deq.bits.mask)
node _has_body_T_1 = neq(_has_body_T, UInt<1>(0h0))
node _has_body_T_2 = or(has_body_opdata, _has_body_T_1)
connect has_body, _has_body_T_2
connect q.io.enq, io.protocol
node _q_io_enq_bits_source_T = or(io.protocol.bits.source, UInt<6>(0h34))
connect q.io.enq.bits.source, _q_io_enq_bits_source_T | module TLAToNoC_7( // @[TilelinkAdapters.scala:112:7]
input clock, // @[TilelinkAdapters.scala:112:7]
input reset, // @[TilelinkAdapters.scala:112:7]
output io_protocol_ready, // @[TilelinkAdapters.scala:19:14]
input io_protocol_valid, // @[TilelinkAdapters.scala:19:14]
input [2:0] io_protocol_bits_opcode, // @[TilelinkAdapters.scala:19:14]
input [2:0] io_protocol_bits_param, // @[TilelinkAdapters.scala:19:14]
input [3:0] io_protocol_bits_size, // @[TilelinkAdapters.scala:19:14]
input [6:0] io_protocol_bits_source, // @[TilelinkAdapters.scala:19:14]
input [31:0] io_protocol_bits_address, // @[TilelinkAdapters.scala:19:14]
input [15:0] io_protocol_bits_mask, // @[TilelinkAdapters.scala:19:14]
input [127:0] io_protocol_bits_data, // @[TilelinkAdapters.scala:19:14]
input io_protocol_bits_corrupt, // @[TilelinkAdapters.scala:19:14]
input io_flit_ready, // @[TilelinkAdapters.scala:19:14]
output io_flit_valid, // @[TilelinkAdapters.scala:19:14]
output io_flit_bits_head, // @[TilelinkAdapters.scala:19:14]
output io_flit_bits_tail, // @[TilelinkAdapters.scala:19:14]
output [144:0] io_flit_bits_payload, // @[TilelinkAdapters.scala:19:14]
output [4:0] io_flit_bits_egress_id // @[TilelinkAdapters.scala:19:14]
);
wire [16:0] _GEN; // @[TilelinkAdapters.scala:119:{45,69}]
wire _q_io_deq_valid; // @[TilelinkAdapters.scala:26:17]
wire [2:0] _q_io_deq_bits_opcode; // @[TilelinkAdapters.scala:26:17]
wire [2:0] _q_io_deq_bits_param; // @[TilelinkAdapters.scala:26:17]
wire [3:0] _q_io_deq_bits_size; // @[TilelinkAdapters.scala:26:17]
wire [6:0] _q_io_deq_bits_source; // @[TilelinkAdapters.scala:26:17]
wire [31:0] _q_io_deq_bits_address; // @[TilelinkAdapters.scala:26:17]
wire [15:0] _q_io_deq_bits_mask; // @[TilelinkAdapters.scala:26:17]
wire [127:0] _q_io_deq_bits_data; // @[TilelinkAdapters.scala:26:17]
wire _q_io_deq_bits_corrupt; // @[TilelinkAdapters.scala:26:17]
wire [26:0] _tail_beats1_decode_T = 27'hFFF << _q_io_deq_bits_size; // @[package.scala:243:71]
reg [7:0] head_counter; // @[Edges.scala:229:27]
wire head = head_counter == 8'h0; // @[Edges.scala:229:27, :231:25]
wire [7:0] tail_beats1 = _q_io_deq_bits_opcode[2] ? 8'h0 : ~(_tail_beats1_decode_T[11:4]); // @[package.scala:243:{46,71,76}]
reg [7:0] tail_counter; // @[Edges.scala:229:27]
reg is_body; // @[TilelinkAdapters.scala:39:24]
wire _io_flit_bits_tail_T = _GEN == 17'h0; // @[TilelinkAdapters.scala:119:{45,69}]
wire q_io_deq_ready = io_flit_ready & (is_body | _io_flit_bits_tail_T); // @[TilelinkAdapters.scala:39:24, :41:{35,47}, :119:{45,69}]
wire io_flit_bits_head_0 = head & ~is_body; // @[Edges.scala:231:25]
wire io_flit_bits_tail_0 = (tail_counter == 8'h1 | tail_beats1 == 8'h0) & (is_body | _io_flit_bits_tail_T); // @[Edges.scala:221:14, :229:27, :232:{25,33,43}]
wire [21:0] _GEN_0 = _q_io_deq_bits_address[27:6] ^ 22'h200001; // @[Parameters.scala:137:31]
wire [25:0] _io_flit_bits_egress_id_requestOH_T_35 = _q_io_deq_bits_address[31:6] ^ 26'h2000001; // @[Parameters.scala:137:31]
wire [21:0] _GEN_1 = _q_io_deq_bits_address[27:6] ^ 22'h200002; // @[Parameters.scala:137:31]
wire [25:0] _io_flit_bits_egress_id_requestOH_T_47 = _q_io_deq_bits_address[31:6] ^ 26'h2000002; // @[Parameters.scala:137:31]
wire [21:0] _GEN_2 = _q_io_deq_bits_address[27:6] ^ 22'h200003; // @[Parameters.scala:137:31]
wire [25:0] _io_flit_bits_egress_id_requestOH_T_59 = _q_io_deq_bits_address[31:6] ^ 26'h2000003; // @[Parameters.scala:137:31]
assign _GEN = {~(_q_io_deq_bits_opcode[2]), ~_q_io_deq_bits_mask}; // @[Edges.scala:92:{28,37}]
wire _GEN_3 = io_flit_ready & _q_io_deq_valid; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[TilelinkAdapters.scala:112:7]
if (reset) begin // @[TilelinkAdapters.scala:112:7]
head_counter <= 8'h0; // @[Edges.scala:229:27]
tail_counter <= 8'h0; // @[Edges.scala:229:27]
is_body <= 1'h0; // @[TilelinkAdapters.scala:39:24, :112:7]
end
else begin // @[TilelinkAdapters.scala:112:7]
if (q_io_deq_ready & _q_io_deq_valid) begin // @[Decoupled.scala:51:35]
head_counter <= head ? (_q_io_deq_bits_opcode[2] ? 8'h0 : ~(_tail_beats1_decode_T[11:4])) : head_counter - 8'h1; // @[package.scala:243:{46,71,76}]
tail_counter <= tail_counter == 8'h0 ? tail_beats1 : tail_counter - 8'h1; // @[Edges.scala:221:14, :229:27, :230:28, :231:25, :236:21]
end
is_body <= ~(_GEN_3 & io_flit_bits_tail_0) & (_GEN_3 & io_flit_bits_head_0 | is_body); // @[Decoupled.scala:51:35]
end
always @(posedge) |
Generate the Verilog code corresponding to this FIRRTL code module PE_349 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>}
inst mac_unit of MacUnit_93
connect mac_unit.clock, clock
connect mac_unit.reset, reset
reg c1 : SInt<32>, clock
reg c2 : SInt<32>, clock
connect io.out_a, io.in_a
connect io.out_control.dataflow, io.in_control.dataflow
connect io.out_control.propagate, io.in_control.propagate
connect io.out_control.shift, io.in_control.shift
connect io.out_id, io.in_id
connect io.out_last, io.in_last
connect io.out_valid, io.in_valid
connect mac_unit.io.in_a, io.in_a
reg last_s : UInt<1>, clock
when io.in_valid :
connect last_s, io.in_control.propagate
node flip = neq(last_s, io.in_control.propagate)
node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0))
connect io.bad_dataflow, UInt<1>(0h0)
node _T = eq(io.in_control.dataflow, UInt<1>(0h0))
node _T_1 = and(UInt<1>(0h1), _T)
node _T_2 = or(UInt<1>(0h0), _T_1)
when _T_2 :
node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_3 :
node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1)
node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2)
node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0)
node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4)
node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_1 = asUInt(c1)
node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1)
node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3)
node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1))
node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1)
node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6)
node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7)
node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0))
node _io_out_c_ones_digit_T = dshr(c1, shift_offset)
node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0)
node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit)
node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T)
node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0)
node _io_out_c_T = dshr(c1, shift_offset)
node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1)
node _io_out_c_T_3 = tail(_io_out_c_T_2, 1)
node _io_out_c_T_4 = asSInt(_io_out_c_T_3)
node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4)
node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7)
node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0)
node _io_out_c_T_10 = asSInt(_io_out_c_T_9)
connect io.out_c, _io_out_c_T_10
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE : SInt<8>
node _mac_unit_io_in_b_T = asUInt(io.in_b)
node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T)
connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE
connect mac_unit.io.in_c, c2
connect c2, mac_unit.io.out_d
node c1_sign = bits(io.in_d, 19, 19)
node c1_lo_lo_hi = cat(c1_sign, c1_sign)
node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign)
node c1_lo_hi_hi = cat(c1_sign, c1_sign)
node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign)
node c1_lo = cat(c1_lo_hi, c1_lo_lo)
node c1_hi_lo_hi = cat(c1_sign, c1_sign)
node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign)
node c1_hi_hi_hi = cat(c1_sign, c1_sign)
node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign)
node c1_hi = cat(c1_hi_hi, c1_hi_lo)
node _c1_T = cat(c1_hi, c1_lo)
node c1_lo_1 = asUInt(io.in_d)
node _c1_T_1 = cat(_c1_T, c1_lo_1)
wire _c1_WIRE : SInt<32>
node _c1_T_2 = asSInt(_c1_T_1)
connect _c1_WIRE, _c1_T_2
connect c1, _c1_WIRE
else :
node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1)
node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7)
node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0)
node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9)
node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_10 = asUInt(c2)
node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1)
node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12)
node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1))
node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1)
node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15)
node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16)
node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0))
node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset)
node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0)
node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1)
node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2)
node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0)
node _io_out_c_T_11 = dshr(c2, shift_offset)
node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12)
node _io_out_c_T_14 = tail(_io_out_c_T_13, 1)
node _io_out_c_T_15 = asSInt(_io_out_c_T_14)
node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15)
node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18)
node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0)
node _io_out_c_T_21 = asSInt(_io_out_c_T_20)
connect io.out_c, _io_out_c_T_21
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE_1 : SInt<8>
node _mac_unit_io_in_b_T_2 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2)
connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1
connect mac_unit.io.in_c, c1
connect c1, mac_unit.io.out_d
node c2_sign = bits(io.in_d, 19, 19)
node c2_lo_lo_hi = cat(c2_sign, c2_sign)
node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign)
node c2_lo_hi_hi = cat(c2_sign, c2_sign)
node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign)
node c2_lo = cat(c2_lo_hi, c2_lo_lo)
node c2_hi_lo_hi = cat(c2_sign, c2_sign)
node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign)
node c2_hi_hi_hi = cat(c2_sign, c2_sign)
node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign)
node c2_hi = cat(c2_hi_hi, c2_hi_lo)
node _c2_T = cat(c2_hi, c2_lo)
node c2_lo_1 = asUInt(io.in_d)
node _c2_T_1 = cat(_c2_T, c2_lo_1)
wire _c2_WIRE : SInt<32>
node _c2_T_2 = asSInt(_c2_T_1)
connect _c2_WIRE, _c2_T_2
connect c2, _c2_WIRE
else :
node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1))
node _T_5 = and(UInt<1>(0h1), _T_4)
node _T_6 = or(UInt<1>(0h0), _T_5)
when _T_6 :
node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_7 :
connect io.out_c, c1
wire _mac_unit_io_in_b_WIRE_2 : SInt<8>
node _mac_unit_io_in_b_T_4 = asUInt(c2)
node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4)
connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c1, io.in_d
else :
connect io.out_c, c2
wire _mac_unit_io_in_b_WIRE_3 : SInt<8>
node _mac_unit_io_in_b_T_6 = asUInt(c1)
node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6)
connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c2, io.in_d
else :
connect io.bad_dataflow, UInt<1>(0h1)
invalidate io.out_c
invalidate io.out_b
wire _mac_unit_io_in_b_WIRE_4 : SInt<8>
node _mac_unit_io_in_b_T_8 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8)
connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4
connect mac_unit.io.in_c, c2
node _T_8 = eq(io.in_valid, UInt<1>(0h0))
when _T_8 :
connect c1, c1
connect c2, c2
invalidate mac_unit.io.in_b
invalidate mac_unit.io.in_c | module PE_349( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid, // @[PE.scala:35:14]
output io_bad_dataflow // @[PE.scala:35:14]
);
wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24]
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [31:0] c1; // @[PE.scala:70:15]
wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [31:0] c2; // @[PE.scala:71:15]
wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25]
wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61]
wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38]
wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38]
assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16]
assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10]
wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10]
c1 <= _GEN_7; // @[PE.scala:70:15, :124:10]
if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30]
end
else // @[PE.scala:71:15, :118:101, :119:30]
c2 <= _GEN_7; // @[PE.scala:71:15, :124:10]
end
else begin // @[PE.scala:31:7]
c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10]
c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10]
end
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
end
always @(posedge)
MacUnit_93 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24]
.io_out_d (_mac_unit_io_out_d)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module Tile_41 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>}
inst tile_0_0 of PE_297
connect tile_0_0.clock, clock
connect tile_0_0.reset, reset
connect tile_0_0.io.in_a, io.in_a[0]
connect tile_0_0.io.in_b, io.in_b[0]
connect tile_0_0.io.in_d, io.in_d[0]
connect tile_0_0.io.in_control.shift, io.in_control[0].shift
connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate
connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow
connect tile_0_0.io.in_valid, io.in_valid[0]
connect tile_0_0.io.in_id, io.in_id[0]
connect tile_0_0.io.in_last, io.in_last[0]
connect io.out_c[0], tile_0_0.io.out_c
connect io.out_control[0], tile_0_0.io.out_control
connect io.out_id[0], tile_0_0.io.out_id
connect io.out_last[0], tile_0_0.io.out_last
connect io.out_valid[0], tile_0_0.io.out_valid
connect io.out_b[0], tile_0_0.io.out_b
connect io.bad_dataflow, tile_0_0.io.bad_dataflow
connect io.out_a[0], tile_0_0.io.out_a | module Tile_41( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0 // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
PE_297 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_205 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_sink_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_222
connect io_out_sink_valid_1.clock, clock
connect io_out_sink_valid_1.reset, reset
connect io_out_sink_valid_1.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_sink_valid_1.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_205( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_222 io_out_sink_valid_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_104 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_172
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_104( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_172 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PE_437 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>}
inst mac_unit of MacUnit_181
connect mac_unit.clock, clock
connect mac_unit.reset, reset
reg c1 : SInt<32>, clock
reg c2 : SInt<32>, clock
connect io.out_a, io.in_a
connect io.out_control.dataflow, io.in_control.dataflow
connect io.out_control.propagate, io.in_control.propagate
connect io.out_control.shift, io.in_control.shift
connect io.out_id, io.in_id
connect io.out_last, io.in_last
connect io.out_valid, io.in_valid
connect mac_unit.io.in_a, io.in_a
reg last_s : UInt<1>, clock
when io.in_valid :
connect last_s, io.in_control.propagate
node flip = neq(last_s, io.in_control.propagate)
node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0))
connect io.bad_dataflow, UInt<1>(0h0)
node _T = eq(io.in_control.dataflow, UInt<1>(0h0))
node _T_1 = and(UInt<1>(0h1), _T)
node _T_2 = or(UInt<1>(0h0), _T_1)
when _T_2 :
node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_3 :
node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1)
node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2)
node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0)
node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4)
node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_1 = asUInt(c1)
node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1)
node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3)
node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1))
node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1)
node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6)
node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7)
node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0))
node _io_out_c_ones_digit_T = dshr(c1, shift_offset)
node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0)
node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit)
node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T)
node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0)
node _io_out_c_T = dshr(c1, shift_offset)
node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1)
node _io_out_c_T_3 = tail(_io_out_c_T_2, 1)
node _io_out_c_T_4 = asSInt(_io_out_c_T_3)
node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4)
node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7)
node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0)
node _io_out_c_T_10 = asSInt(_io_out_c_T_9)
connect io.out_c, _io_out_c_T_10
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE : SInt<8>
node _mac_unit_io_in_b_T = asUInt(io.in_b)
node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T)
connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE
connect mac_unit.io.in_c, c2
connect c2, mac_unit.io.out_d
node c1_sign = bits(io.in_d, 19, 19)
node c1_lo_lo_hi = cat(c1_sign, c1_sign)
node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign)
node c1_lo_hi_hi = cat(c1_sign, c1_sign)
node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign)
node c1_lo = cat(c1_lo_hi, c1_lo_lo)
node c1_hi_lo_hi = cat(c1_sign, c1_sign)
node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign)
node c1_hi_hi_hi = cat(c1_sign, c1_sign)
node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign)
node c1_hi = cat(c1_hi_hi, c1_hi_lo)
node _c1_T = cat(c1_hi, c1_lo)
node c1_lo_1 = asUInt(io.in_d)
node _c1_T_1 = cat(_c1_T, c1_lo_1)
wire _c1_WIRE : SInt<32>
node _c1_T_2 = asSInt(_c1_T_1)
connect _c1_WIRE, _c1_T_2
connect c1, _c1_WIRE
else :
node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1)
node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7)
node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0)
node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9)
node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_10 = asUInt(c2)
node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1)
node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12)
node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1))
node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1)
node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15)
node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16)
node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0))
node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset)
node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0)
node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1)
node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2)
node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0)
node _io_out_c_T_11 = dshr(c2, shift_offset)
node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12)
node _io_out_c_T_14 = tail(_io_out_c_T_13, 1)
node _io_out_c_T_15 = asSInt(_io_out_c_T_14)
node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15)
node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18)
node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0)
node _io_out_c_T_21 = asSInt(_io_out_c_T_20)
connect io.out_c, _io_out_c_T_21
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE_1 : SInt<8>
node _mac_unit_io_in_b_T_2 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2)
connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1
connect mac_unit.io.in_c, c1
connect c1, mac_unit.io.out_d
node c2_sign = bits(io.in_d, 19, 19)
node c2_lo_lo_hi = cat(c2_sign, c2_sign)
node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign)
node c2_lo_hi_hi = cat(c2_sign, c2_sign)
node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign)
node c2_lo = cat(c2_lo_hi, c2_lo_lo)
node c2_hi_lo_hi = cat(c2_sign, c2_sign)
node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign)
node c2_hi_hi_hi = cat(c2_sign, c2_sign)
node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign)
node c2_hi = cat(c2_hi_hi, c2_hi_lo)
node _c2_T = cat(c2_hi, c2_lo)
node c2_lo_1 = asUInt(io.in_d)
node _c2_T_1 = cat(_c2_T, c2_lo_1)
wire _c2_WIRE : SInt<32>
node _c2_T_2 = asSInt(_c2_T_1)
connect _c2_WIRE, _c2_T_2
connect c2, _c2_WIRE
else :
node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1))
node _T_5 = and(UInt<1>(0h1), _T_4)
node _T_6 = or(UInt<1>(0h0), _T_5)
when _T_6 :
node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_7 :
connect io.out_c, c1
wire _mac_unit_io_in_b_WIRE_2 : SInt<8>
node _mac_unit_io_in_b_T_4 = asUInt(c2)
node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4)
connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c1, io.in_d
else :
connect io.out_c, c2
wire _mac_unit_io_in_b_WIRE_3 : SInt<8>
node _mac_unit_io_in_b_T_6 = asUInt(c1)
node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6)
connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c2, io.in_d
else :
connect io.bad_dataflow, UInt<1>(0h1)
invalidate io.out_c
invalidate io.out_b
wire _mac_unit_io_in_b_WIRE_4 : SInt<8>
node _mac_unit_io_in_b_T_8 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8)
connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4
connect mac_unit.io.in_c, c2
node _T_8 = eq(io.in_valid, UInt<1>(0h0))
when _T_8 :
connect c1, c1
connect c2, c2
invalidate mac_unit.io.in_b
invalidate mac_unit.io.in_c | module PE_437( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid, // @[PE.scala:35:14]
output io_bad_dataflow // @[PE.scala:35:14]
);
wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24]
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [31:0] c1; // @[PE.scala:70:15]
wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [31:0] c2; // @[PE.scala:71:15]
wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25]
wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61]
wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38]
wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38]
assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16]
assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10]
wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10]
c1 <= _GEN_7; // @[PE.scala:70:15, :124:10]
if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30]
end
else // @[PE.scala:71:15, :118:101, :119:30]
c2 <= _GEN_7; // @[PE.scala:71:15, :124:10]
end
else begin // @[PE.scala:31:7]
c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10]
c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10]
end
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
end
always @(posedge)
MacUnit_181 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24]
.io_out_d (_mac_unit_io_out_d)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module IntSyncCrossingSource_n0x0_9 :
input clock : Clock
input reset : Reset
output auto : { }
skip | module IntSyncCrossingSource_n0x0_9( // @[Crossing.scala:41:9]
input clock, // @[Crossing.scala:41:9]
input reset // @[Crossing.scala:41:9]
);
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLCacheCork :
input clock : Clock
input reset : Reset
output auto : { flip in_3 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip in_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip in_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, out_3 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate nodeIn.e.bits.sink
invalidate nodeIn.e.valid
invalidate nodeIn.e.ready
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.c.bits.corrupt
invalidate nodeIn.c.bits.data
invalidate nodeIn.c.bits.address
invalidate nodeIn.c.bits.source
invalidate nodeIn.c.bits.size
invalidate nodeIn.c.bits.param
invalidate nodeIn.c.bits.opcode
invalidate nodeIn.c.valid
invalidate nodeIn.c.ready
invalidate nodeIn.b.bits.corrupt
invalidate nodeIn.b.bits.data
invalidate nodeIn.b.bits.mask
invalidate nodeIn.b.bits.address
invalidate nodeIn.b.bits.source
invalidate nodeIn.b.bits.size
invalidate nodeIn.b.bits.param
invalidate nodeIn.b.bits.opcode
invalidate nodeIn.b.valid
invalidate nodeIn.b.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
wire nodeIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate nodeIn_1.e.bits.sink
invalidate nodeIn_1.e.valid
invalidate nodeIn_1.e.ready
invalidate nodeIn_1.d.bits.corrupt
invalidate nodeIn_1.d.bits.data
invalidate nodeIn_1.d.bits.denied
invalidate nodeIn_1.d.bits.sink
invalidate nodeIn_1.d.bits.source
invalidate nodeIn_1.d.bits.size
invalidate nodeIn_1.d.bits.param
invalidate nodeIn_1.d.bits.opcode
invalidate nodeIn_1.d.valid
invalidate nodeIn_1.d.ready
invalidate nodeIn_1.c.bits.corrupt
invalidate nodeIn_1.c.bits.data
invalidate nodeIn_1.c.bits.address
invalidate nodeIn_1.c.bits.source
invalidate nodeIn_1.c.bits.size
invalidate nodeIn_1.c.bits.param
invalidate nodeIn_1.c.bits.opcode
invalidate nodeIn_1.c.valid
invalidate nodeIn_1.c.ready
invalidate nodeIn_1.b.bits.corrupt
invalidate nodeIn_1.b.bits.data
invalidate nodeIn_1.b.bits.mask
invalidate nodeIn_1.b.bits.address
invalidate nodeIn_1.b.bits.source
invalidate nodeIn_1.b.bits.size
invalidate nodeIn_1.b.bits.param
invalidate nodeIn_1.b.bits.opcode
invalidate nodeIn_1.b.valid
invalidate nodeIn_1.b.ready
invalidate nodeIn_1.a.bits.corrupt
invalidate nodeIn_1.a.bits.data
invalidate nodeIn_1.a.bits.mask
invalidate nodeIn_1.a.bits.address
invalidate nodeIn_1.a.bits.source
invalidate nodeIn_1.a.bits.size
invalidate nodeIn_1.a.bits.param
invalidate nodeIn_1.a.bits.opcode
invalidate nodeIn_1.a.valid
invalidate nodeIn_1.a.ready
wire nodeIn_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate nodeIn_2.e.bits.sink
invalidate nodeIn_2.e.valid
invalidate nodeIn_2.e.ready
invalidate nodeIn_2.d.bits.corrupt
invalidate nodeIn_2.d.bits.data
invalidate nodeIn_2.d.bits.denied
invalidate nodeIn_2.d.bits.sink
invalidate nodeIn_2.d.bits.source
invalidate nodeIn_2.d.bits.size
invalidate nodeIn_2.d.bits.param
invalidate nodeIn_2.d.bits.opcode
invalidate nodeIn_2.d.valid
invalidate nodeIn_2.d.ready
invalidate nodeIn_2.c.bits.corrupt
invalidate nodeIn_2.c.bits.data
invalidate nodeIn_2.c.bits.address
invalidate nodeIn_2.c.bits.source
invalidate nodeIn_2.c.bits.size
invalidate nodeIn_2.c.bits.param
invalidate nodeIn_2.c.bits.opcode
invalidate nodeIn_2.c.valid
invalidate nodeIn_2.c.ready
invalidate nodeIn_2.b.bits.corrupt
invalidate nodeIn_2.b.bits.data
invalidate nodeIn_2.b.bits.mask
invalidate nodeIn_2.b.bits.address
invalidate nodeIn_2.b.bits.source
invalidate nodeIn_2.b.bits.size
invalidate nodeIn_2.b.bits.param
invalidate nodeIn_2.b.bits.opcode
invalidate nodeIn_2.b.valid
invalidate nodeIn_2.b.ready
invalidate nodeIn_2.a.bits.corrupt
invalidate nodeIn_2.a.bits.data
invalidate nodeIn_2.a.bits.mask
invalidate nodeIn_2.a.bits.address
invalidate nodeIn_2.a.bits.source
invalidate nodeIn_2.a.bits.size
invalidate nodeIn_2.a.bits.param
invalidate nodeIn_2.a.bits.opcode
invalidate nodeIn_2.a.valid
invalidate nodeIn_2.a.ready
wire nodeIn_3 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate nodeIn_3.e.bits.sink
invalidate nodeIn_3.e.valid
invalidate nodeIn_3.e.ready
invalidate nodeIn_3.d.bits.corrupt
invalidate nodeIn_3.d.bits.data
invalidate nodeIn_3.d.bits.denied
invalidate nodeIn_3.d.bits.sink
invalidate nodeIn_3.d.bits.source
invalidate nodeIn_3.d.bits.size
invalidate nodeIn_3.d.bits.param
invalidate nodeIn_3.d.bits.opcode
invalidate nodeIn_3.d.valid
invalidate nodeIn_3.d.ready
invalidate nodeIn_3.c.bits.corrupt
invalidate nodeIn_3.c.bits.data
invalidate nodeIn_3.c.bits.address
invalidate nodeIn_3.c.bits.source
invalidate nodeIn_3.c.bits.size
invalidate nodeIn_3.c.bits.param
invalidate nodeIn_3.c.bits.opcode
invalidate nodeIn_3.c.valid
invalidate nodeIn_3.c.ready
invalidate nodeIn_3.b.bits.corrupt
invalidate nodeIn_3.b.bits.data
invalidate nodeIn_3.b.bits.mask
invalidate nodeIn_3.b.bits.address
invalidate nodeIn_3.b.bits.source
invalidate nodeIn_3.b.bits.size
invalidate nodeIn_3.b.bits.param
invalidate nodeIn_3.b.bits.opcode
invalidate nodeIn_3.b.valid
invalidate nodeIn_3.b.ready
invalidate nodeIn_3.a.bits.corrupt
invalidate nodeIn_3.a.bits.data
invalidate nodeIn_3.a.bits.mask
invalidate nodeIn_3.a.bits.address
invalidate nodeIn_3.a.bits.source
invalidate nodeIn_3.a.bits.size
invalidate nodeIn_3.a.bits.param
invalidate nodeIn_3.a.bits.opcode
invalidate nodeIn_3.a.valid
invalidate nodeIn_3.a.ready
inst monitor of TLMonitor_58
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.e.bits.sink, nodeIn.e.bits.sink
connect monitor.io.in.e.valid, nodeIn.e.valid
connect monitor.io.in.e.ready, nodeIn.e.ready
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.c.bits.corrupt, nodeIn.c.bits.corrupt
connect monitor.io.in.c.bits.data, nodeIn.c.bits.data
connect monitor.io.in.c.bits.address, nodeIn.c.bits.address
connect monitor.io.in.c.bits.source, nodeIn.c.bits.source
connect monitor.io.in.c.bits.size, nodeIn.c.bits.size
connect monitor.io.in.c.bits.param, nodeIn.c.bits.param
connect monitor.io.in.c.bits.opcode, nodeIn.c.bits.opcode
connect monitor.io.in.c.valid, nodeIn.c.valid
connect monitor.io.in.c.ready, nodeIn.c.ready
connect monitor.io.in.b.bits.corrupt, nodeIn.b.bits.corrupt
connect monitor.io.in.b.bits.data, nodeIn.b.bits.data
connect monitor.io.in.b.bits.mask, nodeIn.b.bits.mask
connect monitor.io.in.b.bits.address, nodeIn.b.bits.address
connect monitor.io.in.b.bits.source, nodeIn.b.bits.source
connect monitor.io.in.b.bits.size, nodeIn.b.bits.size
connect monitor.io.in.b.bits.param, nodeIn.b.bits.param
connect monitor.io.in.b.bits.opcode, nodeIn.b.bits.opcode
connect monitor.io.in.b.valid, nodeIn.b.valid
connect monitor.io.in.b.ready, nodeIn.b.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
inst monitor_1 of TLMonitor_59
connect monitor_1.clock, clock
connect monitor_1.reset, reset
connect monitor_1.io.in.e.bits.sink, nodeIn_1.e.bits.sink
connect monitor_1.io.in.e.valid, nodeIn_1.e.valid
connect monitor_1.io.in.e.ready, nodeIn_1.e.ready
connect monitor_1.io.in.d.bits.corrupt, nodeIn_1.d.bits.corrupt
connect monitor_1.io.in.d.bits.data, nodeIn_1.d.bits.data
connect monitor_1.io.in.d.bits.denied, nodeIn_1.d.bits.denied
connect monitor_1.io.in.d.bits.sink, nodeIn_1.d.bits.sink
connect monitor_1.io.in.d.bits.source, nodeIn_1.d.bits.source
connect monitor_1.io.in.d.bits.size, nodeIn_1.d.bits.size
connect monitor_1.io.in.d.bits.param, nodeIn_1.d.bits.param
connect monitor_1.io.in.d.bits.opcode, nodeIn_1.d.bits.opcode
connect monitor_1.io.in.d.valid, nodeIn_1.d.valid
connect monitor_1.io.in.d.ready, nodeIn_1.d.ready
connect monitor_1.io.in.c.bits.corrupt, nodeIn_1.c.bits.corrupt
connect monitor_1.io.in.c.bits.data, nodeIn_1.c.bits.data
connect monitor_1.io.in.c.bits.address, nodeIn_1.c.bits.address
connect monitor_1.io.in.c.bits.source, nodeIn_1.c.bits.source
connect monitor_1.io.in.c.bits.size, nodeIn_1.c.bits.size
connect monitor_1.io.in.c.bits.param, nodeIn_1.c.bits.param
connect monitor_1.io.in.c.bits.opcode, nodeIn_1.c.bits.opcode
connect monitor_1.io.in.c.valid, nodeIn_1.c.valid
connect monitor_1.io.in.c.ready, nodeIn_1.c.ready
connect monitor_1.io.in.b.bits.corrupt, nodeIn_1.b.bits.corrupt
connect monitor_1.io.in.b.bits.data, nodeIn_1.b.bits.data
connect monitor_1.io.in.b.bits.mask, nodeIn_1.b.bits.mask
connect monitor_1.io.in.b.bits.address, nodeIn_1.b.bits.address
connect monitor_1.io.in.b.bits.source, nodeIn_1.b.bits.source
connect monitor_1.io.in.b.bits.size, nodeIn_1.b.bits.size
connect monitor_1.io.in.b.bits.param, nodeIn_1.b.bits.param
connect monitor_1.io.in.b.bits.opcode, nodeIn_1.b.bits.opcode
connect monitor_1.io.in.b.valid, nodeIn_1.b.valid
connect monitor_1.io.in.b.ready, nodeIn_1.b.ready
connect monitor_1.io.in.a.bits.corrupt, nodeIn_1.a.bits.corrupt
connect monitor_1.io.in.a.bits.data, nodeIn_1.a.bits.data
connect monitor_1.io.in.a.bits.mask, nodeIn_1.a.bits.mask
connect monitor_1.io.in.a.bits.address, nodeIn_1.a.bits.address
connect monitor_1.io.in.a.bits.source, nodeIn_1.a.bits.source
connect monitor_1.io.in.a.bits.size, nodeIn_1.a.bits.size
connect monitor_1.io.in.a.bits.param, nodeIn_1.a.bits.param
connect monitor_1.io.in.a.bits.opcode, nodeIn_1.a.bits.opcode
connect monitor_1.io.in.a.valid, nodeIn_1.a.valid
connect monitor_1.io.in.a.ready, nodeIn_1.a.ready
inst monitor_2 of TLMonitor_60
connect monitor_2.clock, clock
connect monitor_2.reset, reset
connect monitor_2.io.in.e.bits.sink, nodeIn_2.e.bits.sink
connect monitor_2.io.in.e.valid, nodeIn_2.e.valid
connect monitor_2.io.in.e.ready, nodeIn_2.e.ready
connect monitor_2.io.in.d.bits.corrupt, nodeIn_2.d.bits.corrupt
connect monitor_2.io.in.d.bits.data, nodeIn_2.d.bits.data
connect monitor_2.io.in.d.bits.denied, nodeIn_2.d.bits.denied
connect monitor_2.io.in.d.bits.sink, nodeIn_2.d.bits.sink
connect monitor_2.io.in.d.bits.source, nodeIn_2.d.bits.source
connect monitor_2.io.in.d.bits.size, nodeIn_2.d.bits.size
connect monitor_2.io.in.d.bits.param, nodeIn_2.d.bits.param
connect monitor_2.io.in.d.bits.opcode, nodeIn_2.d.bits.opcode
connect monitor_2.io.in.d.valid, nodeIn_2.d.valid
connect monitor_2.io.in.d.ready, nodeIn_2.d.ready
connect monitor_2.io.in.c.bits.corrupt, nodeIn_2.c.bits.corrupt
connect monitor_2.io.in.c.bits.data, nodeIn_2.c.bits.data
connect monitor_2.io.in.c.bits.address, nodeIn_2.c.bits.address
connect monitor_2.io.in.c.bits.source, nodeIn_2.c.bits.source
connect monitor_2.io.in.c.bits.size, nodeIn_2.c.bits.size
connect monitor_2.io.in.c.bits.param, nodeIn_2.c.bits.param
connect monitor_2.io.in.c.bits.opcode, nodeIn_2.c.bits.opcode
connect monitor_2.io.in.c.valid, nodeIn_2.c.valid
connect monitor_2.io.in.c.ready, nodeIn_2.c.ready
connect monitor_2.io.in.b.bits.corrupt, nodeIn_2.b.bits.corrupt
connect monitor_2.io.in.b.bits.data, nodeIn_2.b.bits.data
connect monitor_2.io.in.b.bits.mask, nodeIn_2.b.bits.mask
connect monitor_2.io.in.b.bits.address, nodeIn_2.b.bits.address
connect monitor_2.io.in.b.bits.source, nodeIn_2.b.bits.source
connect monitor_2.io.in.b.bits.size, nodeIn_2.b.bits.size
connect monitor_2.io.in.b.bits.param, nodeIn_2.b.bits.param
connect monitor_2.io.in.b.bits.opcode, nodeIn_2.b.bits.opcode
connect monitor_2.io.in.b.valid, nodeIn_2.b.valid
connect monitor_2.io.in.b.ready, nodeIn_2.b.ready
connect monitor_2.io.in.a.bits.corrupt, nodeIn_2.a.bits.corrupt
connect monitor_2.io.in.a.bits.data, nodeIn_2.a.bits.data
connect monitor_2.io.in.a.bits.mask, nodeIn_2.a.bits.mask
connect monitor_2.io.in.a.bits.address, nodeIn_2.a.bits.address
connect monitor_2.io.in.a.bits.source, nodeIn_2.a.bits.source
connect monitor_2.io.in.a.bits.size, nodeIn_2.a.bits.size
connect monitor_2.io.in.a.bits.param, nodeIn_2.a.bits.param
connect monitor_2.io.in.a.bits.opcode, nodeIn_2.a.bits.opcode
connect monitor_2.io.in.a.valid, nodeIn_2.a.valid
connect monitor_2.io.in.a.ready, nodeIn_2.a.ready
inst monitor_3 of TLMonitor_61
connect monitor_3.clock, clock
connect monitor_3.reset, reset
connect monitor_3.io.in.e.bits.sink, nodeIn_3.e.bits.sink
connect monitor_3.io.in.e.valid, nodeIn_3.e.valid
connect monitor_3.io.in.e.ready, nodeIn_3.e.ready
connect monitor_3.io.in.d.bits.corrupt, nodeIn_3.d.bits.corrupt
connect monitor_3.io.in.d.bits.data, nodeIn_3.d.bits.data
connect monitor_3.io.in.d.bits.denied, nodeIn_3.d.bits.denied
connect monitor_3.io.in.d.bits.sink, nodeIn_3.d.bits.sink
connect monitor_3.io.in.d.bits.source, nodeIn_3.d.bits.source
connect monitor_3.io.in.d.bits.size, nodeIn_3.d.bits.size
connect monitor_3.io.in.d.bits.param, nodeIn_3.d.bits.param
connect monitor_3.io.in.d.bits.opcode, nodeIn_3.d.bits.opcode
connect monitor_3.io.in.d.valid, nodeIn_3.d.valid
connect monitor_3.io.in.d.ready, nodeIn_3.d.ready
connect monitor_3.io.in.c.bits.corrupt, nodeIn_3.c.bits.corrupt
connect monitor_3.io.in.c.bits.data, nodeIn_3.c.bits.data
connect monitor_3.io.in.c.bits.address, nodeIn_3.c.bits.address
connect monitor_3.io.in.c.bits.source, nodeIn_3.c.bits.source
connect monitor_3.io.in.c.bits.size, nodeIn_3.c.bits.size
connect monitor_3.io.in.c.bits.param, nodeIn_3.c.bits.param
connect monitor_3.io.in.c.bits.opcode, nodeIn_3.c.bits.opcode
connect monitor_3.io.in.c.valid, nodeIn_3.c.valid
connect monitor_3.io.in.c.ready, nodeIn_3.c.ready
connect monitor_3.io.in.b.bits.corrupt, nodeIn_3.b.bits.corrupt
connect monitor_3.io.in.b.bits.data, nodeIn_3.b.bits.data
connect monitor_3.io.in.b.bits.mask, nodeIn_3.b.bits.mask
connect monitor_3.io.in.b.bits.address, nodeIn_3.b.bits.address
connect monitor_3.io.in.b.bits.source, nodeIn_3.b.bits.source
connect monitor_3.io.in.b.bits.size, nodeIn_3.b.bits.size
connect monitor_3.io.in.b.bits.param, nodeIn_3.b.bits.param
connect monitor_3.io.in.b.bits.opcode, nodeIn_3.b.bits.opcode
connect monitor_3.io.in.b.valid, nodeIn_3.b.valid
connect monitor_3.io.in.b.ready, nodeIn_3.b.ready
connect monitor_3.io.in.a.bits.corrupt, nodeIn_3.a.bits.corrupt
connect monitor_3.io.in.a.bits.data, nodeIn_3.a.bits.data
connect monitor_3.io.in.a.bits.mask, nodeIn_3.a.bits.mask
connect monitor_3.io.in.a.bits.address, nodeIn_3.a.bits.address
connect monitor_3.io.in.a.bits.source, nodeIn_3.a.bits.source
connect monitor_3.io.in.a.bits.size, nodeIn_3.a.bits.size
connect monitor_3.io.in.a.bits.param, nodeIn_3.a.bits.param
connect monitor_3.io.in.a.bits.opcode, nodeIn_3.a.bits.opcode
connect monitor_3.io.in.a.valid, nodeIn_3.a.valid
connect monitor_3.io.in.a.ready, nodeIn_3.a.ready
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
wire x1_nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_nodeOut.d.bits.corrupt
invalidate x1_nodeOut.d.bits.data
invalidate x1_nodeOut.d.bits.denied
invalidate x1_nodeOut.d.bits.sink
invalidate x1_nodeOut.d.bits.source
invalidate x1_nodeOut.d.bits.size
invalidate x1_nodeOut.d.bits.param
invalidate x1_nodeOut.d.bits.opcode
invalidate x1_nodeOut.d.valid
invalidate x1_nodeOut.d.ready
invalidate x1_nodeOut.a.bits.corrupt
invalidate x1_nodeOut.a.bits.data
invalidate x1_nodeOut.a.bits.mask
invalidate x1_nodeOut.a.bits.address
invalidate x1_nodeOut.a.bits.source
invalidate x1_nodeOut.a.bits.size
invalidate x1_nodeOut.a.bits.param
invalidate x1_nodeOut.a.bits.opcode
invalidate x1_nodeOut.a.valid
invalidate x1_nodeOut.a.ready
wire x1_nodeOut_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_nodeOut_1.d.bits.corrupt
invalidate x1_nodeOut_1.d.bits.data
invalidate x1_nodeOut_1.d.bits.denied
invalidate x1_nodeOut_1.d.bits.sink
invalidate x1_nodeOut_1.d.bits.source
invalidate x1_nodeOut_1.d.bits.size
invalidate x1_nodeOut_1.d.bits.param
invalidate x1_nodeOut_1.d.bits.opcode
invalidate x1_nodeOut_1.d.valid
invalidate x1_nodeOut_1.d.ready
invalidate x1_nodeOut_1.a.bits.corrupt
invalidate x1_nodeOut_1.a.bits.data
invalidate x1_nodeOut_1.a.bits.mask
invalidate x1_nodeOut_1.a.bits.address
invalidate x1_nodeOut_1.a.bits.source
invalidate x1_nodeOut_1.a.bits.size
invalidate x1_nodeOut_1.a.bits.param
invalidate x1_nodeOut_1.a.bits.opcode
invalidate x1_nodeOut_1.a.valid
invalidate x1_nodeOut_1.a.ready
wire x1_nodeOut_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_nodeOut_2.d.bits.corrupt
invalidate x1_nodeOut_2.d.bits.data
invalidate x1_nodeOut_2.d.bits.denied
invalidate x1_nodeOut_2.d.bits.sink
invalidate x1_nodeOut_2.d.bits.source
invalidate x1_nodeOut_2.d.bits.size
invalidate x1_nodeOut_2.d.bits.param
invalidate x1_nodeOut_2.d.bits.opcode
invalidate x1_nodeOut_2.d.valid
invalidate x1_nodeOut_2.d.ready
invalidate x1_nodeOut_2.a.bits.corrupt
invalidate x1_nodeOut_2.a.bits.data
invalidate x1_nodeOut_2.a.bits.mask
invalidate x1_nodeOut_2.a.bits.address
invalidate x1_nodeOut_2.a.bits.source
invalidate x1_nodeOut_2.a.bits.size
invalidate x1_nodeOut_2.a.bits.param
invalidate x1_nodeOut_2.a.bits.opcode
invalidate x1_nodeOut_2.a.valid
invalidate x1_nodeOut_2.a.ready
connect auto.out_0, nodeOut
connect auto.out_1, x1_nodeOut
connect auto.out_2, x1_nodeOut_1
connect auto.out_3, x1_nodeOut_2
connect nodeIn, auto.in_0
connect nodeIn_1, auto.in_1
connect nodeIn_2, auto.in_2
connect nodeIn_3, auto.in_3
wire a_a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
wire a_d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
node _isPut_T = eq(nodeIn.a.bits.opcode, UInt<1>(0h0))
node _isPut_T_1 = eq(nodeIn.a.bits.opcode, UInt<1>(0h1))
node isPut = or(_isPut_T, _isPut_T_1)
node _toD_T = eq(nodeIn.a.bits.opcode, UInt<3>(0h6))
node _toD_T_1 = eq(nodeIn.a.bits.param, UInt<2>(0h2))
node _toD_T_2 = and(_toD_T, _toD_T_1)
node _toD_T_3 = eq(nodeIn.a.bits.opcode, UInt<3>(0h7))
node toD = or(_toD_T_2, _toD_T_3)
node _nodeIn_a_ready_T = mux(toD, a_d.ready, a_a.ready)
connect nodeIn.a.ready, _nodeIn_a_ready_T
node _a_a_valid_T = eq(toD, UInt<1>(0h0))
node _a_a_valid_T_1 = and(nodeIn.a.valid, _a_a_valid_T)
connect a_a.valid, _a_a_valid_T_1
connect a_a.bits, nodeIn.a.bits
node _a_a_bits_source_T = shl(nodeIn.a.bits.source, 1)
node _a_a_bits_source_T_1 = mux(isPut, UInt<1>(0h1), UInt<1>(0h0))
node _a_a_bits_source_T_2 = or(_a_a_bits_source_T, _a_a_bits_source_T_1)
connect a_a.bits.source, _a_a_bits_source_T_2
node _T = eq(nodeIn.a.bits.opcode, UInt<3>(0h6))
node _T_1 = eq(nodeIn.a.bits.opcode, UInt<3>(0h7))
node _T_2 = or(_T, _T_1)
when _T_2 :
connect a_a.bits.opcode, UInt<3>(0h4)
connect a_a.bits.param, UInt<1>(0h0)
node _a_a_bits_source_T_3 = shl(nodeIn.a.bits.source, 1)
node _a_a_bits_source_T_4 = or(_a_a_bits_source_T_3, UInt<1>(0h1))
connect a_a.bits.source, _a_a_bits_source_T_4
node _a_d_valid_T = and(nodeIn.a.valid, toD)
connect a_d.valid, _a_d_valid_T
wire a_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
connect a_d_bits_d.opcode, UInt<3>(0h4)
connect a_d_bits_d.param, UInt<2>(0h0)
connect a_d_bits_d.size, nodeIn.a.bits.size
connect a_d_bits_d.source, nodeIn.a.bits.source
connect a_d_bits_d.sink, UInt<1>(0h0)
connect a_d_bits_d.denied, UInt<1>(0h0)
invalidate a_d_bits_d.data
connect a_d_bits_d.corrupt, UInt<1>(0h0)
connect a_d.bits.corrupt, a_d_bits_d.corrupt
connect a_d.bits.data, a_d_bits_d.data
connect a_d.bits.denied, a_d_bits_d.denied
connect a_d.bits.sink, a_d_bits_d.sink
connect a_d.bits.source, a_d_bits_d.source
connect a_d.bits.size, a_d_bits_d.size
connect a_d.bits.param, a_d_bits_d.param
connect a_d.bits.opcode, a_d_bits_d.opcode
wire c_a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
node _c_a_valid_T = eq(nodeIn.c.bits.opcode, UInt<3>(0h7))
node _c_a_valid_T_1 = and(nodeIn.c.valid, _c_a_valid_T)
connect c_a.valid, _c_a_valid_T_1
node _c_a_bits_T = shl(nodeIn.c.bits.source, 1)
node _c_a_bits_legal_T = leq(UInt<1>(0h0), nodeIn.c.bits.size)
node _c_a_bits_legal_T_1 = leq(nodeIn.c.bits.size, UInt<3>(0h6))
node _c_a_bits_legal_T_2 = and(_c_a_bits_legal_T, _c_a_bits_legal_T_1)
node _c_a_bits_legal_T_3 = or(UInt<1>(0h0), _c_a_bits_legal_T_2)
node _c_a_bits_legal_T_4 = xor(nodeIn.c.bits.address, UInt<1>(0h0))
node _c_a_bits_legal_T_5 = cvt(_c_a_bits_legal_T_4)
node _c_a_bits_legal_T_6 = and(_c_a_bits_legal_T_5, asSInt(UInt<1>(0h0)))
node _c_a_bits_legal_T_7 = asSInt(_c_a_bits_legal_T_6)
node _c_a_bits_legal_T_8 = eq(_c_a_bits_legal_T_7, asSInt(UInt<1>(0h0)))
node _c_a_bits_legal_T_9 = and(_c_a_bits_legal_T_3, _c_a_bits_legal_T_8)
node c_a_bits_legal = or(UInt<1>(0h0), _c_a_bits_legal_T_9)
wire c_a_bits_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect c_a_bits_a.opcode, UInt<1>(0h0)
connect c_a_bits_a.param, UInt<1>(0h0)
connect c_a_bits_a.size, nodeIn.c.bits.size
connect c_a_bits_a.source, _c_a_bits_T
connect c_a_bits_a.address, nodeIn.c.bits.address
node _c_a_bits_a_mask_sizeOH_T = or(nodeIn.c.bits.size, UInt<3>(0h0))
node c_a_bits_a_mask_sizeOH_shiftAmount = bits(_c_a_bits_a_mask_sizeOH_T, 1, 0)
node _c_a_bits_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), c_a_bits_a_mask_sizeOH_shiftAmount)
node _c_a_bits_a_mask_sizeOH_T_2 = bits(_c_a_bits_a_mask_sizeOH_T_1, 2, 0)
node c_a_bits_a_mask_sizeOH = or(_c_a_bits_a_mask_sizeOH_T_2, UInt<1>(0h1))
node c_a_bits_a_mask_sub_sub_sub_0_1 = geq(nodeIn.c.bits.size, UInt<2>(0h3))
node c_a_bits_a_mask_sub_sub_size = bits(c_a_bits_a_mask_sizeOH, 2, 2)
node c_a_bits_a_mask_sub_sub_bit = bits(nodeIn.c.bits.address, 2, 2)
node c_a_bits_a_mask_sub_sub_nbit = eq(c_a_bits_a_mask_sub_sub_bit, UInt<1>(0h0))
node c_a_bits_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), c_a_bits_a_mask_sub_sub_nbit)
node _c_a_bits_a_mask_sub_sub_acc_T = and(c_a_bits_a_mask_sub_sub_size, c_a_bits_a_mask_sub_sub_0_2)
node c_a_bits_a_mask_sub_sub_0_1 = or(c_a_bits_a_mask_sub_sub_sub_0_1, _c_a_bits_a_mask_sub_sub_acc_T)
node c_a_bits_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), c_a_bits_a_mask_sub_sub_bit)
node _c_a_bits_a_mask_sub_sub_acc_T_1 = and(c_a_bits_a_mask_sub_sub_size, c_a_bits_a_mask_sub_sub_1_2)
node c_a_bits_a_mask_sub_sub_1_1 = or(c_a_bits_a_mask_sub_sub_sub_0_1, _c_a_bits_a_mask_sub_sub_acc_T_1)
node c_a_bits_a_mask_sub_size = bits(c_a_bits_a_mask_sizeOH, 1, 1)
node c_a_bits_a_mask_sub_bit = bits(nodeIn.c.bits.address, 1, 1)
node c_a_bits_a_mask_sub_nbit = eq(c_a_bits_a_mask_sub_bit, UInt<1>(0h0))
node c_a_bits_a_mask_sub_0_2 = and(c_a_bits_a_mask_sub_sub_0_2, c_a_bits_a_mask_sub_nbit)
node _c_a_bits_a_mask_sub_acc_T = and(c_a_bits_a_mask_sub_size, c_a_bits_a_mask_sub_0_2)
node c_a_bits_a_mask_sub_0_1 = or(c_a_bits_a_mask_sub_sub_0_1, _c_a_bits_a_mask_sub_acc_T)
node c_a_bits_a_mask_sub_1_2 = and(c_a_bits_a_mask_sub_sub_0_2, c_a_bits_a_mask_sub_bit)
node _c_a_bits_a_mask_sub_acc_T_1 = and(c_a_bits_a_mask_sub_size, c_a_bits_a_mask_sub_1_2)
node c_a_bits_a_mask_sub_1_1 = or(c_a_bits_a_mask_sub_sub_0_1, _c_a_bits_a_mask_sub_acc_T_1)
node c_a_bits_a_mask_sub_2_2 = and(c_a_bits_a_mask_sub_sub_1_2, c_a_bits_a_mask_sub_nbit)
node _c_a_bits_a_mask_sub_acc_T_2 = and(c_a_bits_a_mask_sub_size, c_a_bits_a_mask_sub_2_2)
node c_a_bits_a_mask_sub_2_1 = or(c_a_bits_a_mask_sub_sub_1_1, _c_a_bits_a_mask_sub_acc_T_2)
node c_a_bits_a_mask_sub_3_2 = and(c_a_bits_a_mask_sub_sub_1_2, c_a_bits_a_mask_sub_bit)
node _c_a_bits_a_mask_sub_acc_T_3 = and(c_a_bits_a_mask_sub_size, c_a_bits_a_mask_sub_3_2)
node c_a_bits_a_mask_sub_3_1 = or(c_a_bits_a_mask_sub_sub_1_1, _c_a_bits_a_mask_sub_acc_T_3)
node c_a_bits_a_mask_size = bits(c_a_bits_a_mask_sizeOH, 0, 0)
node c_a_bits_a_mask_bit = bits(nodeIn.c.bits.address, 0, 0)
node c_a_bits_a_mask_nbit = eq(c_a_bits_a_mask_bit, UInt<1>(0h0))
node c_a_bits_a_mask_eq = and(c_a_bits_a_mask_sub_0_2, c_a_bits_a_mask_nbit)
node _c_a_bits_a_mask_acc_T = and(c_a_bits_a_mask_size, c_a_bits_a_mask_eq)
node c_a_bits_a_mask_acc = or(c_a_bits_a_mask_sub_0_1, _c_a_bits_a_mask_acc_T)
node c_a_bits_a_mask_eq_1 = and(c_a_bits_a_mask_sub_0_2, c_a_bits_a_mask_bit)
node _c_a_bits_a_mask_acc_T_1 = and(c_a_bits_a_mask_size, c_a_bits_a_mask_eq_1)
node c_a_bits_a_mask_acc_1 = or(c_a_bits_a_mask_sub_0_1, _c_a_bits_a_mask_acc_T_1)
node c_a_bits_a_mask_eq_2 = and(c_a_bits_a_mask_sub_1_2, c_a_bits_a_mask_nbit)
node _c_a_bits_a_mask_acc_T_2 = and(c_a_bits_a_mask_size, c_a_bits_a_mask_eq_2)
node c_a_bits_a_mask_acc_2 = or(c_a_bits_a_mask_sub_1_1, _c_a_bits_a_mask_acc_T_2)
node c_a_bits_a_mask_eq_3 = and(c_a_bits_a_mask_sub_1_2, c_a_bits_a_mask_bit)
node _c_a_bits_a_mask_acc_T_3 = and(c_a_bits_a_mask_size, c_a_bits_a_mask_eq_3)
node c_a_bits_a_mask_acc_3 = or(c_a_bits_a_mask_sub_1_1, _c_a_bits_a_mask_acc_T_3)
node c_a_bits_a_mask_eq_4 = and(c_a_bits_a_mask_sub_2_2, c_a_bits_a_mask_nbit)
node _c_a_bits_a_mask_acc_T_4 = and(c_a_bits_a_mask_size, c_a_bits_a_mask_eq_4)
node c_a_bits_a_mask_acc_4 = or(c_a_bits_a_mask_sub_2_1, _c_a_bits_a_mask_acc_T_4)
node c_a_bits_a_mask_eq_5 = and(c_a_bits_a_mask_sub_2_2, c_a_bits_a_mask_bit)
node _c_a_bits_a_mask_acc_T_5 = and(c_a_bits_a_mask_size, c_a_bits_a_mask_eq_5)
node c_a_bits_a_mask_acc_5 = or(c_a_bits_a_mask_sub_2_1, _c_a_bits_a_mask_acc_T_5)
node c_a_bits_a_mask_eq_6 = and(c_a_bits_a_mask_sub_3_2, c_a_bits_a_mask_nbit)
node _c_a_bits_a_mask_acc_T_6 = and(c_a_bits_a_mask_size, c_a_bits_a_mask_eq_6)
node c_a_bits_a_mask_acc_6 = or(c_a_bits_a_mask_sub_3_1, _c_a_bits_a_mask_acc_T_6)
node c_a_bits_a_mask_eq_7 = and(c_a_bits_a_mask_sub_3_2, c_a_bits_a_mask_bit)
node _c_a_bits_a_mask_acc_T_7 = and(c_a_bits_a_mask_size, c_a_bits_a_mask_eq_7)
node c_a_bits_a_mask_acc_7 = or(c_a_bits_a_mask_sub_3_1, _c_a_bits_a_mask_acc_T_7)
node c_a_bits_a_mask_lo_lo = cat(c_a_bits_a_mask_acc_1, c_a_bits_a_mask_acc)
node c_a_bits_a_mask_lo_hi = cat(c_a_bits_a_mask_acc_3, c_a_bits_a_mask_acc_2)
node c_a_bits_a_mask_lo = cat(c_a_bits_a_mask_lo_hi, c_a_bits_a_mask_lo_lo)
node c_a_bits_a_mask_hi_lo = cat(c_a_bits_a_mask_acc_5, c_a_bits_a_mask_acc_4)
node c_a_bits_a_mask_hi_hi = cat(c_a_bits_a_mask_acc_7, c_a_bits_a_mask_acc_6)
node c_a_bits_a_mask_hi = cat(c_a_bits_a_mask_hi_hi, c_a_bits_a_mask_hi_lo)
node _c_a_bits_a_mask_T = cat(c_a_bits_a_mask_hi, c_a_bits_a_mask_lo)
connect c_a_bits_a.mask, _c_a_bits_a_mask_T
connect c_a_bits_a.data, nodeIn.c.bits.data
connect c_a_bits_a.corrupt, nodeIn.c.bits.corrupt
connect c_a.bits, c_a_bits_a
wire c_d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
node _c_d_valid_T = eq(nodeIn.c.bits.opcode, UInt<3>(0h6))
node _c_d_valid_T_1 = and(nodeIn.c.valid, _c_d_valid_T)
connect c_d.valid, _c_d_valid_T_1
wire c_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
connect c_d_bits_d.opcode, UInt<3>(0h6)
connect c_d_bits_d.param, UInt<1>(0h0)
connect c_d_bits_d.size, nodeIn.c.bits.size
connect c_d_bits_d.source, nodeIn.c.bits.source
connect c_d_bits_d.sink, UInt<1>(0h0)
connect c_d_bits_d.denied, UInt<1>(0h0)
invalidate c_d_bits_d.data
connect c_d_bits_d.corrupt, UInt<1>(0h0)
connect c_d.bits.corrupt, c_d_bits_d.corrupt
connect c_d.bits.data, c_d_bits_d.data
connect c_d.bits.denied, c_d_bits_d.denied
connect c_d.bits.sink, c_d_bits_d.sink
connect c_d.bits.source, c_d_bits_d.source
connect c_d.bits.size, c_d_bits_d.size
connect c_d.bits.param, c_d_bits_d.param
connect c_d.bits.opcode, c_d_bits_d.opcode
node _T_3 = eq(nodeIn.c.valid, UInt<1>(0h0))
node _T_4 = eq(nodeIn.c.bits.opcode, UInt<3>(0h6))
node _T_5 = or(_T_3, _T_4)
node _T_6 = eq(nodeIn.c.bits.opcode, UInt<3>(0h7))
node _T_7 = or(_T_5, _T_6)
node _T_8 = asUInt(reset)
node _T_9 = eq(_T_8, UInt<1>(0h0))
when _T_9 :
node _T_10 = eq(_T_7, UInt<1>(0h0))
when _T_10 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at CacheCork.scala:116 assert (!in.c.valid || in.c.bits.opcode === Release || in.c.bits.opcode === ReleaseData)\n") : printf
assert(clock, _T_7, UInt<1>(0h1), "") : assert
node _nodeIn_c_ready_T = eq(nodeIn.c.bits.opcode, UInt<3>(0h6))
node _nodeIn_c_ready_T_1 = mux(_nodeIn_c_ready_T, c_d.ready, c_a.ready)
connect nodeIn.c.ready, _nodeIn_c_ready_T_1
connect nodeIn.e.ready, UInt<1>(0h1)
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<5>(0h0)
connect _WIRE.bits.size, UInt<3>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.ready, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.mask, UInt<8>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<5>(0h0)
connect _WIRE_2.bits.size, UInt<3>(0h0)
connect _WIRE_2.bits.param, UInt<2>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_11 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at CacheCork.scala:124 assert (!out.b.valid)\n") : printf_1
assert(clock, _T_11, UInt<1>(0h1), "") : assert_1
inst pool of IDPool
connect pool.clock, clock
connect pool.reset, reset
node _pool_io_free_valid_T = and(nodeIn.e.ready, nodeIn.e.valid)
connect pool.io.free.valid, _pool_io_free_valid_T
connect pool.io.free.bits, nodeIn.e.bits.sink
wire in_d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
node _d_first_T = and(in_d.ready, in_d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), in_d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(in_d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
node _d_grant_T = eq(in_d.bits.opcode, UInt<3>(0h5))
node _d_grant_T_1 = eq(in_d.bits.opcode, UInt<3>(0h4))
node d_grant = or(_d_grant_T, _d_grant_T_1)
node _pool_io_alloc_ready_T = and(nodeIn.d.ready, nodeIn.d.valid)
node _pool_io_alloc_ready_T_1 = and(_pool_io_alloc_ready_T, d_first)
node _pool_io_alloc_ready_T_2 = and(_pool_io_alloc_ready_T_1, d_grant)
connect pool.io.alloc.ready, _pool_io_alloc_ready_T_2
node _nodeIn_d_valid_T = eq(d_first, UInt<1>(0h0))
node _nodeIn_d_valid_T_1 = or(pool.io.alloc.valid, _nodeIn_d_valid_T)
node _nodeIn_d_valid_T_2 = eq(d_grant, UInt<1>(0h0))
node _nodeIn_d_valid_T_3 = or(_nodeIn_d_valid_T_1, _nodeIn_d_valid_T_2)
node _nodeIn_d_valid_T_4 = and(in_d.valid, _nodeIn_d_valid_T_3)
connect nodeIn.d.valid, _nodeIn_d_valid_T_4
node _in_d_ready_T = eq(d_first, UInt<1>(0h0))
node _in_d_ready_T_1 = or(pool.io.alloc.valid, _in_d_ready_T)
node _in_d_ready_T_2 = eq(d_grant, UInt<1>(0h0))
node _in_d_ready_T_3 = or(_in_d_ready_T_1, _in_d_ready_T_2)
node _in_d_ready_T_4 = and(nodeIn.d.ready, _in_d_ready_T_3)
connect in_d.ready, _in_d_ready_T_4
connect nodeIn.d.bits.corrupt, in_d.bits.corrupt
connect nodeIn.d.bits.data, in_d.bits.data
connect nodeIn.d.bits.denied, in_d.bits.denied
connect nodeIn.d.bits.sink, in_d.bits.sink
connect nodeIn.d.bits.source, in_d.bits.source
connect nodeIn.d.bits.size, in_d.bits.size
connect nodeIn.d.bits.param, in_d.bits.param
connect nodeIn.d.bits.opcode, in_d.bits.opcode
reg nodeIn_d_bits_sink_r : UInt<3>, clock
when d_first :
connect nodeIn_d_bits_sink_r, pool.io.alloc.bits
node _nodeIn_d_bits_sink_T = mux(d_first, pool.io.alloc.bits, nodeIn_d_bits_sink_r)
connect nodeIn.d.bits.sink, _nodeIn_d_bits_sink_T
wire d_d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect d_d, nodeOut.d
node _d_d_bits_source_T = shr(nodeOut.d.bits.source, 1)
connect d_d.bits.source, _d_d_bits_source_T
reg wSourceVec : UInt<1>[10], clock
node _aWOk_T = xor(nodeIn.a.bits.address, UInt<1>(0h0))
node _aWOk_T_1 = cvt(_aWOk_T)
node _aWOk_T_2 = and(_aWOk_T_1, asSInt(UInt<1>(0h0)))
node _aWOk_T_3 = asSInt(_aWOk_T_2)
node _aWOk_T_4 = eq(_aWOk_T_3, asSInt(UInt<1>(0h0)))
node _bypass_T = and(UInt<1>(0h0), nodeIn.a.valid)
node _bypass_T_1 = eq(nodeIn.a.bits.source, d_d.bits.source)
node bypass = and(_bypass_T, _bypass_T_1)
node _dWHeld_T = mux(bypass, UInt<1>(0h1), wSourceVec[d_d.bits.source])
reg dWHeld_r : UInt<1>, clock
when d_first :
connect dWHeld_r, _dWHeld_T
node dWHeld = mux(d_first, _dWHeld_T, dWHeld_r)
node _T_15 = and(nodeIn.a.ready, nodeIn.a.valid)
when _T_15 :
connect wSourceVec[nodeIn.a.bits.source], UInt<1>(0h1)
node _T_16 = eq(nodeOut.d.bits.opcode, UInt<1>(0h1))
node _T_17 = bits(nodeOut.d.bits.source, 0, 0)
node _T_18 = and(_T_16, _T_17)
when _T_18 :
connect d_d.bits.opcode, UInt<3>(0h5)
node _d_d_bits_param_T = mux(dWHeld, UInt<2>(0h0), UInt<2>(0h1))
connect d_d.bits.param, _d_d_bits_param_T
node _T_19 = eq(nodeOut.d.bits.opcode, UInt<1>(0h0))
node _T_20 = bits(nodeOut.d.bits.source, 0, 0)
node _T_21 = eq(_T_20, UInt<1>(0h0))
node _T_22 = and(_T_19, _T_21)
when _T_22 :
connect d_d.bits.opcode, UInt<3>(0h6)
node _decode_T = dshl(UInt<6>(0h3f), c_a.bits.size)
node _decode_T_1 = bits(_decode_T, 5, 0)
node _decode_T_2 = not(_decode_T_1)
node decode = shr(_decode_T_2, 3)
node _opdata_T = bits(c_a.bits.opcode, 2, 2)
node opdata = eq(_opdata_T, UInt<1>(0h0))
node _T_23 = mux(opdata, decode, UInt<1>(0h0))
node _decode_T_3 = dshl(UInt<6>(0h3f), a_a.bits.size)
node _decode_T_4 = bits(_decode_T_3, 5, 0)
node _decode_T_5 = not(_decode_T_4)
node decode_1 = shr(_decode_T_5, 3)
node _opdata_T_1 = bits(a_a.bits.opcode, 2, 2)
node opdata_1 = eq(_opdata_T_1, UInt<1>(0h0))
node _T_24 = mux(opdata_1, decode_1, UInt<1>(0h0))
regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0)
node idle = eq(beatsLeft, UInt<1>(0h0))
node latch = and(idle, nodeOut.a.ready)
node _readys_T = cat(a_a.valid, c_a.valid)
node _readys_T_1 = shl(_readys_T, 1)
node _readys_T_2 = bits(_readys_T_1, 1, 0)
node _readys_T_3 = or(_readys_T, _readys_T_2)
node _readys_T_4 = bits(_readys_T_3, 1, 0)
node _readys_T_5 = shl(_readys_T_4, 1)
node _readys_T_6 = bits(_readys_T_5, 1, 0)
node _readys_T_7 = not(_readys_T_6)
node _readys_T_8 = bits(_readys_T_7, 0, 0)
node _readys_T_9 = bits(_readys_T_7, 1, 1)
wire readys : UInt<1>[2]
connect readys[0], _readys_T_8
connect readys[1], _readys_T_9
node _winner_T = and(readys[0], c_a.valid)
node _winner_T_1 = and(readys[1], a_a.valid)
wire winner : UInt<1>[2]
connect winner[0], _winner_T
connect winner[1], _winner_T_1
node prefixOR_1 = or(UInt<1>(0h0), winner[0])
node _prefixOR_T = or(prefixOR_1, winner[1])
node _T_25 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_26 = eq(winner[0], UInt<1>(0h0))
node _T_27 = or(_T_25, _T_26)
node _T_28 = eq(prefixOR_1, UInt<1>(0h0))
node _T_29 = eq(winner[1], UInt<1>(0h0))
node _T_30 = or(_T_28, _T_29)
node _T_31 = and(_T_27, _T_30)
node _T_32 = asUInt(reset)
node _T_33 = eq(_T_32, UInt<1>(0h0))
when _T_33 :
node _T_34 = eq(_T_31, UInt<1>(0h0))
when _T_34 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_2
assert(clock, _T_31, UInt<1>(0h1), "") : assert_2
node _T_35 = or(c_a.valid, a_a.valid)
node _T_36 = eq(_T_35, UInt<1>(0h0))
node _T_37 = or(winner[0], winner[1])
node _T_38 = or(_T_36, _T_37)
node _T_39 = asUInt(reset)
node _T_40 = eq(_T_39, UInt<1>(0h0))
when _T_40 :
node _T_41 = eq(_T_38, UInt<1>(0h0))
when _T_41 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_3
assert(clock, _T_38, UInt<1>(0h1), "") : assert_3
node maskedBeats_0 = mux(winner[0], _T_23, UInt<1>(0h0))
node maskedBeats_1 = mux(winner[1], _T_24, UInt<1>(0h0))
node initBeats = or(maskedBeats_0, maskedBeats_1)
node _beatsLeft_T = and(nodeOut.a.ready, nodeOut.a.valid)
node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T)
node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1)
node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2)
connect beatsLeft, _beatsLeft_T_3
wire _state_WIRE : UInt<1>[2]
connect _state_WIRE[0], UInt<1>(0h0)
connect _state_WIRE[1], UInt<1>(0h0)
regreset state : UInt<1>[2], clock, reset, _state_WIRE
node muxState = mux(idle, winner, state)
connect state, muxState
node allowed = mux(idle, readys, state)
node _c_a_ready_T = and(nodeOut.a.ready, allowed[0])
connect c_a.ready, _c_a_ready_T
node _a_a_ready_T = and(nodeOut.a.ready, allowed[1])
connect a_a.ready, _a_a_ready_T
node _nodeOut_a_valid_T = or(c_a.valid, a_a.valid)
node _nodeOut_a_valid_T_1 = mux(state[0], c_a.valid, UInt<1>(0h0))
node _nodeOut_a_valid_T_2 = mux(state[1], a_a.valid, UInt<1>(0h0))
node _nodeOut_a_valid_T_3 = or(_nodeOut_a_valid_T_1, _nodeOut_a_valid_T_2)
wire _nodeOut_a_valid_WIRE : UInt<1>
connect _nodeOut_a_valid_WIRE, _nodeOut_a_valid_T_3
node _nodeOut_a_valid_T_4 = mux(idle, _nodeOut_a_valid_T, _nodeOut_a_valid_WIRE)
connect nodeOut.a.valid, _nodeOut_a_valid_T_4
wire _nodeOut_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
node _nodeOut_a_bits_T = mux(muxState[0], c_a.bits.corrupt, UInt<1>(0h0))
node _nodeOut_a_bits_T_1 = mux(muxState[1], a_a.bits.corrupt, UInt<1>(0h0))
node _nodeOut_a_bits_T_2 = or(_nodeOut_a_bits_T, _nodeOut_a_bits_T_1)
wire _nodeOut_a_bits_WIRE_1 : UInt<1>
connect _nodeOut_a_bits_WIRE_1, _nodeOut_a_bits_T_2
connect _nodeOut_a_bits_WIRE.corrupt, _nodeOut_a_bits_WIRE_1
node _nodeOut_a_bits_T_3 = mux(muxState[0], c_a.bits.data, UInt<1>(0h0))
node _nodeOut_a_bits_T_4 = mux(muxState[1], a_a.bits.data, UInt<1>(0h0))
node _nodeOut_a_bits_T_5 = or(_nodeOut_a_bits_T_3, _nodeOut_a_bits_T_4)
wire _nodeOut_a_bits_WIRE_2 : UInt<64>
connect _nodeOut_a_bits_WIRE_2, _nodeOut_a_bits_T_5
connect _nodeOut_a_bits_WIRE.data, _nodeOut_a_bits_WIRE_2
node _nodeOut_a_bits_T_6 = mux(muxState[0], c_a.bits.mask, UInt<1>(0h0))
node _nodeOut_a_bits_T_7 = mux(muxState[1], a_a.bits.mask, UInt<1>(0h0))
node _nodeOut_a_bits_T_8 = or(_nodeOut_a_bits_T_6, _nodeOut_a_bits_T_7)
wire _nodeOut_a_bits_WIRE_3 : UInt<8>
connect _nodeOut_a_bits_WIRE_3, _nodeOut_a_bits_T_8
connect _nodeOut_a_bits_WIRE.mask, _nodeOut_a_bits_WIRE_3
wire _nodeOut_a_bits_WIRE_4 : { }
connect _nodeOut_a_bits_WIRE.echo, _nodeOut_a_bits_WIRE_4
wire _nodeOut_a_bits_WIRE_5 : { }
connect _nodeOut_a_bits_WIRE.user, _nodeOut_a_bits_WIRE_5
node _nodeOut_a_bits_T_9 = mux(muxState[0], c_a.bits.address, UInt<1>(0h0))
node _nodeOut_a_bits_T_10 = mux(muxState[1], a_a.bits.address, UInt<1>(0h0))
node _nodeOut_a_bits_T_11 = or(_nodeOut_a_bits_T_9, _nodeOut_a_bits_T_10)
wire _nodeOut_a_bits_WIRE_6 : UInt<32>
connect _nodeOut_a_bits_WIRE_6, _nodeOut_a_bits_T_11
connect _nodeOut_a_bits_WIRE.address, _nodeOut_a_bits_WIRE_6
node _nodeOut_a_bits_T_12 = mux(muxState[0], c_a.bits.source, UInt<1>(0h0))
node _nodeOut_a_bits_T_13 = mux(muxState[1], a_a.bits.source, UInt<1>(0h0))
node _nodeOut_a_bits_T_14 = or(_nodeOut_a_bits_T_12, _nodeOut_a_bits_T_13)
wire _nodeOut_a_bits_WIRE_7 : UInt<5>
connect _nodeOut_a_bits_WIRE_7, _nodeOut_a_bits_T_14
connect _nodeOut_a_bits_WIRE.source, _nodeOut_a_bits_WIRE_7
node _nodeOut_a_bits_T_15 = mux(muxState[0], c_a.bits.size, UInt<1>(0h0))
node _nodeOut_a_bits_T_16 = mux(muxState[1], a_a.bits.size, UInt<1>(0h0))
node _nodeOut_a_bits_T_17 = or(_nodeOut_a_bits_T_15, _nodeOut_a_bits_T_16)
wire _nodeOut_a_bits_WIRE_8 : UInt<3>
connect _nodeOut_a_bits_WIRE_8, _nodeOut_a_bits_T_17
connect _nodeOut_a_bits_WIRE.size, _nodeOut_a_bits_WIRE_8
node _nodeOut_a_bits_T_18 = mux(muxState[0], c_a.bits.param, UInt<1>(0h0))
node _nodeOut_a_bits_T_19 = mux(muxState[1], a_a.bits.param, UInt<1>(0h0))
node _nodeOut_a_bits_T_20 = or(_nodeOut_a_bits_T_18, _nodeOut_a_bits_T_19)
wire _nodeOut_a_bits_WIRE_9 : UInt<3>
connect _nodeOut_a_bits_WIRE_9, _nodeOut_a_bits_T_20
connect _nodeOut_a_bits_WIRE.param, _nodeOut_a_bits_WIRE_9
node _nodeOut_a_bits_T_21 = mux(muxState[0], c_a.bits.opcode, UInt<1>(0h0))
node _nodeOut_a_bits_T_22 = mux(muxState[1], a_a.bits.opcode, UInt<1>(0h0))
node _nodeOut_a_bits_T_23 = or(_nodeOut_a_bits_T_21, _nodeOut_a_bits_T_22)
wire _nodeOut_a_bits_WIRE_10 : UInt<3>
connect _nodeOut_a_bits_WIRE_10, _nodeOut_a_bits_T_23
connect _nodeOut_a_bits_WIRE.opcode, _nodeOut_a_bits_WIRE_10
connect nodeOut.a.bits.corrupt, _nodeOut_a_bits_WIRE.corrupt
connect nodeOut.a.bits.data, _nodeOut_a_bits_WIRE.data
connect nodeOut.a.bits.mask, _nodeOut_a_bits_WIRE.mask
connect nodeOut.a.bits.address, _nodeOut_a_bits_WIRE.address
connect nodeOut.a.bits.source, _nodeOut_a_bits_WIRE.source
connect nodeOut.a.bits.size, _nodeOut_a_bits_WIRE.size
connect nodeOut.a.bits.param, _nodeOut_a_bits_WIRE.param
connect nodeOut.a.bits.opcode, _nodeOut_a_bits_WIRE.opcode
node _decode_T_6 = dshl(UInt<6>(0h3f), d_d.bits.size)
node _decode_T_7 = bits(_decode_T_6, 5, 0)
node _decode_T_8 = not(_decode_T_7)
node decode_2 = shr(_decode_T_8, 3)
node opdata_2 = bits(d_d.bits.opcode, 0, 0)
node _T_42 = mux(opdata_2, decode_2, UInt<1>(0h0))
inst q of Queue2_TLBundleD_a32d64s4k3z3c_4
connect q.clock, clock
connect q.reset, reset
connect q.io.enq.valid, c_d.valid
connect q.io.enq.bits.corrupt, c_d.bits.corrupt
connect q.io.enq.bits.data, c_d.bits.data
connect q.io.enq.bits.denied, c_d.bits.denied
connect q.io.enq.bits.sink, c_d.bits.sink
connect q.io.enq.bits.source, c_d.bits.source
connect q.io.enq.bits.size, c_d.bits.size
connect q.io.enq.bits.param, c_d.bits.param
connect q.io.enq.bits.opcode, c_d.bits.opcode
connect c_d.ready, q.io.enq.ready
inst q_1 of Queue2_TLBundleD_a32d64s4k3z3c_5
connect q_1.clock, clock
connect q_1.reset, reset
connect q_1.io.enq.valid, a_d.valid
connect q_1.io.enq.bits.corrupt, a_d.bits.corrupt
connect q_1.io.enq.bits.data, a_d.bits.data
connect q_1.io.enq.bits.denied, a_d.bits.denied
connect q_1.io.enq.bits.sink, a_d.bits.sink
connect q_1.io.enq.bits.source, a_d.bits.source
connect q_1.io.enq.bits.size, a_d.bits.size
connect q_1.io.enq.bits.param, a_d.bits.param
connect q_1.io.enq.bits.opcode, a_d.bits.opcode
connect a_d.ready, q_1.io.enq.ready
regreset beatsLeft_1 : UInt, clock, reset, UInt<1>(0h0)
node idle_1 = eq(beatsLeft_1, UInt<1>(0h0))
node latch_1 = and(idle_1, in_d.ready)
node readys_hi = cat(q_1.io.deq.valid, q.io.deq.valid)
node _readys_T_10 = cat(readys_hi, d_d.valid)
node _readys_T_11 = shl(_readys_T_10, 1)
node _readys_T_12 = bits(_readys_T_11, 2, 0)
node _readys_T_13 = or(_readys_T_10, _readys_T_12)
node _readys_T_14 = shl(_readys_T_13, 2)
node _readys_T_15 = bits(_readys_T_14, 2, 0)
node _readys_T_16 = or(_readys_T_13, _readys_T_15)
node _readys_T_17 = bits(_readys_T_16, 2, 0)
node _readys_T_18 = shl(_readys_T_17, 1)
node _readys_T_19 = bits(_readys_T_18, 2, 0)
node _readys_T_20 = not(_readys_T_19)
node _readys_T_21 = bits(_readys_T_20, 0, 0)
node _readys_T_22 = bits(_readys_T_20, 1, 1)
node _readys_T_23 = bits(_readys_T_20, 2, 2)
wire readys_1 : UInt<1>[3]
connect readys_1[0], _readys_T_21
connect readys_1[1], _readys_T_22
connect readys_1[2], _readys_T_23
node _winner_T_2 = and(readys_1[0], d_d.valid)
node _winner_T_3 = and(readys_1[1], q.io.deq.valid)
node _winner_T_4 = and(readys_1[2], q_1.io.deq.valid)
wire winner_1 : UInt<1>[3]
connect winner_1[0], _winner_T_2
connect winner_1[1], _winner_T_3
connect winner_1[2], _winner_T_4
node prefixOR_1_1 = or(UInt<1>(0h0), winner_1[0])
node prefixOR_2 = or(prefixOR_1_1, winner_1[1])
node _prefixOR_T_1 = or(prefixOR_2, winner_1[2])
node _T_43 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_44 = eq(winner_1[0], UInt<1>(0h0))
node _T_45 = or(_T_43, _T_44)
node _T_46 = eq(prefixOR_1_1, UInt<1>(0h0))
node _T_47 = eq(winner_1[1], UInt<1>(0h0))
node _T_48 = or(_T_46, _T_47)
node _T_49 = eq(prefixOR_2, UInt<1>(0h0))
node _T_50 = eq(winner_1[2], UInt<1>(0h0))
node _T_51 = or(_T_49, _T_50)
node _T_52 = and(_T_45, _T_48)
node _T_53 = and(_T_52, _T_51)
node _T_54 = asUInt(reset)
node _T_55 = eq(_T_54, UInt<1>(0h0))
when _T_55 :
node _T_56 = eq(_T_53, UInt<1>(0h0))
when _T_56 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_4
assert(clock, _T_53, UInt<1>(0h1), "") : assert_4
node _T_57 = or(d_d.valid, q.io.deq.valid)
node _T_58 = or(_T_57, q_1.io.deq.valid)
node _T_59 = eq(_T_58, UInt<1>(0h0))
node _T_60 = or(winner_1[0], winner_1[1])
node _T_61 = or(_T_60, winner_1[2])
node _T_62 = or(_T_59, _T_61)
node _T_63 = asUInt(reset)
node _T_64 = eq(_T_63, UInt<1>(0h0))
when _T_64 :
node _T_65 = eq(_T_62, UInt<1>(0h0))
when _T_65 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_5
assert(clock, _T_62, UInt<1>(0h1), "") : assert_5
node maskedBeats_0_1 = mux(winner_1[0], _T_42, UInt<1>(0h0))
node maskedBeats_1_1 = mux(winner_1[1], UInt<1>(0h0), UInt<1>(0h0))
node maskedBeats_2 = mux(winner_1[2], UInt<1>(0h0), UInt<1>(0h0))
node _initBeats_T = or(maskedBeats_0_1, maskedBeats_1_1)
node initBeats_1 = or(_initBeats_T, maskedBeats_2)
node _beatsLeft_T_4 = and(in_d.ready, in_d.valid)
node _beatsLeft_T_5 = sub(beatsLeft_1, _beatsLeft_T_4)
node _beatsLeft_T_6 = tail(_beatsLeft_T_5, 1)
node _beatsLeft_T_7 = mux(latch_1, initBeats_1, _beatsLeft_T_6)
connect beatsLeft_1, _beatsLeft_T_7
wire _state_WIRE_1 : UInt<1>[3]
connect _state_WIRE_1[0], UInt<1>(0h0)
connect _state_WIRE_1[1], UInt<1>(0h0)
connect _state_WIRE_1[2], UInt<1>(0h0)
regreset state_1 : UInt<1>[3], clock, reset, _state_WIRE_1
node muxState_1 = mux(idle_1, winner_1, state_1)
connect state_1, muxState_1
node allowed_1 = mux(idle_1, readys_1, state_1)
node _d_d_ready_T = and(in_d.ready, allowed_1[0])
connect d_d.ready, _d_d_ready_T
node _q_io_deq_ready_T = and(in_d.ready, allowed_1[1])
connect q.io.deq.ready, _q_io_deq_ready_T
node _q_io_deq_ready_T_1 = and(in_d.ready, allowed_1[2])
connect q_1.io.deq.ready, _q_io_deq_ready_T_1
node _in_d_valid_T = or(d_d.valid, q.io.deq.valid)
node _in_d_valid_T_1 = or(_in_d_valid_T, q_1.io.deq.valid)
node _in_d_valid_T_2 = mux(state_1[0], d_d.valid, UInt<1>(0h0))
node _in_d_valid_T_3 = mux(state_1[1], q.io.deq.valid, UInt<1>(0h0))
node _in_d_valid_T_4 = mux(state_1[2], q_1.io.deq.valid, UInt<1>(0h0))
node _in_d_valid_T_5 = or(_in_d_valid_T_2, _in_d_valid_T_3)
node _in_d_valid_T_6 = or(_in_d_valid_T_5, _in_d_valid_T_4)
wire _in_d_valid_WIRE : UInt<1>
connect _in_d_valid_WIRE, _in_d_valid_T_6
node _in_d_valid_T_7 = mux(idle_1, _in_d_valid_T_1, _in_d_valid_WIRE)
connect in_d.valid, _in_d_valid_T_7
wire _in_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
node _in_d_bits_T = mux(muxState_1[0], d_d.bits.corrupt, UInt<1>(0h0))
node _in_d_bits_T_1 = mux(muxState_1[1], q.io.deq.bits.corrupt, UInt<1>(0h0))
node _in_d_bits_T_2 = mux(muxState_1[2], q_1.io.deq.bits.corrupt, UInt<1>(0h0))
node _in_d_bits_T_3 = or(_in_d_bits_T, _in_d_bits_T_1)
node _in_d_bits_T_4 = or(_in_d_bits_T_3, _in_d_bits_T_2)
wire _in_d_bits_WIRE_1 : UInt<1>
connect _in_d_bits_WIRE_1, _in_d_bits_T_4
connect _in_d_bits_WIRE.corrupt, _in_d_bits_WIRE_1
node _in_d_bits_T_5 = mux(muxState_1[0], d_d.bits.data, UInt<1>(0h0))
node _in_d_bits_T_6 = mux(muxState_1[1], q.io.deq.bits.data, UInt<1>(0h0))
node _in_d_bits_T_7 = mux(muxState_1[2], q_1.io.deq.bits.data, UInt<1>(0h0))
node _in_d_bits_T_8 = or(_in_d_bits_T_5, _in_d_bits_T_6)
node _in_d_bits_T_9 = or(_in_d_bits_T_8, _in_d_bits_T_7)
wire _in_d_bits_WIRE_2 : UInt<64>
connect _in_d_bits_WIRE_2, _in_d_bits_T_9
connect _in_d_bits_WIRE.data, _in_d_bits_WIRE_2
wire _in_d_bits_WIRE_3 : { }
connect _in_d_bits_WIRE.echo, _in_d_bits_WIRE_3
wire _in_d_bits_WIRE_4 : { }
connect _in_d_bits_WIRE.user, _in_d_bits_WIRE_4
node _in_d_bits_T_10 = mux(muxState_1[0], d_d.bits.denied, UInt<1>(0h0))
node _in_d_bits_T_11 = mux(muxState_1[1], q.io.deq.bits.denied, UInt<1>(0h0))
node _in_d_bits_T_12 = mux(muxState_1[2], q_1.io.deq.bits.denied, UInt<1>(0h0))
node _in_d_bits_T_13 = or(_in_d_bits_T_10, _in_d_bits_T_11)
node _in_d_bits_T_14 = or(_in_d_bits_T_13, _in_d_bits_T_12)
wire _in_d_bits_WIRE_5 : UInt<1>
connect _in_d_bits_WIRE_5, _in_d_bits_T_14
connect _in_d_bits_WIRE.denied, _in_d_bits_WIRE_5
node _in_d_bits_T_15 = mux(muxState_1[0], d_d.bits.sink, UInt<1>(0h0))
node _in_d_bits_T_16 = mux(muxState_1[1], q.io.deq.bits.sink, UInt<1>(0h0))
node _in_d_bits_T_17 = mux(muxState_1[2], q_1.io.deq.bits.sink, UInt<1>(0h0))
node _in_d_bits_T_18 = or(_in_d_bits_T_15, _in_d_bits_T_16)
node _in_d_bits_T_19 = or(_in_d_bits_T_18, _in_d_bits_T_17)
wire _in_d_bits_WIRE_6 : UInt<3>
connect _in_d_bits_WIRE_6, _in_d_bits_T_19
connect _in_d_bits_WIRE.sink, _in_d_bits_WIRE_6
node _in_d_bits_T_20 = mux(muxState_1[0], d_d.bits.source, UInt<1>(0h0))
node _in_d_bits_T_21 = mux(muxState_1[1], q.io.deq.bits.source, UInt<1>(0h0))
node _in_d_bits_T_22 = mux(muxState_1[2], q_1.io.deq.bits.source, UInt<1>(0h0))
node _in_d_bits_T_23 = or(_in_d_bits_T_20, _in_d_bits_T_21)
node _in_d_bits_T_24 = or(_in_d_bits_T_23, _in_d_bits_T_22)
wire _in_d_bits_WIRE_7 : UInt<4>
connect _in_d_bits_WIRE_7, _in_d_bits_T_24
connect _in_d_bits_WIRE.source, _in_d_bits_WIRE_7
node _in_d_bits_T_25 = mux(muxState_1[0], d_d.bits.size, UInt<1>(0h0))
node _in_d_bits_T_26 = mux(muxState_1[1], q.io.deq.bits.size, UInt<1>(0h0))
node _in_d_bits_T_27 = mux(muxState_1[2], q_1.io.deq.bits.size, UInt<1>(0h0))
node _in_d_bits_T_28 = or(_in_d_bits_T_25, _in_d_bits_T_26)
node _in_d_bits_T_29 = or(_in_d_bits_T_28, _in_d_bits_T_27)
wire _in_d_bits_WIRE_8 : UInt<3>
connect _in_d_bits_WIRE_8, _in_d_bits_T_29
connect _in_d_bits_WIRE.size, _in_d_bits_WIRE_8
node _in_d_bits_T_30 = mux(muxState_1[0], d_d.bits.param, UInt<1>(0h0))
node _in_d_bits_T_31 = mux(muxState_1[1], q.io.deq.bits.param, UInt<1>(0h0))
node _in_d_bits_T_32 = mux(muxState_1[2], q_1.io.deq.bits.param, UInt<1>(0h0))
node _in_d_bits_T_33 = or(_in_d_bits_T_30, _in_d_bits_T_31)
node _in_d_bits_T_34 = or(_in_d_bits_T_33, _in_d_bits_T_32)
wire _in_d_bits_WIRE_9 : UInt<2>
connect _in_d_bits_WIRE_9, _in_d_bits_T_34
connect _in_d_bits_WIRE.param, _in_d_bits_WIRE_9
node _in_d_bits_T_35 = mux(muxState_1[0], d_d.bits.opcode, UInt<1>(0h0))
node _in_d_bits_T_36 = mux(muxState_1[1], q.io.deq.bits.opcode, UInt<1>(0h0))
node _in_d_bits_T_37 = mux(muxState_1[2], q_1.io.deq.bits.opcode, UInt<1>(0h0))
node _in_d_bits_T_38 = or(_in_d_bits_T_35, _in_d_bits_T_36)
node _in_d_bits_T_39 = or(_in_d_bits_T_38, _in_d_bits_T_37)
wire _in_d_bits_WIRE_10 : UInt<3>
connect _in_d_bits_WIRE_10, _in_d_bits_T_39
connect _in_d_bits_WIRE.opcode, _in_d_bits_WIRE_10
connect in_d.bits.corrupt, _in_d_bits_WIRE.corrupt
connect in_d.bits.data, _in_d_bits_WIRE.data
connect in_d.bits.denied, _in_d_bits_WIRE.denied
connect in_d.bits.sink, _in_d_bits_WIRE.sink
connect in_d.bits.source, _in_d_bits_WIRE.source
connect in_d.bits.size, _in_d_bits_WIRE.size
connect in_d.bits.param, _in_d_bits_WIRE.param
connect in_d.bits.opcode, _in_d_bits_WIRE.opcode
connect nodeIn.b.valid, UInt<1>(0h0)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.address, UInt<32>(0h0)
connect _WIRE_4.bits.source, UInt<5>(0h0)
connect _WIRE_4.bits.size, UInt<3>(0h0)
connect _WIRE_4.bits.param, UInt<3>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.valid, UInt<1>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_6.bits.sink, UInt<1>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
connect _WIRE_7.valid, UInt<1>(0h0)
wire a_a_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
wire a_d_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
node _isPut_T_2 = eq(nodeIn_1.a.bits.opcode, UInt<1>(0h0))
node _isPut_T_3 = eq(nodeIn_1.a.bits.opcode, UInt<1>(0h1))
node isPut_1 = or(_isPut_T_2, _isPut_T_3)
node _toD_T_4 = eq(nodeIn_1.a.bits.opcode, UInt<3>(0h6))
node _toD_T_5 = eq(nodeIn_1.a.bits.param, UInt<2>(0h2))
node _toD_T_6 = and(_toD_T_4, _toD_T_5)
node _toD_T_7 = eq(nodeIn_1.a.bits.opcode, UInt<3>(0h7))
node toD_1 = or(_toD_T_6, _toD_T_7)
node _nodeIn_a_ready_T_1 = mux(toD_1, a_d_1.ready, a_a_1.ready)
connect nodeIn_1.a.ready, _nodeIn_a_ready_T_1
node _a_a_valid_T_2 = eq(toD_1, UInt<1>(0h0))
node _a_a_valid_T_3 = and(nodeIn_1.a.valid, _a_a_valid_T_2)
connect a_a_1.valid, _a_a_valid_T_3
connect a_a_1.bits, nodeIn_1.a.bits
node _a_a_bits_source_T_5 = shl(nodeIn_1.a.bits.source, 1)
node _a_a_bits_source_T_6 = mux(isPut_1, UInt<1>(0h1), UInt<1>(0h0))
node _a_a_bits_source_T_7 = or(_a_a_bits_source_T_5, _a_a_bits_source_T_6)
connect a_a_1.bits.source, _a_a_bits_source_T_7
node _T_66 = eq(nodeIn_1.a.bits.opcode, UInt<3>(0h6))
node _T_67 = eq(nodeIn_1.a.bits.opcode, UInt<3>(0h7))
node _T_68 = or(_T_66, _T_67)
when _T_68 :
connect a_a_1.bits.opcode, UInt<3>(0h4)
connect a_a_1.bits.param, UInt<1>(0h0)
node _a_a_bits_source_T_8 = shl(nodeIn_1.a.bits.source, 1)
node _a_a_bits_source_T_9 = or(_a_a_bits_source_T_8, UInt<1>(0h1))
connect a_a_1.bits.source, _a_a_bits_source_T_9
node _a_d_valid_T_1 = and(nodeIn_1.a.valid, toD_1)
connect a_d_1.valid, _a_d_valid_T_1
wire a_d_bits_d_1 : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
connect a_d_bits_d_1.opcode, UInt<3>(0h4)
connect a_d_bits_d_1.param, UInt<2>(0h0)
connect a_d_bits_d_1.size, nodeIn_1.a.bits.size
connect a_d_bits_d_1.source, nodeIn_1.a.bits.source
connect a_d_bits_d_1.sink, UInt<1>(0h0)
connect a_d_bits_d_1.denied, UInt<1>(0h0)
invalidate a_d_bits_d_1.data
connect a_d_bits_d_1.corrupt, UInt<1>(0h0)
connect a_d_1.bits.corrupt, a_d_bits_d_1.corrupt
connect a_d_1.bits.data, a_d_bits_d_1.data
connect a_d_1.bits.denied, a_d_bits_d_1.denied
connect a_d_1.bits.sink, a_d_bits_d_1.sink
connect a_d_1.bits.source, a_d_bits_d_1.source
connect a_d_1.bits.size, a_d_bits_d_1.size
connect a_d_1.bits.param, a_d_bits_d_1.param
connect a_d_1.bits.opcode, a_d_bits_d_1.opcode
wire c_a_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
node _c_a_valid_T_2 = eq(nodeIn_1.c.bits.opcode, UInt<3>(0h7))
node _c_a_valid_T_3 = and(nodeIn_1.c.valid, _c_a_valid_T_2)
connect c_a_1.valid, _c_a_valid_T_3
node _c_a_bits_T_1 = shl(nodeIn_1.c.bits.source, 1)
node _c_a_bits_legal_T_10 = leq(UInt<1>(0h0), nodeIn_1.c.bits.size)
node _c_a_bits_legal_T_11 = leq(nodeIn_1.c.bits.size, UInt<3>(0h6))
node _c_a_bits_legal_T_12 = and(_c_a_bits_legal_T_10, _c_a_bits_legal_T_11)
node _c_a_bits_legal_T_13 = or(UInt<1>(0h0), _c_a_bits_legal_T_12)
node _c_a_bits_legal_T_14 = xor(nodeIn_1.c.bits.address, UInt<1>(0h0))
node _c_a_bits_legal_T_15 = cvt(_c_a_bits_legal_T_14)
node _c_a_bits_legal_T_16 = and(_c_a_bits_legal_T_15, asSInt(UInt<1>(0h0)))
node _c_a_bits_legal_T_17 = asSInt(_c_a_bits_legal_T_16)
node _c_a_bits_legal_T_18 = eq(_c_a_bits_legal_T_17, asSInt(UInt<1>(0h0)))
node _c_a_bits_legal_T_19 = and(_c_a_bits_legal_T_13, _c_a_bits_legal_T_18)
node c_a_bits_legal_1 = or(UInt<1>(0h0), _c_a_bits_legal_T_19)
wire c_a_bits_a_1 : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect c_a_bits_a_1.opcode, UInt<1>(0h0)
connect c_a_bits_a_1.param, UInt<1>(0h0)
connect c_a_bits_a_1.size, nodeIn_1.c.bits.size
connect c_a_bits_a_1.source, _c_a_bits_T_1
connect c_a_bits_a_1.address, nodeIn_1.c.bits.address
node _c_a_bits_a_mask_sizeOH_T_3 = or(nodeIn_1.c.bits.size, UInt<3>(0h0))
node c_a_bits_a_mask_sizeOH_shiftAmount_1 = bits(_c_a_bits_a_mask_sizeOH_T_3, 1, 0)
node _c_a_bits_a_mask_sizeOH_T_4 = dshl(UInt<1>(0h1), c_a_bits_a_mask_sizeOH_shiftAmount_1)
node _c_a_bits_a_mask_sizeOH_T_5 = bits(_c_a_bits_a_mask_sizeOH_T_4, 2, 0)
node c_a_bits_a_mask_sizeOH_1 = or(_c_a_bits_a_mask_sizeOH_T_5, UInt<1>(0h1))
node c_a_bits_a_mask_sub_sub_sub_0_1_1 = geq(nodeIn_1.c.bits.size, UInt<2>(0h3))
node c_a_bits_a_mask_sub_sub_size_1 = bits(c_a_bits_a_mask_sizeOH_1, 2, 2)
node c_a_bits_a_mask_sub_sub_bit_1 = bits(nodeIn_1.c.bits.address, 2, 2)
node c_a_bits_a_mask_sub_sub_nbit_1 = eq(c_a_bits_a_mask_sub_sub_bit_1, UInt<1>(0h0))
node c_a_bits_a_mask_sub_sub_0_2_1 = and(UInt<1>(0h1), c_a_bits_a_mask_sub_sub_nbit_1)
node _c_a_bits_a_mask_sub_sub_acc_T_2 = and(c_a_bits_a_mask_sub_sub_size_1, c_a_bits_a_mask_sub_sub_0_2_1)
node c_a_bits_a_mask_sub_sub_0_1_1 = or(c_a_bits_a_mask_sub_sub_sub_0_1_1, _c_a_bits_a_mask_sub_sub_acc_T_2)
node c_a_bits_a_mask_sub_sub_1_2_1 = and(UInt<1>(0h1), c_a_bits_a_mask_sub_sub_bit_1)
node _c_a_bits_a_mask_sub_sub_acc_T_3 = and(c_a_bits_a_mask_sub_sub_size_1, c_a_bits_a_mask_sub_sub_1_2_1)
node c_a_bits_a_mask_sub_sub_1_1_1 = or(c_a_bits_a_mask_sub_sub_sub_0_1_1, _c_a_bits_a_mask_sub_sub_acc_T_3)
node c_a_bits_a_mask_sub_size_1 = bits(c_a_bits_a_mask_sizeOH_1, 1, 1)
node c_a_bits_a_mask_sub_bit_1 = bits(nodeIn_1.c.bits.address, 1, 1)
node c_a_bits_a_mask_sub_nbit_1 = eq(c_a_bits_a_mask_sub_bit_1, UInt<1>(0h0))
node c_a_bits_a_mask_sub_0_2_1 = and(c_a_bits_a_mask_sub_sub_0_2_1, c_a_bits_a_mask_sub_nbit_1)
node _c_a_bits_a_mask_sub_acc_T_4 = and(c_a_bits_a_mask_sub_size_1, c_a_bits_a_mask_sub_0_2_1)
node c_a_bits_a_mask_sub_0_1_1 = or(c_a_bits_a_mask_sub_sub_0_1_1, _c_a_bits_a_mask_sub_acc_T_4)
node c_a_bits_a_mask_sub_1_2_1 = and(c_a_bits_a_mask_sub_sub_0_2_1, c_a_bits_a_mask_sub_bit_1)
node _c_a_bits_a_mask_sub_acc_T_5 = and(c_a_bits_a_mask_sub_size_1, c_a_bits_a_mask_sub_1_2_1)
node c_a_bits_a_mask_sub_1_1_1 = or(c_a_bits_a_mask_sub_sub_0_1_1, _c_a_bits_a_mask_sub_acc_T_5)
node c_a_bits_a_mask_sub_2_2_1 = and(c_a_bits_a_mask_sub_sub_1_2_1, c_a_bits_a_mask_sub_nbit_1)
node _c_a_bits_a_mask_sub_acc_T_6 = and(c_a_bits_a_mask_sub_size_1, c_a_bits_a_mask_sub_2_2_1)
node c_a_bits_a_mask_sub_2_1_1 = or(c_a_bits_a_mask_sub_sub_1_1_1, _c_a_bits_a_mask_sub_acc_T_6)
node c_a_bits_a_mask_sub_3_2_1 = and(c_a_bits_a_mask_sub_sub_1_2_1, c_a_bits_a_mask_sub_bit_1)
node _c_a_bits_a_mask_sub_acc_T_7 = and(c_a_bits_a_mask_sub_size_1, c_a_bits_a_mask_sub_3_2_1)
node c_a_bits_a_mask_sub_3_1_1 = or(c_a_bits_a_mask_sub_sub_1_1_1, _c_a_bits_a_mask_sub_acc_T_7)
node c_a_bits_a_mask_size_1 = bits(c_a_bits_a_mask_sizeOH_1, 0, 0)
node c_a_bits_a_mask_bit_1 = bits(nodeIn_1.c.bits.address, 0, 0)
node c_a_bits_a_mask_nbit_1 = eq(c_a_bits_a_mask_bit_1, UInt<1>(0h0))
node c_a_bits_a_mask_eq_8 = and(c_a_bits_a_mask_sub_0_2_1, c_a_bits_a_mask_nbit_1)
node _c_a_bits_a_mask_acc_T_8 = and(c_a_bits_a_mask_size_1, c_a_bits_a_mask_eq_8)
node c_a_bits_a_mask_acc_8 = or(c_a_bits_a_mask_sub_0_1_1, _c_a_bits_a_mask_acc_T_8)
node c_a_bits_a_mask_eq_9 = and(c_a_bits_a_mask_sub_0_2_1, c_a_bits_a_mask_bit_1)
node _c_a_bits_a_mask_acc_T_9 = and(c_a_bits_a_mask_size_1, c_a_bits_a_mask_eq_9)
node c_a_bits_a_mask_acc_9 = or(c_a_bits_a_mask_sub_0_1_1, _c_a_bits_a_mask_acc_T_9)
node c_a_bits_a_mask_eq_10 = and(c_a_bits_a_mask_sub_1_2_1, c_a_bits_a_mask_nbit_1)
node _c_a_bits_a_mask_acc_T_10 = and(c_a_bits_a_mask_size_1, c_a_bits_a_mask_eq_10)
node c_a_bits_a_mask_acc_10 = or(c_a_bits_a_mask_sub_1_1_1, _c_a_bits_a_mask_acc_T_10)
node c_a_bits_a_mask_eq_11 = and(c_a_bits_a_mask_sub_1_2_1, c_a_bits_a_mask_bit_1)
node _c_a_bits_a_mask_acc_T_11 = and(c_a_bits_a_mask_size_1, c_a_bits_a_mask_eq_11)
node c_a_bits_a_mask_acc_11 = or(c_a_bits_a_mask_sub_1_1_1, _c_a_bits_a_mask_acc_T_11)
node c_a_bits_a_mask_eq_12 = and(c_a_bits_a_mask_sub_2_2_1, c_a_bits_a_mask_nbit_1)
node _c_a_bits_a_mask_acc_T_12 = and(c_a_bits_a_mask_size_1, c_a_bits_a_mask_eq_12)
node c_a_bits_a_mask_acc_12 = or(c_a_bits_a_mask_sub_2_1_1, _c_a_bits_a_mask_acc_T_12)
node c_a_bits_a_mask_eq_13 = and(c_a_bits_a_mask_sub_2_2_1, c_a_bits_a_mask_bit_1)
node _c_a_bits_a_mask_acc_T_13 = and(c_a_bits_a_mask_size_1, c_a_bits_a_mask_eq_13)
node c_a_bits_a_mask_acc_13 = or(c_a_bits_a_mask_sub_2_1_1, _c_a_bits_a_mask_acc_T_13)
node c_a_bits_a_mask_eq_14 = and(c_a_bits_a_mask_sub_3_2_1, c_a_bits_a_mask_nbit_1)
node _c_a_bits_a_mask_acc_T_14 = and(c_a_bits_a_mask_size_1, c_a_bits_a_mask_eq_14)
node c_a_bits_a_mask_acc_14 = or(c_a_bits_a_mask_sub_3_1_1, _c_a_bits_a_mask_acc_T_14)
node c_a_bits_a_mask_eq_15 = and(c_a_bits_a_mask_sub_3_2_1, c_a_bits_a_mask_bit_1)
node _c_a_bits_a_mask_acc_T_15 = and(c_a_bits_a_mask_size_1, c_a_bits_a_mask_eq_15)
node c_a_bits_a_mask_acc_15 = or(c_a_bits_a_mask_sub_3_1_1, _c_a_bits_a_mask_acc_T_15)
node c_a_bits_a_mask_lo_lo_1 = cat(c_a_bits_a_mask_acc_9, c_a_bits_a_mask_acc_8)
node c_a_bits_a_mask_lo_hi_1 = cat(c_a_bits_a_mask_acc_11, c_a_bits_a_mask_acc_10)
node c_a_bits_a_mask_lo_1 = cat(c_a_bits_a_mask_lo_hi_1, c_a_bits_a_mask_lo_lo_1)
node c_a_bits_a_mask_hi_lo_1 = cat(c_a_bits_a_mask_acc_13, c_a_bits_a_mask_acc_12)
node c_a_bits_a_mask_hi_hi_1 = cat(c_a_bits_a_mask_acc_15, c_a_bits_a_mask_acc_14)
node c_a_bits_a_mask_hi_1 = cat(c_a_bits_a_mask_hi_hi_1, c_a_bits_a_mask_hi_lo_1)
node _c_a_bits_a_mask_T_1 = cat(c_a_bits_a_mask_hi_1, c_a_bits_a_mask_lo_1)
connect c_a_bits_a_1.mask, _c_a_bits_a_mask_T_1
connect c_a_bits_a_1.data, nodeIn_1.c.bits.data
connect c_a_bits_a_1.corrupt, nodeIn_1.c.bits.corrupt
connect c_a_1.bits, c_a_bits_a_1
wire c_d_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
node _c_d_valid_T_2 = eq(nodeIn_1.c.bits.opcode, UInt<3>(0h6))
node _c_d_valid_T_3 = and(nodeIn_1.c.valid, _c_d_valid_T_2)
connect c_d_1.valid, _c_d_valid_T_3
wire c_d_bits_d_1 : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
connect c_d_bits_d_1.opcode, UInt<3>(0h6)
connect c_d_bits_d_1.param, UInt<1>(0h0)
connect c_d_bits_d_1.size, nodeIn_1.c.bits.size
connect c_d_bits_d_1.source, nodeIn_1.c.bits.source
connect c_d_bits_d_1.sink, UInt<1>(0h0)
connect c_d_bits_d_1.denied, UInt<1>(0h0)
invalidate c_d_bits_d_1.data
connect c_d_bits_d_1.corrupt, UInt<1>(0h0)
connect c_d_1.bits.corrupt, c_d_bits_d_1.corrupt
connect c_d_1.bits.data, c_d_bits_d_1.data
connect c_d_1.bits.denied, c_d_bits_d_1.denied
connect c_d_1.bits.sink, c_d_bits_d_1.sink
connect c_d_1.bits.source, c_d_bits_d_1.source
connect c_d_1.bits.size, c_d_bits_d_1.size
connect c_d_1.bits.param, c_d_bits_d_1.param
connect c_d_1.bits.opcode, c_d_bits_d_1.opcode
node _T_69 = eq(nodeIn_1.c.valid, UInt<1>(0h0))
node _T_70 = eq(nodeIn_1.c.bits.opcode, UInt<3>(0h6))
node _T_71 = or(_T_69, _T_70)
node _T_72 = eq(nodeIn_1.c.bits.opcode, UInt<3>(0h7))
node _T_73 = or(_T_71, _T_72)
node _T_74 = asUInt(reset)
node _T_75 = eq(_T_74, UInt<1>(0h0))
when _T_75 :
node _T_76 = eq(_T_73, UInt<1>(0h0))
when _T_76 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at CacheCork.scala:116 assert (!in.c.valid || in.c.bits.opcode === Release || in.c.bits.opcode === ReleaseData)\n") : printf_6
assert(clock, _T_73, UInt<1>(0h1), "") : assert_6
node _nodeIn_c_ready_T_2 = eq(nodeIn_1.c.bits.opcode, UInt<3>(0h6))
node _nodeIn_c_ready_T_3 = mux(_nodeIn_c_ready_T_2, c_d_1.ready, c_a_1.ready)
connect nodeIn_1.c.ready, _nodeIn_c_ready_T_3
connect nodeIn_1.e.ready, UInt<1>(0h1)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.mask, UInt<8>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<5>(0h0)
connect _WIRE_8.bits.size, UInt<3>(0h0)
connect _WIRE_8.bits.param, UInt<2>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
connect _WIRE_9.ready, UInt<1>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.mask, UInt<8>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<5>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<2>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_77 = eq(_WIRE_11.valid, UInt<1>(0h0))
node _T_78 = asUInt(reset)
node _T_79 = eq(_T_78, UInt<1>(0h0))
when _T_79 :
node _T_80 = eq(_T_77, UInt<1>(0h0))
when _T_80 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at CacheCork.scala:124 assert (!out.b.valid)\n") : printf_7
assert(clock, _T_77, UInt<1>(0h1), "") : assert_7
inst pool_1 of IDPool_1
connect pool_1.clock, clock
connect pool_1.reset, reset
node _pool_io_free_valid_T_1 = and(nodeIn_1.e.ready, nodeIn_1.e.valid)
connect pool_1.io.free.valid, _pool_io_free_valid_T_1
connect pool_1.io.free.bits, nodeIn_1.e.bits.sink
wire in_d_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
node _d_first_T_1 = and(in_d_1.ready, in_d_1.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), in_d_1.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(in_d_1.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
node _d_grant_T_2 = eq(in_d_1.bits.opcode, UInt<3>(0h5))
node _d_grant_T_3 = eq(in_d_1.bits.opcode, UInt<3>(0h4))
node d_grant_1 = or(_d_grant_T_2, _d_grant_T_3)
node _pool_io_alloc_ready_T_3 = and(nodeIn_1.d.ready, nodeIn_1.d.valid)
node _pool_io_alloc_ready_T_4 = and(_pool_io_alloc_ready_T_3, d_first_1)
node _pool_io_alloc_ready_T_5 = and(_pool_io_alloc_ready_T_4, d_grant_1)
connect pool_1.io.alloc.ready, _pool_io_alloc_ready_T_5
node _nodeIn_d_valid_T_5 = eq(d_first_1, UInt<1>(0h0))
node _nodeIn_d_valid_T_6 = or(pool_1.io.alloc.valid, _nodeIn_d_valid_T_5)
node _nodeIn_d_valid_T_7 = eq(d_grant_1, UInt<1>(0h0))
node _nodeIn_d_valid_T_8 = or(_nodeIn_d_valid_T_6, _nodeIn_d_valid_T_7)
node _nodeIn_d_valid_T_9 = and(in_d_1.valid, _nodeIn_d_valid_T_8)
connect nodeIn_1.d.valid, _nodeIn_d_valid_T_9
node _in_d_ready_T_5 = eq(d_first_1, UInt<1>(0h0))
node _in_d_ready_T_6 = or(pool_1.io.alloc.valid, _in_d_ready_T_5)
node _in_d_ready_T_7 = eq(d_grant_1, UInt<1>(0h0))
node _in_d_ready_T_8 = or(_in_d_ready_T_6, _in_d_ready_T_7)
node _in_d_ready_T_9 = and(nodeIn_1.d.ready, _in_d_ready_T_8)
connect in_d_1.ready, _in_d_ready_T_9
connect nodeIn_1.d.bits.corrupt, in_d_1.bits.corrupt
connect nodeIn_1.d.bits.data, in_d_1.bits.data
connect nodeIn_1.d.bits.denied, in_d_1.bits.denied
connect nodeIn_1.d.bits.sink, in_d_1.bits.sink
connect nodeIn_1.d.bits.source, in_d_1.bits.source
connect nodeIn_1.d.bits.size, in_d_1.bits.size
connect nodeIn_1.d.bits.param, in_d_1.bits.param
connect nodeIn_1.d.bits.opcode, in_d_1.bits.opcode
reg nodeIn_d_bits_sink_r_1 : UInt<3>, clock
when d_first_1 :
connect nodeIn_d_bits_sink_r_1, pool_1.io.alloc.bits
node _nodeIn_d_bits_sink_T_1 = mux(d_first_1, pool_1.io.alloc.bits, nodeIn_d_bits_sink_r_1)
connect nodeIn_1.d.bits.sink, _nodeIn_d_bits_sink_T_1
wire d_d_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect d_d_1, x1_nodeOut.d
node _d_d_bits_source_T_1 = shr(x1_nodeOut.d.bits.source, 1)
connect d_d_1.bits.source, _d_d_bits_source_T_1
reg wSourceVec_1 : UInt<1>[10], clock
node _aWOk_T_5 = xor(nodeIn_1.a.bits.address, UInt<1>(0h0))
node _aWOk_T_6 = cvt(_aWOk_T_5)
node _aWOk_T_7 = and(_aWOk_T_6, asSInt(UInt<1>(0h0)))
node _aWOk_T_8 = asSInt(_aWOk_T_7)
node _aWOk_T_9 = eq(_aWOk_T_8, asSInt(UInt<1>(0h0)))
node _bypass_T_2 = and(UInt<1>(0h0), nodeIn_1.a.valid)
node _bypass_T_3 = eq(nodeIn_1.a.bits.source, d_d_1.bits.source)
node bypass_1 = and(_bypass_T_2, _bypass_T_3)
node _dWHeld_T_1 = mux(bypass_1, UInt<1>(0h1), wSourceVec_1[d_d_1.bits.source])
reg dWHeld_r_1 : UInt<1>, clock
when d_first_1 :
connect dWHeld_r_1, _dWHeld_T_1
node dWHeld_1 = mux(d_first_1, _dWHeld_T_1, dWHeld_r_1)
node _T_81 = and(nodeIn_1.a.ready, nodeIn_1.a.valid)
when _T_81 :
connect wSourceVec_1[nodeIn_1.a.bits.source], UInt<1>(0h1)
node _T_82 = eq(x1_nodeOut.d.bits.opcode, UInt<1>(0h1))
node _T_83 = bits(x1_nodeOut.d.bits.source, 0, 0)
node _T_84 = and(_T_82, _T_83)
when _T_84 :
connect d_d_1.bits.opcode, UInt<3>(0h5)
node _d_d_bits_param_T_1 = mux(dWHeld_1, UInt<2>(0h0), UInt<2>(0h1))
connect d_d_1.bits.param, _d_d_bits_param_T_1
node _T_85 = eq(x1_nodeOut.d.bits.opcode, UInt<1>(0h0))
node _T_86 = bits(x1_nodeOut.d.bits.source, 0, 0)
node _T_87 = eq(_T_86, UInt<1>(0h0))
node _T_88 = and(_T_85, _T_87)
when _T_88 :
connect d_d_1.bits.opcode, UInt<3>(0h6)
node _decode_T_9 = dshl(UInt<6>(0h3f), c_a_1.bits.size)
node _decode_T_10 = bits(_decode_T_9, 5, 0)
node _decode_T_11 = not(_decode_T_10)
node decode_3 = shr(_decode_T_11, 3)
node _opdata_T_2 = bits(c_a_1.bits.opcode, 2, 2)
node opdata_3 = eq(_opdata_T_2, UInt<1>(0h0))
node _T_89 = mux(opdata_3, decode_3, UInt<1>(0h0))
node _decode_T_12 = dshl(UInt<6>(0h3f), a_a_1.bits.size)
node _decode_T_13 = bits(_decode_T_12, 5, 0)
node _decode_T_14 = not(_decode_T_13)
node decode_4 = shr(_decode_T_14, 3)
node _opdata_T_3 = bits(a_a_1.bits.opcode, 2, 2)
node opdata_4 = eq(_opdata_T_3, UInt<1>(0h0))
node _T_90 = mux(opdata_4, decode_4, UInt<1>(0h0))
regreset beatsLeft_2 : UInt, clock, reset, UInt<1>(0h0)
node idle_2 = eq(beatsLeft_2, UInt<1>(0h0))
node latch_2 = and(idle_2, x1_nodeOut.a.ready)
node _readys_T_24 = cat(a_a_1.valid, c_a_1.valid)
node _readys_T_25 = shl(_readys_T_24, 1)
node _readys_T_26 = bits(_readys_T_25, 1, 0)
node _readys_T_27 = or(_readys_T_24, _readys_T_26)
node _readys_T_28 = bits(_readys_T_27, 1, 0)
node _readys_T_29 = shl(_readys_T_28, 1)
node _readys_T_30 = bits(_readys_T_29, 1, 0)
node _readys_T_31 = not(_readys_T_30)
node _readys_T_32 = bits(_readys_T_31, 0, 0)
node _readys_T_33 = bits(_readys_T_31, 1, 1)
wire readys_2 : UInt<1>[2]
connect readys_2[0], _readys_T_32
connect readys_2[1], _readys_T_33
node _winner_T_5 = and(readys_2[0], c_a_1.valid)
node _winner_T_6 = and(readys_2[1], a_a_1.valid)
wire winner_2 : UInt<1>[2]
connect winner_2[0], _winner_T_5
connect winner_2[1], _winner_T_6
node prefixOR_1_2 = or(UInt<1>(0h0), winner_2[0])
node _prefixOR_T_2 = or(prefixOR_1_2, winner_2[1])
node _T_91 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_92 = eq(winner_2[0], UInt<1>(0h0))
node _T_93 = or(_T_91, _T_92)
node _T_94 = eq(prefixOR_1_2, UInt<1>(0h0))
node _T_95 = eq(winner_2[1], UInt<1>(0h0))
node _T_96 = or(_T_94, _T_95)
node _T_97 = and(_T_93, _T_96)
node _T_98 = asUInt(reset)
node _T_99 = eq(_T_98, UInt<1>(0h0))
when _T_99 :
node _T_100 = eq(_T_97, UInt<1>(0h0))
when _T_100 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_8
assert(clock, _T_97, UInt<1>(0h1), "") : assert_8
node _T_101 = or(c_a_1.valid, a_a_1.valid)
node _T_102 = eq(_T_101, UInt<1>(0h0))
node _T_103 = or(winner_2[0], winner_2[1])
node _T_104 = or(_T_102, _T_103)
node _T_105 = asUInt(reset)
node _T_106 = eq(_T_105, UInt<1>(0h0))
when _T_106 :
node _T_107 = eq(_T_104, UInt<1>(0h0))
when _T_107 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_9
assert(clock, _T_104, UInt<1>(0h1), "") : assert_9
node maskedBeats_0_2 = mux(winner_2[0], _T_89, UInt<1>(0h0))
node maskedBeats_1_2 = mux(winner_2[1], _T_90, UInt<1>(0h0))
node initBeats_2 = or(maskedBeats_0_2, maskedBeats_1_2)
node _beatsLeft_T_8 = and(x1_nodeOut.a.ready, x1_nodeOut.a.valid)
node _beatsLeft_T_9 = sub(beatsLeft_2, _beatsLeft_T_8)
node _beatsLeft_T_10 = tail(_beatsLeft_T_9, 1)
node _beatsLeft_T_11 = mux(latch_2, initBeats_2, _beatsLeft_T_10)
connect beatsLeft_2, _beatsLeft_T_11
wire _state_WIRE_2 : UInt<1>[2]
connect _state_WIRE_2[0], UInt<1>(0h0)
connect _state_WIRE_2[1], UInt<1>(0h0)
regreset state_2 : UInt<1>[2], clock, reset, _state_WIRE_2
node muxState_2 = mux(idle_2, winner_2, state_2)
connect state_2, muxState_2
node allowed_2 = mux(idle_2, readys_2, state_2)
node _c_a_ready_T_1 = and(x1_nodeOut.a.ready, allowed_2[0])
connect c_a_1.ready, _c_a_ready_T_1
node _a_a_ready_T_1 = and(x1_nodeOut.a.ready, allowed_2[1])
connect a_a_1.ready, _a_a_ready_T_1
node _nodeOut_a_valid_T_5 = or(c_a_1.valid, a_a_1.valid)
node _nodeOut_a_valid_T_6 = mux(state_2[0], c_a_1.valid, UInt<1>(0h0))
node _nodeOut_a_valid_T_7 = mux(state_2[1], a_a_1.valid, UInt<1>(0h0))
node _nodeOut_a_valid_T_8 = or(_nodeOut_a_valid_T_6, _nodeOut_a_valid_T_7)
wire _nodeOut_a_valid_WIRE_1 : UInt<1>
connect _nodeOut_a_valid_WIRE_1, _nodeOut_a_valid_T_8
node _nodeOut_a_valid_T_9 = mux(idle_2, _nodeOut_a_valid_T_5, _nodeOut_a_valid_WIRE_1)
connect x1_nodeOut.a.valid, _nodeOut_a_valid_T_9
wire _nodeOut_a_bits_WIRE_11 : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
node _nodeOut_a_bits_T_24 = mux(muxState_2[0], c_a_1.bits.corrupt, UInt<1>(0h0))
node _nodeOut_a_bits_T_25 = mux(muxState_2[1], a_a_1.bits.corrupt, UInt<1>(0h0))
node _nodeOut_a_bits_T_26 = or(_nodeOut_a_bits_T_24, _nodeOut_a_bits_T_25)
wire _nodeOut_a_bits_WIRE_12 : UInt<1>
connect _nodeOut_a_bits_WIRE_12, _nodeOut_a_bits_T_26
connect _nodeOut_a_bits_WIRE_11.corrupt, _nodeOut_a_bits_WIRE_12
node _nodeOut_a_bits_T_27 = mux(muxState_2[0], c_a_1.bits.data, UInt<1>(0h0))
node _nodeOut_a_bits_T_28 = mux(muxState_2[1], a_a_1.bits.data, UInt<1>(0h0))
node _nodeOut_a_bits_T_29 = or(_nodeOut_a_bits_T_27, _nodeOut_a_bits_T_28)
wire _nodeOut_a_bits_WIRE_13 : UInt<64>
connect _nodeOut_a_bits_WIRE_13, _nodeOut_a_bits_T_29
connect _nodeOut_a_bits_WIRE_11.data, _nodeOut_a_bits_WIRE_13
node _nodeOut_a_bits_T_30 = mux(muxState_2[0], c_a_1.bits.mask, UInt<1>(0h0))
node _nodeOut_a_bits_T_31 = mux(muxState_2[1], a_a_1.bits.mask, UInt<1>(0h0))
node _nodeOut_a_bits_T_32 = or(_nodeOut_a_bits_T_30, _nodeOut_a_bits_T_31)
wire _nodeOut_a_bits_WIRE_14 : UInt<8>
connect _nodeOut_a_bits_WIRE_14, _nodeOut_a_bits_T_32
connect _nodeOut_a_bits_WIRE_11.mask, _nodeOut_a_bits_WIRE_14
wire _nodeOut_a_bits_WIRE_15 : { }
connect _nodeOut_a_bits_WIRE_11.echo, _nodeOut_a_bits_WIRE_15
wire _nodeOut_a_bits_WIRE_16 : { }
connect _nodeOut_a_bits_WIRE_11.user, _nodeOut_a_bits_WIRE_16
node _nodeOut_a_bits_T_33 = mux(muxState_2[0], c_a_1.bits.address, UInt<1>(0h0))
node _nodeOut_a_bits_T_34 = mux(muxState_2[1], a_a_1.bits.address, UInt<1>(0h0))
node _nodeOut_a_bits_T_35 = or(_nodeOut_a_bits_T_33, _nodeOut_a_bits_T_34)
wire _nodeOut_a_bits_WIRE_17 : UInt<32>
connect _nodeOut_a_bits_WIRE_17, _nodeOut_a_bits_T_35
connect _nodeOut_a_bits_WIRE_11.address, _nodeOut_a_bits_WIRE_17
node _nodeOut_a_bits_T_36 = mux(muxState_2[0], c_a_1.bits.source, UInt<1>(0h0))
node _nodeOut_a_bits_T_37 = mux(muxState_2[1], a_a_1.bits.source, UInt<1>(0h0))
node _nodeOut_a_bits_T_38 = or(_nodeOut_a_bits_T_36, _nodeOut_a_bits_T_37)
wire _nodeOut_a_bits_WIRE_18 : UInt<5>
connect _nodeOut_a_bits_WIRE_18, _nodeOut_a_bits_T_38
connect _nodeOut_a_bits_WIRE_11.source, _nodeOut_a_bits_WIRE_18
node _nodeOut_a_bits_T_39 = mux(muxState_2[0], c_a_1.bits.size, UInt<1>(0h0))
node _nodeOut_a_bits_T_40 = mux(muxState_2[1], a_a_1.bits.size, UInt<1>(0h0))
node _nodeOut_a_bits_T_41 = or(_nodeOut_a_bits_T_39, _nodeOut_a_bits_T_40)
wire _nodeOut_a_bits_WIRE_19 : UInt<3>
connect _nodeOut_a_bits_WIRE_19, _nodeOut_a_bits_T_41
connect _nodeOut_a_bits_WIRE_11.size, _nodeOut_a_bits_WIRE_19
node _nodeOut_a_bits_T_42 = mux(muxState_2[0], c_a_1.bits.param, UInt<1>(0h0))
node _nodeOut_a_bits_T_43 = mux(muxState_2[1], a_a_1.bits.param, UInt<1>(0h0))
node _nodeOut_a_bits_T_44 = or(_nodeOut_a_bits_T_42, _nodeOut_a_bits_T_43)
wire _nodeOut_a_bits_WIRE_20 : UInt<3>
connect _nodeOut_a_bits_WIRE_20, _nodeOut_a_bits_T_44
connect _nodeOut_a_bits_WIRE_11.param, _nodeOut_a_bits_WIRE_20
node _nodeOut_a_bits_T_45 = mux(muxState_2[0], c_a_1.bits.opcode, UInt<1>(0h0))
node _nodeOut_a_bits_T_46 = mux(muxState_2[1], a_a_1.bits.opcode, UInt<1>(0h0))
node _nodeOut_a_bits_T_47 = or(_nodeOut_a_bits_T_45, _nodeOut_a_bits_T_46)
wire _nodeOut_a_bits_WIRE_21 : UInt<3>
connect _nodeOut_a_bits_WIRE_21, _nodeOut_a_bits_T_47
connect _nodeOut_a_bits_WIRE_11.opcode, _nodeOut_a_bits_WIRE_21
connect x1_nodeOut.a.bits.corrupt, _nodeOut_a_bits_WIRE_11.corrupt
connect x1_nodeOut.a.bits.data, _nodeOut_a_bits_WIRE_11.data
connect x1_nodeOut.a.bits.mask, _nodeOut_a_bits_WIRE_11.mask
connect x1_nodeOut.a.bits.address, _nodeOut_a_bits_WIRE_11.address
connect x1_nodeOut.a.bits.source, _nodeOut_a_bits_WIRE_11.source
connect x1_nodeOut.a.bits.size, _nodeOut_a_bits_WIRE_11.size
connect x1_nodeOut.a.bits.param, _nodeOut_a_bits_WIRE_11.param
connect x1_nodeOut.a.bits.opcode, _nodeOut_a_bits_WIRE_11.opcode
node _decode_T_15 = dshl(UInt<6>(0h3f), d_d_1.bits.size)
node _decode_T_16 = bits(_decode_T_15, 5, 0)
node _decode_T_17 = not(_decode_T_16)
node decode_5 = shr(_decode_T_17, 3)
node opdata_5 = bits(d_d_1.bits.opcode, 0, 0)
node _T_108 = mux(opdata_5, decode_5, UInt<1>(0h0))
inst q_2 of Queue2_TLBundleD_a32d64s4k3z3c_6
connect q_2.clock, clock
connect q_2.reset, reset
connect q_2.io.enq.valid, c_d_1.valid
connect q_2.io.enq.bits.corrupt, c_d_1.bits.corrupt
connect q_2.io.enq.bits.data, c_d_1.bits.data
connect q_2.io.enq.bits.denied, c_d_1.bits.denied
connect q_2.io.enq.bits.sink, c_d_1.bits.sink
connect q_2.io.enq.bits.source, c_d_1.bits.source
connect q_2.io.enq.bits.size, c_d_1.bits.size
connect q_2.io.enq.bits.param, c_d_1.bits.param
connect q_2.io.enq.bits.opcode, c_d_1.bits.opcode
connect c_d_1.ready, q_2.io.enq.ready
inst q_3 of Queue2_TLBundleD_a32d64s4k3z3c_7
connect q_3.clock, clock
connect q_3.reset, reset
connect q_3.io.enq.valid, a_d_1.valid
connect q_3.io.enq.bits.corrupt, a_d_1.bits.corrupt
connect q_3.io.enq.bits.data, a_d_1.bits.data
connect q_3.io.enq.bits.denied, a_d_1.bits.denied
connect q_3.io.enq.bits.sink, a_d_1.bits.sink
connect q_3.io.enq.bits.source, a_d_1.bits.source
connect q_3.io.enq.bits.size, a_d_1.bits.size
connect q_3.io.enq.bits.param, a_d_1.bits.param
connect q_3.io.enq.bits.opcode, a_d_1.bits.opcode
connect a_d_1.ready, q_3.io.enq.ready
regreset beatsLeft_3 : UInt, clock, reset, UInt<1>(0h0)
node idle_3 = eq(beatsLeft_3, UInt<1>(0h0))
node latch_3 = and(idle_3, in_d_1.ready)
node readys_hi_1 = cat(q_3.io.deq.valid, q_2.io.deq.valid)
node _readys_T_34 = cat(readys_hi_1, d_d_1.valid)
node _readys_T_35 = shl(_readys_T_34, 1)
node _readys_T_36 = bits(_readys_T_35, 2, 0)
node _readys_T_37 = or(_readys_T_34, _readys_T_36)
node _readys_T_38 = shl(_readys_T_37, 2)
node _readys_T_39 = bits(_readys_T_38, 2, 0)
node _readys_T_40 = or(_readys_T_37, _readys_T_39)
node _readys_T_41 = bits(_readys_T_40, 2, 0)
node _readys_T_42 = shl(_readys_T_41, 1)
node _readys_T_43 = bits(_readys_T_42, 2, 0)
node _readys_T_44 = not(_readys_T_43)
node _readys_T_45 = bits(_readys_T_44, 0, 0)
node _readys_T_46 = bits(_readys_T_44, 1, 1)
node _readys_T_47 = bits(_readys_T_44, 2, 2)
wire readys_3 : UInt<1>[3]
connect readys_3[0], _readys_T_45
connect readys_3[1], _readys_T_46
connect readys_3[2], _readys_T_47
node _winner_T_7 = and(readys_3[0], d_d_1.valid)
node _winner_T_8 = and(readys_3[1], q_2.io.deq.valid)
node _winner_T_9 = and(readys_3[2], q_3.io.deq.valid)
wire winner_3 : UInt<1>[3]
connect winner_3[0], _winner_T_7
connect winner_3[1], _winner_T_8
connect winner_3[2], _winner_T_9
node prefixOR_1_3 = or(UInt<1>(0h0), winner_3[0])
node prefixOR_2_1 = or(prefixOR_1_3, winner_3[1])
node _prefixOR_T_3 = or(prefixOR_2_1, winner_3[2])
node _T_109 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_110 = eq(winner_3[0], UInt<1>(0h0))
node _T_111 = or(_T_109, _T_110)
node _T_112 = eq(prefixOR_1_3, UInt<1>(0h0))
node _T_113 = eq(winner_3[1], UInt<1>(0h0))
node _T_114 = or(_T_112, _T_113)
node _T_115 = eq(prefixOR_2_1, UInt<1>(0h0))
node _T_116 = eq(winner_3[2], UInt<1>(0h0))
node _T_117 = or(_T_115, _T_116)
node _T_118 = and(_T_111, _T_114)
node _T_119 = and(_T_118, _T_117)
node _T_120 = asUInt(reset)
node _T_121 = eq(_T_120, UInt<1>(0h0))
when _T_121 :
node _T_122 = eq(_T_119, UInt<1>(0h0))
when _T_122 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_10
assert(clock, _T_119, UInt<1>(0h1), "") : assert_10
node _T_123 = or(d_d_1.valid, q_2.io.deq.valid)
node _T_124 = or(_T_123, q_3.io.deq.valid)
node _T_125 = eq(_T_124, UInt<1>(0h0))
node _T_126 = or(winner_3[0], winner_3[1])
node _T_127 = or(_T_126, winner_3[2])
node _T_128 = or(_T_125, _T_127)
node _T_129 = asUInt(reset)
node _T_130 = eq(_T_129, UInt<1>(0h0))
when _T_130 :
node _T_131 = eq(_T_128, UInt<1>(0h0))
when _T_131 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_11
assert(clock, _T_128, UInt<1>(0h1), "") : assert_11
node maskedBeats_0_3 = mux(winner_3[0], _T_108, UInt<1>(0h0))
node maskedBeats_1_3 = mux(winner_3[1], UInt<1>(0h0), UInt<1>(0h0))
node maskedBeats_2_1 = mux(winner_3[2], UInt<1>(0h0), UInt<1>(0h0))
node _initBeats_T_1 = or(maskedBeats_0_3, maskedBeats_1_3)
node initBeats_3 = or(_initBeats_T_1, maskedBeats_2_1)
node _beatsLeft_T_12 = and(in_d_1.ready, in_d_1.valid)
node _beatsLeft_T_13 = sub(beatsLeft_3, _beatsLeft_T_12)
node _beatsLeft_T_14 = tail(_beatsLeft_T_13, 1)
node _beatsLeft_T_15 = mux(latch_3, initBeats_3, _beatsLeft_T_14)
connect beatsLeft_3, _beatsLeft_T_15
wire _state_WIRE_3 : UInt<1>[3]
connect _state_WIRE_3[0], UInt<1>(0h0)
connect _state_WIRE_3[1], UInt<1>(0h0)
connect _state_WIRE_3[2], UInt<1>(0h0)
regreset state_3 : UInt<1>[3], clock, reset, _state_WIRE_3
node muxState_3 = mux(idle_3, winner_3, state_3)
connect state_3, muxState_3
node allowed_3 = mux(idle_3, readys_3, state_3)
node _d_d_ready_T_1 = and(in_d_1.ready, allowed_3[0])
connect d_d_1.ready, _d_d_ready_T_1
node _q_io_deq_ready_T_2 = and(in_d_1.ready, allowed_3[1])
connect q_2.io.deq.ready, _q_io_deq_ready_T_2
node _q_io_deq_ready_T_3 = and(in_d_1.ready, allowed_3[2])
connect q_3.io.deq.ready, _q_io_deq_ready_T_3
node _in_d_valid_T_8 = or(d_d_1.valid, q_2.io.deq.valid)
node _in_d_valid_T_9 = or(_in_d_valid_T_8, q_3.io.deq.valid)
node _in_d_valid_T_10 = mux(state_3[0], d_d_1.valid, UInt<1>(0h0))
node _in_d_valid_T_11 = mux(state_3[1], q_2.io.deq.valid, UInt<1>(0h0))
node _in_d_valid_T_12 = mux(state_3[2], q_3.io.deq.valid, UInt<1>(0h0))
node _in_d_valid_T_13 = or(_in_d_valid_T_10, _in_d_valid_T_11)
node _in_d_valid_T_14 = or(_in_d_valid_T_13, _in_d_valid_T_12)
wire _in_d_valid_WIRE_1 : UInt<1>
connect _in_d_valid_WIRE_1, _in_d_valid_T_14
node _in_d_valid_T_15 = mux(idle_3, _in_d_valid_T_9, _in_d_valid_WIRE_1)
connect in_d_1.valid, _in_d_valid_T_15
wire _in_d_bits_WIRE_11 : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
node _in_d_bits_T_40 = mux(muxState_3[0], d_d_1.bits.corrupt, UInt<1>(0h0))
node _in_d_bits_T_41 = mux(muxState_3[1], q_2.io.deq.bits.corrupt, UInt<1>(0h0))
node _in_d_bits_T_42 = mux(muxState_3[2], q_3.io.deq.bits.corrupt, UInt<1>(0h0))
node _in_d_bits_T_43 = or(_in_d_bits_T_40, _in_d_bits_T_41)
node _in_d_bits_T_44 = or(_in_d_bits_T_43, _in_d_bits_T_42)
wire _in_d_bits_WIRE_12 : UInt<1>
connect _in_d_bits_WIRE_12, _in_d_bits_T_44
connect _in_d_bits_WIRE_11.corrupt, _in_d_bits_WIRE_12
node _in_d_bits_T_45 = mux(muxState_3[0], d_d_1.bits.data, UInt<1>(0h0))
node _in_d_bits_T_46 = mux(muxState_3[1], q_2.io.deq.bits.data, UInt<1>(0h0))
node _in_d_bits_T_47 = mux(muxState_3[2], q_3.io.deq.bits.data, UInt<1>(0h0))
node _in_d_bits_T_48 = or(_in_d_bits_T_45, _in_d_bits_T_46)
node _in_d_bits_T_49 = or(_in_d_bits_T_48, _in_d_bits_T_47)
wire _in_d_bits_WIRE_13 : UInt<64>
connect _in_d_bits_WIRE_13, _in_d_bits_T_49
connect _in_d_bits_WIRE_11.data, _in_d_bits_WIRE_13
wire _in_d_bits_WIRE_14 : { }
connect _in_d_bits_WIRE_11.echo, _in_d_bits_WIRE_14
wire _in_d_bits_WIRE_15 : { }
connect _in_d_bits_WIRE_11.user, _in_d_bits_WIRE_15
node _in_d_bits_T_50 = mux(muxState_3[0], d_d_1.bits.denied, UInt<1>(0h0))
node _in_d_bits_T_51 = mux(muxState_3[1], q_2.io.deq.bits.denied, UInt<1>(0h0))
node _in_d_bits_T_52 = mux(muxState_3[2], q_3.io.deq.bits.denied, UInt<1>(0h0))
node _in_d_bits_T_53 = or(_in_d_bits_T_50, _in_d_bits_T_51)
node _in_d_bits_T_54 = or(_in_d_bits_T_53, _in_d_bits_T_52)
wire _in_d_bits_WIRE_16 : UInt<1>
connect _in_d_bits_WIRE_16, _in_d_bits_T_54
connect _in_d_bits_WIRE_11.denied, _in_d_bits_WIRE_16
node _in_d_bits_T_55 = mux(muxState_3[0], d_d_1.bits.sink, UInt<1>(0h0))
node _in_d_bits_T_56 = mux(muxState_3[1], q_2.io.deq.bits.sink, UInt<1>(0h0))
node _in_d_bits_T_57 = mux(muxState_3[2], q_3.io.deq.bits.sink, UInt<1>(0h0))
node _in_d_bits_T_58 = or(_in_d_bits_T_55, _in_d_bits_T_56)
node _in_d_bits_T_59 = or(_in_d_bits_T_58, _in_d_bits_T_57)
wire _in_d_bits_WIRE_17 : UInt<3>
connect _in_d_bits_WIRE_17, _in_d_bits_T_59
connect _in_d_bits_WIRE_11.sink, _in_d_bits_WIRE_17
node _in_d_bits_T_60 = mux(muxState_3[0], d_d_1.bits.source, UInt<1>(0h0))
node _in_d_bits_T_61 = mux(muxState_3[1], q_2.io.deq.bits.source, UInt<1>(0h0))
node _in_d_bits_T_62 = mux(muxState_3[2], q_3.io.deq.bits.source, UInt<1>(0h0))
node _in_d_bits_T_63 = or(_in_d_bits_T_60, _in_d_bits_T_61)
node _in_d_bits_T_64 = or(_in_d_bits_T_63, _in_d_bits_T_62)
wire _in_d_bits_WIRE_18 : UInt<4>
connect _in_d_bits_WIRE_18, _in_d_bits_T_64
connect _in_d_bits_WIRE_11.source, _in_d_bits_WIRE_18
node _in_d_bits_T_65 = mux(muxState_3[0], d_d_1.bits.size, UInt<1>(0h0))
node _in_d_bits_T_66 = mux(muxState_3[1], q_2.io.deq.bits.size, UInt<1>(0h0))
node _in_d_bits_T_67 = mux(muxState_3[2], q_3.io.deq.bits.size, UInt<1>(0h0))
node _in_d_bits_T_68 = or(_in_d_bits_T_65, _in_d_bits_T_66)
node _in_d_bits_T_69 = or(_in_d_bits_T_68, _in_d_bits_T_67)
wire _in_d_bits_WIRE_19 : UInt<3>
connect _in_d_bits_WIRE_19, _in_d_bits_T_69
connect _in_d_bits_WIRE_11.size, _in_d_bits_WIRE_19
node _in_d_bits_T_70 = mux(muxState_3[0], d_d_1.bits.param, UInt<1>(0h0))
node _in_d_bits_T_71 = mux(muxState_3[1], q_2.io.deq.bits.param, UInt<1>(0h0))
node _in_d_bits_T_72 = mux(muxState_3[2], q_3.io.deq.bits.param, UInt<1>(0h0))
node _in_d_bits_T_73 = or(_in_d_bits_T_70, _in_d_bits_T_71)
node _in_d_bits_T_74 = or(_in_d_bits_T_73, _in_d_bits_T_72)
wire _in_d_bits_WIRE_20 : UInt<2>
connect _in_d_bits_WIRE_20, _in_d_bits_T_74
connect _in_d_bits_WIRE_11.param, _in_d_bits_WIRE_20
node _in_d_bits_T_75 = mux(muxState_3[0], d_d_1.bits.opcode, UInt<1>(0h0))
node _in_d_bits_T_76 = mux(muxState_3[1], q_2.io.deq.bits.opcode, UInt<1>(0h0))
node _in_d_bits_T_77 = mux(muxState_3[2], q_3.io.deq.bits.opcode, UInt<1>(0h0))
node _in_d_bits_T_78 = or(_in_d_bits_T_75, _in_d_bits_T_76)
node _in_d_bits_T_79 = or(_in_d_bits_T_78, _in_d_bits_T_77)
wire _in_d_bits_WIRE_21 : UInt<3>
connect _in_d_bits_WIRE_21, _in_d_bits_T_79
connect _in_d_bits_WIRE_11.opcode, _in_d_bits_WIRE_21
connect in_d_1.bits.corrupt, _in_d_bits_WIRE_11.corrupt
connect in_d_1.bits.data, _in_d_bits_WIRE_11.data
connect in_d_1.bits.denied, _in_d_bits_WIRE_11.denied
connect in_d_1.bits.sink, _in_d_bits_WIRE_11.sink
connect in_d_1.bits.source, _in_d_bits_WIRE_11.source
connect in_d_1.bits.size, _in_d_bits_WIRE_11.size
connect in_d_1.bits.param, _in_d_bits_WIRE_11.param
connect in_d_1.bits.opcode, _in_d_bits_WIRE_11.opcode
connect nodeIn_1.b.valid, UInt<1>(0h0)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<5>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
connect _WIRE_13.valid, UInt<1>(0h0)
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_14.bits.sink, UInt<1>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
connect _WIRE_15.valid, UInt<1>(0h0)
wire a_a_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
wire a_d_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
node _isPut_T_4 = eq(nodeIn_2.a.bits.opcode, UInt<1>(0h0))
node _isPut_T_5 = eq(nodeIn_2.a.bits.opcode, UInt<1>(0h1))
node isPut_2 = or(_isPut_T_4, _isPut_T_5)
node _toD_T_8 = eq(nodeIn_2.a.bits.opcode, UInt<3>(0h6))
node _toD_T_9 = eq(nodeIn_2.a.bits.param, UInt<2>(0h2))
node _toD_T_10 = and(_toD_T_8, _toD_T_9)
node _toD_T_11 = eq(nodeIn_2.a.bits.opcode, UInt<3>(0h7))
node toD_2 = or(_toD_T_10, _toD_T_11)
node _nodeIn_a_ready_T_2 = mux(toD_2, a_d_2.ready, a_a_2.ready)
connect nodeIn_2.a.ready, _nodeIn_a_ready_T_2
node _a_a_valid_T_4 = eq(toD_2, UInt<1>(0h0))
node _a_a_valid_T_5 = and(nodeIn_2.a.valid, _a_a_valid_T_4)
connect a_a_2.valid, _a_a_valid_T_5
connect a_a_2.bits, nodeIn_2.a.bits
node _a_a_bits_source_T_10 = shl(nodeIn_2.a.bits.source, 1)
node _a_a_bits_source_T_11 = mux(isPut_2, UInt<1>(0h1), UInt<1>(0h0))
node _a_a_bits_source_T_12 = or(_a_a_bits_source_T_10, _a_a_bits_source_T_11)
connect a_a_2.bits.source, _a_a_bits_source_T_12
node _T_132 = eq(nodeIn_2.a.bits.opcode, UInt<3>(0h6))
node _T_133 = eq(nodeIn_2.a.bits.opcode, UInt<3>(0h7))
node _T_134 = or(_T_132, _T_133)
when _T_134 :
connect a_a_2.bits.opcode, UInt<3>(0h4)
connect a_a_2.bits.param, UInt<1>(0h0)
node _a_a_bits_source_T_13 = shl(nodeIn_2.a.bits.source, 1)
node _a_a_bits_source_T_14 = or(_a_a_bits_source_T_13, UInt<1>(0h1))
connect a_a_2.bits.source, _a_a_bits_source_T_14
node _a_d_valid_T_2 = and(nodeIn_2.a.valid, toD_2)
connect a_d_2.valid, _a_d_valid_T_2
wire a_d_bits_d_2 : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
connect a_d_bits_d_2.opcode, UInt<3>(0h4)
connect a_d_bits_d_2.param, UInt<2>(0h0)
connect a_d_bits_d_2.size, nodeIn_2.a.bits.size
connect a_d_bits_d_2.source, nodeIn_2.a.bits.source
connect a_d_bits_d_2.sink, UInt<1>(0h0)
connect a_d_bits_d_2.denied, UInt<1>(0h0)
invalidate a_d_bits_d_2.data
connect a_d_bits_d_2.corrupt, UInt<1>(0h0)
connect a_d_2.bits.corrupt, a_d_bits_d_2.corrupt
connect a_d_2.bits.data, a_d_bits_d_2.data
connect a_d_2.bits.denied, a_d_bits_d_2.denied
connect a_d_2.bits.sink, a_d_bits_d_2.sink
connect a_d_2.bits.source, a_d_bits_d_2.source
connect a_d_2.bits.size, a_d_bits_d_2.size
connect a_d_2.bits.param, a_d_bits_d_2.param
connect a_d_2.bits.opcode, a_d_bits_d_2.opcode
wire c_a_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
node _c_a_valid_T_4 = eq(nodeIn_2.c.bits.opcode, UInt<3>(0h7))
node _c_a_valid_T_5 = and(nodeIn_2.c.valid, _c_a_valid_T_4)
connect c_a_2.valid, _c_a_valid_T_5
node _c_a_bits_T_2 = shl(nodeIn_2.c.bits.source, 1)
node _c_a_bits_legal_T_20 = leq(UInt<1>(0h0), nodeIn_2.c.bits.size)
node _c_a_bits_legal_T_21 = leq(nodeIn_2.c.bits.size, UInt<3>(0h6))
node _c_a_bits_legal_T_22 = and(_c_a_bits_legal_T_20, _c_a_bits_legal_T_21)
node _c_a_bits_legal_T_23 = or(UInt<1>(0h0), _c_a_bits_legal_T_22)
node _c_a_bits_legal_T_24 = xor(nodeIn_2.c.bits.address, UInt<1>(0h0))
node _c_a_bits_legal_T_25 = cvt(_c_a_bits_legal_T_24)
node _c_a_bits_legal_T_26 = and(_c_a_bits_legal_T_25, asSInt(UInt<1>(0h0)))
node _c_a_bits_legal_T_27 = asSInt(_c_a_bits_legal_T_26)
node _c_a_bits_legal_T_28 = eq(_c_a_bits_legal_T_27, asSInt(UInt<1>(0h0)))
node _c_a_bits_legal_T_29 = and(_c_a_bits_legal_T_23, _c_a_bits_legal_T_28)
node c_a_bits_legal_2 = or(UInt<1>(0h0), _c_a_bits_legal_T_29)
wire c_a_bits_a_2 : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect c_a_bits_a_2.opcode, UInt<1>(0h0)
connect c_a_bits_a_2.param, UInt<1>(0h0)
connect c_a_bits_a_2.size, nodeIn_2.c.bits.size
connect c_a_bits_a_2.source, _c_a_bits_T_2
connect c_a_bits_a_2.address, nodeIn_2.c.bits.address
node _c_a_bits_a_mask_sizeOH_T_6 = or(nodeIn_2.c.bits.size, UInt<3>(0h0))
node c_a_bits_a_mask_sizeOH_shiftAmount_2 = bits(_c_a_bits_a_mask_sizeOH_T_6, 1, 0)
node _c_a_bits_a_mask_sizeOH_T_7 = dshl(UInt<1>(0h1), c_a_bits_a_mask_sizeOH_shiftAmount_2)
node _c_a_bits_a_mask_sizeOH_T_8 = bits(_c_a_bits_a_mask_sizeOH_T_7, 2, 0)
node c_a_bits_a_mask_sizeOH_2 = or(_c_a_bits_a_mask_sizeOH_T_8, UInt<1>(0h1))
node c_a_bits_a_mask_sub_sub_sub_0_1_2 = geq(nodeIn_2.c.bits.size, UInt<2>(0h3))
node c_a_bits_a_mask_sub_sub_size_2 = bits(c_a_bits_a_mask_sizeOH_2, 2, 2)
node c_a_bits_a_mask_sub_sub_bit_2 = bits(nodeIn_2.c.bits.address, 2, 2)
node c_a_bits_a_mask_sub_sub_nbit_2 = eq(c_a_bits_a_mask_sub_sub_bit_2, UInt<1>(0h0))
node c_a_bits_a_mask_sub_sub_0_2_2 = and(UInt<1>(0h1), c_a_bits_a_mask_sub_sub_nbit_2)
node _c_a_bits_a_mask_sub_sub_acc_T_4 = and(c_a_bits_a_mask_sub_sub_size_2, c_a_bits_a_mask_sub_sub_0_2_2)
node c_a_bits_a_mask_sub_sub_0_1_2 = or(c_a_bits_a_mask_sub_sub_sub_0_1_2, _c_a_bits_a_mask_sub_sub_acc_T_4)
node c_a_bits_a_mask_sub_sub_1_2_2 = and(UInt<1>(0h1), c_a_bits_a_mask_sub_sub_bit_2)
node _c_a_bits_a_mask_sub_sub_acc_T_5 = and(c_a_bits_a_mask_sub_sub_size_2, c_a_bits_a_mask_sub_sub_1_2_2)
node c_a_bits_a_mask_sub_sub_1_1_2 = or(c_a_bits_a_mask_sub_sub_sub_0_1_2, _c_a_bits_a_mask_sub_sub_acc_T_5)
node c_a_bits_a_mask_sub_size_2 = bits(c_a_bits_a_mask_sizeOH_2, 1, 1)
node c_a_bits_a_mask_sub_bit_2 = bits(nodeIn_2.c.bits.address, 1, 1)
node c_a_bits_a_mask_sub_nbit_2 = eq(c_a_bits_a_mask_sub_bit_2, UInt<1>(0h0))
node c_a_bits_a_mask_sub_0_2_2 = and(c_a_bits_a_mask_sub_sub_0_2_2, c_a_bits_a_mask_sub_nbit_2)
node _c_a_bits_a_mask_sub_acc_T_8 = and(c_a_bits_a_mask_sub_size_2, c_a_bits_a_mask_sub_0_2_2)
node c_a_bits_a_mask_sub_0_1_2 = or(c_a_bits_a_mask_sub_sub_0_1_2, _c_a_bits_a_mask_sub_acc_T_8)
node c_a_bits_a_mask_sub_1_2_2 = and(c_a_bits_a_mask_sub_sub_0_2_2, c_a_bits_a_mask_sub_bit_2)
node _c_a_bits_a_mask_sub_acc_T_9 = and(c_a_bits_a_mask_sub_size_2, c_a_bits_a_mask_sub_1_2_2)
node c_a_bits_a_mask_sub_1_1_2 = or(c_a_bits_a_mask_sub_sub_0_1_2, _c_a_bits_a_mask_sub_acc_T_9)
node c_a_bits_a_mask_sub_2_2_2 = and(c_a_bits_a_mask_sub_sub_1_2_2, c_a_bits_a_mask_sub_nbit_2)
node _c_a_bits_a_mask_sub_acc_T_10 = and(c_a_bits_a_mask_sub_size_2, c_a_bits_a_mask_sub_2_2_2)
node c_a_bits_a_mask_sub_2_1_2 = or(c_a_bits_a_mask_sub_sub_1_1_2, _c_a_bits_a_mask_sub_acc_T_10)
node c_a_bits_a_mask_sub_3_2_2 = and(c_a_bits_a_mask_sub_sub_1_2_2, c_a_bits_a_mask_sub_bit_2)
node _c_a_bits_a_mask_sub_acc_T_11 = and(c_a_bits_a_mask_sub_size_2, c_a_bits_a_mask_sub_3_2_2)
node c_a_bits_a_mask_sub_3_1_2 = or(c_a_bits_a_mask_sub_sub_1_1_2, _c_a_bits_a_mask_sub_acc_T_11)
node c_a_bits_a_mask_size_2 = bits(c_a_bits_a_mask_sizeOH_2, 0, 0)
node c_a_bits_a_mask_bit_2 = bits(nodeIn_2.c.bits.address, 0, 0)
node c_a_bits_a_mask_nbit_2 = eq(c_a_bits_a_mask_bit_2, UInt<1>(0h0))
node c_a_bits_a_mask_eq_16 = and(c_a_bits_a_mask_sub_0_2_2, c_a_bits_a_mask_nbit_2)
node _c_a_bits_a_mask_acc_T_16 = and(c_a_bits_a_mask_size_2, c_a_bits_a_mask_eq_16)
node c_a_bits_a_mask_acc_16 = or(c_a_bits_a_mask_sub_0_1_2, _c_a_bits_a_mask_acc_T_16)
node c_a_bits_a_mask_eq_17 = and(c_a_bits_a_mask_sub_0_2_2, c_a_bits_a_mask_bit_2)
node _c_a_bits_a_mask_acc_T_17 = and(c_a_bits_a_mask_size_2, c_a_bits_a_mask_eq_17)
node c_a_bits_a_mask_acc_17 = or(c_a_bits_a_mask_sub_0_1_2, _c_a_bits_a_mask_acc_T_17)
node c_a_bits_a_mask_eq_18 = and(c_a_bits_a_mask_sub_1_2_2, c_a_bits_a_mask_nbit_2)
node _c_a_bits_a_mask_acc_T_18 = and(c_a_bits_a_mask_size_2, c_a_bits_a_mask_eq_18)
node c_a_bits_a_mask_acc_18 = or(c_a_bits_a_mask_sub_1_1_2, _c_a_bits_a_mask_acc_T_18)
node c_a_bits_a_mask_eq_19 = and(c_a_bits_a_mask_sub_1_2_2, c_a_bits_a_mask_bit_2)
node _c_a_bits_a_mask_acc_T_19 = and(c_a_bits_a_mask_size_2, c_a_bits_a_mask_eq_19)
node c_a_bits_a_mask_acc_19 = or(c_a_bits_a_mask_sub_1_1_2, _c_a_bits_a_mask_acc_T_19)
node c_a_bits_a_mask_eq_20 = and(c_a_bits_a_mask_sub_2_2_2, c_a_bits_a_mask_nbit_2)
node _c_a_bits_a_mask_acc_T_20 = and(c_a_bits_a_mask_size_2, c_a_bits_a_mask_eq_20)
node c_a_bits_a_mask_acc_20 = or(c_a_bits_a_mask_sub_2_1_2, _c_a_bits_a_mask_acc_T_20)
node c_a_bits_a_mask_eq_21 = and(c_a_bits_a_mask_sub_2_2_2, c_a_bits_a_mask_bit_2)
node _c_a_bits_a_mask_acc_T_21 = and(c_a_bits_a_mask_size_2, c_a_bits_a_mask_eq_21)
node c_a_bits_a_mask_acc_21 = or(c_a_bits_a_mask_sub_2_1_2, _c_a_bits_a_mask_acc_T_21)
node c_a_bits_a_mask_eq_22 = and(c_a_bits_a_mask_sub_3_2_2, c_a_bits_a_mask_nbit_2)
node _c_a_bits_a_mask_acc_T_22 = and(c_a_bits_a_mask_size_2, c_a_bits_a_mask_eq_22)
node c_a_bits_a_mask_acc_22 = or(c_a_bits_a_mask_sub_3_1_2, _c_a_bits_a_mask_acc_T_22)
node c_a_bits_a_mask_eq_23 = and(c_a_bits_a_mask_sub_3_2_2, c_a_bits_a_mask_bit_2)
node _c_a_bits_a_mask_acc_T_23 = and(c_a_bits_a_mask_size_2, c_a_bits_a_mask_eq_23)
node c_a_bits_a_mask_acc_23 = or(c_a_bits_a_mask_sub_3_1_2, _c_a_bits_a_mask_acc_T_23)
node c_a_bits_a_mask_lo_lo_2 = cat(c_a_bits_a_mask_acc_17, c_a_bits_a_mask_acc_16)
node c_a_bits_a_mask_lo_hi_2 = cat(c_a_bits_a_mask_acc_19, c_a_bits_a_mask_acc_18)
node c_a_bits_a_mask_lo_2 = cat(c_a_bits_a_mask_lo_hi_2, c_a_bits_a_mask_lo_lo_2)
node c_a_bits_a_mask_hi_lo_2 = cat(c_a_bits_a_mask_acc_21, c_a_bits_a_mask_acc_20)
node c_a_bits_a_mask_hi_hi_2 = cat(c_a_bits_a_mask_acc_23, c_a_bits_a_mask_acc_22)
node c_a_bits_a_mask_hi_2 = cat(c_a_bits_a_mask_hi_hi_2, c_a_bits_a_mask_hi_lo_2)
node _c_a_bits_a_mask_T_2 = cat(c_a_bits_a_mask_hi_2, c_a_bits_a_mask_lo_2)
connect c_a_bits_a_2.mask, _c_a_bits_a_mask_T_2
connect c_a_bits_a_2.data, nodeIn_2.c.bits.data
connect c_a_bits_a_2.corrupt, nodeIn_2.c.bits.corrupt
connect c_a_2.bits, c_a_bits_a_2
wire c_d_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
node _c_d_valid_T_4 = eq(nodeIn_2.c.bits.opcode, UInt<3>(0h6))
node _c_d_valid_T_5 = and(nodeIn_2.c.valid, _c_d_valid_T_4)
connect c_d_2.valid, _c_d_valid_T_5
wire c_d_bits_d_2 : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
connect c_d_bits_d_2.opcode, UInt<3>(0h6)
connect c_d_bits_d_2.param, UInt<1>(0h0)
connect c_d_bits_d_2.size, nodeIn_2.c.bits.size
connect c_d_bits_d_2.source, nodeIn_2.c.bits.source
connect c_d_bits_d_2.sink, UInt<1>(0h0)
connect c_d_bits_d_2.denied, UInt<1>(0h0)
invalidate c_d_bits_d_2.data
connect c_d_bits_d_2.corrupt, UInt<1>(0h0)
connect c_d_2.bits.corrupt, c_d_bits_d_2.corrupt
connect c_d_2.bits.data, c_d_bits_d_2.data
connect c_d_2.bits.denied, c_d_bits_d_2.denied
connect c_d_2.bits.sink, c_d_bits_d_2.sink
connect c_d_2.bits.source, c_d_bits_d_2.source
connect c_d_2.bits.size, c_d_bits_d_2.size
connect c_d_2.bits.param, c_d_bits_d_2.param
connect c_d_2.bits.opcode, c_d_bits_d_2.opcode
node _T_135 = eq(nodeIn_2.c.valid, UInt<1>(0h0))
node _T_136 = eq(nodeIn_2.c.bits.opcode, UInt<3>(0h6))
node _T_137 = or(_T_135, _T_136)
node _T_138 = eq(nodeIn_2.c.bits.opcode, UInt<3>(0h7))
node _T_139 = or(_T_137, _T_138)
node _T_140 = asUInt(reset)
node _T_141 = eq(_T_140, UInt<1>(0h0))
when _T_141 :
node _T_142 = eq(_T_139, UInt<1>(0h0))
when _T_142 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at CacheCork.scala:116 assert (!in.c.valid || in.c.bits.opcode === Release || in.c.bits.opcode === ReleaseData)\n") : printf_12
assert(clock, _T_139, UInt<1>(0h1), "") : assert_12
node _nodeIn_c_ready_T_4 = eq(nodeIn_2.c.bits.opcode, UInt<3>(0h6))
node _nodeIn_c_ready_T_5 = mux(_nodeIn_c_ready_T_4, c_d_2.ready, c_a_2.ready)
connect nodeIn_2.c.ready, _nodeIn_c_ready_T_5
connect nodeIn_2.e.ready, UInt<1>(0h1)
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.mask, UInt<8>(0h0)
connect _WIRE_16.bits.address, UInt<32>(0h0)
connect _WIRE_16.bits.source, UInt<5>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<2>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
connect _WIRE_17.ready, UInt<1>(0h0)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.mask, UInt<8>(0h0)
connect _WIRE_18.bits.address, UInt<32>(0h0)
connect _WIRE_18.bits.source, UInt<5>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<2>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_143 = eq(_WIRE_19.valid, UInt<1>(0h0))
node _T_144 = asUInt(reset)
node _T_145 = eq(_T_144, UInt<1>(0h0))
when _T_145 :
node _T_146 = eq(_T_143, UInt<1>(0h0))
when _T_146 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at CacheCork.scala:124 assert (!out.b.valid)\n") : printf_13
assert(clock, _T_143, UInt<1>(0h1), "") : assert_13
inst pool_2 of IDPool_2
connect pool_2.clock, clock
connect pool_2.reset, reset
node _pool_io_free_valid_T_2 = and(nodeIn_2.e.ready, nodeIn_2.e.valid)
connect pool_2.io.free.valid, _pool_io_free_valid_T_2
connect pool_2.io.free.bits, nodeIn_2.e.bits.sink
wire in_d_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
node _d_first_T_2 = and(in_d_2.ready, in_d_2.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), in_d_2.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(in_d_2.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
node _d_grant_T_4 = eq(in_d_2.bits.opcode, UInt<3>(0h5))
node _d_grant_T_5 = eq(in_d_2.bits.opcode, UInt<3>(0h4))
node d_grant_2 = or(_d_grant_T_4, _d_grant_T_5)
node _pool_io_alloc_ready_T_6 = and(nodeIn_2.d.ready, nodeIn_2.d.valid)
node _pool_io_alloc_ready_T_7 = and(_pool_io_alloc_ready_T_6, d_first_2)
node _pool_io_alloc_ready_T_8 = and(_pool_io_alloc_ready_T_7, d_grant_2)
connect pool_2.io.alloc.ready, _pool_io_alloc_ready_T_8
node _nodeIn_d_valid_T_10 = eq(d_first_2, UInt<1>(0h0))
node _nodeIn_d_valid_T_11 = or(pool_2.io.alloc.valid, _nodeIn_d_valid_T_10)
node _nodeIn_d_valid_T_12 = eq(d_grant_2, UInt<1>(0h0))
node _nodeIn_d_valid_T_13 = or(_nodeIn_d_valid_T_11, _nodeIn_d_valid_T_12)
node _nodeIn_d_valid_T_14 = and(in_d_2.valid, _nodeIn_d_valid_T_13)
connect nodeIn_2.d.valid, _nodeIn_d_valid_T_14
node _in_d_ready_T_10 = eq(d_first_2, UInt<1>(0h0))
node _in_d_ready_T_11 = or(pool_2.io.alloc.valid, _in_d_ready_T_10)
node _in_d_ready_T_12 = eq(d_grant_2, UInt<1>(0h0))
node _in_d_ready_T_13 = or(_in_d_ready_T_11, _in_d_ready_T_12)
node _in_d_ready_T_14 = and(nodeIn_2.d.ready, _in_d_ready_T_13)
connect in_d_2.ready, _in_d_ready_T_14
connect nodeIn_2.d.bits.corrupt, in_d_2.bits.corrupt
connect nodeIn_2.d.bits.data, in_d_2.bits.data
connect nodeIn_2.d.bits.denied, in_d_2.bits.denied
connect nodeIn_2.d.bits.sink, in_d_2.bits.sink
connect nodeIn_2.d.bits.source, in_d_2.bits.source
connect nodeIn_2.d.bits.size, in_d_2.bits.size
connect nodeIn_2.d.bits.param, in_d_2.bits.param
connect nodeIn_2.d.bits.opcode, in_d_2.bits.opcode
reg nodeIn_d_bits_sink_r_2 : UInt<3>, clock
when d_first_2 :
connect nodeIn_d_bits_sink_r_2, pool_2.io.alloc.bits
node _nodeIn_d_bits_sink_T_2 = mux(d_first_2, pool_2.io.alloc.bits, nodeIn_d_bits_sink_r_2)
connect nodeIn_2.d.bits.sink, _nodeIn_d_bits_sink_T_2
wire d_d_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect d_d_2, x1_nodeOut_1.d
node _d_d_bits_source_T_2 = shr(x1_nodeOut_1.d.bits.source, 1)
connect d_d_2.bits.source, _d_d_bits_source_T_2
reg wSourceVec_2 : UInt<1>[10], clock
node _aWOk_T_10 = xor(nodeIn_2.a.bits.address, UInt<1>(0h0))
node _aWOk_T_11 = cvt(_aWOk_T_10)
node _aWOk_T_12 = and(_aWOk_T_11, asSInt(UInt<1>(0h0)))
node _aWOk_T_13 = asSInt(_aWOk_T_12)
node _aWOk_T_14 = eq(_aWOk_T_13, asSInt(UInt<1>(0h0)))
node _bypass_T_4 = and(UInt<1>(0h0), nodeIn_2.a.valid)
node _bypass_T_5 = eq(nodeIn_2.a.bits.source, d_d_2.bits.source)
node bypass_2 = and(_bypass_T_4, _bypass_T_5)
node _dWHeld_T_2 = mux(bypass_2, UInt<1>(0h1), wSourceVec_2[d_d_2.bits.source])
reg dWHeld_r_2 : UInt<1>, clock
when d_first_2 :
connect dWHeld_r_2, _dWHeld_T_2
node dWHeld_2 = mux(d_first_2, _dWHeld_T_2, dWHeld_r_2)
node _T_147 = and(nodeIn_2.a.ready, nodeIn_2.a.valid)
when _T_147 :
connect wSourceVec_2[nodeIn_2.a.bits.source], UInt<1>(0h1)
node _T_148 = eq(x1_nodeOut_1.d.bits.opcode, UInt<1>(0h1))
node _T_149 = bits(x1_nodeOut_1.d.bits.source, 0, 0)
node _T_150 = and(_T_148, _T_149)
when _T_150 :
connect d_d_2.bits.opcode, UInt<3>(0h5)
node _d_d_bits_param_T_2 = mux(dWHeld_2, UInt<2>(0h0), UInt<2>(0h1))
connect d_d_2.bits.param, _d_d_bits_param_T_2
node _T_151 = eq(x1_nodeOut_1.d.bits.opcode, UInt<1>(0h0))
node _T_152 = bits(x1_nodeOut_1.d.bits.source, 0, 0)
node _T_153 = eq(_T_152, UInt<1>(0h0))
node _T_154 = and(_T_151, _T_153)
when _T_154 :
connect d_d_2.bits.opcode, UInt<3>(0h6)
node _decode_T_18 = dshl(UInt<6>(0h3f), c_a_2.bits.size)
node _decode_T_19 = bits(_decode_T_18, 5, 0)
node _decode_T_20 = not(_decode_T_19)
node decode_6 = shr(_decode_T_20, 3)
node _opdata_T_4 = bits(c_a_2.bits.opcode, 2, 2)
node opdata_6 = eq(_opdata_T_4, UInt<1>(0h0))
node _T_155 = mux(opdata_6, decode_6, UInt<1>(0h0))
node _decode_T_21 = dshl(UInt<6>(0h3f), a_a_2.bits.size)
node _decode_T_22 = bits(_decode_T_21, 5, 0)
node _decode_T_23 = not(_decode_T_22)
node decode_7 = shr(_decode_T_23, 3)
node _opdata_T_5 = bits(a_a_2.bits.opcode, 2, 2)
node opdata_7 = eq(_opdata_T_5, UInt<1>(0h0))
node _T_156 = mux(opdata_7, decode_7, UInt<1>(0h0))
regreset beatsLeft_4 : UInt, clock, reset, UInt<1>(0h0)
node idle_4 = eq(beatsLeft_4, UInt<1>(0h0))
node latch_4 = and(idle_4, x1_nodeOut_1.a.ready)
node _readys_T_48 = cat(a_a_2.valid, c_a_2.valid)
node _readys_T_49 = shl(_readys_T_48, 1)
node _readys_T_50 = bits(_readys_T_49, 1, 0)
node _readys_T_51 = or(_readys_T_48, _readys_T_50)
node _readys_T_52 = bits(_readys_T_51, 1, 0)
node _readys_T_53 = shl(_readys_T_52, 1)
node _readys_T_54 = bits(_readys_T_53, 1, 0)
node _readys_T_55 = not(_readys_T_54)
node _readys_T_56 = bits(_readys_T_55, 0, 0)
node _readys_T_57 = bits(_readys_T_55, 1, 1)
wire readys_4 : UInt<1>[2]
connect readys_4[0], _readys_T_56
connect readys_4[1], _readys_T_57
node _winner_T_10 = and(readys_4[0], c_a_2.valid)
node _winner_T_11 = and(readys_4[1], a_a_2.valid)
wire winner_4 : UInt<1>[2]
connect winner_4[0], _winner_T_10
connect winner_4[1], _winner_T_11
node prefixOR_1_4 = or(UInt<1>(0h0), winner_4[0])
node _prefixOR_T_4 = or(prefixOR_1_4, winner_4[1])
node _T_157 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_158 = eq(winner_4[0], UInt<1>(0h0))
node _T_159 = or(_T_157, _T_158)
node _T_160 = eq(prefixOR_1_4, UInt<1>(0h0))
node _T_161 = eq(winner_4[1], UInt<1>(0h0))
node _T_162 = or(_T_160, _T_161)
node _T_163 = and(_T_159, _T_162)
node _T_164 = asUInt(reset)
node _T_165 = eq(_T_164, UInt<1>(0h0))
when _T_165 :
node _T_166 = eq(_T_163, UInt<1>(0h0))
when _T_166 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_14
assert(clock, _T_163, UInt<1>(0h1), "") : assert_14
node _T_167 = or(c_a_2.valid, a_a_2.valid)
node _T_168 = eq(_T_167, UInt<1>(0h0))
node _T_169 = or(winner_4[0], winner_4[1])
node _T_170 = or(_T_168, _T_169)
node _T_171 = asUInt(reset)
node _T_172 = eq(_T_171, UInt<1>(0h0))
when _T_172 :
node _T_173 = eq(_T_170, UInt<1>(0h0))
when _T_173 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_15
assert(clock, _T_170, UInt<1>(0h1), "") : assert_15
node maskedBeats_0_4 = mux(winner_4[0], _T_155, UInt<1>(0h0))
node maskedBeats_1_4 = mux(winner_4[1], _T_156, UInt<1>(0h0))
node initBeats_4 = or(maskedBeats_0_4, maskedBeats_1_4)
node _beatsLeft_T_16 = and(x1_nodeOut_1.a.ready, x1_nodeOut_1.a.valid)
node _beatsLeft_T_17 = sub(beatsLeft_4, _beatsLeft_T_16)
node _beatsLeft_T_18 = tail(_beatsLeft_T_17, 1)
node _beatsLeft_T_19 = mux(latch_4, initBeats_4, _beatsLeft_T_18)
connect beatsLeft_4, _beatsLeft_T_19
wire _state_WIRE_4 : UInt<1>[2]
connect _state_WIRE_4[0], UInt<1>(0h0)
connect _state_WIRE_4[1], UInt<1>(0h0)
regreset state_4 : UInt<1>[2], clock, reset, _state_WIRE_4
node muxState_4 = mux(idle_4, winner_4, state_4)
connect state_4, muxState_4
node allowed_4 = mux(idle_4, readys_4, state_4)
node _c_a_ready_T_2 = and(x1_nodeOut_1.a.ready, allowed_4[0])
connect c_a_2.ready, _c_a_ready_T_2
node _a_a_ready_T_2 = and(x1_nodeOut_1.a.ready, allowed_4[1])
connect a_a_2.ready, _a_a_ready_T_2
node _nodeOut_a_valid_T_10 = or(c_a_2.valid, a_a_2.valid)
node _nodeOut_a_valid_T_11 = mux(state_4[0], c_a_2.valid, UInt<1>(0h0))
node _nodeOut_a_valid_T_12 = mux(state_4[1], a_a_2.valid, UInt<1>(0h0))
node _nodeOut_a_valid_T_13 = or(_nodeOut_a_valid_T_11, _nodeOut_a_valid_T_12)
wire _nodeOut_a_valid_WIRE_2 : UInt<1>
connect _nodeOut_a_valid_WIRE_2, _nodeOut_a_valid_T_13
node _nodeOut_a_valid_T_14 = mux(idle_4, _nodeOut_a_valid_T_10, _nodeOut_a_valid_WIRE_2)
connect x1_nodeOut_1.a.valid, _nodeOut_a_valid_T_14
wire _nodeOut_a_bits_WIRE_22 : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
node _nodeOut_a_bits_T_48 = mux(muxState_4[0], c_a_2.bits.corrupt, UInt<1>(0h0))
node _nodeOut_a_bits_T_49 = mux(muxState_4[1], a_a_2.bits.corrupt, UInt<1>(0h0))
node _nodeOut_a_bits_T_50 = or(_nodeOut_a_bits_T_48, _nodeOut_a_bits_T_49)
wire _nodeOut_a_bits_WIRE_23 : UInt<1>
connect _nodeOut_a_bits_WIRE_23, _nodeOut_a_bits_T_50
connect _nodeOut_a_bits_WIRE_22.corrupt, _nodeOut_a_bits_WIRE_23
node _nodeOut_a_bits_T_51 = mux(muxState_4[0], c_a_2.bits.data, UInt<1>(0h0))
node _nodeOut_a_bits_T_52 = mux(muxState_4[1], a_a_2.bits.data, UInt<1>(0h0))
node _nodeOut_a_bits_T_53 = or(_nodeOut_a_bits_T_51, _nodeOut_a_bits_T_52)
wire _nodeOut_a_bits_WIRE_24 : UInt<64>
connect _nodeOut_a_bits_WIRE_24, _nodeOut_a_bits_T_53
connect _nodeOut_a_bits_WIRE_22.data, _nodeOut_a_bits_WIRE_24
node _nodeOut_a_bits_T_54 = mux(muxState_4[0], c_a_2.bits.mask, UInt<1>(0h0))
node _nodeOut_a_bits_T_55 = mux(muxState_4[1], a_a_2.bits.mask, UInt<1>(0h0))
node _nodeOut_a_bits_T_56 = or(_nodeOut_a_bits_T_54, _nodeOut_a_bits_T_55)
wire _nodeOut_a_bits_WIRE_25 : UInt<8>
connect _nodeOut_a_bits_WIRE_25, _nodeOut_a_bits_T_56
connect _nodeOut_a_bits_WIRE_22.mask, _nodeOut_a_bits_WIRE_25
wire _nodeOut_a_bits_WIRE_26 : { }
connect _nodeOut_a_bits_WIRE_22.echo, _nodeOut_a_bits_WIRE_26
wire _nodeOut_a_bits_WIRE_27 : { }
connect _nodeOut_a_bits_WIRE_22.user, _nodeOut_a_bits_WIRE_27
node _nodeOut_a_bits_T_57 = mux(muxState_4[0], c_a_2.bits.address, UInt<1>(0h0))
node _nodeOut_a_bits_T_58 = mux(muxState_4[1], a_a_2.bits.address, UInt<1>(0h0))
node _nodeOut_a_bits_T_59 = or(_nodeOut_a_bits_T_57, _nodeOut_a_bits_T_58)
wire _nodeOut_a_bits_WIRE_28 : UInt<32>
connect _nodeOut_a_bits_WIRE_28, _nodeOut_a_bits_T_59
connect _nodeOut_a_bits_WIRE_22.address, _nodeOut_a_bits_WIRE_28
node _nodeOut_a_bits_T_60 = mux(muxState_4[0], c_a_2.bits.source, UInt<1>(0h0))
node _nodeOut_a_bits_T_61 = mux(muxState_4[1], a_a_2.bits.source, UInt<1>(0h0))
node _nodeOut_a_bits_T_62 = or(_nodeOut_a_bits_T_60, _nodeOut_a_bits_T_61)
wire _nodeOut_a_bits_WIRE_29 : UInt<5>
connect _nodeOut_a_bits_WIRE_29, _nodeOut_a_bits_T_62
connect _nodeOut_a_bits_WIRE_22.source, _nodeOut_a_bits_WIRE_29
node _nodeOut_a_bits_T_63 = mux(muxState_4[0], c_a_2.bits.size, UInt<1>(0h0))
node _nodeOut_a_bits_T_64 = mux(muxState_4[1], a_a_2.bits.size, UInt<1>(0h0))
node _nodeOut_a_bits_T_65 = or(_nodeOut_a_bits_T_63, _nodeOut_a_bits_T_64)
wire _nodeOut_a_bits_WIRE_30 : UInt<3>
connect _nodeOut_a_bits_WIRE_30, _nodeOut_a_bits_T_65
connect _nodeOut_a_bits_WIRE_22.size, _nodeOut_a_bits_WIRE_30
node _nodeOut_a_bits_T_66 = mux(muxState_4[0], c_a_2.bits.param, UInt<1>(0h0))
node _nodeOut_a_bits_T_67 = mux(muxState_4[1], a_a_2.bits.param, UInt<1>(0h0))
node _nodeOut_a_bits_T_68 = or(_nodeOut_a_bits_T_66, _nodeOut_a_bits_T_67)
wire _nodeOut_a_bits_WIRE_31 : UInt<3>
connect _nodeOut_a_bits_WIRE_31, _nodeOut_a_bits_T_68
connect _nodeOut_a_bits_WIRE_22.param, _nodeOut_a_bits_WIRE_31
node _nodeOut_a_bits_T_69 = mux(muxState_4[0], c_a_2.bits.opcode, UInt<1>(0h0))
node _nodeOut_a_bits_T_70 = mux(muxState_4[1], a_a_2.bits.opcode, UInt<1>(0h0))
node _nodeOut_a_bits_T_71 = or(_nodeOut_a_bits_T_69, _nodeOut_a_bits_T_70)
wire _nodeOut_a_bits_WIRE_32 : UInt<3>
connect _nodeOut_a_bits_WIRE_32, _nodeOut_a_bits_T_71
connect _nodeOut_a_bits_WIRE_22.opcode, _nodeOut_a_bits_WIRE_32
connect x1_nodeOut_1.a.bits.corrupt, _nodeOut_a_bits_WIRE_22.corrupt
connect x1_nodeOut_1.a.bits.data, _nodeOut_a_bits_WIRE_22.data
connect x1_nodeOut_1.a.bits.mask, _nodeOut_a_bits_WIRE_22.mask
connect x1_nodeOut_1.a.bits.address, _nodeOut_a_bits_WIRE_22.address
connect x1_nodeOut_1.a.bits.source, _nodeOut_a_bits_WIRE_22.source
connect x1_nodeOut_1.a.bits.size, _nodeOut_a_bits_WIRE_22.size
connect x1_nodeOut_1.a.bits.param, _nodeOut_a_bits_WIRE_22.param
connect x1_nodeOut_1.a.bits.opcode, _nodeOut_a_bits_WIRE_22.opcode
node _decode_T_24 = dshl(UInt<6>(0h3f), d_d_2.bits.size)
node _decode_T_25 = bits(_decode_T_24, 5, 0)
node _decode_T_26 = not(_decode_T_25)
node decode_8 = shr(_decode_T_26, 3)
node opdata_8 = bits(d_d_2.bits.opcode, 0, 0)
node _T_174 = mux(opdata_8, decode_8, UInt<1>(0h0))
inst q_4 of Queue2_TLBundleD_a32d64s4k3z3c_8
connect q_4.clock, clock
connect q_4.reset, reset
connect q_4.io.enq.valid, c_d_2.valid
connect q_4.io.enq.bits.corrupt, c_d_2.bits.corrupt
connect q_4.io.enq.bits.data, c_d_2.bits.data
connect q_4.io.enq.bits.denied, c_d_2.bits.denied
connect q_4.io.enq.bits.sink, c_d_2.bits.sink
connect q_4.io.enq.bits.source, c_d_2.bits.source
connect q_4.io.enq.bits.size, c_d_2.bits.size
connect q_4.io.enq.bits.param, c_d_2.bits.param
connect q_4.io.enq.bits.opcode, c_d_2.bits.opcode
connect c_d_2.ready, q_4.io.enq.ready
inst q_5 of Queue2_TLBundleD_a32d64s4k3z3c_9
connect q_5.clock, clock
connect q_5.reset, reset
connect q_5.io.enq.valid, a_d_2.valid
connect q_5.io.enq.bits.corrupt, a_d_2.bits.corrupt
connect q_5.io.enq.bits.data, a_d_2.bits.data
connect q_5.io.enq.bits.denied, a_d_2.bits.denied
connect q_5.io.enq.bits.sink, a_d_2.bits.sink
connect q_5.io.enq.bits.source, a_d_2.bits.source
connect q_5.io.enq.bits.size, a_d_2.bits.size
connect q_5.io.enq.bits.param, a_d_2.bits.param
connect q_5.io.enq.bits.opcode, a_d_2.bits.opcode
connect a_d_2.ready, q_5.io.enq.ready
regreset beatsLeft_5 : UInt, clock, reset, UInt<1>(0h0)
node idle_5 = eq(beatsLeft_5, UInt<1>(0h0))
node latch_5 = and(idle_5, in_d_2.ready)
node readys_hi_2 = cat(q_5.io.deq.valid, q_4.io.deq.valid)
node _readys_T_58 = cat(readys_hi_2, d_d_2.valid)
node _readys_T_59 = shl(_readys_T_58, 1)
node _readys_T_60 = bits(_readys_T_59, 2, 0)
node _readys_T_61 = or(_readys_T_58, _readys_T_60)
node _readys_T_62 = shl(_readys_T_61, 2)
node _readys_T_63 = bits(_readys_T_62, 2, 0)
node _readys_T_64 = or(_readys_T_61, _readys_T_63)
node _readys_T_65 = bits(_readys_T_64, 2, 0)
node _readys_T_66 = shl(_readys_T_65, 1)
node _readys_T_67 = bits(_readys_T_66, 2, 0)
node _readys_T_68 = not(_readys_T_67)
node _readys_T_69 = bits(_readys_T_68, 0, 0)
node _readys_T_70 = bits(_readys_T_68, 1, 1)
node _readys_T_71 = bits(_readys_T_68, 2, 2)
wire readys_5 : UInt<1>[3]
connect readys_5[0], _readys_T_69
connect readys_5[1], _readys_T_70
connect readys_5[2], _readys_T_71
node _winner_T_12 = and(readys_5[0], d_d_2.valid)
node _winner_T_13 = and(readys_5[1], q_4.io.deq.valid)
node _winner_T_14 = and(readys_5[2], q_5.io.deq.valid)
wire winner_5 : UInt<1>[3]
connect winner_5[0], _winner_T_12
connect winner_5[1], _winner_T_13
connect winner_5[2], _winner_T_14
node prefixOR_1_5 = or(UInt<1>(0h0), winner_5[0])
node prefixOR_2_2 = or(prefixOR_1_5, winner_5[1])
node _prefixOR_T_5 = or(prefixOR_2_2, winner_5[2])
node _T_175 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_176 = eq(winner_5[0], UInt<1>(0h0))
node _T_177 = or(_T_175, _T_176)
node _T_178 = eq(prefixOR_1_5, UInt<1>(0h0))
node _T_179 = eq(winner_5[1], UInt<1>(0h0))
node _T_180 = or(_T_178, _T_179)
node _T_181 = eq(prefixOR_2_2, UInt<1>(0h0))
node _T_182 = eq(winner_5[2], UInt<1>(0h0))
node _T_183 = or(_T_181, _T_182)
node _T_184 = and(_T_177, _T_180)
node _T_185 = and(_T_184, _T_183)
node _T_186 = asUInt(reset)
node _T_187 = eq(_T_186, UInt<1>(0h0))
when _T_187 :
node _T_188 = eq(_T_185, UInt<1>(0h0))
when _T_188 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_16
assert(clock, _T_185, UInt<1>(0h1), "") : assert_16
node _T_189 = or(d_d_2.valid, q_4.io.deq.valid)
node _T_190 = or(_T_189, q_5.io.deq.valid)
node _T_191 = eq(_T_190, UInt<1>(0h0))
node _T_192 = or(winner_5[0], winner_5[1])
node _T_193 = or(_T_192, winner_5[2])
node _T_194 = or(_T_191, _T_193)
node _T_195 = asUInt(reset)
node _T_196 = eq(_T_195, UInt<1>(0h0))
when _T_196 :
node _T_197 = eq(_T_194, UInt<1>(0h0))
when _T_197 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_17
assert(clock, _T_194, UInt<1>(0h1), "") : assert_17
node maskedBeats_0_5 = mux(winner_5[0], _T_174, UInt<1>(0h0))
node maskedBeats_1_5 = mux(winner_5[1], UInt<1>(0h0), UInt<1>(0h0))
node maskedBeats_2_2 = mux(winner_5[2], UInt<1>(0h0), UInt<1>(0h0))
node _initBeats_T_2 = or(maskedBeats_0_5, maskedBeats_1_5)
node initBeats_5 = or(_initBeats_T_2, maskedBeats_2_2)
node _beatsLeft_T_20 = and(in_d_2.ready, in_d_2.valid)
node _beatsLeft_T_21 = sub(beatsLeft_5, _beatsLeft_T_20)
node _beatsLeft_T_22 = tail(_beatsLeft_T_21, 1)
node _beatsLeft_T_23 = mux(latch_5, initBeats_5, _beatsLeft_T_22)
connect beatsLeft_5, _beatsLeft_T_23
wire _state_WIRE_5 : UInt<1>[3]
connect _state_WIRE_5[0], UInt<1>(0h0)
connect _state_WIRE_5[1], UInt<1>(0h0)
connect _state_WIRE_5[2], UInt<1>(0h0)
regreset state_5 : UInt<1>[3], clock, reset, _state_WIRE_5
node muxState_5 = mux(idle_5, winner_5, state_5)
connect state_5, muxState_5
node allowed_5 = mux(idle_5, readys_5, state_5)
node _d_d_ready_T_2 = and(in_d_2.ready, allowed_5[0])
connect d_d_2.ready, _d_d_ready_T_2
node _q_io_deq_ready_T_4 = and(in_d_2.ready, allowed_5[1])
connect q_4.io.deq.ready, _q_io_deq_ready_T_4
node _q_io_deq_ready_T_5 = and(in_d_2.ready, allowed_5[2])
connect q_5.io.deq.ready, _q_io_deq_ready_T_5
node _in_d_valid_T_16 = or(d_d_2.valid, q_4.io.deq.valid)
node _in_d_valid_T_17 = or(_in_d_valid_T_16, q_5.io.deq.valid)
node _in_d_valid_T_18 = mux(state_5[0], d_d_2.valid, UInt<1>(0h0))
node _in_d_valid_T_19 = mux(state_5[1], q_4.io.deq.valid, UInt<1>(0h0))
node _in_d_valid_T_20 = mux(state_5[2], q_5.io.deq.valid, UInt<1>(0h0))
node _in_d_valid_T_21 = or(_in_d_valid_T_18, _in_d_valid_T_19)
node _in_d_valid_T_22 = or(_in_d_valid_T_21, _in_d_valid_T_20)
wire _in_d_valid_WIRE_2 : UInt<1>
connect _in_d_valid_WIRE_2, _in_d_valid_T_22
node _in_d_valid_T_23 = mux(idle_5, _in_d_valid_T_17, _in_d_valid_WIRE_2)
connect in_d_2.valid, _in_d_valid_T_23
wire _in_d_bits_WIRE_22 : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
node _in_d_bits_T_80 = mux(muxState_5[0], d_d_2.bits.corrupt, UInt<1>(0h0))
node _in_d_bits_T_81 = mux(muxState_5[1], q_4.io.deq.bits.corrupt, UInt<1>(0h0))
node _in_d_bits_T_82 = mux(muxState_5[2], q_5.io.deq.bits.corrupt, UInt<1>(0h0))
node _in_d_bits_T_83 = or(_in_d_bits_T_80, _in_d_bits_T_81)
node _in_d_bits_T_84 = or(_in_d_bits_T_83, _in_d_bits_T_82)
wire _in_d_bits_WIRE_23 : UInt<1>
connect _in_d_bits_WIRE_23, _in_d_bits_T_84
connect _in_d_bits_WIRE_22.corrupt, _in_d_bits_WIRE_23
node _in_d_bits_T_85 = mux(muxState_5[0], d_d_2.bits.data, UInt<1>(0h0))
node _in_d_bits_T_86 = mux(muxState_5[1], q_4.io.deq.bits.data, UInt<1>(0h0))
node _in_d_bits_T_87 = mux(muxState_5[2], q_5.io.deq.bits.data, UInt<1>(0h0))
node _in_d_bits_T_88 = or(_in_d_bits_T_85, _in_d_bits_T_86)
node _in_d_bits_T_89 = or(_in_d_bits_T_88, _in_d_bits_T_87)
wire _in_d_bits_WIRE_24 : UInt<64>
connect _in_d_bits_WIRE_24, _in_d_bits_T_89
connect _in_d_bits_WIRE_22.data, _in_d_bits_WIRE_24
wire _in_d_bits_WIRE_25 : { }
connect _in_d_bits_WIRE_22.echo, _in_d_bits_WIRE_25
wire _in_d_bits_WIRE_26 : { }
connect _in_d_bits_WIRE_22.user, _in_d_bits_WIRE_26
node _in_d_bits_T_90 = mux(muxState_5[0], d_d_2.bits.denied, UInt<1>(0h0))
node _in_d_bits_T_91 = mux(muxState_5[1], q_4.io.deq.bits.denied, UInt<1>(0h0))
node _in_d_bits_T_92 = mux(muxState_5[2], q_5.io.deq.bits.denied, UInt<1>(0h0))
node _in_d_bits_T_93 = or(_in_d_bits_T_90, _in_d_bits_T_91)
node _in_d_bits_T_94 = or(_in_d_bits_T_93, _in_d_bits_T_92)
wire _in_d_bits_WIRE_27 : UInt<1>
connect _in_d_bits_WIRE_27, _in_d_bits_T_94
connect _in_d_bits_WIRE_22.denied, _in_d_bits_WIRE_27
node _in_d_bits_T_95 = mux(muxState_5[0], d_d_2.bits.sink, UInt<1>(0h0))
node _in_d_bits_T_96 = mux(muxState_5[1], q_4.io.deq.bits.sink, UInt<1>(0h0))
node _in_d_bits_T_97 = mux(muxState_5[2], q_5.io.deq.bits.sink, UInt<1>(0h0))
node _in_d_bits_T_98 = or(_in_d_bits_T_95, _in_d_bits_T_96)
node _in_d_bits_T_99 = or(_in_d_bits_T_98, _in_d_bits_T_97)
wire _in_d_bits_WIRE_28 : UInt<3>
connect _in_d_bits_WIRE_28, _in_d_bits_T_99
connect _in_d_bits_WIRE_22.sink, _in_d_bits_WIRE_28
node _in_d_bits_T_100 = mux(muxState_5[0], d_d_2.bits.source, UInt<1>(0h0))
node _in_d_bits_T_101 = mux(muxState_5[1], q_4.io.deq.bits.source, UInt<1>(0h0))
node _in_d_bits_T_102 = mux(muxState_5[2], q_5.io.deq.bits.source, UInt<1>(0h0))
node _in_d_bits_T_103 = or(_in_d_bits_T_100, _in_d_bits_T_101)
node _in_d_bits_T_104 = or(_in_d_bits_T_103, _in_d_bits_T_102)
wire _in_d_bits_WIRE_29 : UInt<4>
connect _in_d_bits_WIRE_29, _in_d_bits_T_104
connect _in_d_bits_WIRE_22.source, _in_d_bits_WIRE_29
node _in_d_bits_T_105 = mux(muxState_5[0], d_d_2.bits.size, UInt<1>(0h0))
node _in_d_bits_T_106 = mux(muxState_5[1], q_4.io.deq.bits.size, UInt<1>(0h0))
node _in_d_bits_T_107 = mux(muxState_5[2], q_5.io.deq.bits.size, UInt<1>(0h0))
node _in_d_bits_T_108 = or(_in_d_bits_T_105, _in_d_bits_T_106)
node _in_d_bits_T_109 = or(_in_d_bits_T_108, _in_d_bits_T_107)
wire _in_d_bits_WIRE_30 : UInt<3>
connect _in_d_bits_WIRE_30, _in_d_bits_T_109
connect _in_d_bits_WIRE_22.size, _in_d_bits_WIRE_30
node _in_d_bits_T_110 = mux(muxState_5[0], d_d_2.bits.param, UInt<1>(0h0))
node _in_d_bits_T_111 = mux(muxState_5[1], q_4.io.deq.bits.param, UInt<1>(0h0))
node _in_d_bits_T_112 = mux(muxState_5[2], q_5.io.deq.bits.param, UInt<1>(0h0))
node _in_d_bits_T_113 = or(_in_d_bits_T_110, _in_d_bits_T_111)
node _in_d_bits_T_114 = or(_in_d_bits_T_113, _in_d_bits_T_112)
wire _in_d_bits_WIRE_31 : UInt<2>
connect _in_d_bits_WIRE_31, _in_d_bits_T_114
connect _in_d_bits_WIRE_22.param, _in_d_bits_WIRE_31
node _in_d_bits_T_115 = mux(muxState_5[0], d_d_2.bits.opcode, UInt<1>(0h0))
node _in_d_bits_T_116 = mux(muxState_5[1], q_4.io.deq.bits.opcode, UInt<1>(0h0))
node _in_d_bits_T_117 = mux(muxState_5[2], q_5.io.deq.bits.opcode, UInt<1>(0h0))
node _in_d_bits_T_118 = or(_in_d_bits_T_115, _in_d_bits_T_116)
node _in_d_bits_T_119 = or(_in_d_bits_T_118, _in_d_bits_T_117)
wire _in_d_bits_WIRE_32 : UInt<3>
connect _in_d_bits_WIRE_32, _in_d_bits_T_119
connect _in_d_bits_WIRE_22.opcode, _in_d_bits_WIRE_32
connect in_d_2.bits.corrupt, _in_d_bits_WIRE_22.corrupt
connect in_d_2.bits.data, _in_d_bits_WIRE_22.data
connect in_d_2.bits.denied, _in_d_bits_WIRE_22.denied
connect in_d_2.bits.sink, _in_d_bits_WIRE_22.sink
connect in_d_2.bits.source, _in_d_bits_WIRE_22.source
connect in_d_2.bits.size, _in_d_bits_WIRE_22.size
connect in_d_2.bits.param, _in_d_bits_WIRE_22.param
connect in_d_2.bits.opcode, _in_d_bits_WIRE_22.opcode
connect nodeIn_2.b.valid, UInt<1>(0h0)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<32>(0h0)
connect _WIRE_20.bits.source, UInt<5>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
connect _WIRE_21.valid, UInt<1>(0h0)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_22.bits.sink, UInt<1>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
connect _WIRE_23.valid, UInt<1>(0h0)
wire a_a_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
wire a_d_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
node _isPut_T_6 = eq(nodeIn_3.a.bits.opcode, UInt<1>(0h0))
node _isPut_T_7 = eq(nodeIn_3.a.bits.opcode, UInt<1>(0h1))
node isPut_3 = or(_isPut_T_6, _isPut_T_7)
node _toD_T_12 = eq(nodeIn_3.a.bits.opcode, UInt<3>(0h6))
node _toD_T_13 = eq(nodeIn_3.a.bits.param, UInt<2>(0h2))
node _toD_T_14 = and(_toD_T_12, _toD_T_13)
node _toD_T_15 = eq(nodeIn_3.a.bits.opcode, UInt<3>(0h7))
node toD_3 = or(_toD_T_14, _toD_T_15)
node _nodeIn_a_ready_T_3 = mux(toD_3, a_d_3.ready, a_a_3.ready)
connect nodeIn_3.a.ready, _nodeIn_a_ready_T_3
node _a_a_valid_T_6 = eq(toD_3, UInt<1>(0h0))
node _a_a_valid_T_7 = and(nodeIn_3.a.valid, _a_a_valid_T_6)
connect a_a_3.valid, _a_a_valid_T_7
connect a_a_3.bits, nodeIn_3.a.bits
node _a_a_bits_source_T_15 = shl(nodeIn_3.a.bits.source, 1)
node _a_a_bits_source_T_16 = mux(isPut_3, UInt<1>(0h1), UInt<1>(0h0))
node _a_a_bits_source_T_17 = or(_a_a_bits_source_T_15, _a_a_bits_source_T_16)
connect a_a_3.bits.source, _a_a_bits_source_T_17
node _T_198 = eq(nodeIn_3.a.bits.opcode, UInt<3>(0h6))
node _T_199 = eq(nodeIn_3.a.bits.opcode, UInt<3>(0h7))
node _T_200 = or(_T_198, _T_199)
when _T_200 :
connect a_a_3.bits.opcode, UInt<3>(0h4)
connect a_a_3.bits.param, UInt<1>(0h0)
node _a_a_bits_source_T_18 = shl(nodeIn_3.a.bits.source, 1)
node _a_a_bits_source_T_19 = or(_a_a_bits_source_T_18, UInt<1>(0h1))
connect a_a_3.bits.source, _a_a_bits_source_T_19
node _a_d_valid_T_3 = and(nodeIn_3.a.valid, toD_3)
connect a_d_3.valid, _a_d_valid_T_3
wire a_d_bits_d_3 : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
connect a_d_bits_d_3.opcode, UInt<3>(0h4)
connect a_d_bits_d_3.param, UInt<2>(0h0)
connect a_d_bits_d_3.size, nodeIn_3.a.bits.size
connect a_d_bits_d_3.source, nodeIn_3.a.bits.source
connect a_d_bits_d_3.sink, UInt<1>(0h0)
connect a_d_bits_d_3.denied, UInt<1>(0h0)
invalidate a_d_bits_d_3.data
connect a_d_bits_d_3.corrupt, UInt<1>(0h0)
connect a_d_3.bits.corrupt, a_d_bits_d_3.corrupt
connect a_d_3.bits.data, a_d_bits_d_3.data
connect a_d_3.bits.denied, a_d_bits_d_3.denied
connect a_d_3.bits.sink, a_d_bits_d_3.sink
connect a_d_3.bits.source, a_d_bits_d_3.source
connect a_d_3.bits.size, a_d_bits_d_3.size
connect a_d_3.bits.param, a_d_bits_d_3.param
connect a_d_3.bits.opcode, a_d_bits_d_3.opcode
wire c_a_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
node _c_a_valid_T_6 = eq(nodeIn_3.c.bits.opcode, UInt<3>(0h7))
node _c_a_valid_T_7 = and(nodeIn_3.c.valid, _c_a_valid_T_6)
connect c_a_3.valid, _c_a_valid_T_7
node _c_a_bits_T_3 = shl(nodeIn_3.c.bits.source, 1)
node _c_a_bits_legal_T_30 = leq(UInt<1>(0h0), nodeIn_3.c.bits.size)
node _c_a_bits_legal_T_31 = leq(nodeIn_3.c.bits.size, UInt<3>(0h6))
node _c_a_bits_legal_T_32 = and(_c_a_bits_legal_T_30, _c_a_bits_legal_T_31)
node _c_a_bits_legal_T_33 = or(UInt<1>(0h0), _c_a_bits_legal_T_32)
node _c_a_bits_legal_T_34 = xor(nodeIn_3.c.bits.address, UInt<1>(0h0))
node _c_a_bits_legal_T_35 = cvt(_c_a_bits_legal_T_34)
node _c_a_bits_legal_T_36 = and(_c_a_bits_legal_T_35, asSInt(UInt<1>(0h0)))
node _c_a_bits_legal_T_37 = asSInt(_c_a_bits_legal_T_36)
node _c_a_bits_legal_T_38 = eq(_c_a_bits_legal_T_37, asSInt(UInt<1>(0h0)))
node _c_a_bits_legal_T_39 = and(_c_a_bits_legal_T_33, _c_a_bits_legal_T_38)
node c_a_bits_legal_3 = or(UInt<1>(0h0), _c_a_bits_legal_T_39)
wire c_a_bits_a_3 : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect c_a_bits_a_3.opcode, UInt<1>(0h0)
connect c_a_bits_a_3.param, UInt<1>(0h0)
connect c_a_bits_a_3.size, nodeIn_3.c.bits.size
connect c_a_bits_a_3.source, _c_a_bits_T_3
connect c_a_bits_a_3.address, nodeIn_3.c.bits.address
node _c_a_bits_a_mask_sizeOH_T_9 = or(nodeIn_3.c.bits.size, UInt<3>(0h0))
node c_a_bits_a_mask_sizeOH_shiftAmount_3 = bits(_c_a_bits_a_mask_sizeOH_T_9, 1, 0)
node _c_a_bits_a_mask_sizeOH_T_10 = dshl(UInt<1>(0h1), c_a_bits_a_mask_sizeOH_shiftAmount_3)
node _c_a_bits_a_mask_sizeOH_T_11 = bits(_c_a_bits_a_mask_sizeOH_T_10, 2, 0)
node c_a_bits_a_mask_sizeOH_3 = or(_c_a_bits_a_mask_sizeOH_T_11, UInt<1>(0h1))
node c_a_bits_a_mask_sub_sub_sub_0_1_3 = geq(nodeIn_3.c.bits.size, UInt<2>(0h3))
node c_a_bits_a_mask_sub_sub_size_3 = bits(c_a_bits_a_mask_sizeOH_3, 2, 2)
node c_a_bits_a_mask_sub_sub_bit_3 = bits(nodeIn_3.c.bits.address, 2, 2)
node c_a_bits_a_mask_sub_sub_nbit_3 = eq(c_a_bits_a_mask_sub_sub_bit_3, UInt<1>(0h0))
node c_a_bits_a_mask_sub_sub_0_2_3 = and(UInt<1>(0h1), c_a_bits_a_mask_sub_sub_nbit_3)
node _c_a_bits_a_mask_sub_sub_acc_T_6 = and(c_a_bits_a_mask_sub_sub_size_3, c_a_bits_a_mask_sub_sub_0_2_3)
node c_a_bits_a_mask_sub_sub_0_1_3 = or(c_a_bits_a_mask_sub_sub_sub_0_1_3, _c_a_bits_a_mask_sub_sub_acc_T_6)
node c_a_bits_a_mask_sub_sub_1_2_3 = and(UInt<1>(0h1), c_a_bits_a_mask_sub_sub_bit_3)
node _c_a_bits_a_mask_sub_sub_acc_T_7 = and(c_a_bits_a_mask_sub_sub_size_3, c_a_bits_a_mask_sub_sub_1_2_3)
node c_a_bits_a_mask_sub_sub_1_1_3 = or(c_a_bits_a_mask_sub_sub_sub_0_1_3, _c_a_bits_a_mask_sub_sub_acc_T_7)
node c_a_bits_a_mask_sub_size_3 = bits(c_a_bits_a_mask_sizeOH_3, 1, 1)
node c_a_bits_a_mask_sub_bit_3 = bits(nodeIn_3.c.bits.address, 1, 1)
node c_a_bits_a_mask_sub_nbit_3 = eq(c_a_bits_a_mask_sub_bit_3, UInt<1>(0h0))
node c_a_bits_a_mask_sub_0_2_3 = and(c_a_bits_a_mask_sub_sub_0_2_3, c_a_bits_a_mask_sub_nbit_3)
node _c_a_bits_a_mask_sub_acc_T_12 = and(c_a_bits_a_mask_sub_size_3, c_a_bits_a_mask_sub_0_2_3)
node c_a_bits_a_mask_sub_0_1_3 = or(c_a_bits_a_mask_sub_sub_0_1_3, _c_a_bits_a_mask_sub_acc_T_12)
node c_a_bits_a_mask_sub_1_2_3 = and(c_a_bits_a_mask_sub_sub_0_2_3, c_a_bits_a_mask_sub_bit_3)
node _c_a_bits_a_mask_sub_acc_T_13 = and(c_a_bits_a_mask_sub_size_3, c_a_bits_a_mask_sub_1_2_3)
node c_a_bits_a_mask_sub_1_1_3 = or(c_a_bits_a_mask_sub_sub_0_1_3, _c_a_bits_a_mask_sub_acc_T_13)
node c_a_bits_a_mask_sub_2_2_3 = and(c_a_bits_a_mask_sub_sub_1_2_3, c_a_bits_a_mask_sub_nbit_3)
node _c_a_bits_a_mask_sub_acc_T_14 = and(c_a_bits_a_mask_sub_size_3, c_a_bits_a_mask_sub_2_2_3)
node c_a_bits_a_mask_sub_2_1_3 = or(c_a_bits_a_mask_sub_sub_1_1_3, _c_a_bits_a_mask_sub_acc_T_14)
node c_a_bits_a_mask_sub_3_2_3 = and(c_a_bits_a_mask_sub_sub_1_2_3, c_a_bits_a_mask_sub_bit_3)
node _c_a_bits_a_mask_sub_acc_T_15 = and(c_a_bits_a_mask_sub_size_3, c_a_bits_a_mask_sub_3_2_3)
node c_a_bits_a_mask_sub_3_1_3 = or(c_a_bits_a_mask_sub_sub_1_1_3, _c_a_bits_a_mask_sub_acc_T_15)
node c_a_bits_a_mask_size_3 = bits(c_a_bits_a_mask_sizeOH_3, 0, 0)
node c_a_bits_a_mask_bit_3 = bits(nodeIn_3.c.bits.address, 0, 0)
node c_a_bits_a_mask_nbit_3 = eq(c_a_bits_a_mask_bit_3, UInt<1>(0h0))
node c_a_bits_a_mask_eq_24 = and(c_a_bits_a_mask_sub_0_2_3, c_a_bits_a_mask_nbit_3)
node _c_a_bits_a_mask_acc_T_24 = and(c_a_bits_a_mask_size_3, c_a_bits_a_mask_eq_24)
node c_a_bits_a_mask_acc_24 = or(c_a_bits_a_mask_sub_0_1_3, _c_a_bits_a_mask_acc_T_24)
node c_a_bits_a_mask_eq_25 = and(c_a_bits_a_mask_sub_0_2_3, c_a_bits_a_mask_bit_3)
node _c_a_bits_a_mask_acc_T_25 = and(c_a_bits_a_mask_size_3, c_a_bits_a_mask_eq_25)
node c_a_bits_a_mask_acc_25 = or(c_a_bits_a_mask_sub_0_1_3, _c_a_bits_a_mask_acc_T_25)
node c_a_bits_a_mask_eq_26 = and(c_a_bits_a_mask_sub_1_2_3, c_a_bits_a_mask_nbit_3)
node _c_a_bits_a_mask_acc_T_26 = and(c_a_bits_a_mask_size_3, c_a_bits_a_mask_eq_26)
node c_a_bits_a_mask_acc_26 = or(c_a_bits_a_mask_sub_1_1_3, _c_a_bits_a_mask_acc_T_26)
node c_a_bits_a_mask_eq_27 = and(c_a_bits_a_mask_sub_1_2_3, c_a_bits_a_mask_bit_3)
node _c_a_bits_a_mask_acc_T_27 = and(c_a_bits_a_mask_size_3, c_a_bits_a_mask_eq_27)
node c_a_bits_a_mask_acc_27 = or(c_a_bits_a_mask_sub_1_1_3, _c_a_bits_a_mask_acc_T_27)
node c_a_bits_a_mask_eq_28 = and(c_a_bits_a_mask_sub_2_2_3, c_a_bits_a_mask_nbit_3)
node _c_a_bits_a_mask_acc_T_28 = and(c_a_bits_a_mask_size_3, c_a_bits_a_mask_eq_28)
node c_a_bits_a_mask_acc_28 = or(c_a_bits_a_mask_sub_2_1_3, _c_a_bits_a_mask_acc_T_28)
node c_a_bits_a_mask_eq_29 = and(c_a_bits_a_mask_sub_2_2_3, c_a_bits_a_mask_bit_3)
node _c_a_bits_a_mask_acc_T_29 = and(c_a_bits_a_mask_size_3, c_a_bits_a_mask_eq_29)
node c_a_bits_a_mask_acc_29 = or(c_a_bits_a_mask_sub_2_1_3, _c_a_bits_a_mask_acc_T_29)
node c_a_bits_a_mask_eq_30 = and(c_a_bits_a_mask_sub_3_2_3, c_a_bits_a_mask_nbit_3)
node _c_a_bits_a_mask_acc_T_30 = and(c_a_bits_a_mask_size_3, c_a_bits_a_mask_eq_30)
node c_a_bits_a_mask_acc_30 = or(c_a_bits_a_mask_sub_3_1_3, _c_a_bits_a_mask_acc_T_30)
node c_a_bits_a_mask_eq_31 = and(c_a_bits_a_mask_sub_3_2_3, c_a_bits_a_mask_bit_3)
node _c_a_bits_a_mask_acc_T_31 = and(c_a_bits_a_mask_size_3, c_a_bits_a_mask_eq_31)
node c_a_bits_a_mask_acc_31 = or(c_a_bits_a_mask_sub_3_1_3, _c_a_bits_a_mask_acc_T_31)
node c_a_bits_a_mask_lo_lo_3 = cat(c_a_bits_a_mask_acc_25, c_a_bits_a_mask_acc_24)
node c_a_bits_a_mask_lo_hi_3 = cat(c_a_bits_a_mask_acc_27, c_a_bits_a_mask_acc_26)
node c_a_bits_a_mask_lo_3 = cat(c_a_bits_a_mask_lo_hi_3, c_a_bits_a_mask_lo_lo_3)
node c_a_bits_a_mask_hi_lo_3 = cat(c_a_bits_a_mask_acc_29, c_a_bits_a_mask_acc_28)
node c_a_bits_a_mask_hi_hi_3 = cat(c_a_bits_a_mask_acc_31, c_a_bits_a_mask_acc_30)
node c_a_bits_a_mask_hi_3 = cat(c_a_bits_a_mask_hi_hi_3, c_a_bits_a_mask_hi_lo_3)
node _c_a_bits_a_mask_T_3 = cat(c_a_bits_a_mask_hi_3, c_a_bits_a_mask_lo_3)
connect c_a_bits_a_3.mask, _c_a_bits_a_mask_T_3
connect c_a_bits_a_3.data, nodeIn_3.c.bits.data
connect c_a_bits_a_3.corrupt, nodeIn_3.c.bits.corrupt
connect c_a_3.bits, c_a_bits_a_3
wire c_d_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
node _c_d_valid_T_6 = eq(nodeIn_3.c.bits.opcode, UInt<3>(0h6))
node _c_d_valid_T_7 = and(nodeIn_3.c.valid, _c_d_valid_T_6)
connect c_d_3.valid, _c_d_valid_T_7
wire c_d_bits_d_3 : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
connect c_d_bits_d_3.opcode, UInt<3>(0h6)
connect c_d_bits_d_3.param, UInt<1>(0h0)
connect c_d_bits_d_3.size, nodeIn_3.c.bits.size
connect c_d_bits_d_3.source, nodeIn_3.c.bits.source
connect c_d_bits_d_3.sink, UInt<1>(0h0)
connect c_d_bits_d_3.denied, UInt<1>(0h0)
invalidate c_d_bits_d_3.data
connect c_d_bits_d_3.corrupt, UInt<1>(0h0)
connect c_d_3.bits.corrupt, c_d_bits_d_3.corrupt
connect c_d_3.bits.data, c_d_bits_d_3.data
connect c_d_3.bits.denied, c_d_bits_d_3.denied
connect c_d_3.bits.sink, c_d_bits_d_3.sink
connect c_d_3.bits.source, c_d_bits_d_3.source
connect c_d_3.bits.size, c_d_bits_d_3.size
connect c_d_3.bits.param, c_d_bits_d_3.param
connect c_d_3.bits.opcode, c_d_bits_d_3.opcode
node _T_201 = eq(nodeIn_3.c.valid, UInt<1>(0h0))
node _T_202 = eq(nodeIn_3.c.bits.opcode, UInt<3>(0h6))
node _T_203 = or(_T_201, _T_202)
node _T_204 = eq(nodeIn_3.c.bits.opcode, UInt<3>(0h7))
node _T_205 = or(_T_203, _T_204)
node _T_206 = asUInt(reset)
node _T_207 = eq(_T_206, UInt<1>(0h0))
when _T_207 :
node _T_208 = eq(_T_205, UInt<1>(0h0))
when _T_208 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at CacheCork.scala:116 assert (!in.c.valid || in.c.bits.opcode === Release || in.c.bits.opcode === ReleaseData)\n") : printf_18
assert(clock, _T_205, UInt<1>(0h1), "") : assert_18
node _nodeIn_c_ready_T_6 = eq(nodeIn_3.c.bits.opcode, UInt<3>(0h6))
node _nodeIn_c_ready_T_7 = mux(_nodeIn_c_ready_T_6, c_d_3.ready, c_a_3.ready)
connect nodeIn_3.c.ready, _nodeIn_c_ready_T_7
connect nodeIn_3.e.ready, UInt<1>(0h1)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.mask, UInt<8>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<5>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<2>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
connect _WIRE_25.ready, UInt<1>(0h0)
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.mask, UInt<8>(0h0)
connect _WIRE_26.bits.address, UInt<32>(0h0)
connect _WIRE_26.bits.source, UInt<5>(0h0)
connect _WIRE_26.bits.size, UInt<3>(0h0)
connect _WIRE_26.bits.param, UInt<2>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
node _T_209 = eq(_WIRE_27.valid, UInt<1>(0h0))
node _T_210 = asUInt(reset)
node _T_211 = eq(_T_210, UInt<1>(0h0))
when _T_211 :
node _T_212 = eq(_T_209, UInt<1>(0h0))
when _T_212 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at CacheCork.scala:124 assert (!out.b.valid)\n") : printf_19
assert(clock, _T_209, UInt<1>(0h1), "") : assert_19
inst pool_3 of IDPool_3
connect pool_3.clock, clock
connect pool_3.reset, reset
node _pool_io_free_valid_T_3 = and(nodeIn_3.e.ready, nodeIn_3.e.valid)
connect pool_3.io.free.valid, _pool_io_free_valid_T_3
connect pool_3.io.free.bits, nodeIn_3.e.bits.sink
wire in_d_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
node _d_first_T_3 = and(in_d_3.ready, in_d_3.valid)
node _d_first_beats1_decode_T_9 = dshl(UInt<6>(0h3f), in_d_3.bits.size)
node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 5, 0)
node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10)
node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3)
node d_first_beats1_opdata_3 = bits(in_d_3.bits.opcode, 0, 0)
node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0))
regreset d_first_counter_3 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1))
node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1)
node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0))
node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1))
node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0))
node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7)
node d_first_done_3 = and(d_first_last_3, _d_first_T_3)
node _d_first_count_T_3 = not(d_first_counter1_3)
node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3)
when _d_first_T_3 :
node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3)
connect d_first_counter_3, _d_first_counter_T_3
node _d_grant_T_6 = eq(in_d_3.bits.opcode, UInt<3>(0h5))
node _d_grant_T_7 = eq(in_d_3.bits.opcode, UInt<3>(0h4))
node d_grant_3 = or(_d_grant_T_6, _d_grant_T_7)
node _pool_io_alloc_ready_T_9 = and(nodeIn_3.d.ready, nodeIn_3.d.valid)
node _pool_io_alloc_ready_T_10 = and(_pool_io_alloc_ready_T_9, d_first_3)
node _pool_io_alloc_ready_T_11 = and(_pool_io_alloc_ready_T_10, d_grant_3)
connect pool_3.io.alloc.ready, _pool_io_alloc_ready_T_11
node _nodeIn_d_valid_T_15 = eq(d_first_3, UInt<1>(0h0))
node _nodeIn_d_valid_T_16 = or(pool_3.io.alloc.valid, _nodeIn_d_valid_T_15)
node _nodeIn_d_valid_T_17 = eq(d_grant_3, UInt<1>(0h0))
node _nodeIn_d_valid_T_18 = or(_nodeIn_d_valid_T_16, _nodeIn_d_valid_T_17)
node _nodeIn_d_valid_T_19 = and(in_d_3.valid, _nodeIn_d_valid_T_18)
connect nodeIn_3.d.valid, _nodeIn_d_valid_T_19
node _in_d_ready_T_15 = eq(d_first_3, UInt<1>(0h0))
node _in_d_ready_T_16 = or(pool_3.io.alloc.valid, _in_d_ready_T_15)
node _in_d_ready_T_17 = eq(d_grant_3, UInt<1>(0h0))
node _in_d_ready_T_18 = or(_in_d_ready_T_16, _in_d_ready_T_17)
node _in_d_ready_T_19 = and(nodeIn_3.d.ready, _in_d_ready_T_18)
connect in_d_3.ready, _in_d_ready_T_19
connect nodeIn_3.d.bits.corrupt, in_d_3.bits.corrupt
connect nodeIn_3.d.bits.data, in_d_3.bits.data
connect nodeIn_3.d.bits.denied, in_d_3.bits.denied
connect nodeIn_3.d.bits.sink, in_d_3.bits.sink
connect nodeIn_3.d.bits.source, in_d_3.bits.source
connect nodeIn_3.d.bits.size, in_d_3.bits.size
connect nodeIn_3.d.bits.param, in_d_3.bits.param
connect nodeIn_3.d.bits.opcode, in_d_3.bits.opcode
reg nodeIn_d_bits_sink_r_3 : UInt<3>, clock
when d_first_3 :
connect nodeIn_d_bits_sink_r_3, pool_3.io.alloc.bits
node _nodeIn_d_bits_sink_T_3 = mux(d_first_3, pool_3.io.alloc.bits, nodeIn_d_bits_sink_r_3)
connect nodeIn_3.d.bits.sink, _nodeIn_d_bits_sink_T_3
wire d_d_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect d_d_3, x1_nodeOut_2.d
node _d_d_bits_source_T_3 = shr(x1_nodeOut_2.d.bits.source, 1)
connect d_d_3.bits.source, _d_d_bits_source_T_3
reg wSourceVec_3 : UInt<1>[10], clock
node _aWOk_T_15 = xor(nodeIn_3.a.bits.address, UInt<1>(0h0))
node _aWOk_T_16 = cvt(_aWOk_T_15)
node _aWOk_T_17 = and(_aWOk_T_16, asSInt(UInt<1>(0h0)))
node _aWOk_T_18 = asSInt(_aWOk_T_17)
node _aWOk_T_19 = eq(_aWOk_T_18, asSInt(UInt<1>(0h0)))
node _bypass_T_6 = and(UInt<1>(0h0), nodeIn_3.a.valid)
node _bypass_T_7 = eq(nodeIn_3.a.bits.source, d_d_3.bits.source)
node bypass_3 = and(_bypass_T_6, _bypass_T_7)
node _dWHeld_T_3 = mux(bypass_3, UInt<1>(0h1), wSourceVec_3[d_d_3.bits.source])
reg dWHeld_r_3 : UInt<1>, clock
when d_first_3 :
connect dWHeld_r_3, _dWHeld_T_3
node dWHeld_3 = mux(d_first_3, _dWHeld_T_3, dWHeld_r_3)
node _T_213 = and(nodeIn_3.a.ready, nodeIn_3.a.valid)
when _T_213 :
connect wSourceVec_3[nodeIn_3.a.bits.source], UInt<1>(0h1)
node _T_214 = eq(x1_nodeOut_2.d.bits.opcode, UInt<1>(0h1))
node _T_215 = bits(x1_nodeOut_2.d.bits.source, 0, 0)
node _T_216 = and(_T_214, _T_215)
when _T_216 :
connect d_d_3.bits.opcode, UInt<3>(0h5)
node _d_d_bits_param_T_3 = mux(dWHeld_3, UInt<2>(0h0), UInt<2>(0h1))
connect d_d_3.bits.param, _d_d_bits_param_T_3
node _T_217 = eq(x1_nodeOut_2.d.bits.opcode, UInt<1>(0h0))
node _T_218 = bits(x1_nodeOut_2.d.bits.source, 0, 0)
node _T_219 = eq(_T_218, UInt<1>(0h0))
node _T_220 = and(_T_217, _T_219)
when _T_220 :
connect d_d_3.bits.opcode, UInt<3>(0h6)
node _decode_T_27 = dshl(UInt<6>(0h3f), c_a_3.bits.size)
node _decode_T_28 = bits(_decode_T_27, 5, 0)
node _decode_T_29 = not(_decode_T_28)
node decode_9 = shr(_decode_T_29, 3)
node _opdata_T_6 = bits(c_a_3.bits.opcode, 2, 2)
node opdata_9 = eq(_opdata_T_6, UInt<1>(0h0))
node _T_221 = mux(opdata_9, decode_9, UInt<1>(0h0))
node _decode_T_30 = dshl(UInt<6>(0h3f), a_a_3.bits.size)
node _decode_T_31 = bits(_decode_T_30, 5, 0)
node _decode_T_32 = not(_decode_T_31)
node decode_10 = shr(_decode_T_32, 3)
node _opdata_T_7 = bits(a_a_3.bits.opcode, 2, 2)
node opdata_10 = eq(_opdata_T_7, UInt<1>(0h0))
node _T_222 = mux(opdata_10, decode_10, UInt<1>(0h0))
regreset beatsLeft_6 : UInt, clock, reset, UInt<1>(0h0)
node idle_6 = eq(beatsLeft_6, UInt<1>(0h0))
node latch_6 = and(idle_6, x1_nodeOut_2.a.ready)
node _readys_T_72 = cat(a_a_3.valid, c_a_3.valid)
node _readys_T_73 = shl(_readys_T_72, 1)
node _readys_T_74 = bits(_readys_T_73, 1, 0)
node _readys_T_75 = or(_readys_T_72, _readys_T_74)
node _readys_T_76 = bits(_readys_T_75, 1, 0)
node _readys_T_77 = shl(_readys_T_76, 1)
node _readys_T_78 = bits(_readys_T_77, 1, 0)
node _readys_T_79 = not(_readys_T_78)
node _readys_T_80 = bits(_readys_T_79, 0, 0)
node _readys_T_81 = bits(_readys_T_79, 1, 1)
wire readys_6 : UInt<1>[2]
connect readys_6[0], _readys_T_80
connect readys_6[1], _readys_T_81
node _winner_T_15 = and(readys_6[0], c_a_3.valid)
node _winner_T_16 = and(readys_6[1], a_a_3.valid)
wire winner_6 : UInt<1>[2]
connect winner_6[0], _winner_T_15
connect winner_6[1], _winner_T_16
node prefixOR_1_6 = or(UInt<1>(0h0), winner_6[0])
node _prefixOR_T_6 = or(prefixOR_1_6, winner_6[1])
node _T_223 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_224 = eq(winner_6[0], UInt<1>(0h0))
node _T_225 = or(_T_223, _T_224)
node _T_226 = eq(prefixOR_1_6, UInt<1>(0h0))
node _T_227 = eq(winner_6[1], UInt<1>(0h0))
node _T_228 = or(_T_226, _T_227)
node _T_229 = and(_T_225, _T_228)
node _T_230 = asUInt(reset)
node _T_231 = eq(_T_230, UInt<1>(0h0))
when _T_231 :
node _T_232 = eq(_T_229, UInt<1>(0h0))
when _T_232 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_20
assert(clock, _T_229, UInt<1>(0h1), "") : assert_20
node _T_233 = or(c_a_3.valid, a_a_3.valid)
node _T_234 = eq(_T_233, UInt<1>(0h0))
node _T_235 = or(winner_6[0], winner_6[1])
node _T_236 = or(_T_234, _T_235)
node _T_237 = asUInt(reset)
node _T_238 = eq(_T_237, UInt<1>(0h0))
when _T_238 :
node _T_239 = eq(_T_236, UInt<1>(0h0))
when _T_239 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_21
assert(clock, _T_236, UInt<1>(0h1), "") : assert_21
node maskedBeats_0_6 = mux(winner_6[0], _T_221, UInt<1>(0h0))
node maskedBeats_1_6 = mux(winner_6[1], _T_222, UInt<1>(0h0))
node initBeats_6 = or(maskedBeats_0_6, maskedBeats_1_6)
node _beatsLeft_T_24 = and(x1_nodeOut_2.a.ready, x1_nodeOut_2.a.valid)
node _beatsLeft_T_25 = sub(beatsLeft_6, _beatsLeft_T_24)
node _beatsLeft_T_26 = tail(_beatsLeft_T_25, 1)
node _beatsLeft_T_27 = mux(latch_6, initBeats_6, _beatsLeft_T_26)
connect beatsLeft_6, _beatsLeft_T_27
wire _state_WIRE_6 : UInt<1>[2]
connect _state_WIRE_6[0], UInt<1>(0h0)
connect _state_WIRE_6[1], UInt<1>(0h0)
regreset state_6 : UInt<1>[2], clock, reset, _state_WIRE_6
node muxState_6 = mux(idle_6, winner_6, state_6)
connect state_6, muxState_6
node allowed_6 = mux(idle_6, readys_6, state_6)
node _c_a_ready_T_3 = and(x1_nodeOut_2.a.ready, allowed_6[0])
connect c_a_3.ready, _c_a_ready_T_3
node _a_a_ready_T_3 = and(x1_nodeOut_2.a.ready, allowed_6[1])
connect a_a_3.ready, _a_a_ready_T_3
node _nodeOut_a_valid_T_15 = or(c_a_3.valid, a_a_3.valid)
node _nodeOut_a_valid_T_16 = mux(state_6[0], c_a_3.valid, UInt<1>(0h0))
node _nodeOut_a_valid_T_17 = mux(state_6[1], a_a_3.valid, UInt<1>(0h0))
node _nodeOut_a_valid_T_18 = or(_nodeOut_a_valid_T_16, _nodeOut_a_valid_T_17)
wire _nodeOut_a_valid_WIRE_3 : UInt<1>
connect _nodeOut_a_valid_WIRE_3, _nodeOut_a_valid_T_18
node _nodeOut_a_valid_T_19 = mux(idle_6, _nodeOut_a_valid_T_15, _nodeOut_a_valid_WIRE_3)
connect x1_nodeOut_2.a.valid, _nodeOut_a_valid_T_19
wire _nodeOut_a_bits_WIRE_33 : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
node _nodeOut_a_bits_T_72 = mux(muxState_6[0], c_a_3.bits.corrupt, UInt<1>(0h0))
node _nodeOut_a_bits_T_73 = mux(muxState_6[1], a_a_3.bits.corrupt, UInt<1>(0h0))
node _nodeOut_a_bits_T_74 = or(_nodeOut_a_bits_T_72, _nodeOut_a_bits_T_73)
wire _nodeOut_a_bits_WIRE_34 : UInt<1>
connect _nodeOut_a_bits_WIRE_34, _nodeOut_a_bits_T_74
connect _nodeOut_a_bits_WIRE_33.corrupt, _nodeOut_a_bits_WIRE_34
node _nodeOut_a_bits_T_75 = mux(muxState_6[0], c_a_3.bits.data, UInt<1>(0h0))
node _nodeOut_a_bits_T_76 = mux(muxState_6[1], a_a_3.bits.data, UInt<1>(0h0))
node _nodeOut_a_bits_T_77 = or(_nodeOut_a_bits_T_75, _nodeOut_a_bits_T_76)
wire _nodeOut_a_bits_WIRE_35 : UInt<64>
connect _nodeOut_a_bits_WIRE_35, _nodeOut_a_bits_T_77
connect _nodeOut_a_bits_WIRE_33.data, _nodeOut_a_bits_WIRE_35
node _nodeOut_a_bits_T_78 = mux(muxState_6[0], c_a_3.bits.mask, UInt<1>(0h0))
node _nodeOut_a_bits_T_79 = mux(muxState_6[1], a_a_3.bits.mask, UInt<1>(0h0))
node _nodeOut_a_bits_T_80 = or(_nodeOut_a_bits_T_78, _nodeOut_a_bits_T_79)
wire _nodeOut_a_bits_WIRE_36 : UInt<8>
connect _nodeOut_a_bits_WIRE_36, _nodeOut_a_bits_T_80
connect _nodeOut_a_bits_WIRE_33.mask, _nodeOut_a_bits_WIRE_36
wire _nodeOut_a_bits_WIRE_37 : { }
connect _nodeOut_a_bits_WIRE_33.echo, _nodeOut_a_bits_WIRE_37
wire _nodeOut_a_bits_WIRE_38 : { }
connect _nodeOut_a_bits_WIRE_33.user, _nodeOut_a_bits_WIRE_38
node _nodeOut_a_bits_T_81 = mux(muxState_6[0], c_a_3.bits.address, UInt<1>(0h0))
node _nodeOut_a_bits_T_82 = mux(muxState_6[1], a_a_3.bits.address, UInt<1>(0h0))
node _nodeOut_a_bits_T_83 = or(_nodeOut_a_bits_T_81, _nodeOut_a_bits_T_82)
wire _nodeOut_a_bits_WIRE_39 : UInt<32>
connect _nodeOut_a_bits_WIRE_39, _nodeOut_a_bits_T_83
connect _nodeOut_a_bits_WIRE_33.address, _nodeOut_a_bits_WIRE_39
node _nodeOut_a_bits_T_84 = mux(muxState_6[0], c_a_3.bits.source, UInt<1>(0h0))
node _nodeOut_a_bits_T_85 = mux(muxState_6[1], a_a_3.bits.source, UInt<1>(0h0))
node _nodeOut_a_bits_T_86 = or(_nodeOut_a_bits_T_84, _nodeOut_a_bits_T_85)
wire _nodeOut_a_bits_WIRE_40 : UInt<5>
connect _nodeOut_a_bits_WIRE_40, _nodeOut_a_bits_T_86
connect _nodeOut_a_bits_WIRE_33.source, _nodeOut_a_bits_WIRE_40
node _nodeOut_a_bits_T_87 = mux(muxState_6[0], c_a_3.bits.size, UInt<1>(0h0))
node _nodeOut_a_bits_T_88 = mux(muxState_6[1], a_a_3.bits.size, UInt<1>(0h0))
node _nodeOut_a_bits_T_89 = or(_nodeOut_a_bits_T_87, _nodeOut_a_bits_T_88)
wire _nodeOut_a_bits_WIRE_41 : UInt<3>
connect _nodeOut_a_bits_WIRE_41, _nodeOut_a_bits_T_89
connect _nodeOut_a_bits_WIRE_33.size, _nodeOut_a_bits_WIRE_41
node _nodeOut_a_bits_T_90 = mux(muxState_6[0], c_a_3.bits.param, UInt<1>(0h0))
node _nodeOut_a_bits_T_91 = mux(muxState_6[1], a_a_3.bits.param, UInt<1>(0h0))
node _nodeOut_a_bits_T_92 = or(_nodeOut_a_bits_T_90, _nodeOut_a_bits_T_91)
wire _nodeOut_a_bits_WIRE_42 : UInt<3>
connect _nodeOut_a_bits_WIRE_42, _nodeOut_a_bits_T_92
connect _nodeOut_a_bits_WIRE_33.param, _nodeOut_a_bits_WIRE_42
node _nodeOut_a_bits_T_93 = mux(muxState_6[0], c_a_3.bits.opcode, UInt<1>(0h0))
node _nodeOut_a_bits_T_94 = mux(muxState_6[1], a_a_3.bits.opcode, UInt<1>(0h0))
node _nodeOut_a_bits_T_95 = or(_nodeOut_a_bits_T_93, _nodeOut_a_bits_T_94)
wire _nodeOut_a_bits_WIRE_43 : UInt<3>
connect _nodeOut_a_bits_WIRE_43, _nodeOut_a_bits_T_95
connect _nodeOut_a_bits_WIRE_33.opcode, _nodeOut_a_bits_WIRE_43
connect x1_nodeOut_2.a.bits.corrupt, _nodeOut_a_bits_WIRE_33.corrupt
connect x1_nodeOut_2.a.bits.data, _nodeOut_a_bits_WIRE_33.data
connect x1_nodeOut_2.a.bits.mask, _nodeOut_a_bits_WIRE_33.mask
connect x1_nodeOut_2.a.bits.address, _nodeOut_a_bits_WIRE_33.address
connect x1_nodeOut_2.a.bits.source, _nodeOut_a_bits_WIRE_33.source
connect x1_nodeOut_2.a.bits.size, _nodeOut_a_bits_WIRE_33.size
connect x1_nodeOut_2.a.bits.param, _nodeOut_a_bits_WIRE_33.param
connect x1_nodeOut_2.a.bits.opcode, _nodeOut_a_bits_WIRE_33.opcode
node _decode_T_33 = dshl(UInt<6>(0h3f), d_d_3.bits.size)
node _decode_T_34 = bits(_decode_T_33, 5, 0)
node _decode_T_35 = not(_decode_T_34)
node decode_11 = shr(_decode_T_35, 3)
node opdata_11 = bits(d_d_3.bits.opcode, 0, 0)
node _T_240 = mux(opdata_11, decode_11, UInt<1>(0h0))
inst q_6 of Queue2_TLBundleD_a32d64s4k3z3c_10
connect q_6.clock, clock
connect q_6.reset, reset
connect q_6.io.enq.valid, c_d_3.valid
connect q_6.io.enq.bits.corrupt, c_d_3.bits.corrupt
connect q_6.io.enq.bits.data, c_d_3.bits.data
connect q_6.io.enq.bits.denied, c_d_3.bits.denied
connect q_6.io.enq.bits.sink, c_d_3.bits.sink
connect q_6.io.enq.bits.source, c_d_3.bits.source
connect q_6.io.enq.bits.size, c_d_3.bits.size
connect q_6.io.enq.bits.param, c_d_3.bits.param
connect q_6.io.enq.bits.opcode, c_d_3.bits.opcode
connect c_d_3.ready, q_6.io.enq.ready
inst q_7 of Queue2_TLBundleD_a32d64s4k3z3c_11
connect q_7.clock, clock
connect q_7.reset, reset
connect q_7.io.enq.valid, a_d_3.valid
connect q_7.io.enq.bits.corrupt, a_d_3.bits.corrupt
connect q_7.io.enq.bits.data, a_d_3.bits.data
connect q_7.io.enq.bits.denied, a_d_3.bits.denied
connect q_7.io.enq.bits.sink, a_d_3.bits.sink
connect q_7.io.enq.bits.source, a_d_3.bits.source
connect q_7.io.enq.bits.size, a_d_3.bits.size
connect q_7.io.enq.bits.param, a_d_3.bits.param
connect q_7.io.enq.bits.opcode, a_d_3.bits.opcode
connect a_d_3.ready, q_7.io.enq.ready
regreset beatsLeft_7 : UInt, clock, reset, UInt<1>(0h0)
node idle_7 = eq(beatsLeft_7, UInt<1>(0h0))
node latch_7 = and(idle_7, in_d_3.ready)
node readys_hi_3 = cat(q_7.io.deq.valid, q_6.io.deq.valid)
node _readys_T_82 = cat(readys_hi_3, d_d_3.valid)
node _readys_T_83 = shl(_readys_T_82, 1)
node _readys_T_84 = bits(_readys_T_83, 2, 0)
node _readys_T_85 = or(_readys_T_82, _readys_T_84)
node _readys_T_86 = shl(_readys_T_85, 2)
node _readys_T_87 = bits(_readys_T_86, 2, 0)
node _readys_T_88 = or(_readys_T_85, _readys_T_87)
node _readys_T_89 = bits(_readys_T_88, 2, 0)
node _readys_T_90 = shl(_readys_T_89, 1)
node _readys_T_91 = bits(_readys_T_90, 2, 0)
node _readys_T_92 = not(_readys_T_91)
node _readys_T_93 = bits(_readys_T_92, 0, 0)
node _readys_T_94 = bits(_readys_T_92, 1, 1)
node _readys_T_95 = bits(_readys_T_92, 2, 2)
wire readys_7 : UInt<1>[3]
connect readys_7[0], _readys_T_93
connect readys_7[1], _readys_T_94
connect readys_7[2], _readys_T_95
node _winner_T_17 = and(readys_7[0], d_d_3.valid)
node _winner_T_18 = and(readys_7[1], q_6.io.deq.valid)
node _winner_T_19 = and(readys_7[2], q_7.io.deq.valid)
wire winner_7 : UInt<1>[3]
connect winner_7[0], _winner_T_17
connect winner_7[1], _winner_T_18
connect winner_7[2], _winner_T_19
node prefixOR_1_7 = or(UInt<1>(0h0), winner_7[0])
node prefixOR_2_3 = or(prefixOR_1_7, winner_7[1])
node _prefixOR_T_7 = or(prefixOR_2_3, winner_7[2])
node _T_241 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_242 = eq(winner_7[0], UInt<1>(0h0))
node _T_243 = or(_T_241, _T_242)
node _T_244 = eq(prefixOR_1_7, UInt<1>(0h0))
node _T_245 = eq(winner_7[1], UInt<1>(0h0))
node _T_246 = or(_T_244, _T_245)
node _T_247 = eq(prefixOR_2_3, UInt<1>(0h0))
node _T_248 = eq(winner_7[2], UInt<1>(0h0))
node _T_249 = or(_T_247, _T_248)
node _T_250 = and(_T_243, _T_246)
node _T_251 = and(_T_250, _T_249)
node _T_252 = asUInt(reset)
node _T_253 = eq(_T_252, UInt<1>(0h0))
when _T_253 :
node _T_254 = eq(_T_251, UInt<1>(0h0))
when _T_254 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_22
assert(clock, _T_251, UInt<1>(0h1), "") : assert_22
node _T_255 = or(d_d_3.valid, q_6.io.deq.valid)
node _T_256 = or(_T_255, q_7.io.deq.valid)
node _T_257 = eq(_T_256, UInt<1>(0h0))
node _T_258 = or(winner_7[0], winner_7[1])
node _T_259 = or(_T_258, winner_7[2])
node _T_260 = or(_T_257, _T_259)
node _T_261 = asUInt(reset)
node _T_262 = eq(_T_261, UInt<1>(0h0))
when _T_262 :
node _T_263 = eq(_T_260, UInt<1>(0h0))
when _T_263 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_23
assert(clock, _T_260, UInt<1>(0h1), "") : assert_23
node maskedBeats_0_7 = mux(winner_7[0], _T_240, UInt<1>(0h0))
node maskedBeats_1_7 = mux(winner_7[1], UInt<1>(0h0), UInt<1>(0h0))
node maskedBeats_2_3 = mux(winner_7[2], UInt<1>(0h0), UInt<1>(0h0))
node _initBeats_T_3 = or(maskedBeats_0_7, maskedBeats_1_7)
node initBeats_7 = or(_initBeats_T_3, maskedBeats_2_3)
node _beatsLeft_T_28 = and(in_d_3.ready, in_d_3.valid)
node _beatsLeft_T_29 = sub(beatsLeft_7, _beatsLeft_T_28)
node _beatsLeft_T_30 = tail(_beatsLeft_T_29, 1)
node _beatsLeft_T_31 = mux(latch_7, initBeats_7, _beatsLeft_T_30)
connect beatsLeft_7, _beatsLeft_T_31
wire _state_WIRE_7 : UInt<1>[3]
connect _state_WIRE_7[0], UInt<1>(0h0)
connect _state_WIRE_7[1], UInt<1>(0h0)
connect _state_WIRE_7[2], UInt<1>(0h0)
regreset state_7 : UInt<1>[3], clock, reset, _state_WIRE_7
node muxState_7 = mux(idle_7, winner_7, state_7)
connect state_7, muxState_7
node allowed_7 = mux(idle_7, readys_7, state_7)
node _d_d_ready_T_3 = and(in_d_3.ready, allowed_7[0])
connect d_d_3.ready, _d_d_ready_T_3
node _q_io_deq_ready_T_6 = and(in_d_3.ready, allowed_7[1])
connect q_6.io.deq.ready, _q_io_deq_ready_T_6
node _q_io_deq_ready_T_7 = and(in_d_3.ready, allowed_7[2])
connect q_7.io.deq.ready, _q_io_deq_ready_T_7
node _in_d_valid_T_24 = or(d_d_3.valid, q_6.io.deq.valid)
node _in_d_valid_T_25 = or(_in_d_valid_T_24, q_7.io.deq.valid)
node _in_d_valid_T_26 = mux(state_7[0], d_d_3.valid, UInt<1>(0h0))
node _in_d_valid_T_27 = mux(state_7[1], q_6.io.deq.valid, UInt<1>(0h0))
node _in_d_valid_T_28 = mux(state_7[2], q_7.io.deq.valid, UInt<1>(0h0))
node _in_d_valid_T_29 = or(_in_d_valid_T_26, _in_d_valid_T_27)
node _in_d_valid_T_30 = or(_in_d_valid_T_29, _in_d_valid_T_28)
wire _in_d_valid_WIRE_3 : UInt<1>
connect _in_d_valid_WIRE_3, _in_d_valid_T_30
node _in_d_valid_T_31 = mux(idle_7, _in_d_valid_T_25, _in_d_valid_WIRE_3)
connect in_d_3.valid, _in_d_valid_T_31
wire _in_d_bits_WIRE_33 : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
node _in_d_bits_T_120 = mux(muxState_7[0], d_d_3.bits.corrupt, UInt<1>(0h0))
node _in_d_bits_T_121 = mux(muxState_7[1], q_6.io.deq.bits.corrupt, UInt<1>(0h0))
node _in_d_bits_T_122 = mux(muxState_7[2], q_7.io.deq.bits.corrupt, UInt<1>(0h0))
node _in_d_bits_T_123 = or(_in_d_bits_T_120, _in_d_bits_T_121)
node _in_d_bits_T_124 = or(_in_d_bits_T_123, _in_d_bits_T_122)
wire _in_d_bits_WIRE_34 : UInt<1>
connect _in_d_bits_WIRE_34, _in_d_bits_T_124
connect _in_d_bits_WIRE_33.corrupt, _in_d_bits_WIRE_34
node _in_d_bits_T_125 = mux(muxState_7[0], d_d_3.bits.data, UInt<1>(0h0))
node _in_d_bits_T_126 = mux(muxState_7[1], q_6.io.deq.bits.data, UInt<1>(0h0))
node _in_d_bits_T_127 = mux(muxState_7[2], q_7.io.deq.bits.data, UInt<1>(0h0))
node _in_d_bits_T_128 = or(_in_d_bits_T_125, _in_d_bits_T_126)
node _in_d_bits_T_129 = or(_in_d_bits_T_128, _in_d_bits_T_127)
wire _in_d_bits_WIRE_35 : UInt<64>
connect _in_d_bits_WIRE_35, _in_d_bits_T_129
connect _in_d_bits_WIRE_33.data, _in_d_bits_WIRE_35
wire _in_d_bits_WIRE_36 : { }
connect _in_d_bits_WIRE_33.echo, _in_d_bits_WIRE_36
wire _in_d_bits_WIRE_37 : { }
connect _in_d_bits_WIRE_33.user, _in_d_bits_WIRE_37
node _in_d_bits_T_130 = mux(muxState_7[0], d_d_3.bits.denied, UInt<1>(0h0))
node _in_d_bits_T_131 = mux(muxState_7[1], q_6.io.deq.bits.denied, UInt<1>(0h0))
node _in_d_bits_T_132 = mux(muxState_7[2], q_7.io.deq.bits.denied, UInt<1>(0h0))
node _in_d_bits_T_133 = or(_in_d_bits_T_130, _in_d_bits_T_131)
node _in_d_bits_T_134 = or(_in_d_bits_T_133, _in_d_bits_T_132)
wire _in_d_bits_WIRE_38 : UInt<1>
connect _in_d_bits_WIRE_38, _in_d_bits_T_134
connect _in_d_bits_WIRE_33.denied, _in_d_bits_WIRE_38
node _in_d_bits_T_135 = mux(muxState_7[0], d_d_3.bits.sink, UInt<1>(0h0))
node _in_d_bits_T_136 = mux(muxState_7[1], q_6.io.deq.bits.sink, UInt<1>(0h0))
node _in_d_bits_T_137 = mux(muxState_7[2], q_7.io.deq.bits.sink, UInt<1>(0h0))
node _in_d_bits_T_138 = or(_in_d_bits_T_135, _in_d_bits_T_136)
node _in_d_bits_T_139 = or(_in_d_bits_T_138, _in_d_bits_T_137)
wire _in_d_bits_WIRE_39 : UInt<3>
connect _in_d_bits_WIRE_39, _in_d_bits_T_139
connect _in_d_bits_WIRE_33.sink, _in_d_bits_WIRE_39
node _in_d_bits_T_140 = mux(muxState_7[0], d_d_3.bits.source, UInt<1>(0h0))
node _in_d_bits_T_141 = mux(muxState_7[1], q_6.io.deq.bits.source, UInt<1>(0h0))
node _in_d_bits_T_142 = mux(muxState_7[2], q_7.io.deq.bits.source, UInt<1>(0h0))
node _in_d_bits_T_143 = or(_in_d_bits_T_140, _in_d_bits_T_141)
node _in_d_bits_T_144 = or(_in_d_bits_T_143, _in_d_bits_T_142)
wire _in_d_bits_WIRE_40 : UInt<4>
connect _in_d_bits_WIRE_40, _in_d_bits_T_144
connect _in_d_bits_WIRE_33.source, _in_d_bits_WIRE_40
node _in_d_bits_T_145 = mux(muxState_7[0], d_d_3.bits.size, UInt<1>(0h0))
node _in_d_bits_T_146 = mux(muxState_7[1], q_6.io.deq.bits.size, UInt<1>(0h0))
node _in_d_bits_T_147 = mux(muxState_7[2], q_7.io.deq.bits.size, UInt<1>(0h0))
node _in_d_bits_T_148 = or(_in_d_bits_T_145, _in_d_bits_T_146)
node _in_d_bits_T_149 = or(_in_d_bits_T_148, _in_d_bits_T_147)
wire _in_d_bits_WIRE_41 : UInt<3>
connect _in_d_bits_WIRE_41, _in_d_bits_T_149
connect _in_d_bits_WIRE_33.size, _in_d_bits_WIRE_41
node _in_d_bits_T_150 = mux(muxState_7[0], d_d_3.bits.param, UInt<1>(0h0))
node _in_d_bits_T_151 = mux(muxState_7[1], q_6.io.deq.bits.param, UInt<1>(0h0))
node _in_d_bits_T_152 = mux(muxState_7[2], q_7.io.deq.bits.param, UInt<1>(0h0))
node _in_d_bits_T_153 = or(_in_d_bits_T_150, _in_d_bits_T_151)
node _in_d_bits_T_154 = or(_in_d_bits_T_153, _in_d_bits_T_152)
wire _in_d_bits_WIRE_42 : UInt<2>
connect _in_d_bits_WIRE_42, _in_d_bits_T_154
connect _in_d_bits_WIRE_33.param, _in_d_bits_WIRE_42
node _in_d_bits_T_155 = mux(muxState_7[0], d_d_3.bits.opcode, UInt<1>(0h0))
node _in_d_bits_T_156 = mux(muxState_7[1], q_6.io.deq.bits.opcode, UInt<1>(0h0))
node _in_d_bits_T_157 = mux(muxState_7[2], q_7.io.deq.bits.opcode, UInt<1>(0h0))
node _in_d_bits_T_158 = or(_in_d_bits_T_155, _in_d_bits_T_156)
node _in_d_bits_T_159 = or(_in_d_bits_T_158, _in_d_bits_T_157)
wire _in_d_bits_WIRE_43 : UInt<3>
connect _in_d_bits_WIRE_43, _in_d_bits_T_159
connect _in_d_bits_WIRE_33.opcode, _in_d_bits_WIRE_43
connect in_d_3.bits.corrupt, _in_d_bits_WIRE_33.corrupt
connect in_d_3.bits.data, _in_d_bits_WIRE_33.data
connect in_d_3.bits.denied, _in_d_bits_WIRE_33.denied
connect in_d_3.bits.sink, _in_d_bits_WIRE_33.sink
connect in_d_3.bits.source, _in_d_bits_WIRE_33.source
connect in_d_3.bits.size, _in_d_bits_WIRE_33.size
connect in_d_3.bits.param, _in_d_bits_WIRE_33.param
connect in_d_3.bits.opcode, _in_d_bits_WIRE_33.opcode
connect nodeIn_3.b.valid, UInt<1>(0h0)
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.address, UInt<32>(0h0)
connect _WIRE_28.bits.source, UInt<5>(0h0)
connect _WIRE_28.bits.size, UInt<3>(0h0)
connect _WIRE_28.bits.param, UInt<3>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
connect _WIRE_29.valid, UInt<1>(0h0)
wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_30.bits.sink, UInt<1>(0h0)
connect _WIRE_30.valid, UInt<1>(0h0)
connect _WIRE_30.ready, UInt<1>(0h0)
wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_31.bits, _WIRE_30.bits
connect _WIRE_31.valid, _WIRE_30.valid
connect _WIRE_31.ready, _WIRE_30.ready
connect _WIRE_31.valid, UInt<1>(0h0) | module TLCacheCork( // @[CacheCork.scala:42:9]
input clock, // @[CacheCork.scala:42:9]
input reset, // @[CacheCork.scala:42:9]
output auto_in_3_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_3_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_3_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_3_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_3_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_3_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_3_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_3_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_3_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_3_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_3_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_3_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_3_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_3_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_3_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_3_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_3_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_3_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_3_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_3_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_3_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_3_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_3_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_3_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_3_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_3_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_3_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_3_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_3_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_3_e_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_3_e_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_2_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_2_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_2_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_2_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_2_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_2_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_2_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_2_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_2_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_2_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_2_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_2_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_2_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_2_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_2_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_2_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_2_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_2_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_2_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_2_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_2_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_2_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_2_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_2_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_2_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_2_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_2_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_2_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_2_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_2_e_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_2_e_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_1_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_1_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_1_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_1_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_1_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_1_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_1_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_1_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_1_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_1_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_1_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_1_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_1_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_1_e_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_1_e_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_0_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_0_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_0_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_0_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_0_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_0_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_0_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_0_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_0_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_0_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_0_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_0_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_0_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_0_e_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_0_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_3_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_3_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_3_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_3_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_3_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_out_3_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_3_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_3_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_3_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_3_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_3_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_3_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_3_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_3_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_3_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_out_3_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_out_3_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_3_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_3_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_2_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_2_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_2_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_2_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_2_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_out_2_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_2_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_2_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_2_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_2_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_2_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_2_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_2_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_2_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_2_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_out_2_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_out_2_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_2_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_2_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_1_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_1_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_1_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_0_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_0_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_0_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_0_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_0_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire [2:0] _in_d_bits_T_159; // @[Mux.scala:30:73]
wire in_d_3_valid; // @[Arbiter.scala:96:24]
wire a_a_3_ready; // @[Arbiter.scala:94:31]
wire c_a_3_ready; // @[Arbiter.scala:94:31]
wire nodeIn_3_d_valid; // @[CacheCork.scala:135:34]
wire [2:0] _in_d_bits_T_119; // @[Mux.scala:30:73]
wire in_d_2_valid; // @[Arbiter.scala:96:24]
wire a_a_2_ready; // @[Arbiter.scala:94:31]
wire c_a_2_ready; // @[Arbiter.scala:94:31]
wire nodeIn_2_d_valid; // @[CacheCork.scala:135:34]
wire [2:0] _in_d_bits_T_79; // @[Mux.scala:30:73]
wire in_d_1_valid; // @[Arbiter.scala:96:24]
wire a_a_1_ready; // @[Arbiter.scala:94:31]
wire c_a_1_ready; // @[Arbiter.scala:94:31]
wire nodeIn_1_d_valid; // @[CacheCork.scala:135:34]
wire [2:0] _in_d_bits_T_39; // @[Mux.scala:30:73]
wire in_d_valid; // @[Arbiter.scala:96:24]
wire a_a_ready; // @[Arbiter.scala:94:31]
wire c_a_ready; // @[Arbiter.scala:94:31]
wire nodeIn_d_valid; // @[CacheCork.scala:135:34]
wire _q_7_io_enq_ready; // @[Decoupled.scala:362:21]
wire _q_7_io_deq_valid; // @[Decoupled.scala:362:21]
wire [2:0] _q_7_io_deq_bits_opcode; // @[Decoupled.scala:362:21]
wire [1:0] _q_7_io_deq_bits_param; // @[Decoupled.scala:362:21]
wire [2:0] _q_7_io_deq_bits_size; // @[Decoupled.scala:362:21]
wire [3:0] _q_7_io_deq_bits_source; // @[Decoupled.scala:362:21]
wire _q_7_io_deq_bits_denied; // @[Decoupled.scala:362:21]
wire [63:0] _q_7_io_deq_bits_data; // @[Decoupled.scala:362:21]
wire _q_7_io_deq_bits_corrupt; // @[Decoupled.scala:362:21]
wire _q_6_io_enq_ready; // @[Decoupled.scala:362:21]
wire _q_6_io_deq_valid; // @[Decoupled.scala:362:21]
wire [2:0] _q_6_io_deq_bits_opcode; // @[Decoupled.scala:362:21]
wire [1:0] _q_6_io_deq_bits_param; // @[Decoupled.scala:362:21]
wire [2:0] _q_6_io_deq_bits_size; // @[Decoupled.scala:362:21]
wire [3:0] _q_6_io_deq_bits_source; // @[Decoupled.scala:362:21]
wire _q_6_io_deq_bits_denied; // @[Decoupled.scala:362:21]
wire [63:0] _q_6_io_deq_bits_data; // @[Decoupled.scala:362:21]
wire _q_6_io_deq_bits_corrupt; // @[Decoupled.scala:362:21]
wire _pool_3_io_alloc_valid; // @[CacheCork.scala:127:26]
wire [2:0] _pool_3_io_alloc_bits; // @[CacheCork.scala:127:26]
wire _q_5_io_enq_ready; // @[Decoupled.scala:362:21]
wire _q_5_io_deq_valid; // @[Decoupled.scala:362:21]
wire [2:0] _q_5_io_deq_bits_opcode; // @[Decoupled.scala:362:21]
wire [1:0] _q_5_io_deq_bits_param; // @[Decoupled.scala:362:21]
wire [2:0] _q_5_io_deq_bits_size; // @[Decoupled.scala:362:21]
wire [3:0] _q_5_io_deq_bits_source; // @[Decoupled.scala:362:21]
wire _q_5_io_deq_bits_denied; // @[Decoupled.scala:362:21]
wire [63:0] _q_5_io_deq_bits_data; // @[Decoupled.scala:362:21]
wire _q_5_io_deq_bits_corrupt; // @[Decoupled.scala:362:21]
wire _q_4_io_enq_ready; // @[Decoupled.scala:362:21]
wire _q_4_io_deq_valid; // @[Decoupled.scala:362:21]
wire [2:0] _q_4_io_deq_bits_opcode; // @[Decoupled.scala:362:21]
wire [1:0] _q_4_io_deq_bits_param; // @[Decoupled.scala:362:21]
wire [2:0] _q_4_io_deq_bits_size; // @[Decoupled.scala:362:21]
wire [3:0] _q_4_io_deq_bits_source; // @[Decoupled.scala:362:21]
wire _q_4_io_deq_bits_denied; // @[Decoupled.scala:362:21]
wire [63:0] _q_4_io_deq_bits_data; // @[Decoupled.scala:362:21]
wire _q_4_io_deq_bits_corrupt; // @[Decoupled.scala:362:21]
wire _pool_2_io_alloc_valid; // @[CacheCork.scala:127:26]
wire [2:0] _pool_2_io_alloc_bits; // @[CacheCork.scala:127:26]
wire _q_3_io_enq_ready; // @[Decoupled.scala:362:21]
wire _q_3_io_deq_valid; // @[Decoupled.scala:362:21]
wire [2:0] _q_3_io_deq_bits_opcode; // @[Decoupled.scala:362:21]
wire [1:0] _q_3_io_deq_bits_param; // @[Decoupled.scala:362:21]
wire [2:0] _q_3_io_deq_bits_size; // @[Decoupled.scala:362:21]
wire [3:0] _q_3_io_deq_bits_source; // @[Decoupled.scala:362:21]
wire _q_3_io_deq_bits_denied; // @[Decoupled.scala:362:21]
wire [63:0] _q_3_io_deq_bits_data; // @[Decoupled.scala:362:21]
wire _q_3_io_deq_bits_corrupt; // @[Decoupled.scala:362:21]
wire _q_2_io_enq_ready; // @[Decoupled.scala:362:21]
wire _q_2_io_deq_valid; // @[Decoupled.scala:362:21]
wire [2:0] _q_2_io_deq_bits_opcode; // @[Decoupled.scala:362:21]
wire [1:0] _q_2_io_deq_bits_param; // @[Decoupled.scala:362:21]
wire [2:0] _q_2_io_deq_bits_size; // @[Decoupled.scala:362:21]
wire [3:0] _q_2_io_deq_bits_source; // @[Decoupled.scala:362:21]
wire _q_2_io_deq_bits_denied; // @[Decoupled.scala:362:21]
wire [63:0] _q_2_io_deq_bits_data; // @[Decoupled.scala:362:21]
wire _q_2_io_deq_bits_corrupt; // @[Decoupled.scala:362:21]
wire _pool_1_io_alloc_valid; // @[CacheCork.scala:127:26]
wire [2:0] _pool_1_io_alloc_bits; // @[CacheCork.scala:127:26]
wire _q_1_io_enq_ready; // @[Decoupled.scala:362:21]
wire _q_1_io_deq_valid; // @[Decoupled.scala:362:21]
wire [2:0] _q_1_io_deq_bits_opcode; // @[Decoupled.scala:362:21]
wire [1:0] _q_1_io_deq_bits_param; // @[Decoupled.scala:362:21]
wire [2:0] _q_1_io_deq_bits_size; // @[Decoupled.scala:362:21]
wire [3:0] _q_1_io_deq_bits_source; // @[Decoupled.scala:362:21]
wire _q_1_io_deq_bits_denied; // @[Decoupled.scala:362:21]
wire [63:0] _q_1_io_deq_bits_data; // @[Decoupled.scala:362:21]
wire _q_1_io_deq_bits_corrupt; // @[Decoupled.scala:362:21]
wire _q_io_enq_ready; // @[Decoupled.scala:362:21]
wire _q_io_deq_valid; // @[Decoupled.scala:362:21]
wire [2:0] _q_io_deq_bits_opcode; // @[Decoupled.scala:362:21]
wire [1:0] _q_io_deq_bits_param; // @[Decoupled.scala:362:21]
wire [2:0] _q_io_deq_bits_size; // @[Decoupled.scala:362:21]
wire [3:0] _q_io_deq_bits_source; // @[Decoupled.scala:362:21]
wire _q_io_deq_bits_denied; // @[Decoupled.scala:362:21]
wire [63:0] _q_io_deq_bits_data; // @[Decoupled.scala:362:21]
wire _q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21]
wire _pool_io_alloc_valid; // @[CacheCork.scala:127:26]
wire [2:0] _pool_io_alloc_bits; // @[CacheCork.scala:127:26]
wire _toD_T = auto_in_0_a_bits_opcode == 3'h6; // @[CacheCork.scala:77:37]
wire toD = _toD_T & auto_in_0_a_bits_param == 3'h2 | (&auto_in_0_a_bits_opcode); // @[CacheCork.scala:77:{37,54,73,97}, :78:37]
wire nodeIn_a_ready = toD ? _q_1_io_enq_ready : a_a_ready; // @[Decoupled.scala:362:21]
wire a_a_valid = auto_in_0_a_valid & ~toD; // @[CacheCork.scala:77:97, :81:{33,36}]
wire _GEN = _toD_T | (&auto_in_0_a_bits_opcode); // @[CacheCork.scala:77:37, :78:37, :86:49]
wire [2:0] a_a_bits_opcode = _GEN ? 3'h4 : auto_in_0_a_bits_opcode; // @[CacheCork.scala:42:9, :82:18, :86:{49,86}, :87:27]
wire winner_0 = auto_in_0_c_valid & (&auto_in_0_c_bits_opcode); // @[CacheCork.scala:102:{33,53}]
wire c_a_bits_a_mask_sub_sub_sub_0_1 = auto_in_0_c_bits_size > 3'h2; // @[Misc.scala:206:21]
wire c_a_bits_a_mask_sub_sub_size = auto_in_0_c_bits_size[1:0] == 2'h2; // @[OneHot.scala:64:49]
wire c_a_bits_a_mask_sub_sub_0_1 = c_a_bits_a_mask_sub_sub_sub_0_1 | c_a_bits_a_mask_sub_sub_size & ~(auto_in_0_c_bits_address[2]); // @[Misc.scala:206:21, :209:26, :210:26, :211:20, :215:{29,38}]
wire c_a_bits_a_mask_sub_sub_1_1 = c_a_bits_a_mask_sub_sub_sub_0_1 | c_a_bits_a_mask_sub_sub_size & auto_in_0_c_bits_address[2]; // @[Misc.scala:206:21, :209:26, :210:26, :215:{29,38}]
wire c_a_bits_a_mask_sub_size = auto_in_0_c_bits_size[1:0] == 2'h1; // @[OneHot.scala:64:49]
wire c_a_bits_a_mask_sub_0_2 = ~(auto_in_0_c_bits_address[2]) & ~(auto_in_0_c_bits_address[1]); // @[Misc.scala:210:26, :211:20, :214:27]
wire c_a_bits_a_mask_sub_0_1 = c_a_bits_a_mask_sub_sub_0_1 | c_a_bits_a_mask_sub_size & c_a_bits_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:{29,38}]
wire c_a_bits_a_mask_sub_1_2 = ~(auto_in_0_c_bits_address[2]) & auto_in_0_c_bits_address[1]; // @[Misc.scala:210:26, :211:20, :214:27]
wire c_a_bits_a_mask_sub_1_1 = c_a_bits_a_mask_sub_sub_0_1 | c_a_bits_a_mask_sub_size & c_a_bits_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:{29,38}]
wire c_a_bits_a_mask_sub_2_2 = auto_in_0_c_bits_address[2] & ~(auto_in_0_c_bits_address[1]); // @[Misc.scala:210:26, :211:20, :214:27]
wire c_a_bits_a_mask_sub_2_1 = c_a_bits_a_mask_sub_sub_1_1 | c_a_bits_a_mask_sub_size & c_a_bits_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:{29,38}]
wire c_a_bits_a_mask_sub_3_2 = auto_in_0_c_bits_address[2] & auto_in_0_c_bits_address[1]; // @[Misc.scala:210:26, :214:27]
wire c_a_bits_a_mask_sub_3_1 = c_a_bits_a_mask_sub_sub_1_1 | c_a_bits_a_mask_sub_size & c_a_bits_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:{29,38}]
wire _nodeIn_c_ready_T = auto_in_0_c_bits_opcode == 3'h6; // @[CacheCork.scala:113:53]
wire nodeIn_c_ready = _nodeIn_c_ready_T ? _q_io_enq_ready : c_a_ready; // @[Decoupled.scala:362:21]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire d_grant = _in_d_bits_T_39 == 3'h5 | _in_d_bits_T_39 == 3'h4; // @[Mux.scala:30:73]
wire [3:0] _GEN_0 = {_pool_io_alloc_valid, d_first_counter}; // @[Edges.scala:229:27, :231:25]
assign nodeIn_d_valid = in_d_valid & ((|_GEN_0) | ~d_grant); // @[Edges.scala:231:25]
wire in_d_ready = auto_in_0_d_ready & ((|_GEN_0) | ~d_grant); // @[Edges.scala:231:25]
reg [2:0] nodeIn_d_bits_sink_r; // @[package.scala:88:63]
wire [2:0] nodeIn_d_bits_sink = d_first ? _pool_io_alloc_bits : nodeIn_d_bits_sink_r; // @[package.scala:88:{42,63}]
wire _GEN_1 = auto_out_0_d_bits_opcode == 3'h1 & auto_out_0_d_bits_source[0]; // @[CacheCork.scala:42:9, :162:{33,51,71}]
wire [2:0] d_d_bits_opcode = auto_out_0_d_bits_opcode == 3'h0 & ~(auto_out_0_d_bits_source[0]) ? 3'h6 : _GEN_1 ? 3'h5 : auto_out_0_d_bits_opcode; // @[CacheCork.scala:42:9, :142:13, :162:{51,71,76}, :163:27, :166:{33,47,50,73}, :167:27]
reg [2:0] beatsLeft; // @[Arbiter.scala:60:30]
wire idle = beatsLeft == 3'h0; // @[CacheCork.scala:42:9]
wire winner_1 = ~winner_0 & a_a_valid; // @[CacheCork.scala:81:33, :102:33]
wire _nodeOut_a_valid_T = winner_0 | a_a_valid; // @[CacheCork.scala:81:33, :102:33]
reg state_0; // @[Arbiter.scala:88:26]
reg state_1; // @[Arbiter.scala:88:26]
wire muxState_0 = idle ? winner_0 : state_0; // @[CacheCork.scala:102:33]
wire muxState_1 = idle ? winner_1 : state_1; // @[Arbiter.scala:61:28, :71:69, :88:26, :89:25]
assign c_a_ready = auto_out_0_a_ready & (idle | state_0); // @[Arbiter.scala:61:28, :88:26, :92:24, :94:31]
assign a_a_ready = auto_out_0_a_ready & (idle ? ~winner_0 : state_1); // @[CacheCork.scala:102:33]
wire nodeOut_a_valid = idle ? _nodeOut_a_valid_T : state_0 & winner_0 | state_1 & a_a_valid; // @[Mux.scala:30:73]
reg [2:0] beatsLeft_1; // @[Arbiter.scala:60:30]
wire idle_1 = beatsLeft_1 == 3'h0; // @[CacheCork.scala:42:9]
wire _GEN_2 = _q_io_deq_valid | auto_out_0_d_valid; // @[Decoupled.scala:362:21]
wire winner_1_1 = ~auto_out_0_d_valid & _q_io_deq_valid; // @[Decoupled.scala:362:21]
wire winner_1_2 = ~_GEN_2 & _q_1_io_deq_valid; // @[Decoupled.scala:362:21]
wire _in_d_valid_T = auto_out_0_d_valid | _q_io_deq_valid; // @[Decoupled.scala:362:21]
reg state_1_0; // @[Arbiter.scala:88:26]
reg state_1_1; // @[Arbiter.scala:88:26]
reg state_1_2; // @[Arbiter.scala:88:26]
wire muxState_1_0 = idle_1 ? auto_out_0_d_valid : state_1_0; // @[Arbiter.scala:61:28, :88:26, :89:25]
wire muxState_1_1 = idle_1 ? winner_1_1 : state_1_1; // @[Arbiter.scala:61:28, :71:69, :88:26, :89:25]
wire muxState_1_2 = idle_1 ? winner_1_2 : state_1_2; // @[Arbiter.scala:61:28, :71:69, :88:26, :89:25]
assign in_d_valid = idle_1 ? _in_d_valid_T | _q_1_io_deq_valid : state_1_0 & auto_out_0_d_valid | state_1_1 & _q_io_deq_valid | state_1_2 & _q_1_io_deq_valid; // @[Mux.scala:30:73]
wire _in_d_bits_T_4 = muxState_1_0 & auto_out_0_d_bits_corrupt | muxState_1_1 & _q_io_deq_bits_corrupt | muxState_1_2 & _q_1_io_deq_bits_corrupt; // @[Mux.scala:30:73]
wire _in_d_bits_T_14 = muxState_1_0 & auto_out_0_d_bits_denied | muxState_1_1 & _q_io_deq_bits_denied | muxState_1_2 & _q_1_io_deq_bits_denied; // @[Mux.scala:30:73]
wire [3:0] _in_d_bits_T_24 = (muxState_1_0 ? auto_out_0_d_bits_source[4:1] : 4'h0) | (muxState_1_1 ? _q_io_deq_bits_source : 4'h0) | (muxState_1_2 ? _q_1_io_deq_bits_source : 4'h0); // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_29 = (muxState_1_0 ? auto_out_0_d_bits_size : 3'h0) | (muxState_1_1 ? _q_io_deq_bits_size : 3'h0) | (muxState_1_2 ? _q_1_io_deq_bits_size : 3'h0); // @[Mux.scala:30:73]
wire [1:0] _in_d_bits_T_34 = (~muxState_1_0 | _GEN_1 ? 2'h0 : auto_out_0_d_bits_param) | (muxState_1_1 ? _q_io_deq_bits_param : 2'h0) | (muxState_1_2 ? _q_1_io_deq_bits_param : 2'h0); // @[Mux.scala:30:73]
assign _in_d_bits_T_39 = (muxState_1_0 ? d_d_bits_opcode : 3'h0) | (muxState_1_1 ? _q_io_deq_bits_opcode : 3'h0) | (muxState_1_2 ? _q_1_io_deq_bits_opcode : 3'h0); // @[Mux.scala:30:73]
wire _toD_T_4 = auto_in_1_a_bits_opcode == 3'h6; // @[CacheCork.scala:77:37]
wire toD_1 = _toD_T_4 & auto_in_1_a_bits_param == 3'h2 | (&auto_in_1_a_bits_opcode); // @[CacheCork.scala:77:{37,54,73,97}, :78:37]
wire nodeIn_1_a_ready = toD_1 ? _q_3_io_enq_ready : a_a_1_ready; // @[Decoupled.scala:362:21]
wire a_a_1_valid = auto_in_1_a_valid & ~toD_1; // @[CacheCork.scala:77:97, :81:{33,36}]
wire _GEN_3 = _toD_T_4 | (&auto_in_1_a_bits_opcode); // @[CacheCork.scala:77:37, :78:37, :86:49]
wire [2:0] a_a_1_bits_opcode = _GEN_3 ? 3'h4 : auto_in_1_a_bits_opcode; // @[CacheCork.scala:42:9, :82:18, :86:{49,86}, :87:27]
wire winner_2_0 = auto_in_1_c_valid & (&auto_in_1_c_bits_opcode); // @[CacheCork.scala:102:{33,53}]
wire c_a_bits_a_mask_sub_sub_sub_0_1_1 = auto_in_1_c_bits_size > 3'h2; // @[Misc.scala:206:21]
wire c_a_bits_a_mask_sub_sub_size_1 = auto_in_1_c_bits_size[1:0] == 2'h2; // @[OneHot.scala:64:49]
wire c_a_bits_a_mask_sub_sub_0_1_1 = c_a_bits_a_mask_sub_sub_sub_0_1_1 | c_a_bits_a_mask_sub_sub_size_1 & ~(auto_in_1_c_bits_address[2]); // @[Misc.scala:206:21, :209:26, :210:26, :211:20, :215:{29,38}]
wire c_a_bits_a_mask_sub_sub_1_1_1 = c_a_bits_a_mask_sub_sub_sub_0_1_1 | c_a_bits_a_mask_sub_sub_size_1 & auto_in_1_c_bits_address[2]; // @[Misc.scala:206:21, :209:26, :210:26, :215:{29,38}]
wire c_a_bits_a_mask_sub_size_1 = auto_in_1_c_bits_size[1:0] == 2'h1; // @[OneHot.scala:64:49]
wire c_a_bits_a_mask_sub_0_2_1 = ~(auto_in_1_c_bits_address[2]) & ~(auto_in_1_c_bits_address[1]); // @[Misc.scala:210:26, :211:20, :214:27]
wire c_a_bits_a_mask_sub_0_1_1 = c_a_bits_a_mask_sub_sub_0_1_1 | c_a_bits_a_mask_sub_size_1 & c_a_bits_a_mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:{29,38}]
wire c_a_bits_a_mask_sub_1_2_1 = ~(auto_in_1_c_bits_address[2]) & auto_in_1_c_bits_address[1]; // @[Misc.scala:210:26, :211:20, :214:27]
wire c_a_bits_a_mask_sub_1_1_1 = c_a_bits_a_mask_sub_sub_0_1_1 | c_a_bits_a_mask_sub_size_1 & c_a_bits_a_mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:{29,38}]
wire c_a_bits_a_mask_sub_2_2_1 = auto_in_1_c_bits_address[2] & ~(auto_in_1_c_bits_address[1]); // @[Misc.scala:210:26, :211:20, :214:27]
wire c_a_bits_a_mask_sub_2_1_1 = c_a_bits_a_mask_sub_sub_1_1_1 | c_a_bits_a_mask_sub_size_1 & c_a_bits_a_mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:{29,38}]
wire c_a_bits_a_mask_sub_3_2_1 = auto_in_1_c_bits_address[2] & auto_in_1_c_bits_address[1]; // @[Misc.scala:210:26, :214:27]
wire c_a_bits_a_mask_sub_3_1_1 = c_a_bits_a_mask_sub_sub_1_1_1 | c_a_bits_a_mask_sub_size_1 & c_a_bits_a_mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:{29,38}]
wire _nodeIn_c_ready_T_2 = auto_in_1_c_bits_opcode == 3'h6; // @[CacheCork.scala:113:53]
wire nodeIn_1_c_ready = _nodeIn_c_ready_T_2 ? _q_2_io_enq_ready : c_a_1_ready; // @[Decoupled.scala:362:21]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire d_grant_1 = _in_d_bits_T_79 == 3'h5 | _in_d_bits_T_79 == 3'h4; // @[Mux.scala:30:73]
wire [3:0] _GEN_4 = {_pool_1_io_alloc_valid, d_first_counter_1}; // @[Edges.scala:229:27, :231:25]
assign nodeIn_1_d_valid = in_d_1_valid & ((|_GEN_4) | ~d_grant_1); // @[Edges.scala:231:25]
wire in_d_1_ready = auto_in_1_d_ready & ((|_GEN_4) | ~d_grant_1); // @[Edges.scala:231:25]
reg [2:0] nodeIn_d_bits_sink_r_1; // @[package.scala:88:63]
wire [2:0] nodeIn_1_d_bits_sink = d_first_1 ? _pool_1_io_alloc_bits : nodeIn_d_bits_sink_r_1; // @[package.scala:88:{42,63}]
wire _GEN_5 = auto_out_1_d_bits_opcode == 3'h1 & auto_out_1_d_bits_source[0]; // @[CacheCork.scala:42:9, :162:{33,51,71}]
wire [2:0] d_d_1_bits_opcode = auto_out_1_d_bits_opcode == 3'h0 & ~(auto_out_1_d_bits_source[0]) ? 3'h6 : _GEN_5 ? 3'h5 : auto_out_1_d_bits_opcode; // @[CacheCork.scala:42:9, :142:13, :162:{51,71,76}, :163:27, :166:{33,47,50,73}, :167:27]
reg [2:0] beatsLeft_2; // @[Arbiter.scala:60:30]
wire idle_2 = beatsLeft_2 == 3'h0; // @[CacheCork.scala:42:9]
wire winner_2_1 = ~winner_2_0 & a_a_1_valid; // @[CacheCork.scala:81:33, :102:33]
wire _nodeOut_a_valid_T_5 = winner_2_0 | a_a_1_valid; // @[CacheCork.scala:81:33, :102:33]
reg state_2_0; // @[Arbiter.scala:88:26]
reg state_2_1; // @[Arbiter.scala:88:26]
wire muxState_2_0 = idle_2 ? winner_2_0 : state_2_0; // @[CacheCork.scala:102:33]
wire muxState_2_1 = idle_2 ? winner_2_1 : state_2_1; // @[Arbiter.scala:61:28, :71:69, :88:26, :89:25]
assign c_a_1_ready = auto_out_1_a_ready & (idle_2 | state_2_0); // @[Arbiter.scala:61:28, :88:26, :92:24, :94:31]
assign a_a_1_ready = auto_out_1_a_ready & (idle_2 ? ~winner_2_0 : state_2_1); // @[CacheCork.scala:102:33]
wire x1_nodeOut_a_valid = idle_2 ? _nodeOut_a_valid_T_5 : state_2_0 & winner_2_0 | state_2_1 & a_a_1_valid; // @[Mux.scala:30:73]
reg [2:0] beatsLeft_3; // @[Arbiter.scala:60:30]
wire idle_3 = beatsLeft_3 == 3'h0; // @[CacheCork.scala:42:9]
wire _GEN_6 = _q_2_io_deq_valid | auto_out_1_d_valid; // @[Decoupled.scala:362:21]
wire winner_3_1 = ~auto_out_1_d_valid & _q_2_io_deq_valid; // @[Decoupled.scala:362:21]
wire winner_3_2 = ~_GEN_6 & _q_3_io_deq_valid; // @[Decoupled.scala:362:21]
wire _in_d_valid_T_8 = auto_out_1_d_valid | _q_2_io_deq_valid; // @[Decoupled.scala:362:21]
reg state_3_0; // @[Arbiter.scala:88:26]
reg state_3_1; // @[Arbiter.scala:88:26]
reg state_3_2; // @[Arbiter.scala:88:26]
wire muxState_3_0 = idle_3 ? auto_out_1_d_valid : state_3_0; // @[Arbiter.scala:61:28, :88:26, :89:25]
wire muxState_3_1 = idle_3 ? winner_3_1 : state_3_1; // @[Arbiter.scala:61:28, :71:69, :88:26, :89:25]
wire muxState_3_2 = idle_3 ? winner_3_2 : state_3_2; // @[Arbiter.scala:61:28, :71:69, :88:26, :89:25]
assign in_d_1_valid = idle_3 ? _in_d_valid_T_8 | _q_3_io_deq_valid : state_3_0 & auto_out_1_d_valid | state_3_1 & _q_2_io_deq_valid | state_3_2 & _q_3_io_deq_valid; // @[Mux.scala:30:73]
wire _in_d_bits_T_44 = muxState_3_0 & auto_out_1_d_bits_corrupt | muxState_3_1 & _q_2_io_deq_bits_corrupt | muxState_3_2 & _q_3_io_deq_bits_corrupt; // @[Mux.scala:30:73]
wire _in_d_bits_T_54 = muxState_3_0 & auto_out_1_d_bits_denied | muxState_3_1 & _q_2_io_deq_bits_denied | muxState_3_2 & _q_3_io_deq_bits_denied; // @[Mux.scala:30:73]
wire [3:0] _in_d_bits_T_64 = (muxState_3_0 ? auto_out_1_d_bits_source[4:1] : 4'h0) | (muxState_3_1 ? _q_2_io_deq_bits_source : 4'h0) | (muxState_3_2 ? _q_3_io_deq_bits_source : 4'h0); // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_69 = (muxState_3_0 ? auto_out_1_d_bits_size : 3'h0) | (muxState_3_1 ? _q_2_io_deq_bits_size : 3'h0) | (muxState_3_2 ? _q_3_io_deq_bits_size : 3'h0); // @[Mux.scala:30:73]
wire [1:0] _in_d_bits_T_74 = (~muxState_3_0 | _GEN_5 ? 2'h0 : auto_out_1_d_bits_param) | (muxState_3_1 ? _q_2_io_deq_bits_param : 2'h0) | (muxState_3_2 ? _q_3_io_deq_bits_param : 2'h0); // @[Mux.scala:30:73]
assign _in_d_bits_T_79 = (muxState_3_0 ? d_d_1_bits_opcode : 3'h0) | (muxState_3_1 ? _q_2_io_deq_bits_opcode : 3'h0) | (muxState_3_2 ? _q_3_io_deq_bits_opcode : 3'h0); // @[Mux.scala:30:73]
wire _toD_T_8 = auto_in_2_a_bits_opcode == 3'h6; // @[CacheCork.scala:77:37]
wire toD_2 = _toD_T_8 & auto_in_2_a_bits_param == 3'h2 | (&auto_in_2_a_bits_opcode); // @[CacheCork.scala:77:{37,54,73,97}, :78:37]
wire nodeIn_2_a_ready = toD_2 ? _q_5_io_enq_ready : a_a_2_ready; // @[Decoupled.scala:362:21]
wire a_a_2_valid = auto_in_2_a_valid & ~toD_2; // @[CacheCork.scala:77:97, :81:{33,36}]
wire _GEN_7 = _toD_T_8 | (&auto_in_2_a_bits_opcode); // @[CacheCork.scala:77:37, :78:37, :86:49]
wire [2:0] a_a_2_bits_opcode = _GEN_7 ? 3'h4 : auto_in_2_a_bits_opcode; // @[CacheCork.scala:42:9, :82:18, :86:{49,86}, :87:27]
wire winner_4_0 = auto_in_2_c_valid & (&auto_in_2_c_bits_opcode); // @[CacheCork.scala:102:{33,53}]
wire c_a_bits_a_mask_sub_sub_sub_0_1_2 = auto_in_2_c_bits_size > 3'h2; // @[Misc.scala:206:21]
wire c_a_bits_a_mask_sub_sub_size_2 = auto_in_2_c_bits_size[1:0] == 2'h2; // @[OneHot.scala:64:49]
wire c_a_bits_a_mask_sub_sub_0_1_2 = c_a_bits_a_mask_sub_sub_sub_0_1_2 | c_a_bits_a_mask_sub_sub_size_2 & ~(auto_in_2_c_bits_address[2]); // @[Misc.scala:206:21, :209:26, :210:26, :211:20, :215:{29,38}]
wire c_a_bits_a_mask_sub_sub_1_1_2 = c_a_bits_a_mask_sub_sub_sub_0_1_2 | c_a_bits_a_mask_sub_sub_size_2 & auto_in_2_c_bits_address[2]; // @[Misc.scala:206:21, :209:26, :210:26, :215:{29,38}]
wire c_a_bits_a_mask_sub_size_2 = auto_in_2_c_bits_size[1:0] == 2'h1; // @[OneHot.scala:64:49]
wire c_a_bits_a_mask_sub_0_2_2 = ~(auto_in_2_c_bits_address[2]) & ~(auto_in_2_c_bits_address[1]); // @[Misc.scala:210:26, :211:20, :214:27]
wire c_a_bits_a_mask_sub_0_1_2 = c_a_bits_a_mask_sub_sub_0_1_2 | c_a_bits_a_mask_sub_size_2 & c_a_bits_a_mask_sub_0_2_2; // @[Misc.scala:209:26, :214:27, :215:{29,38}]
wire c_a_bits_a_mask_sub_1_2_2 = ~(auto_in_2_c_bits_address[2]) & auto_in_2_c_bits_address[1]; // @[Misc.scala:210:26, :211:20, :214:27]
wire c_a_bits_a_mask_sub_1_1_2 = c_a_bits_a_mask_sub_sub_0_1_2 | c_a_bits_a_mask_sub_size_2 & c_a_bits_a_mask_sub_1_2_2; // @[Misc.scala:209:26, :214:27, :215:{29,38}]
wire c_a_bits_a_mask_sub_2_2_2 = auto_in_2_c_bits_address[2] & ~(auto_in_2_c_bits_address[1]); // @[Misc.scala:210:26, :211:20, :214:27]
wire c_a_bits_a_mask_sub_2_1_2 = c_a_bits_a_mask_sub_sub_1_1_2 | c_a_bits_a_mask_sub_size_2 & c_a_bits_a_mask_sub_2_2_2; // @[Misc.scala:209:26, :214:27, :215:{29,38}]
wire c_a_bits_a_mask_sub_3_2_2 = auto_in_2_c_bits_address[2] & auto_in_2_c_bits_address[1]; // @[Misc.scala:210:26, :214:27]
wire c_a_bits_a_mask_sub_3_1_2 = c_a_bits_a_mask_sub_sub_1_1_2 | c_a_bits_a_mask_sub_size_2 & c_a_bits_a_mask_sub_3_2_2; // @[Misc.scala:209:26, :214:27, :215:{29,38}]
wire _nodeIn_c_ready_T_4 = auto_in_2_c_bits_opcode == 3'h6; // @[CacheCork.scala:113:53]
wire nodeIn_2_c_ready = _nodeIn_c_ready_T_4 ? _q_4_io_enq_ready : c_a_2_ready; // @[Decoupled.scala:362:21]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire d_grant_2 = _in_d_bits_T_119 == 3'h5 | _in_d_bits_T_119 == 3'h4; // @[Mux.scala:30:73]
wire [3:0] _GEN_8 = {_pool_2_io_alloc_valid, d_first_counter_2}; // @[Edges.scala:229:27, :231:25]
assign nodeIn_2_d_valid = in_d_2_valid & ((|_GEN_8) | ~d_grant_2); // @[Edges.scala:231:25]
wire in_d_2_ready = auto_in_2_d_ready & ((|_GEN_8) | ~d_grant_2); // @[Edges.scala:231:25]
reg [2:0] nodeIn_d_bits_sink_r_2; // @[package.scala:88:63]
wire [2:0] nodeIn_2_d_bits_sink = d_first_2 ? _pool_2_io_alloc_bits : nodeIn_d_bits_sink_r_2; // @[package.scala:88:{42,63}]
wire _GEN_9 = auto_out_2_d_bits_opcode == 3'h1 & auto_out_2_d_bits_source[0]; // @[CacheCork.scala:42:9, :162:{33,51,71}]
wire [2:0] d_d_2_bits_opcode = auto_out_2_d_bits_opcode == 3'h0 & ~(auto_out_2_d_bits_source[0]) ? 3'h6 : _GEN_9 ? 3'h5 : auto_out_2_d_bits_opcode; // @[CacheCork.scala:42:9, :142:13, :162:{51,71,76}, :163:27, :166:{33,47,50,73}, :167:27]
reg [2:0] beatsLeft_4; // @[Arbiter.scala:60:30]
wire idle_4 = beatsLeft_4 == 3'h0; // @[CacheCork.scala:42:9]
wire winner_4_1 = ~winner_4_0 & a_a_2_valid; // @[CacheCork.scala:81:33, :102:33]
wire _nodeOut_a_valid_T_10 = winner_4_0 | a_a_2_valid; // @[CacheCork.scala:81:33, :102:33]
reg state_4_0; // @[Arbiter.scala:88:26]
reg state_4_1; // @[Arbiter.scala:88:26]
wire muxState_4_0 = idle_4 ? winner_4_0 : state_4_0; // @[CacheCork.scala:102:33]
wire muxState_4_1 = idle_4 ? winner_4_1 : state_4_1; // @[Arbiter.scala:61:28, :71:69, :88:26, :89:25]
assign c_a_2_ready = auto_out_2_a_ready & (idle_4 | state_4_0); // @[Arbiter.scala:61:28, :88:26, :92:24, :94:31]
assign a_a_2_ready = auto_out_2_a_ready & (idle_4 ? ~winner_4_0 : state_4_1); // @[CacheCork.scala:102:33]
wire x1_nodeOut_1_a_valid = idle_4 ? _nodeOut_a_valid_T_10 : state_4_0 & winner_4_0 | state_4_1 & a_a_2_valid; // @[Mux.scala:30:73]
reg [2:0] beatsLeft_5; // @[Arbiter.scala:60:30]
wire idle_5 = beatsLeft_5 == 3'h0; // @[CacheCork.scala:42:9]
wire _GEN_10 = _q_4_io_deq_valid | auto_out_2_d_valid; // @[Decoupled.scala:362:21]
wire winner_5_1 = ~auto_out_2_d_valid & _q_4_io_deq_valid; // @[Decoupled.scala:362:21]
wire winner_5_2 = ~_GEN_10 & _q_5_io_deq_valid; // @[Decoupled.scala:362:21]
wire _in_d_valid_T_16 = auto_out_2_d_valid | _q_4_io_deq_valid; // @[Decoupled.scala:362:21]
reg state_5_0; // @[Arbiter.scala:88:26]
reg state_5_1; // @[Arbiter.scala:88:26]
reg state_5_2; // @[Arbiter.scala:88:26]
wire muxState_5_0 = idle_5 ? auto_out_2_d_valid : state_5_0; // @[Arbiter.scala:61:28, :88:26, :89:25]
wire muxState_5_1 = idle_5 ? winner_5_1 : state_5_1; // @[Arbiter.scala:61:28, :71:69, :88:26, :89:25]
wire muxState_5_2 = idle_5 ? winner_5_2 : state_5_2; // @[Arbiter.scala:61:28, :71:69, :88:26, :89:25]
assign in_d_2_valid = idle_5 ? _in_d_valid_T_16 | _q_5_io_deq_valid : state_5_0 & auto_out_2_d_valid | state_5_1 & _q_4_io_deq_valid | state_5_2 & _q_5_io_deq_valid; // @[Mux.scala:30:73]
wire _in_d_bits_T_84 = muxState_5_0 & auto_out_2_d_bits_corrupt | muxState_5_1 & _q_4_io_deq_bits_corrupt | muxState_5_2 & _q_5_io_deq_bits_corrupt; // @[Mux.scala:30:73]
wire _in_d_bits_T_94 = muxState_5_0 & auto_out_2_d_bits_denied | muxState_5_1 & _q_4_io_deq_bits_denied | muxState_5_2 & _q_5_io_deq_bits_denied; // @[Mux.scala:30:73]
wire [3:0] _in_d_bits_T_104 = (muxState_5_0 ? auto_out_2_d_bits_source[4:1] : 4'h0) | (muxState_5_1 ? _q_4_io_deq_bits_source : 4'h0) | (muxState_5_2 ? _q_5_io_deq_bits_source : 4'h0); // @[Mux.scala:30:73]
wire [2:0] _in_d_bits_T_109 = (muxState_5_0 ? auto_out_2_d_bits_size : 3'h0) | (muxState_5_1 ? _q_4_io_deq_bits_size : 3'h0) | (muxState_5_2 ? _q_5_io_deq_bits_size : 3'h0); // @[Mux.scala:30:73]
wire [1:0] _in_d_bits_T_114 = (~muxState_5_0 | _GEN_9 ? 2'h0 : auto_out_2_d_bits_param) | (muxState_5_1 ? _q_4_io_deq_bits_param : 2'h0) | (muxState_5_2 ? _q_5_io_deq_bits_param : 2'h0); // @[Mux.scala:30:73]
assign _in_d_bits_T_119 = (muxState_5_0 ? d_d_2_bits_opcode : 3'h0) | (muxState_5_1 ? _q_4_io_deq_bits_opcode : 3'h0) | (muxState_5_2 ? _q_5_io_deq_bits_opcode : 3'h0); // @[Mux.scala:30:73]
wire _toD_T_12 = auto_in_3_a_bits_opcode == 3'h6; // @[CacheCork.scala:77:37]
wire toD_3 = _toD_T_12 & auto_in_3_a_bits_param == 3'h2 | (&auto_in_3_a_bits_opcode); // @[CacheCork.scala:77:{37,54,73,97}, :78:37]
wire nodeIn_3_a_ready = toD_3 ? _q_7_io_enq_ready : a_a_3_ready; // @[Decoupled.scala:362:21]
wire a_a_3_valid = auto_in_3_a_valid & ~toD_3; // @[CacheCork.scala:77:97, :81:{33,36}]
wire _GEN_11 = _toD_T_12 | (&auto_in_3_a_bits_opcode); // @[CacheCork.scala:77:37, :78:37, :86:49]
wire [2:0] a_a_3_bits_opcode = _GEN_11 ? 3'h4 : auto_in_3_a_bits_opcode; // @[CacheCork.scala:42:9, :82:18, :86:{49,86}, :87:27]
wire winner_6_0 = auto_in_3_c_valid & (&auto_in_3_c_bits_opcode); // @[CacheCork.scala:102:{33,53}]
wire c_a_bits_a_mask_sub_sub_sub_0_1_3 = auto_in_3_c_bits_size > 3'h2; // @[Misc.scala:206:21]
wire c_a_bits_a_mask_sub_sub_size_3 = auto_in_3_c_bits_size[1:0] == 2'h2; // @[OneHot.scala:64:49]
wire c_a_bits_a_mask_sub_sub_0_1_3 = c_a_bits_a_mask_sub_sub_sub_0_1_3 | c_a_bits_a_mask_sub_sub_size_3 & ~(auto_in_3_c_bits_address[2]); // @[Misc.scala:206:21, :209:26, :210:26, :211:20, :215:{29,38}]
wire c_a_bits_a_mask_sub_sub_1_1_3 = c_a_bits_a_mask_sub_sub_sub_0_1_3 | c_a_bits_a_mask_sub_sub_size_3 & auto_in_3_c_bits_address[2]; // @[Misc.scala:206:21, :209:26, :210:26, :215:{29,38}]
wire c_a_bits_a_mask_sub_size_3 = auto_in_3_c_bits_size[1:0] == 2'h1; // @[OneHot.scala:64:49]
wire c_a_bits_a_mask_sub_0_2_3 = ~(auto_in_3_c_bits_address[2]) & ~(auto_in_3_c_bits_address[1]); // @[Misc.scala:210:26, :211:20, :214:27]
wire c_a_bits_a_mask_sub_0_1_3 = c_a_bits_a_mask_sub_sub_0_1_3 | c_a_bits_a_mask_sub_size_3 & c_a_bits_a_mask_sub_0_2_3; // @[Misc.scala:209:26, :214:27, :215:{29,38}]
wire c_a_bits_a_mask_sub_1_2_3 = ~(auto_in_3_c_bits_address[2]) & auto_in_3_c_bits_address[1]; // @[Misc.scala:210:26, :211:20, :214:27]
wire c_a_bits_a_mask_sub_1_1_3 = c_a_bits_a_mask_sub_sub_0_1_3 | c_a_bits_a_mask_sub_size_3 & c_a_bits_a_mask_sub_1_2_3; // @[Misc.scala:209:26, :214:27, :215:{29,38}]
wire c_a_bits_a_mask_sub_2_2_3 = auto_in_3_c_bits_address[2] & ~(auto_in_3_c_bits_address[1]); // @[Misc.scala:210:26, :211:20, :214:27]
wire c_a_bits_a_mask_sub_2_1_3 = c_a_bits_a_mask_sub_sub_1_1_3 | c_a_bits_a_mask_sub_size_3 & c_a_bits_a_mask_sub_2_2_3; // @[Misc.scala:209:26, :214:27, :215:{29,38}]
wire c_a_bits_a_mask_sub_3_2_3 = auto_in_3_c_bits_address[2] & auto_in_3_c_bits_address[1]; // @[Misc.scala:210:26, :214:27]
wire c_a_bits_a_mask_sub_3_1_3 = c_a_bits_a_mask_sub_sub_1_1_3 | c_a_bits_a_mask_sub_size_3 & c_a_bits_a_mask_sub_3_2_3; // @[Misc.scala:209:26, :214:27, :215:{29,38}]
wire _nodeIn_c_ready_T_6 = auto_in_3_c_bits_opcode == 3'h6; // @[CacheCork.scala:113:53]
wire nodeIn_3_c_ready = _nodeIn_c_ready_T_6 ? _q_6_io_enq_ready : c_a_3_ready; // @[Decoupled.scala:362:21]
reg [2:0] d_first_counter_3; // @[Edges.scala:229:27]
wire d_first_3 = d_first_counter_3 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire d_grant_3 = _in_d_bits_T_159 == 3'h5 | _in_d_bits_T_159 == 3'h4; // @[Mux.scala:30:73]
wire [3:0] _GEN_12 = {_pool_3_io_alloc_valid, d_first_counter_3}; // @[Edges.scala:229:27, :231:25]
assign nodeIn_3_d_valid = in_d_3_valid & ((|_GEN_12) | ~d_grant_3); // @[Edges.scala:231:25]
wire in_d_3_ready = auto_in_3_d_ready & ((|_GEN_12) | ~d_grant_3); // @[Edges.scala:231:25]
reg [2:0] nodeIn_d_bits_sink_r_3; // @[package.scala:88:63]
wire [2:0] nodeIn_3_d_bits_sink = d_first_3 ? _pool_3_io_alloc_bits : nodeIn_d_bits_sink_r_3; // @[package.scala:88:{42,63}]
wire _GEN_13 = auto_out_3_d_bits_opcode == 3'h1 & auto_out_3_d_bits_source[0]; // @[CacheCork.scala:42:9, :162:{33,51,71}]
wire [2:0] d_d_3_bits_opcode = auto_out_3_d_bits_opcode == 3'h0 & ~(auto_out_3_d_bits_source[0]) ? 3'h6 : _GEN_13 ? 3'h5 : auto_out_3_d_bits_opcode; // @[CacheCork.scala:42:9, :142:13, :162:{51,71,76}, :163:27, :166:{33,47,50,73}, :167:27]
reg [2:0] beatsLeft_6; // @[Arbiter.scala:60:30]
wire idle_6 = beatsLeft_6 == 3'h0; // @[CacheCork.scala:42:9]
wire winner_6_1 = ~winner_6_0 & a_a_3_valid; // @[CacheCork.scala:81:33, :102:33]
wire _nodeOut_a_valid_T_15 = winner_6_0 | a_a_3_valid; // @[CacheCork.scala:81:33, :102:33]
reg state_6_0; // @[Arbiter.scala:88:26]
reg state_6_1; // @[Arbiter.scala:88:26]
wire muxState_6_0 = idle_6 ? winner_6_0 : state_6_0; // @[CacheCork.scala:102:33]
wire muxState_6_1 = idle_6 ? winner_6_1 : state_6_1; // @[Arbiter.scala:61:28, :71:69, :88:26, :89:25]
assign c_a_3_ready = auto_out_3_a_ready & (idle_6 | state_6_0); // @[Arbiter.scala:61:28, :88:26, :92:24, :94:31]
assign a_a_3_ready = auto_out_3_a_ready & (idle_6 ? ~winner_6_0 : state_6_1); // @[CacheCork.scala:102:33]
wire x1_nodeOut_2_a_valid = idle_6 ? _nodeOut_a_valid_T_15 : state_6_0 & winner_6_0 | state_6_1 & a_a_3_valid; // @[Mux.scala:30:73]
reg [2:0] beatsLeft_7; // @[Arbiter.scala:60:30]
wire idle_7 = beatsLeft_7 == 3'h0; // @[CacheCork.scala:42:9]
wire _GEN_14 = _q_6_io_deq_valid | auto_out_3_d_valid; // @[Decoupled.scala:362:21]
wire winner_7_1 = ~auto_out_3_d_valid & _q_6_io_deq_valid; // @[Decoupled.scala:362:21]
wire winner_7_2 = ~_GEN_14 & _q_7_io_deq_valid; // @[Decoupled.scala:362:21]
wire _in_d_valid_T_24 = auto_out_3_d_valid | _q_6_io_deq_valid; // @[Decoupled.scala:362:21] |
Generate the Verilog code corresponding to this FIRRTL code module MulRawFN_21 :
output io : { flip a : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, flip b : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}}
inst mulFullRaw of MulFullRawFN_21
connect mulFullRaw.io.a.sig, io.a.sig
connect mulFullRaw.io.a.sExp, io.a.sExp
connect mulFullRaw.io.a.sign, io.a.sign
connect mulFullRaw.io.a.isZero, io.a.isZero
connect mulFullRaw.io.a.isInf, io.a.isInf
connect mulFullRaw.io.a.isNaN, io.a.isNaN
connect mulFullRaw.io.b.sig, io.b.sig
connect mulFullRaw.io.b.sExp, io.b.sExp
connect mulFullRaw.io.b.sign, io.b.sign
connect mulFullRaw.io.b.isZero, io.b.isZero
connect mulFullRaw.io.b.isInf, io.b.isInf
connect mulFullRaw.io.b.isNaN, io.b.isNaN
connect io.invalidExc, mulFullRaw.io.invalidExc
connect io.rawOut, mulFullRaw.io.rawOut
node _io_rawOut_sig_T = shr(mulFullRaw.io.rawOut.sig, 22)
node _io_rawOut_sig_T_1 = bits(mulFullRaw.io.rawOut.sig, 21, 0)
node _io_rawOut_sig_T_2 = orr(_io_rawOut_sig_T_1)
node _io_rawOut_sig_T_3 = cat(_io_rawOut_sig_T, _io_rawOut_sig_T_2)
connect io.rawOut.sig, _io_rawOut_sig_T_3 | module MulRawFN_21( // @[MulRecFN.scala:75:7]
input io_a_isNaN, // @[MulRecFN.scala:77:16]
input io_a_isInf, // @[MulRecFN.scala:77:16]
input io_a_isZero, // @[MulRecFN.scala:77:16]
input io_a_sign, // @[MulRecFN.scala:77:16]
input [9:0] io_a_sExp, // @[MulRecFN.scala:77:16]
input [24:0] io_a_sig, // @[MulRecFN.scala:77:16]
input io_b_isNaN, // @[MulRecFN.scala:77:16]
input io_b_isInf, // @[MulRecFN.scala:77:16]
input io_b_isZero, // @[MulRecFN.scala:77:16]
input io_b_sign, // @[MulRecFN.scala:77:16]
input [9:0] io_b_sExp, // @[MulRecFN.scala:77:16]
input [24:0] io_b_sig, // @[MulRecFN.scala:77:16]
output io_invalidExc, // @[MulRecFN.scala:77:16]
output io_rawOut_isNaN, // @[MulRecFN.scala:77:16]
output io_rawOut_isInf, // @[MulRecFN.scala:77:16]
output io_rawOut_isZero, // @[MulRecFN.scala:77:16]
output io_rawOut_sign, // @[MulRecFN.scala:77:16]
output [9:0] io_rawOut_sExp, // @[MulRecFN.scala:77:16]
output [26:0] io_rawOut_sig // @[MulRecFN.scala:77:16]
);
wire [47:0] _mulFullRaw_io_rawOut_sig; // @[MulRecFN.scala:84:28]
wire io_a_isNaN_0 = io_a_isNaN; // @[MulRecFN.scala:75:7]
wire io_a_isInf_0 = io_a_isInf; // @[MulRecFN.scala:75:7]
wire io_a_isZero_0 = io_a_isZero; // @[MulRecFN.scala:75:7]
wire io_a_sign_0 = io_a_sign; // @[MulRecFN.scala:75:7]
wire [9:0] io_a_sExp_0 = io_a_sExp; // @[MulRecFN.scala:75:7]
wire [24:0] io_a_sig_0 = io_a_sig; // @[MulRecFN.scala:75:7]
wire io_b_isNaN_0 = io_b_isNaN; // @[MulRecFN.scala:75:7]
wire io_b_isInf_0 = io_b_isInf; // @[MulRecFN.scala:75:7]
wire io_b_isZero_0 = io_b_isZero; // @[MulRecFN.scala:75:7]
wire io_b_sign_0 = io_b_sign; // @[MulRecFN.scala:75:7]
wire [9:0] io_b_sExp_0 = io_b_sExp; // @[MulRecFN.scala:75:7]
wire [24:0] io_b_sig_0 = io_b_sig; // @[MulRecFN.scala:75:7]
wire [26:0] _io_rawOut_sig_T_3; // @[MulRecFN.scala:93:10]
wire io_rawOut_isNaN_0; // @[MulRecFN.scala:75:7]
wire io_rawOut_isInf_0; // @[MulRecFN.scala:75:7]
wire io_rawOut_isZero_0; // @[MulRecFN.scala:75:7]
wire io_rawOut_sign_0; // @[MulRecFN.scala:75:7]
wire [9:0] io_rawOut_sExp_0; // @[MulRecFN.scala:75:7]
wire [26:0] io_rawOut_sig_0; // @[MulRecFN.scala:75:7]
wire io_invalidExc_0; // @[MulRecFN.scala:75:7]
wire [25:0] _io_rawOut_sig_T = _mulFullRaw_io_rawOut_sig[47:22]; // @[MulRecFN.scala:84:28, :93:15]
wire [21:0] _io_rawOut_sig_T_1 = _mulFullRaw_io_rawOut_sig[21:0]; // @[MulRecFN.scala:84:28, :93:37]
wire _io_rawOut_sig_T_2 = |_io_rawOut_sig_T_1; // @[MulRecFN.scala:93:{37,55}]
assign _io_rawOut_sig_T_3 = {_io_rawOut_sig_T, _io_rawOut_sig_T_2}; // @[MulRecFN.scala:93:{10,15,55}]
assign io_rawOut_sig_0 = _io_rawOut_sig_T_3; // @[MulRecFN.scala:75:7, :93:10]
MulFullRawFN_21 mulFullRaw ( // @[MulRecFN.scala:84:28]
.io_a_isNaN (io_a_isNaN_0), // @[MulRecFN.scala:75:7]
.io_a_isInf (io_a_isInf_0), // @[MulRecFN.scala:75:7]
.io_a_isZero (io_a_isZero_0), // @[MulRecFN.scala:75:7]
.io_a_sign (io_a_sign_0), // @[MulRecFN.scala:75:7]
.io_a_sExp (io_a_sExp_0), // @[MulRecFN.scala:75:7]
.io_a_sig (io_a_sig_0), // @[MulRecFN.scala:75:7]
.io_b_isNaN (io_b_isNaN_0), // @[MulRecFN.scala:75:7]
.io_b_isInf (io_b_isInf_0), // @[MulRecFN.scala:75:7]
.io_b_isZero (io_b_isZero_0), // @[MulRecFN.scala:75:7]
.io_b_sign (io_b_sign_0), // @[MulRecFN.scala:75:7]
.io_b_sExp (io_b_sExp_0), // @[MulRecFN.scala:75:7]
.io_b_sig (io_b_sig_0), // @[MulRecFN.scala:75:7]
.io_invalidExc (io_invalidExc_0),
.io_rawOut_isNaN (io_rawOut_isNaN_0),
.io_rawOut_isInf (io_rawOut_isInf_0),
.io_rawOut_isZero (io_rawOut_isZero_0),
.io_rawOut_sign (io_rawOut_sign_0),
.io_rawOut_sExp (io_rawOut_sExp_0),
.io_rawOut_sig (_mulFullRaw_io_rawOut_sig)
); // @[MulRecFN.scala:84:28]
assign io_invalidExc = io_invalidExc_0; // @[MulRecFN.scala:75:7]
assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulRecFN.scala:75:7]
assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulRecFN.scala:75:7]
assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulRecFN.scala:75:7]
assign io_rawOut_sign = io_rawOut_sign_0; // @[MulRecFN.scala:75:7]
assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulRecFN.scala:75:7]
assign io_rawOut_sig = io_rawOut_sig_0; // @[MulRecFN.scala:75:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_106 :
input clock : Clock
input reset : Reset
output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], credit_return : UInt<10>, vc_free : UInt<10>}}
wire _in_flight_WIRE : UInt<1>[10]
connect _in_flight_WIRE[0], UInt<1>(0h0)
connect _in_flight_WIRE[1], UInt<1>(0h0)
connect _in_flight_WIRE[2], UInt<1>(0h0)
connect _in_flight_WIRE[3], UInt<1>(0h0)
connect _in_flight_WIRE[4], UInt<1>(0h0)
connect _in_flight_WIRE[5], UInt<1>(0h0)
connect _in_flight_WIRE[6], UInt<1>(0h0)
connect _in_flight_WIRE[7], UInt<1>(0h0)
connect _in_flight_WIRE[8], UInt<1>(0h0)
connect _in_flight_WIRE[9], UInt<1>(0h0)
regreset in_flight : UInt<1>[10], clock, reset, _in_flight_WIRE
when io.in.flit[0].valid :
when io.in.flit[0].bits.head :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1)
node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
when io.in.flit[0].bits.tail :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)
node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T_4 :
node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0))
node _T_6 = or(_T_5, UInt<1>(0h0))
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1
assert(clock, _T_6, UInt<1>(0h1), "") : assert_1
node _T_10 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1))
node _T_11 = or(_T_10, UInt<1>(0h0))
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2
assert(clock, _T_11, UInt<1>(0h1), "") : assert_2
node _T_15 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2))
node _T_16 = or(_T_15, UInt<1>(0h0))
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3
assert(clock, _T_16, UInt<1>(0h1), "") : assert_3
node _T_20 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3))
node _T_21 = or(_T_20, UInt<1>(0h0))
node _T_22 = asUInt(reset)
node _T_23 = eq(_T_22, UInt<1>(0h0))
when _T_23 :
node _T_24 = eq(_T_21, UInt<1>(0h0))
when _T_24 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_4
assert(clock, _T_21, UInt<1>(0h1), "") : assert_4
node _T_25 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h4))
node _T_26 = or(_T_25, UInt<1>(0h0))
node _T_27 = asUInt(reset)
node _T_28 = eq(_T_27, UInt<1>(0h0))
when _T_28 :
node _T_29 = eq(_T_26, UInt<1>(0h0))
when _T_29 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_5
assert(clock, _T_26, UInt<1>(0h1), "") : assert_5
node _T_30 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h5))
node _T_31 = or(_T_30, UInt<1>(0h0))
node _T_32 = asUInt(reset)
node _T_33 = eq(_T_32, UInt<1>(0h0))
when _T_33 :
node _T_34 = eq(_T_31, UInt<1>(0h0))
when _T_34 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_6
assert(clock, _T_31, UInt<1>(0h1), "") : assert_6
node _T_35 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h6))
node _T_36 = or(_T_35, UInt<1>(0h0))
node _T_37 = asUInt(reset)
node _T_38 = eq(_T_37, UInt<1>(0h0))
when _T_38 :
node _T_39 = eq(_T_36, UInt<1>(0h0))
when _T_39 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_7
assert(clock, _T_36, UInt<1>(0h1), "") : assert_7
node _T_40 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h7))
node _T_41 = or(_T_40, UInt<1>(0h0))
node _T_42 = asUInt(reset)
node _T_43 = eq(_T_42, UInt<1>(0h0))
when _T_43 :
node _T_44 = eq(_T_41, UInt<1>(0h0))
when _T_44 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_8
assert(clock, _T_41, UInt<1>(0h1), "") : assert_8
node _T_45 = neq(io.in.flit[0].bits.virt_channel_id, UInt<4>(0h8))
node _T_46 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_47 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_48 = and(_T_46, _T_47)
node _T_49 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_50 = and(_T_48, _T_49)
node _T_51 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h3))
node _T_52 = and(_T_50, _T_51)
node _T_53 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_54 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_55 = and(_T_53, _T_54)
node _T_56 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_57 = and(_T_55, _T_56)
node _T_58 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h3))
node _T_59 = and(_T_57, _T_58)
node _T_60 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_61 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_62 = and(_T_60, _T_61)
node _T_63 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_64 = and(_T_62, _T_63)
node _T_65 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_66 = and(_T_64, _T_65)
node _T_67 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_68 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_69 = and(_T_67, _T_68)
node _T_70 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_71 = and(_T_69, _T_70)
node _T_72 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h3))
node _T_73 = and(_T_71, _T_72)
node _T_74 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_75 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_76 = and(_T_74, _T_75)
node _T_77 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_78 = and(_T_76, _T_77)
node _T_79 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h3))
node _T_80 = and(_T_78, _T_79)
node _T_81 = or(_T_52, _T_59)
node _T_82 = or(_T_81, _T_66)
node _T_83 = or(_T_82, _T_73)
node _T_84 = or(_T_83, _T_80)
node _T_85 = or(_T_45, _T_84)
node _T_86 = asUInt(reset)
node _T_87 = eq(_T_86, UInt<1>(0h0))
when _T_87 :
node _T_88 = eq(_T_85, UInt<1>(0h0))
when _T_88 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_9
assert(clock, _T_85, UInt<1>(0h1), "") : assert_9
node _T_89 = neq(io.in.flit[0].bits.virt_channel_id, UInt<4>(0h9))
node _T_90 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_91 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_92 = and(_T_90, _T_91)
node _T_93 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_94 = and(_T_92, _T_93)
node _T_95 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h3))
node _T_96 = and(_T_94, _T_95)
node _T_97 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_98 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_99 = and(_T_97, _T_98)
node _T_100 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_101 = and(_T_99, _T_100)
node _T_102 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h3))
node _T_103 = and(_T_101, _T_102)
node _T_104 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_105 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_106 = and(_T_104, _T_105)
node _T_107 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_108 = and(_T_106, _T_107)
node _T_109 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_110 = and(_T_108, _T_109)
node _T_111 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_112 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_113 = and(_T_111, _T_112)
node _T_114 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_115 = and(_T_113, _T_114)
node _T_116 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h3))
node _T_117 = and(_T_115, _T_116)
node _T_118 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_119 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_120 = and(_T_118, _T_119)
node _T_121 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_122 = and(_T_120, _T_121)
node _T_123 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h3))
node _T_124 = and(_T_122, _T_123)
node _T_125 = or(_T_96, _T_103)
node _T_126 = or(_T_125, _T_110)
node _T_127 = or(_T_126, _T_117)
node _T_128 = or(_T_127, _T_124)
node _T_129 = or(_T_89, _T_128)
node _T_130 = asUInt(reset)
node _T_131 = eq(_T_130, UInt<1>(0h0))
when _T_131 :
node _T_132 = eq(_T_129, UInt<1>(0h0))
when _T_132 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_10
assert(clock, _T_129, UInt<1>(0h1), "") : assert_10 | module NoCMonitor_106( // @[Monitor.scala:11:7]
input clock, // @[Monitor.scala:11:7]
input reset, // @[Monitor.scala:11:7]
input io_in_flit_0_valid, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_head, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14]
input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14]
input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14]
input [2:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14]
input [3:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14]
);
reg in_flight_0; // @[Monitor.scala:16:26]
reg in_flight_1; // @[Monitor.scala:16:26]
reg in_flight_2; // @[Monitor.scala:16:26]
reg in_flight_3; // @[Monitor.scala:16:26]
reg in_flight_4; // @[Monitor.scala:16:26]
reg in_flight_5; // @[Monitor.scala:16:26]
reg in_flight_6; // @[Monitor.scala:16:26]
reg in_flight_7; // @[Monitor.scala:16:26]
reg in_flight_8; // @[Monitor.scala:16:26]
reg in_flight_9; // @[Monitor.scala:16:26]
wire _GEN = io_in_flit_0_bits_virt_channel_id == 4'h0; // @[Monitor.scala:21:46]
wire _GEN_0 = io_in_flit_0_bits_virt_channel_id == 4'h1; // @[Monitor.scala:21:46]
wire _GEN_1 = io_in_flit_0_bits_virt_channel_id == 4'h2; // @[Monitor.scala:21:46]
wire _GEN_2 = io_in_flit_0_bits_virt_channel_id == 4'h3; // @[Monitor.scala:21:46]
wire _GEN_3 = io_in_flit_0_bits_virt_channel_id == 4'h4; // @[Monitor.scala:21:46]
wire _GEN_4 = io_in_flit_0_bits_virt_channel_id == 4'h5; // @[Monitor.scala:21:46]
wire _GEN_5 = io_in_flit_0_bits_virt_channel_id == 4'h6; // @[Monitor.scala:21:46]
wire _GEN_6 = io_in_flit_0_bits_virt_channel_id == 4'h7; // @[Monitor.scala:21:46] |
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_169 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>}
node _io_out_d_T = mul(io.in_a, io.in_b)
node _io_out_d_T_1 = add(_io_out_d_T, io.in_c)
node _io_out_d_T_2 = tail(_io_out_d_T_1, 1)
node _io_out_d_T_3 = asSInt(_io_out_d_T_2)
connect io.out_d, _io_out_d_T_3 | module MacUnit_169( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [19:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54]
assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLInterconnectCoupler_cbus_to_plic :
input clock : Clock
input reset : Reset
output auto : { fragmenter_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip tl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
inst fragmenter of TLFragmenter_PLIC
connect fragmenter.clock, clock
connect fragmenter.reset, reset
wire tlOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate tlOut.d.bits.corrupt
invalidate tlOut.d.bits.data
invalidate tlOut.d.bits.denied
invalidate tlOut.d.bits.sink
invalidate tlOut.d.bits.source
invalidate tlOut.d.bits.size
invalidate tlOut.d.bits.param
invalidate tlOut.d.bits.opcode
invalidate tlOut.d.valid
invalidate tlOut.d.ready
invalidate tlOut.a.bits.corrupt
invalidate tlOut.a.bits.data
invalidate tlOut.a.bits.mask
invalidate tlOut.a.bits.address
invalidate tlOut.a.bits.source
invalidate tlOut.a.bits.size
invalidate tlOut.a.bits.param
invalidate tlOut.a.bits.opcode
invalidate tlOut.a.valid
invalidate tlOut.a.ready
wire tlIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate tlIn.d.bits.corrupt
invalidate tlIn.d.bits.data
invalidate tlIn.d.bits.denied
invalidate tlIn.d.bits.sink
invalidate tlIn.d.bits.source
invalidate tlIn.d.bits.size
invalidate tlIn.d.bits.param
invalidate tlIn.d.bits.opcode
invalidate tlIn.d.valid
invalidate tlIn.d.ready
invalidate tlIn.a.bits.corrupt
invalidate tlIn.a.bits.data
invalidate tlIn.a.bits.mask
invalidate tlIn.a.bits.address
invalidate tlIn.a.bits.source
invalidate tlIn.a.bits.size
invalidate tlIn.a.bits.param
invalidate tlIn.a.bits.opcode
invalidate tlIn.a.valid
invalidate tlIn.a.ready
connect tlOut, tlIn
connect fragmenter.auto.anon_in, tlOut
connect tlIn, auto.tl_in
connect fragmenter.auto.anon_out.d, auto.fragmenter_anon_out.d
connect auto.fragmenter_anon_out.a.bits, fragmenter.auto.anon_out.a.bits
connect auto.fragmenter_anon_out.a.valid, fragmenter.auto.anon_out.a.valid
connect fragmenter.auto.anon_out.a.ready, auto.fragmenter_anon_out.a.ready
extmodule plusarg_reader_60 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_61 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLInterconnectCoupler_cbus_to_plic( // @[LazyModuleImp.scala:138:7]
input clock, // @[LazyModuleImp.scala:138:7]
input reset, // @[LazyModuleImp.scala:138:7]
input auto_fragmenter_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_fragmenter_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_fragmenter_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_fragmenter_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_fragmenter_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [11:0] auto_fragmenter_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [27:0] auto_fragmenter_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_fragmenter_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_fragmenter_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_fragmenter_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_fragmenter_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_fragmenter_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_fragmenter_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_fragmenter_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [11:0] auto_fragmenter_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_fragmenter_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [27:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_tl_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_tl_in_d_bits_data // @[LazyModuleImp.scala:107:25]
);
wire tlOut_d_valid; // @[MixedNode.scala:542:17]
wire [63:0] tlOut_d_bits_data; // @[MixedNode.scala:542:17]
wire [7:0] tlOut_d_bits_source; // @[MixedNode.scala:542:17]
wire [2:0] tlOut_d_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] tlOut_d_bits_opcode; // @[MixedNode.scala:542:17]
wire tlOut_a_ready; // @[MixedNode.scala:542:17]
wire auto_fragmenter_anon_out_a_ready_0 = auto_fragmenter_anon_out_a_ready; // @[LazyModuleImp.scala:138:7]
wire auto_fragmenter_anon_out_d_valid_0 = auto_fragmenter_anon_out_d_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_fragmenter_anon_out_d_bits_opcode_0 = auto_fragmenter_anon_out_d_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [1:0] auto_fragmenter_anon_out_d_bits_size_0 = auto_fragmenter_anon_out_d_bits_size; // @[LazyModuleImp.scala:138:7]
wire [11:0] auto_fragmenter_anon_out_d_bits_source_0 = auto_fragmenter_anon_out_d_bits_source; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_fragmenter_anon_out_d_bits_data_0 = auto_fragmenter_anon_out_d_bits_data; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_a_valid_0 = auto_tl_in_a_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_in_a_bits_opcode_0 = auto_tl_in_a_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_in_a_bits_param_0 = auto_tl_in_a_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_in_a_bits_size_0 = auto_tl_in_a_bits_size; // @[LazyModuleImp.scala:138:7]
wire [7:0] auto_tl_in_a_bits_source_0 = auto_tl_in_a_bits_source; // @[LazyModuleImp.scala:138:7]
wire [27:0] auto_tl_in_a_bits_address_0 = auto_tl_in_a_bits_address; // @[LazyModuleImp.scala:138:7]
wire [7:0] auto_tl_in_a_bits_mask_0 = auto_tl_in_a_bits_mask; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_tl_in_a_bits_data_0 = auto_tl_in_a_bits_data; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_a_bits_corrupt_0 = auto_tl_in_a_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_d_ready_0 = auto_tl_in_d_ready; // @[LazyModuleImp.scala:138:7]
wire auto_fragmenter_anon_out_d_bits_sink = 1'h0; // @[Fragmenter.scala:345:34]
wire auto_fragmenter_anon_out_d_bits_denied = 1'h0; // @[Fragmenter.scala:345:34]
wire auto_fragmenter_anon_out_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:345:34]
wire auto_tl_in_d_bits_sink = 1'h0; // @[Fragmenter.scala:345:34]
wire auto_tl_in_d_bits_denied = 1'h0; // @[Fragmenter.scala:345:34]
wire auto_tl_in_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:345:34]
wire tlOut_d_bits_sink = 1'h0; // @[Fragmenter.scala:345:34]
wire tlOut_d_bits_denied = 1'h0; // @[Fragmenter.scala:345:34]
wire tlOut_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:345:34]
wire tlIn_d_bits_sink = 1'h0; // @[Fragmenter.scala:345:34]
wire tlIn_d_bits_denied = 1'h0; // @[Fragmenter.scala:345:34]
wire tlIn_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:345:34]
wire [1:0] auto_fragmenter_anon_out_d_bits_param = 2'h0; // @[Fragmenter.scala:345:34]
wire [1:0] auto_tl_in_d_bits_param = 2'h0; // @[Fragmenter.scala:345:34]
wire [1:0] tlOut_d_bits_param = 2'h0; // @[Fragmenter.scala:345:34]
wire [1:0] tlIn_d_bits_param = 2'h0; // @[Fragmenter.scala:345:34]
wire tlIn_a_ready; // @[MixedNode.scala:551:17]
wire tlIn_a_valid = auto_tl_in_a_valid_0; // @[MixedNode.scala:551:17]
wire [2:0] tlIn_a_bits_opcode = auto_tl_in_a_bits_opcode_0; // @[MixedNode.scala:551:17]
wire [2:0] tlIn_a_bits_param = auto_tl_in_a_bits_param_0; // @[MixedNode.scala:551:17]
wire [2:0] tlIn_a_bits_size = auto_tl_in_a_bits_size_0; // @[MixedNode.scala:551:17]
wire [7:0] tlIn_a_bits_source = auto_tl_in_a_bits_source_0; // @[MixedNode.scala:551:17]
wire [27:0] tlIn_a_bits_address = auto_tl_in_a_bits_address_0; // @[MixedNode.scala:551:17]
wire [7:0] tlIn_a_bits_mask = auto_tl_in_a_bits_mask_0; // @[MixedNode.scala:551:17]
wire [63:0] tlIn_a_bits_data = auto_tl_in_a_bits_data_0; // @[MixedNode.scala:551:17]
wire tlIn_a_bits_corrupt = auto_tl_in_a_bits_corrupt_0; // @[MixedNode.scala:551:17]
wire tlIn_d_ready = auto_tl_in_d_ready_0; // @[MixedNode.scala:551:17]
wire tlIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] tlIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] tlIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [7:0] tlIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [63:0] tlIn_d_bits_data; // @[MixedNode.scala:551:17]
wire [2:0] auto_fragmenter_anon_out_a_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_fragmenter_anon_out_a_bits_param_0; // @[LazyModuleImp.scala:138:7]
wire [1:0] auto_fragmenter_anon_out_a_bits_size_0; // @[LazyModuleImp.scala:138:7]
wire [11:0] auto_fragmenter_anon_out_a_bits_source_0; // @[LazyModuleImp.scala:138:7]
wire [27:0] auto_fragmenter_anon_out_a_bits_address_0; // @[LazyModuleImp.scala:138:7]
wire [7:0] auto_fragmenter_anon_out_a_bits_mask_0; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_fragmenter_anon_out_a_bits_data_0; // @[LazyModuleImp.scala:138:7]
wire auto_fragmenter_anon_out_a_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
wire auto_fragmenter_anon_out_a_valid_0; // @[LazyModuleImp.scala:138:7]
wire auto_fragmenter_anon_out_d_ready_0; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_a_ready_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7]
wire [7:0] auto_tl_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_tl_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_d_valid_0; // @[LazyModuleImp.scala:138:7]
assign tlIn_a_ready = tlOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign tlIn_d_valid = tlOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlIn_d_bits_opcode = tlOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign tlIn_d_bits_size = tlOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign tlIn_d_bits_source = tlOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign tlIn_d_bits_data = tlOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] tlOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] tlOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] tlOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [7:0] tlOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [27:0] tlOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] tlOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] tlOut_a_bits_data; // @[MixedNode.scala:542:17]
wire tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire tlOut_a_valid; // @[MixedNode.scala:542:17]
wire tlOut_d_ready; // @[MixedNode.scala:542:17]
assign auto_tl_in_a_ready_0 = tlIn_a_ready; // @[MixedNode.scala:551:17]
assign tlOut_a_valid = tlIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_opcode = tlIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_param = tlIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_size = tlIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_source = tlIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_address = tlIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_mask = tlIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_data = tlIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_corrupt = tlIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_d_ready = tlIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_tl_in_d_valid_0 = tlIn_d_valid; // @[MixedNode.scala:551:17]
assign auto_tl_in_d_bits_opcode_0 = tlIn_d_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_tl_in_d_bits_size_0 = tlIn_d_bits_size; // @[MixedNode.scala:551:17]
assign auto_tl_in_d_bits_source_0 = tlIn_d_bits_source; // @[MixedNode.scala:551:17]
assign auto_tl_in_d_bits_data_0 = tlIn_d_bits_data; // @[MixedNode.scala:551:17]
TLFragmenter_PLIC fragmenter ( // @[Fragmenter.scala:345:34]
.clock (clock),
.reset (reset),
.auto_anon_in_a_ready (tlOut_a_ready),
.auto_anon_in_a_valid (tlOut_a_valid), // @[MixedNode.scala:542:17]
.auto_anon_in_a_bits_opcode (tlOut_a_bits_opcode), // @[MixedNode.scala:542:17]
.auto_anon_in_a_bits_param (tlOut_a_bits_param), // @[MixedNode.scala:542:17]
.auto_anon_in_a_bits_size (tlOut_a_bits_size), // @[MixedNode.scala:542:17]
.auto_anon_in_a_bits_source (tlOut_a_bits_source), // @[MixedNode.scala:542:17]
.auto_anon_in_a_bits_address (tlOut_a_bits_address), // @[MixedNode.scala:542:17]
.auto_anon_in_a_bits_mask (tlOut_a_bits_mask), // @[MixedNode.scala:542:17]
.auto_anon_in_a_bits_data (tlOut_a_bits_data), // @[MixedNode.scala:542:17]
.auto_anon_in_a_bits_corrupt (tlOut_a_bits_corrupt), // @[MixedNode.scala:542:17]
.auto_anon_in_d_ready (tlOut_d_ready), // @[MixedNode.scala:542:17]
.auto_anon_in_d_valid (tlOut_d_valid),
.auto_anon_in_d_bits_opcode (tlOut_d_bits_opcode),
.auto_anon_in_d_bits_size (tlOut_d_bits_size),
.auto_anon_in_d_bits_source (tlOut_d_bits_source),
.auto_anon_in_d_bits_data (tlOut_d_bits_data),
.auto_anon_out_a_ready (auto_fragmenter_anon_out_a_ready_0), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_a_valid (auto_fragmenter_anon_out_a_valid_0),
.auto_anon_out_a_bits_opcode (auto_fragmenter_anon_out_a_bits_opcode_0),
.auto_anon_out_a_bits_param (auto_fragmenter_anon_out_a_bits_param_0),
.auto_anon_out_a_bits_size (auto_fragmenter_anon_out_a_bits_size_0),
.auto_anon_out_a_bits_source (auto_fragmenter_anon_out_a_bits_source_0),
.auto_anon_out_a_bits_address (auto_fragmenter_anon_out_a_bits_address_0),
.auto_anon_out_a_bits_mask (auto_fragmenter_anon_out_a_bits_mask_0),
.auto_anon_out_a_bits_data (auto_fragmenter_anon_out_a_bits_data_0),
.auto_anon_out_a_bits_corrupt (auto_fragmenter_anon_out_a_bits_corrupt_0),
.auto_anon_out_d_ready (auto_fragmenter_anon_out_d_ready_0),
.auto_anon_out_d_valid (auto_fragmenter_anon_out_d_valid_0), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_d_bits_opcode (auto_fragmenter_anon_out_d_bits_opcode_0), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_d_bits_size (auto_fragmenter_anon_out_d_bits_size_0), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_d_bits_source (auto_fragmenter_anon_out_d_bits_source_0), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_d_bits_data (auto_fragmenter_anon_out_d_bits_data_0) // @[LazyModuleImp.scala:138:7]
); // @[Fragmenter.scala:345:34]
assign auto_fragmenter_anon_out_a_valid = auto_fragmenter_anon_out_a_valid_0; // @[LazyModuleImp.scala:138:7]
assign auto_fragmenter_anon_out_a_bits_opcode = auto_fragmenter_anon_out_a_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
assign auto_fragmenter_anon_out_a_bits_param = auto_fragmenter_anon_out_a_bits_param_0; // @[LazyModuleImp.scala:138:7]
assign auto_fragmenter_anon_out_a_bits_size = auto_fragmenter_anon_out_a_bits_size_0; // @[LazyModuleImp.scala:138:7]
assign auto_fragmenter_anon_out_a_bits_source = auto_fragmenter_anon_out_a_bits_source_0; // @[LazyModuleImp.scala:138:7]
assign auto_fragmenter_anon_out_a_bits_address = auto_fragmenter_anon_out_a_bits_address_0; // @[LazyModuleImp.scala:138:7]
assign auto_fragmenter_anon_out_a_bits_mask = auto_fragmenter_anon_out_a_bits_mask_0; // @[LazyModuleImp.scala:138:7]
assign auto_fragmenter_anon_out_a_bits_data = auto_fragmenter_anon_out_a_bits_data_0; // @[LazyModuleImp.scala:138:7]
assign auto_fragmenter_anon_out_a_bits_corrupt = auto_fragmenter_anon_out_a_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
assign auto_fragmenter_anon_out_d_ready = auto_fragmenter_anon_out_d_ready_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_a_ready = auto_tl_in_a_ready_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_valid = auto_tl_in_d_valid_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_bits_opcode = auto_tl_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_bits_size = auto_tl_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_bits_source = auto_tl_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_bits_data = auto_tl_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module BundleBridgeNexus_NoOutput_6 :
output auto : { }
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset | module BundleBridgeNexus_NoOutput_6(); // @[BundleBridgeNexus.scala:20:9]
wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_45 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 4, 0)
node _source_ok_T = shr(io.in.a.bits.source, 5)
node _source_ok_T_1 = eq(_source_ok_T, UInt<2>(0h3))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<5>(0h13))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 4, 0)
node _source_ok_T_6 = shr(io.in.a.bits.source, 5)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<2>(0h2))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<5>(0h13))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 4, 0)
node _source_ok_T_12 = shr(io.in.a.bits.source, 5)
node _source_ok_T_13 = eq(_source_ok_T_12, UInt<1>(0h1))
node _source_ok_T_14 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_15 = and(_source_ok_T_13, _source_ok_T_14)
node _source_ok_T_16 = leq(source_ok_uncommonBits_2, UInt<5>(0h13))
node _source_ok_T_17 = and(_source_ok_T_15, _source_ok_T_16)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 4, 0)
node _source_ok_T_18 = shr(io.in.a.bits.source, 5)
node _source_ok_T_19 = eq(_source_ok_T_18, UInt<1>(0h0))
node _source_ok_T_20 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_21 = and(_source_ok_T_19, _source_ok_T_20)
node _source_ok_T_22 = leq(source_ok_uncommonBits_3, UInt<5>(0h13))
node _source_ok_T_23 = and(_source_ok_T_21, _source_ok_T_22)
wire _source_ok_WIRE : UInt<1>[4]
connect _source_ok_WIRE[0], _source_ok_T_5
connect _source_ok_WIRE[1], _source_ok_T_11
connect _source_ok_WIRE[2], _source_ok_T_17
connect _source_ok_WIRE[3], _source_ok_T_23
node _source_ok_T_24 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_25 = or(_source_ok_T_24, _source_ok_WIRE[2])
node source_ok = or(_source_ok_T_25, _source_ok_WIRE[3])
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits = bits(_uncommonBits_T, 4, 0)
node _T_4 = shr(io.in.a.bits.source, 5)
node _T_5 = eq(_T_4, UInt<2>(0h3))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<5>(0h13))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<9>(0hc0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 4, 0)
node _T_17 = shr(io.in.a.bits.source, 5)
node _T_18 = eq(_T_17, UInt<2>(0h2))
node _T_19 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_20 = and(_T_18, _T_19)
node _T_21 = leq(uncommonBits_1, UInt<5>(0h13))
node _T_22 = and(_T_20, _T_21)
node _T_23 = eq(_T_22, UInt<1>(0h0))
node _T_24 = xor(io.in.a.bits.address, UInt<7>(0h40))
node _T_25 = cvt(_T_24)
node _T_26 = and(_T_25, asSInt(UInt<9>(0hc0)))
node _T_27 = asSInt(_T_26)
node _T_28 = eq(_T_27, asSInt(UInt<1>(0h0)))
node _T_29 = or(_T_23, _T_28)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 4, 0)
node _T_30 = shr(io.in.a.bits.source, 5)
node _T_31 = eq(_T_30, UInt<1>(0h1))
node _T_32 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_33 = and(_T_31, _T_32)
node _T_34 = leq(uncommonBits_2, UInt<5>(0h13))
node _T_35 = and(_T_33, _T_34)
node _T_36 = eq(_T_35, UInt<1>(0h0))
node _T_37 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_38 = cvt(_T_37)
node _T_39 = and(_T_38, asSInt(UInt<9>(0hc0)))
node _T_40 = asSInt(_T_39)
node _T_41 = eq(_T_40, asSInt(UInt<1>(0h0)))
node _T_42 = or(_T_36, _T_41)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 4, 0)
node _T_43 = shr(io.in.a.bits.source, 5)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_46 = and(_T_44, _T_45)
node _T_47 = leq(uncommonBits_3, UInt<5>(0h13))
node _T_48 = and(_T_46, _T_47)
node _T_49 = eq(_T_48, UInt<1>(0h0))
node _T_50 = xor(io.in.a.bits.address, UInt<8>(0hc0))
node _T_51 = cvt(_T_50)
node _T_52 = and(_T_51, asSInt(UInt<9>(0hc0)))
node _T_53 = asSInt(_T_52)
node _T_54 = eq(_T_53, asSInt(UInt<1>(0h0)))
node _T_55 = or(_T_49, _T_54)
node _T_56 = and(_T_16, _T_29)
node _T_57 = and(_T_56, _T_42)
node _T_58 = and(_T_57, _T_55)
node _T_59 = asUInt(reset)
node _T_60 = eq(_T_59, UInt<1>(0h0))
when _T_60 :
node _T_61 = eq(_T_58, UInt<1>(0h0))
when _T_61 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_58, UInt<1>(0h1), "") : assert_1
node _T_62 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_62 :
node _T_63 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_64 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_65 = and(_T_63, _T_64)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 4, 0)
node _T_66 = shr(io.in.a.bits.source, 5)
node _T_67 = eq(_T_66, UInt<2>(0h3))
node _T_68 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_69 = and(_T_67, _T_68)
node _T_70 = leq(uncommonBits_4, UInt<5>(0h13))
node _T_71 = and(_T_69, _T_70)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 4, 0)
node _T_72 = shr(io.in.a.bits.source, 5)
node _T_73 = eq(_T_72, UInt<2>(0h2))
node _T_74 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_75 = and(_T_73, _T_74)
node _T_76 = leq(uncommonBits_5, UInt<5>(0h13))
node _T_77 = and(_T_75, _T_76)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 4, 0)
node _T_78 = shr(io.in.a.bits.source, 5)
node _T_79 = eq(_T_78, UInt<1>(0h1))
node _T_80 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_81 = and(_T_79, _T_80)
node _T_82 = leq(uncommonBits_6, UInt<5>(0h13))
node _T_83 = and(_T_81, _T_82)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 4, 0)
node _T_84 = shr(io.in.a.bits.source, 5)
node _T_85 = eq(_T_84, UInt<1>(0h0))
node _T_86 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_87 = and(_T_85, _T_86)
node _T_88 = leq(uncommonBits_7, UInt<5>(0h13))
node _T_89 = and(_T_87, _T_88)
node _T_90 = or(_T_71, _T_77)
node _T_91 = or(_T_90, _T_83)
node _T_92 = or(_T_91, _T_89)
node _T_93 = and(_T_65, _T_92)
node _T_94 = or(UInt<1>(0h0), _T_93)
node _T_95 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_96 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_97 = cvt(_T_96)
node _T_98 = and(_T_97, asSInt(UInt<29>(0h10000000)))
node _T_99 = asSInt(_T_98)
node _T_100 = eq(_T_99, asSInt(UInt<1>(0h0)))
node _T_101 = and(_T_95, _T_100)
node _T_102 = or(UInt<1>(0h0), _T_101)
node _T_103 = and(_T_94, _T_102)
node _T_104 = asUInt(reset)
node _T_105 = eq(_T_104, UInt<1>(0h0))
when _T_105 :
node _T_106 = eq(_T_103, UInt<1>(0h0))
when _T_106 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_103, UInt<1>(0h1), "") : assert_2
node _T_107 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_108 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_109 = and(_T_107, _T_108)
node _T_110 = or(UInt<1>(0h0), _T_109)
node _T_111 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_112 = cvt(_T_111)
node _T_113 = and(_T_112, asSInt(UInt<29>(0h10000000)))
node _T_114 = asSInt(_T_113)
node _T_115 = eq(_T_114, asSInt(UInt<1>(0h0)))
node _T_116 = and(_T_110, _T_115)
node _T_117 = or(UInt<1>(0h0), _T_116)
node _T_118 = and(UInt<1>(0h0), _T_117)
node _T_119 = asUInt(reset)
node _T_120 = eq(_T_119, UInt<1>(0h0))
when _T_120 :
node _T_121 = eq(_T_118, UInt<1>(0h0))
when _T_121 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_118, UInt<1>(0h1), "") : assert_3
node _T_122 = asUInt(reset)
node _T_123 = eq(_T_122, UInt<1>(0h0))
when _T_123 :
node _T_124 = eq(source_ok, UInt<1>(0h0))
when _T_124 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_125 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_126 = asUInt(reset)
node _T_127 = eq(_T_126, UInt<1>(0h0))
when _T_127 :
node _T_128 = eq(_T_125, UInt<1>(0h0))
when _T_128 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_125, UInt<1>(0h1), "") : assert_5
node _T_129 = asUInt(reset)
node _T_130 = eq(_T_129, UInt<1>(0h0))
when _T_130 :
node _T_131 = eq(is_aligned, UInt<1>(0h0))
when _T_131 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_132 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_133 = asUInt(reset)
node _T_134 = eq(_T_133, UInt<1>(0h0))
when _T_134 :
node _T_135 = eq(_T_132, UInt<1>(0h0))
when _T_135 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_132, UInt<1>(0h1), "") : assert_7
node _T_136 = not(io.in.a.bits.mask)
node _T_137 = eq(_T_136, UInt<1>(0h0))
node _T_138 = asUInt(reset)
node _T_139 = eq(_T_138, UInt<1>(0h0))
when _T_139 :
node _T_140 = eq(_T_137, UInt<1>(0h0))
when _T_140 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_137, UInt<1>(0h1), "") : assert_8
node _T_141 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_142 = asUInt(reset)
node _T_143 = eq(_T_142, UInt<1>(0h0))
when _T_143 :
node _T_144 = eq(_T_141, UInt<1>(0h0))
when _T_144 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_141, UInt<1>(0h1), "") : assert_9
node _T_145 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_145 :
node _T_146 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_147 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_148 = and(_T_146, _T_147)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 4, 0)
node _T_149 = shr(io.in.a.bits.source, 5)
node _T_150 = eq(_T_149, UInt<2>(0h3))
node _T_151 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_152 = and(_T_150, _T_151)
node _T_153 = leq(uncommonBits_8, UInt<5>(0h13))
node _T_154 = and(_T_152, _T_153)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 4, 0)
node _T_155 = shr(io.in.a.bits.source, 5)
node _T_156 = eq(_T_155, UInt<2>(0h2))
node _T_157 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_158 = and(_T_156, _T_157)
node _T_159 = leq(uncommonBits_9, UInt<5>(0h13))
node _T_160 = and(_T_158, _T_159)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 4, 0)
node _T_161 = shr(io.in.a.bits.source, 5)
node _T_162 = eq(_T_161, UInt<1>(0h1))
node _T_163 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_164 = and(_T_162, _T_163)
node _T_165 = leq(uncommonBits_10, UInt<5>(0h13))
node _T_166 = and(_T_164, _T_165)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 4, 0)
node _T_167 = shr(io.in.a.bits.source, 5)
node _T_168 = eq(_T_167, UInt<1>(0h0))
node _T_169 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_170 = and(_T_168, _T_169)
node _T_171 = leq(uncommonBits_11, UInt<5>(0h13))
node _T_172 = and(_T_170, _T_171)
node _T_173 = or(_T_154, _T_160)
node _T_174 = or(_T_173, _T_166)
node _T_175 = or(_T_174, _T_172)
node _T_176 = and(_T_148, _T_175)
node _T_177 = or(UInt<1>(0h0), _T_176)
node _T_178 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_179 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_180 = cvt(_T_179)
node _T_181 = and(_T_180, asSInt(UInt<29>(0h10000000)))
node _T_182 = asSInt(_T_181)
node _T_183 = eq(_T_182, asSInt(UInt<1>(0h0)))
node _T_184 = and(_T_178, _T_183)
node _T_185 = or(UInt<1>(0h0), _T_184)
node _T_186 = and(_T_177, _T_185)
node _T_187 = asUInt(reset)
node _T_188 = eq(_T_187, UInt<1>(0h0))
when _T_188 :
node _T_189 = eq(_T_186, UInt<1>(0h0))
when _T_189 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_186, UInt<1>(0h1), "") : assert_10
node _T_190 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_191 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_192 = and(_T_190, _T_191)
node _T_193 = or(UInt<1>(0h0), _T_192)
node _T_194 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_195 = cvt(_T_194)
node _T_196 = and(_T_195, asSInt(UInt<29>(0h10000000)))
node _T_197 = asSInt(_T_196)
node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0)))
node _T_199 = and(_T_193, _T_198)
node _T_200 = or(UInt<1>(0h0), _T_199)
node _T_201 = and(UInt<1>(0h0), _T_200)
node _T_202 = asUInt(reset)
node _T_203 = eq(_T_202, UInt<1>(0h0))
when _T_203 :
node _T_204 = eq(_T_201, UInt<1>(0h0))
when _T_204 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_201, UInt<1>(0h1), "") : assert_11
node _T_205 = asUInt(reset)
node _T_206 = eq(_T_205, UInt<1>(0h0))
when _T_206 :
node _T_207 = eq(source_ok, UInt<1>(0h0))
when _T_207 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_208 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_209 = asUInt(reset)
node _T_210 = eq(_T_209, UInt<1>(0h0))
when _T_210 :
node _T_211 = eq(_T_208, UInt<1>(0h0))
when _T_211 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_208, UInt<1>(0h1), "") : assert_13
node _T_212 = asUInt(reset)
node _T_213 = eq(_T_212, UInt<1>(0h0))
when _T_213 :
node _T_214 = eq(is_aligned, UInt<1>(0h0))
when _T_214 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_215 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_216 = asUInt(reset)
node _T_217 = eq(_T_216, UInt<1>(0h0))
when _T_217 :
node _T_218 = eq(_T_215, UInt<1>(0h0))
when _T_218 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_215, UInt<1>(0h1), "") : assert_15
node _T_219 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_220 = asUInt(reset)
node _T_221 = eq(_T_220, UInt<1>(0h0))
when _T_221 :
node _T_222 = eq(_T_219, UInt<1>(0h0))
when _T_222 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_219, UInt<1>(0h1), "") : assert_16
node _T_223 = not(io.in.a.bits.mask)
node _T_224 = eq(_T_223, UInt<1>(0h0))
node _T_225 = asUInt(reset)
node _T_226 = eq(_T_225, UInt<1>(0h0))
when _T_226 :
node _T_227 = eq(_T_224, UInt<1>(0h0))
when _T_227 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_224, UInt<1>(0h1), "") : assert_17
node _T_228 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_229 = asUInt(reset)
node _T_230 = eq(_T_229, UInt<1>(0h0))
when _T_230 :
node _T_231 = eq(_T_228, UInt<1>(0h0))
when _T_231 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_228, UInt<1>(0h1), "") : assert_18
node _T_232 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_232 :
node _T_233 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_234 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_235 = and(_T_233, _T_234)
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 4, 0)
node _T_236 = shr(io.in.a.bits.source, 5)
node _T_237 = eq(_T_236, UInt<2>(0h3))
node _T_238 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_239 = and(_T_237, _T_238)
node _T_240 = leq(uncommonBits_12, UInt<5>(0h13))
node _T_241 = and(_T_239, _T_240)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 4, 0)
node _T_242 = shr(io.in.a.bits.source, 5)
node _T_243 = eq(_T_242, UInt<2>(0h2))
node _T_244 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_245 = and(_T_243, _T_244)
node _T_246 = leq(uncommonBits_13, UInt<5>(0h13))
node _T_247 = and(_T_245, _T_246)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 4, 0)
node _T_248 = shr(io.in.a.bits.source, 5)
node _T_249 = eq(_T_248, UInt<1>(0h1))
node _T_250 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_251 = and(_T_249, _T_250)
node _T_252 = leq(uncommonBits_14, UInt<5>(0h13))
node _T_253 = and(_T_251, _T_252)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 4, 0)
node _T_254 = shr(io.in.a.bits.source, 5)
node _T_255 = eq(_T_254, UInt<1>(0h0))
node _T_256 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_257 = and(_T_255, _T_256)
node _T_258 = leq(uncommonBits_15, UInt<5>(0h13))
node _T_259 = and(_T_257, _T_258)
node _T_260 = or(_T_241, _T_247)
node _T_261 = or(_T_260, _T_253)
node _T_262 = or(_T_261, _T_259)
node _T_263 = and(_T_235, _T_262)
node _T_264 = or(UInt<1>(0h0), _T_263)
node _T_265 = asUInt(reset)
node _T_266 = eq(_T_265, UInt<1>(0h0))
when _T_266 :
node _T_267 = eq(_T_264, UInt<1>(0h0))
when _T_267 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_264, UInt<1>(0h1), "") : assert_19
node _T_268 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_269 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_270 = and(_T_268, _T_269)
node _T_271 = or(UInt<1>(0h0), _T_270)
node _T_272 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_273 = cvt(_T_272)
node _T_274 = and(_T_273, asSInt(UInt<29>(0h10000000)))
node _T_275 = asSInt(_T_274)
node _T_276 = eq(_T_275, asSInt(UInt<1>(0h0)))
node _T_277 = and(_T_271, _T_276)
node _T_278 = or(UInt<1>(0h0), _T_277)
node _T_279 = asUInt(reset)
node _T_280 = eq(_T_279, UInt<1>(0h0))
when _T_280 :
node _T_281 = eq(_T_278, UInt<1>(0h0))
when _T_281 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_278, UInt<1>(0h1), "") : assert_20
node _T_282 = asUInt(reset)
node _T_283 = eq(_T_282, UInt<1>(0h0))
when _T_283 :
node _T_284 = eq(source_ok, UInt<1>(0h0))
when _T_284 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_285 = asUInt(reset)
node _T_286 = eq(_T_285, UInt<1>(0h0))
when _T_286 :
node _T_287 = eq(is_aligned, UInt<1>(0h0))
when _T_287 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_288 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_289 = asUInt(reset)
node _T_290 = eq(_T_289, UInt<1>(0h0))
when _T_290 :
node _T_291 = eq(_T_288, UInt<1>(0h0))
when _T_291 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_288, UInt<1>(0h1), "") : assert_23
node _T_292 = eq(io.in.a.bits.mask, mask)
node _T_293 = asUInt(reset)
node _T_294 = eq(_T_293, UInt<1>(0h0))
when _T_294 :
node _T_295 = eq(_T_292, UInt<1>(0h0))
when _T_295 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_292, UInt<1>(0h1), "") : assert_24
node _T_296 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_297 = asUInt(reset)
node _T_298 = eq(_T_297, UInt<1>(0h0))
when _T_298 :
node _T_299 = eq(_T_296, UInt<1>(0h0))
when _T_299 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_296, UInt<1>(0h1), "") : assert_25
node _T_300 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_300 :
node _T_301 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_302 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_303 = and(_T_301, _T_302)
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 4, 0)
node _T_304 = shr(io.in.a.bits.source, 5)
node _T_305 = eq(_T_304, UInt<2>(0h3))
node _T_306 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_307 = and(_T_305, _T_306)
node _T_308 = leq(uncommonBits_16, UInt<5>(0h13))
node _T_309 = and(_T_307, _T_308)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 4, 0)
node _T_310 = shr(io.in.a.bits.source, 5)
node _T_311 = eq(_T_310, UInt<2>(0h2))
node _T_312 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_313 = and(_T_311, _T_312)
node _T_314 = leq(uncommonBits_17, UInt<5>(0h13))
node _T_315 = and(_T_313, _T_314)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 4, 0)
node _T_316 = shr(io.in.a.bits.source, 5)
node _T_317 = eq(_T_316, UInt<1>(0h1))
node _T_318 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_319 = and(_T_317, _T_318)
node _T_320 = leq(uncommonBits_18, UInt<5>(0h13))
node _T_321 = and(_T_319, _T_320)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 4, 0)
node _T_322 = shr(io.in.a.bits.source, 5)
node _T_323 = eq(_T_322, UInt<1>(0h0))
node _T_324 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_325 = and(_T_323, _T_324)
node _T_326 = leq(uncommonBits_19, UInt<5>(0h13))
node _T_327 = and(_T_325, _T_326)
node _T_328 = or(_T_309, _T_315)
node _T_329 = or(_T_328, _T_321)
node _T_330 = or(_T_329, _T_327)
node _T_331 = and(_T_303, _T_330)
node _T_332 = or(UInt<1>(0h0), _T_331)
node _T_333 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_334 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_335 = and(_T_333, _T_334)
node _T_336 = or(UInt<1>(0h0), _T_335)
node _T_337 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_338 = cvt(_T_337)
node _T_339 = and(_T_338, asSInt(UInt<29>(0h10000000)))
node _T_340 = asSInt(_T_339)
node _T_341 = eq(_T_340, asSInt(UInt<1>(0h0)))
node _T_342 = and(_T_336, _T_341)
node _T_343 = or(UInt<1>(0h0), _T_342)
node _T_344 = and(_T_332, _T_343)
node _T_345 = asUInt(reset)
node _T_346 = eq(_T_345, UInt<1>(0h0))
when _T_346 :
node _T_347 = eq(_T_344, UInt<1>(0h0))
when _T_347 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_344, UInt<1>(0h1), "") : assert_26
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(source_ok, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_351 = asUInt(reset)
node _T_352 = eq(_T_351, UInt<1>(0h0))
when _T_352 :
node _T_353 = eq(is_aligned, UInt<1>(0h0))
when _T_353 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_354 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_355 = asUInt(reset)
node _T_356 = eq(_T_355, UInt<1>(0h0))
when _T_356 :
node _T_357 = eq(_T_354, UInt<1>(0h0))
when _T_357 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_354, UInt<1>(0h1), "") : assert_29
node _T_358 = eq(io.in.a.bits.mask, mask)
node _T_359 = asUInt(reset)
node _T_360 = eq(_T_359, UInt<1>(0h0))
when _T_360 :
node _T_361 = eq(_T_358, UInt<1>(0h0))
when _T_361 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_358, UInt<1>(0h1), "") : assert_30
node _T_362 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_362 :
node _T_363 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_364 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_365 = and(_T_363, _T_364)
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 4, 0)
node _T_366 = shr(io.in.a.bits.source, 5)
node _T_367 = eq(_T_366, UInt<2>(0h3))
node _T_368 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_369 = and(_T_367, _T_368)
node _T_370 = leq(uncommonBits_20, UInt<5>(0h13))
node _T_371 = and(_T_369, _T_370)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 4, 0)
node _T_372 = shr(io.in.a.bits.source, 5)
node _T_373 = eq(_T_372, UInt<2>(0h2))
node _T_374 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_375 = and(_T_373, _T_374)
node _T_376 = leq(uncommonBits_21, UInt<5>(0h13))
node _T_377 = and(_T_375, _T_376)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 4, 0)
node _T_378 = shr(io.in.a.bits.source, 5)
node _T_379 = eq(_T_378, UInt<1>(0h1))
node _T_380 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_381 = and(_T_379, _T_380)
node _T_382 = leq(uncommonBits_22, UInt<5>(0h13))
node _T_383 = and(_T_381, _T_382)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 4, 0)
node _T_384 = shr(io.in.a.bits.source, 5)
node _T_385 = eq(_T_384, UInt<1>(0h0))
node _T_386 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_387 = and(_T_385, _T_386)
node _T_388 = leq(uncommonBits_23, UInt<5>(0h13))
node _T_389 = and(_T_387, _T_388)
node _T_390 = or(_T_371, _T_377)
node _T_391 = or(_T_390, _T_383)
node _T_392 = or(_T_391, _T_389)
node _T_393 = and(_T_365, _T_392)
node _T_394 = or(UInt<1>(0h0), _T_393)
node _T_395 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_396 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_397 = and(_T_395, _T_396)
node _T_398 = or(UInt<1>(0h0), _T_397)
node _T_399 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_400 = cvt(_T_399)
node _T_401 = and(_T_400, asSInt(UInt<29>(0h10000000)))
node _T_402 = asSInt(_T_401)
node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0)))
node _T_404 = and(_T_398, _T_403)
node _T_405 = or(UInt<1>(0h0), _T_404)
node _T_406 = and(_T_394, _T_405)
node _T_407 = asUInt(reset)
node _T_408 = eq(_T_407, UInt<1>(0h0))
when _T_408 :
node _T_409 = eq(_T_406, UInt<1>(0h0))
when _T_409 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_406, UInt<1>(0h1), "") : assert_31
node _T_410 = asUInt(reset)
node _T_411 = eq(_T_410, UInt<1>(0h0))
when _T_411 :
node _T_412 = eq(source_ok, UInt<1>(0h0))
when _T_412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_413 = asUInt(reset)
node _T_414 = eq(_T_413, UInt<1>(0h0))
when _T_414 :
node _T_415 = eq(is_aligned, UInt<1>(0h0))
when _T_415 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_416 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_417 = asUInt(reset)
node _T_418 = eq(_T_417, UInt<1>(0h0))
when _T_418 :
node _T_419 = eq(_T_416, UInt<1>(0h0))
when _T_419 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_416, UInt<1>(0h1), "") : assert_34
node _T_420 = not(mask)
node _T_421 = and(io.in.a.bits.mask, _T_420)
node _T_422 = eq(_T_421, UInt<1>(0h0))
node _T_423 = asUInt(reset)
node _T_424 = eq(_T_423, UInt<1>(0h0))
when _T_424 :
node _T_425 = eq(_T_422, UInt<1>(0h0))
when _T_425 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_422, UInt<1>(0h1), "") : assert_35
node _T_426 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_426 :
node _T_427 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_428 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_429 = and(_T_427, _T_428)
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 4, 0)
node _T_430 = shr(io.in.a.bits.source, 5)
node _T_431 = eq(_T_430, UInt<2>(0h3))
node _T_432 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_433 = and(_T_431, _T_432)
node _T_434 = leq(uncommonBits_24, UInt<5>(0h13))
node _T_435 = and(_T_433, _T_434)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 4, 0)
node _T_436 = shr(io.in.a.bits.source, 5)
node _T_437 = eq(_T_436, UInt<2>(0h2))
node _T_438 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_439 = and(_T_437, _T_438)
node _T_440 = leq(uncommonBits_25, UInt<5>(0h13))
node _T_441 = and(_T_439, _T_440)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 4, 0)
node _T_442 = shr(io.in.a.bits.source, 5)
node _T_443 = eq(_T_442, UInt<1>(0h1))
node _T_444 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_445 = and(_T_443, _T_444)
node _T_446 = leq(uncommonBits_26, UInt<5>(0h13))
node _T_447 = and(_T_445, _T_446)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 4, 0)
node _T_448 = shr(io.in.a.bits.source, 5)
node _T_449 = eq(_T_448, UInt<1>(0h0))
node _T_450 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_451 = and(_T_449, _T_450)
node _T_452 = leq(uncommonBits_27, UInt<5>(0h13))
node _T_453 = and(_T_451, _T_452)
node _T_454 = or(_T_435, _T_441)
node _T_455 = or(_T_454, _T_447)
node _T_456 = or(_T_455, _T_453)
node _T_457 = and(_T_429, _T_456)
node _T_458 = or(UInt<1>(0h0), _T_457)
node _T_459 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_460 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_461 = cvt(_T_460)
node _T_462 = and(_T_461, asSInt(UInt<29>(0h10000000)))
node _T_463 = asSInt(_T_462)
node _T_464 = eq(_T_463, asSInt(UInt<1>(0h0)))
node _T_465 = and(_T_459, _T_464)
node _T_466 = or(UInt<1>(0h0), _T_465)
node _T_467 = and(_T_458, _T_466)
node _T_468 = asUInt(reset)
node _T_469 = eq(_T_468, UInt<1>(0h0))
when _T_469 :
node _T_470 = eq(_T_467, UInt<1>(0h0))
when _T_470 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_467, UInt<1>(0h1), "") : assert_36
node _T_471 = asUInt(reset)
node _T_472 = eq(_T_471, UInt<1>(0h0))
when _T_472 :
node _T_473 = eq(source_ok, UInt<1>(0h0))
when _T_473 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_474 = asUInt(reset)
node _T_475 = eq(_T_474, UInt<1>(0h0))
when _T_475 :
node _T_476 = eq(is_aligned, UInt<1>(0h0))
when _T_476 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_477 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_478 = asUInt(reset)
node _T_479 = eq(_T_478, UInt<1>(0h0))
when _T_479 :
node _T_480 = eq(_T_477, UInt<1>(0h0))
when _T_480 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_477, UInt<1>(0h1), "") : assert_39
node _T_481 = eq(io.in.a.bits.mask, mask)
node _T_482 = asUInt(reset)
node _T_483 = eq(_T_482, UInt<1>(0h0))
when _T_483 :
node _T_484 = eq(_T_481, UInt<1>(0h0))
when _T_484 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_481, UInt<1>(0h1), "") : assert_40
node _T_485 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_485 :
node _T_486 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_487 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_488 = and(_T_486, _T_487)
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 4, 0)
node _T_489 = shr(io.in.a.bits.source, 5)
node _T_490 = eq(_T_489, UInt<2>(0h3))
node _T_491 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_492 = and(_T_490, _T_491)
node _T_493 = leq(uncommonBits_28, UInt<5>(0h13))
node _T_494 = and(_T_492, _T_493)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 4, 0)
node _T_495 = shr(io.in.a.bits.source, 5)
node _T_496 = eq(_T_495, UInt<2>(0h2))
node _T_497 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_498 = and(_T_496, _T_497)
node _T_499 = leq(uncommonBits_29, UInt<5>(0h13))
node _T_500 = and(_T_498, _T_499)
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 4, 0)
node _T_501 = shr(io.in.a.bits.source, 5)
node _T_502 = eq(_T_501, UInt<1>(0h1))
node _T_503 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_504 = and(_T_502, _T_503)
node _T_505 = leq(uncommonBits_30, UInt<5>(0h13))
node _T_506 = and(_T_504, _T_505)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 4, 0)
node _T_507 = shr(io.in.a.bits.source, 5)
node _T_508 = eq(_T_507, UInt<1>(0h0))
node _T_509 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_510 = and(_T_508, _T_509)
node _T_511 = leq(uncommonBits_31, UInt<5>(0h13))
node _T_512 = and(_T_510, _T_511)
node _T_513 = or(_T_494, _T_500)
node _T_514 = or(_T_513, _T_506)
node _T_515 = or(_T_514, _T_512)
node _T_516 = and(_T_488, _T_515)
node _T_517 = or(UInt<1>(0h0), _T_516)
node _T_518 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_519 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_520 = cvt(_T_519)
node _T_521 = and(_T_520, asSInt(UInt<29>(0h10000000)))
node _T_522 = asSInt(_T_521)
node _T_523 = eq(_T_522, asSInt(UInt<1>(0h0)))
node _T_524 = and(_T_518, _T_523)
node _T_525 = or(UInt<1>(0h0), _T_524)
node _T_526 = and(_T_517, _T_525)
node _T_527 = asUInt(reset)
node _T_528 = eq(_T_527, UInt<1>(0h0))
when _T_528 :
node _T_529 = eq(_T_526, UInt<1>(0h0))
when _T_529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_526, UInt<1>(0h1), "") : assert_41
node _T_530 = asUInt(reset)
node _T_531 = eq(_T_530, UInt<1>(0h0))
when _T_531 :
node _T_532 = eq(source_ok, UInt<1>(0h0))
when _T_532 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_533 = asUInt(reset)
node _T_534 = eq(_T_533, UInt<1>(0h0))
when _T_534 :
node _T_535 = eq(is_aligned, UInt<1>(0h0))
when _T_535 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_536 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_537 = asUInt(reset)
node _T_538 = eq(_T_537, UInt<1>(0h0))
when _T_538 :
node _T_539 = eq(_T_536, UInt<1>(0h0))
when _T_539 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_536, UInt<1>(0h1), "") : assert_44
node _T_540 = eq(io.in.a.bits.mask, mask)
node _T_541 = asUInt(reset)
node _T_542 = eq(_T_541, UInt<1>(0h0))
when _T_542 :
node _T_543 = eq(_T_540, UInt<1>(0h0))
when _T_543 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_540, UInt<1>(0h1), "") : assert_45
node _T_544 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_544 :
node _T_545 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_546 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_547 = and(_T_545, _T_546)
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 4, 0)
node _T_548 = shr(io.in.a.bits.source, 5)
node _T_549 = eq(_T_548, UInt<2>(0h3))
node _T_550 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_551 = and(_T_549, _T_550)
node _T_552 = leq(uncommonBits_32, UInt<5>(0h13))
node _T_553 = and(_T_551, _T_552)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 4, 0)
node _T_554 = shr(io.in.a.bits.source, 5)
node _T_555 = eq(_T_554, UInt<2>(0h2))
node _T_556 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_557 = and(_T_555, _T_556)
node _T_558 = leq(uncommonBits_33, UInt<5>(0h13))
node _T_559 = and(_T_557, _T_558)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 4, 0)
node _T_560 = shr(io.in.a.bits.source, 5)
node _T_561 = eq(_T_560, UInt<1>(0h1))
node _T_562 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_563 = and(_T_561, _T_562)
node _T_564 = leq(uncommonBits_34, UInt<5>(0h13))
node _T_565 = and(_T_563, _T_564)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 4, 0)
node _T_566 = shr(io.in.a.bits.source, 5)
node _T_567 = eq(_T_566, UInt<1>(0h0))
node _T_568 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_569 = and(_T_567, _T_568)
node _T_570 = leq(uncommonBits_35, UInt<5>(0h13))
node _T_571 = and(_T_569, _T_570)
node _T_572 = or(_T_553, _T_559)
node _T_573 = or(_T_572, _T_565)
node _T_574 = or(_T_573, _T_571)
node _T_575 = and(_T_547, _T_574)
node _T_576 = or(UInt<1>(0h0), _T_575)
node _T_577 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_578 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_579 = cvt(_T_578)
node _T_580 = and(_T_579, asSInt(UInt<29>(0h10000000)))
node _T_581 = asSInt(_T_580)
node _T_582 = eq(_T_581, asSInt(UInt<1>(0h0)))
node _T_583 = and(_T_577, _T_582)
node _T_584 = or(UInt<1>(0h0), _T_583)
node _T_585 = and(_T_576, _T_584)
node _T_586 = asUInt(reset)
node _T_587 = eq(_T_586, UInt<1>(0h0))
when _T_587 :
node _T_588 = eq(_T_585, UInt<1>(0h0))
when _T_588 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_585, UInt<1>(0h1), "") : assert_46
node _T_589 = asUInt(reset)
node _T_590 = eq(_T_589, UInt<1>(0h0))
when _T_590 :
node _T_591 = eq(source_ok, UInt<1>(0h0))
when _T_591 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_592 = asUInt(reset)
node _T_593 = eq(_T_592, UInt<1>(0h0))
when _T_593 :
node _T_594 = eq(is_aligned, UInt<1>(0h0))
when _T_594 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_595 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_596 = asUInt(reset)
node _T_597 = eq(_T_596, UInt<1>(0h0))
when _T_597 :
node _T_598 = eq(_T_595, UInt<1>(0h0))
when _T_598 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_595, UInt<1>(0h1), "") : assert_49
node _T_599 = eq(io.in.a.bits.mask, mask)
node _T_600 = asUInt(reset)
node _T_601 = eq(_T_600, UInt<1>(0h0))
when _T_601 :
node _T_602 = eq(_T_599, UInt<1>(0h0))
when _T_602 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_599, UInt<1>(0h1), "") : assert_50
node _T_603 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_604 = asUInt(reset)
node _T_605 = eq(_T_604, UInt<1>(0h0))
when _T_605 :
node _T_606 = eq(_T_603, UInt<1>(0h0))
when _T_606 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_603, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_607 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_608 = asUInt(reset)
node _T_609 = eq(_T_608, UInt<1>(0h0))
when _T_609 :
node _T_610 = eq(_T_607, UInt<1>(0h0))
when _T_610 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_607, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 4, 0)
node _source_ok_T_26 = shr(io.in.d.bits.source, 5)
node _source_ok_T_27 = eq(_source_ok_T_26, UInt<2>(0h3))
node _source_ok_T_28 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_29 = and(_source_ok_T_27, _source_ok_T_28)
node _source_ok_T_30 = leq(source_ok_uncommonBits_4, UInt<5>(0h13))
node _source_ok_T_31 = and(_source_ok_T_29, _source_ok_T_30)
node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 4, 0)
node _source_ok_T_32 = shr(io.in.d.bits.source, 5)
node _source_ok_T_33 = eq(_source_ok_T_32, UInt<2>(0h2))
node _source_ok_T_34 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_35 = and(_source_ok_T_33, _source_ok_T_34)
node _source_ok_T_36 = leq(source_ok_uncommonBits_5, UInt<5>(0h13))
node _source_ok_T_37 = and(_source_ok_T_35, _source_ok_T_36)
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 4, 0)
node _source_ok_T_38 = shr(io.in.d.bits.source, 5)
node _source_ok_T_39 = eq(_source_ok_T_38, UInt<1>(0h1))
node _source_ok_T_40 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_41 = and(_source_ok_T_39, _source_ok_T_40)
node _source_ok_T_42 = leq(source_ok_uncommonBits_6, UInt<5>(0h13))
node _source_ok_T_43 = and(_source_ok_T_41, _source_ok_T_42)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 4, 0)
node _source_ok_T_44 = shr(io.in.d.bits.source, 5)
node _source_ok_T_45 = eq(_source_ok_T_44, UInt<1>(0h0))
node _source_ok_T_46 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_47 = and(_source_ok_T_45, _source_ok_T_46)
node _source_ok_T_48 = leq(source_ok_uncommonBits_7, UInt<5>(0h13))
node _source_ok_T_49 = and(_source_ok_T_47, _source_ok_T_48)
wire _source_ok_WIRE_1 : UInt<1>[4]
connect _source_ok_WIRE_1[0], _source_ok_T_31
connect _source_ok_WIRE_1[1], _source_ok_T_37
connect _source_ok_WIRE_1[2], _source_ok_T_43
connect _source_ok_WIRE_1[3], _source_ok_T_49
node _source_ok_T_50 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE_1[2])
node source_ok_1 = or(_source_ok_T_51, _source_ok_WIRE_1[3])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_611 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_611 :
node _T_612 = asUInt(reset)
node _T_613 = eq(_T_612, UInt<1>(0h0))
when _T_613 :
node _T_614 = eq(source_ok_1, UInt<1>(0h0))
when _T_614 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_615 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_616 = asUInt(reset)
node _T_617 = eq(_T_616, UInt<1>(0h0))
when _T_617 :
node _T_618 = eq(_T_615, UInt<1>(0h0))
when _T_618 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_615, UInt<1>(0h1), "") : assert_54
node _T_619 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_620 = asUInt(reset)
node _T_621 = eq(_T_620, UInt<1>(0h0))
when _T_621 :
node _T_622 = eq(_T_619, UInt<1>(0h0))
when _T_622 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_619, UInt<1>(0h1), "") : assert_55
node _T_623 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_624 = asUInt(reset)
node _T_625 = eq(_T_624, UInt<1>(0h0))
when _T_625 :
node _T_626 = eq(_T_623, UInt<1>(0h0))
when _T_626 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_623, UInt<1>(0h1), "") : assert_56
node _T_627 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_628 = asUInt(reset)
node _T_629 = eq(_T_628, UInt<1>(0h0))
when _T_629 :
node _T_630 = eq(_T_627, UInt<1>(0h0))
when _T_630 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_627, UInt<1>(0h1), "") : assert_57
node _T_631 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_631 :
node _T_632 = asUInt(reset)
node _T_633 = eq(_T_632, UInt<1>(0h0))
when _T_633 :
node _T_634 = eq(source_ok_1, UInt<1>(0h0))
when _T_634 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_635 = asUInt(reset)
node _T_636 = eq(_T_635, UInt<1>(0h0))
when _T_636 :
node _T_637 = eq(sink_ok, UInt<1>(0h0))
when _T_637 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_638 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_639 = asUInt(reset)
node _T_640 = eq(_T_639, UInt<1>(0h0))
when _T_640 :
node _T_641 = eq(_T_638, UInt<1>(0h0))
when _T_641 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_638, UInt<1>(0h1), "") : assert_60
node _T_642 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_643 = asUInt(reset)
node _T_644 = eq(_T_643, UInt<1>(0h0))
when _T_644 :
node _T_645 = eq(_T_642, UInt<1>(0h0))
when _T_645 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_642, UInt<1>(0h1), "") : assert_61
node _T_646 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_647 = asUInt(reset)
node _T_648 = eq(_T_647, UInt<1>(0h0))
when _T_648 :
node _T_649 = eq(_T_646, UInt<1>(0h0))
when _T_649 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_646, UInt<1>(0h1), "") : assert_62
node _T_650 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_651 = asUInt(reset)
node _T_652 = eq(_T_651, UInt<1>(0h0))
when _T_652 :
node _T_653 = eq(_T_650, UInt<1>(0h0))
when _T_653 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_650, UInt<1>(0h1), "") : assert_63
node _T_654 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_655 = or(UInt<1>(0h1), _T_654)
node _T_656 = asUInt(reset)
node _T_657 = eq(_T_656, UInt<1>(0h0))
when _T_657 :
node _T_658 = eq(_T_655, UInt<1>(0h0))
when _T_658 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_655, UInt<1>(0h1), "") : assert_64
node _T_659 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_659 :
node _T_660 = asUInt(reset)
node _T_661 = eq(_T_660, UInt<1>(0h0))
when _T_661 :
node _T_662 = eq(source_ok_1, UInt<1>(0h0))
when _T_662 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_663 = asUInt(reset)
node _T_664 = eq(_T_663, UInt<1>(0h0))
when _T_664 :
node _T_665 = eq(sink_ok, UInt<1>(0h0))
when _T_665 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_666 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_667 = asUInt(reset)
node _T_668 = eq(_T_667, UInt<1>(0h0))
when _T_668 :
node _T_669 = eq(_T_666, UInt<1>(0h0))
when _T_669 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_666, UInt<1>(0h1), "") : assert_67
node _T_670 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_671 = asUInt(reset)
node _T_672 = eq(_T_671, UInt<1>(0h0))
when _T_672 :
node _T_673 = eq(_T_670, UInt<1>(0h0))
when _T_673 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_670, UInt<1>(0h1), "") : assert_68
node _T_674 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_675 = asUInt(reset)
node _T_676 = eq(_T_675, UInt<1>(0h0))
when _T_676 :
node _T_677 = eq(_T_674, UInt<1>(0h0))
when _T_677 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_674, UInt<1>(0h1), "") : assert_69
node _T_678 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_679 = or(_T_678, io.in.d.bits.corrupt)
node _T_680 = asUInt(reset)
node _T_681 = eq(_T_680, UInt<1>(0h0))
when _T_681 :
node _T_682 = eq(_T_679, UInt<1>(0h0))
when _T_682 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_679, UInt<1>(0h1), "") : assert_70
node _T_683 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_684 = or(UInt<1>(0h1), _T_683)
node _T_685 = asUInt(reset)
node _T_686 = eq(_T_685, UInt<1>(0h0))
when _T_686 :
node _T_687 = eq(_T_684, UInt<1>(0h0))
when _T_687 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_684, UInt<1>(0h1), "") : assert_71
node _T_688 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_688 :
node _T_689 = asUInt(reset)
node _T_690 = eq(_T_689, UInt<1>(0h0))
when _T_690 :
node _T_691 = eq(source_ok_1, UInt<1>(0h0))
when _T_691 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_692 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_693 = asUInt(reset)
node _T_694 = eq(_T_693, UInt<1>(0h0))
when _T_694 :
node _T_695 = eq(_T_692, UInt<1>(0h0))
when _T_695 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_692, UInt<1>(0h1), "") : assert_73
node _T_696 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_697 = asUInt(reset)
node _T_698 = eq(_T_697, UInt<1>(0h0))
when _T_698 :
node _T_699 = eq(_T_696, UInt<1>(0h0))
when _T_699 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_696, UInt<1>(0h1), "") : assert_74
node _T_700 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_701 = or(UInt<1>(0h1), _T_700)
node _T_702 = asUInt(reset)
node _T_703 = eq(_T_702, UInt<1>(0h0))
when _T_703 :
node _T_704 = eq(_T_701, UInt<1>(0h0))
when _T_704 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_701, UInt<1>(0h1), "") : assert_75
node _T_705 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_705 :
node _T_706 = asUInt(reset)
node _T_707 = eq(_T_706, UInt<1>(0h0))
when _T_707 :
node _T_708 = eq(source_ok_1, UInt<1>(0h0))
when _T_708 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_709 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_710 = asUInt(reset)
node _T_711 = eq(_T_710, UInt<1>(0h0))
when _T_711 :
node _T_712 = eq(_T_709, UInt<1>(0h0))
when _T_712 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_709, UInt<1>(0h1), "") : assert_77
node _T_713 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_714 = or(_T_713, io.in.d.bits.corrupt)
node _T_715 = asUInt(reset)
node _T_716 = eq(_T_715, UInt<1>(0h0))
when _T_716 :
node _T_717 = eq(_T_714, UInt<1>(0h0))
when _T_717 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_714, UInt<1>(0h1), "") : assert_78
node _T_718 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_719 = or(UInt<1>(0h1), _T_718)
node _T_720 = asUInt(reset)
node _T_721 = eq(_T_720, UInt<1>(0h0))
when _T_721 :
node _T_722 = eq(_T_719, UInt<1>(0h0))
when _T_722 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_719, UInt<1>(0h1), "") : assert_79
node _T_723 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_723 :
node _T_724 = asUInt(reset)
node _T_725 = eq(_T_724, UInt<1>(0h0))
when _T_725 :
node _T_726 = eq(source_ok_1, UInt<1>(0h0))
when _T_726 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_727 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_728 = asUInt(reset)
node _T_729 = eq(_T_728, UInt<1>(0h0))
when _T_729 :
node _T_730 = eq(_T_727, UInt<1>(0h0))
when _T_730 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_727, UInt<1>(0h1), "") : assert_81
node _T_731 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_732 = asUInt(reset)
node _T_733 = eq(_T_732, UInt<1>(0h0))
when _T_733 :
node _T_734 = eq(_T_731, UInt<1>(0h0))
when _T_734 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_731, UInt<1>(0h1), "") : assert_82
node _T_735 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_736 = or(UInt<1>(0h1), _T_735)
node _T_737 = asUInt(reset)
node _T_738 = eq(_T_737, UInt<1>(0h0))
when _T_738 :
node _T_739 = eq(_T_736, UInt<1>(0h0))
when _T_739 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_736, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<7>(0h0)
connect _WIRE.bits.size, UInt<3>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_740 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_741 = asUInt(reset)
node _T_742 = eq(_T_741, UInt<1>(0h0))
when _T_742 :
node _T_743 = eq(_T_740, UInt<1>(0h0))
when _T_743 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_740, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<7>(0h0)
connect _WIRE_2.bits.size, UInt<3>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_744 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_745 = asUInt(reset)
node _T_746 = eq(_T_745, UInt<1>(0h0))
when _T_746 :
node _T_747 = eq(_T_744, UInt<1>(0h0))
when _T_747 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_744, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_748 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_749 = asUInt(reset)
node _T_750 = eq(_T_749, UInt<1>(0h0))
when _T_750 :
node _T_751 = eq(_T_748, UInt<1>(0h0))
when _T_751 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_748, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_752 = eq(a_first, UInt<1>(0h0))
node _T_753 = and(io.in.a.valid, _T_752)
when _T_753 :
node _T_754 = eq(io.in.a.bits.opcode, opcode)
node _T_755 = asUInt(reset)
node _T_756 = eq(_T_755, UInt<1>(0h0))
when _T_756 :
node _T_757 = eq(_T_754, UInt<1>(0h0))
when _T_757 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_754, UInt<1>(0h1), "") : assert_87
node _T_758 = eq(io.in.a.bits.param, param)
node _T_759 = asUInt(reset)
node _T_760 = eq(_T_759, UInt<1>(0h0))
when _T_760 :
node _T_761 = eq(_T_758, UInt<1>(0h0))
when _T_761 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_758, UInt<1>(0h1), "") : assert_88
node _T_762 = eq(io.in.a.bits.size, size)
node _T_763 = asUInt(reset)
node _T_764 = eq(_T_763, UInt<1>(0h0))
when _T_764 :
node _T_765 = eq(_T_762, UInt<1>(0h0))
when _T_765 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_762, UInt<1>(0h1), "") : assert_89
node _T_766 = eq(io.in.a.bits.source, source)
node _T_767 = asUInt(reset)
node _T_768 = eq(_T_767, UInt<1>(0h0))
when _T_768 :
node _T_769 = eq(_T_766, UInt<1>(0h0))
when _T_769 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_766, UInt<1>(0h1), "") : assert_90
node _T_770 = eq(io.in.a.bits.address, address)
node _T_771 = asUInt(reset)
node _T_772 = eq(_T_771, UInt<1>(0h0))
when _T_772 :
node _T_773 = eq(_T_770, UInt<1>(0h0))
when _T_773 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_770, UInt<1>(0h1), "") : assert_91
node _T_774 = and(io.in.a.ready, io.in.a.valid)
node _T_775 = and(_T_774, a_first)
when _T_775 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_776 = eq(d_first, UInt<1>(0h0))
node _T_777 = and(io.in.d.valid, _T_776)
when _T_777 :
node _T_778 = eq(io.in.d.bits.opcode, opcode_1)
node _T_779 = asUInt(reset)
node _T_780 = eq(_T_779, UInt<1>(0h0))
when _T_780 :
node _T_781 = eq(_T_778, UInt<1>(0h0))
when _T_781 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_778, UInt<1>(0h1), "") : assert_92
node _T_782 = eq(io.in.d.bits.param, param_1)
node _T_783 = asUInt(reset)
node _T_784 = eq(_T_783, UInt<1>(0h0))
when _T_784 :
node _T_785 = eq(_T_782, UInt<1>(0h0))
when _T_785 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_782, UInt<1>(0h1), "") : assert_93
node _T_786 = eq(io.in.d.bits.size, size_1)
node _T_787 = asUInt(reset)
node _T_788 = eq(_T_787, UInt<1>(0h0))
when _T_788 :
node _T_789 = eq(_T_786, UInt<1>(0h0))
when _T_789 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_786, UInt<1>(0h1), "") : assert_94
node _T_790 = eq(io.in.d.bits.source, source_1)
node _T_791 = asUInt(reset)
node _T_792 = eq(_T_791, UInt<1>(0h0))
when _T_792 :
node _T_793 = eq(_T_790, UInt<1>(0h0))
when _T_793 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_790, UInt<1>(0h1), "") : assert_95
node _T_794 = eq(io.in.d.bits.sink, sink)
node _T_795 = asUInt(reset)
node _T_796 = eq(_T_795, UInt<1>(0h0))
when _T_796 :
node _T_797 = eq(_T_794, UInt<1>(0h0))
when _T_797 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_794, UInt<1>(0h1), "") : assert_96
node _T_798 = eq(io.in.d.bits.denied, denied)
node _T_799 = asUInt(reset)
node _T_800 = eq(_T_799, UInt<1>(0h0))
when _T_800 :
node _T_801 = eq(_T_798, UInt<1>(0h0))
when _T_801 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_798, UInt<1>(0h1), "") : assert_97
node _T_802 = and(io.in.d.ready, io.in.d.valid)
node _T_803 = and(_T_802, d_first)
when _T_803 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<116>, clock, reset, UInt<116>(0h0)
regreset inflight_opcodes : UInt<464>, clock, reset, UInt<464>(0h0)
regreset inflight_sizes : UInt<464>, clock, reset, UInt<464>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<116>
connect a_set, UInt<116>(0h0)
wire a_set_wo_ready : UInt<116>
connect a_set_wo_ready, UInt<116>(0h0)
wire a_opcodes_set : UInt<464>
connect a_opcodes_set, UInt<464>(0h0)
wire a_sizes_set : UInt<464>
connect a_sizes_set, UInt<464>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_804 = and(io.in.a.valid, a_first_1)
node _T_805 = and(_T_804, UInt<1>(0h1))
when _T_805 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_806 = and(io.in.a.ready, io.in.a.valid)
node _T_807 = and(_T_806, a_first_1)
node _T_808 = and(_T_807, UInt<1>(0h1))
when _T_808 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_809 = dshr(inflight, io.in.a.bits.source)
node _T_810 = bits(_T_809, 0, 0)
node _T_811 = eq(_T_810, UInt<1>(0h0))
node _T_812 = asUInt(reset)
node _T_813 = eq(_T_812, UInt<1>(0h0))
when _T_813 :
node _T_814 = eq(_T_811, UInt<1>(0h0))
when _T_814 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_811, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<116>
connect d_clr, UInt<116>(0h0)
wire d_clr_wo_ready : UInt<116>
connect d_clr_wo_ready, UInt<116>(0h0)
wire d_opcodes_clr : UInt<464>
connect d_opcodes_clr, UInt<464>(0h0)
wire d_sizes_clr : UInt<464>
connect d_sizes_clr, UInt<464>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_815 = and(io.in.d.valid, d_first_1)
node _T_816 = and(_T_815, UInt<1>(0h1))
node _T_817 = eq(d_release_ack, UInt<1>(0h0))
node _T_818 = and(_T_816, _T_817)
when _T_818 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_819 = and(io.in.d.ready, io.in.d.valid)
node _T_820 = and(_T_819, d_first_1)
node _T_821 = and(_T_820, UInt<1>(0h1))
node _T_822 = eq(d_release_ack, UInt<1>(0h0))
node _T_823 = and(_T_821, _T_822)
when _T_823 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_824 = and(io.in.d.valid, d_first_1)
node _T_825 = and(_T_824, UInt<1>(0h1))
node _T_826 = eq(d_release_ack, UInt<1>(0h0))
node _T_827 = and(_T_825, _T_826)
when _T_827 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_828 = dshr(inflight, io.in.d.bits.source)
node _T_829 = bits(_T_828, 0, 0)
node _T_830 = or(_T_829, same_cycle_resp)
node _T_831 = asUInt(reset)
node _T_832 = eq(_T_831, UInt<1>(0h0))
when _T_832 :
node _T_833 = eq(_T_830, UInt<1>(0h0))
when _T_833 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_830, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_834 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_835 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_836 = or(_T_834, _T_835)
node _T_837 = asUInt(reset)
node _T_838 = eq(_T_837, UInt<1>(0h0))
when _T_838 :
node _T_839 = eq(_T_836, UInt<1>(0h0))
when _T_839 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_836, UInt<1>(0h1), "") : assert_100
node _T_840 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_841 = asUInt(reset)
node _T_842 = eq(_T_841, UInt<1>(0h0))
when _T_842 :
node _T_843 = eq(_T_840, UInt<1>(0h0))
when _T_843 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_840, UInt<1>(0h1), "") : assert_101
else :
node _T_844 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_845 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_846 = or(_T_844, _T_845)
node _T_847 = asUInt(reset)
node _T_848 = eq(_T_847, UInt<1>(0h0))
when _T_848 :
node _T_849 = eq(_T_846, UInt<1>(0h0))
when _T_849 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_846, UInt<1>(0h1), "") : assert_102
node _T_850 = eq(io.in.d.bits.size, a_size_lookup)
node _T_851 = asUInt(reset)
node _T_852 = eq(_T_851, UInt<1>(0h0))
when _T_852 :
node _T_853 = eq(_T_850, UInt<1>(0h0))
when _T_853 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_850, UInt<1>(0h1), "") : assert_103
node _T_854 = and(io.in.d.valid, d_first_1)
node _T_855 = and(_T_854, a_first_1)
node _T_856 = and(_T_855, io.in.a.valid)
node _T_857 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_858 = and(_T_856, _T_857)
node _T_859 = eq(d_release_ack, UInt<1>(0h0))
node _T_860 = and(_T_858, _T_859)
when _T_860 :
node _T_861 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_862 = or(_T_861, io.in.a.ready)
node _T_863 = asUInt(reset)
node _T_864 = eq(_T_863, UInt<1>(0h0))
when _T_864 :
node _T_865 = eq(_T_862, UInt<1>(0h0))
when _T_865 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_862, UInt<1>(0h1), "") : assert_104
node _T_866 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_867 = orr(a_set_wo_ready)
node _T_868 = eq(_T_867, UInt<1>(0h0))
node _T_869 = or(_T_866, _T_868)
node _T_870 = asUInt(reset)
node _T_871 = eq(_T_870, UInt<1>(0h0))
when _T_871 :
node _T_872 = eq(_T_869, UInt<1>(0h0))
when _T_872 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_869, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_122
node _T_873 = orr(inflight)
node _T_874 = eq(_T_873, UInt<1>(0h0))
node _T_875 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_876 = or(_T_874, _T_875)
node _T_877 = lt(watchdog, plusarg_reader.out)
node _T_878 = or(_T_876, _T_877)
node _T_879 = asUInt(reset)
node _T_880 = eq(_T_879, UInt<1>(0h0))
when _T_880 :
node _T_881 = eq(_T_878, UInt<1>(0h0))
when _T_881 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_878, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_882 = and(io.in.a.ready, io.in.a.valid)
node _T_883 = and(io.in.d.ready, io.in.d.valid)
node _T_884 = or(_T_882, _T_883)
when _T_884 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<116>, clock, reset, UInt<116>(0h0)
regreset inflight_opcodes_1 : UInt<464>, clock, reset, UInt<464>(0h0)
regreset inflight_sizes_1 : UInt<464>, clock, reset, UInt<464>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<32>(0h0)
connect _c_first_WIRE.bits.source, UInt<7>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<116>
connect c_set, UInt<116>(0h0)
wire c_set_wo_ready : UInt<116>
connect c_set_wo_ready, UInt<116>(0h0)
wire c_opcodes_set : UInt<464>
connect c_opcodes_set, UInt<464>(0h0)
wire c_sizes_set : UInt<464>
connect c_sizes_set, UInt<464>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<7>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_885 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<7>(0h0)
connect _WIRE_8.bits.size, UInt<3>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_886 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_887 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_888 = and(_T_886, _T_887)
node _T_889 = and(_T_885, _T_888)
when _T_889 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<7>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_890 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_891 = and(_T_890, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<7>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_892 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_893 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_894 = and(_T_892, _T_893)
node _T_895 = and(_T_891, _T_894)
when _T_895 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<7>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_896 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_897 = bits(_T_896, 0, 0)
node _T_898 = eq(_T_897, UInt<1>(0h0))
node _T_899 = asUInt(reset)
node _T_900 = eq(_T_899, UInt<1>(0h0))
when _T_900 :
node _T_901 = eq(_T_898, UInt<1>(0h0))
when _T_901 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_898, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<116>
connect d_clr_1, UInt<116>(0h0)
wire d_clr_wo_ready_1 : UInt<116>
connect d_clr_wo_ready_1, UInt<116>(0h0)
wire d_opcodes_clr_1 : UInt<464>
connect d_opcodes_clr_1, UInt<464>(0h0)
wire d_sizes_clr_1 : UInt<464>
connect d_sizes_clr_1, UInt<464>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_902 = and(io.in.d.valid, d_first_2)
node _T_903 = and(_T_902, UInt<1>(0h1))
node _T_904 = and(_T_903, d_release_ack_1)
when _T_904 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_905 = and(io.in.d.ready, io.in.d.valid)
node _T_906 = and(_T_905, d_first_2)
node _T_907 = and(_T_906, UInt<1>(0h1))
node _T_908 = and(_T_907, d_release_ack_1)
when _T_908 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_909 = and(io.in.d.valid, d_first_2)
node _T_910 = and(_T_909, UInt<1>(0h1))
node _T_911 = and(_T_910, d_release_ack_1)
when _T_911 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_912 = dshr(inflight_1, io.in.d.bits.source)
node _T_913 = bits(_T_912, 0, 0)
node _T_914 = or(_T_913, same_cycle_resp_1)
node _T_915 = asUInt(reset)
node _T_916 = eq(_T_915, UInt<1>(0h0))
when _T_916 :
node _T_917 = eq(_T_914, UInt<1>(0h0))
when _T_917 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_914, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<32>(0h0)
connect _WIRE_16.bits.source, UInt<7>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_918 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_919 = asUInt(reset)
node _T_920 = eq(_T_919, UInt<1>(0h0))
when _T_920 :
node _T_921 = eq(_T_918, UInt<1>(0h0))
when _T_921 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_918, UInt<1>(0h1), "") : assert_109
else :
node _T_922 = eq(io.in.d.bits.size, c_size_lookup)
node _T_923 = asUInt(reset)
node _T_924 = eq(_T_923, UInt<1>(0h0))
when _T_924 :
node _T_925 = eq(_T_922, UInt<1>(0h0))
when _T_925 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_922, UInt<1>(0h1), "") : assert_110
node _T_926 = and(io.in.d.valid, d_first_2)
node _T_927 = and(_T_926, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<32>(0h0)
connect _WIRE_18.bits.source, UInt<7>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_928 = and(_T_927, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<32>(0h0)
connect _WIRE_20.bits.source, UInt<7>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_929 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_930 = and(_T_928, _T_929)
node _T_931 = and(_T_930, d_release_ack_1)
node _T_932 = eq(c_probe_ack, UInt<1>(0h0))
node _T_933 = and(_T_931, _T_932)
when _T_933 :
node _T_934 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<32>(0h0)
connect _WIRE_22.bits.source, UInt<7>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_935 = or(_T_934, _WIRE_23.ready)
node _T_936 = asUInt(reset)
node _T_937 = eq(_T_936, UInt<1>(0h0))
when _T_937 :
node _T_938 = eq(_T_935, UInt<1>(0h0))
when _T_938 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_935, UInt<1>(0h1), "") : assert_111
node _T_939 = orr(c_set_wo_ready)
when _T_939 :
node _T_940 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_941 = asUInt(reset)
node _T_942 = eq(_T_941, UInt<1>(0h0))
when _T_942 :
node _T_943 = eq(_T_940, UInt<1>(0h0))
when _T_943 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_940, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_123
node _T_944 = orr(inflight_1)
node _T_945 = eq(_T_944, UInt<1>(0h0))
node _T_946 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_947 = or(_T_945, _T_946)
node _T_948 = lt(watchdog_1, plusarg_reader_1.out)
node _T_949 = or(_T_947, _T_948)
node _T_950 = asUInt(reset)
node _T_951 = eq(_T_950, UInt<1>(0h0))
when _T_951 :
node _T_952 = eq(_T_949, UInt<1>(0h0))
when _T_952 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_949, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<7>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_953 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_954 = and(io.in.d.ready, io.in.d.valid)
node _T_955 = or(_T_953, _T_954)
when _T_955 :
connect watchdog_1, UInt<1>(0h0)
extmodule plusarg_reader_124 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_125 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLMonitor_45( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg denied; // @[Monitor.scala:543:22]
reg [115:0] inflight; // @[Monitor.scala:614:27]
reg [463:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [463:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire [127:0] _GEN_0 = {121'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
wire [127:0] _GEN_3 = {121'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [115:0] inflight_1; // @[Monitor.scala:726:35]
reg [463:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module TLXbar_pbus_out_i1_o3_a29d64s10k1z3u :
input clock : Clock
input reset : Reset
output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonIn.d.bits.corrupt
invalidate anonIn.d.bits.data
invalidate anonIn.d.bits.denied
invalidate anonIn.d.bits.sink
invalidate anonIn.d.bits.source
invalidate anonIn.d.bits.size
invalidate anonIn.d.bits.param
invalidate anonIn.d.bits.opcode
invalidate anonIn.d.valid
invalidate anonIn.d.ready
invalidate anonIn.a.bits.corrupt
invalidate anonIn.a.bits.data
invalidate anonIn.a.bits.mask
invalidate anonIn.a.bits.user.amba_prot.fetch
invalidate anonIn.a.bits.user.amba_prot.secure
invalidate anonIn.a.bits.user.amba_prot.privileged
invalidate anonIn.a.bits.user.amba_prot.writealloc
invalidate anonIn.a.bits.user.amba_prot.readalloc
invalidate anonIn.a.bits.user.amba_prot.modifiable
invalidate anonIn.a.bits.user.amba_prot.bufferable
invalidate anonIn.a.bits.address
invalidate anonIn.a.bits.source
invalidate anonIn.a.bits.size
invalidate anonIn.a.bits.param
invalidate anonIn.a.bits.opcode
invalidate anonIn.a.valid
invalidate anonIn.a.ready
inst monitor of TLMonitor_7
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, anonIn.d.bits.data
connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied
connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink
connect monitor.io.in.d.bits.source, anonIn.d.bits.source
connect monitor.io.in.d.bits.size, anonIn.d.bits.size
connect monitor.io.in.d.bits.param, anonIn.d.bits.param
connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode
connect monitor.io.in.d.valid, anonIn.d.valid
connect monitor.io.in.d.ready, anonIn.d.ready
connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, anonIn.a.bits.data
connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask
connect monitor.io.in.a.bits.user.amba_prot.fetch, anonIn.a.bits.user.amba_prot.fetch
connect monitor.io.in.a.bits.user.amba_prot.secure, anonIn.a.bits.user.amba_prot.secure
connect monitor.io.in.a.bits.user.amba_prot.privileged, anonIn.a.bits.user.amba_prot.privileged
connect monitor.io.in.a.bits.user.amba_prot.writealloc, anonIn.a.bits.user.amba_prot.writealloc
connect monitor.io.in.a.bits.user.amba_prot.readalloc, anonIn.a.bits.user.amba_prot.readalloc
connect monitor.io.in.a.bits.user.amba_prot.modifiable, anonIn.a.bits.user.amba_prot.modifiable
connect monitor.io.in.a.bits.user.amba_prot.bufferable, anonIn.a.bits.user.amba_prot.bufferable
connect monitor.io.in.a.bits.address, anonIn.a.bits.address
connect monitor.io.in.a.bits.source, anonIn.a.bits.source
connect monitor.io.in.a.bits.size, anonIn.a.bits.size
connect monitor.io.in.a.bits.param, anonIn.a.bits.param
connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode
connect monitor.io.in.a.valid, anonIn.a.valid
connect monitor.io.in.a.ready, anonIn.a.ready
wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonOut.d.bits.corrupt
invalidate anonOut.d.bits.data
invalidate anonOut.d.bits.denied
invalidate anonOut.d.bits.sink
invalidate anonOut.d.bits.source
invalidate anonOut.d.bits.size
invalidate anonOut.d.bits.param
invalidate anonOut.d.bits.opcode
invalidate anonOut.d.valid
invalidate anonOut.d.ready
invalidate anonOut.a.bits.corrupt
invalidate anonOut.a.bits.data
invalidate anonOut.a.bits.mask
invalidate anonOut.a.bits.address
invalidate anonOut.a.bits.source
invalidate anonOut.a.bits.size
invalidate anonOut.a.bits.param
invalidate anonOut.a.bits.opcode
invalidate anonOut.a.valid
invalidate anonOut.a.ready
wire x1_anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_anonOut.d.bits.corrupt
invalidate x1_anonOut.d.bits.data
invalidate x1_anonOut.d.bits.denied
invalidate x1_anonOut.d.bits.sink
invalidate x1_anonOut.d.bits.source
invalidate x1_anonOut.d.bits.size
invalidate x1_anonOut.d.bits.param
invalidate x1_anonOut.d.bits.opcode
invalidate x1_anonOut.d.valid
invalidate x1_anonOut.d.ready
invalidate x1_anonOut.a.bits.corrupt
invalidate x1_anonOut.a.bits.data
invalidate x1_anonOut.a.bits.mask
invalidate x1_anonOut.a.bits.address
invalidate x1_anonOut.a.bits.source
invalidate x1_anonOut.a.bits.size
invalidate x1_anonOut.a.bits.param
invalidate x1_anonOut.a.bits.opcode
invalidate x1_anonOut.a.valid
invalidate x1_anonOut.a.ready
wire x1_anonOut_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_anonOut_1.d.bits.corrupt
invalidate x1_anonOut_1.d.bits.data
invalidate x1_anonOut_1.d.bits.denied
invalidate x1_anonOut_1.d.bits.sink
invalidate x1_anonOut_1.d.bits.source
invalidate x1_anonOut_1.d.bits.size
invalidate x1_anonOut_1.d.bits.param
invalidate x1_anonOut_1.d.bits.opcode
invalidate x1_anonOut_1.d.valid
invalidate x1_anonOut_1.d.ready
invalidate x1_anonOut_1.a.bits.corrupt
invalidate x1_anonOut_1.a.bits.data
invalidate x1_anonOut_1.a.bits.mask
invalidate x1_anonOut_1.a.bits.user.amba_prot.fetch
invalidate x1_anonOut_1.a.bits.user.amba_prot.secure
invalidate x1_anonOut_1.a.bits.user.amba_prot.privileged
invalidate x1_anonOut_1.a.bits.user.amba_prot.writealloc
invalidate x1_anonOut_1.a.bits.user.amba_prot.readalloc
invalidate x1_anonOut_1.a.bits.user.amba_prot.modifiable
invalidate x1_anonOut_1.a.bits.user.amba_prot.bufferable
invalidate x1_anonOut_1.a.bits.address
invalidate x1_anonOut_1.a.bits.source
invalidate x1_anonOut_1.a.bits.size
invalidate x1_anonOut_1.a.bits.param
invalidate x1_anonOut_1.a.bits.opcode
invalidate x1_anonOut_1.a.valid
invalidate x1_anonOut_1.a.ready
connect auto.anon_out_0, anonOut
connect auto.anon_out_1, x1_anonOut
connect auto.anon_out_2, x1_anonOut_1
connect anonIn, auto.anon_in
wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[1]
invalidate in[0].a.bits.user.amba_prot.fetch
invalidate in[0].a.bits.user.amba_prot.secure
invalidate in[0].a.bits.user.amba_prot.privileged
invalidate in[0].a.bits.user.amba_prot.writealloc
invalidate in[0].a.bits.user.amba_prot.readalloc
invalidate in[0].a.bits.user.amba_prot.modifiable
invalidate in[0].a.bits.user.amba_prot.bufferable
connect in[0].a.bits.corrupt, anonIn.a.bits.corrupt
connect in[0].a.bits.data, anonIn.a.bits.data
connect in[0].a.bits.mask, anonIn.a.bits.mask
connect in[0].a.bits.user.amba_prot.fetch, anonIn.a.bits.user.amba_prot.fetch
connect in[0].a.bits.user.amba_prot.secure, anonIn.a.bits.user.amba_prot.secure
connect in[0].a.bits.user.amba_prot.privileged, anonIn.a.bits.user.amba_prot.privileged
connect in[0].a.bits.user.amba_prot.writealloc, anonIn.a.bits.user.amba_prot.writealloc
connect in[0].a.bits.user.amba_prot.readalloc, anonIn.a.bits.user.amba_prot.readalloc
connect in[0].a.bits.user.amba_prot.modifiable, anonIn.a.bits.user.amba_prot.modifiable
connect in[0].a.bits.user.amba_prot.bufferable, anonIn.a.bits.user.amba_prot.bufferable
connect in[0].a.bits.address, anonIn.a.bits.address
connect in[0].a.bits.source, anonIn.a.bits.source
connect in[0].a.bits.size, anonIn.a.bits.size
connect in[0].a.bits.param, anonIn.a.bits.param
connect in[0].a.bits.opcode, anonIn.a.bits.opcode
connect in[0].a.valid, anonIn.a.valid
connect anonIn.a.ready, in[0].a.ready
node _in_0_a_bits_source_T = or(anonIn.a.bits.source, UInt<1>(0h0))
connect in[0].a.bits.source, _in_0_a_bits_source_T
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<29>(0h0)
connect _WIRE.bits.source, UInt<10>(0h0)
connect _WIRE.bits.size, UInt<3>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
invalidate _WIRE_1.bits.corrupt
invalidate _WIRE_1.bits.data
invalidate _WIRE_1.bits.mask
invalidate _WIRE_1.bits.address
invalidate _WIRE_1.bits.source
invalidate _WIRE_1.bits.size
invalidate _WIRE_1.bits.param
invalidate _WIRE_1.bits.opcode
invalidate _WIRE_1.valid
invalidate _WIRE_1.ready
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.mask, UInt<8>(0h0)
connect _WIRE_2.bits.address, UInt<29>(0h0)
connect _WIRE_2.bits.source, UInt<10>(0h0)
connect _WIRE_2.bits.size, UInt<3>(0h0)
connect _WIRE_2.bits.param, UInt<2>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
invalidate _WIRE_3.bits.corrupt
invalidate _WIRE_3.bits.data
invalidate _WIRE_3.bits.mask
invalidate _WIRE_3.bits.address
invalidate _WIRE_3.bits.source
invalidate _WIRE_3.bits.size
invalidate _WIRE_3.bits.param
invalidate _WIRE_3.bits.opcode
invalidate _WIRE_3.valid
invalidate _WIRE_3.ready
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<29>(0h0)
connect _WIRE_4.bits.source, UInt<10>(0h0)
connect _WIRE_4.bits.size, UInt<3>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.mask, UInt<8>(0h0)
connect _WIRE_6.bits.address, UInt<29>(0h0)
connect _WIRE_6.bits.source, UInt<10>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<2>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
connect _WIRE_7.valid, UInt<1>(0h0)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_8.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_8.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_8.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_8.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_8.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_8.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_8.bits.address, UInt<29>(0h0)
connect _WIRE_8.bits.source, UInt<10>(0h0)
connect _WIRE_8.bits.size, UInt<3>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
invalidate _WIRE_9.bits.corrupt
invalidate _WIRE_9.bits.data
invalidate _WIRE_9.bits.user.amba_prot.fetch
invalidate _WIRE_9.bits.user.amba_prot.secure
invalidate _WIRE_9.bits.user.amba_prot.privileged
invalidate _WIRE_9.bits.user.amba_prot.writealloc
invalidate _WIRE_9.bits.user.amba_prot.readalloc
invalidate _WIRE_9.bits.user.amba_prot.modifiable
invalidate _WIRE_9.bits.user.amba_prot.bufferable
invalidate _WIRE_9.bits.address
invalidate _WIRE_9.bits.source
invalidate _WIRE_9.bits.size
invalidate _WIRE_9.bits.param
invalidate _WIRE_9.bits.opcode
invalidate _WIRE_9.valid
invalidate _WIRE_9.ready
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_10.bits.address, UInt<29>(0h0)
connect _WIRE_10.bits.source, UInt<10>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
invalidate _WIRE_11.bits.corrupt
invalidate _WIRE_11.bits.data
invalidate _WIRE_11.bits.user.amba_prot.fetch
invalidate _WIRE_11.bits.user.amba_prot.secure
invalidate _WIRE_11.bits.user.amba_prot.privileged
invalidate _WIRE_11.bits.user.amba_prot.writealloc
invalidate _WIRE_11.bits.user.amba_prot.readalloc
invalidate _WIRE_11.bits.user.amba_prot.modifiable
invalidate _WIRE_11.bits.user.amba_prot.bufferable
invalidate _WIRE_11.bits.address
invalidate _WIRE_11.bits.source
invalidate _WIRE_11.bits.size
invalidate _WIRE_11.bits.param
invalidate _WIRE_11.bits.opcode
invalidate _WIRE_11.valid
invalidate _WIRE_11.ready
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_12.bits.address, UInt<29>(0h0)
connect _WIRE_12.bits.source, UInt<10>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
connect _WIRE_13.valid, UInt<1>(0h0)
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_14.bits.address, UInt<29>(0h0)
connect _WIRE_14.bits.source, UInt<10>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
connect _WIRE_15.ready, UInt<1>(0h1)
connect anonIn.d.bits.corrupt, in[0].d.bits.corrupt
connect anonIn.d.bits.data, in[0].d.bits.data
connect anonIn.d.bits.denied, in[0].d.bits.denied
connect anonIn.d.bits.sink, in[0].d.bits.sink
connect anonIn.d.bits.source, in[0].d.bits.source
connect anonIn.d.bits.size, in[0].d.bits.size
connect anonIn.d.bits.param, in[0].d.bits.param
connect anonIn.d.bits.opcode, in[0].d.bits.opcode
connect anonIn.d.valid, in[0].d.valid
connect in[0].d.ready, anonIn.d.ready
node _anonIn_d_bits_source_T = bits(in[0].d.bits.source, 9, 0)
connect anonIn.d.bits.source, _anonIn_d_bits_source_T
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_16.bits.sink, UInt<1>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
invalidate _WIRE_17.bits.sink
invalidate _WIRE_17.valid
invalidate _WIRE_17.ready
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_18.bits.sink, UInt<1>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
invalidate _WIRE_19.bits.sink
invalidate _WIRE_19.valid
invalidate _WIRE_19.ready
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_20.bits.sink, UInt<1>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
connect _WIRE_21.valid, UInt<1>(0h0)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_22.bits.sink, UInt<1>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
connect _WIRE_23.ready, UInt<1>(0h1)
wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[3]
invalidate out[0].a.bits.user.amba_prot.fetch
invalidate out[0].a.bits.user.amba_prot.secure
invalidate out[0].a.bits.user.amba_prot.privileged
invalidate out[0].a.bits.user.amba_prot.writealloc
invalidate out[0].a.bits.user.amba_prot.readalloc
invalidate out[0].a.bits.user.amba_prot.modifiable
invalidate out[0].a.bits.user.amba_prot.bufferable
connect anonOut.a.bits.corrupt, out[0].a.bits.corrupt
connect anonOut.a.bits.data, out[0].a.bits.data
connect anonOut.a.bits.mask, out[0].a.bits.mask
connect anonOut.a.bits.address, out[0].a.bits.address
connect anonOut.a.bits.source, out[0].a.bits.source
connect anonOut.a.bits.size, out[0].a.bits.size
connect anonOut.a.bits.param, out[0].a.bits.param
connect anonOut.a.bits.opcode, out[0].a.bits.opcode
connect anonOut.a.valid, out[0].a.valid
connect out[0].a.ready, anonOut.a.ready
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.mask, UInt<8>(0h0)
connect _WIRE_24.bits.address, UInt<29>(0h0)
connect _WIRE_24.bits.source, UInt<10>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<2>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
invalidate _WIRE_25.bits.corrupt
invalidate _WIRE_25.bits.data
invalidate _WIRE_25.bits.mask
invalidate _WIRE_25.bits.address
invalidate _WIRE_25.bits.source
invalidate _WIRE_25.bits.size
invalidate _WIRE_25.bits.param
invalidate _WIRE_25.bits.opcode
invalidate _WIRE_25.valid
invalidate _WIRE_25.ready
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.mask, UInt<8>(0h0)
connect _WIRE_26.bits.address, UInt<13>(0h0)
connect _WIRE_26.bits.source, UInt<10>(0h0)
connect _WIRE_26.bits.size, UInt<3>(0h0)
connect _WIRE_26.bits.param, UInt<2>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
invalidate _WIRE_27.bits.corrupt
invalidate _WIRE_27.bits.data
invalidate _WIRE_27.bits.mask
invalidate _WIRE_27.bits.address
invalidate _WIRE_27.bits.source
invalidate _WIRE_27.bits.size
invalidate _WIRE_27.bits.param
invalidate _WIRE_27.bits.opcode
invalidate _WIRE_27.valid
invalidate _WIRE_27.ready
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.mask, UInt<8>(0h0)
connect _WIRE_28.bits.address, UInt<29>(0h0)
connect _WIRE_28.bits.source, UInt<10>(0h0)
connect _WIRE_28.bits.size, UInt<3>(0h0)
connect _WIRE_28.bits.param, UInt<2>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
connect _WIRE_29.valid, UInt<1>(0h0)
wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_30.bits.corrupt, UInt<1>(0h0)
connect _WIRE_30.bits.data, UInt<64>(0h0)
connect _WIRE_30.bits.mask, UInt<8>(0h0)
connect _WIRE_30.bits.address, UInt<13>(0h0)
connect _WIRE_30.bits.source, UInt<10>(0h0)
connect _WIRE_30.bits.size, UInt<3>(0h0)
connect _WIRE_30.bits.param, UInt<2>(0h0)
connect _WIRE_30.bits.opcode, UInt<3>(0h0)
connect _WIRE_30.valid, UInt<1>(0h0)
connect _WIRE_30.ready, UInt<1>(0h0)
wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_31.bits, _WIRE_30.bits
connect _WIRE_31.valid, _WIRE_30.valid
connect _WIRE_31.ready, _WIRE_30.ready
connect _WIRE_31.ready, UInt<1>(0h1)
wire _WIRE_32 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_32.bits.corrupt, UInt<1>(0h0)
connect _WIRE_32.bits.data, UInt<64>(0h0)
connect _WIRE_32.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_32.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_32.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_32.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_32.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_32.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_32.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_32.bits.address, UInt<29>(0h0)
connect _WIRE_32.bits.source, UInt<10>(0h0)
connect _WIRE_32.bits.size, UInt<3>(0h0)
connect _WIRE_32.bits.param, UInt<3>(0h0)
connect _WIRE_32.bits.opcode, UInt<3>(0h0)
connect _WIRE_32.valid, UInt<1>(0h0)
connect _WIRE_32.ready, UInt<1>(0h0)
wire _WIRE_33 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_33.bits, _WIRE_32.bits
connect _WIRE_33.valid, _WIRE_32.valid
connect _WIRE_33.ready, _WIRE_32.ready
invalidate _WIRE_33.bits.corrupt
invalidate _WIRE_33.bits.data
invalidate _WIRE_33.bits.user.amba_prot.fetch
invalidate _WIRE_33.bits.user.amba_prot.secure
invalidate _WIRE_33.bits.user.amba_prot.privileged
invalidate _WIRE_33.bits.user.amba_prot.writealloc
invalidate _WIRE_33.bits.user.amba_prot.readalloc
invalidate _WIRE_33.bits.user.amba_prot.modifiable
invalidate _WIRE_33.bits.user.amba_prot.bufferable
invalidate _WIRE_33.bits.address
invalidate _WIRE_33.bits.source
invalidate _WIRE_33.bits.size
invalidate _WIRE_33.bits.param
invalidate _WIRE_33.bits.opcode
invalidate _WIRE_33.valid
invalidate _WIRE_33.ready
wire _WIRE_34 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_34.bits.corrupt, UInt<1>(0h0)
connect _WIRE_34.bits.data, UInt<64>(0h0)
connect _WIRE_34.bits.address, UInt<13>(0h0)
connect _WIRE_34.bits.source, UInt<10>(0h0)
connect _WIRE_34.bits.size, UInt<3>(0h0)
connect _WIRE_34.bits.param, UInt<3>(0h0)
connect _WIRE_34.bits.opcode, UInt<3>(0h0)
connect _WIRE_34.valid, UInt<1>(0h0)
connect _WIRE_34.ready, UInt<1>(0h0)
wire _WIRE_35 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_35.bits, _WIRE_34.bits
connect _WIRE_35.valid, _WIRE_34.valid
connect _WIRE_35.ready, _WIRE_34.ready
invalidate _WIRE_35.bits.corrupt
invalidate _WIRE_35.bits.data
invalidate _WIRE_35.bits.address
invalidate _WIRE_35.bits.source
invalidate _WIRE_35.bits.size
invalidate _WIRE_35.bits.param
invalidate _WIRE_35.bits.opcode
invalidate _WIRE_35.valid
invalidate _WIRE_35.ready
wire _WIRE_36 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_36.bits.corrupt, UInt<1>(0h0)
connect _WIRE_36.bits.data, UInt<64>(0h0)
connect _WIRE_36.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_36.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_36.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_36.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_36.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_36.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_36.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_36.bits.address, UInt<29>(0h0)
connect _WIRE_36.bits.source, UInt<10>(0h0)
connect _WIRE_36.bits.size, UInt<3>(0h0)
connect _WIRE_36.bits.param, UInt<3>(0h0)
connect _WIRE_36.bits.opcode, UInt<3>(0h0)
connect _WIRE_36.valid, UInt<1>(0h0)
connect _WIRE_36.ready, UInt<1>(0h0)
wire _WIRE_37 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_37.bits, _WIRE_36.bits
connect _WIRE_37.valid, _WIRE_36.valid
connect _WIRE_37.ready, _WIRE_36.ready
connect _WIRE_37.ready, UInt<1>(0h1)
wire _WIRE_38 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_38.bits.corrupt, UInt<1>(0h0)
connect _WIRE_38.bits.data, UInt<64>(0h0)
connect _WIRE_38.bits.address, UInt<13>(0h0)
connect _WIRE_38.bits.source, UInt<10>(0h0)
connect _WIRE_38.bits.size, UInt<3>(0h0)
connect _WIRE_38.bits.param, UInt<3>(0h0)
connect _WIRE_38.bits.opcode, UInt<3>(0h0)
connect _WIRE_38.valid, UInt<1>(0h0)
connect _WIRE_38.ready, UInt<1>(0h0)
wire _WIRE_39 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_39.bits, _WIRE_38.bits
connect _WIRE_39.valid, _WIRE_38.valid
connect _WIRE_39.ready, _WIRE_38.ready
connect _WIRE_39.valid, UInt<1>(0h0)
connect out[0].d.bits.corrupt, anonOut.d.bits.corrupt
connect out[0].d.bits.data, anonOut.d.bits.data
connect out[0].d.bits.denied, anonOut.d.bits.denied
connect out[0].d.bits.sink, anonOut.d.bits.sink
connect out[0].d.bits.source, anonOut.d.bits.source
connect out[0].d.bits.size, anonOut.d.bits.size
connect out[0].d.bits.param, anonOut.d.bits.param
connect out[0].d.bits.opcode, anonOut.d.bits.opcode
connect out[0].d.valid, anonOut.d.valid
connect anonOut.d.ready, out[0].d.ready
node _out_0_d_bits_sink_T = or(anonOut.d.bits.sink, UInt<1>(0h0))
connect out[0].d.bits.sink, _out_0_d_bits_sink_T
wire _WIRE_40 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_40.bits.sink, UInt<1>(0h0)
connect _WIRE_40.valid, UInt<1>(0h0)
connect _WIRE_40.ready, UInt<1>(0h0)
wire _WIRE_41 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_41.bits, _WIRE_40.bits
connect _WIRE_41.valid, _WIRE_40.valid
connect _WIRE_41.ready, _WIRE_40.ready
invalidate _WIRE_41.bits.sink
invalidate _WIRE_41.valid
invalidate _WIRE_41.ready
wire _WIRE_42 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_42.bits.sink, UInt<1>(0h0)
connect _WIRE_42.valid, UInt<1>(0h0)
connect _WIRE_42.ready, UInt<1>(0h0)
wire _WIRE_43 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_43.bits, _WIRE_42.bits
connect _WIRE_43.valid, _WIRE_42.valid
connect _WIRE_43.ready, _WIRE_42.ready
invalidate _WIRE_43.bits.sink
invalidate _WIRE_43.valid
invalidate _WIRE_43.ready
wire _WIRE_44 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_44.bits.sink, UInt<1>(0h0)
connect _WIRE_44.valid, UInt<1>(0h0)
connect _WIRE_44.ready, UInt<1>(0h0)
wire _WIRE_45 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_45.bits, _WIRE_44.bits
connect _WIRE_45.valid, _WIRE_44.valid
connect _WIRE_45.ready, _WIRE_44.ready
connect _WIRE_45.ready, UInt<1>(0h1)
wire _WIRE_46 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_46.bits.sink, UInt<1>(0h0)
connect _WIRE_46.valid, UInt<1>(0h0)
connect _WIRE_46.ready, UInt<1>(0h0)
wire _WIRE_47 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_47.bits, _WIRE_46.bits
connect _WIRE_47.valid, _WIRE_46.valid
connect _WIRE_47.ready, _WIRE_46.ready
connect _WIRE_47.valid, UInt<1>(0h0)
invalidate out[1].a.bits.user.amba_prot.fetch
invalidate out[1].a.bits.user.amba_prot.secure
invalidate out[1].a.bits.user.amba_prot.privileged
invalidate out[1].a.bits.user.amba_prot.writealloc
invalidate out[1].a.bits.user.amba_prot.readalloc
invalidate out[1].a.bits.user.amba_prot.modifiable
invalidate out[1].a.bits.user.amba_prot.bufferable
connect x1_anonOut.a.bits.corrupt, out[1].a.bits.corrupt
connect x1_anonOut.a.bits.data, out[1].a.bits.data
connect x1_anonOut.a.bits.mask, out[1].a.bits.mask
connect x1_anonOut.a.bits.address, out[1].a.bits.address
connect x1_anonOut.a.bits.source, out[1].a.bits.source
connect x1_anonOut.a.bits.size, out[1].a.bits.size
connect x1_anonOut.a.bits.param, out[1].a.bits.param
connect x1_anonOut.a.bits.opcode, out[1].a.bits.opcode
connect x1_anonOut.a.valid, out[1].a.valid
connect out[1].a.ready, x1_anonOut.a.ready
wire _WIRE_48 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_48.bits.corrupt, UInt<1>(0h0)
connect _WIRE_48.bits.data, UInt<64>(0h0)
connect _WIRE_48.bits.mask, UInt<8>(0h0)
connect _WIRE_48.bits.address, UInt<29>(0h0)
connect _WIRE_48.bits.source, UInt<10>(0h0)
connect _WIRE_48.bits.size, UInt<3>(0h0)
connect _WIRE_48.bits.param, UInt<2>(0h0)
connect _WIRE_48.bits.opcode, UInt<3>(0h0)
connect _WIRE_48.valid, UInt<1>(0h0)
connect _WIRE_48.ready, UInt<1>(0h0)
wire _WIRE_49 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_49.bits, _WIRE_48.bits
connect _WIRE_49.valid, _WIRE_48.valid
connect _WIRE_49.ready, _WIRE_48.ready
invalidate _WIRE_49.bits.corrupt
invalidate _WIRE_49.bits.data
invalidate _WIRE_49.bits.mask
invalidate _WIRE_49.bits.address
invalidate _WIRE_49.bits.source
invalidate _WIRE_49.bits.size
invalidate _WIRE_49.bits.param
invalidate _WIRE_49.bits.opcode
invalidate _WIRE_49.valid
invalidate _WIRE_49.ready
wire _WIRE_50 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_50.bits.corrupt, UInt<1>(0h0)
connect _WIRE_50.bits.data, UInt<64>(0h0)
connect _WIRE_50.bits.mask, UInt<8>(0h0)
connect _WIRE_50.bits.address, UInt<29>(0h0)
connect _WIRE_50.bits.source, UInt<10>(0h0)
connect _WIRE_50.bits.size, UInt<3>(0h0)
connect _WIRE_50.bits.param, UInt<2>(0h0)
connect _WIRE_50.bits.opcode, UInt<3>(0h0)
connect _WIRE_50.valid, UInt<1>(0h0)
connect _WIRE_50.ready, UInt<1>(0h0)
wire _WIRE_51 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_51.bits, _WIRE_50.bits
connect _WIRE_51.valid, _WIRE_50.valid
connect _WIRE_51.ready, _WIRE_50.ready
invalidate _WIRE_51.bits.corrupt
invalidate _WIRE_51.bits.data
invalidate _WIRE_51.bits.mask
invalidate _WIRE_51.bits.address
invalidate _WIRE_51.bits.source
invalidate _WIRE_51.bits.size
invalidate _WIRE_51.bits.param
invalidate _WIRE_51.bits.opcode
invalidate _WIRE_51.valid
invalidate _WIRE_51.ready
wire _WIRE_52 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_52.bits.corrupt, UInt<1>(0h0)
connect _WIRE_52.bits.data, UInt<64>(0h0)
connect _WIRE_52.bits.mask, UInt<8>(0h0)
connect _WIRE_52.bits.address, UInt<29>(0h0)
connect _WIRE_52.bits.source, UInt<10>(0h0)
connect _WIRE_52.bits.size, UInt<3>(0h0)
connect _WIRE_52.bits.param, UInt<2>(0h0)
connect _WIRE_52.bits.opcode, UInt<3>(0h0)
connect _WIRE_52.valid, UInt<1>(0h0)
connect _WIRE_52.ready, UInt<1>(0h0)
wire _WIRE_53 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_53.bits, _WIRE_52.bits
connect _WIRE_53.valid, _WIRE_52.valid
connect _WIRE_53.ready, _WIRE_52.ready
connect _WIRE_53.valid, UInt<1>(0h0)
wire _WIRE_54 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_54.bits.corrupt, UInt<1>(0h0)
connect _WIRE_54.bits.data, UInt<64>(0h0)
connect _WIRE_54.bits.mask, UInt<8>(0h0)
connect _WIRE_54.bits.address, UInt<29>(0h0)
connect _WIRE_54.bits.source, UInt<10>(0h0)
connect _WIRE_54.bits.size, UInt<3>(0h0)
connect _WIRE_54.bits.param, UInt<2>(0h0)
connect _WIRE_54.bits.opcode, UInt<3>(0h0)
connect _WIRE_54.valid, UInt<1>(0h0)
connect _WIRE_54.ready, UInt<1>(0h0)
wire _WIRE_55 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_55.bits, _WIRE_54.bits
connect _WIRE_55.valid, _WIRE_54.valid
connect _WIRE_55.ready, _WIRE_54.ready
connect _WIRE_55.ready, UInt<1>(0h1)
wire _WIRE_56 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_56.bits.corrupt, UInt<1>(0h0)
connect _WIRE_56.bits.data, UInt<64>(0h0)
connect _WIRE_56.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_56.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_56.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_56.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_56.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_56.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_56.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_56.bits.address, UInt<29>(0h0)
connect _WIRE_56.bits.source, UInt<10>(0h0)
connect _WIRE_56.bits.size, UInt<3>(0h0)
connect _WIRE_56.bits.param, UInt<3>(0h0)
connect _WIRE_56.bits.opcode, UInt<3>(0h0)
connect _WIRE_56.valid, UInt<1>(0h0)
connect _WIRE_56.ready, UInt<1>(0h0)
wire _WIRE_57 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_57.bits, _WIRE_56.bits
connect _WIRE_57.valid, _WIRE_56.valid
connect _WIRE_57.ready, _WIRE_56.ready
invalidate _WIRE_57.bits.corrupt
invalidate _WIRE_57.bits.data
invalidate _WIRE_57.bits.user.amba_prot.fetch
invalidate _WIRE_57.bits.user.amba_prot.secure
invalidate _WIRE_57.bits.user.amba_prot.privileged
invalidate _WIRE_57.bits.user.amba_prot.writealloc
invalidate _WIRE_57.bits.user.amba_prot.readalloc
invalidate _WIRE_57.bits.user.amba_prot.modifiable
invalidate _WIRE_57.bits.user.amba_prot.bufferable
invalidate _WIRE_57.bits.address
invalidate _WIRE_57.bits.source
invalidate _WIRE_57.bits.size
invalidate _WIRE_57.bits.param
invalidate _WIRE_57.bits.opcode
invalidate _WIRE_57.valid
invalidate _WIRE_57.ready
wire _WIRE_58 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_58.bits.corrupt, UInt<1>(0h0)
connect _WIRE_58.bits.data, UInt<64>(0h0)
connect _WIRE_58.bits.address, UInt<29>(0h0)
connect _WIRE_58.bits.source, UInt<10>(0h0)
connect _WIRE_58.bits.size, UInt<3>(0h0)
connect _WIRE_58.bits.param, UInt<3>(0h0)
connect _WIRE_58.bits.opcode, UInt<3>(0h0)
connect _WIRE_58.valid, UInt<1>(0h0)
connect _WIRE_58.ready, UInt<1>(0h0)
wire _WIRE_59 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_59.bits, _WIRE_58.bits
connect _WIRE_59.valid, _WIRE_58.valid
connect _WIRE_59.ready, _WIRE_58.ready
invalidate _WIRE_59.bits.corrupt
invalidate _WIRE_59.bits.data
invalidate _WIRE_59.bits.address
invalidate _WIRE_59.bits.source
invalidate _WIRE_59.bits.size
invalidate _WIRE_59.bits.param
invalidate _WIRE_59.bits.opcode
invalidate _WIRE_59.valid
invalidate _WIRE_59.ready
wire _WIRE_60 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_60.bits.corrupt, UInt<1>(0h0)
connect _WIRE_60.bits.data, UInt<64>(0h0)
connect _WIRE_60.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_60.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_60.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_60.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_60.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_60.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_60.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_60.bits.address, UInt<29>(0h0)
connect _WIRE_60.bits.source, UInt<10>(0h0)
connect _WIRE_60.bits.size, UInt<3>(0h0)
connect _WIRE_60.bits.param, UInt<3>(0h0)
connect _WIRE_60.bits.opcode, UInt<3>(0h0)
connect _WIRE_60.valid, UInt<1>(0h0)
connect _WIRE_60.ready, UInt<1>(0h0)
wire _WIRE_61 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_61.bits, _WIRE_60.bits
connect _WIRE_61.valid, _WIRE_60.valid
connect _WIRE_61.ready, _WIRE_60.ready
connect _WIRE_61.ready, UInt<1>(0h1)
wire _WIRE_62 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_62.bits.corrupt, UInt<1>(0h0)
connect _WIRE_62.bits.data, UInt<64>(0h0)
connect _WIRE_62.bits.address, UInt<29>(0h0)
connect _WIRE_62.bits.source, UInt<10>(0h0)
connect _WIRE_62.bits.size, UInt<3>(0h0)
connect _WIRE_62.bits.param, UInt<3>(0h0)
connect _WIRE_62.bits.opcode, UInt<3>(0h0)
connect _WIRE_62.valid, UInt<1>(0h0)
connect _WIRE_62.ready, UInt<1>(0h0)
wire _WIRE_63 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_63.bits, _WIRE_62.bits
connect _WIRE_63.valid, _WIRE_62.valid
connect _WIRE_63.ready, _WIRE_62.ready
connect _WIRE_63.valid, UInt<1>(0h0)
connect out[1].d.bits.corrupt, x1_anonOut.d.bits.corrupt
connect out[1].d.bits.data, x1_anonOut.d.bits.data
connect out[1].d.bits.denied, x1_anonOut.d.bits.denied
connect out[1].d.bits.sink, x1_anonOut.d.bits.sink
connect out[1].d.bits.source, x1_anonOut.d.bits.source
connect out[1].d.bits.size, x1_anonOut.d.bits.size
connect out[1].d.bits.param, x1_anonOut.d.bits.param
connect out[1].d.bits.opcode, x1_anonOut.d.bits.opcode
connect out[1].d.valid, x1_anonOut.d.valid
connect x1_anonOut.d.ready, out[1].d.ready
node _out_1_d_bits_sink_T = or(x1_anonOut.d.bits.sink, UInt<1>(0h0))
connect out[1].d.bits.sink, _out_1_d_bits_sink_T
wire _WIRE_64 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_64.bits.sink, UInt<1>(0h0)
connect _WIRE_64.valid, UInt<1>(0h0)
connect _WIRE_64.ready, UInt<1>(0h0)
wire _WIRE_65 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_65.bits, _WIRE_64.bits
connect _WIRE_65.valid, _WIRE_64.valid
connect _WIRE_65.ready, _WIRE_64.ready
invalidate _WIRE_65.bits.sink
invalidate _WIRE_65.valid
invalidate _WIRE_65.ready
wire _WIRE_66 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_66.bits.sink, UInt<1>(0h0)
connect _WIRE_66.valid, UInt<1>(0h0)
connect _WIRE_66.ready, UInt<1>(0h0)
wire _WIRE_67 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_67.bits, _WIRE_66.bits
connect _WIRE_67.valid, _WIRE_66.valid
connect _WIRE_67.ready, _WIRE_66.ready
invalidate _WIRE_67.bits.sink
invalidate _WIRE_67.valid
invalidate _WIRE_67.ready
wire _WIRE_68 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_68.bits.sink, UInt<1>(0h0)
connect _WIRE_68.valid, UInt<1>(0h0)
connect _WIRE_68.ready, UInt<1>(0h0)
wire _WIRE_69 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_69.bits, _WIRE_68.bits
connect _WIRE_69.valid, _WIRE_68.valid
connect _WIRE_69.ready, _WIRE_68.ready
connect _WIRE_69.ready, UInt<1>(0h1)
wire _WIRE_70 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_70.bits.sink, UInt<1>(0h0)
connect _WIRE_70.valid, UInt<1>(0h0)
connect _WIRE_70.ready, UInt<1>(0h0)
wire _WIRE_71 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_71.bits, _WIRE_70.bits
connect _WIRE_71.valid, _WIRE_70.valid
connect _WIRE_71.ready, _WIRE_70.ready
connect _WIRE_71.valid, UInt<1>(0h0)
invalidate out[2].a.bits.user.amba_prot.fetch
invalidate out[2].a.bits.user.amba_prot.secure
invalidate out[2].a.bits.user.amba_prot.privileged
invalidate out[2].a.bits.user.amba_prot.writealloc
invalidate out[2].a.bits.user.amba_prot.readalloc
invalidate out[2].a.bits.user.amba_prot.modifiable
invalidate out[2].a.bits.user.amba_prot.bufferable
connect x1_anonOut_1.a.bits.corrupt, out[2].a.bits.corrupt
connect x1_anonOut_1.a.bits.data, out[2].a.bits.data
connect x1_anonOut_1.a.bits.mask, out[2].a.bits.mask
connect x1_anonOut_1.a.bits.user.amba_prot.fetch, out[2].a.bits.user.amba_prot.fetch
connect x1_anonOut_1.a.bits.user.amba_prot.secure, out[2].a.bits.user.amba_prot.secure
connect x1_anonOut_1.a.bits.user.amba_prot.privileged, out[2].a.bits.user.amba_prot.privileged
connect x1_anonOut_1.a.bits.user.amba_prot.writealloc, out[2].a.bits.user.amba_prot.writealloc
connect x1_anonOut_1.a.bits.user.amba_prot.readalloc, out[2].a.bits.user.amba_prot.readalloc
connect x1_anonOut_1.a.bits.user.amba_prot.modifiable, out[2].a.bits.user.amba_prot.modifiable
connect x1_anonOut_1.a.bits.user.amba_prot.bufferable, out[2].a.bits.user.amba_prot.bufferable
connect x1_anonOut_1.a.bits.address, out[2].a.bits.address
connect x1_anonOut_1.a.bits.source, out[2].a.bits.source
connect x1_anonOut_1.a.bits.size, out[2].a.bits.size
connect x1_anonOut_1.a.bits.param, out[2].a.bits.param
connect x1_anonOut_1.a.bits.opcode, out[2].a.bits.opcode
connect x1_anonOut_1.a.valid, out[2].a.valid
connect out[2].a.ready, x1_anonOut_1.a.ready
wire _WIRE_72 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_72.bits.corrupt, UInt<1>(0h0)
connect _WIRE_72.bits.data, UInt<64>(0h0)
connect _WIRE_72.bits.mask, UInt<8>(0h0)
connect _WIRE_72.bits.address, UInt<29>(0h0)
connect _WIRE_72.bits.source, UInt<10>(0h0)
connect _WIRE_72.bits.size, UInt<3>(0h0)
connect _WIRE_72.bits.param, UInt<2>(0h0)
connect _WIRE_72.bits.opcode, UInt<3>(0h0)
connect _WIRE_72.valid, UInt<1>(0h0)
connect _WIRE_72.ready, UInt<1>(0h0)
wire _WIRE_73 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_73.bits, _WIRE_72.bits
connect _WIRE_73.valid, _WIRE_72.valid
connect _WIRE_73.ready, _WIRE_72.ready
invalidate _WIRE_73.bits.corrupt
invalidate _WIRE_73.bits.data
invalidate _WIRE_73.bits.mask
invalidate _WIRE_73.bits.address
invalidate _WIRE_73.bits.source
invalidate _WIRE_73.bits.size
invalidate _WIRE_73.bits.param
invalidate _WIRE_73.bits.opcode
invalidate _WIRE_73.valid
invalidate _WIRE_73.ready
wire _WIRE_74 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_74.bits.corrupt, UInt<1>(0h0)
connect _WIRE_74.bits.data, UInt<64>(0h0)
connect _WIRE_74.bits.mask, UInt<8>(0h0)
connect _WIRE_74.bits.address, UInt<29>(0h0)
connect _WIRE_74.bits.source, UInt<10>(0h0)
connect _WIRE_74.bits.size, UInt<3>(0h0)
connect _WIRE_74.bits.param, UInt<2>(0h0)
connect _WIRE_74.bits.opcode, UInt<3>(0h0)
connect _WIRE_74.valid, UInt<1>(0h0)
connect _WIRE_74.ready, UInt<1>(0h0)
wire _WIRE_75 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_75.bits, _WIRE_74.bits
connect _WIRE_75.valid, _WIRE_74.valid
connect _WIRE_75.ready, _WIRE_74.ready
invalidate _WIRE_75.bits.corrupt
invalidate _WIRE_75.bits.data
invalidate _WIRE_75.bits.mask
invalidate _WIRE_75.bits.address
invalidate _WIRE_75.bits.source
invalidate _WIRE_75.bits.size
invalidate _WIRE_75.bits.param
invalidate _WIRE_75.bits.opcode
invalidate _WIRE_75.valid
invalidate _WIRE_75.ready
wire _WIRE_76 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_76.bits.corrupt, UInt<1>(0h0)
connect _WIRE_76.bits.data, UInt<64>(0h0)
connect _WIRE_76.bits.mask, UInt<8>(0h0)
connect _WIRE_76.bits.address, UInt<29>(0h0)
connect _WIRE_76.bits.source, UInt<10>(0h0)
connect _WIRE_76.bits.size, UInt<3>(0h0)
connect _WIRE_76.bits.param, UInt<2>(0h0)
connect _WIRE_76.bits.opcode, UInt<3>(0h0)
connect _WIRE_76.valid, UInt<1>(0h0)
connect _WIRE_76.ready, UInt<1>(0h0)
wire _WIRE_77 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_77.bits, _WIRE_76.bits
connect _WIRE_77.valid, _WIRE_76.valid
connect _WIRE_77.ready, _WIRE_76.ready
connect _WIRE_77.valid, UInt<1>(0h0)
wire _WIRE_78 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_78.bits.corrupt, UInt<1>(0h0)
connect _WIRE_78.bits.data, UInt<64>(0h0)
connect _WIRE_78.bits.mask, UInt<8>(0h0)
connect _WIRE_78.bits.address, UInt<29>(0h0)
connect _WIRE_78.bits.source, UInt<10>(0h0)
connect _WIRE_78.bits.size, UInt<3>(0h0)
connect _WIRE_78.bits.param, UInt<2>(0h0)
connect _WIRE_78.bits.opcode, UInt<3>(0h0)
connect _WIRE_78.valid, UInt<1>(0h0)
connect _WIRE_78.ready, UInt<1>(0h0)
wire _WIRE_79 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_79.bits, _WIRE_78.bits
connect _WIRE_79.valid, _WIRE_78.valid
connect _WIRE_79.ready, _WIRE_78.ready
connect _WIRE_79.ready, UInt<1>(0h1)
wire _WIRE_80 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_80.bits.corrupt, UInt<1>(0h0)
connect _WIRE_80.bits.data, UInt<64>(0h0)
connect _WIRE_80.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_80.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_80.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_80.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_80.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_80.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_80.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_80.bits.address, UInt<29>(0h0)
connect _WIRE_80.bits.source, UInt<10>(0h0)
connect _WIRE_80.bits.size, UInt<3>(0h0)
connect _WIRE_80.bits.param, UInt<3>(0h0)
connect _WIRE_80.bits.opcode, UInt<3>(0h0)
connect _WIRE_80.valid, UInt<1>(0h0)
connect _WIRE_80.ready, UInt<1>(0h0)
wire _WIRE_81 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_81.bits, _WIRE_80.bits
connect _WIRE_81.valid, _WIRE_80.valid
connect _WIRE_81.ready, _WIRE_80.ready
invalidate _WIRE_81.bits.corrupt
invalidate _WIRE_81.bits.data
invalidate _WIRE_81.bits.user.amba_prot.fetch
invalidate _WIRE_81.bits.user.amba_prot.secure
invalidate _WIRE_81.bits.user.amba_prot.privileged
invalidate _WIRE_81.bits.user.amba_prot.writealloc
invalidate _WIRE_81.bits.user.amba_prot.readalloc
invalidate _WIRE_81.bits.user.amba_prot.modifiable
invalidate _WIRE_81.bits.user.amba_prot.bufferable
invalidate _WIRE_81.bits.address
invalidate _WIRE_81.bits.source
invalidate _WIRE_81.bits.size
invalidate _WIRE_81.bits.param
invalidate _WIRE_81.bits.opcode
invalidate _WIRE_81.valid
invalidate _WIRE_81.ready
wire _WIRE_82 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_82.bits.corrupt, UInt<1>(0h0)
connect _WIRE_82.bits.data, UInt<64>(0h0)
connect _WIRE_82.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_82.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_82.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_82.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_82.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_82.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_82.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_82.bits.address, UInt<29>(0h0)
connect _WIRE_82.bits.source, UInt<10>(0h0)
connect _WIRE_82.bits.size, UInt<3>(0h0)
connect _WIRE_82.bits.param, UInt<3>(0h0)
connect _WIRE_82.bits.opcode, UInt<3>(0h0)
connect _WIRE_82.valid, UInt<1>(0h0)
connect _WIRE_82.ready, UInt<1>(0h0)
wire _WIRE_83 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_83.bits, _WIRE_82.bits
connect _WIRE_83.valid, _WIRE_82.valid
connect _WIRE_83.ready, _WIRE_82.ready
invalidate _WIRE_83.bits.corrupt
invalidate _WIRE_83.bits.data
invalidate _WIRE_83.bits.user.amba_prot.fetch
invalidate _WIRE_83.bits.user.amba_prot.secure
invalidate _WIRE_83.bits.user.amba_prot.privileged
invalidate _WIRE_83.bits.user.amba_prot.writealloc
invalidate _WIRE_83.bits.user.amba_prot.readalloc
invalidate _WIRE_83.bits.user.amba_prot.modifiable
invalidate _WIRE_83.bits.user.amba_prot.bufferable
invalidate _WIRE_83.bits.address
invalidate _WIRE_83.bits.source
invalidate _WIRE_83.bits.size
invalidate _WIRE_83.bits.param
invalidate _WIRE_83.bits.opcode
invalidate _WIRE_83.valid
invalidate _WIRE_83.ready
wire _WIRE_84 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_84.bits.corrupt, UInt<1>(0h0)
connect _WIRE_84.bits.data, UInt<64>(0h0)
connect _WIRE_84.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_84.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_84.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_84.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_84.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_84.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_84.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_84.bits.address, UInt<29>(0h0)
connect _WIRE_84.bits.source, UInt<10>(0h0)
connect _WIRE_84.bits.size, UInt<3>(0h0)
connect _WIRE_84.bits.param, UInt<3>(0h0)
connect _WIRE_84.bits.opcode, UInt<3>(0h0)
connect _WIRE_84.valid, UInt<1>(0h0)
connect _WIRE_84.ready, UInt<1>(0h0)
wire _WIRE_85 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_85.bits, _WIRE_84.bits
connect _WIRE_85.valid, _WIRE_84.valid
connect _WIRE_85.ready, _WIRE_84.ready
connect _WIRE_85.ready, UInt<1>(0h1)
wire _WIRE_86 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_86.bits.corrupt, UInt<1>(0h0)
connect _WIRE_86.bits.data, UInt<64>(0h0)
connect _WIRE_86.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_86.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_86.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_86.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_86.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_86.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_86.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_86.bits.address, UInt<29>(0h0)
connect _WIRE_86.bits.source, UInt<10>(0h0)
connect _WIRE_86.bits.size, UInt<3>(0h0)
connect _WIRE_86.bits.param, UInt<3>(0h0)
connect _WIRE_86.bits.opcode, UInt<3>(0h0)
connect _WIRE_86.valid, UInt<1>(0h0)
connect _WIRE_86.ready, UInt<1>(0h0)
wire _WIRE_87 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_87.bits, _WIRE_86.bits
connect _WIRE_87.valid, _WIRE_86.valid
connect _WIRE_87.ready, _WIRE_86.ready
connect _WIRE_87.valid, UInt<1>(0h0)
connect out[2].d.bits.corrupt, x1_anonOut_1.d.bits.corrupt
connect out[2].d.bits.data, x1_anonOut_1.d.bits.data
connect out[2].d.bits.denied, x1_anonOut_1.d.bits.denied
connect out[2].d.bits.sink, x1_anonOut_1.d.bits.sink
connect out[2].d.bits.source, x1_anonOut_1.d.bits.source
connect out[2].d.bits.size, x1_anonOut_1.d.bits.size
connect out[2].d.bits.param, x1_anonOut_1.d.bits.param
connect out[2].d.bits.opcode, x1_anonOut_1.d.bits.opcode
connect out[2].d.valid, x1_anonOut_1.d.valid
connect x1_anonOut_1.d.ready, out[2].d.ready
node _out_2_d_bits_sink_T = or(x1_anonOut_1.d.bits.sink, UInt<1>(0h0))
connect out[2].d.bits.sink, _out_2_d_bits_sink_T
wire _WIRE_88 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_88.bits.sink, UInt<1>(0h0)
connect _WIRE_88.valid, UInt<1>(0h0)
connect _WIRE_88.ready, UInt<1>(0h0)
wire _WIRE_89 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_89.bits, _WIRE_88.bits
connect _WIRE_89.valid, _WIRE_88.valid
connect _WIRE_89.ready, _WIRE_88.ready
invalidate _WIRE_89.bits.sink
invalidate _WIRE_89.valid
invalidate _WIRE_89.ready
wire _WIRE_90 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_90.bits.sink, UInt<1>(0h0)
connect _WIRE_90.valid, UInt<1>(0h0)
connect _WIRE_90.ready, UInt<1>(0h0)
wire _WIRE_91 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_91.bits, _WIRE_90.bits
connect _WIRE_91.valid, _WIRE_90.valid
connect _WIRE_91.ready, _WIRE_90.ready
invalidate _WIRE_91.bits.sink
invalidate _WIRE_91.valid
invalidate _WIRE_91.ready
wire _WIRE_92 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_92.bits.sink, UInt<1>(0h0)
connect _WIRE_92.valid, UInt<1>(0h0)
connect _WIRE_92.ready, UInt<1>(0h0)
wire _WIRE_93 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_93.bits, _WIRE_92.bits
connect _WIRE_93.valid, _WIRE_92.valid
connect _WIRE_93.ready, _WIRE_92.ready
connect _WIRE_93.ready, UInt<1>(0h1)
wire _WIRE_94 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_94.bits.sink, UInt<1>(0h0)
connect _WIRE_94.valid, UInt<1>(0h0)
connect _WIRE_94.ready, UInt<1>(0h0)
wire _WIRE_95 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_95.bits, _WIRE_94.bits
connect _WIRE_95.valid, _WIRE_94.valid
connect _WIRE_95.ready, _WIRE_94.ready
connect _WIRE_95.valid, UInt<1>(0h0)
wire _addressC_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _addressC_WIRE.bits.corrupt, UInt<1>(0h0)
connect _addressC_WIRE.bits.data, UInt<64>(0h0)
connect _addressC_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _addressC_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _addressC_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _addressC_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _addressC_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _addressC_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _addressC_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _addressC_WIRE.bits.address, UInt<29>(0h0)
connect _addressC_WIRE.bits.source, UInt<10>(0h0)
connect _addressC_WIRE.bits.size, UInt<3>(0h0)
connect _addressC_WIRE.bits.param, UInt<3>(0h0)
connect _addressC_WIRE.bits.opcode, UInt<3>(0h0)
connect _addressC_WIRE.valid, UInt<1>(0h0)
connect _addressC_WIRE.ready, UInt<1>(0h0)
wire _addressC_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _addressC_WIRE_1.bits, _addressC_WIRE.bits
connect _addressC_WIRE_1.valid, _addressC_WIRE.valid
connect _addressC_WIRE_1.ready, _addressC_WIRE.ready
node _requestAIO_T = xor(in[0].a.bits.address, UInt<1>(0h0))
node _requestAIO_T_1 = cvt(_requestAIO_T)
node _requestAIO_T_2 = and(_requestAIO_T_1, asSInt(UInt<30>(0h10040000)))
node _requestAIO_T_3 = asSInt(_requestAIO_T_2)
node _requestAIO_T_4 = eq(_requestAIO_T_3, asSInt(UInt<1>(0h0)))
node requestAIO_0_0 = or(UInt<1>(0h0), _requestAIO_T_4)
node _requestAIO_T_5 = xor(in[0].a.bits.address, UInt<29>(0h10000000))
node _requestAIO_T_6 = cvt(_requestAIO_T_5)
node _requestAIO_T_7 = and(_requestAIO_T_6, asSInt(UInt<30>(0h10040000)))
node _requestAIO_T_8 = asSInt(_requestAIO_T_7)
node _requestAIO_T_9 = eq(_requestAIO_T_8, asSInt(UInt<1>(0h0)))
node requestAIO_0_1 = or(UInt<1>(0h0), _requestAIO_T_9)
node _requestAIO_T_10 = xor(in[0].a.bits.address, UInt<29>(0h10040000))
node _requestAIO_T_11 = cvt(_requestAIO_T_10)
node _requestAIO_T_12 = and(_requestAIO_T_11, asSInt(UInt<30>(0h10040000)))
node _requestAIO_T_13 = asSInt(_requestAIO_T_12)
node _requestAIO_T_14 = eq(_requestAIO_T_13, asSInt(UInt<1>(0h0)))
node requestAIO_0_2 = or(UInt<1>(0h0), _requestAIO_T_14)
node _requestCIO_T = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0))
node _requestCIO_T_1 = cvt(_requestCIO_T)
node _requestCIO_T_2 = and(_requestCIO_T_1, asSInt(UInt<1>(0h0)))
node _requestCIO_T_3 = asSInt(_requestCIO_T_2)
node _requestCIO_T_4 = eq(_requestCIO_T_3, asSInt(UInt<1>(0h0)))
node requestCIO_0_0 = or(UInt<1>(0h1), _requestCIO_T_4)
node _requestCIO_T_5 = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0))
node _requestCIO_T_6 = cvt(_requestCIO_T_5)
node _requestCIO_T_7 = and(_requestCIO_T_6, asSInt(UInt<1>(0h0)))
node _requestCIO_T_8 = asSInt(_requestCIO_T_7)
node _requestCIO_T_9 = eq(_requestCIO_T_8, asSInt(UInt<1>(0h0)))
node requestCIO_0_1 = or(UInt<1>(0h1), _requestCIO_T_9)
node _requestCIO_T_10 = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0))
node _requestCIO_T_11 = cvt(_requestCIO_T_10)
node _requestCIO_T_12 = and(_requestCIO_T_11, asSInt(UInt<1>(0h0)))
node _requestCIO_T_13 = asSInt(_requestCIO_T_12)
node _requestCIO_T_14 = eq(_requestCIO_T_13, asSInt(UInt<1>(0h0)))
node requestCIO_0_2 = or(UInt<1>(0h1), _requestCIO_T_14)
wire _requestBOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE.bits.corrupt, UInt<1>(0h0)
connect _requestBOI_WIRE.bits.data, UInt<64>(0h0)
connect _requestBOI_WIRE.bits.mask, UInt<8>(0h0)
connect _requestBOI_WIRE.bits.address, UInt<29>(0h0)
connect _requestBOI_WIRE.bits.source, UInt<10>(0h0)
connect _requestBOI_WIRE.bits.size, UInt<3>(0h0)
connect _requestBOI_WIRE.bits.param, UInt<2>(0h0)
connect _requestBOI_WIRE.bits.opcode, UInt<3>(0h0)
connect _requestBOI_WIRE.valid, UInt<1>(0h0)
connect _requestBOI_WIRE.ready, UInt<1>(0h0)
wire _requestBOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_1.bits, _requestBOI_WIRE.bits
connect _requestBOI_WIRE_1.valid, _requestBOI_WIRE.valid
connect _requestBOI_WIRE_1.ready, _requestBOI_WIRE.ready
node _requestBOI_uncommonBits_T = or(_requestBOI_WIRE_1.bits.source, UInt<10>(0h0))
node requestBOI_uncommonBits = bits(_requestBOI_uncommonBits_T, 9, 0)
node _requestBOI_T = shr(_requestBOI_WIRE_1.bits.source, 10)
node _requestBOI_T_1 = eq(_requestBOI_T, UInt<1>(0h0))
node _requestBOI_T_2 = leq(UInt<1>(0h0), requestBOI_uncommonBits)
node _requestBOI_T_3 = and(_requestBOI_T_1, _requestBOI_T_2)
node _requestBOI_T_4 = leq(requestBOI_uncommonBits, UInt<10>(0h3ff))
node requestBOI_0_0 = and(_requestBOI_T_3, _requestBOI_T_4)
wire _requestBOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _requestBOI_WIRE_2.bits.data, UInt<64>(0h0)
connect _requestBOI_WIRE_2.bits.mask, UInt<8>(0h0)
connect _requestBOI_WIRE_2.bits.address, UInt<29>(0h0)
connect _requestBOI_WIRE_2.bits.source, UInt<10>(0h0)
connect _requestBOI_WIRE_2.bits.size, UInt<3>(0h0)
connect _requestBOI_WIRE_2.bits.param, UInt<2>(0h0)
connect _requestBOI_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _requestBOI_WIRE_2.valid, UInt<1>(0h0)
connect _requestBOI_WIRE_2.ready, UInt<1>(0h0)
wire _requestBOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_3.bits, _requestBOI_WIRE_2.bits
connect _requestBOI_WIRE_3.valid, _requestBOI_WIRE_2.valid
connect _requestBOI_WIRE_3.ready, _requestBOI_WIRE_2.ready
node _requestBOI_uncommonBits_T_1 = or(_requestBOI_WIRE_3.bits.source, UInt<10>(0h0))
node requestBOI_uncommonBits_1 = bits(_requestBOI_uncommonBits_T_1, 9, 0)
node _requestBOI_T_5 = shr(_requestBOI_WIRE_3.bits.source, 10)
node _requestBOI_T_6 = eq(_requestBOI_T_5, UInt<1>(0h0))
node _requestBOI_T_7 = leq(UInt<1>(0h0), requestBOI_uncommonBits_1)
node _requestBOI_T_8 = and(_requestBOI_T_6, _requestBOI_T_7)
node _requestBOI_T_9 = leq(requestBOI_uncommonBits_1, UInt<10>(0h3ff))
node requestBOI_1_0 = and(_requestBOI_T_8, _requestBOI_T_9)
wire _requestBOI_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _requestBOI_WIRE_4.bits.data, UInt<64>(0h0)
connect _requestBOI_WIRE_4.bits.mask, UInt<8>(0h0)
connect _requestBOI_WIRE_4.bits.address, UInt<29>(0h0)
connect _requestBOI_WIRE_4.bits.source, UInt<10>(0h0)
connect _requestBOI_WIRE_4.bits.size, UInt<3>(0h0)
connect _requestBOI_WIRE_4.bits.param, UInt<2>(0h0)
connect _requestBOI_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _requestBOI_WIRE_4.valid, UInt<1>(0h0)
connect _requestBOI_WIRE_4.ready, UInt<1>(0h0)
wire _requestBOI_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_5.bits, _requestBOI_WIRE_4.bits
connect _requestBOI_WIRE_5.valid, _requestBOI_WIRE_4.valid
connect _requestBOI_WIRE_5.ready, _requestBOI_WIRE_4.ready
node _requestBOI_uncommonBits_T_2 = or(_requestBOI_WIRE_5.bits.source, UInt<10>(0h0))
node requestBOI_uncommonBits_2 = bits(_requestBOI_uncommonBits_T_2, 9, 0)
node _requestBOI_T_10 = shr(_requestBOI_WIRE_5.bits.source, 10)
node _requestBOI_T_11 = eq(_requestBOI_T_10, UInt<1>(0h0))
node _requestBOI_T_12 = leq(UInt<1>(0h0), requestBOI_uncommonBits_2)
node _requestBOI_T_13 = and(_requestBOI_T_11, _requestBOI_T_12)
node _requestBOI_T_14 = leq(requestBOI_uncommonBits_2, UInt<10>(0h3ff))
node requestBOI_2_0 = and(_requestBOI_T_13, _requestBOI_T_14)
node _requestDOI_uncommonBits_T = or(out[0].d.bits.source, UInt<10>(0h0))
node requestDOI_uncommonBits = bits(_requestDOI_uncommonBits_T, 9, 0)
node _requestDOI_T = shr(out[0].d.bits.source, 10)
node _requestDOI_T_1 = eq(_requestDOI_T, UInt<1>(0h0))
node _requestDOI_T_2 = leq(UInt<1>(0h0), requestDOI_uncommonBits)
node _requestDOI_T_3 = and(_requestDOI_T_1, _requestDOI_T_2)
node _requestDOI_T_4 = leq(requestDOI_uncommonBits, UInt<10>(0h3ff))
node requestDOI_0_0 = and(_requestDOI_T_3, _requestDOI_T_4)
node _requestDOI_uncommonBits_T_1 = or(out[1].d.bits.source, UInt<10>(0h0))
node requestDOI_uncommonBits_1 = bits(_requestDOI_uncommonBits_T_1, 9, 0)
node _requestDOI_T_5 = shr(out[1].d.bits.source, 10)
node _requestDOI_T_6 = eq(_requestDOI_T_5, UInt<1>(0h0))
node _requestDOI_T_7 = leq(UInt<1>(0h0), requestDOI_uncommonBits_1)
node _requestDOI_T_8 = and(_requestDOI_T_6, _requestDOI_T_7)
node _requestDOI_T_9 = leq(requestDOI_uncommonBits_1, UInt<10>(0h3ff))
node requestDOI_1_0 = and(_requestDOI_T_8, _requestDOI_T_9)
node _requestDOI_uncommonBits_T_2 = or(out[2].d.bits.source, UInt<10>(0h0))
node requestDOI_uncommonBits_2 = bits(_requestDOI_uncommonBits_T_2, 9, 0)
node _requestDOI_T_10 = shr(out[2].d.bits.source, 10)
node _requestDOI_T_11 = eq(_requestDOI_T_10, UInt<1>(0h0))
node _requestDOI_T_12 = leq(UInt<1>(0h0), requestDOI_uncommonBits_2)
node _requestDOI_T_13 = and(_requestDOI_T_11, _requestDOI_T_12)
node _requestDOI_T_14 = leq(requestDOI_uncommonBits_2, UInt<10>(0h3ff))
node requestDOI_2_0 = and(_requestDOI_T_13, _requestDOI_T_14)
wire _requestEIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE.bits.sink, UInt<1>(0h0)
connect _requestEIO_WIRE.valid, UInt<1>(0h0)
connect _requestEIO_WIRE.ready, UInt<1>(0h0)
wire _requestEIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_1.bits, _requestEIO_WIRE.bits
connect _requestEIO_WIRE_1.valid, _requestEIO_WIRE.valid
connect _requestEIO_WIRE_1.ready, _requestEIO_WIRE.ready
wire _requestEIO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_2.bits.sink, UInt<1>(0h0)
connect _requestEIO_WIRE_2.valid, UInt<1>(0h0)
connect _requestEIO_WIRE_2.ready, UInt<1>(0h0)
wire _requestEIO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_3.bits, _requestEIO_WIRE_2.bits
connect _requestEIO_WIRE_3.valid, _requestEIO_WIRE_2.valid
connect _requestEIO_WIRE_3.ready, _requestEIO_WIRE_2.ready
wire _requestEIO_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_4.bits.sink, UInt<1>(0h0)
connect _requestEIO_WIRE_4.valid, UInt<1>(0h0)
connect _requestEIO_WIRE_4.ready, UInt<1>(0h0)
wire _requestEIO_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_5.bits, _requestEIO_WIRE_4.bits
connect _requestEIO_WIRE_5.valid, _requestEIO_WIRE_4.valid
connect _requestEIO_WIRE_5.ready, _requestEIO_WIRE_4.ready
node _beatsAI_decode_T = dshl(UInt<6>(0h3f), in[0].a.bits.size)
node _beatsAI_decode_T_1 = bits(_beatsAI_decode_T, 5, 0)
node _beatsAI_decode_T_2 = not(_beatsAI_decode_T_1)
node beatsAI_decode = shr(_beatsAI_decode_T_2, 3)
node _beatsAI_opdata_T = bits(in[0].a.bits.opcode, 2, 2)
node beatsAI_opdata = eq(_beatsAI_opdata_T, UInt<1>(0h0))
node beatsAI_0 = mux(beatsAI_opdata, beatsAI_decode, UInt<1>(0h0))
wire _beatsBO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsBO_WIRE.bits.corrupt, UInt<1>(0h0)
connect _beatsBO_WIRE.bits.data, UInt<64>(0h0)
connect _beatsBO_WIRE.bits.mask, UInt<8>(0h0)
connect _beatsBO_WIRE.bits.address, UInt<29>(0h0)
connect _beatsBO_WIRE.bits.source, UInt<10>(0h0)
connect _beatsBO_WIRE.bits.size, UInt<3>(0h0)
connect _beatsBO_WIRE.bits.param, UInt<2>(0h0)
connect _beatsBO_WIRE.bits.opcode, UInt<3>(0h0)
connect _beatsBO_WIRE.valid, UInt<1>(0h0)
connect _beatsBO_WIRE.ready, UInt<1>(0h0)
wire _beatsBO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsBO_WIRE_1.bits, _beatsBO_WIRE.bits
connect _beatsBO_WIRE_1.valid, _beatsBO_WIRE.valid
connect _beatsBO_WIRE_1.ready, _beatsBO_WIRE.ready
node _beatsBO_decode_T = dshl(UInt<6>(0h3f), _beatsBO_WIRE_1.bits.size)
node _beatsBO_decode_T_1 = bits(_beatsBO_decode_T, 5, 0)
node _beatsBO_decode_T_2 = not(_beatsBO_decode_T_1)
node beatsBO_decode = shr(_beatsBO_decode_T_2, 3)
node _beatsBO_opdata_T = bits(_beatsBO_WIRE_1.bits.opcode, 2, 2)
node beatsBO_opdata = eq(_beatsBO_opdata_T, UInt<1>(0h0))
node beatsBO_0 = mux(UInt<1>(0h0), beatsBO_decode, UInt<1>(0h0))
wire _beatsBO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsBO_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _beatsBO_WIRE_2.bits.data, UInt<64>(0h0)
connect _beatsBO_WIRE_2.bits.mask, UInt<8>(0h0)
connect _beatsBO_WIRE_2.bits.address, UInt<29>(0h0)
connect _beatsBO_WIRE_2.bits.source, UInt<10>(0h0)
connect _beatsBO_WIRE_2.bits.size, UInt<3>(0h0)
connect _beatsBO_WIRE_2.bits.param, UInt<2>(0h0)
connect _beatsBO_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _beatsBO_WIRE_2.valid, UInt<1>(0h0)
connect _beatsBO_WIRE_2.ready, UInt<1>(0h0)
wire _beatsBO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsBO_WIRE_3.bits, _beatsBO_WIRE_2.bits
connect _beatsBO_WIRE_3.valid, _beatsBO_WIRE_2.valid
connect _beatsBO_WIRE_3.ready, _beatsBO_WIRE_2.ready
node _beatsBO_decode_T_3 = dshl(UInt<6>(0h3f), _beatsBO_WIRE_3.bits.size)
node _beatsBO_decode_T_4 = bits(_beatsBO_decode_T_3, 5, 0)
node _beatsBO_decode_T_5 = not(_beatsBO_decode_T_4)
node beatsBO_decode_1 = shr(_beatsBO_decode_T_5, 3)
node _beatsBO_opdata_T_1 = bits(_beatsBO_WIRE_3.bits.opcode, 2, 2)
node beatsBO_opdata_1 = eq(_beatsBO_opdata_T_1, UInt<1>(0h0))
node beatsBO_1 = mux(UInt<1>(0h0), beatsBO_decode_1, UInt<1>(0h0))
wire _beatsBO_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsBO_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _beatsBO_WIRE_4.bits.data, UInt<64>(0h0)
connect _beatsBO_WIRE_4.bits.mask, UInt<8>(0h0)
connect _beatsBO_WIRE_4.bits.address, UInt<29>(0h0)
connect _beatsBO_WIRE_4.bits.source, UInt<10>(0h0)
connect _beatsBO_WIRE_4.bits.size, UInt<3>(0h0)
connect _beatsBO_WIRE_4.bits.param, UInt<2>(0h0)
connect _beatsBO_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _beatsBO_WIRE_4.valid, UInt<1>(0h0)
connect _beatsBO_WIRE_4.ready, UInt<1>(0h0)
wire _beatsBO_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsBO_WIRE_5.bits, _beatsBO_WIRE_4.bits
connect _beatsBO_WIRE_5.valid, _beatsBO_WIRE_4.valid
connect _beatsBO_WIRE_5.ready, _beatsBO_WIRE_4.ready
node _beatsBO_decode_T_6 = dshl(UInt<6>(0h3f), _beatsBO_WIRE_5.bits.size)
node _beatsBO_decode_T_7 = bits(_beatsBO_decode_T_6, 5, 0)
node _beatsBO_decode_T_8 = not(_beatsBO_decode_T_7)
node beatsBO_decode_2 = shr(_beatsBO_decode_T_8, 3)
node _beatsBO_opdata_T_2 = bits(_beatsBO_WIRE_5.bits.opcode, 2, 2)
node beatsBO_opdata_2 = eq(_beatsBO_opdata_T_2, UInt<1>(0h0))
node beatsBO_2 = mux(UInt<1>(0h0), beatsBO_decode_2, UInt<1>(0h0))
wire _beatsCI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsCI_WIRE.bits.corrupt, UInt<1>(0h0)
connect _beatsCI_WIRE.bits.data, UInt<64>(0h0)
connect _beatsCI_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _beatsCI_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _beatsCI_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _beatsCI_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _beatsCI_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _beatsCI_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _beatsCI_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _beatsCI_WIRE.bits.address, UInt<29>(0h0)
connect _beatsCI_WIRE.bits.source, UInt<10>(0h0)
connect _beatsCI_WIRE.bits.size, UInt<3>(0h0)
connect _beatsCI_WIRE.bits.param, UInt<3>(0h0)
connect _beatsCI_WIRE.bits.opcode, UInt<3>(0h0)
connect _beatsCI_WIRE.valid, UInt<1>(0h0)
connect _beatsCI_WIRE.ready, UInt<1>(0h0)
wire _beatsCI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsCI_WIRE_1.bits, _beatsCI_WIRE.bits
connect _beatsCI_WIRE_1.valid, _beatsCI_WIRE.valid
connect _beatsCI_WIRE_1.ready, _beatsCI_WIRE.ready
node _beatsCI_decode_T = dshl(UInt<6>(0h3f), _beatsCI_WIRE_1.bits.size)
node _beatsCI_decode_T_1 = bits(_beatsCI_decode_T, 5, 0)
node _beatsCI_decode_T_2 = not(_beatsCI_decode_T_1)
node beatsCI_decode = shr(_beatsCI_decode_T_2, 3)
node beatsCI_opdata = bits(_beatsCI_WIRE_1.bits.opcode, 0, 0)
node beatsCI_0 = mux(beatsCI_opdata, beatsCI_decode, UInt<1>(0h0))
node _beatsDO_decode_T = dshl(UInt<6>(0h3f), out[0].d.bits.size)
node _beatsDO_decode_T_1 = bits(_beatsDO_decode_T, 5, 0)
node _beatsDO_decode_T_2 = not(_beatsDO_decode_T_1)
node beatsDO_decode = shr(_beatsDO_decode_T_2, 3)
node beatsDO_opdata = bits(out[0].d.bits.opcode, 0, 0)
node beatsDO_0 = mux(beatsDO_opdata, beatsDO_decode, UInt<1>(0h0))
node _beatsDO_decode_T_3 = dshl(UInt<6>(0h3f), out[1].d.bits.size)
node _beatsDO_decode_T_4 = bits(_beatsDO_decode_T_3, 5, 0)
node _beatsDO_decode_T_5 = not(_beatsDO_decode_T_4)
node beatsDO_decode_1 = shr(_beatsDO_decode_T_5, 3)
node beatsDO_opdata_1 = bits(out[1].d.bits.opcode, 0, 0)
node beatsDO_1 = mux(beatsDO_opdata_1, beatsDO_decode_1, UInt<1>(0h0))
node _beatsDO_decode_T_6 = dshl(UInt<6>(0h3f), out[2].d.bits.size)
node _beatsDO_decode_T_7 = bits(_beatsDO_decode_T_6, 5, 0)
node _beatsDO_decode_T_8 = not(_beatsDO_decode_T_7)
node beatsDO_decode_2 = shr(_beatsDO_decode_T_8, 3)
node beatsDO_opdata_2 = bits(out[2].d.bits.opcode, 0, 0)
node beatsDO_2 = mux(beatsDO_opdata_2, beatsDO_decode_2, UInt<1>(0h0))
wire _beatsEI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _beatsEI_WIRE.bits.sink, UInt<1>(0h0)
connect _beatsEI_WIRE.valid, UInt<1>(0h0)
connect _beatsEI_WIRE.ready, UInt<1>(0h0)
wire _beatsEI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _beatsEI_WIRE_1.bits, _beatsEI_WIRE.bits
connect _beatsEI_WIRE_1.valid, _beatsEI_WIRE.valid
connect _beatsEI_WIRE_1.ready, _beatsEI_WIRE.ready
wire portsAOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[3]
connect portsAOI_filtered[0].bits, in[0].a.bits
node _portsAOI_filtered_0_valid_T = or(requestAIO_0_0, UInt<1>(0h0))
node _portsAOI_filtered_0_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_0_valid_T)
connect portsAOI_filtered[0].valid, _portsAOI_filtered_0_valid_T_1
connect portsAOI_filtered[1].bits, in[0].a.bits
node _portsAOI_filtered_1_valid_T = or(requestAIO_0_1, UInt<1>(0h0))
node _portsAOI_filtered_1_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_1_valid_T)
connect portsAOI_filtered[1].valid, _portsAOI_filtered_1_valid_T_1
connect portsAOI_filtered[2].bits, in[0].a.bits
node _portsAOI_filtered_2_valid_T = or(requestAIO_0_2, UInt<1>(0h0))
node _portsAOI_filtered_2_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_2_valid_T)
connect portsAOI_filtered[2].valid, _portsAOI_filtered_2_valid_T_1
node _portsAOI_in_0_a_ready_T = mux(requestAIO_0_0, portsAOI_filtered[0].ready, UInt<1>(0h0))
node _portsAOI_in_0_a_ready_T_1 = mux(requestAIO_0_1, portsAOI_filtered[1].ready, UInt<1>(0h0))
node _portsAOI_in_0_a_ready_T_2 = mux(requestAIO_0_2, portsAOI_filtered[2].ready, UInt<1>(0h0))
node _portsAOI_in_0_a_ready_T_3 = or(_portsAOI_in_0_a_ready_T, _portsAOI_in_0_a_ready_T_1)
node _portsAOI_in_0_a_ready_T_4 = or(_portsAOI_in_0_a_ready_T_3, _portsAOI_in_0_a_ready_T_2)
wire _portsAOI_in_0_a_ready_WIRE : UInt<1>
connect _portsAOI_in_0_a_ready_WIRE, _portsAOI_in_0_a_ready_T_4
connect in[0].a.ready, _portsAOI_in_0_a_ready_WIRE
wire _portsBIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _portsBIO_WIRE.bits.corrupt, UInt<1>(0h0)
connect _portsBIO_WIRE.bits.data, UInt<64>(0h0)
connect _portsBIO_WIRE.bits.mask, UInt<8>(0h0)
connect _portsBIO_WIRE.bits.address, UInt<29>(0h0)
connect _portsBIO_WIRE.bits.source, UInt<10>(0h0)
connect _portsBIO_WIRE.bits.size, UInt<3>(0h0)
connect _portsBIO_WIRE.bits.param, UInt<2>(0h0)
connect _portsBIO_WIRE.bits.opcode, UInt<3>(0h0)
connect _portsBIO_WIRE.valid, UInt<1>(0h0)
connect _portsBIO_WIRE.ready, UInt<1>(0h0)
wire _portsBIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _portsBIO_WIRE_1.bits, _portsBIO_WIRE.bits
connect _portsBIO_WIRE_1.valid, _portsBIO_WIRE.valid
connect _portsBIO_WIRE_1.ready, _portsBIO_WIRE.ready
wire portsBIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsBIO_filtered[0].bits, _portsBIO_WIRE_1.bits
node _portsBIO_filtered_0_valid_T = or(requestBOI_0_0, UInt<1>(0h1))
node _portsBIO_filtered_0_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_0_valid_T)
connect portsBIO_filtered[0].valid, _portsBIO_filtered_0_valid_T_1
connect _portsBIO_WIRE_1.ready, portsBIO_filtered[0].ready
wire _portsBIO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _portsBIO_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _portsBIO_WIRE_2.bits.data, UInt<64>(0h0)
connect _portsBIO_WIRE_2.bits.mask, UInt<8>(0h0)
connect _portsBIO_WIRE_2.bits.address, UInt<29>(0h0)
connect _portsBIO_WIRE_2.bits.source, UInt<10>(0h0)
connect _portsBIO_WIRE_2.bits.size, UInt<3>(0h0)
connect _portsBIO_WIRE_2.bits.param, UInt<2>(0h0)
connect _portsBIO_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _portsBIO_WIRE_2.valid, UInt<1>(0h0)
connect _portsBIO_WIRE_2.ready, UInt<1>(0h0)
wire _portsBIO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _portsBIO_WIRE_3.bits, _portsBIO_WIRE_2.bits
connect _portsBIO_WIRE_3.valid, _portsBIO_WIRE_2.valid
connect _portsBIO_WIRE_3.ready, _portsBIO_WIRE_2.ready
wire portsBIO_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsBIO_filtered_1[0].bits, _portsBIO_WIRE_3.bits
node _portsBIO_filtered_0_valid_T_2 = or(requestBOI_1_0, UInt<1>(0h1))
node _portsBIO_filtered_0_valid_T_3 = and(_portsBIO_WIRE_3.valid, _portsBIO_filtered_0_valid_T_2)
connect portsBIO_filtered_1[0].valid, _portsBIO_filtered_0_valid_T_3
connect _portsBIO_WIRE_3.ready, portsBIO_filtered_1[0].ready
wire _portsBIO_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _portsBIO_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _portsBIO_WIRE_4.bits.data, UInt<64>(0h0)
connect _portsBIO_WIRE_4.bits.mask, UInt<8>(0h0)
connect _portsBIO_WIRE_4.bits.address, UInt<29>(0h0)
connect _portsBIO_WIRE_4.bits.source, UInt<10>(0h0)
connect _portsBIO_WIRE_4.bits.size, UInt<3>(0h0)
connect _portsBIO_WIRE_4.bits.param, UInt<2>(0h0)
connect _portsBIO_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _portsBIO_WIRE_4.valid, UInt<1>(0h0)
connect _portsBIO_WIRE_4.ready, UInt<1>(0h0)
wire _portsBIO_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _portsBIO_WIRE_5.bits, _portsBIO_WIRE_4.bits
connect _portsBIO_WIRE_5.valid, _portsBIO_WIRE_4.valid
connect _portsBIO_WIRE_5.ready, _portsBIO_WIRE_4.ready
wire portsBIO_filtered_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsBIO_filtered_2[0].bits, _portsBIO_WIRE_5.bits
node _portsBIO_filtered_0_valid_T_4 = or(requestBOI_2_0, UInt<1>(0h1))
node _portsBIO_filtered_0_valid_T_5 = and(_portsBIO_WIRE_5.valid, _portsBIO_filtered_0_valid_T_4)
connect portsBIO_filtered_2[0].valid, _portsBIO_filtered_0_valid_T_5
connect _portsBIO_WIRE_5.ready, portsBIO_filtered_2[0].ready
wire _portsCOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _portsCOI_WIRE.bits.corrupt, UInt<1>(0h0)
connect _portsCOI_WIRE.bits.data, UInt<64>(0h0)
connect _portsCOI_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _portsCOI_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _portsCOI_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _portsCOI_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _portsCOI_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _portsCOI_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _portsCOI_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _portsCOI_WIRE.bits.address, UInt<29>(0h0)
connect _portsCOI_WIRE.bits.source, UInt<10>(0h0)
connect _portsCOI_WIRE.bits.size, UInt<3>(0h0)
connect _portsCOI_WIRE.bits.param, UInt<3>(0h0)
connect _portsCOI_WIRE.bits.opcode, UInt<3>(0h0)
connect _portsCOI_WIRE.valid, UInt<1>(0h0)
connect _portsCOI_WIRE.ready, UInt<1>(0h0)
wire _portsCOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _portsCOI_WIRE_1.bits, _portsCOI_WIRE.bits
connect _portsCOI_WIRE_1.valid, _portsCOI_WIRE.valid
connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE.ready
wire portsCOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[3]
connect portsCOI_filtered[0].bits, _portsCOI_WIRE_1.bits
node _portsCOI_filtered_0_valid_T = or(requestCIO_0_0, UInt<1>(0h0))
node _portsCOI_filtered_0_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_0_valid_T)
connect portsCOI_filtered[0].valid, _portsCOI_filtered_0_valid_T_1
connect portsCOI_filtered[1].bits, _portsCOI_WIRE_1.bits
node _portsCOI_filtered_1_valid_T = or(requestCIO_0_1, UInt<1>(0h0))
node _portsCOI_filtered_1_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_1_valid_T)
connect portsCOI_filtered[1].valid, _portsCOI_filtered_1_valid_T_1
connect portsCOI_filtered[2].bits, _portsCOI_WIRE_1.bits
node _portsCOI_filtered_2_valid_T = or(requestCIO_0_2, UInt<1>(0h0))
node _portsCOI_filtered_2_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_2_valid_T)
connect portsCOI_filtered[2].valid, _portsCOI_filtered_2_valid_T_1
node _portsCOI_T = mux(requestCIO_0_0, portsCOI_filtered[0].ready, UInt<1>(0h0))
node _portsCOI_T_1 = mux(requestCIO_0_1, portsCOI_filtered[1].ready, UInt<1>(0h0))
node _portsCOI_T_2 = mux(requestCIO_0_2, portsCOI_filtered[2].ready, UInt<1>(0h0))
node _portsCOI_T_3 = or(_portsCOI_T, _portsCOI_T_1)
node _portsCOI_T_4 = or(_portsCOI_T_3, _portsCOI_T_2)
wire _portsCOI_WIRE_2 : UInt<1>
connect _portsCOI_WIRE_2, _portsCOI_T_4
connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE_2
wire portsDIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsDIO_filtered[0].bits.corrupt, out[0].d.bits.corrupt
connect portsDIO_filtered[0].bits.data, out[0].d.bits.data
connect portsDIO_filtered[0].bits.denied, out[0].d.bits.denied
connect portsDIO_filtered[0].bits.sink, out[0].d.bits.sink
connect portsDIO_filtered[0].bits.source, out[0].d.bits.source
connect portsDIO_filtered[0].bits.size, out[0].d.bits.size
connect portsDIO_filtered[0].bits.param, out[0].d.bits.param
connect portsDIO_filtered[0].bits.opcode, out[0].d.bits.opcode
node _portsDIO_filtered_0_valid_T = or(requestDOI_0_0, UInt<1>(0h1))
node _portsDIO_filtered_0_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_0_valid_T)
connect portsDIO_filtered[0].valid, _portsDIO_filtered_0_valid_T_1
connect out[0].d.ready, portsDIO_filtered[0].ready
wire portsDIO_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsDIO_filtered_1[0].bits.corrupt, out[1].d.bits.corrupt
connect portsDIO_filtered_1[0].bits.data, out[1].d.bits.data
connect portsDIO_filtered_1[0].bits.denied, out[1].d.bits.denied
connect portsDIO_filtered_1[0].bits.sink, out[1].d.bits.sink
connect portsDIO_filtered_1[0].bits.source, out[1].d.bits.source
connect portsDIO_filtered_1[0].bits.size, out[1].d.bits.size
connect portsDIO_filtered_1[0].bits.param, out[1].d.bits.param
connect portsDIO_filtered_1[0].bits.opcode, out[1].d.bits.opcode
node _portsDIO_filtered_0_valid_T_2 = or(requestDOI_1_0, UInt<1>(0h1))
node _portsDIO_filtered_0_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_0_valid_T_2)
connect portsDIO_filtered_1[0].valid, _portsDIO_filtered_0_valid_T_3
connect out[1].d.ready, portsDIO_filtered_1[0].ready
wire portsDIO_filtered_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsDIO_filtered_2[0].bits.corrupt, out[2].d.bits.corrupt
connect portsDIO_filtered_2[0].bits.data, out[2].d.bits.data
connect portsDIO_filtered_2[0].bits.denied, out[2].d.bits.denied
connect portsDIO_filtered_2[0].bits.sink, out[2].d.bits.sink
connect portsDIO_filtered_2[0].bits.source, out[2].d.bits.source
connect portsDIO_filtered_2[0].bits.size, out[2].d.bits.size
connect portsDIO_filtered_2[0].bits.param, out[2].d.bits.param
connect portsDIO_filtered_2[0].bits.opcode, out[2].d.bits.opcode
node _portsDIO_filtered_0_valid_T_4 = or(requestDOI_2_0, UInt<1>(0h1))
node _portsDIO_filtered_0_valid_T_5 = and(out[2].d.valid, _portsDIO_filtered_0_valid_T_4)
connect portsDIO_filtered_2[0].valid, _portsDIO_filtered_0_valid_T_5
connect out[2].d.ready, portsDIO_filtered_2[0].ready
wire _portsEOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _portsEOI_WIRE.bits.sink, UInt<1>(0h0)
connect _portsEOI_WIRE.valid, UInt<1>(0h0)
connect _portsEOI_WIRE.ready, UInt<1>(0h0)
wire _portsEOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _portsEOI_WIRE_1.bits, _portsEOI_WIRE.bits
connect _portsEOI_WIRE_1.valid, _portsEOI_WIRE.valid
connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE.ready
wire portsEOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}[3]
connect portsEOI_filtered[0].bits, _portsEOI_WIRE_1.bits
node _portsEOI_filtered_0_valid_T = or(UInt<1>(0h0), UInt<1>(0h0))
node _portsEOI_filtered_0_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_0_valid_T)
connect portsEOI_filtered[0].valid, _portsEOI_filtered_0_valid_T_1
connect portsEOI_filtered[1].bits, _portsEOI_WIRE_1.bits
node _portsEOI_filtered_1_valid_T = or(UInt<1>(0h0), UInt<1>(0h0))
node _portsEOI_filtered_1_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_1_valid_T)
connect portsEOI_filtered[1].valid, _portsEOI_filtered_1_valid_T_1
connect portsEOI_filtered[2].bits, _portsEOI_WIRE_1.bits
node _portsEOI_filtered_2_valid_T = or(UInt<1>(0h0), UInt<1>(0h0))
node _portsEOI_filtered_2_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_2_valid_T)
connect portsEOI_filtered[2].valid, _portsEOI_filtered_2_valid_T_1
node _portsEOI_T = mux(UInt<1>(0h0), portsEOI_filtered[0].ready, UInt<1>(0h0))
node _portsEOI_T_1 = mux(UInt<1>(0h0), portsEOI_filtered[1].ready, UInt<1>(0h0))
node _portsEOI_T_2 = mux(UInt<1>(0h0), portsEOI_filtered[2].ready, UInt<1>(0h0))
node _portsEOI_T_3 = or(_portsEOI_T, _portsEOI_T_1)
node _portsEOI_T_4 = or(_portsEOI_T_3, _portsEOI_T_2)
wire _portsEOI_WIRE_2 : UInt<1>
connect _portsEOI_WIRE_2, _portsEOI_T_4
connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE_2
connect out[0].a, portsAOI_filtered[0]
wire _WIRE_96 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_96.bits.corrupt, UInt<1>(0h0)
connect _WIRE_96.bits.data, UInt<64>(0h0)
connect _WIRE_96.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_96.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_96.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_96.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_96.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_96.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_96.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_96.bits.address, UInt<29>(0h0)
connect _WIRE_96.bits.source, UInt<10>(0h0)
connect _WIRE_96.bits.size, UInt<3>(0h0)
connect _WIRE_96.bits.param, UInt<3>(0h0)
connect _WIRE_96.bits.opcode, UInt<3>(0h0)
connect _WIRE_96.valid, UInt<1>(0h0)
connect _WIRE_96.ready, UInt<1>(0h0)
wire _WIRE_97 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_97.bits, _WIRE_96.bits
connect _WIRE_97.valid, _WIRE_96.valid
connect _WIRE_97.ready, _WIRE_96.ready
invalidate _WIRE_97.bits.corrupt
invalidate _WIRE_97.bits.data
invalidate _WIRE_97.bits.user.amba_prot.fetch
invalidate _WIRE_97.bits.user.amba_prot.secure
invalidate _WIRE_97.bits.user.amba_prot.privileged
invalidate _WIRE_97.bits.user.amba_prot.writealloc
invalidate _WIRE_97.bits.user.amba_prot.readalloc
invalidate _WIRE_97.bits.user.amba_prot.modifiable
invalidate _WIRE_97.bits.user.amba_prot.bufferable
invalidate _WIRE_97.bits.address
invalidate _WIRE_97.bits.source
invalidate _WIRE_97.bits.size
invalidate _WIRE_97.bits.param
invalidate _WIRE_97.bits.opcode
wire _WIRE_98 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_98.bits.sink, UInt<1>(0h0)
connect _WIRE_98.valid, UInt<1>(0h0)
connect _WIRE_98.ready, UInt<1>(0h0)
wire _WIRE_99 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_99.bits, _WIRE_98.bits
connect _WIRE_99.valid, _WIRE_98.valid
connect _WIRE_99.ready, _WIRE_98.ready
invalidate _WIRE_99.bits.sink
connect portsCOI_filtered[0].ready, UInt<1>(0h0)
connect portsEOI_filtered[0].ready, UInt<1>(0h0)
connect out[1].a, portsAOI_filtered[1]
wire _WIRE_100 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_100.bits.corrupt, UInt<1>(0h0)
connect _WIRE_100.bits.data, UInt<64>(0h0)
connect _WIRE_100.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_100.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_100.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_100.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_100.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_100.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_100.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_100.bits.address, UInt<29>(0h0)
connect _WIRE_100.bits.source, UInt<10>(0h0)
connect _WIRE_100.bits.size, UInt<3>(0h0)
connect _WIRE_100.bits.param, UInt<3>(0h0)
connect _WIRE_100.bits.opcode, UInt<3>(0h0)
connect _WIRE_100.valid, UInt<1>(0h0)
connect _WIRE_100.ready, UInt<1>(0h0)
wire _WIRE_101 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_101.bits, _WIRE_100.bits
connect _WIRE_101.valid, _WIRE_100.valid
connect _WIRE_101.ready, _WIRE_100.ready
invalidate _WIRE_101.bits.corrupt
invalidate _WIRE_101.bits.data
invalidate _WIRE_101.bits.user.amba_prot.fetch
invalidate _WIRE_101.bits.user.amba_prot.secure
invalidate _WIRE_101.bits.user.amba_prot.privileged
invalidate _WIRE_101.bits.user.amba_prot.writealloc
invalidate _WIRE_101.bits.user.amba_prot.readalloc
invalidate _WIRE_101.bits.user.amba_prot.modifiable
invalidate _WIRE_101.bits.user.amba_prot.bufferable
invalidate _WIRE_101.bits.address
invalidate _WIRE_101.bits.source
invalidate _WIRE_101.bits.size
invalidate _WIRE_101.bits.param
invalidate _WIRE_101.bits.opcode
wire _WIRE_102 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_102.bits.sink, UInt<1>(0h0)
connect _WIRE_102.valid, UInt<1>(0h0)
connect _WIRE_102.ready, UInt<1>(0h0)
wire _WIRE_103 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_103.bits, _WIRE_102.bits
connect _WIRE_103.valid, _WIRE_102.valid
connect _WIRE_103.ready, _WIRE_102.ready
invalidate _WIRE_103.bits.sink
connect portsCOI_filtered[1].ready, UInt<1>(0h0)
connect portsEOI_filtered[1].ready, UInt<1>(0h0)
connect out[2].a, portsAOI_filtered[2]
wire _WIRE_104 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_104.bits.corrupt, UInt<1>(0h0)
connect _WIRE_104.bits.data, UInt<64>(0h0)
connect _WIRE_104.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_104.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_104.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_104.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_104.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_104.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_104.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_104.bits.address, UInt<29>(0h0)
connect _WIRE_104.bits.source, UInt<10>(0h0)
connect _WIRE_104.bits.size, UInt<3>(0h0)
connect _WIRE_104.bits.param, UInt<3>(0h0)
connect _WIRE_104.bits.opcode, UInt<3>(0h0)
connect _WIRE_104.valid, UInt<1>(0h0)
connect _WIRE_104.ready, UInt<1>(0h0)
wire _WIRE_105 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_105.bits, _WIRE_104.bits
connect _WIRE_105.valid, _WIRE_104.valid
connect _WIRE_105.ready, _WIRE_104.ready
invalidate _WIRE_105.bits.corrupt
invalidate _WIRE_105.bits.data
invalidate _WIRE_105.bits.user.amba_prot.fetch
invalidate _WIRE_105.bits.user.amba_prot.secure
invalidate _WIRE_105.bits.user.amba_prot.privileged
invalidate _WIRE_105.bits.user.amba_prot.writealloc
invalidate _WIRE_105.bits.user.amba_prot.readalloc
invalidate _WIRE_105.bits.user.amba_prot.modifiable
invalidate _WIRE_105.bits.user.amba_prot.bufferable
invalidate _WIRE_105.bits.address
invalidate _WIRE_105.bits.source
invalidate _WIRE_105.bits.size
invalidate _WIRE_105.bits.param
invalidate _WIRE_105.bits.opcode
wire _WIRE_106 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_106.bits.sink, UInt<1>(0h0)
connect _WIRE_106.valid, UInt<1>(0h0)
connect _WIRE_106.ready, UInt<1>(0h0)
wire _WIRE_107 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_107.bits, _WIRE_106.bits
connect _WIRE_107.valid, _WIRE_106.valid
connect _WIRE_107.ready, _WIRE_106.ready
invalidate _WIRE_107.bits.sink
connect portsCOI_filtered[2].ready, UInt<1>(0h0)
connect portsEOI_filtered[2].ready, UInt<1>(0h0)
wire _WIRE_108 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_108.bits.corrupt, UInt<1>(0h0)
connect _WIRE_108.bits.data, UInt<64>(0h0)
connect _WIRE_108.bits.mask, UInt<8>(0h0)
connect _WIRE_108.bits.address, UInt<29>(0h0)
connect _WIRE_108.bits.source, UInt<10>(0h0)
connect _WIRE_108.bits.size, UInt<3>(0h0)
connect _WIRE_108.bits.param, UInt<2>(0h0)
connect _WIRE_108.bits.opcode, UInt<3>(0h0)
connect _WIRE_108.valid, UInt<1>(0h0)
connect _WIRE_108.ready, UInt<1>(0h0)
wire _WIRE_109 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_109.bits, _WIRE_108.bits
connect _WIRE_109.valid, _WIRE_108.valid
connect _WIRE_109.ready, _WIRE_108.ready
invalidate _WIRE_109.bits.corrupt
invalidate _WIRE_109.bits.data
invalidate _WIRE_109.bits.mask
invalidate _WIRE_109.bits.address
invalidate _WIRE_109.bits.source
invalidate _WIRE_109.bits.size
invalidate _WIRE_109.bits.param
invalidate _WIRE_109.bits.opcode
regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0)
node idle = eq(beatsLeft, UInt<1>(0h0))
node latch = and(idle, in[0].d.ready)
node readys_hi = cat(portsDIO_filtered_2[0].valid, portsDIO_filtered_1[0].valid)
node _readys_T = cat(readys_hi, portsDIO_filtered[0].valid)
node readys_valid = bits(_readys_T, 2, 0)
node _readys_T_1 = eq(readys_valid, _readys_T)
node _readys_T_2 = asUInt(reset)
node _readys_T_3 = eq(_readys_T_2, UInt<1>(0h0))
when _readys_T_3 :
node _readys_T_4 = eq(_readys_T_1, UInt<1>(0h0))
when _readys_T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf
assert(clock, _readys_T_1, UInt<1>(0h1), "") : readys_assert
regreset readys_mask : UInt<3>, clock, reset, UInt<3>(0h7)
node _readys_filter_T = not(readys_mask)
node _readys_filter_T_1 = and(readys_valid, _readys_filter_T)
node readys_filter = cat(_readys_filter_T_1, readys_valid)
node _readys_unready_T = shr(readys_filter, 1)
node _readys_unready_T_1 = or(readys_filter, _readys_unready_T)
node _readys_unready_T_2 = shr(_readys_unready_T_1, 2)
node _readys_unready_T_3 = or(_readys_unready_T_1, _readys_unready_T_2)
node _readys_unready_T_4 = bits(_readys_unready_T_3, 5, 0)
node _readys_unready_T_5 = shr(_readys_unready_T_4, 1)
node _readys_unready_T_6 = shl(readys_mask, 3)
node readys_unready = or(_readys_unready_T_5, _readys_unready_T_6)
node _readys_readys_T = shr(readys_unready, 3)
node _readys_readys_T_1 = bits(readys_unready, 2, 0)
node _readys_readys_T_2 = and(_readys_readys_T, _readys_readys_T_1)
node readys_readys = not(_readys_readys_T_2)
node _readys_T_5 = orr(readys_valid)
node _readys_T_6 = and(latch, _readys_T_5)
when _readys_T_6 :
node _readys_mask_T = and(readys_readys, readys_valid)
node _readys_mask_T_1 = shl(_readys_mask_T, 1)
node _readys_mask_T_2 = bits(_readys_mask_T_1, 2, 0)
node _readys_mask_T_3 = or(_readys_mask_T, _readys_mask_T_2)
node _readys_mask_T_4 = shl(_readys_mask_T_3, 2)
node _readys_mask_T_5 = bits(_readys_mask_T_4, 2, 0)
node _readys_mask_T_6 = or(_readys_mask_T_3, _readys_mask_T_5)
node _readys_mask_T_7 = bits(_readys_mask_T_6, 2, 0)
connect readys_mask, _readys_mask_T_7
node _readys_T_7 = bits(readys_readys, 2, 0)
node _readys_T_8 = bits(_readys_T_7, 0, 0)
node _readys_T_9 = bits(_readys_T_7, 1, 1)
node _readys_T_10 = bits(_readys_T_7, 2, 2)
wire readys : UInt<1>[3]
connect readys[0], _readys_T_8
connect readys[1], _readys_T_9
connect readys[2], _readys_T_10
node _winner_T = and(readys[0], portsDIO_filtered[0].valid)
node _winner_T_1 = and(readys[1], portsDIO_filtered_1[0].valid)
node _winner_T_2 = and(readys[2], portsDIO_filtered_2[0].valid)
wire winner : UInt<1>[3]
connect winner[0], _winner_T
connect winner[1], _winner_T_1
connect winner[2], _winner_T_2
node prefixOR_1 = or(UInt<1>(0h0), winner[0])
node prefixOR_2 = or(prefixOR_1, winner[1])
node _prefixOR_T = or(prefixOR_2, winner[2])
node _T = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_1 = eq(winner[0], UInt<1>(0h0))
node _T_2 = or(_T, _T_1)
node _T_3 = eq(prefixOR_1, UInt<1>(0h0))
node _T_4 = eq(winner[1], UInt<1>(0h0))
node _T_5 = or(_T_3, _T_4)
node _T_6 = eq(prefixOR_2, UInt<1>(0h0))
node _T_7 = eq(winner[2], UInt<1>(0h0))
node _T_8 = or(_T_6, _T_7)
node _T_9 = and(_T_2, _T_5)
node _T_10 = and(_T_9, _T_8)
node _T_11 = asUInt(reset)
node _T_12 = eq(_T_11, UInt<1>(0h0))
when _T_12 :
node _T_13 = eq(_T_10, UInt<1>(0h0))
when _T_13 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf
assert(clock, _T_10, UInt<1>(0h1), "") : assert
node _T_14 = or(portsDIO_filtered[0].valid, portsDIO_filtered_1[0].valid)
node _T_15 = or(_T_14, portsDIO_filtered_2[0].valid)
node _T_16 = eq(_T_15, UInt<1>(0h0))
node _T_17 = or(winner[0], winner[1])
node _T_18 = or(_T_17, winner[2])
node _T_19 = or(_T_16, _T_18)
node _T_20 = asUInt(reset)
node _T_21 = eq(_T_20, UInt<1>(0h0))
when _T_21 :
node _T_22 = eq(_T_19, UInt<1>(0h0))
when _T_22 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_1
assert(clock, _T_19, UInt<1>(0h1), "") : assert_1
node maskedBeats_0 = mux(winner[0], beatsDO_0, UInt<1>(0h0))
node maskedBeats_1 = mux(winner[1], beatsDO_1, UInt<1>(0h0))
node maskedBeats_2 = mux(winner[2], beatsDO_2, UInt<1>(0h0))
node _initBeats_T = or(maskedBeats_0, maskedBeats_1)
node initBeats = or(_initBeats_T, maskedBeats_2)
node _beatsLeft_T = and(in[0].d.ready, in[0].d.valid)
node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T)
node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1)
node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2)
connect beatsLeft, _beatsLeft_T_3
wire _state_WIRE : UInt<1>[3]
connect _state_WIRE[0], UInt<1>(0h0)
connect _state_WIRE[1], UInt<1>(0h0)
connect _state_WIRE[2], UInt<1>(0h0)
regreset state : UInt<1>[3], clock, reset, _state_WIRE
node muxState = mux(idle, winner, state)
connect state, muxState
node allowed = mux(idle, readys, state)
node _filtered_0_ready_T = and(in[0].d.ready, allowed[0])
connect portsDIO_filtered[0].ready, _filtered_0_ready_T
node _filtered_0_ready_T_1 = and(in[0].d.ready, allowed[1])
connect portsDIO_filtered_1[0].ready, _filtered_0_ready_T_1
node _filtered_0_ready_T_2 = and(in[0].d.ready, allowed[2])
connect portsDIO_filtered_2[0].ready, _filtered_0_ready_T_2
node _in_0_d_valid_T = or(portsDIO_filtered[0].valid, portsDIO_filtered_1[0].valid)
node _in_0_d_valid_T_1 = or(_in_0_d_valid_T, portsDIO_filtered_2[0].valid)
node _in_0_d_valid_T_2 = mux(state[0], portsDIO_filtered[0].valid, UInt<1>(0h0))
node _in_0_d_valid_T_3 = mux(state[1], portsDIO_filtered_1[0].valid, UInt<1>(0h0))
node _in_0_d_valid_T_4 = mux(state[2], portsDIO_filtered_2[0].valid, UInt<1>(0h0))
node _in_0_d_valid_T_5 = or(_in_0_d_valid_T_2, _in_0_d_valid_T_3)
node _in_0_d_valid_T_6 = or(_in_0_d_valid_T_5, _in_0_d_valid_T_4)
wire _in_0_d_valid_WIRE : UInt<1>
connect _in_0_d_valid_WIRE, _in_0_d_valid_T_6
node _in_0_d_valid_T_7 = mux(idle, _in_0_d_valid_T_1, _in_0_d_valid_WIRE)
connect in[0].d.valid, _in_0_d_valid_T_7
wire _in_0_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
node _in_0_d_bits_T = mux(muxState[0], portsDIO_filtered[0].bits.corrupt, UInt<1>(0h0))
node _in_0_d_bits_T_1 = mux(muxState[1], portsDIO_filtered_1[0].bits.corrupt, UInt<1>(0h0))
node _in_0_d_bits_T_2 = mux(muxState[2], portsDIO_filtered_2[0].bits.corrupt, UInt<1>(0h0))
node _in_0_d_bits_T_3 = or(_in_0_d_bits_T, _in_0_d_bits_T_1)
node _in_0_d_bits_T_4 = or(_in_0_d_bits_T_3, _in_0_d_bits_T_2)
wire _in_0_d_bits_WIRE_1 : UInt<1>
connect _in_0_d_bits_WIRE_1, _in_0_d_bits_T_4
connect _in_0_d_bits_WIRE.corrupt, _in_0_d_bits_WIRE_1
node _in_0_d_bits_T_5 = mux(muxState[0], portsDIO_filtered[0].bits.data, UInt<1>(0h0))
node _in_0_d_bits_T_6 = mux(muxState[1], portsDIO_filtered_1[0].bits.data, UInt<1>(0h0))
node _in_0_d_bits_T_7 = mux(muxState[2], portsDIO_filtered_2[0].bits.data, UInt<1>(0h0))
node _in_0_d_bits_T_8 = or(_in_0_d_bits_T_5, _in_0_d_bits_T_6)
node _in_0_d_bits_T_9 = or(_in_0_d_bits_T_8, _in_0_d_bits_T_7)
wire _in_0_d_bits_WIRE_2 : UInt<64>
connect _in_0_d_bits_WIRE_2, _in_0_d_bits_T_9
connect _in_0_d_bits_WIRE.data, _in_0_d_bits_WIRE_2
wire _in_0_d_bits_WIRE_3 : { }
connect _in_0_d_bits_WIRE.echo, _in_0_d_bits_WIRE_3
wire _in_0_d_bits_WIRE_4 : { }
connect _in_0_d_bits_WIRE.user, _in_0_d_bits_WIRE_4
node _in_0_d_bits_T_10 = mux(muxState[0], portsDIO_filtered[0].bits.denied, UInt<1>(0h0))
node _in_0_d_bits_T_11 = mux(muxState[1], portsDIO_filtered_1[0].bits.denied, UInt<1>(0h0))
node _in_0_d_bits_T_12 = mux(muxState[2], portsDIO_filtered_2[0].bits.denied, UInt<1>(0h0))
node _in_0_d_bits_T_13 = or(_in_0_d_bits_T_10, _in_0_d_bits_T_11)
node _in_0_d_bits_T_14 = or(_in_0_d_bits_T_13, _in_0_d_bits_T_12)
wire _in_0_d_bits_WIRE_5 : UInt<1>
connect _in_0_d_bits_WIRE_5, _in_0_d_bits_T_14
connect _in_0_d_bits_WIRE.denied, _in_0_d_bits_WIRE_5
node _in_0_d_bits_T_15 = mux(muxState[0], portsDIO_filtered[0].bits.sink, UInt<1>(0h0))
node _in_0_d_bits_T_16 = mux(muxState[1], portsDIO_filtered_1[0].bits.sink, UInt<1>(0h0))
node _in_0_d_bits_T_17 = mux(muxState[2], portsDIO_filtered_2[0].bits.sink, UInt<1>(0h0))
node _in_0_d_bits_T_18 = or(_in_0_d_bits_T_15, _in_0_d_bits_T_16)
node _in_0_d_bits_T_19 = or(_in_0_d_bits_T_18, _in_0_d_bits_T_17)
wire _in_0_d_bits_WIRE_6 : UInt<1>
connect _in_0_d_bits_WIRE_6, _in_0_d_bits_T_19
connect _in_0_d_bits_WIRE.sink, _in_0_d_bits_WIRE_6
node _in_0_d_bits_T_20 = mux(muxState[0], portsDIO_filtered[0].bits.source, UInt<1>(0h0))
node _in_0_d_bits_T_21 = mux(muxState[1], portsDIO_filtered_1[0].bits.source, UInt<1>(0h0))
node _in_0_d_bits_T_22 = mux(muxState[2], portsDIO_filtered_2[0].bits.source, UInt<1>(0h0))
node _in_0_d_bits_T_23 = or(_in_0_d_bits_T_20, _in_0_d_bits_T_21)
node _in_0_d_bits_T_24 = or(_in_0_d_bits_T_23, _in_0_d_bits_T_22)
wire _in_0_d_bits_WIRE_7 : UInt<10>
connect _in_0_d_bits_WIRE_7, _in_0_d_bits_T_24
connect _in_0_d_bits_WIRE.source, _in_0_d_bits_WIRE_7
node _in_0_d_bits_T_25 = mux(muxState[0], portsDIO_filtered[0].bits.size, UInt<1>(0h0))
node _in_0_d_bits_T_26 = mux(muxState[1], portsDIO_filtered_1[0].bits.size, UInt<1>(0h0))
node _in_0_d_bits_T_27 = mux(muxState[2], portsDIO_filtered_2[0].bits.size, UInt<1>(0h0))
node _in_0_d_bits_T_28 = or(_in_0_d_bits_T_25, _in_0_d_bits_T_26)
node _in_0_d_bits_T_29 = or(_in_0_d_bits_T_28, _in_0_d_bits_T_27)
wire _in_0_d_bits_WIRE_8 : UInt<3>
connect _in_0_d_bits_WIRE_8, _in_0_d_bits_T_29
connect _in_0_d_bits_WIRE.size, _in_0_d_bits_WIRE_8
node _in_0_d_bits_T_30 = mux(muxState[0], portsDIO_filtered[0].bits.param, UInt<1>(0h0))
node _in_0_d_bits_T_31 = mux(muxState[1], portsDIO_filtered_1[0].bits.param, UInt<1>(0h0))
node _in_0_d_bits_T_32 = mux(muxState[2], portsDIO_filtered_2[0].bits.param, UInt<1>(0h0))
node _in_0_d_bits_T_33 = or(_in_0_d_bits_T_30, _in_0_d_bits_T_31)
node _in_0_d_bits_T_34 = or(_in_0_d_bits_T_33, _in_0_d_bits_T_32)
wire _in_0_d_bits_WIRE_9 : UInt<2>
connect _in_0_d_bits_WIRE_9, _in_0_d_bits_T_34
connect _in_0_d_bits_WIRE.param, _in_0_d_bits_WIRE_9
node _in_0_d_bits_T_35 = mux(muxState[0], portsDIO_filtered[0].bits.opcode, UInt<1>(0h0))
node _in_0_d_bits_T_36 = mux(muxState[1], portsDIO_filtered_1[0].bits.opcode, UInt<1>(0h0))
node _in_0_d_bits_T_37 = mux(muxState[2], portsDIO_filtered_2[0].bits.opcode, UInt<1>(0h0))
node _in_0_d_bits_T_38 = or(_in_0_d_bits_T_35, _in_0_d_bits_T_36)
node _in_0_d_bits_T_39 = or(_in_0_d_bits_T_38, _in_0_d_bits_T_37)
wire _in_0_d_bits_WIRE_10 : UInt<3>
connect _in_0_d_bits_WIRE_10, _in_0_d_bits_T_39
connect _in_0_d_bits_WIRE.opcode, _in_0_d_bits_WIRE_10
connect in[0].d.bits.corrupt, _in_0_d_bits_WIRE.corrupt
connect in[0].d.bits.data, _in_0_d_bits_WIRE.data
connect in[0].d.bits.denied, _in_0_d_bits_WIRE.denied
connect in[0].d.bits.sink, _in_0_d_bits_WIRE.sink
connect in[0].d.bits.source, _in_0_d_bits_WIRE.source
connect in[0].d.bits.size, _in_0_d_bits_WIRE.size
connect in[0].d.bits.param, _in_0_d_bits_WIRE.param
connect in[0].d.bits.opcode, _in_0_d_bits_WIRE.opcode
connect portsBIO_filtered[0].ready, UInt<1>(0h0)
connect portsBIO_filtered_1[0].ready, UInt<1>(0h0)
connect portsBIO_filtered_2[0].ready, UInt<1>(0h0)
extmodule plusarg_reader_16 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_17 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLXbar_pbus_out_i1_o3_a29d64s10k1z3u( // @[Xbar.scala:74:9]
input clock, // @[Xbar.scala:74:9]
input reset, // @[Xbar.scala:74:9]
output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [9:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [28:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_user_amba_prot_fetch, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [9:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_2_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_2_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_2_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_2_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_2_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [9:0] auto_anon_out_2_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [28:0] auto_anon_out_2_a_bits_address, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_2_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_2_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_2_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_2_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_2_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_2_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_2_a_bits_user_amba_prot_fetch, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_2_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_2_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_2_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_2_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_2_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_2_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_2_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_2_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [9:0] auto_anon_out_2_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_2_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_2_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_2_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_2_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [9:0] auto_anon_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [28:0] auto_anon_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [9:0] auto_anon_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_0_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [9:0] auto_anon_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [12:0] auto_anon_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_0_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [9:0] auto_anon_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_0_d_bits_data // @[LazyModuleImp.scala:107:25]
);
wire requestAIO_0_0 = {auto_anon_in_a_bits_address[28], auto_anon_in_a_bits_address[18]} == 2'h0; // @[Parameters.scala:137:{41,46,59}]
wire requestAIO_0_1 = {~(auto_anon_in_a_bits_address[28]), auto_anon_in_a_bits_address[18]} == 2'h0; // @[Parameters.scala:137:{31,41,46,59}]
wire [10:0] _requestAIO_T_10 = auto_anon_in_a_bits_address[28:18] ^ 11'h401; // @[Parameters.scala:137:31]
wire requestAIO_0_2 = {_requestAIO_T_10[10], _requestAIO_T_10[0]} == 2'h0; // @[Parameters.scala:137:{31,41,46,59}]
wire _portsAOI_in_0_a_ready_T_4 = requestAIO_0_0 & auto_anon_out_0_a_ready | requestAIO_0_1 & auto_anon_out_1_a_ready | requestAIO_0_2 & auto_anon_out_2_a_ready; // @[Mux.scala:30:73]
reg [2:0] beatsLeft; // @[Arbiter.scala:60:30]
wire idle = beatsLeft == 3'h0; // @[Arbiter.scala:60:30, :61:28]
wire [2:0] readys_valid = {auto_anon_out_2_d_valid, auto_anon_out_1_d_valid, auto_anon_out_0_d_valid}; // @[Arbiter.scala:68:51]
reg [2:0] readys_mask; // @[Arbiter.scala:23:23]
wire [2:0] _readys_filter_T_1 = readys_valid & ~readys_mask; // @[Arbiter.scala:23:23, :24:{28,30}, :68:51]
wire [3:0] _GEN = {_readys_filter_T_1[1:0], auto_anon_out_2_d_valid, auto_anon_out_1_d_valid} | {_readys_filter_T_1, auto_anon_out_2_d_valid}; // @[package.scala:262:{43,48}]
wire [2:0] readys_readys = ~({readys_mask[2], _readys_filter_T_1[2] | readys_mask[1], _GEN[3] | readys_mask[0]} & (_GEN[2:0] | {_readys_filter_T_1[2], _GEN[3:2]})); // @[package.scala:262:{43,48}]
wire winner_0 = readys_readys[0] & auto_anon_out_0_d_valid; // @[Arbiter.scala:26:18, :68:76, :71:69]
wire winner_1 = readys_readys[1] & auto_anon_out_1_d_valid; // @[Arbiter.scala:26:18, :68:76, :71:69]
wire winner_2 = readys_readys[2] & auto_anon_out_2_d_valid; // @[Arbiter.scala:26:18, :68:76, :71:69]
wire _in_0_d_valid_T = auto_anon_out_0_d_valid | auto_anon_out_1_d_valid; // @[Arbiter.scala:79:31] |
Generate the Verilog code corresponding to this FIRRTL code module PE_293 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>}
inst mac_unit of MacUnit_37
connect mac_unit.clock, clock
connect mac_unit.reset, reset
reg c1 : SInt<8>, clock
reg c2 : SInt<8>, clock
connect io.out_a, io.in_a
connect io.out_control.dataflow, io.in_control.dataflow
connect io.out_control.propagate, io.in_control.propagate
connect io.out_control.shift, io.in_control.shift
connect io.out_id, io.in_id
connect io.out_last, io.in_last
connect io.out_valid, io.in_valid
connect mac_unit.io.in_a, io.in_a
reg last_s : UInt<1>, clock
when io.in_valid :
connect last_s, io.in_control.propagate
node flip = neq(last_s, io.in_control.propagate)
node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0))
connect io.bad_dataflow, UInt<1>(0h0)
node _T = eq(io.in_control.dataflow, UInt<1>(0h0))
node _T_1 = and(UInt<1>(0h0), _T)
node _T_2 = or(UInt<1>(0h0), _T_1)
when _T_2 :
node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_3 :
node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1)
node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2)
node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0)
node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4)
node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_1 = asUInt(c1)
node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1)
node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3)
node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1))
node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1)
node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6)
node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7)
node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0))
node _io_out_c_ones_digit_T = dshr(c1, shift_offset)
node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0)
node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit)
node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T)
node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0)
node _io_out_c_T = dshr(c1, shift_offset)
node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1)
node _io_out_c_T_3 = tail(_io_out_c_T_2, 1)
node _io_out_c_T_4 = asSInt(_io_out_c_T_3)
node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4)
node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7)
node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0)
node _io_out_c_T_10 = asSInt(_io_out_c_T_9)
connect io.out_c, _io_out_c_T_10
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE : SInt<8>
node _mac_unit_io_in_b_T = asUInt(io.in_b)
node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T)
connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE
connect mac_unit.io.in_c, c2
connect c2, mac_unit.io.out_d
node _c1_T = bits(io.in_d, 7, 0)
node _c1_T_1 = asSInt(_c1_T)
connect c1, _c1_T_1
else :
node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1)
node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7)
node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0)
node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9)
node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_10 = asUInt(c2)
node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1)
node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12)
node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1))
node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1)
node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15)
node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16)
node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0))
node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset)
node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0)
node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1)
node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2)
node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0)
node _io_out_c_T_11 = dshr(c2, shift_offset)
node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12)
node _io_out_c_T_14 = tail(_io_out_c_T_13, 1)
node _io_out_c_T_15 = asSInt(_io_out_c_T_14)
node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15)
node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18)
node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0)
node _io_out_c_T_21 = asSInt(_io_out_c_T_20)
connect io.out_c, _io_out_c_T_21
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE_1 : SInt<8>
node _mac_unit_io_in_b_T_2 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2)
connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1
connect mac_unit.io.in_c, c1
connect c1, mac_unit.io.out_d
node _c2_T = bits(io.in_d, 7, 0)
node _c2_T_1 = asSInt(_c2_T)
connect c2, _c2_T_1
else :
node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1))
node _T_5 = and(UInt<1>(0h0), _T_4)
node _T_6 = or(UInt<1>(0h1), _T_5)
when _T_6 :
node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_7 :
connect io.out_c, c1
wire _mac_unit_io_in_b_WIRE_2 : SInt<8>
node _mac_unit_io_in_b_T_4 = asUInt(c2)
node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4)
connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c1, io.in_d
else :
connect io.out_c, c2
wire _mac_unit_io_in_b_WIRE_3 : SInt<8>
node _mac_unit_io_in_b_T_6 = asUInt(c1)
node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6)
connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c2, io.in_d
else :
connect io.bad_dataflow, UInt<1>(0h1)
invalidate io.out_c
invalidate io.out_b
wire _mac_unit_io_in_b_WIRE_4 : SInt<8>
node _mac_unit_io_in_b_T_8 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8)
connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4
connect mac_unit.io.in_c, c2
node _T_8 = eq(io.in_valid, UInt<1>(0h0))
when _T_8 :
connect c1, c1
connect c2, c2
invalidate mac_unit.io.in_b
invalidate mac_unit.io.in_c | module PE_293( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid // @[PE.scala:35:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7]
wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60]
wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [7:0] c1; // @[PE.scala:70:15]
wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [7:0] c2; // @[PE.scala:71:15]
wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25]
wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}]
wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16]
wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8]
c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15]
if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8]
c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15]
if (io_in_valid_0) // @[PE.scala:31:7]
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
always @(posedge)
MacUnit_37 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_b_0), // @[PE.scala:31:7]
.io_out_d (io_out_b_0)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MemoryBus :
output auto : { buffer_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, coupler_to_memory_controller_port_named_axi4_axi4yank_out : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { }}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { }, last : UInt<1>}}}, fixedClockNode_anon_out_1 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_0 : { clock : Clock, reset : Reset}, flip mbus_clock_groups_in : { member : { mbus_0 : { clock : Clock, reset : Reset}}}, flip bus_xing_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
output clock : Clock
output reset : Reset
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
inst mbus_clock_groups of ClockGroupAggregator_mbus
inst clockGroup of ClockGroup_4
inst fixedClockNode of FixedClockBroadcast_3_1
inst broadcast of BundleBridgeNexus_NoOutput_4
inst mbus_xbar of TLXbar_mbus_i1_o2_a32d64s4k1z3u
connect mbus_xbar.clock, childClock
connect mbus_xbar.reset, childReset
inst fixer of TLFIFOFixer_4
connect fixer.clock, childClock
connect fixer.reset, childReset
inst picker of ProbePicker
connect picker.clock, childClock
connect picker.reset, childReset
inst buffer of TLBuffer_a32d64s4k1z3u
connect buffer.clock, childClock
connect buffer.reset, childReset
inst coupler_to_memory_controller_port_named_tl_mem of TLInterconnectCoupler_mbus_to_memory_controller_port_named_tl_mem
connect coupler_to_memory_controller_port_named_tl_mem.clock, childClock
connect coupler_to_memory_controller_port_named_tl_mem.reset, childReset
inst xbar of TLXbar_i1_o1_a32d64s4k1z3u
connect xbar.clock, childClock
connect xbar.reset, childReset
inst coupler_to_memory_controller_port_named_axi4 of TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4
connect coupler_to_memory_controller_port_named_axi4.clock, childClock
connect coupler_to_memory_controller_port_named_axi4.reset, childReset
inst coupler_to_mbusscratchpad00 of TLInterconnectCoupler_mbus_to_mbusscratchpad00
connect coupler_to_mbusscratchpad00.clock, childClock
connect coupler_to_mbusscratchpad00.reset, childReset
inst buffer_1 of TLBuffer_a28d64s4k1z3u
connect buffer_1.clock, childClock
connect buffer_1.reset, childReset
wire clockSinkNodeIn : { clock : Clock, reset : Reset}
invalidate clockSinkNodeIn.reset
invalidate clockSinkNodeIn.clock
wire bus_xingOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate bus_xingOut.d.bits.corrupt
invalidate bus_xingOut.d.bits.data
invalidate bus_xingOut.d.bits.denied
invalidate bus_xingOut.d.bits.sink
invalidate bus_xingOut.d.bits.source
invalidate bus_xingOut.d.bits.size
invalidate bus_xingOut.d.bits.param
invalidate bus_xingOut.d.bits.opcode
invalidate bus_xingOut.d.valid
invalidate bus_xingOut.d.ready
invalidate bus_xingOut.a.bits.corrupt
invalidate bus_xingOut.a.bits.data
invalidate bus_xingOut.a.bits.mask
invalidate bus_xingOut.a.bits.address
invalidate bus_xingOut.a.bits.source
invalidate bus_xingOut.a.bits.size
invalidate bus_xingOut.a.bits.param
invalidate bus_xingOut.a.bits.opcode
invalidate bus_xingOut.a.valid
invalidate bus_xingOut.a.ready
wire bus_xingIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate bus_xingIn.d.bits.corrupt
invalidate bus_xingIn.d.bits.data
invalidate bus_xingIn.d.bits.denied
invalidate bus_xingIn.d.bits.sink
invalidate bus_xingIn.d.bits.source
invalidate bus_xingIn.d.bits.size
invalidate bus_xingIn.d.bits.param
invalidate bus_xingIn.d.bits.opcode
invalidate bus_xingIn.d.valid
invalidate bus_xingIn.d.ready
invalidate bus_xingIn.a.bits.corrupt
invalidate bus_xingIn.a.bits.data
invalidate bus_xingIn.a.bits.mask
invalidate bus_xingIn.a.bits.address
invalidate bus_xingIn.a.bits.source
invalidate bus_xingIn.a.bits.size
invalidate bus_xingIn.a.bits.param
invalidate bus_xingIn.a.bits.opcode
invalidate bus_xingIn.a.valid
invalidate bus_xingIn.a.ready
connect bus_xingOut, bus_xingIn
connect clockGroup.auto.in, mbus_clock_groups.auto.out
connect fixedClockNode.auto.anon_in, clockGroup.auto.out
connect clockSinkNodeIn, fixedClockNode.auto.anon_out_0
connect picker.auto.in_0, mbus_xbar.auto.anon_out_0
connect picker.auto.in_1, mbus_xbar.auto.anon_out_1
connect mbus_xbar.auto.anon_in, fixer.auto.anon_out
connect coupler_to_memory_controller_port_named_axi4.auto.tl_in, picker.auto.out_0
connect coupler_to_mbusscratchpad00.auto.tl_in, picker.auto.out_1
connect fixer.auto.anon_in, buffer.auto.out
connect buffer.auto.in, bus_xingOut
connect coupler_to_memory_controller_port_named_axi4.auto.widget_anon_in, xbar.auto.anon_out
connect xbar.auto.anon_in, coupler_to_memory_controller_port_named_axi4.auto.tl_out
connect buffer_1.auto.in, coupler_to_mbusscratchpad00.auto.tl_out
connect bus_xingIn, auto.bus_xing_in
connect mbus_clock_groups.auto.in, auto.mbus_clock_groups_in
connect auto.fixedClockNode_anon_out_0, fixedClockNode.auto.anon_out_1
connect auto.fixedClockNode_anon_out_1, fixedClockNode.auto.anon_out_2
connect coupler_to_memory_controller_port_named_axi4.auto.axi4yank_out.r, auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.r
connect auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.ar.bits, coupler_to_memory_controller_port_named_axi4.auto.axi4yank_out.ar.bits
connect auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.ar.valid, coupler_to_memory_controller_port_named_axi4.auto.axi4yank_out.ar.valid
connect coupler_to_memory_controller_port_named_axi4.auto.axi4yank_out.ar.ready, auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.ar.ready
connect coupler_to_memory_controller_port_named_axi4.auto.axi4yank_out.b, auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.b
connect auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.w.bits, coupler_to_memory_controller_port_named_axi4.auto.axi4yank_out.w.bits
connect auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.w.valid, coupler_to_memory_controller_port_named_axi4.auto.axi4yank_out.w.valid
connect coupler_to_memory_controller_port_named_axi4.auto.axi4yank_out.w.ready, auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.w.ready
connect auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.aw.bits, coupler_to_memory_controller_port_named_axi4.auto.axi4yank_out.aw.bits
connect auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.aw.valid, coupler_to_memory_controller_port_named_axi4.auto.axi4yank_out.aw.valid
connect coupler_to_memory_controller_port_named_axi4.auto.axi4yank_out.aw.ready, auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.aw.ready
connect buffer_1.auto.out.d, auto.buffer_out.d
connect auto.buffer_out.a.bits, buffer_1.auto.out.a.bits
connect auto.buffer_out.a.valid, buffer_1.auto.out.a.valid
connect buffer_1.auto.out.a.ready, auto.buffer_out.a.ready
connect childClock, clockSinkNodeIn.clock
connect childReset, clockSinkNodeIn.reset
connect clock, clockSinkNodeIn.clock
connect reset, clockSinkNodeIn.reset | module MemoryBus( // @[ClockDomain.scala:14:9]
input auto_buffer_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_buffer_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_buffer_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_buffer_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_buffer_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_buffer_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [27:0] auto_buffer_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_buffer_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_buffer_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_buffer_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_buffer_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_buffer_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_buffer_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_buffer_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_buffer_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_buffer_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_buffer_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_buffer_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_buffer_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_buffer_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_valid, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_id, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_addr, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_len, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_burst, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_lock, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_cache, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_prot, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_qos, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_valid, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_data, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_strb, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_last, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_valid, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_id, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_resp, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_valid, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_id, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_addr, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_len, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_burst, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_lock, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_cache, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_prot, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_qos, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_valid, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_id, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_data, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_resp, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_last, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_1_clock, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_0_clock, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_0_reset, // @[LazyModuleImp.scala:107:25]
input auto_mbus_clock_groups_in_member_mbus_0_clock, // @[LazyModuleImp.scala:107:25]
input auto_mbus_clock_groups_in_member_mbus_0_reset, // @[LazyModuleImp.scala:107:25]
output auto_bus_xing_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_bus_xing_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_bus_xing_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_bus_xing_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_bus_xing_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_bus_xing_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_bus_xing_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_bus_xing_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_bus_xing_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_bus_xing_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_bus_xing_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_bus_xing_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_bus_xing_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_bus_xing_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_bus_xing_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_bus_xing_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_bus_xing_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_bus_xing_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_bus_xing_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_bus_xing_in_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire _buffer_1_auto_in_a_ready; // @[Buffer.scala:75:28]
wire _buffer_1_auto_in_d_valid; // @[Buffer.scala:75:28]
wire [2:0] _buffer_1_auto_in_d_bits_opcode; // @[Buffer.scala:75:28]
wire [1:0] _buffer_1_auto_in_d_bits_param; // @[Buffer.scala:75:28]
wire [2:0] _buffer_1_auto_in_d_bits_size; // @[Buffer.scala:75:28]
wire [3:0] _buffer_1_auto_in_d_bits_source; // @[Buffer.scala:75:28]
wire _buffer_1_auto_in_d_bits_sink; // @[Buffer.scala:75:28]
wire _buffer_1_auto_in_d_bits_denied; // @[Buffer.scala:75:28]
wire [63:0] _buffer_1_auto_in_d_bits_data; // @[Buffer.scala:75:28]
wire _buffer_1_auto_in_d_bits_corrupt; // @[Buffer.scala:75:28]
wire _coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_a_ready; // @[LazyScope.scala:98:27]
wire _coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_valid; // @[LazyScope.scala:98:27]
wire [2:0] _coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_opcode; // @[LazyScope.scala:98:27]
wire [2:0] _coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_size; // @[LazyScope.scala:98:27]
wire [3:0] _coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_source; // @[LazyScope.scala:98:27]
wire _coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_denied; // @[LazyScope.scala:98:27]
wire [63:0] _coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_data; // @[LazyScope.scala:98:27]
wire _coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_corrupt; // @[LazyScope.scala:98:27]
wire _coupler_to_memory_controller_port_named_axi4_auto_tl_in_a_ready; // @[LazyScope.scala:98:27]
wire _coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_valid; // @[LazyScope.scala:98:27]
wire [2:0] _coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27]
wire [2:0] _coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27]
wire [3:0] _coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27]
wire _coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_denied; // @[LazyScope.scala:98:27]
wire [63:0] _coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27]
wire _coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_corrupt; // @[LazyScope.scala:98:27]
wire _coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_valid; // @[LazyScope.scala:98:27]
wire [2:0] _coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_opcode; // @[LazyScope.scala:98:27]
wire [2:0] _coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_param; // @[LazyScope.scala:98:27]
wire [2:0] _coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_size; // @[LazyScope.scala:98:27]
wire [3:0] _coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_source; // @[LazyScope.scala:98:27]
wire [31:0] _coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_address; // @[LazyScope.scala:98:27]
wire [7:0] _coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_mask; // @[LazyScope.scala:98:27]
wire [63:0] _coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_data; // @[LazyScope.scala:98:27]
wire _coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_corrupt; // @[LazyScope.scala:98:27]
wire _coupler_to_memory_controller_port_named_axi4_auto_tl_out_d_ready; // @[LazyScope.scala:98:27]
wire _picker_auto_in_1_a_ready; // @[ProbePicker.scala:69:28]
wire _picker_auto_in_1_d_valid; // @[ProbePicker.scala:69:28]
wire [2:0] _picker_auto_in_1_d_bits_opcode; // @[ProbePicker.scala:69:28]
wire [1:0] _picker_auto_in_1_d_bits_param; // @[ProbePicker.scala:69:28]
wire [2:0] _picker_auto_in_1_d_bits_size; // @[ProbePicker.scala:69:28]
wire [3:0] _picker_auto_in_1_d_bits_source; // @[ProbePicker.scala:69:28]
wire _picker_auto_in_1_d_bits_sink; // @[ProbePicker.scala:69:28]
wire _picker_auto_in_1_d_bits_denied; // @[ProbePicker.scala:69:28]
wire [63:0] _picker_auto_in_1_d_bits_data; // @[ProbePicker.scala:69:28]
wire _picker_auto_in_1_d_bits_corrupt; // @[ProbePicker.scala:69:28]
wire _picker_auto_in_0_a_ready; // @[ProbePicker.scala:69:28]
wire _picker_auto_in_0_d_valid; // @[ProbePicker.scala:69:28]
wire [2:0] _picker_auto_in_0_d_bits_opcode; // @[ProbePicker.scala:69:28]
wire [2:0] _picker_auto_in_0_d_bits_size; // @[ProbePicker.scala:69:28]
wire [3:0] _picker_auto_in_0_d_bits_source; // @[ProbePicker.scala:69:28]
wire _picker_auto_in_0_d_bits_denied; // @[ProbePicker.scala:69:28]
wire [63:0] _picker_auto_in_0_d_bits_data; // @[ProbePicker.scala:69:28]
wire _picker_auto_in_0_d_bits_corrupt; // @[ProbePicker.scala:69:28]
wire _picker_auto_out_1_a_valid; // @[ProbePicker.scala:69:28]
wire [2:0] _picker_auto_out_1_a_bits_opcode; // @[ProbePicker.scala:69:28]
wire [2:0] _picker_auto_out_1_a_bits_param; // @[ProbePicker.scala:69:28]
wire [2:0] _picker_auto_out_1_a_bits_size; // @[ProbePicker.scala:69:28]
wire [3:0] _picker_auto_out_1_a_bits_source; // @[ProbePicker.scala:69:28]
wire [27:0] _picker_auto_out_1_a_bits_address; // @[ProbePicker.scala:69:28]
wire [7:0] _picker_auto_out_1_a_bits_mask; // @[ProbePicker.scala:69:28]
wire [63:0] _picker_auto_out_1_a_bits_data; // @[ProbePicker.scala:69:28]
wire _picker_auto_out_1_a_bits_corrupt; // @[ProbePicker.scala:69:28]
wire _picker_auto_out_1_d_ready; // @[ProbePicker.scala:69:28]
wire _picker_auto_out_0_a_valid; // @[ProbePicker.scala:69:28]
wire [2:0] _picker_auto_out_0_a_bits_opcode; // @[ProbePicker.scala:69:28]
wire [2:0] _picker_auto_out_0_a_bits_param; // @[ProbePicker.scala:69:28]
wire [2:0] _picker_auto_out_0_a_bits_size; // @[ProbePicker.scala:69:28]
wire [3:0] _picker_auto_out_0_a_bits_source; // @[ProbePicker.scala:69:28]
wire [31:0] _picker_auto_out_0_a_bits_address; // @[ProbePicker.scala:69:28]
wire [7:0] _picker_auto_out_0_a_bits_mask; // @[ProbePicker.scala:69:28]
wire [63:0] _picker_auto_out_0_a_bits_data; // @[ProbePicker.scala:69:28]
wire _picker_auto_out_0_a_bits_corrupt; // @[ProbePicker.scala:69:28]
wire _picker_auto_out_0_d_ready; // @[ProbePicker.scala:69:28]
wire _mbus_xbar_auto_anon_out_1_a_valid; // @[MemoryBus.scala:47:32]
wire [2:0] _mbus_xbar_auto_anon_out_1_a_bits_opcode; // @[MemoryBus.scala:47:32]
wire [2:0] _mbus_xbar_auto_anon_out_1_a_bits_param; // @[MemoryBus.scala:47:32]
wire [2:0] _mbus_xbar_auto_anon_out_1_a_bits_size; // @[MemoryBus.scala:47:32]
wire [3:0] _mbus_xbar_auto_anon_out_1_a_bits_source; // @[MemoryBus.scala:47:32]
wire [27:0] _mbus_xbar_auto_anon_out_1_a_bits_address; // @[MemoryBus.scala:47:32]
wire [7:0] _mbus_xbar_auto_anon_out_1_a_bits_mask; // @[MemoryBus.scala:47:32]
wire [63:0] _mbus_xbar_auto_anon_out_1_a_bits_data; // @[MemoryBus.scala:47:32]
wire _mbus_xbar_auto_anon_out_1_a_bits_corrupt; // @[MemoryBus.scala:47:32]
wire _mbus_xbar_auto_anon_out_1_d_ready; // @[MemoryBus.scala:47:32]
wire _mbus_xbar_auto_anon_out_0_a_valid; // @[MemoryBus.scala:47:32]
wire [2:0] _mbus_xbar_auto_anon_out_0_a_bits_opcode; // @[MemoryBus.scala:47:32]
wire [2:0] _mbus_xbar_auto_anon_out_0_a_bits_param; // @[MemoryBus.scala:47:32]
wire [2:0] _mbus_xbar_auto_anon_out_0_a_bits_size; // @[MemoryBus.scala:47:32]
wire [3:0] _mbus_xbar_auto_anon_out_0_a_bits_source; // @[MemoryBus.scala:47:32]
wire [31:0] _mbus_xbar_auto_anon_out_0_a_bits_address; // @[MemoryBus.scala:47:32]
wire [7:0] _mbus_xbar_auto_anon_out_0_a_bits_mask; // @[MemoryBus.scala:47:32]
wire [63:0] _mbus_xbar_auto_anon_out_0_a_bits_data; // @[MemoryBus.scala:47:32]
wire _mbus_xbar_auto_anon_out_0_a_bits_corrupt; // @[MemoryBus.scala:47:32]
wire _mbus_xbar_auto_anon_out_0_d_ready; // @[MemoryBus.scala:47:32]
wire _fixedClockNode_auto_anon_out_0_clock; // @[ClockGroup.scala:115:114]
wire _fixedClockNode_auto_anon_out_0_reset; // @[ClockGroup.scala:115:114]
FixedClockBroadcast_3 fixedClockNode ( // @[ClockGroup.scala:115:114]
.auto_anon_in_clock (auto_mbus_clock_groups_in_member_mbus_0_clock),
.auto_anon_in_reset (auto_mbus_clock_groups_in_member_mbus_0_reset),
.auto_anon_out_2_clock (auto_fixedClockNode_anon_out_1_clock),
.auto_anon_out_2_reset (/* unused */),
.auto_anon_out_1_clock (auto_fixedClockNode_anon_out_0_clock),
.auto_anon_out_1_reset (auto_fixedClockNode_anon_out_0_reset),
.auto_anon_out_0_clock (_fixedClockNode_auto_anon_out_0_clock),
.auto_anon_out_0_reset (_fixedClockNode_auto_anon_out_0_reset)
); // @[ClockGroup.scala:115:114]
TLXbar_mbus_i1_o2_a32d64s4k1z3u mbus_xbar ( // @[MemoryBus.scala:47:32]
.clock (_fixedClockNode_auto_anon_out_0_clock), // @[ClockGroup.scala:115:114]
.reset (_fixedClockNode_auto_anon_out_0_reset), // @[ClockGroup.scala:115:114]
.auto_anon_in_a_ready (auto_bus_xing_in_a_ready),
.auto_anon_in_a_valid (auto_bus_xing_in_a_valid),
.auto_anon_in_a_bits_opcode (auto_bus_xing_in_a_bits_opcode),
.auto_anon_in_a_bits_param (auto_bus_xing_in_a_bits_param),
.auto_anon_in_a_bits_size (auto_bus_xing_in_a_bits_size),
.auto_anon_in_a_bits_source (auto_bus_xing_in_a_bits_source),
.auto_anon_in_a_bits_address (auto_bus_xing_in_a_bits_address),
.auto_anon_in_a_bits_mask (auto_bus_xing_in_a_bits_mask),
.auto_anon_in_a_bits_data (auto_bus_xing_in_a_bits_data),
.auto_anon_in_a_bits_corrupt (auto_bus_xing_in_a_bits_corrupt),
.auto_anon_in_d_ready (auto_bus_xing_in_d_ready),
.auto_anon_in_d_valid (auto_bus_xing_in_d_valid),
.auto_anon_in_d_bits_opcode (auto_bus_xing_in_d_bits_opcode),
.auto_anon_in_d_bits_param (auto_bus_xing_in_d_bits_param),
.auto_anon_in_d_bits_size (auto_bus_xing_in_d_bits_size),
.auto_anon_in_d_bits_source (auto_bus_xing_in_d_bits_source),
.auto_anon_in_d_bits_sink (auto_bus_xing_in_d_bits_sink),
.auto_anon_in_d_bits_denied (auto_bus_xing_in_d_bits_denied),
.auto_anon_in_d_bits_data (auto_bus_xing_in_d_bits_data),
.auto_anon_in_d_bits_corrupt (auto_bus_xing_in_d_bits_corrupt),
.auto_anon_out_1_a_ready (_picker_auto_in_1_a_ready), // @[ProbePicker.scala:69:28]
.auto_anon_out_1_a_valid (_mbus_xbar_auto_anon_out_1_a_valid),
.auto_anon_out_1_a_bits_opcode (_mbus_xbar_auto_anon_out_1_a_bits_opcode),
.auto_anon_out_1_a_bits_param (_mbus_xbar_auto_anon_out_1_a_bits_param),
.auto_anon_out_1_a_bits_size (_mbus_xbar_auto_anon_out_1_a_bits_size),
.auto_anon_out_1_a_bits_source (_mbus_xbar_auto_anon_out_1_a_bits_source),
.auto_anon_out_1_a_bits_address (_mbus_xbar_auto_anon_out_1_a_bits_address),
.auto_anon_out_1_a_bits_mask (_mbus_xbar_auto_anon_out_1_a_bits_mask),
.auto_anon_out_1_a_bits_data (_mbus_xbar_auto_anon_out_1_a_bits_data),
.auto_anon_out_1_a_bits_corrupt (_mbus_xbar_auto_anon_out_1_a_bits_corrupt),
.auto_anon_out_1_d_ready (_mbus_xbar_auto_anon_out_1_d_ready),
.auto_anon_out_1_d_valid (_picker_auto_in_1_d_valid), // @[ProbePicker.scala:69:28]
.auto_anon_out_1_d_bits_opcode (_picker_auto_in_1_d_bits_opcode), // @[ProbePicker.scala:69:28]
.auto_anon_out_1_d_bits_param (_picker_auto_in_1_d_bits_param), // @[ProbePicker.scala:69:28]
.auto_anon_out_1_d_bits_size (_picker_auto_in_1_d_bits_size), // @[ProbePicker.scala:69:28]
.auto_anon_out_1_d_bits_source (_picker_auto_in_1_d_bits_source), // @[ProbePicker.scala:69:28]
.auto_anon_out_1_d_bits_sink (_picker_auto_in_1_d_bits_sink), // @[ProbePicker.scala:69:28]
.auto_anon_out_1_d_bits_denied (_picker_auto_in_1_d_bits_denied), // @[ProbePicker.scala:69:28]
.auto_anon_out_1_d_bits_data (_picker_auto_in_1_d_bits_data), // @[ProbePicker.scala:69:28]
.auto_anon_out_1_d_bits_corrupt (_picker_auto_in_1_d_bits_corrupt), // @[ProbePicker.scala:69:28]
.auto_anon_out_0_a_ready (_picker_auto_in_0_a_ready), // @[ProbePicker.scala:69:28]
.auto_anon_out_0_a_valid (_mbus_xbar_auto_anon_out_0_a_valid),
.auto_anon_out_0_a_bits_opcode (_mbus_xbar_auto_anon_out_0_a_bits_opcode),
.auto_anon_out_0_a_bits_param (_mbus_xbar_auto_anon_out_0_a_bits_param),
.auto_anon_out_0_a_bits_size (_mbus_xbar_auto_anon_out_0_a_bits_size),
.auto_anon_out_0_a_bits_source (_mbus_xbar_auto_anon_out_0_a_bits_source),
.auto_anon_out_0_a_bits_address (_mbus_xbar_auto_anon_out_0_a_bits_address),
.auto_anon_out_0_a_bits_mask (_mbus_xbar_auto_anon_out_0_a_bits_mask),
.auto_anon_out_0_a_bits_data (_mbus_xbar_auto_anon_out_0_a_bits_data),
.auto_anon_out_0_a_bits_corrupt (_mbus_xbar_auto_anon_out_0_a_bits_corrupt),
.auto_anon_out_0_d_ready (_mbus_xbar_auto_anon_out_0_d_ready),
.auto_anon_out_0_d_valid (_picker_auto_in_0_d_valid), // @[ProbePicker.scala:69:28]
.auto_anon_out_0_d_bits_opcode (_picker_auto_in_0_d_bits_opcode), // @[ProbePicker.scala:69:28]
.auto_anon_out_0_d_bits_size (_picker_auto_in_0_d_bits_size), // @[ProbePicker.scala:69:28]
.auto_anon_out_0_d_bits_source (_picker_auto_in_0_d_bits_source), // @[ProbePicker.scala:69:28]
.auto_anon_out_0_d_bits_denied (_picker_auto_in_0_d_bits_denied), // @[ProbePicker.scala:69:28]
.auto_anon_out_0_d_bits_data (_picker_auto_in_0_d_bits_data), // @[ProbePicker.scala:69:28]
.auto_anon_out_0_d_bits_corrupt (_picker_auto_in_0_d_bits_corrupt) // @[ProbePicker.scala:69:28]
); // @[MemoryBus.scala:47:32]
ProbePicker picker ( // @[ProbePicker.scala:69:28]
.clock (_fixedClockNode_auto_anon_out_0_clock), // @[ClockGroup.scala:115:114]
.reset (_fixedClockNode_auto_anon_out_0_reset), // @[ClockGroup.scala:115:114]
.auto_in_1_a_ready (_picker_auto_in_1_a_ready),
.auto_in_1_a_valid (_mbus_xbar_auto_anon_out_1_a_valid), // @[MemoryBus.scala:47:32]
.auto_in_1_a_bits_opcode (_mbus_xbar_auto_anon_out_1_a_bits_opcode), // @[MemoryBus.scala:47:32]
.auto_in_1_a_bits_param (_mbus_xbar_auto_anon_out_1_a_bits_param), // @[MemoryBus.scala:47:32]
.auto_in_1_a_bits_size (_mbus_xbar_auto_anon_out_1_a_bits_size), // @[MemoryBus.scala:47:32]
.auto_in_1_a_bits_source (_mbus_xbar_auto_anon_out_1_a_bits_source), // @[MemoryBus.scala:47:32]
.auto_in_1_a_bits_address (_mbus_xbar_auto_anon_out_1_a_bits_address), // @[MemoryBus.scala:47:32]
.auto_in_1_a_bits_mask (_mbus_xbar_auto_anon_out_1_a_bits_mask), // @[MemoryBus.scala:47:32]
.auto_in_1_a_bits_data (_mbus_xbar_auto_anon_out_1_a_bits_data), // @[MemoryBus.scala:47:32]
.auto_in_1_a_bits_corrupt (_mbus_xbar_auto_anon_out_1_a_bits_corrupt), // @[MemoryBus.scala:47:32]
.auto_in_1_d_ready (_mbus_xbar_auto_anon_out_1_d_ready), // @[MemoryBus.scala:47:32]
.auto_in_1_d_valid (_picker_auto_in_1_d_valid),
.auto_in_1_d_bits_opcode (_picker_auto_in_1_d_bits_opcode),
.auto_in_1_d_bits_param (_picker_auto_in_1_d_bits_param),
.auto_in_1_d_bits_size (_picker_auto_in_1_d_bits_size),
.auto_in_1_d_bits_source (_picker_auto_in_1_d_bits_source),
.auto_in_1_d_bits_sink (_picker_auto_in_1_d_bits_sink),
.auto_in_1_d_bits_denied (_picker_auto_in_1_d_bits_denied),
.auto_in_1_d_bits_data (_picker_auto_in_1_d_bits_data),
.auto_in_1_d_bits_corrupt (_picker_auto_in_1_d_bits_corrupt),
.auto_in_0_a_ready (_picker_auto_in_0_a_ready),
.auto_in_0_a_valid (_mbus_xbar_auto_anon_out_0_a_valid), // @[MemoryBus.scala:47:32]
.auto_in_0_a_bits_opcode (_mbus_xbar_auto_anon_out_0_a_bits_opcode), // @[MemoryBus.scala:47:32]
.auto_in_0_a_bits_param (_mbus_xbar_auto_anon_out_0_a_bits_param), // @[MemoryBus.scala:47:32]
.auto_in_0_a_bits_size (_mbus_xbar_auto_anon_out_0_a_bits_size), // @[MemoryBus.scala:47:32]
.auto_in_0_a_bits_source (_mbus_xbar_auto_anon_out_0_a_bits_source), // @[MemoryBus.scala:47:32]
.auto_in_0_a_bits_address (_mbus_xbar_auto_anon_out_0_a_bits_address), // @[MemoryBus.scala:47:32]
.auto_in_0_a_bits_mask (_mbus_xbar_auto_anon_out_0_a_bits_mask), // @[MemoryBus.scala:47:32]
.auto_in_0_a_bits_data (_mbus_xbar_auto_anon_out_0_a_bits_data), // @[MemoryBus.scala:47:32]
.auto_in_0_a_bits_corrupt (_mbus_xbar_auto_anon_out_0_a_bits_corrupt), // @[MemoryBus.scala:47:32]
.auto_in_0_d_ready (_mbus_xbar_auto_anon_out_0_d_ready), // @[MemoryBus.scala:47:32]
.auto_in_0_d_valid (_picker_auto_in_0_d_valid),
.auto_in_0_d_bits_opcode (_picker_auto_in_0_d_bits_opcode),
.auto_in_0_d_bits_size (_picker_auto_in_0_d_bits_size),
.auto_in_0_d_bits_source (_picker_auto_in_0_d_bits_source),
.auto_in_0_d_bits_denied (_picker_auto_in_0_d_bits_denied),
.auto_in_0_d_bits_data (_picker_auto_in_0_d_bits_data),
.auto_in_0_d_bits_corrupt (_picker_auto_in_0_d_bits_corrupt),
.auto_out_1_a_ready (_buffer_1_auto_in_a_ready), // @[Buffer.scala:75:28]
.auto_out_1_a_valid (_picker_auto_out_1_a_valid),
.auto_out_1_a_bits_opcode (_picker_auto_out_1_a_bits_opcode),
.auto_out_1_a_bits_param (_picker_auto_out_1_a_bits_param),
.auto_out_1_a_bits_size (_picker_auto_out_1_a_bits_size),
.auto_out_1_a_bits_source (_picker_auto_out_1_a_bits_source),
.auto_out_1_a_bits_address (_picker_auto_out_1_a_bits_address),
.auto_out_1_a_bits_mask (_picker_auto_out_1_a_bits_mask),
.auto_out_1_a_bits_data (_picker_auto_out_1_a_bits_data),
.auto_out_1_a_bits_corrupt (_picker_auto_out_1_a_bits_corrupt),
.auto_out_1_d_ready (_picker_auto_out_1_d_ready),
.auto_out_1_d_valid (_buffer_1_auto_in_d_valid), // @[Buffer.scala:75:28]
.auto_out_1_d_bits_opcode (_buffer_1_auto_in_d_bits_opcode), // @[Buffer.scala:75:28]
.auto_out_1_d_bits_param (_buffer_1_auto_in_d_bits_param), // @[Buffer.scala:75:28]
.auto_out_1_d_bits_size (_buffer_1_auto_in_d_bits_size), // @[Buffer.scala:75:28]
.auto_out_1_d_bits_source (_buffer_1_auto_in_d_bits_source), // @[Buffer.scala:75:28]
.auto_out_1_d_bits_sink (_buffer_1_auto_in_d_bits_sink), // @[Buffer.scala:75:28]
.auto_out_1_d_bits_denied (_buffer_1_auto_in_d_bits_denied), // @[Buffer.scala:75:28]
.auto_out_1_d_bits_data (_buffer_1_auto_in_d_bits_data), // @[Buffer.scala:75:28]
.auto_out_1_d_bits_corrupt (_buffer_1_auto_in_d_bits_corrupt), // @[Buffer.scala:75:28]
.auto_out_0_a_ready (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_a_ready), // @[LazyScope.scala:98:27]
.auto_out_0_a_valid (_picker_auto_out_0_a_valid),
.auto_out_0_a_bits_opcode (_picker_auto_out_0_a_bits_opcode),
.auto_out_0_a_bits_param (_picker_auto_out_0_a_bits_param),
.auto_out_0_a_bits_size (_picker_auto_out_0_a_bits_size),
.auto_out_0_a_bits_source (_picker_auto_out_0_a_bits_source),
.auto_out_0_a_bits_address (_picker_auto_out_0_a_bits_address),
.auto_out_0_a_bits_mask (_picker_auto_out_0_a_bits_mask),
.auto_out_0_a_bits_data (_picker_auto_out_0_a_bits_data),
.auto_out_0_a_bits_corrupt (_picker_auto_out_0_a_bits_corrupt),
.auto_out_0_d_ready (_picker_auto_out_0_d_ready),
.auto_out_0_d_valid (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_valid), // @[LazyScope.scala:98:27]
.auto_out_0_d_bits_opcode (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_opcode), // @[LazyScope.scala:98:27]
.auto_out_0_d_bits_size (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27]
.auto_out_0_d_bits_source (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27]
.auto_out_0_d_bits_denied (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_denied), // @[LazyScope.scala:98:27]
.auto_out_0_d_bits_data (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_data), // @[LazyScope.scala:98:27]
.auto_out_0_d_bits_corrupt (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_corrupt) // @[LazyScope.scala:98:27]
); // @[ProbePicker.scala:69:28]
TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4 coupler_to_memory_controller_port_named_axi4 ( // @[LazyScope.scala:98:27]
.clock (_fixedClockNode_auto_anon_out_0_clock), // @[ClockGroup.scala:115:114]
.reset (_fixedClockNode_auto_anon_out_0_reset), // @[ClockGroup.scala:115:114]
.auto_widget_anon_in_a_ready (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_a_ready),
.auto_widget_anon_in_a_valid (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_valid), // @[LazyScope.scala:98:27]
.auto_widget_anon_in_a_bits_opcode (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_opcode), // @[LazyScope.scala:98:27]
.auto_widget_anon_in_a_bits_param (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_param), // @[LazyScope.scala:98:27]
.auto_widget_anon_in_a_bits_size (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_size), // @[LazyScope.scala:98:27]
.auto_widget_anon_in_a_bits_source (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_source), // @[LazyScope.scala:98:27]
.auto_widget_anon_in_a_bits_address (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_address), // @[LazyScope.scala:98:27]
.auto_widget_anon_in_a_bits_mask (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_mask), // @[LazyScope.scala:98:27]
.auto_widget_anon_in_a_bits_data (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_data), // @[LazyScope.scala:98:27]
.auto_widget_anon_in_a_bits_corrupt (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_corrupt), // @[LazyScope.scala:98:27]
.auto_widget_anon_in_d_ready (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_d_ready), // @[LazyScope.scala:98:27]
.auto_widget_anon_in_d_valid (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_valid),
.auto_widget_anon_in_d_bits_opcode (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_opcode),
.auto_widget_anon_in_d_bits_size (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_size),
.auto_widget_anon_in_d_bits_source (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_source),
.auto_widget_anon_in_d_bits_denied (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_denied),
.auto_widget_anon_in_d_bits_data (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_data),
.auto_widget_anon_in_d_bits_corrupt (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_corrupt),
.auto_axi4yank_out_aw_ready (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_ready),
.auto_axi4yank_out_aw_valid (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_valid),
.auto_axi4yank_out_aw_bits_id (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_id),
.auto_axi4yank_out_aw_bits_addr (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_addr),
.auto_axi4yank_out_aw_bits_len (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_len),
.auto_axi4yank_out_aw_bits_size (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_size),
.auto_axi4yank_out_aw_bits_burst (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_burst),
.auto_axi4yank_out_aw_bits_lock (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_lock),
.auto_axi4yank_out_aw_bits_cache (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_cache),
.auto_axi4yank_out_aw_bits_prot (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_prot),
.auto_axi4yank_out_aw_bits_qos (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_qos),
.auto_axi4yank_out_w_ready (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_ready),
.auto_axi4yank_out_w_valid (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_valid),
.auto_axi4yank_out_w_bits_data (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_data),
.auto_axi4yank_out_w_bits_strb (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_strb),
.auto_axi4yank_out_w_bits_last (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_last),
.auto_axi4yank_out_b_ready (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_ready),
.auto_axi4yank_out_b_valid (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_valid),
.auto_axi4yank_out_b_bits_id (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_id),
.auto_axi4yank_out_b_bits_resp (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_resp),
.auto_axi4yank_out_ar_ready (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_ready),
.auto_axi4yank_out_ar_valid (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_valid),
.auto_axi4yank_out_ar_bits_id (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_id),
.auto_axi4yank_out_ar_bits_addr (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_addr),
.auto_axi4yank_out_ar_bits_len (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_len),
.auto_axi4yank_out_ar_bits_size (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_size),
.auto_axi4yank_out_ar_bits_burst (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_burst),
.auto_axi4yank_out_ar_bits_lock (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_lock),
.auto_axi4yank_out_ar_bits_cache (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_cache),
.auto_axi4yank_out_ar_bits_prot (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_prot),
.auto_axi4yank_out_ar_bits_qos (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_qos),
.auto_axi4yank_out_r_ready (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_ready),
.auto_axi4yank_out_r_valid (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_valid),
.auto_axi4yank_out_r_bits_id (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_id),
.auto_axi4yank_out_r_bits_data (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_data),
.auto_axi4yank_out_r_bits_resp (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_resp),
.auto_axi4yank_out_r_bits_last (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_last),
.auto_tl_in_a_ready (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_a_ready),
.auto_tl_in_a_valid (_picker_auto_out_0_a_valid), // @[ProbePicker.scala:69:28]
.auto_tl_in_a_bits_opcode (_picker_auto_out_0_a_bits_opcode), // @[ProbePicker.scala:69:28]
.auto_tl_in_a_bits_param (_picker_auto_out_0_a_bits_param), // @[ProbePicker.scala:69:28]
.auto_tl_in_a_bits_size (_picker_auto_out_0_a_bits_size), // @[ProbePicker.scala:69:28]
.auto_tl_in_a_bits_source (_picker_auto_out_0_a_bits_source), // @[ProbePicker.scala:69:28]
.auto_tl_in_a_bits_address (_picker_auto_out_0_a_bits_address), // @[ProbePicker.scala:69:28]
.auto_tl_in_a_bits_mask (_picker_auto_out_0_a_bits_mask), // @[ProbePicker.scala:69:28]
.auto_tl_in_a_bits_data (_picker_auto_out_0_a_bits_data), // @[ProbePicker.scala:69:28]
.auto_tl_in_a_bits_corrupt (_picker_auto_out_0_a_bits_corrupt), // @[ProbePicker.scala:69:28]
.auto_tl_in_d_ready (_picker_auto_out_0_d_ready), // @[ProbePicker.scala:69:28]
.auto_tl_in_d_valid (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_valid),
.auto_tl_in_d_bits_opcode (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_opcode),
.auto_tl_in_d_bits_size (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_size),
.auto_tl_in_d_bits_source (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_source),
.auto_tl_in_d_bits_denied (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_denied),
.auto_tl_in_d_bits_data (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_data),
.auto_tl_in_d_bits_corrupt (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_corrupt),
.auto_tl_out_a_ready (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_a_ready), // @[LazyScope.scala:98:27]
.auto_tl_out_a_valid (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_valid),
.auto_tl_out_a_bits_opcode (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_opcode),
.auto_tl_out_a_bits_param (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_param),
.auto_tl_out_a_bits_size (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_size),
.auto_tl_out_a_bits_source (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_source),
.auto_tl_out_a_bits_address (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_address),
.auto_tl_out_a_bits_mask (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_mask),
.auto_tl_out_a_bits_data (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_data),
.auto_tl_out_a_bits_corrupt (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_corrupt),
.auto_tl_out_d_ready (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_d_ready),
.auto_tl_out_d_valid (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_valid), // @[LazyScope.scala:98:27]
.auto_tl_out_d_bits_opcode (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_opcode), // @[LazyScope.scala:98:27]
.auto_tl_out_d_bits_size (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_size), // @[LazyScope.scala:98:27]
.auto_tl_out_d_bits_source (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_source), // @[LazyScope.scala:98:27]
.auto_tl_out_d_bits_denied (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_denied), // @[LazyScope.scala:98:27]
.auto_tl_out_d_bits_data (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_data), // @[LazyScope.scala:98:27]
.auto_tl_out_d_bits_corrupt (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_corrupt) // @[LazyScope.scala:98:27]
); // @[LazyScope.scala:98:27]
TLBuffer_a28d64s4k1z3u buffer_1 ( // @[Buffer.scala:75:28]
.clock (_fixedClockNode_auto_anon_out_0_clock), // @[ClockGroup.scala:115:114]
.reset (_fixedClockNode_auto_anon_out_0_reset), // @[ClockGroup.scala:115:114]
.auto_in_a_ready (_buffer_1_auto_in_a_ready),
.auto_in_a_valid (_picker_auto_out_1_a_valid), // @[ProbePicker.scala:69:28]
.auto_in_a_bits_opcode (_picker_auto_out_1_a_bits_opcode), // @[ProbePicker.scala:69:28]
.auto_in_a_bits_param (_picker_auto_out_1_a_bits_param), // @[ProbePicker.scala:69:28]
.auto_in_a_bits_size (_picker_auto_out_1_a_bits_size), // @[ProbePicker.scala:69:28]
.auto_in_a_bits_source (_picker_auto_out_1_a_bits_source), // @[ProbePicker.scala:69:28]
.auto_in_a_bits_address (_picker_auto_out_1_a_bits_address), // @[ProbePicker.scala:69:28]
.auto_in_a_bits_mask (_picker_auto_out_1_a_bits_mask), // @[ProbePicker.scala:69:28]
.auto_in_a_bits_data (_picker_auto_out_1_a_bits_data), // @[ProbePicker.scala:69:28]
.auto_in_a_bits_corrupt (_picker_auto_out_1_a_bits_corrupt), // @[ProbePicker.scala:69:28]
.auto_in_d_ready (_picker_auto_out_1_d_ready), // @[ProbePicker.scala:69:28]
.auto_in_d_valid (_buffer_1_auto_in_d_valid),
.auto_in_d_bits_opcode (_buffer_1_auto_in_d_bits_opcode),
.auto_in_d_bits_param (_buffer_1_auto_in_d_bits_param),
.auto_in_d_bits_size (_buffer_1_auto_in_d_bits_size),
.auto_in_d_bits_source (_buffer_1_auto_in_d_bits_source),
.auto_in_d_bits_sink (_buffer_1_auto_in_d_bits_sink),
.auto_in_d_bits_denied (_buffer_1_auto_in_d_bits_denied),
.auto_in_d_bits_data (_buffer_1_auto_in_d_bits_data),
.auto_in_d_bits_corrupt (_buffer_1_auto_in_d_bits_corrupt),
.auto_out_a_ready (auto_buffer_out_a_ready),
.auto_out_a_valid (auto_buffer_out_a_valid),
.auto_out_a_bits_opcode (auto_buffer_out_a_bits_opcode),
.auto_out_a_bits_param (auto_buffer_out_a_bits_param),
.auto_out_a_bits_size (auto_buffer_out_a_bits_size),
.auto_out_a_bits_source (auto_buffer_out_a_bits_source),
.auto_out_a_bits_address (auto_buffer_out_a_bits_address),
.auto_out_a_bits_mask (auto_buffer_out_a_bits_mask),
.auto_out_a_bits_data (auto_buffer_out_a_bits_data),
.auto_out_a_bits_corrupt (auto_buffer_out_a_bits_corrupt),
.auto_out_d_ready (auto_buffer_out_d_ready),
.auto_out_d_valid (auto_buffer_out_d_valid),
.auto_out_d_bits_opcode (auto_buffer_out_d_bits_opcode),
.auto_out_d_bits_param (auto_buffer_out_d_bits_param),
.auto_out_d_bits_size (auto_buffer_out_d_bits_size),
.auto_out_d_bits_source (auto_buffer_out_d_bits_source),
.auto_out_d_bits_sink (auto_buffer_out_d_bits_sink),
.auto_out_d_bits_denied (auto_buffer_out_d_bits_denied),
.auto_out_d_bits_data (auto_buffer_out_d_bits_data),
.auto_out_d_bits_corrupt (auto_buffer_out_d_bits_corrupt)
); // @[Buffer.scala:75:28]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_34 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<6>(0h20))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 2, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 3)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<2>(0h2))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<3>(0h7))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 2, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 3)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<2>(0h3))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<3>(0h7))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<1>(0h0))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<1>(0h1))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0)
node _source_ok_T_25 = shr(io.in.a.bits.source, 2)
node _source_ok_T_26 = eq(_source_ok_T_25, UInt<2>(0h2))
node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27)
node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<2>(0h3))
node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29)
node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0)
node _source_ok_T_31 = shr(io.in.a.bits.source, 2)
node _source_ok_T_32 = eq(_source_ok_T_31, UInt<2>(0h3))
node _source_ok_T_33 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_34 = and(_source_ok_T_32, _source_ok_T_33)
node _source_ok_T_35 = leq(source_ok_uncommonBits_5, UInt<2>(0h3))
node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35)
node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<8>(0h80))
wire _source_ok_WIRE : UInt<1>[10]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_30
connect _source_ok_WIRE[6], _source_ok_T_36
connect _source_ok_WIRE[7], _source_ok_T_37
connect _source_ok_WIRE[8], _source_ok_T_38
connect _source_ok_WIRE[9], _source_ok_T_39
node _source_ok_T_40 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_41 = or(_source_ok_T_40, _source_ok_WIRE[2])
node _source_ok_T_42 = or(_source_ok_T_41, _source_ok_WIRE[3])
node _source_ok_T_43 = or(_source_ok_T_42, _source_ok_WIRE[4])
node _source_ok_T_44 = or(_source_ok_T_43, _source_ok_WIRE[5])
node _source_ok_T_45 = or(_source_ok_T_44, _source_ok_WIRE[6])
node _source_ok_T_46 = or(_source_ok_T_45, _source_ok_WIRE[7])
node _source_ok_T_47 = or(_source_ok_T_46, _source_ok_WIRE[8])
node source_ok = or(_source_ok_T_47, _source_ok_WIRE[9])
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits = bits(_uncommonBits_T, 2, 0)
node _T_12 = shr(io.in.a.bits.source, 3)
node _T_13 = eq(_T_12, UInt<2>(0h2))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<3>(0h7))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 2, 0)
node _T_25 = shr(io.in.a.bits.source, 3)
node _T_26 = eq(_T_25, UInt<2>(0h3))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<3>(0h7))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<1>(0h0))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<1>(0h1))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0)
node _T_64 = shr(io.in.a.bits.source, 2)
node _T_65 = eq(_T_64, UInt<2>(0h2))
node _T_66 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_67 = and(_T_65, _T_66)
node _T_68 = leq(uncommonBits_4, UInt<2>(0h3))
node _T_69 = and(_T_67, _T_68)
node _T_70 = eq(_T_69, UInt<1>(0h0))
node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_72 = cvt(_T_71)
node _T_73 = and(_T_72, asSInt(UInt<1>(0h0)))
node _T_74 = asSInt(_T_73)
node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0)))
node _T_76 = or(_T_70, _T_75)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_77 = shr(io.in.a.bits.source, 2)
node _T_78 = eq(_T_77, UInt<2>(0h3))
node _T_79 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_80 = and(_T_78, _T_79)
node _T_81 = leq(uncommonBits_5, UInt<2>(0h3))
node _T_82 = and(_T_80, _T_81)
node _T_83 = eq(_T_82, UInt<1>(0h0))
node _T_84 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_85 = cvt(_T_84)
node _T_86 = and(_T_85, asSInt(UInt<1>(0h0)))
node _T_87 = asSInt(_T_86)
node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0)))
node _T_89 = or(_T_83, _T_88)
node _T_90 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_91 = eq(_T_90, UInt<1>(0h0))
node _T_92 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_93 = cvt(_T_92)
node _T_94 = and(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = asSInt(_T_94)
node _T_96 = eq(_T_95, asSInt(UInt<1>(0h0)))
node _T_97 = or(_T_91, _T_96)
node _T_98 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_99 = eq(_T_98, UInt<1>(0h0))
node _T_100 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_101 = cvt(_T_100)
node _T_102 = and(_T_101, asSInt(UInt<1>(0h0)))
node _T_103 = asSInt(_T_102)
node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0)))
node _T_105 = or(_T_99, _T_104)
node _T_106 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_107 = eq(_T_106, UInt<1>(0h0))
node _T_108 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_109 = cvt(_T_108)
node _T_110 = and(_T_109, asSInt(UInt<1>(0h0)))
node _T_111 = asSInt(_T_110)
node _T_112 = eq(_T_111, asSInt(UInt<1>(0h0)))
node _T_113 = or(_T_107, _T_112)
node _T_114 = and(_T_11, _T_24)
node _T_115 = and(_T_114, _T_37)
node _T_116 = and(_T_115, _T_50)
node _T_117 = and(_T_116, _T_63)
node _T_118 = and(_T_117, _T_76)
node _T_119 = and(_T_118, _T_89)
node _T_120 = and(_T_119, _T_97)
node _T_121 = and(_T_120, _T_105)
node _T_122 = and(_T_121, _T_113)
node _T_123 = asUInt(reset)
node _T_124 = eq(_T_123, UInt<1>(0h0))
when _T_124 :
node _T_125 = eq(_T_122, UInt<1>(0h0))
when _T_125 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_122, UInt<1>(0h1), "") : assert_1
node _T_126 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_126 :
node _T_127 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_128 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_129 = and(_T_127, _T_128)
node _T_130 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 2, 0)
node _T_131 = shr(io.in.a.bits.source, 3)
node _T_132 = eq(_T_131, UInt<2>(0h2))
node _T_133 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_134 = and(_T_132, _T_133)
node _T_135 = leq(uncommonBits_6, UInt<3>(0h7))
node _T_136 = and(_T_134, _T_135)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 2, 0)
node _T_137 = shr(io.in.a.bits.source, 3)
node _T_138 = eq(_T_137, UInt<2>(0h3))
node _T_139 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_140 = and(_T_138, _T_139)
node _T_141 = leq(uncommonBits_7, UInt<3>(0h7))
node _T_142 = and(_T_140, _T_141)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_143 = shr(io.in.a.bits.source, 2)
node _T_144 = eq(_T_143, UInt<1>(0h0))
node _T_145 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_146 = and(_T_144, _T_145)
node _T_147 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_148 = and(_T_146, _T_147)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_149 = shr(io.in.a.bits.source, 2)
node _T_150 = eq(_T_149, UInt<1>(0h1))
node _T_151 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_152 = and(_T_150, _T_151)
node _T_153 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_154 = and(_T_152, _T_153)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_155 = shr(io.in.a.bits.source, 2)
node _T_156 = eq(_T_155, UInt<2>(0h2))
node _T_157 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_158 = and(_T_156, _T_157)
node _T_159 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_160 = and(_T_158, _T_159)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0)
node _T_161 = shr(io.in.a.bits.source, 2)
node _T_162 = eq(_T_161, UInt<2>(0h3))
node _T_163 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_164 = and(_T_162, _T_163)
node _T_165 = leq(uncommonBits_11, UInt<2>(0h3))
node _T_166 = and(_T_164, _T_165)
node _T_167 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_168 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_169 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_170 = or(_T_130, _T_136)
node _T_171 = or(_T_170, _T_142)
node _T_172 = or(_T_171, _T_148)
node _T_173 = or(_T_172, _T_154)
node _T_174 = or(_T_173, _T_160)
node _T_175 = or(_T_174, _T_166)
node _T_176 = or(_T_175, _T_167)
node _T_177 = or(_T_176, _T_168)
node _T_178 = or(_T_177, _T_169)
node _T_179 = and(_T_129, _T_178)
node _T_180 = or(UInt<1>(0h0), _T_179)
node _T_181 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_182 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_183 = cvt(_T_182)
node _T_184 = and(_T_183, asSInt(UInt<18>(0h2f000)))
node _T_185 = asSInt(_T_184)
node _T_186 = eq(_T_185, asSInt(UInt<1>(0h0)))
node _T_187 = and(_T_181, _T_186)
node _T_188 = or(UInt<1>(0h0), _T_187)
node _T_189 = and(_T_180, _T_188)
node _T_190 = asUInt(reset)
node _T_191 = eq(_T_190, UInt<1>(0h0))
when _T_191 :
node _T_192 = eq(_T_189, UInt<1>(0h0))
when _T_192 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_189, UInt<1>(0h1), "") : assert_2
node _T_193 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_194 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_195 = and(_T_193, _T_194)
node _T_196 = or(UInt<1>(0h0), _T_195)
node _T_197 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_198 = cvt(_T_197)
node _T_199 = and(_T_198, asSInt(UInt<18>(0h2f000)))
node _T_200 = asSInt(_T_199)
node _T_201 = eq(_T_200, asSInt(UInt<1>(0h0)))
node _T_202 = and(_T_196, _T_201)
node _T_203 = or(UInt<1>(0h0), _T_202)
node _T_204 = and(UInt<1>(0h0), _T_203)
node _T_205 = asUInt(reset)
node _T_206 = eq(_T_205, UInt<1>(0h0))
when _T_206 :
node _T_207 = eq(_T_204, UInt<1>(0h0))
when _T_207 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_204, UInt<1>(0h1), "") : assert_3
node _T_208 = asUInt(reset)
node _T_209 = eq(_T_208, UInt<1>(0h0))
when _T_209 :
node _T_210 = eq(source_ok, UInt<1>(0h0))
when _T_210 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_211 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_212 = asUInt(reset)
node _T_213 = eq(_T_212, UInt<1>(0h0))
when _T_213 :
node _T_214 = eq(_T_211, UInt<1>(0h0))
when _T_214 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_211, UInt<1>(0h1), "") : assert_5
node _T_215 = asUInt(reset)
node _T_216 = eq(_T_215, UInt<1>(0h0))
when _T_216 :
node _T_217 = eq(is_aligned, UInt<1>(0h0))
when _T_217 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_218 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_218, UInt<1>(0h1), "") : assert_7
node _T_222 = not(io.in.a.bits.mask)
node _T_223 = eq(_T_222, UInt<1>(0h0))
node _T_224 = asUInt(reset)
node _T_225 = eq(_T_224, UInt<1>(0h0))
when _T_225 :
node _T_226 = eq(_T_223, UInt<1>(0h0))
when _T_226 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_223, UInt<1>(0h1), "") : assert_8
node _T_227 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_228 = asUInt(reset)
node _T_229 = eq(_T_228, UInt<1>(0h0))
when _T_229 :
node _T_230 = eq(_T_227, UInt<1>(0h0))
when _T_230 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_227, UInt<1>(0h1), "") : assert_9
node _T_231 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_231 :
node _T_232 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_233 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_234 = and(_T_232, _T_233)
node _T_235 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 2, 0)
node _T_236 = shr(io.in.a.bits.source, 3)
node _T_237 = eq(_T_236, UInt<2>(0h2))
node _T_238 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_239 = and(_T_237, _T_238)
node _T_240 = leq(uncommonBits_12, UInt<3>(0h7))
node _T_241 = and(_T_239, _T_240)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 2, 0)
node _T_242 = shr(io.in.a.bits.source, 3)
node _T_243 = eq(_T_242, UInt<2>(0h3))
node _T_244 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_245 = and(_T_243, _T_244)
node _T_246 = leq(uncommonBits_13, UInt<3>(0h7))
node _T_247 = and(_T_245, _T_246)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_248 = shr(io.in.a.bits.source, 2)
node _T_249 = eq(_T_248, UInt<1>(0h0))
node _T_250 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_251 = and(_T_249, _T_250)
node _T_252 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_253 = and(_T_251, _T_252)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_254 = shr(io.in.a.bits.source, 2)
node _T_255 = eq(_T_254, UInt<1>(0h1))
node _T_256 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_257 = and(_T_255, _T_256)
node _T_258 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_259 = and(_T_257, _T_258)
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_260 = shr(io.in.a.bits.source, 2)
node _T_261 = eq(_T_260, UInt<2>(0h2))
node _T_262 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_263 = and(_T_261, _T_262)
node _T_264 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_265 = and(_T_263, _T_264)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_266 = shr(io.in.a.bits.source, 2)
node _T_267 = eq(_T_266, UInt<2>(0h3))
node _T_268 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_269 = and(_T_267, _T_268)
node _T_270 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_271 = and(_T_269, _T_270)
node _T_272 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_273 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_274 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_275 = or(_T_235, _T_241)
node _T_276 = or(_T_275, _T_247)
node _T_277 = or(_T_276, _T_253)
node _T_278 = or(_T_277, _T_259)
node _T_279 = or(_T_278, _T_265)
node _T_280 = or(_T_279, _T_271)
node _T_281 = or(_T_280, _T_272)
node _T_282 = or(_T_281, _T_273)
node _T_283 = or(_T_282, _T_274)
node _T_284 = and(_T_234, _T_283)
node _T_285 = or(UInt<1>(0h0), _T_284)
node _T_286 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_287 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_288 = cvt(_T_287)
node _T_289 = and(_T_288, asSInt(UInt<18>(0h2f000)))
node _T_290 = asSInt(_T_289)
node _T_291 = eq(_T_290, asSInt(UInt<1>(0h0)))
node _T_292 = and(_T_286, _T_291)
node _T_293 = or(UInt<1>(0h0), _T_292)
node _T_294 = and(_T_285, _T_293)
node _T_295 = asUInt(reset)
node _T_296 = eq(_T_295, UInt<1>(0h0))
when _T_296 :
node _T_297 = eq(_T_294, UInt<1>(0h0))
when _T_297 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_294, UInt<1>(0h1), "") : assert_10
node _T_298 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_299 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_300 = and(_T_298, _T_299)
node _T_301 = or(UInt<1>(0h0), _T_300)
node _T_302 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_303 = cvt(_T_302)
node _T_304 = and(_T_303, asSInt(UInt<18>(0h2f000)))
node _T_305 = asSInt(_T_304)
node _T_306 = eq(_T_305, asSInt(UInt<1>(0h0)))
node _T_307 = and(_T_301, _T_306)
node _T_308 = or(UInt<1>(0h0), _T_307)
node _T_309 = and(UInt<1>(0h0), _T_308)
node _T_310 = asUInt(reset)
node _T_311 = eq(_T_310, UInt<1>(0h0))
when _T_311 :
node _T_312 = eq(_T_309, UInt<1>(0h0))
when _T_312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_309, UInt<1>(0h1), "") : assert_11
node _T_313 = asUInt(reset)
node _T_314 = eq(_T_313, UInt<1>(0h0))
when _T_314 :
node _T_315 = eq(source_ok, UInt<1>(0h0))
when _T_315 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_316 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_317 = asUInt(reset)
node _T_318 = eq(_T_317, UInt<1>(0h0))
when _T_318 :
node _T_319 = eq(_T_316, UInt<1>(0h0))
when _T_319 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_316, UInt<1>(0h1), "") : assert_13
node _T_320 = asUInt(reset)
node _T_321 = eq(_T_320, UInt<1>(0h0))
when _T_321 :
node _T_322 = eq(is_aligned, UInt<1>(0h0))
when _T_322 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_323 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_324 = asUInt(reset)
node _T_325 = eq(_T_324, UInt<1>(0h0))
when _T_325 :
node _T_326 = eq(_T_323, UInt<1>(0h0))
when _T_326 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_323, UInt<1>(0h1), "") : assert_15
node _T_327 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_328 = asUInt(reset)
node _T_329 = eq(_T_328, UInt<1>(0h0))
when _T_329 :
node _T_330 = eq(_T_327, UInt<1>(0h0))
when _T_330 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_327, UInt<1>(0h1), "") : assert_16
node _T_331 = not(io.in.a.bits.mask)
node _T_332 = eq(_T_331, UInt<1>(0h0))
node _T_333 = asUInt(reset)
node _T_334 = eq(_T_333, UInt<1>(0h0))
when _T_334 :
node _T_335 = eq(_T_332, UInt<1>(0h0))
when _T_335 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_332, UInt<1>(0h1), "") : assert_17
node _T_336 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_337 = asUInt(reset)
node _T_338 = eq(_T_337, UInt<1>(0h0))
when _T_338 :
node _T_339 = eq(_T_336, UInt<1>(0h0))
when _T_339 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_336, UInt<1>(0h1), "") : assert_18
node _T_340 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_340 :
node _T_341 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_342 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_343 = and(_T_341, _T_342)
node _T_344 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 2, 0)
node _T_345 = shr(io.in.a.bits.source, 3)
node _T_346 = eq(_T_345, UInt<2>(0h2))
node _T_347 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_348 = and(_T_346, _T_347)
node _T_349 = leq(uncommonBits_18, UInt<3>(0h7))
node _T_350 = and(_T_348, _T_349)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 2, 0)
node _T_351 = shr(io.in.a.bits.source, 3)
node _T_352 = eq(_T_351, UInt<2>(0h3))
node _T_353 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_354 = and(_T_352, _T_353)
node _T_355 = leq(uncommonBits_19, UInt<3>(0h7))
node _T_356 = and(_T_354, _T_355)
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_357 = shr(io.in.a.bits.source, 2)
node _T_358 = eq(_T_357, UInt<1>(0h0))
node _T_359 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_360 = and(_T_358, _T_359)
node _T_361 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_362 = and(_T_360, _T_361)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_363 = shr(io.in.a.bits.source, 2)
node _T_364 = eq(_T_363, UInt<1>(0h1))
node _T_365 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_366 = and(_T_364, _T_365)
node _T_367 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_368 = and(_T_366, _T_367)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_369 = shr(io.in.a.bits.source, 2)
node _T_370 = eq(_T_369, UInt<2>(0h2))
node _T_371 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_372 = and(_T_370, _T_371)
node _T_373 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_374 = and(_T_372, _T_373)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_375 = shr(io.in.a.bits.source, 2)
node _T_376 = eq(_T_375, UInt<2>(0h3))
node _T_377 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_378 = and(_T_376, _T_377)
node _T_379 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_380 = and(_T_378, _T_379)
node _T_381 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_382 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_383 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_384 = or(_T_344, _T_350)
node _T_385 = or(_T_384, _T_356)
node _T_386 = or(_T_385, _T_362)
node _T_387 = or(_T_386, _T_368)
node _T_388 = or(_T_387, _T_374)
node _T_389 = or(_T_388, _T_380)
node _T_390 = or(_T_389, _T_381)
node _T_391 = or(_T_390, _T_382)
node _T_392 = or(_T_391, _T_383)
node _T_393 = and(_T_343, _T_392)
node _T_394 = or(UInt<1>(0h0), _T_393)
node _T_395 = asUInt(reset)
node _T_396 = eq(_T_395, UInt<1>(0h0))
when _T_396 :
node _T_397 = eq(_T_394, UInt<1>(0h0))
when _T_397 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_394, UInt<1>(0h1), "") : assert_19
node _T_398 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_399 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_400 = and(_T_398, _T_399)
node _T_401 = or(UInt<1>(0h0), _T_400)
node _T_402 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_403 = cvt(_T_402)
node _T_404 = and(_T_403, asSInt(UInt<18>(0h2f000)))
node _T_405 = asSInt(_T_404)
node _T_406 = eq(_T_405, asSInt(UInt<1>(0h0)))
node _T_407 = and(_T_401, _T_406)
node _T_408 = or(UInt<1>(0h0), _T_407)
node _T_409 = asUInt(reset)
node _T_410 = eq(_T_409, UInt<1>(0h0))
when _T_410 :
node _T_411 = eq(_T_408, UInt<1>(0h0))
when _T_411 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_408, UInt<1>(0h1), "") : assert_20
node _T_412 = asUInt(reset)
node _T_413 = eq(_T_412, UInt<1>(0h0))
when _T_413 :
node _T_414 = eq(source_ok, UInt<1>(0h0))
when _T_414 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_415 = asUInt(reset)
node _T_416 = eq(_T_415, UInt<1>(0h0))
when _T_416 :
node _T_417 = eq(is_aligned, UInt<1>(0h0))
when _T_417 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_418 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_419 = asUInt(reset)
node _T_420 = eq(_T_419, UInt<1>(0h0))
when _T_420 :
node _T_421 = eq(_T_418, UInt<1>(0h0))
when _T_421 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_418, UInt<1>(0h1), "") : assert_23
node _T_422 = eq(io.in.a.bits.mask, mask)
node _T_423 = asUInt(reset)
node _T_424 = eq(_T_423, UInt<1>(0h0))
when _T_424 :
node _T_425 = eq(_T_422, UInt<1>(0h0))
when _T_425 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_422, UInt<1>(0h1), "") : assert_24
node _T_426 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_427 = asUInt(reset)
node _T_428 = eq(_T_427, UInt<1>(0h0))
when _T_428 :
node _T_429 = eq(_T_426, UInt<1>(0h0))
when _T_429 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_426, UInt<1>(0h1), "") : assert_25
node _T_430 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_430 :
node _T_431 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_432 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_433 = and(_T_431, _T_432)
node _T_434 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 2, 0)
node _T_435 = shr(io.in.a.bits.source, 3)
node _T_436 = eq(_T_435, UInt<2>(0h2))
node _T_437 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_438 = and(_T_436, _T_437)
node _T_439 = leq(uncommonBits_24, UInt<3>(0h7))
node _T_440 = and(_T_438, _T_439)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 2, 0)
node _T_441 = shr(io.in.a.bits.source, 3)
node _T_442 = eq(_T_441, UInt<2>(0h3))
node _T_443 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_444 = and(_T_442, _T_443)
node _T_445 = leq(uncommonBits_25, UInt<3>(0h7))
node _T_446 = and(_T_444, _T_445)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_447 = shr(io.in.a.bits.source, 2)
node _T_448 = eq(_T_447, UInt<1>(0h0))
node _T_449 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_450 = and(_T_448, _T_449)
node _T_451 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_452 = and(_T_450, _T_451)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_453 = shr(io.in.a.bits.source, 2)
node _T_454 = eq(_T_453, UInt<1>(0h1))
node _T_455 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_456 = and(_T_454, _T_455)
node _T_457 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_458 = and(_T_456, _T_457)
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_459 = shr(io.in.a.bits.source, 2)
node _T_460 = eq(_T_459, UInt<2>(0h2))
node _T_461 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_462 = and(_T_460, _T_461)
node _T_463 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_464 = and(_T_462, _T_463)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0)
node _T_465 = shr(io.in.a.bits.source, 2)
node _T_466 = eq(_T_465, UInt<2>(0h3))
node _T_467 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_468 = and(_T_466, _T_467)
node _T_469 = leq(uncommonBits_29, UInt<2>(0h3))
node _T_470 = and(_T_468, _T_469)
node _T_471 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_472 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_473 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_474 = or(_T_434, _T_440)
node _T_475 = or(_T_474, _T_446)
node _T_476 = or(_T_475, _T_452)
node _T_477 = or(_T_476, _T_458)
node _T_478 = or(_T_477, _T_464)
node _T_479 = or(_T_478, _T_470)
node _T_480 = or(_T_479, _T_471)
node _T_481 = or(_T_480, _T_472)
node _T_482 = or(_T_481, _T_473)
node _T_483 = and(_T_433, _T_482)
node _T_484 = or(UInt<1>(0h0), _T_483)
node _T_485 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_486 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_487 = and(_T_485, _T_486)
node _T_488 = or(UInt<1>(0h0), _T_487)
node _T_489 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_490 = cvt(_T_489)
node _T_491 = and(_T_490, asSInt(UInt<18>(0h2f000)))
node _T_492 = asSInt(_T_491)
node _T_493 = eq(_T_492, asSInt(UInt<1>(0h0)))
node _T_494 = and(_T_488, _T_493)
node _T_495 = or(UInt<1>(0h0), _T_494)
node _T_496 = and(_T_484, _T_495)
node _T_497 = asUInt(reset)
node _T_498 = eq(_T_497, UInt<1>(0h0))
when _T_498 :
node _T_499 = eq(_T_496, UInt<1>(0h0))
when _T_499 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_496, UInt<1>(0h1), "") : assert_26
node _T_500 = asUInt(reset)
node _T_501 = eq(_T_500, UInt<1>(0h0))
when _T_501 :
node _T_502 = eq(source_ok, UInt<1>(0h0))
when _T_502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_503 = asUInt(reset)
node _T_504 = eq(_T_503, UInt<1>(0h0))
when _T_504 :
node _T_505 = eq(is_aligned, UInt<1>(0h0))
when _T_505 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_506 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_507 = asUInt(reset)
node _T_508 = eq(_T_507, UInt<1>(0h0))
when _T_508 :
node _T_509 = eq(_T_506, UInt<1>(0h0))
when _T_509 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_506, UInt<1>(0h1), "") : assert_29
node _T_510 = eq(io.in.a.bits.mask, mask)
node _T_511 = asUInt(reset)
node _T_512 = eq(_T_511, UInt<1>(0h0))
when _T_512 :
node _T_513 = eq(_T_510, UInt<1>(0h0))
when _T_513 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_510, UInt<1>(0h1), "") : assert_30
node _T_514 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_514 :
node _T_515 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_516 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_517 = and(_T_515, _T_516)
node _T_518 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 2, 0)
node _T_519 = shr(io.in.a.bits.source, 3)
node _T_520 = eq(_T_519, UInt<2>(0h2))
node _T_521 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_522 = and(_T_520, _T_521)
node _T_523 = leq(uncommonBits_30, UInt<3>(0h7))
node _T_524 = and(_T_522, _T_523)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 2, 0)
node _T_525 = shr(io.in.a.bits.source, 3)
node _T_526 = eq(_T_525, UInt<2>(0h3))
node _T_527 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_528 = and(_T_526, _T_527)
node _T_529 = leq(uncommonBits_31, UInt<3>(0h7))
node _T_530 = and(_T_528, _T_529)
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_531 = shr(io.in.a.bits.source, 2)
node _T_532 = eq(_T_531, UInt<1>(0h0))
node _T_533 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_534 = and(_T_532, _T_533)
node _T_535 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_536 = and(_T_534, _T_535)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_537 = shr(io.in.a.bits.source, 2)
node _T_538 = eq(_T_537, UInt<1>(0h1))
node _T_539 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_540 = and(_T_538, _T_539)
node _T_541 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_542 = and(_T_540, _T_541)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0)
node _T_543 = shr(io.in.a.bits.source, 2)
node _T_544 = eq(_T_543, UInt<2>(0h2))
node _T_545 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_546 = and(_T_544, _T_545)
node _T_547 = leq(uncommonBits_34, UInt<2>(0h3))
node _T_548 = and(_T_546, _T_547)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_549 = shr(io.in.a.bits.source, 2)
node _T_550 = eq(_T_549, UInt<2>(0h3))
node _T_551 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_552 = and(_T_550, _T_551)
node _T_553 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_554 = and(_T_552, _T_553)
node _T_555 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_556 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_557 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_558 = or(_T_518, _T_524)
node _T_559 = or(_T_558, _T_530)
node _T_560 = or(_T_559, _T_536)
node _T_561 = or(_T_560, _T_542)
node _T_562 = or(_T_561, _T_548)
node _T_563 = or(_T_562, _T_554)
node _T_564 = or(_T_563, _T_555)
node _T_565 = or(_T_564, _T_556)
node _T_566 = or(_T_565, _T_557)
node _T_567 = and(_T_517, _T_566)
node _T_568 = or(UInt<1>(0h0), _T_567)
node _T_569 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_570 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_571 = and(_T_569, _T_570)
node _T_572 = or(UInt<1>(0h0), _T_571)
node _T_573 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_574 = cvt(_T_573)
node _T_575 = and(_T_574, asSInt(UInt<18>(0h2f000)))
node _T_576 = asSInt(_T_575)
node _T_577 = eq(_T_576, asSInt(UInt<1>(0h0)))
node _T_578 = and(_T_572, _T_577)
node _T_579 = or(UInt<1>(0h0), _T_578)
node _T_580 = and(_T_568, _T_579)
node _T_581 = asUInt(reset)
node _T_582 = eq(_T_581, UInt<1>(0h0))
when _T_582 :
node _T_583 = eq(_T_580, UInt<1>(0h0))
when _T_583 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_580, UInt<1>(0h1), "") : assert_31
node _T_584 = asUInt(reset)
node _T_585 = eq(_T_584, UInt<1>(0h0))
when _T_585 :
node _T_586 = eq(source_ok, UInt<1>(0h0))
when _T_586 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_587 = asUInt(reset)
node _T_588 = eq(_T_587, UInt<1>(0h0))
when _T_588 :
node _T_589 = eq(is_aligned, UInt<1>(0h0))
when _T_589 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_590 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_591 = asUInt(reset)
node _T_592 = eq(_T_591, UInt<1>(0h0))
when _T_592 :
node _T_593 = eq(_T_590, UInt<1>(0h0))
when _T_593 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_590, UInt<1>(0h1), "") : assert_34
node _T_594 = not(mask)
node _T_595 = and(io.in.a.bits.mask, _T_594)
node _T_596 = eq(_T_595, UInt<1>(0h0))
node _T_597 = asUInt(reset)
node _T_598 = eq(_T_597, UInt<1>(0h0))
when _T_598 :
node _T_599 = eq(_T_596, UInt<1>(0h0))
when _T_599 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_596, UInt<1>(0h1), "") : assert_35
node _T_600 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_600 :
node _T_601 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_602 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_603 = and(_T_601, _T_602)
node _T_604 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 2, 0)
node _T_605 = shr(io.in.a.bits.source, 3)
node _T_606 = eq(_T_605, UInt<2>(0h2))
node _T_607 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_608 = and(_T_606, _T_607)
node _T_609 = leq(uncommonBits_36, UInt<3>(0h7))
node _T_610 = and(_T_608, _T_609)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 2, 0)
node _T_611 = shr(io.in.a.bits.source, 3)
node _T_612 = eq(_T_611, UInt<2>(0h3))
node _T_613 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_614 = and(_T_612, _T_613)
node _T_615 = leq(uncommonBits_37, UInt<3>(0h7))
node _T_616 = and(_T_614, _T_615)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_617 = shr(io.in.a.bits.source, 2)
node _T_618 = eq(_T_617, UInt<1>(0h0))
node _T_619 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_620 = and(_T_618, _T_619)
node _T_621 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_622 = and(_T_620, _T_621)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0)
node _T_623 = shr(io.in.a.bits.source, 2)
node _T_624 = eq(_T_623, UInt<1>(0h1))
node _T_625 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_626 = and(_T_624, _T_625)
node _T_627 = leq(uncommonBits_39, UInt<2>(0h3))
node _T_628 = and(_T_626, _T_627)
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0)
node _T_629 = shr(io.in.a.bits.source, 2)
node _T_630 = eq(_T_629, UInt<2>(0h2))
node _T_631 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_632 = and(_T_630, _T_631)
node _T_633 = leq(uncommonBits_40, UInt<2>(0h3))
node _T_634 = and(_T_632, _T_633)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0)
node _T_635 = shr(io.in.a.bits.source, 2)
node _T_636 = eq(_T_635, UInt<2>(0h3))
node _T_637 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_638 = and(_T_636, _T_637)
node _T_639 = leq(uncommonBits_41, UInt<2>(0h3))
node _T_640 = and(_T_638, _T_639)
node _T_641 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_642 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_643 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_644 = or(_T_604, _T_610)
node _T_645 = or(_T_644, _T_616)
node _T_646 = or(_T_645, _T_622)
node _T_647 = or(_T_646, _T_628)
node _T_648 = or(_T_647, _T_634)
node _T_649 = or(_T_648, _T_640)
node _T_650 = or(_T_649, _T_641)
node _T_651 = or(_T_650, _T_642)
node _T_652 = or(_T_651, _T_643)
node _T_653 = and(_T_603, _T_652)
node _T_654 = or(UInt<1>(0h0), _T_653)
node _T_655 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_656 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_657 = cvt(_T_656)
node _T_658 = and(_T_657, asSInt(UInt<18>(0h2f000)))
node _T_659 = asSInt(_T_658)
node _T_660 = eq(_T_659, asSInt(UInt<1>(0h0)))
node _T_661 = and(_T_655, _T_660)
node _T_662 = or(UInt<1>(0h0), _T_661)
node _T_663 = and(_T_654, _T_662)
node _T_664 = asUInt(reset)
node _T_665 = eq(_T_664, UInt<1>(0h0))
when _T_665 :
node _T_666 = eq(_T_663, UInt<1>(0h0))
when _T_666 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_663, UInt<1>(0h1), "") : assert_36
node _T_667 = asUInt(reset)
node _T_668 = eq(_T_667, UInt<1>(0h0))
when _T_668 :
node _T_669 = eq(source_ok, UInt<1>(0h0))
when _T_669 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_670 = asUInt(reset)
node _T_671 = eq(_T_670, UInt<1>(0h0))
when _T_671 :
node _T_672 = eq(is_aligned, UInt<1>(0h0))
when _T_672 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_673 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_674 = asUInt(reset)
node _T_675 = eq(_T_674, UInt<1>(0h0))
when _T_675 :
node _T_676 = eq(_T_673, UInt<1>(0h0))
when _T_676 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_673, UInt<1>(0h1), "") : assert_39
node _T_677 = eq(io.in.a.bits.mask, mask)
node _T_678 = asUInt(reset)
node _T_679 = eq(_T_678, UInt<1>(0h0))
when _T_679 :
node _T_680 = eq(_T_677, UInt<1>(0h0))
when _T_680 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_677, UInt<1>(0h1), "") : assert_40
node _T_681 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_681 :
node _T_682 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_683 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_684 = and(_T_682, _T_683)
node _T_685 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 2, 0)
node _T_686 = shr(io.in.a.bits.source, 3)
node _T_687 = eq(_T_686, UInt<2>(0h2))
node _T_688 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_689 = and(_T_687, _T_688)
node _T_690 = leq(uncommonBits_42, UInt<3>(0h7))
node _T_691 = and(_T_689, _T_690)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 2, 0)
node _T_692 = shr(io.in.a.bits.source, 3)
node _T_693 = eq(_T_692, UInt<2>(0h3))
node _T_694 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_695 = and(_T_693, _T_694)
node _T_696 = leq(uncommonBits_43, UInt<3>(0h7))
node _T_697 = and(_T_695, _T_696)
node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0)
node _T_698 = shr(io.in.a.bits.source, 2)
node _T_699 = eq(_T_698, UInt<1>(0h0))
node _T_700 = leq(UInt<1>(0h0), uncommonBits_44)
node _T_701 = and(_T_699, _T_700)
node _T_702 = leq(uncommonBits_44, UInt<2>(0h3))
node _T_703 = and(_T_701, _T_702)
node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0)
node _T_704 = shr(io.in.a.bits.source, 2)
node _T_705 = eq(_T_704, UInt<1>(0h1))
node _T_706 = leq(UInt<1>(0h0), uncommonBits_45)
node _T_707 = and(_T_705, _T_706)
node _T_708 = leq(uncommonBits_45, UInt<2>(0h3))
node _T_709 = and(_T_707, _T_708)
node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_46 = bits(_uncommonBits_T_46, 1, 0)
node _T_710 = shr(io.in.a.bits.source, 2)
node _T_711 = eq(_T_710, UInt<2>(0h2))
node _T_712 = leq(UInt<1>(0h0), uncommonBits_46)
node _T_713 = and(_T_711, _T_712)
node _T_714 = leq(uncommonBits_46, UInt<2>(0h3))
node _T_715 = and(_T_713, _T_714)
node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_47 = bits(_uncommonBits_T_47, 1, 0)
node _T_716 = shr(io.in.a.bits.source, 2)
node _T_717 = eq(_T_716, UInt<2>(0h3))
node _T_718 = leq(UInt<1>(0h0), uncommonBits_47)
node _T_719 = and(_T_717, _T_718)
node _T_720 = leq(uncommonBits_47, UInt<2>(0h3))
node _T_721 = and(_T_719, _T_720)
node _T_722 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_723 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_724 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_725 = or(_T_685, _T_691)
node _T_726 = or(_T_725, _T_697)
node _T_727 = or(_T_726, _T_703)
node _T_728 = or(_T_727, _T_709)
node _T_729 = or(_T_728, _T_715)
node _T_730 = or(_T_729, _T_721)
node _T_731 = or(_T_730, _T_722)
node _T_732 = or(_T_731, _T_723)
node _T_733 = or(_T_732, _T_724)
node _T_734 = and(_T_684, _T_733)
node _T_735 = or(UInt<1>(0h0), _T_734)
node _T_736 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_737 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_738 = cvt(_T_737)
node _T_739 = and(_T_738, asSInt(UInt<18>(0h2f000)))
node _T_740 = asSInt(_T_739)
node _T_741 = eq(_T_740, asSInt(UInt<1>(0h0)))
node _T_742 = and(_T_736, _T_741)
node _T_743 = or(UInt<1>(0h0), _T_742)
node _T_744 = and(_T_735, _T_743)
node _T_745 = asUInt(reset)
node _T_746 = eq(_T_745, UInt<1>(0h0))
when _T_746 :
node _T_747 = eq(_T_744, UInt<1>(0h0))
when _T_747 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_744, UInt<1>(0h1), "") : assert_41
node _T_748 = asUInt(reset)
node _T_749 = eq(_T_748, UInt<1>(0h0))
when _T_749 :
node _T_750 = eq(source_ok, UInt<1>(0h0))
when _T_750 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_751 = asUInt(reset)
node _T_752 = eq(_T_751, UInt<1>(0h0))
when _T_752 :
node _T_753 = eq(is_aligned, UInt<1>(0h0))
when _T_753 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_754 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_755 = asUInt(reset)
node _T_756 = eq(_T_755, UInt<1>(0h0))
when _T_756 :
node _T_757 = eq(_T_754, UInt<1>(0h0))
when _T_757 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_754, UInt<1>(0h1), "") : assert_44
node _T_758 = eq(io.in.a.bits.mask, mask)
node _T_759 = asUInt(reset)
node _T_760 = eq(_T_759, UInt<1>(0h0))
when _T_760 :
node _T_761 = eq(_T_758, UInt<1>(0h0))
when _T_761 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_758, UInt<1>(0h1), "") : assert_45
node _T_762 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_762 :
node _T_763 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_764 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_765 = and(_T_763, _T_764)
node _T_766 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_48 = bits(_uncommonBits_T_48, 2, 0)
node _T_767 = shr(io.in.a.bits.source, 3)
node _T_768 = eq(_T_767, UInt<2>(0h2))
node _T_769 = leq(UInt<1>(0h0), uncommonBits_48)
node _T_770 = and(_T_768, _T_769)
node _T_771 = leq(uncommonBits_48, UInt<3>(0h7))
node _T_772 = and(_T_770, _T_771)
node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_49 = bits(_uncommonBits_T_49, 2, 0)
node _T_773 = shr(io.in.a.bits.source, 3)
node _T_774 = eq(_T_773, UInt<2>(0h3))
node _T_775 = leq(UInt<1>(0h0), uncommonBits_49)
node _T_776 = and(_T_774, _T_775)
node _T_777 = leq(uncommonBits_49, UInt<3>(0h7))
node _T_778 = and(_T_776, _T_777)
node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0)
node _T_779 = shr(io.in.a.bits.source, 2)
node _T_780 = eq(_T_779, UInt<1>(0h0))
node _T_781 = leq(UInt<1>(0h0), uncommonBits_50)
node _T_782 = and(_T_780, _T_781)
node _T_783 = leq(uncommonBits_50, UInt<2>(0h3))
node _T_784 = and(_T_782, _T_783)
node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0)
node _T_785 = shr(io.in.a.bits.source, 2)
node _T_786 = eq(_T_785, UInt<1>(0h1))
node _T_787 = leq(UInt<1>(0h0), uncommonBits_51)
node _T_788 = and(_T_786, _T_787)
node _T_789 = leq(uncommonBits_51, UInt<2>(0h3))
node _T_790 = and(_T_788, _T_789)
node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0)
node _T_791 = shr(io.in.a.bits.source, 2)
node _T_792 = eq(_T_791, UInt<2>(0h2))
node _T_793 = leq(UInt<1>(0h0), uncommonBits_52)
node _T_794 = and(_T_792, _T_793)
node _T_795 = leq(uncommonBits_52, UInt<2>(0h3))
node _T_796 = and(_T_794, _T_795)
node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_53 = bits(_uncommonBits_T_53, 1, 0)
node _T_797 = shr(io.in.a.bits.source, 2)
node _T_798 = eq(_T_797, UInt<2>(0h3))
node _T_799 = leq(UInt<1>(0h0), uncommonBits_53)
node _T_800 = and(_T_798, _T_799)
node _T_801 = leq(uncommonBits_53, UInt<2>(0h3))
node _T_802 = and(_T_800, _T_801)
node _T_803 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_804 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_805 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_806 = or(_T_766, _T_772)
node _T_807 = or(_T_806, _T_778)
node _T_808 = or(_T_807, _T_784)
node _T_809 = or(_T_808, _T_790)
node _T_810 = or(_T_809, _T_796)
node _T_811 = or(_T_810, _T_802)
node _T_812 = or(_T_811, _T_803)
node _T_813 = or(_T_812, _T_804)
node _T_814 = or(_T_813, _T_805)
node _T_815 = and(_T_765, _T_814)
node _T_816 = or(UInt<1>(0h0), _T_815)
node _T_817 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_818 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_819 = cvt(_T_818)
node _T_820 = and(_T_819, asSInt(UInt<18>(0h2f000)))
node _T_821 = asSInt(_T_820)
node _T_822 = eq(_T_821, asSInt(UInt<1>(0h0)))
node _T_823 = and(_T_817, _T_822)
node _T_824 = or(UInt<1>(0h0), _T_823)
node _T_825 = and(_T_816, _T_824)
node _T_826 = asUInt(reset)
node _T_827 = eq(_T_826, UInt<1>(0h0))
when _T_827 :
node _T_828 = eq(_T_825, UInt<1>(0h0))
when _T_828 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_825, UInt<1>(0h1), "") : assert_46
node _T_829 = asUInt(reset)
node _T_830 = eq(_T_829, UInt<1>(0h0))
when _T_830 :
node _T_831 = eq(source_ok, UInt<1>(0h0))
when _T_831 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_832 = asUInt(reset)
node _T_833 = eq(_T_832, UInt<1>(0h0))
when _T_833 :
node _T_834 = eq(is_aligned, UInt<1>(0h0))
when _T_834 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_835 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_836 = asUInt(reset)
node _T_837 = eq(_T_836, UInt<1>(0h0))
when _T_837 :
node _T_838 = eq(_T_835, UInt<1>(0h0))
when _T_838 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_835, UInt<1>(0h1), "") : assert_49
node _T_839 = eq(io.in.a.bits.mask, mask)
node _T_840 = asUInt(reset)
node _T_841 = eq(_T_840, UInt<1>(0h0))
when _T_841 :
node _T_842 = eq(_T_839, UInt<1>(0h0))
when _T_842 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_839, UInt<1>(0h1), "") : assert_50
node _T_843 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_844 = asUInt(reset)
node _T_845 = eq(_T_844, UInt<1>(0h0))
when _T_845 :
node _T_846 = eq(_T_843, UInt<1>(0h0))
when _T_846 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_843, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_847 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_848 = asUInt(reset)
node _T_849 = eq(_T_848, UInt<1>(0h0))
when _T_849 :
node _T_850 = eq(_T_847, UInt<1>(0h0))
when _T_850 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_847, UInt<1>(0h1), "") : assert_52
node _source_ok_T_48 = eq(io.in.d.bits.source, UInt<6>(0h20))
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 2, 0)
node _source_ok_T_49 = shr(io.in.d.bits.source, 3)
node _source_ok_T_50 = eq(_source_ok_T_49, UInt<2>(0h2))
node _source_ok_T_51 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51)
node _source_ok_T_53 = leq(source_ok_uncommonBits_6, UInt<3>(0h7))
node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 2, 0)
node _source_ok_T_55 = shr(io.in.d.bits.source, 3)
node _source_ok_T_56 = eq(_source_ok_T_55, UInt<2>(0h3))
node _source_ok_T_57 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57)
node _source_ok_T_59 = leq(source_ok_uncommonBits_7, UInt<3>(0h7))
node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59)
node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0)
node _source_ok_T_61 = shr(io.in.d.bits.source, 2)
node _source_ok_T_62 = eq(_source_ok_T_61, UInt<1>(0h0))
node _source_ok_T_63 = leq(UInt<1>(0h0), source_ok_uncommonBits_8)
node _source_ok_T_64 = and(_source_ok_T_62, _source_ok_T_63)
node _source_ok_T_65 = leq(source_ok_uncommonBits_8, UInt<2>(0h3))
node _source_ok_T_66 = and(_source_ok_T_64, _source_ok_T_65)
node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0)
node _source_ok_T_67 = shr(io.in.d.bits.source, 2)
node _source_ok_T_68 = eq(_source_ok_T_67, UInt<1>(0h1))
node _source_ok_T_69 = leq(UInt<1>(0h0), source_ok_uncommonBits_9)
node _source_ok_T_70 = and(_source_ok_T_68, _source_ok_T_69)
node _source_ok_T_71 = leq(source_ok_uncommonBits_9, UInt<2>(0h3))
node _source_ok_T_72 = and(_source_ok_T_70, _source_ok_T_71)
node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 1, 0)
node _source_ok_T_73 = shr(io.in.d.bits.source, 2)
node _source_ok_T_74 = eq(_source_ok_T_73, UInt<2>(0h2))
node _source_ok_T_75 = leq(UInt<1>(0h0), source_ok_uncommonBits_10)
node _source_ok_T_76 = and(_source_ok_T_74, _source_ok_T_75)
node _source_ok_T_77 = leq(source_ok_uncommonBits_10, UInt<2>(0h3))
node _source_ok_T_78 = and(_source_ok_T_76, _source_ok_T_77)
node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 1, 0)
node _source_ok_T_79 = shr(io.in.d.bits.source, 2)
node _source_ok_T_80 = eq(_source_ok_T_79, UInt<2>(0h3))
node _source_ok_T_81 = leq(UInt<1>(0h0), source_ok_uncommonBits_11)
node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81)
node _source_ok_T_83 = leq(source_ok_uncommonBits_11, UInt<2>(0h3))
node _source_ok_T_84 = and(_source_ok_T_82, _source_ok_T_83)
node _source_ok_T_85 = eq(io.in.d.bits.source, UInt<7>(0h41))
node _source_ok_T_86 = eq(io.in.d.bits.source, UInt<7>(0h40))
node _source_ok_T_87 = eq(io.in.d.bits.source, UInt<8>(0h80))
wire _source_ok_WIRE_1 : UInt<1>[10]
connect _source_ok_WIRE_1[0], _source_ok_T_48
connect _source_ok_WIRE_1[1], _source_ok_T_54
connect _source_ok_WIRE_1[2], _source_ok_T_60
connect _source_ok_WIRE_1[3], _source_ok_T_66
connect _source_ok_WIRE_1[4], _source_ok_T_72
connect _source_ok_WIRE_1[5], _source_ok_T_78
connect _source_ok_WIRE_1[6], _source_ok_T_84
connect _source_ok_WIRE_1[7], _source_ok_T_85
connect _source_ok_WIRE_1[8], _source_ok_T_86
connect _source_ok_WIRE_1[9], _source_ok_T_87
node _source_ok_T_88 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_89 = or(_source_ok_T_88, _source_ok_WIRE_1[2])
node _source_ok_T_90 = or(_source_ok_T_89, _source_ok_WIRE_1[3])
node _source_ok_T_91 = or(_source_ok_T_90, _source_ok_WIRE_1[4])
node _source_ok_T_92 = or(_source_ok_T_91, _source_ok_WIRE_1[5])
node _source_ok_T_93 = or(_source_ok_T_92, _source_ok_WIRE_1[6])
node _source_ok_T_94 = or(_source_ok_T_93, _source_ok_WIRE_1[7])
node _source_ok_T_95 = or(_source_ok_T_94, _source_ok_WIRE_1[8])
node source_ok_1 = or(_source_ok_T_95, _source_ok_WIRE_1[9])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_851 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_851 :
node _T_852 = asUInt(reset)
node _T_853 = eq(_T_852, UInt<1>(0h0))
when _T_853 :
node _T_854 = eq(source_ok_1, UInt<1>(0h0))
when _T_854 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_855 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_856 = asUInt(reset)
node _T_857 = eq(_T_856, UInt<1>(0h0))
when _T_857 :
node _T_858 = eq(_T_855, UInt<1>(0h0))
when _T_858 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_855, UInt<1>(0h1), "") : assert_54
node _T_859 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_860 = asUInt(reset)
node _T_861 = eq(_T_860, UInt<1>(0h0))
when _T_861 :
node _T_862 = eq(_T_859, UInt<1>(0h0))
when _T_862 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_859, UInt<1>(0h1), "") : assert_55
node _T_863 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_864 = asUInt(reset)
node _T_865 = eq(_T_864, UInt<1>(0h0))
when _T_865 :
node _T_866 = eq(_T_863, UInt<1>(0h0))
when _T_866 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_863, UInt<1>(0h1), "") : assert_56
node _T_867 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_868 = asUInt(reset)
node _T_869 = eq(_T_868, UInt<1>(0h0))
when _T_869 :
node _T_870 = eq(_T_867, UInt<1>(0h0))
when _T_870 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_867, UInt<1>(0h1), "") : assert_57
node _T_871 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_871 :
node _T_872 = asUInt(reset)
node _T_873 = eq(_T_872, UInt<1>(0h0))
when _T_873 :
node _T_874 = eq(source_ok_1, UInt<1>(0h0))
when _T_874 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_875 = asUInt(reset)
node _T_876 = eq(_T_875, UInt<1>(0h0))
when _T_876 :
node _T_877 = eq(sink_ok, UInt<1>(0h0))
when _T_877 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_878 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_879 = asUInt(reset)
node _T_880 = eq(_T_879, UInt<1>(0h0))
when _T_880 :
node _T_881 = eq(_T_878, UInt<1>(0h0))
when _T_881 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_878, UInt<1>(0h1), "") : assert_60
node _T_882 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_883 = asUInt(reset)
node _T_884 = eq(_T_883, UInt<1>(0h0))
when _T_884 :
node _T_885 = eq(_T_882, UInt<1>(0h0))
when _T_885 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_882, UInt<1>(0h1), "") : assert_61
node _T_886 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_887 = asUInt(reset)
node _T_888 = eq(_T_887, UInt<1>(0h0))
when _T_888 :
node _T_889 = eq(_T_886, UInt<1>(0h0))
when _T_889 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_886, UInt<1>(0h1), "") : assert_62
node _T_890 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_891 = asUInt(reset)
node _T_892 = eq(_T_891, UInt<1>(0h0))
when _T_892 :
node _T_893 = eq(_T_890, UInt<1>(0h0))
when _T_893 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_890, UInt<1>(0h1), "") : assert_63
node _T_894 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_895 = or(UInt<1>(0h0), _T_894)
node _T_896 = asUInt(reset)
node _T_897 = eq(_T_896, UInt<1>(0h0))
when _T_897 :
node _T_898 = eq(_T_895, UInt<1>(0h0))
when _T_898 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_895, UInt<1>(0h1), "") : assert_64
node _T_899 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_899 :
node _T_900 = asUInt(reset)
node _T_901 = eq(_T_900, UInt<1>(0h0))
when _T_901 :
node _T_902 = eq(source_ok_1, UInt<1>(0h0))
when _T_902 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_903 = asUInt(reset)
node _T_904 = eq(_T_903, UInt<1>(0h0))
when _T_904 :
node _T_905 = eq(sink_ok, UInt<1>(0h0))
when _T_905 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_906 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_907 = asUInt(reset)
node _T_908 = eq(_T_907, UInt<1>(0h0))
when _T_908 :
node _T_909 = eq(_T_906, UInt<1>(0h0))
when _T_909 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_906, UInt<1>(0h1), "") : assert_67
node _T_910 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_911 = asUInt(reset)
node _T_912 = eq(_T_911, UInt<1>(0h0))
when _T_912 :
node _T_913 = eq(_T_910, UInt<1>(0h0))
when _T_913 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_910, UInt<1>(0h1), "") : assert_68
node _T_914 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_915 = asUInt(reset)
node _T_916 = eq(_T_915, UInt<1>(0h0))
when _T_916 :
node _T_917 = eq(_T_914, UInt<1>(0h0))
when _T_917 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_914, UInt<1>(0h1), "") : assert_69
node _T_918 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_919 = or(_T_918, io.in.d.bits.corrupt)
node _T_920 = asUInt(reset)
node _T_921 = eq(_T_920, UInt<1>(0h0))
when _T_921 :
node _T_922 = eq(_T_919, UInt<1>(0h0))
when _T_922 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_919, UInt<1>(0h1), "") : assert_70
node _T_923 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_924 = or(UInt<1>(0h0), _T_923)
node _T_925 = asUInt(reset)
node _T_926 = eq(_T_925, UInt<1>(0h0))
when _T_926 :
node _T_927 = eq(_T_924, UInt<1>(0h0))
when _T_927 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_924, UInt<1>(0h1), "") : assert_71
node _T_928 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_928 :
node _T_929 = asUInt(reset)
node _T_930 = eq(_T_929, UInt<1>(0h0))
when _T_930 :
node _T_931 = eq(source_ok_1, UInt<1>(0h0))
when _T_931 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_932 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_933 = asUInt(reset)
node _T_934 = eq(_T_933, UInt<1>(0h0))
when _T_934 :
node _T_935 = eq(_T_932, UInt<1>(0h0))
when _T_935 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_932, UInt<1>(0h1), "") : assert_73
node _T_936 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_937 = asUInt(reset)
node _T_938 = eq(_T_937, UInt<1>(0h0))
when _T_938 :
node _T_939 = eq(_T_936, UInt<1>(0h0))
when _T_939 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_936, UInt<1>(0h1), "") : assert_74
node _T_940 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_941 = or(UInt<1>(0h0), _T_940)
node _T_942 = asUInt(reset)
node _T_943 = eq(_T_942, UInt<1>(0h0))
when _T_943 :
node _T_944 = eq(_T_941, UInt<1>(0h0))
when _T_944 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_941, UInt<1>(0h1), "") : assert_75
node _T_945 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_945 :
node _T_946 = asUInt(reset)
node _T_947 = eq(_T_946, UInt<1>(0h0))
when _T_947 :
node _T_948 = eq(source_ok_1, UInt<1>(0h0))
when _T_948 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_949 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_950 = asUInt(reset)
node _T_951 = eq(_T_950, UInt<1>(0h0))
when _T_951 :
node _T_952 = eq(_T_949, UInt<1>(0h0))
when _T_952 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_949, UInt<1>(0h1), "") : assert_77
node _T_953 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_954 = or(_T_953, io.in.d.bits.corrupt)
node _T_955 = asUInt(reset)
node _T_956 = eq(_T_955, UInt<1>(0h0))
when _T_956 :
node _T_957 = eq(_T_954, UInt<1>(0h0))
when _T_957 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_954, UInt<1>(0h1), "") : assert_78
node _T_958 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_959 = or(UInt<1>(0h0), _T_958)
node _T_960 = asUInt(reset)
node _T_961 = eq(_T_960, UInt<1>(0h0))
when _T_961 :
node _T_962 = eq(_T_959, UInt<1>(0h0))
when _T_962 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_959, UInt<1>(0h1), "") : assert_79
node _T_963 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_963 :
node _T_964 = asUInt(reset)
node _T_965 = eq(_T_964, UInt<1>(0h0))
when _T_965 :
node _T_966 = eq(source_ok_1, UInt<1>(0h0))
when _T_966 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_967 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_968 = asUInt(reset)
node _T_969 = eq(_T_968, UInt<1>(0h0))
when _T_969 :
node _T_970 = eq(_T_967, UInt<1>(0h0))
when _T_970 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_967, UInt<1>(0h1), "") : assert_81
node _T_971 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_972 = asUInt(reset)
node _T_973 = eq(_T_972, UInt<1>(0h0))
when _T_973 :
node _T_974 = eq(_T_971, UInt<1>(0h0))
when _T_974 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_971, UInt<1>(0h1), "") : assert_82
node _T_975 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_976 = or(UInt<1>(0h0), _T_975)
node _T_977 = asUInt(reset)
node _T_978 = eq(_T_977, UInt<1>(0h0))
when _T_978 :
node _T_979 = eq(_T_976, UInt<1>(0h0))
when _T_979 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_976, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<21>(0h0)
connect _WIRE.bits.source, UInt<8>(0h0)
connect _WIRE.bits.size, UInt<3>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_980 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_981 = asUInt(reset)
node _T_982 = eq(_T_981, UInt<1>(0h0))
when _T_982 :
node _T_983 = eq(_T_980, UInt<1>(0h0))
when _T_983 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_980, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<21>(0h0)
connect _WIRE_2.bits.source, UInt<8>(0h0)
connect _WIRE_2.bits.size, UInt<3>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_984 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_985 = asUInt(reset)
node _T_986 = eq(_T_985, UInt<1>(0h0))
when _T_986 :
node _T_987 = eq(_T_984, UInt<1>(0h0))
when _T_987 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_984, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_988 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_989 = asUInt(reset)
node _T_990 = eq(_T_989, UInt<1>(0h0))
when _T_990 :
node _T_991 = eq(_T_988, UInt<1>(0h0))
when _T_991 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_988, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_992 = eq(a_first, UInt<1>(0h0))
node _T_993 = and(io.in.a.valid, _T_992)
when _T_993 :
node _T_994 = eq(io.in.a.bits.opcode, opcode)
node _T_995 = asUInt(reset)
node _T_996 = eq(_T_995, UInt<1>(0h0))
when _T_996 :
node _T_997 = eq(_T_994, UInt<1>(0h0))
when _T_997 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_994, UInt<1>(0h1), "") : assert_87
node _T_998 = eq(io.in.a.bits.param, param)
node _T_999 = asUInt(reset)
node _T_1000 = eq(_T_999, UInt<1>(0h0))
when _T_1000 :
node _T_1001 = eq(_T_998, UInt<1>(0h0))
when _T_1001 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_998, UInt<1>(0h1), "") : assert_88
node _T_1002 = eq(io.in.a.bits.size, size)
node _T_1003 = asUInt(reset)
node _T_1004 = eq(_T_1003, UInt<1>(0h0))
when _T_1004 :
node _T_1005 = eq(_T_1002, UInt<1>(0h0))
when _T_1005 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1002, UInt<1>(0h1), "") : assert_89
node _T_1006 = eq(io.in.a.bits.source, source)
node _T_1007 = asUInt(reset)
node _T_1008 = eq(_T_1007, UInt<1>(0h0))
when _T_1008 :
node _T_1009 = eq(_T_1006, UInt<1>(0h0))
when _T_1009 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1006, UInt<1>(0h1), "") : assert_90
node _T_1010 = eq(io.in.a.bits.address, address)
node _T_1011 = asUInt(reset)
node _T_1012 = eq(_T_1011, UInt<1>(0h0))
when _T_1012 :
node _T_1013 = eq(_T_1010, UInt<1>(0h0))
when _T_1013 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1010, UInt<1>(0h1), "") : assert_91
node _T_1014 = and(io.in.a.ready, io.in.a.valid)
node _T_1015 = and(_T_1014, a_first)
when _T_1015 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1016 = eq(d_first, UInt<1>(0h0))
node _T_1017 = and(io.in.d.valid, _T_1016)
when _T_1017 :
node _T_1018 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1019 = asUInt(reset)
node _T_1020 = eq(_T_1019, UInt<1>(0h0))
when _T_1020 :
node _T_1021 = eq(_T_1018, UInt<1>(0h0))
when _T_1021 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1018, UInt<1>(0h1), "") : assert_92
node _T_1022 = eq(io.in.d.bits.param, param_1)
node _T_1023 = asUInt(reset)
node _T_1024 = eq(_T_1023, UInt<1>(0h0))
when _T_1024 :
node _T_1025 = eq(_T_1022, UInt<1>(0h0))
when _T_1025 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1022, UInt<1>(0h1), "") : assert_93
node _T_1026 = eq(io.in.d.bits.size, size_1)
node _T_1027 = asUInt(reset)
node _T_1028 = eq(_T_1027, UInt<1>(0h0))
when _T_1028 :
node _T_1029 = eq(_T_1026, UInt<1>(0h0))
when _T_1029 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1026, UInt<1>(0h1), "") : assert_94
node _T_1030 = eq(io.in.d.bits.source, source_1)
node _T_1031 = asUInt(reset)
node _T_1032 = eq(_T_1031, UInt<1>(0h0))
when _T_1032 :
node _T_1033 = eq(_T_1030, UInt<1>(0h0))
when _T_1033 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1030, UInt<1>(0h1), "") : assert_95
node _T_1034 = eq(io.in.d.bits.sink, sink)
node _T_1035 = asUInt(reset)
node _T_1036 = eq(_T_1035, UInt<1>(0h0))
when _T_1036 :
node _T_1037 = eq(_T_1034, UInt<1>(0h0))
when _T_1037 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1034, UInt<1>(0h1), "") : assert_96
node _T_1038 = eq(io.in.d.bits.denied, denied)
node _T_1039 = asUInt(reset)
node _T_1040 = eq(_T_1039, UInt<1>(0h0))
when _T_1040 :
node _T_1041 = eq(_T_1038, UInt<1>(0h0))
when _T_1041 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1038, UInt<1>(0h1), "") : assert_97
node _T_1042 = and(io.in.d.ready, io.in.d.valid)
node _T_1043 = and(_T_1042, d_first)
when _T_1043 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<129>, clock, reset, UInt<129>(0h0)
regreset inflight_opcodes : UInt<516>, clock, reset, UInt<516>(0h0)
regreset inflight_sizes : UInt<516>, clock, reset, UInt<516>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<129>
connect a_set, UInt<129>(0h0)
wire a_set_wo_ready : UInt<129>
connect a_set_wo_ready, UInt<129>(0h0)
wire a_opcodes_set : UInt<516>
connect a_opcodes_set, UInt<516>(0h0)
wire a_sizes_set : UInt<516>
connect a_sizes_set, UInt<516>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_1044 = and(io.in.a.valid, a_first_1)
node _T_1045 = and(_T_1044, UInt<1>(0h1))
when _T_1045 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1046 = and(io.in.a.ready, io.in.a.valid)
node _T_1047 = and(_T_1046, a_first_1)
node _T_1048 = and(_T_1047, UInt<1>(0h1))
when _T_1048 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1049 = dshr(inflight, io.in.a.bits.source)
node _T_1050 = bits(_T_1049, 0, 0)
node _T_1051 = eq(_T_1050, UInt<1>(0h0))
node _T_1052 = asUInt(reset)
node _T_1053 = eq(_T_1052, UInt<1>(0h0))
when _T_1053 :
node _T_1054 = eq(_T_1051, UInt<1>(0h0))
when _T_1054 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1051, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<129>
connect d_clr, UInt<129>(0h0)
wire d_clr_wo_ready : UInt<129>
connect d_clr_wo_ready, UInt<129>(0h0)
wire d_opcodes_clr : UInt<516>
connect d_opcodes_clr, UInt<516>(0h0)
wire d_sizes_clr : UInt<516>
connect d_sizes_clr, UInt<516>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1055 = and(io.in.d.valid, d_first_1)
node _T_1056 = and(_T_1055, UInt<1>(0h1))
node _T_1057 = eq(d_release_ack, UInt<1>(0h0))
node _T_1058 = and(_T_1056, _T_1057)
when _T_1058 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1059 = and(io.in.d.ready, io.in.d.valid)
node _T_1060 = and(_T_1059, d_first_1)
node _T_1061 = and(_T_1060, UInt<1>(0h1))
node _T_1062 = eq(d_release_ack, UInt<1>(0h0))
node _T_1063 = and(_T_1061, _T_1062)
when _T_1063 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1064 = and(io.in.d.valid, d_first_1)
node _T_1065 = and(_T_1064, UInt<1>(0h1))
node _T_1066 = eq(d_release_ack, UInt<1>(0h0))
node _T_1067 = and(_T_1065, _T_1066)
when _T_1067 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1068 = dshr(inflight, io.in.d.bits.source)
node _T_1069 = bits(_T_1068, 0, 0)
node _T_1070 = or(_T_1069, same_cycle_resp)
node _T_1071 = asUInt(reset)
node _T_1072 = eq(_T_1071, UInt<1>(0h0))
when _T_1072 :
node _T_1073 = eq(_T_1070, UInt<1>(0h0))
when _T_1073 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1070, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1074 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1075 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1076 = or(_T_1074, _T_1075)
node _T_1077 = asUInt(reset)
node _T_1078 = eq(_T_1077, UInt<1>(0h0))
when _T_1078 :
node _T_1079 = eq(_T_1076, UInt<1>(0h0))
when _T_1079 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1076, UInt<1>(0h1), "") : assert_100
node _T_1080 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1081 = asUInt(reset)
node _T_1082 = eq(_T_1081, UInt<1>(0h0))
when _T_1082 :
node _T_1083 = eq(_T_1080, UInt<1>(0h0))
when _T_1083 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1080, UInt<1>(0h1), "") : assert_101
else :
node _T_1084 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1085 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1086 = or(_T_1084, _T_1085)
node _T_1087 = asUInt(reset)
node _T_1088 = eq(_T_1087, UInt<1>(0h0))
when _T_1088 :
node _T_1089 = eq(_T_1086, UInt<1>(0h0))
when _T_1089 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1086, UInt<1>(0h1), "") : assert_102
node _T_1090 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1091 = asUInt(reset)
node _T_1092 = eq(_T_1091, UInt<1>(0h0))
when _T_1092 :
node _T_1093 = eq(_T_1090, UInt<1>(0h0))
when _T_1093 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1090, UInt<1>(0h1), "") : assert_103
node _T_1094 = and(io.in.d.valid, d_first_1)
node _T_1095 = and(_T_1094, a_first_1)
node _T_1096 = and(_T_1095, io.in.a.valid)
node _T_1097 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1098 = and(_T_1096, _T_1097)
node _T_1099 = eq(d_release_ack, UInt<1>(0h0))
node _T_1100 = and(_T_1098, _T_1099)
when _T_1100 :
node _T_1101 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1102 = or(_T_1101, io.in.a.ready)
node _T_1103 = asUInt(reset)
node _T_1104 = eq(_T_1103, UInt<1>(0h0))
when _T_1104 :
node _T_1105 = eq(_T_1102, UInt<1>(0h0))
when _T_1105 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1102, UInt<1>(0h1), "") : assert_104
node _T_1106 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1107 = orr(a_set_wo_ready)
node _T_1108 = eq(_T_1107, UInt<1>(0h0))
node _T_1109 = or(_T_1106, _T_1108)
node _T_1110 = asUInt(reset)
node _T_1111 = eq(_T_1110, UInt<1>(0h0))
when _T_1111 :
node _T_1112 = eq(_T_1109, UInt<1>(0h0))
when _T_1112 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1109, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_68
node _T_1113 = orr(inflight)
node _T_1114 = eq(_T_1113, UInt<1>(0h0))
node _T_1115 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1116 = or(_T_1114, _T_1115)
node _T_1117 = lt(watchdog, plusarg_reader.out)
node _T_1118 = or(_T_1116, _T_1117)
node _T_1119 = asUInt(reset)
node _T_1120 = eq(_T_1119, UInt<1>(0h0))
when _T_1120 :
node _T_1121 = eq(_T_1118, UInt<1>(0h0))
when _T_1121 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1118, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1122 = and(io.in.a.ready, io.in.a.valid)
node _T_1123 = and(io.in.d.ready, io.in.d.valid)
node _T_1124 = or(_T_1122, _T_1123)
when _T_1124 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<129>, clock, reset, UInt<129>(0h0)
regreset inflight_opcodes_1 : UInt<516>, clock, reset, UInt<516>(0h0)
regreset inflight_sizes_1 : UInt<516>, clock, reset, UInt<516>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<21>(0h0)
connect _c_first_WIRE.bits.source, UInt<8>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<21>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<8>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<129>
connect c_set, UInt<129>(0h0)
wire c_set_wo_ready : UInt<129>
connect c_set_wo_ready, UInt<129>(0h0)
wire c_opcodes_set : UInt<516>
connect c_opcodes_set, UInt<516>(0h0)
wire c_sizes_set : UInt<516>
connect c_sizes_set, UInt<516>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<21>(0h0)
connect _WIRE_6.bits.source, UInt<8>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1125 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<21>(0h0)
connect _WIRE_8.bits.source, UInt<8>(0h0)
connect _WIRE_8.bits.size, UInt<3>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1126 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_1127 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_1128 = and(_T_1126, _T_1127)
node _T_1129 = and(_T_1125, _T_1128)
when _T_1129 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<21>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<8>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<21>(0h0)
connect _WIRE_10.bits.source, UInt<8>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1130 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_1131 = and(_T_1130, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<21>(0h0)
connect _WIRE_12.bits.source, UInt<8>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1132 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1133 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1134 = and(_T_1132, _T_1133)
node _T_1135 = and(_T_1131, _T_1134)
when _T_1135 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<21>(0h0)
connect _c_set_WIRE.bits.source, UInt<8>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<21>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<8>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<21>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<8>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<21>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<8>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<21>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<8>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<21>(0h0)
connect _WIRE_14.bits.source, UInt<8>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1136 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_1137 = bits(_T_1136, 0, 0)
node _T_1138 = eq(_T_1137, UInt<1>(0h0))
node _T_1139 = asUInt(reset)
node _T_1140 = eq(_T_1139, UInt<1>(0h0))
when _T_1140 :
node _T_1141 = eq(_T_1138, UInt<1>(0h0))
when _T_1141 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1138, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<21>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<8>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<21>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<8>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<129>
connect d_clr_1, UInt<129>(0h0)
wire d_clr_wo_ready_1 : UInt<129>
connect d_clr_wo_ready_1, UInt<129>(0h0)
wire d_opcodes_clr_1 : UInt<516>
connect d_opcodes_clr_1, UInt<516>(0h0)
wire d_sizes_clr_1 : UInt<516>
connect d_sizes_clr_1, UInt<516>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1142 = and(io.in.d.valid, d_first_2)
node _T_1143 = and(_T_1142, UInt<1>(0h1))
node _T_1144 = and(_T_1143, d_release_ack_1)
when _T_1144 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1145 = and(io.in.d.ready, io.in.d.valid)
node _T_1146 = and(_T_1145, d_first_2)
node _T_1147 = and(_T_1146, UInt<1>(0h1))
node _T_1148 = and(_T_1147, d_release_ack_1)
when _T_1148 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1149 = and(io.in.d.valid, d_first_2)
node _T_1150 = and(_T_1149, UInt<1>(0h1))
node _T_1151 = and(_T_1150, d_release_ack_1)
when _T_1151 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<21>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<8>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<21>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<8>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<21>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<8>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1152 = dshr(inflight_1, io.in.d.bits.source)
node _T_1153 = bits(_T_1152, 0, 0)
node _T_1154 = or(_T_1153, same_cycle_resp_1)
node _T_1155 = asUInt(reset)
node _T_1156 = eq(_T_1155, UInt<1>(0h0))
when _T_1156 :
node _T_1157 = eq(_T_1154, UInt<1>(0h0))
when _T_1157 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1154, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<21>(0h0)
connect _WIRE_16.bits.source, UInt<8>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1158 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_1159 = asUInt(reset)
node _T_1160 = eq(_T_1159, UInt<1>(0h0))
when _T_1160 :
node _T_1161 = eq(_T_1158, UInt<1>(0h0))
when _T_1161 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1158, UInt<1>(0h1), "") : assert_109
else :
node _T_1162 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1163 = asUInt(reset)
node _T_1164 = eq(_T_1163, UInt<1>(0h0))
when _T_1164 :
node _T_1165 = eq(_T_1162, UInt<1>(0h0))
when _T_1165 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1162, UInt<1>(0h1), "") : assert_110
node _T_1166 = and(io.in.d.valid, d_first_2)
node _T_1167 = and(_T_1166, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<21>(0h0)
connect _WIRE_18.bits.source, UInt<8>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1168 = and(_T_1167, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<21>(0h0)
connect _WIRE_20.bits.source, UInt<8>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1169 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_1170 = and(_T_1168, _T_1169)
node _T_1171 = and(_T_1170, d_release_ack_1)
node _T_1172 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1173 = and(_T_1171, _T_1172)
when _T_1173 :
node _T_1174 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<21>(0h0)
connect _WIRE_22.bits.source, UInt<8>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1175 = or(_T_1174, _WIRE_23.ready)
node _T_1176 = asUInt(reset)
node _T_1177 = eq(_T_1176, UInt<1>(0h0))
when _T_1177 :
node _T_1178 = eq(_T_1175, UInt<1>(0h0))
when _T_1178 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1175, UInt<1>(0h1), "") : assert_111
node _T_1179 = orr(c_set_wo_ready)
when _T_1179 :
node _T_1180 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1181 = asUInt(reset)
node _T_1182 = eq(_T_1181, UInt<1>(0h0))
when _T_1182 :
node _T_1183 = eq(_T_1180, UInt<1>(0h0))
when _T_1183 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1180, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_69
node _T_1184 = orr(inflight_1)
node _T_1185 = eq(_T_1184, UInt<1>(0h0))
node _T_1186 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1187 = or(_T_1185, _T_1186)
node _T_1188 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1189 = or(_T_1187, _T_1188)
node _T_1190 = asUInt(reset)
node _T_1191 = eq(_T_1190, UInt<1>(0h0))
when _T_1191 :
node _T_1192 = eq(_T_1189, UInt<1>(0h0))
when _T_1192 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1189, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<21>(0h0)
connect _WIRE_24.bits.source, UInt<8>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1193 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_1194 = and(io.in.d.ready, io.in.d.valid)
node _T_1195 = or(_T_1193, _T_1194)
when _T_1195 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_34( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_63 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_69 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_71 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_75 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_77 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_83 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_first_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_first_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_first_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_first_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [2050:0] _c_opcodes_set_T_1 = 2051'h0; // @[Monitor.scala:767:54]
wire [2050:0] _c_sizes_set_T_1 = 2051'h0; // @[Monitor.scala:768:52]
wire [10:0] _c_opcodes_set_T = 11'h0; // @[Monitor.scala:767:79]
wire [10:0] _c_sizes_set_T = 11'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [255:0] _c_set_wo_ready_T = 256'h1; // @[OneHot.scala:58:35]
wire [255:0] _c_set_T = 256'h1; // @[OneHot.scala:58:35]
wire [515:0] c_opcodes_set = 516'h0; // @[Monitor.scala:740:34]
wire [515:0] c_sizes_set = 516'h0; // @[Monitor.scala:741:34]
wire [128:0] c_set = 129'h0; // @[Monitor.scala:738:34]
wire [128:0] c_set_wo_ready = 129'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 8'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] _source_ok_T_13 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_19 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_25 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_31 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_14 = _source_ok_T_13 == 6'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 6'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_26 = _source_ok_T_25 == 6'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_32 = _source_ok_T_31 == 6'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31]
wire _source_ok_T_37 = io_in_a_bits_source_0 == 8'h41; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_37; // @[Parameters.scala:1138:31]
wire _source_ok_T_38 = io_in_a_bits_source_0 == 8'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_38; // @[Parameters.scala:1138:31]
wire _source_ok_T_39 = io_in_a_bits_source_0 == 8'h80; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_9 = _source_ok_T_39; // @[Parameters.scala:1138:31]
wire _source_ok_T_40 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_41 = _source_ok_T_40 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_42 = _source_ok_T_41 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_43 = _source_ok_T_42 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_44 = _source_ok_T_43 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_45 = _source_ok_T_44 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_46 = _source_ok_T_45 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_47 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [20:0] _is_aligned_T = {15'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [2:0] uncommonBits = _uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_1 = _uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_6 = _uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_7 = _uncommonBits_T_7[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_12 = _uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_13 = _uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_18 = _uncommonBits_T_18[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_19 = _uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_24 = _uncommonBits_T_24[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_25 = _uncommonBits_T_25[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_30 = _uncommonBits_T_30[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_31 = _uncommonBits_T_31[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_36 = _uncommonBits_T_36[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_37 = _uncommonBits_T_37[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_42 = _uncommonBits_T_42[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_43 = _uncommonBits_T_43[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_48 = _uncommonBits_T_48[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_49 = _uncommonBits_T_49[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_48 = io_in_d_bits_source_0 == 8'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_48; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_49 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_55 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_50 = _source_ok_T_49 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_54; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_56 = _source_ok_T_55 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_60; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] _source_ok_T_61 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_67 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_73 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_79 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_62 = _source_ok_T_61 == 6'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_64 = _source_ok_T_62; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_66; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_68 = _source_ok_T_67 == 6'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_70 = _source_ok_T_68; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_72 = _source_ok_T_70; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_72; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_74 = _source_ok_T_73 == 6'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_76 = _source_ok_T_74; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_78 = _source_ok_T_76; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_5 = _source_ok_T_78; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_80 = _source_ok_T_79 == 6'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_84 = _source_ok_T_82; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_6 = _source_ok_T_84; // @[Parameters.scala:1138:31]
wire _source_ok_T_85 = io_in_d_bits_source_0 == 8'h41; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_85; // @[Parameters.scala:1138:31]
wire _source_ok_T_86 = io_in_d_bits_source_0 == 8'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_86; // @[Parameters.scala:1138:31]
wire _source_ok_T_87 = io_in_d_bits_source_0 == 8'h80; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_9 = _source_ok_T_87; // @[Parameters.scala:1138:31]
wire _source_ok_T_88 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_89 = _source_ok_T_88 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_90 = _source_ok_T_89 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_91 = _source_ok_T_90 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_92 = _source_ok_T_91 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_93 = _source_ok_T_92 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_94 = _source_ok_T_93 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_95 = _source_ok_T_94 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_95 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1122 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1122; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1122; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [7:0] source; // @[Monitor.scala:390:22]
reg [20:0] address; // @[Monitor.scala:391:22]
wire _T_1195 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1195; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1195; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1195; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [7:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [128:0] inflight; // @[Monitor.scala:614:27]
reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [515:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [128:0] a_set; // @[Monitor.scala:626:34]
wire [128:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [515:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [515:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [515:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [515:0] _a_opcode_lookup_T_6 = {512'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [515:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [515:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [515:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [515:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[515:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [255:0] _GEN_2 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [255:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire _T_1048 = _T_1122 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1048 ? _a_set_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1048 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1048 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [10:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [10:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [10:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1048 ? _a_opcodes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [2050:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1048 ? _a_sizes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [128:0] d_clr; // @[Monitor.scala:664:34]
wire [128:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [515:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [515:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1094 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [255:0] _GEN_5 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1094 & ~d_release_ack ? _d_clr_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire _T_1063 = _T_1195 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1063 ? _d_clr_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1063 ? _d_opcodes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [2062:0] _d_sizes_clr_T_5 = 2063'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1063 ? _d_sizes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [128:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [128:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [128:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [515:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [515:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [515:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [515:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [515:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [515:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [128:0] inflight_1; // @[Monitor.scala:726:35]
wire [128:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [515:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [515:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [515:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [515:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [515:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [515:0] _c_opcode_lookup_T_6 = {512'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [515:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [515:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [515:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [515:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[515:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [128:0] d_clr_1; // @[Monitor.scala:774:34]
wire [128:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [515:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [515:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1166 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1166 & d_release_ack_1 ? _d_clr_wo_ready_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire _T_1148 = _T_1195 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1148 ? _d_clr_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1148 ? _d_opcodes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [2062:0] _d_sizes_clr_T_11 = 2063'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1148 ? _d_sizes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0; // @[Monitor.scala:36:7, :795:113]
wire [128:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [128:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [515:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [515:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [515:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [515:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_130 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_222
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_130( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_222 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_58 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<4>, q : UInt<4>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_505
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
node _output_T_2 = asAsyncReset(reset)
node _output_T_3 = bits(io.d, 1, 1)
inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_506
connect output_chain_1.clock, clock
connect output_chain_1.reset, _output_T_2
connect output_chain_1.io.d, _output_T_3
wire output_1 : UInt<1>
connect output_1, output_chain_1.io.q
node _output_T_4 = asAsyncReset(reset)
node _output_T_5 = bits(io.d, 2, 2)
inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_507
connect output_chain_2.clock, clock
connect output_chain_2.reset, _output_T_4
connect output_chain_2.io.d, _output_T_5
wire output_2 : UInt<1>
connect output_2, output_chain_2.io.q
node _output_T_6 = asAsyncReset(reset)
node _output_T_7 = bits(io.d, 3, 3)
inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_508
connect output_chain_3.clock, clock
connect output_chain_3.reset, _output_T_6
connect output_chain_3.io.d, _output_T_7
wire output_3 : UInt<1>
connect output_3, output_chain_3.io.q
node io_q_lo = cat(output_1, output_0)
node io_q_hi = cat(output_3, output_2)
node _io_q_T = cat(io_q_hi, io_q_lo)
connect io.q, _io_q_T | module AsyncResetSynchronizerShiftReg_w4_d3_i0_58( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input [3:0] io_d, // @[ShiftReg.scala:36:14]
output [3:0] io_q // @[ShiftReg.scala:36:14]
);
wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21]
wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14]
wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7]
wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_1; // @[ShiftReg.scala:48:24]
wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_2; // @[ShiftReg.scala:48:24]
wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_3; // @[ShiftReg.scala:48:24]
wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14]
wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14]
assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14]
assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_505 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_506 output_chain_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_2), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_3), // @[SynchronizerReg.scala:87:41]
.io_q (output_1)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_507 output_chain_2 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_4), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_5), // @[SynchronizerReg.scala:87:41]
.io_q (output_2)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_508 output_chain_3 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_6), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_7), // @[SynchronizerReg.scala:87:41]
.io_q (output_3)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_113 :
output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node rawIn_exp = bits(io.in, 31, 23)
node _rawIn_isZero_T = bits(rawIn_exp, 8, 6)
node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0))
node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7)
node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3))
wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T)
connect rawIn.isNaN, _rawIn_out_isNaN_T_1
node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0))
node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1)
connect rawIn.isInf, _rawIn_out_isInf_T_2
connect rawIn.isZero, rawIn_isZero
node _rawIn_out_sign_T = bits(io.in, 32, 32)
connect rawIn.sign, _rawIn_out_sign_T
node _rawIn_out_sExp_T = cvt(rawIn_exp)
connect rawIn.sExp, _rawIn_out_sExp_T
node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0))
node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T)
node _rawIn_out_sig_T_2 = bits(io.in, 22, 0)
node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2)
connect rawIn.sig, _rawIn_out_sig_T_3
node _io_out_T = shl(io.in, 0)
connect io.out, _io_out_T
node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22)
node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0))
node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0))
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RecFNToRecFN_113( // @[RecFNToRecFN.scala:44:5]
input [32:0] io_in, // @[RecFNToRecFN.scala:48:16]
output [32:0] io_out // @[RecFNToRecFN.scala:48:16]
);
wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5]
wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35]
wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54]
wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5]
wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5]
wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35]
wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}]
wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46]
assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54]
assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_400 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_400( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_440 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_440( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module Repeater_TLBundleA_a29d64s10k1z3u :
input clock : Clock
input reset : Reset
output io : { flip repeat : UInt<1>, full : UInt<1>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}}
regreset full : UInt<1>, clock, reset, UInt<1>(0h0)
reg saved : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}, clock
node _io_deq_valid_T = or(io.enq.valid, full)
connect io.deq.valid, _io_deq_valid_T
node _io_enq_ready_T = eq(full, UInt<1>(0h0))
node _io_enq_ready_T_1 = and(io.deq.ready, _io_enq_ready_T)
connect io.enq.ready, _io_enq_ready_T_1
node _io_deq_bits_T = mux(full, saved, io.enq.bits)
connect io.deq.bits, _io_deq_bits_T
connect io.full, full
node _T = and(io.enq.ready, io.enq.valid)
node _T_1 = and(_T, io.repeat)
when _T_1 :
connect full, UInt<1>(0h1)
connect saved, io.enq.bits
node _T_2 = and(io.deq.ready, io.deq.valid)
node _T_3 = eq(io.repeat, UInt<1>(0h0))
node _T_4 = and(_T_2, _T_3)
when _T_4 :
connect full, UInt<1>(0h0) | module Repeater_TLBundleA_a29d64s10k1z3u( // @[Repeater.scala:10:7]
input clock, // @[Repeater.scala:10:7]
input reset, // @[Repeater.scala:10:7]
input io_repeat, // @[Repeater.scala:13:14]
output io_full, // @[Repeater.scala:13:14]
output io_enq_ready, // @[Repeater.scala:13:14]
input io_enq_valid, // @[Repeater.scala:13:14]
input [2:0] io_enq_bits_opcode, // @[Repeater.scala:13:14]
input [2:0] io_enq_bits_param, // @[Repeater.scala:13:14]
input [2:0] io_enq_bits_size, // @[Repeater.scala:13:14]
input [9:0] io_enq_bits_source, // @[Repeater.scala:13:14]
input [28:0] io_enq_bits_address, // @[Repeater.scala:13:14]
input [7:0] io_enq_bits_mask, // @[Repeater.scala:13:14]
input [63:0] io_enq_bits_data, // @[Repeater.scala:13:14]
input io_enq_bits_corrupt, // @[Repeater.scala:13:14]
input io_deq_ready, // @[Repeater.scala:13:14]
output io_deq_valid, // @[Repeater.scala:13:14]
output [2:0] io_deq_bits_opcode, // @[Repeater.scala:13:14]
output [2:0] io_deq_bits_param, // @[Repeater.scala:13:14]
output [2:0] io_deq_bits_size, // @[Repeater.scala:13:14]
output [9:0] io_deq_bits_source, // @[Repeater.scala:13:14]
output [28:0] io_deq_bits_address, // @[Repeater.scala:13:14]
output [7:0] io_deq_bits_mask, // @[Repeater.scala:13:14]
output io_deq_bits_corrupt // @[Repeater.scala:13:14]
);
wire io_repeat_0 = io_repeat; // @[Repeater.scala:10:7]
wire io_enq_valid_0 = io_enq_valid; // @[Repeater.scala:10:7]
wire [2:0] io_enq_bits_opcode_0 = io_enq_bits_opcode; // @[Repeater.scala:10:7]
wire [2:0] io_enq_bits_param_0 = io_enq_bits_param; // @[Repeater.scala:10:7]
wire [2:0] io_enq_bits_size_0 = io_enq_bits_size; // @[Repeater.scala:10:7]
wire [9:0] io_enq_bits_source_0 = io_enq_bits_source; // @[Repeater.scala:10:7]
wire [28:0] io_enq_bits_address_0 = io_enq_bits_address; // @[Repeater.scala:10:7]
wire [7:0] io_enq_bits_mask_0 = io_enq_bits_mask; // @[Repeater.scala:10:7]
wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[Repeater.scala:10:7]
wire io_enq_bits_corrupt_0 = io_enq_bits_corrupt; // @[Repeater.scala:10:7]
wire io_deq_ready_0 = io_deq_ready; // @[Repeater.scala:10:7]
wire _io_enq_ready_T_1; // @[Repeater.scala:25:32]
wire _io_deq_valid_T; // @[Repeater.scala:24:32]
wire [2:0] _io_deq_bits_T_opcode; // @[Repeater.scala:26:21]
wire [2:0] _io_deq_bits_T_param; // @[Repeater.scala:26:21]
wire [2:0] _io_deq_bits_T_size; // @[Repeater.scala:26:21]
wire [9:0] _io_deq_bits_T_source; // @[Repeater.scala:26:21]
wire [28:0] _io_deq_bits_T_address; // @[Repeater.scala:26:21]
wire [7:0] _io_deq_bits_T_mask; // @[Repeater.scala:26:21]
wire [63:0] _io_deq_bits_T_data; // @[Repeater.scala:26:21]
wire _io_deq_bits_T_corrupt; // @[Repeater.scala:26:21]
wire io_enq_ready_0; // @[Repeater.scala:10:7]
wire [2:0] io_deq_bits_opcode_0; // @[Repeater.scala:10:7]
wire [2:0] io_deq_bits_param_0; // @[Repeater.scala:10:7]
wire [2:0] io_deq_bits_size_0; // @[Repeater.scala:10:7]
wire [9:0] io_deq_bits_source_0; // @[Repeater.scala:10:7]
wire [28:0] io_deq_bits_address_0; // @[Repeater.scala:10:7]
wire [7:0] io_deq_bits_mask_0; // @[Repeater.scala:10:7]
wire [63:0] io_deq_bits_data; // @[Repeater.scala:10:7]
wire io_deq_bits_corrupt_0; // @[Repeater.scala:10:7]
wire io_deq_valid_0; // @[Repeater.scala:10:7]
wire io_full_0; // @[Repeater.scala:10:7]
reg full; // @[Repeater.scala:20:21]
assign io_full_0 = full; // @[Repeater.scala:10:7, :20:21]
reg [2:0] saved_opcode; // @[Repeater.scala:21:18]
reg [2:0] saved_param; // @[Repeater.scala:21:18]
reg [2:0] saved_size; // @[Repeater.scala:21:18]
reg [9:0] saved_source; // @[Repeater.scala:21:18]
reg [28:0] saved_address; // @[Repeater.scala:21:18]
reg [7:0] saved_mask; // @[Repeater.scala:21:18]
reg [63:0] saved_data; // @[Repeater.scala:21:18]
reg saved_corrupt; // @[Repeater.scala:21:18]
assign _io_deq_valid_T = io_enq_valid_0 | full; // @[Repeater.scala:10:7, :20:21, :24:32]
assign io_deq_valid_0 = _io_deq_valid_T; // @[Repeater.scala:10:7, :24:32]
wire _io_enq_ready_T = ~full; // @[Repeater.scala:20:21, :25:35]
assign _io_enq_ready_T_1 = io_deq_ready_0 & _io_enq_ready_T; // @[Repeater.scala:10:7, :25:{32,35}]
assign io_enq_ready_0 = _io_enq_ready_T_1; // @[Repeater.scala:10:7, :25:32]
assign _io_deq_bits_T_opcode = full ? saved_opcode : io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_param = full ? saved_param : io_enq_bits_param_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_size = full ? saved_size : io_enq_bits_size_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_source = full ? saved_source : io_enq_bits_source_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_address = full ? saved_address : io_enq_bits_address_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_mask = full ? saved_mask : io_enq_bits_mask_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_data = full ? saved_data : io_enq_bits_data_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_corrupt = full ? saved_corrupt : io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign io_deq_bits_opcode_0 = _io_deq_bits_T_opcode; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_param_0 = _io_deq_bits_T_param; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_size_0 = _io_deq_bits_T_size; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_source_0 = _io_deq_bits_T_source; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_address_0 = _io_deq_bits_T_address; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_mask_0 = _io_deq_bits_T_mask; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_data = _io_deq_bits_T_data; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_corrupt_0 = _io_deq_bits_T_corrupt; // @[Repeater.scala:10:7, :26:21]
wire _T_1 = io_enq_ready_0 & io_enq_valid_0 & io_repeat_0; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[Repeater.scala:10:7]
if (reset) // @[Repeater.scala:10:7]
full <= 1'h0; // @[Repeater.scala:20:21]
else // @[Repeater.scala:10:7]
full <= ~(io_deq_ready_0 & io_deq_valid_0 & ~io_repeat_0) & (_T_1 | full); // @[Decoupled.scala:51:35]
if (_T_1) begin // @[Decoupled.scala:51:35]
saved_opcode <= io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :21:18]
saved_param <= io_enq_bits_param_0; // @[Repeater.scala:10:7, :21:18]
saved_size <= io_enq_bits_size_0; // @[Repeater.scala:10:7, :21:18]
saved_source <= io_enq_bits_source_0; // @[Repeater.scala:10:7, :21:18]
saved_address <= io_enq_bits_address_0; // @[Repeater.scala:10:7, :21:18]
saved_mask <= io_enq_bits_mask_0; // @[Repeater.scala:10:7, :21:18]
saved_data <= io_enq_bits_data_0; // @[Repeater.scala:10:7, :21:18]
saved_corrupt <= io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :21:18]
end
always @(posedge)
assign io_full = io_full_0; // @[Repeater.scala:10:7]
assign io_enq_ready = io_enq_ready_0; // @[Repeater.scala:10:7]
assign io_deq_valid = io_deq_valid_0; // @[Repeater.scala:10:7]
assign io_deq_bits_opcode = io_deq_bits_opcode_0; // @[Repeater.scala:10:7]
assign io_deq_bits_param = io_deq_bits_param_0; // @[Repeater.scala:10:7]
assign io_deq_bits_size = io_deq_bits_size_0; // @[Repeater.scala:10:7]
assign io_deq_bits_source = io_deq_bits_source_0; // @[Repeater.scala:10:7]
assign io_deq_bits_address = io_deq_bits_address_0; // @[Repeater.scala:10:7]
assign io_deq_bits_mask = io_deq_bits_mask_0; // @[Repeater.scala:10:7]
assign io_deq_bits_corrupt = io_deq_bits_corrupt_0; // @[Repeater.scala:10:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_242 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_242( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module PE_473 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>}
inst mac_unit of MacUnit_217
connect mac_unit.clock, clock
connect mac_unit.reset, reset
reg c1 : SInt<32>, clock
reg c2 : SInt<32>, clock
connect io.out_a, io.in_a
connect io.out_control.dataflow, io.in_control.dataflow
connect io.out_control.propagate, io.in_control.propagate
connect io.out_control.shift, io.in_control.shift
connect io.out_id, io.in_id
connect io.out_last, io.in_last
connect io.out_valid, io.in_valid
connect mac_unit.io.in_a, io.in_a
reg last_s : UInt<1>, clock
when io.in_valid :
connect last_s, io.in_control.propagate
node flip = neq(last_s, io.in_control.propagate)
node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0))
connect io.bad_dataflow, UInt<1>(0h0)
node _T = eq(io.in_control.dataflow, UInt<1>(0h0))
node _T_1 = and(UInt<1>(0h1), _T)
node _T_2 = or(UInt<1>(0h0), _T_1)
when _T_2 :
node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_3 :
node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1)
node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2)
node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0)
node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4)
node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_1 = asUInt(c1)
node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1)
node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3)
node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1))
node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1)
node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6)
node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7)
node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0))
node _io_out_c_ones_digit_T = dshr(c1, shift_offset)
node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0)
node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit)
node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T)
node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0)
node _io_out_c_T = dshr(c1, shift_offset)
node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1)
node _io_out_c_T_3 = tail(_io_out_c_T_2, 1)
node _io_out_c_T_4 = asSInt(_io_out_c_T_3)
node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4)
node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7)
node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0)
node _io_out_c_T_10 = asSInt(_io_out_c_T_9)
connect io.out_c, _io_out_c_T_10
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE : SInt<8>
node _mac_unit_io_in_b_T = asUInt(io.in_b)
node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T)
connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE
connect mac_unit.io.in_c, c2
connect c2, mac_unit.io.out_d
node c1_sign = bits(io.in_d, 19, 19)
node c1_lo_lo_hi = cat(c1_sign, c1_sign)
node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign)
node c1_lo_hi_hi = cat(c1_sign, c1_sign)
node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign)
node c1_lo = cat(c1_lo_hi, c1_lo_lo)
node c1_hi_lo_hi = cat(c1_sign, c1_sign)
node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign)
node c1_hi_hi_hi = cat(c1_sign, c1_sign)
node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign)
node c1_hi = cat(c1_hi_hi, c1_hi_lo)
node _c1_T = cat(c1_hi, c1_lo)
node c1_lo_1 = asUInt(io.in_d)
node _c1_T_1 = cat(_c1_T, c1_lo_1)
wire _c1_WIRE : SInt<32>
node _c1_T_2 = asSInt(_c1_T_1)
connect _c1_WIRE, _c1_T_2
connect c1, _c1_WIRE
else :
node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1)
node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7)
node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0)
node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9)
node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_10 = asUInt(c2)
node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1)
node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12)
node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1))
node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1)
node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15)
node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16)
node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0))
node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset)
node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0)
node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1)
node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2)
node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0)
node _io_out_c_T_11 = dshr(c2, shift_offset)
node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12)
node _io_out_c_T_14 = tail(_io_out_c_T_13, 1)
node _io_out_c_T_15 = asSInt(_io_out_c_T_14)
node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15)
node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18)
node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0)
node _io_out_c_T_21 = asSInt(_io_out_c_T_20)
connect io.out_c, _io_out_c_T_21
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE_1 : SInt<8>
node _mac_unit_io_in_b_T_2 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2)
connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1
connect mac_unit.io.in_c, c1
connect c1, mac_unit.io.out_d
node c2_sign = bits(io.in_d, 19, 19)
node c2_lo_lo_hi = cat(c2_sign, c2_sign)
node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign)
node c2_lo_hi_hi = cat(c2_sign, c2_sign)
node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign)
node c2_lo = cat(c2_lo_hi, c2_lo_lo)
node c2_hi_lo_hi = cat(c2_sign, c2_sign)
node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign)
node c2_hi_hi_hi = cat(c2_sign, c2_sign)
node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign)
node c2_hi = cat(c2_hi_hi, c2_hi_lo)
node _c2_T = cat(c2_hi, c2_lo)
node c2_lo_1 = asUInt(io.in_d)
node _c2_T_1 = cat(_c2_T, c2_lo_1)
wire _c2_WIRE : SInt<32>
node _c2_T_2 = asSInt(_c2_T_1)
connect _c2_WIRE, _c2_T_2
connect c2, _c2_WIRE
else :
node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1))
node _T_5 = and(UInt<1>(0h1), _T_4)
node _T_6 = or(UInt<1>(0h0), _T_5)
when _T_6 :
node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_7 :
connect io.out_c, c1
wire _mac_unit_io_in_b_WIRE_2 : SInt<8>
node _mac_unit_io_in_b_T_4 = asUInt(c2)
node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4)
connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c1, io.in_d
else :
connect io.out_c, c2
wire _mac_unit_io_in_b_WIRE_3 : SInt<8>
node _mac_unit_io_in_b_T_6 = asUInt(c1)
node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6)
connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c2, io.in_d
else :
connect io.bad_dataflow, UInt<1>(0h1)
invalidate io.out_c
invalidate io.out_b
wire _mac_unit_io_in_b_WIRE_4 : SInt<8>
node _mac_unit_io_in_b_T_8 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8)
connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4
connect mac_unit.io.in_c, c2
node _T_8 = eq(io.in_valid, UInt<1>(0h0))
when _T_8 :
connect c1, c1
connect c2, c2
invalidate mac_unit.io.in_b
invalidate mac_unit.io.in_c | module PE_473( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid, // @[PE.scala:35:14]
output io_bad_dataflow // @[PE.scala:35:14]
);
wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24]
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [31:0] c1; // @[PE.scala:70:15]
wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [31:0] c2; // @[PE.scala:71:15]
wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25]
wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61]
wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38]
wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38]
assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16]
assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10]
wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10]
c1 <= _GEN_7; // @[PE.scala:70:15, :124:10]
if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30]
end
else // @[PE.scala:71:15, :118:101, :119:30]
c2 <= _GEN_7; // @[PE.scala:71:15, :124:10]
end
else begin // @[PE.scala:31:7]
c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10]
c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10]
end
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
end
always @(posedge)
MacUnit_217 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24]
.io_out_d (_mac_unit_io_out_d)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_84 :
output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0))
node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1))
node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2))
node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3))
node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4))
node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6))
node _roundMagUp_T = and(roundingMode_min, io.in.sign)
node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0))
node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1)
node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2)
node adjustedSig = shl(io.in.sig, 0)
node doShiftSigDown1 = bits(adjustedSig, 26, 26)
wire common_expOut : UInt<9>
wire common_fractOut : UInt<23>
wire common_overflow : UInt<1>
wire common_totalUnderflow : UInt<1>
wire common_underflow : UInt<1>
wire common_inexact : UInt<1>
node _roundMask_T = bits(io.in.sExp, 8, 0)
node _roundMask_T_1 = not(_roundMask_T)
node roundMask_msb = bits(_roundMask_T_1, 8, 8)
node roundMask_lsbs = bits(_roundMask_T_1, 7, 0)
node roundMask_msb_1 = bits(roundMask_lsbs, 7, 7)
node roundMask_lsbs_1 = bits(roundMask_lsbs, 6, 0)
node roundMask_msb_2 = bits(roundMask_lsbs_1, 6, 6)
node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 5, 0)
node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_2)
node _roundMask_T_2 = bits(roundMask_shift, 63, 42)
node _roundMask_T_3 = bits(_roundMask_T_2, 15, 0)
node _roundMask_T_4 = shl(UInt<8>(0hff), 8)
node _roundMask_T_5 = xor(UInt<16>(0hffff), _roundMask_T_4)
node _roundMask_T_6 = shr(_roundMask_T_3, 8)
node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5)
node _roundMask_T_8 = bits(_roundMask_T_3, 7, 0)
node _roundMask_T_9 = shl(_roundMask_T_8, 8)
node _roundMask_T_10 = not(_roundMask_T_5)
node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10)
node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11)
node _roundMask_T_13 = bits(_roundMask_T_5, 11, 0)
node _roundMask_T_14 = shl(_roundMask_T_13, 4)
node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14)
node _roundMask_T_16 = shr(_roundMask_T_12, 4)
node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15)
node _roundMask_T_18 = bits(_roundMask_T_12, 11, 0)
node _roundMask_T_19 = shl(_roundMask_T_18, 4)
node _roundMask_T_20 = not(_roundMask_T_15)
node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20)
node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21)
node _roundMask_T_23 = bits(_roundMask_T_15, 13, 0)
node _roundMask_T_24 = shl(_roundMask_T_23, 2)
node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24)
node _roundMask_T_26 = shr(_roundMask_T_22, 2)
node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25)
node _roundMask_T_28 = bits(_roundMask_T_22, 13, 0)
node _roundMask_T_29 = shl(_roundMask_T_28, 2)
node _roundMask_T_30 = not(_roundMask_T_25)
node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30)
node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31)
node _roundMask_T_33 = bits(_roundMask_T_25, 14, 0)
node _roundMask_T_34 = shl(_roundMask_T_33, 1)
node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34)
node _roundMask_T_36 = shr(_roundMask_T_32, 1)
node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35)
node _roundMask_T_38 = bits(_roundMask_T_32, 14, 0)
node _roundMask_T_39 = shl(_roundMask_T_38, 1)
node _roundMask_T_40 = not(_roundMask_T_35)
node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40)
node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41)
node _roundMask_T_43 = bits(_roundMask_T_2, 21, 16)
node _roundMask_T_44 = bits(_roundMask_T_43, 3, 0)
node _roundMask_T_45 = bits(_roundMask_T_44, 1, 0)
node _roundMask_T_46 = bits(_roundMask_T_45, 0, 0)
node _roundMask_T_47 = bits(_roundMask_T_45, 1, 1)
node _roundMask_T_48 = cat(_roundMask_T_46, _roundMask_T_47)
node _roundMask_T_49 = bits(_roundMask_T_44, 3, 2)
node _roundMask_T_50 = bits(_roundMask_T_49, 0, 0)
node _roundMask_T_51 = bits(_roundMask_T_49, 1, 1)
node _roundMask_T_52 = cat(_roundMask_T_50, _roundMask_T_51)
node _roundMask_T_53 = cat(_roundMask_T_48, _roundMask_T_52)
node _roundMask_T_54 = bits(_roundMask_T_43, 5, 4)
node _roundMask_T_55 = bits(_roundMask_T_54, 0, 0)
node _roundMask_T_56 = bits(_roundMask_T_54, 1, 1)
node _roundMask_T_57 = cat(_roundMask_T_55, _roundMask_T_56)
node _roundMask_T_58 = cat(_roundMask_T_53, _roundMask_T_57)
node _roundMask_T_59 = cat(_roundMask_T_42, _roundMask_T_58)
node _roundMask_T_60 = not(_roundMask_T_59)
node _roundMask_T_61 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_60)
node _roundMask_T_62 = not(_roundMask_T_61)
node _roundMask_T_63 = cat(_roundMask_T_62, UInt<3>(0h7))
node roundMask_msb_3 = bits(roundMask_lsbs_1, 6, 6)
node roundMask_lsbs_3 = bits(roundMask_lsbs_1, 5, 0)
node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_3)
node _roundMask_T_64 = bits(roundMask_shift_1, 2, 0)
node _roundMask_T_65 = bits(_roundMask_T_64, 1, 0)
node _roundMask_T_66 = bits(_roundMask_T_65, 0, 0)
node _roundMask_T_67 = bits(_roundMask_T_65, 1, 1)
node _roundMask_T_68 = cat(_roundMask_T_66, _roundMask_T_67)
node _roundMask_T_69 = bits(_roundMask_T_64, 2, 2)
node _roundMask_T_70 = cat(_roundMask_T_68, _roundMask_T_69)
node _roundMask_T_71 = mux(roundMask_msb_3, _roundMask_T_70, UInt<1>(0h0))
node _roundMask_T_72 = mux(roundMask_msb_1, _roundMask_T_63, _roundMask_T_71)
node _roundMask_T_73 = mux(roundMask_msb, _roundMask_T_72, UInt<1>(0h0))
node _roundMask_T_74 = or(_roundMask_T_73, doShiftSigDown1)
node roundMask = cat(_roundMask_T_74, UInt<2>(0h3))
node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask)
node shiftedRoundMask = shr(_shiftedRoundMask_T, 1)
node _roundPosMask_T = not(shiftedRoundMask)
node roundPosMask = and(_roundPosMask_T, roundMask)
node _roundPosBit_T = and(adjustedSig, roundPosMask)
node roundPosBit = orr(_roundPosBit_T)
node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask)
node anyRoundExtra = orr(_anyRoundExtra_T)
node anyRound = or(roundPosBit, anyRoundExtra)
node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit)
node _roundIncr_T_2 = and(roundMagUp, anyRound)
node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2)
node _roundedSig_T = or(adjustedSig, roundMask)
node _roundedSig_T_1 = shr(_roundedSig_T, 2)
node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1))
node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit)
node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0))
node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4)
node _roundedSig_T_6 = shr(roundMask, 1)
node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0))
node _roundedSig_T_8 = not(_roundedSig_T_7)
node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8)
node _roundedSig_T_10 = not(roundMask)
node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10)
node _roundedSig_T_12 = shr(_roundedSig_T_11, 2)
node _roundedSig_T_13 = and(roundingMode_odd, anyRound)
node _roundedSig_T_14 = shr(roundPosMask, 1)
node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0))
node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15)
node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16)
node _sRoundedExp_T = shr(roundedSig, 24)
node _sRoundedExp_T_1 = cvt(_sRoundedExp_T)
node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1)
node _common_expOut_T = bits(sRoundedExp, 8, 0)
connect common_expOut, _common_expOut_T
node _common_fractOut_T = bits(roundedSig, 23, 1)
node _common_fractOut_T_1 = bits(roundedSig, 22, 0)
node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1)
connect common_fractOut, _common_fractOut_T_2
node _common_overflow_T = shr(sRoundedExp, 7)
node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3)))
connect common_overflow, _common_overflow_T_1
node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<8>(0h6b)))
connect common_totalUnderflow, _common_totalUnderflow_T
node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2)
node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1)
node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1)
node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2)
node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T)
node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0)
node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2)
node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3)
node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit)
node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound)
node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2)
node _roundCarry_T = bits(roundedSig, 25, 25)
node _roundCarry_T_1 = bits(roundedSig, 24, 24)
node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1)
node _common_underflow_T = shr(io.in.sExp, 8)
node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0)))
node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1)
node _common_underflow_T_3 = bits(roundMask, 3, 3)
node _common_underflow_T_4 = bits(roundMask, 2, 2)
node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4)
node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5)
node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1))
node _common_underflow_T_8 = bits(roundMask, 4, 4)
node _common_underflow_T_9 = bits(roundMask, 3, 3)
node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9)
node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0))
node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11)
node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry)
node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit)
node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr)
node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0))
node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16)
node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17)
connect common_underflow, _common_underflow_T_18
node _common_inexact_T = or(common_totalUnderflow, anyRound)
connect common_inexact, _common_inexact_T
node isNaNOut = or(io.invalidExc, io.in.isNaN)
node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf)
node _commonCase_T = eq(isNaNOut, UInt<1>(0h0))
node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0))
node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1)
node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0))
node commonCase = and(_commonCase_T_2, _commonCase_T_3)
node overflow = and(commonCase, common_overflow)
node underflow = and(commonCase, common_underflow)
node _inexact_T = and(commonCase, common_inexact)
node inexact = or(overflow, _inexact_T)
node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp)
node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow)
node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd)
node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1)
node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0))
node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T)
node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp)
node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T)
node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign)
node _expOut_T = or(io.in.isZero, common_totalUnderflow)
node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0))
node _expOut_T_2 = not(_expOut_T_1)
node _expOut_T_3 = and(common_expOut, _expOut_T_2)
node _expOut_T_4 = not(UInt<9>(0h6b))
node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0))
node _expOut_T_6 = not(_expOut_T_5)
node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6)
node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0))
node _expOut_T_9 = not(_expOut_T_8)
node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9)
node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0))
node _expOut_T_12 = not(_expOut_T_11)
node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12)
node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0))
node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14)
node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0))
node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16)
node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0))
node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18)
node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0))
node expOut = or(_expOut_T_19, _expOut_T_20)
node _fractOut_T = or(isNaNOut, io.in.isZero)
node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow)
node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0))
node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut)
node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0))
node fractOut = or(_fractOut_T_3, _fractOut_T_4)
node _io_out_T = cat(signOut, expOut)
node _io_out_T_1 = cat(_io_out_T, fractOut)
connect io.out, _io_out_T_1
node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc)
node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow)
node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact)
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_84( // @[RoundAnyRawFNToRecFN.scala:48:5]
input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16]
);
wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19]
wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20]
wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24]
wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14]
wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14]
wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18]
wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18]
wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16]
wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16]
wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:284:13]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53]
wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38]
wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38]
wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49]
wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32]
wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60]
wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53]
wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53]
wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53]
wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53]
wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53]
wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27]
wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63]
wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42]
wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29]
wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42]
wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29]
wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60]
wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45]
wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42]
wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39]
wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49]
wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22]
wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33]
wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66]
wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66]
wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57]
wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37]
wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31]
wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16]
wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31]
wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50]
wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37]
wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31]
wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37]
wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40]
wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37]
wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49]
wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37]
wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37]
wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21]
wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25]
wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26]
wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26]
wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26]
wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26]
wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26]
wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26]
wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26]
wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56]
wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22]
wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22]
wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_42 = _roundMask_T_37 | _roundMask_T_41; // @[primitives.scala:77:20]
wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22]
wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20]
wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20]
wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20]
wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20]
wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20]
wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20]
wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20]
wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20]
wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20]
wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20]
wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20]
wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}]
wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}]
wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17]
wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56]
wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22]
wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22]
wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20]
wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20]
wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22]
wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20]
wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20]
wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58]
wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24]
wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] | doShiftSigDown1}; // @[primitives.scala:62:24]
wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}]
wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41]
wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}]
wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28]
wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}]
wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40]
wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}]
wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67]
wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49]
wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42]
wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}]
wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36]
wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31]
wire [26:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32]
wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}]
wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}]
wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30]
wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30]
wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35]
wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35]
wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}]
wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21]
wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32]
wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}]
wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}]
wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67]
wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}]
wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47]
wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54]
wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}]
wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}]
assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37]
assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37]
wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27]
wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27]
assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27]
assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16]
wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30]
assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}]
assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50]
assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31]
assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31]
wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45]
wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44]
wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61]
wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}]
wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67]
wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}]
wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63]
wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}]
wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 | _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}]
wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46]
wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27]
wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27]
wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27]
wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49]
wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}]
wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}]
wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57]
wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49]
wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71]
wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}]
wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30]
wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49]
wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49]
wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}]
wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34]
wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38]
wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45]
wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}]
wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60]
wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27]
assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76]
assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40]
assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49]
assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49]
wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34]
wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22]
wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36]
wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}]
wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64]
wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}]
wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32]
wire _notNaN_isInfOut_T = overflow; // @[RoundAnyRawFNToRecFN.scala:238:32, :248:45]
wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32]
wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43]
wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}]
wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20]
wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}]
wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22]
wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32]
wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}]
wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}]
wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14]
wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17]
wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17]
wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18]
wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}]
wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14]
wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18]
wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15]
wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16]
wire [8:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16]
wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16]
wire [8:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16]
wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22]
wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}]
wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16]
wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16]
wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11]
wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23]
assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}]
assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33]
wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23]
wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}]
wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}]
assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module Rocket :
input clock : Clock
input reset : Reset
output io : { flip hartid : UInt<1>, flip reset_vector : UInt<32>, flip interrupts : { debug : UInt<1>, mtip : UInt<1>, msip : UInt<1>, meip : UInt<1>, seip : UInt<1>, lip : UInt<1>[0]}, imem : { might_request : UInt<1>, flip clock_enabled : UInt<1>, req : { valid : UInt<1>, bits : { pc : UInt<40>, speculative : UInt<1>}}, sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { btb : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}, pc : UInt<40>, data : UInt<32>, mask : UInt<2>, xcpt : { pf : { inst : UInt<1>}, gf : { inst : UInt<1>}, ae : { inst : UInt<1>}}, replay : UInt<1>}}, flip gpa : { valid : UInt<1>, bits : UInt<40>}, flip gpa_is_pte : UInt<1>, btb_update : { valid : UInt<1>, bits : { prediction : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isValid : UInt<1>, br_pc : UInt<39>, cfiType : UInt<2>}}, bht_update : { valid : UInt<1>, bits : { prediction : { history : UInt<8>, value : UInt<1>}, pc : UInt<39>, branch : UInt<1>, taken : UInt<1>, mispredict : UInt<1>}}, ras_update : { valid : UInt<1>, bits : { cfiType : UInt<2>, returnAddr : UInt<39>}}, flush_icache : UInt<1>, flip npc : UInt<40>, flip perf : { acquire : UInt<1>, tlbMiss : UInt<1>}, progress : UInt<1>}, dmem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}}, s1_kill : UInt<1>, s1_data : { data : UInt<64>, mask : UInt<8>}, flip s2_nack : UInt<1>, flip s2_nack_cause_raw : UInt<1>, s2_kill : UInt<1>, flip s2_uncached : UInt<1>, flip s2_paddr : UInt<32>, flip resp : { valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, data : UInt<64>, mask : UInt<8>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, data_raw : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip s2_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, flip s2_gpa : UInt<40>, flip s2_gpa_is_pte : UInt<1>, flip ordered : UInt<1>, flip store_pending : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>, grant : UInt<1>, tlbMiss : UInt<1>, blocked : UInt<1>, canAcceptStoreThenLoad : UInt<1>, canAcceptStoreThenRMW : UInt<1>, canAcceptLoadThenLoad : UInt<1>, storeBufferEmptyAfterLoad : UInt<1>, storeBufferEmptyAfterStore : UInt<1>}, keep_clock_enabled : UInt<1>, flip clock_enabled : UInt<1>}, flip ptw : { flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], perf : { l2miss : UInt<1>, l2hit : UInt<1>, pte_miss : UInt<1>, pte_hit : UInt<1>}, flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}, clock_enabled : UInt<1>}, flip fpu : { flip hartid : UInt<1>, flip time : UInt<64>, flip inst : UInt<32>, flip fromint_data : UInt<64>, flip fcsr_rm : UInt<3>, fcsr_flags : { valid : UInt<1>, bits : UInt<5>}, flip v_sew : UInt<3>, store_data : UInt<64>, toint_data : UInt<64>, flip ll_resp_val : UInt<1>, flip ll_resp_type : UInt<3>, flip ll_resp_tag : UInt<5>, flip ll_resp_data : UInt<64>, flip valid : UInt<1>, fcsr_rdy : UInt<1>, nack_mem : UInt<1>, illegal_rm : UInt<1>, flip killx : UInt<1>, flip killm : UInt<1>, dec : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, sboard_set : UInt<1>, sboard_clr : UInt<1>, sboard_clra : UInt<5>, flip keep_clock_enabled : UInt<1>}, flip rocc : { flip cmd : { flip ready : UInt<1>, valid : UInt<1>, bits : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { rd : UInt<5>, data : UInt<64>}}, mem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}}, s1_kill : UInt<1>, s1_data : { data : UInt<64>, mask : UInt<8>}, flip s2_nack : UInt<1>, flip s2_nack_cause_raw : UInt<1>, s2_kill : UInt<1>, flip s2_uncached : UInt<1>, flip s2_paddr : UInt<32>, flip resp : { valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, data : UInt<64>, mask : UInt<8>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, data_raw : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip s2_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, flip s2_gpa : UInt<40>, flip s2_gpa_is_pte : UInt<1>, flip ordered : UInt<1>, flip store_pending : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>, grant : UInt<1>, tlbMiss : UInt<1>, blocked : UInt<1>, canAcceptStoreThenLoad : UInt<1>, canAcceptStoreThenRMW : UInt<1>, canAcceptLoadThenLoad : UInt<1>, storeBufferEmptyAfterLoad : UInt<1>, storeBufferEmptyAfterStore : UInt<1>}, keep_clock_enabled : UInt<1>, flip clock_enabled : UInt<1>}, busy : UInt<1>, interrupt : UInt<1>, flip exception : UInt<1>, flip csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[0]}, trace : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], time : UInt<64>}, bpwatch : { valid : UInt<1>[1], rvalid : UInt<1>[1], wvalid : UInt<1>[1], ivalid : UInt<1>[1], action : UInt<3>}[1], cease : UInt<1>, wfi : UInt<1>, flip traceStall : UInt<1>}
regreset clock_en_reg : UInt<1>, clock, reset, UInt<1>(0h1)
reg long_latency_stall : UInt<1>, clock
reg id_reg_pause : UInt<1>, clock
reg imem_might_request_reg : UInt<1>, clock
wire clock_en : UInt<1>
connect clock_en, UInt<1>(0h1)
wire _hits_WIRE : UInt<1>[18]
connect _hits_WIRE[0], UInt<1>(0h0)
connect _hits_WIRE[1], UInt<1>(0h0)
connect _hits_WIRE[2], UInt<1>(0h0)
connect _hits_WIRE[3], UInt<1>(0h0)
connect _hits_WIRE[4], UInt<1>(0h0)
connect _hits_WIRE[5], UInt<1>(0h0)
connect _hits_WIRE[6], UInt<1>(0h0)
connect _hits_WIRE[7], UInt<1>(0h0)
connect _hits_WIRE[8], UInt<1>(0h0)
connect _hits_WIRE[9], UInt<1>(0h0)
connect _hits_WIRE[10], UInt<1>(0h0)
connect _hits_WIRE[11], UInt<1>(0h0)
connect _hits_WIRE[12], UInt<1>(0h0)
connect _hits_WIRE[13], UInt<1>(0h0)
connect _hits_WIRE[14], UInt<1>(0h0)
connect _hits_WIRE[15], UInt<1>(0h0)
connect _hits_WIRE[16], UInt<1>(0h0)
connect _hits_WIRE[17], UInt<1>(0h0)
wire hits : UInt<1>[18]
connect hits, _hits_WIRE
wire _hits_WIRE_1 : UInt<1>[11]
connect _hits_WIRE_1[0], UInt<1>(0h0)
connect _hits_WIRE_1[1], UInt<1>(0h0)
connect _hits_WIRE_1[2], UInt<1>(0h0)
connect _hits_WIRE_1[3], UInt<1>(0h0)
connect _hits_WIRE_1[4], UInt<1>(0h0)
connect _hits_WIRE_1[5], UInt<1>(0h0)
connect _hits_WIRE_1[6], UInt<1>(0h0)
connect _hits_WIRE_1[7], UInt<1>(0h0)
connect _hits_WIRE_1[8], UInt<1>(0h0)
connect _hits_WIRE_1[9], UInt<1>(0h0)
connect _hits_WIRE_1[10], UInt<1>(0h0)
wire hits_1 : UInt<1>[11]
connect hits_1, _hits_WIRE_1
wire _hits_WIRE_2 : UInt<1>[6]
connect _hits_WIRE_2[0], UInt<1>(0h0)
connect _hits_WIRE_2[1], UInt<1>(0h0)
connect _hits_WIRE_2[2], UInt<1>(0h0)
connect _hits_WIRE_2[3], UInt<1>(0h0)
connect _hits_WIRE_2[4], UInt<1>(0h0)
connect _hits_WIRE_2[5], UInt<1>(0h0)
wire hits_2 : UInt<1>[6]
connect hits_2, _hits_WIRE_2
reg ex_ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>}, clock
reg mem_ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>}, clock
reg wb_ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>}, clock
reg ex_reg_xcpt_interrupt : UInt<1>, clock
reg ex_reg_valid : UInt<1>, clock
reg ex_reg_rvc : UInt<1>, clock
reg ex_reg_btb_resp : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}, clock
reg ex_reg_xcpt : UInt<1>, clock
reg ex_reg_flush_pipe : UInt<1>, clock
reg ex_reg_load_use : UInt<1>, clock
reg ex_reg_cause : UInt, clock
reg ex_reg_replay : UInt<1>, clock
reg ex_reg_pc : UInt, clock
reg ex_reg_mem_size : UInt, clock
reg ex_reg_hls : UInt<1>, clock
reg ex_reg_inst : UInt, clock
reg ex_reg_raw_inst : UInt, clock
reg ex_reg_wphit : UInt<1>[1], clock
reg ex_reg_set_vconfig : UInt<1>, clock
reg mem_reg_xcpt_interrupt : UInt<1>, clock
reg mem_reg_valid : UInt<1>, clock
reg mem_reg_rvc : UInt<1>, clock
reg mem_reg_btb_resp : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}, clock
reg mem_reg_xcpt : UInt<1>, clock
reg mem_reg_replay : UInt<1>, clock
reg mem_reg_flush_pipe : UInt<1>, clock
reg mem_reg_cause : UInt, clock
reg mem_reg_slow_bypass : UInt<1>, clock
reg mem_reg_load : UInt<1>, clock
reg mem_reg_store : UInt<1>, clock
reg mem_reg_set_vconfig : UInt<1>, clock
reg mem_reg_sfence : UInt<1>, clock
reg mem_reg_pc : UInt, clock
reg mem_reg_inst : UInt, clock
reg mem_reg_mem_size : UInt, clock
reg mem_reg_hls_or_dv : UInt<1>, clock
reg mem_reg_raw_inst : UInt, clock
reg mem_reg_wdata : UInt, clock
reg mem_reg_rs2 : UInt, clock
reg mem_br_taken : UInt<1>, clock
wire take_pc_mem : UInt<1>
reg mem_reg_wphit : UInt<1>[1], clock
reg wb_reg_valid : UInt<1>, clock
reg wb_reg_xcpt : UInt<1>, clock
reg wb_reg_replay : UInt<1>, clock
reg wb_reg_flush_pipe : UInt<1>, clock
reg wb_reg_cause : UInt, clock
reg wb_reg_set_vconfig : UInt<1>, clock
reg wb_reg_sfence : UInt<1>, clock
reg wb_reg_pc : UInt, clock
reg wb_reg_mem_size : UInt, clock
reg wb_reg_hls_or_dv : UInt<1>, clock
reg wb_reg_hfence_v : UInt<1>, clock
reg wb_reg_hfence_g : UInt<1>, clock
reg wb_reg_inst : UInt, clock
reg wb_reg_raw_inst : UInt, clock
reg wb_reg_wdata : UInt, clock
reg wb_reg_rs2 : UInt, clock
wire take_pc_wb : UInt<1>
reg wb_reg_wphit : UInt<1>[1], clock
node take_pc_mem_wb = or(take_pc_wb, take_pc_mem)
inst ibuf of IBuf
connect ibuf.clock, clock
connect ibuf.reset, reset
connect ibuf.io.imem, io.imem.resp
connect ibuf.io.kill, take_pc_mem_wb
wire id_ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>}
wire id_ctrl_decoder_decoded_plaInput : UInt<32>
node id_ctrl_decoder_decoded_invInputs = not(id_ctrl_decoder_decoded_plaInput)
wire id_ctrl_decoder_decoded : UInt<42>
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi, id_ctrl_decoder_decoded_andMatrixOutputs_lo)
node id_ctrl_decoder_decoded_andMatrixOutputs_99_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_1)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_1)
node id_ctrl_decoder_decoded_andMatrixOutputs_102_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_1 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_1)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_1)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_2)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_lo_2)
node id_ctrl_decoder_decoded_andMatrixOutputs_9_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_3)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_lo_3)
node id_ctrl_decoder_decoded_andMatrixOutputs_29_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_2 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_2)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_2)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_4)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_4)
node id_ctrl_decoder_decoded_andMatrixOutputs_139_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_3 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_3)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_5)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_5)
node id_ctrl_decoder_decoded_andMatrixOutputs_117_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_4 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_1 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_1)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_4)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_6)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_6)
node id_ctrl_decoder_decoded_andMatrixOutputs_96_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_lo_7)
node id_ctrl_decoder_decoded_andMatrixOutputs_35_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_7)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_7)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_lo_8)
node id_ctrl_decoder_decoded_andMatrixOutputs_182_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_8)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_5 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_5)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_5)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_8)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_lo_9)
node id_ctrl_decoder_decoded_andMatrixOutputs_128_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_9)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_6 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_6)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_6)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_9)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_lo_10)
node id_ctrl_decoder_decoded_andMatrixOutputs_67_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_10)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_7 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_2 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_7)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_7)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_10)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_lo_11)
node id_ctrl_decoder_decoded_andMatrixOutputs_78_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_11)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_8 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_3 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_1 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_1 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_1 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_1 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_1 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_1 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_1)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_1)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_1)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_1)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_1)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_8)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_8)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_1)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_1)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_11)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_lo_12)
node id_ctrl_decoder_decoded_andMatrixOutputs_190_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_9 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_4 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_2 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_2 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_2 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_2 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_2)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_2)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_4)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_2)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_9)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_2)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_12)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_lo_13)
node id_ctrl_decoder_decoded_andMatrixOutputs_7_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_10 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_5 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_3 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_3 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_3 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_3 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_2 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_2 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_2)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_2)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_3)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_3)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_14 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_2)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_14 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_10)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_10)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_2)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_14 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_3)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_14 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_13)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_14 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_lo_14)
node id_ctrl_decoder_decoded_andMatrixOutputs_98_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_11 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_6 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_4 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_4 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_4 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_4 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_3 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_3 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_3)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_3)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_4)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_4)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_3)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_11)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_11)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_14 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_3)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_4)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_14)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_lo_15)
node id_ctrl_decoder_decoded_andMatrixOutputs_32_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_15)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_15 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_12 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_7 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_5 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_5 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_5 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_5 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_4 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_4 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_4)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_5)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_5)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_4)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_12)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_12)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_4)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_5)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_15)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_lo_16)
node id_ctrl_decoder_decoded_andMatrixOutputs_71_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_16)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_17 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_17 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_17 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_17 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_lo_17)
node id_ctrl_decoder_decoded_andMatrixOutputs_181_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_17)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_17 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_18 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_18 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_18 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_18 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_lo_18)
node id_ctrl_decoder_decoded_andMatrixOutputs_145_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_18)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_18 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_19 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_19 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_19 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_19 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_lo_19)
node id_ctrl_decoder_decoded_andMatrixOutputs_143_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_19)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_16 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_13 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_8 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_6 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_6 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_6)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_13)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_19 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_8)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_20 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_13)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_20 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_20 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_16)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_20 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_lo_20)
node id_ctrl_decoder_decoded_andMatrixOutputs_20_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_20)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_17 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_14 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_9 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_7 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_7 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_14 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_7)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_14)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_20 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_9)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_21 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_14)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_17 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_21 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_21 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_17)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_21 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_lo_21)
node id_ctrl_decoder_decoded_andMatrixOutputs_22_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_21)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_18 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_15 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_15)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_21 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_22 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_15)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_18 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_22 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_22 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_18)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_22 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_lo_22)
node id_ctrl_decoder_decoded_andMatrixOutputs_97_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_22)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_19 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_16 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_10 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_10)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_22 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_19)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_23 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_16)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_19 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_23 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_23 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_19)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_23 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_lo_23)
node id_ctrl_decoder_decoded_andMatrixOutputs_39_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_23)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_20 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_17 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_11 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_17 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_11)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_23 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_20)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_24 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_17)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_20 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_24 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_24 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_20)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_24 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_lo_24)
node id_ctrl_decoder_decoded_andMatrixOutputs_131_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_24)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_21 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_18 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_12 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_8 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_18 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_8)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_21)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_24 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_18)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_25 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_18)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_21 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_25 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_25 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_21)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_25 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_lo_25)
node id_ctrl_decoder_decoded_andMatrixOutputs_191_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_22 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_25 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_26 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_22)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_22 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_26 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_26 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_22)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_26 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_lo_26)
node id_ctrl_decoder_decoded_andMatrixOutputs_164_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27 = bits(id_ctrl_decoder_decoded_invInputs, 7, 7)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26 = bits(id_ctrl_decoder_decoded_invInputs, 8, 8)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_23 = bits(id_ctrl_decoder_decoded_invInputs, 9, 9)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_19 = bits(id_ctrl_decoder_decoded_invInputs, 10, 10)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_13 = bits(id_ctrl_decoder_decoded_invInputs, 11, 11)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_9 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_8 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_6 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_6 = bits(id_ctrl_decoder_decoded_invInputs, 15, 15)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_5 = bits(id_ctrl_decoder_decoded_invInputs, 16, 16)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_5 = bits(id_ctrl_decoder_decoded_invInputs, 17, 17)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_1 = bits(id_ctrl_decoder_decoded_invInputs, 18, 18)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16 = bits(id_ctrl_decoder_decoded_invInputs, 19, 19)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_19 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_1)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_1)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_26 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_5)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_27 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_19)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_6)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_5)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_8)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_13)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_23 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_5)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_23)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_27 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_6)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_27 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_23)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_27 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_lo_27)
node id_ctrl_decoder_decoded_andMatrixOutputs_55_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_24 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_20 = bits(id_ctrl_decoder_decoded_invInputs, 7, 7)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_14 = bits(id_ctrl_decoder_decoded_invInputs, 8, 8)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_10 = bits(id_ctrl_decoder_decoded_invInputs, 9, 9)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_9 = bits(id_ctrl_decoder_decoded_invInputs, 10, 10)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_7 = bits(id_ctrl_decoder_decoded_invInputs, 11, 11)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_7 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_6 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_6 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_2 = bits(id_ctrl_decoder_decoded_invInputs, 15, 15)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_1 = bits(id_ctrl_decoder_decoded_invInputs, 16, 16)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_1 = bits(id_ctrl_decoder_decoded_invInputs, 17, 17)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_1 = bits(id_ctrl_decoder_decoded_invInputs, 18, 18)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_1 = bits(id_ctrl_decoder_decoded_invInputs, 19, 19)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_1 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_1 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_1 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_1 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_1 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_1 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_1 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_1 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_1)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_1)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_1)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_20 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_2)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_1)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_1)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_1)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_1)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_1)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_27 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_6)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_28 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_20)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_2)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_6)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_7)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_10)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_1)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_24 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_6)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_20)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_14 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_1)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_28 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_7)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_28 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_24)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_28 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_lo_28)
node id_ctrl_decoder_decoded_andMatrixOutputs_90_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_25 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_28 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_29 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_25)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_25 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_29 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_29 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_25)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_29 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_lo_29)
node id_ctrl_decoder_decoded_andMatrixOutputs_30_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_26 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_21 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_21 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_21)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_29 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_30 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_21)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_26 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_30 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_30 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_26)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_30 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_lo_30)
node id_ctrl_decoder_decoded_andMatrixOutputs_26_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_27 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_22 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_22 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_22)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_30 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_31 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_22)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_27 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_31 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_31 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_27)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_31 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_lo_31)
node id_ctrl_decoder_decoded_andMatrixOutputs_175_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_31)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_28 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_23 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_15 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_23 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_15)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_31 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_28)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_32 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_23)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_28 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_32 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_32 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_28)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_32 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_lo_32)
node id_ctrl_decoder_decoded_andMatrixOutputs_77_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_32)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_29 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_24 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_16 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_11 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_24 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_11)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_29)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_32 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_24)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_33 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_24)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_29 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_33 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_33 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_29)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_33 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_lo_33)
node id_ctrl_decoder_decoded_andMatrixOutputs_21_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_33)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_30 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_25 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_17 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_12 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_10 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_8 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_8 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_7 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_8)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_25 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_7)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_10)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_17)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_33 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_7)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_34 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_25)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_30 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_30)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_17 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_34 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_8)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_34 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_30)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_34 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_lo_34)
node id_ctrl_decoder_decoded_andMatrixOutputs_121_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_34)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_31 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_26 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_18 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_13 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_11 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_9 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_9 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_8 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_7 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_8)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_26 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_7)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_9)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_13)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_34 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_8)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_35 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_26)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_26)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_31 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_7)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_18 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_35 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_9)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_35 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_31)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_35 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_lo_35)
node id_ctrl_decoder_decoded_andMatrixOutputs_61_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_35)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_32 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_27 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_19 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_14 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_12 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_10 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_10 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_9 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_8 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_9)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_27 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_8)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_10)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_14 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_14)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_35 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_9)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_36 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_27)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_27)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_32 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_8)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_19 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_36 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_10)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_36 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_32)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_36 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_lo_36)
node id_ctrl_decoder_decoded_andMatrixOutputs_105_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_36)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_33 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_28 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_20 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_15 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_13 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_11 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_11 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_10 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_9 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_3 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_3)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_10)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_28 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_3)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_11)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_15)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_36 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_10)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_37 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_28)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_28)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_33 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_9)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_20 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_37 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_11)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_37 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_33)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_37 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_lo_37)
node id_ctrl_decoder_decoded_andMatrixOutputs_24_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_37)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_34 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_29 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_29 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_29)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_37 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_38 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_29)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_34 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_38 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_38 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_34)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_38 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_lo_38)
node id_ctrl_decoder_decoded_andMatrixOutputs_165_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_38)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_35 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_30 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_21 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_30 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_21)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_38 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_35)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_39 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_30)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_35 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_21 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_39 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_39 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_35)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_39 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_lo_39)
node id_ctrl_decoder_decoded_andMatrixOutputs_160_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_39)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_36 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_31 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_31 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_39 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_40 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_31)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_36 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_40 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_40 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_36)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_40 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_lo_40)
node id_ctrl_decoder_decoded_andMatrixOutputs_95_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_40)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_40 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_37 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_32 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_22 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_32 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_22)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_40 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_37)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_41 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_32)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_37 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_22 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_41 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_41 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_37)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_41 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_lo_41)
node id_ctrl_decoder_decoded_andMatrixOutputs_56_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_41)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_41 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_38 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_33 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_23 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_33 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_23)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_41 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_38)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_42 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_33)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_38 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_23 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_42 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_42 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_38)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_42 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_lo_42)
node id_ctrl_decoder_decoded_andMatrixOutputs_16_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_42)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_42 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_39 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_34 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_34 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_34)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_42 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_42)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_43 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_34)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_39 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_43 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_43 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_39)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_43 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_lo_43)
node id_ctrl_decoder_decoded_andMatrixOutputs_185_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_43)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_43 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_40 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_43 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_43)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_44 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_40)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_40 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_44 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_44 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_40)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_44 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_lo_44)
node id_ctrl_decoder_decoded_andMatrixOutputs_140_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_44)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_44 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_41 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_35 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_35 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_35)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_44 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_44)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_45 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_35)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_41 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_45 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_45 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_41)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_45 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_lo_45)
node id_ctrl_decoder_decoded_andMatrixOutputs_53_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_45)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_45 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_42 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_36 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_36 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_36)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_45 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_45)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_46 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_36)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_42 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_46 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_46 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_42)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_46 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_lo_46)
node id_ctrl_decoder_decoded_andMatrixOutputs_193_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_46)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_46 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_43 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_37 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_24 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_37 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_24)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_46 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_43)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_47 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_37)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_43 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_24 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_47 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_47 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_43)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_47 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_lo_47)
node id_ctrl_decoder_decoded_andMatrixOutputs_92_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_47)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_47 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_44 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_38 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_38 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_38)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_47 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_47)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_48 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_38)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_44 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_48 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_48 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_44)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_48 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_lo_48)
node id_ctrl_decoder_decoded_andMatrixOutputs_17_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_48)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_48 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_45 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_39 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_25 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_39 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_25)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_48 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_45)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_49 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_39)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_45 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_25 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_49 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_49 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_45)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_49 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_lo_49)
node id_ctrl_decoder_decoded_andMatrixOutputs_129_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_49)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_49 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_46 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_40 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_40 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_40)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_49 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_49)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_50 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_40)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_46 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_50 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_50 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_46)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_50 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_lo_50)
node id_ctrl_decoder_decoded_andMatrixOutputs_177_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_50)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_50 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_47 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_41 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_26 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_41 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_26)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_50 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_47)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_51 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_41)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_47 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_26 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_51 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_51 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_47)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_51 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_lo_51)
node id_ctrl_decoder_decoded_andMatrixOutputs_123_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_51)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_51 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_48 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_42 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_27 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_16 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_14 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_42 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_14)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_42)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_51 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_27)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_52 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_42)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_14 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_48 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_51)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_27 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_52 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_52 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_48)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_52 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_lo_52)
node id_ctrl_decoder_decoded_andMatrixOutputs_14_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_52)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_52 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_49 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_43 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_28 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_17 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_15 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_12 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_12 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_11 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_10 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_11)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_43 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_10)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_12)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_17 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_17)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_52 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_11)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_53 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_43)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_43)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_52)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_49 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_10)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_28 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_53 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_12)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_53 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_49)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_53 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_lo_53)
node id_ctrl_decoder_decoded_andMatrixOutputs_132_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_53)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_53 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_50 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_44 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_29 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_18 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_16 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_13 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_13 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_12 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_11 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_4 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_4)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_12)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_44 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_4)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_13)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_18 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_18)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_53 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_12)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_54 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_44)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_44)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_53)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_50 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_11)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_29 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_54 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_13)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_54 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_50)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_54 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_lo_54)
node id_ctrl_decoder_decoded_andMatrixOutputs_49_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_54)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_54 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_51 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_45 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_45 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_45)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_54 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_54)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_55 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_45)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_51 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_55 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_55 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_51)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_55 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_lo_55)
node id_ctrl_decoder_decoded_andMatrixOutputs_155_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_55)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_56 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_55 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_52 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_46 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_30 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_46 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_30)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_55 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_52)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_56 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_46)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_52 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_56)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_30 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_56 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_56 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_52)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_56 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_lo_56)
node id_ctrl_decoder_decoded_andMatrixOutputs_184_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_56)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_57 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_56 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_53 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_47 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_31 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_47 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_56 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_53)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_57 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_47)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_53 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_57)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_31 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_57 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_57 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_53)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_57 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_lo_57)
node id_ctrl_decoder_decoded_andMatrixOutputs_148_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_57)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_58 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_57 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_54 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_48 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_32 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_48 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_32)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_57 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_54)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_58 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_48)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_54 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_58)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_32 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_58 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_58 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_54)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_58 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_lo_58)
node id_ctrl_decoder_decoded_andMatrixOutputs_115_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_58)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_59 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_58 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_55 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_49 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_33 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_19 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_17 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_14 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_14 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_13 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_12 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_14 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_13)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_49 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_12)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_14)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_19 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_19)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_58 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_13)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_59 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_49)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_49)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_17 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_58)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_55 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_12)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_14 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_33 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_59 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_14)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_59 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_55)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_59 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_lo_59)
node id_ctrl_decoder_decoded_andMatrixOutputs_162_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_59)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_60 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_59 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_56 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_50 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_34 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_50 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_34)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_59 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_56)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_60 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_50)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_56 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_60)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_34 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_60 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_60 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_56)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_60 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_lo_60)
node id_ctrl_decoder_decoded_andMatrixOutputs_44_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_60)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_61 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_60 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_57 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_51 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_35 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_20 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_18 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_15 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_15 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_14 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_15)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_51 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_14)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_14 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_18)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_20 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_35)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_60 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_14)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_61 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_51)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_18 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_60)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_57 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_57)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_35 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_61 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_15)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_61 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_57)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_61 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_lo_61)
node id_ctrl_decoder_decoded_andMatrixOutputs_126_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_61)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_62 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_61 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_58 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_52 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_36 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_21 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_19 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_16 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_16 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_15 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_16)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_52 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_15)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_19)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_21 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_36)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_61 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_15)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_62 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_52)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_19 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_61)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_58 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_58)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_36 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_62 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_16)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_62 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_58)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_62 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_lo_62)
node id_ctrl_decoder_decoded_andMatrixOutputs_150_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_62)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_63 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_62 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_59 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_53 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_53 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_53)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_62 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_62)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_63 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_53)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_59 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_63 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_63 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_59)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_63 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_lo_63)
node id_ctrl_decoder_decoded_andMatrixOutputs_161_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_63)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_64 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_63 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_60 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_54 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_37 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_22 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_20 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_17 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_17 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_16 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_13 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_17 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_16)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_54 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_13)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_17)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_22 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_22)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_63 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_16)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_64 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_54)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_54)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_20 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_63)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_60 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_13)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_17 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_37 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_64 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_17)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_64 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_60)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_64 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_lo_64)
node id_ctrl_decoder_decoded_andMatrixOutputs_133_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_64)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_65 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_65 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_64 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_61 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_55 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_38 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_23 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_21 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_18 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_18 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_17 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_14 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_18 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_17)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_55 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_14)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_17 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_18)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_23 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_23)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_64 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_17)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_65 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_55)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_14 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_55)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_21 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_64)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_61 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_14)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_18 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_65)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_38 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_65 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_18)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_65 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_61)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_65 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_lo_65)
node id_ctrl_decoder_decoded_andMatrixOutputs_179_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_65)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_66 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_66 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_66 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_66 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_66 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_65 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_62 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_56 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_39 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_24 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_22 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_19 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_19 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_18 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_15 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_5 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_5)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_19 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_18)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_56 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_5)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_18 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_19)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_24 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_24)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_65 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_18)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_66 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_56)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_56)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_22 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_65)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_62 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_15)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_19 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_66)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_39 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_66)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_66 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_19)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_66 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_62)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_66 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_lo_66)
node id_ctrl_decoder_decoded_andMatrixOutputs_5_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_66)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_67 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_67 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_67 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_67 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_67 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_66 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_63 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_57 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_40 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_25 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_23 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_20 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_20 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_19 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_16 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_20 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_19)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_57 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_16)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_19 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_20)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_25 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_25)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_66 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_19)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_67 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_57)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_57)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_23 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_66)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_63 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_16)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_20 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_67)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_40 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_67)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_67 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_20)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_67 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_63)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_67 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_lo_67)
node id_ctrl_decoder_decoded_andMatrixOutputs_88_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_67)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_68 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_68 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_68 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_68 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_68 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_67 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_64 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_58 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_41 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_26 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_24 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_21 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_21 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_20 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_17 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_21 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_20)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_58 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_17)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_20 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_21)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_26 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_26)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_67 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_20)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_68 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_58)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_17 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_58)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_24 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_67)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_64 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_17)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_21 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_68)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_41 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_68)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_68 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_21)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_68 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_64)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_68 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_lo_68)
node id_ctrl_decoder_decoded_andMatrixOutputs_94_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_68)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_69 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_69 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_69 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_69 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_69 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_68 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_65 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_59 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_59 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_59)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_68 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_68)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_69 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_59)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_65 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_69)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_69 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_69)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_69 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_65)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_69 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_lo_69)
node id_ctrl_decoder_decoded_andMatrixOutputs_66_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_69)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_70 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_70 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_70 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_70 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_70 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_69 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_66 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_60 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_42 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_60 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_42)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_69 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_66)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_70 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_60)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_66 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_70)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_42 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_70)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_70 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_70)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_70 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_66)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_70 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_lo_70)
node id_ctrl_decoder_decoded_andMatrixOutputs_125_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_70)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_71 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_71 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_71 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_71 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_71 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_70 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_67 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_61 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_43 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_61 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_43)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_70 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_67)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_71 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_61)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_67 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_71)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_43 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_71)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_71 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_71)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_71 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_67)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_71 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_lo_71)
node id_ctrl_decoder_decoded_andMatrixOutputs_91_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_71)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_72 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_72 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_72 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_72 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_72 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_71 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_68 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_62 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_44 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_62 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_44)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_71 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_68)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_72 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_62)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_68 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_72)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_44 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_72)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_72 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_72)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_72 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_68)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_72 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_lo_72)
node id_ctrl_decoder_decoded_andMatrixOutputs_112_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_72)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_73 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_73 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_73 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_73 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_73 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_72 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_69 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_63 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_45 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_27 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_25 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_22 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_22 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_21 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_18 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_22 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_21)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_63 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_18)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_21 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_22)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_27 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_27)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_72 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_21)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_73 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_63)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_18 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_63)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_25 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_72)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_69 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_18)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_22 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_73)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_45 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_73)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_73 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_22)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_73 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_69)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_73 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_lo_73)
node id_ctrl_decoder_decoded_andMatrixOutputs_170_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_73)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_74 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_74 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_74 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_74 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_74 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_73 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_70 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_64 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_64 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_64)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_73 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_73)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_74 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_64)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_70 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_74)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_74 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_74)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_74 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_70)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_74 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_lo_74)
node id_ctrl_decoder_decoded_andMatrixOutputs_146_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_74)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_75 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_75 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_75 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_75 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_75 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_74 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_71 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_65 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_46 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_65 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_46)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_74 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_71)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_75 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_65)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_71 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_75)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_46 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_75)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_75 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_75)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_75 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_71)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_75 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_lo_75)
node id_ctrl_decoder_decoded_andMatrixOutputs_168_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_75)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_76 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_76 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_76 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_76 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_76 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_75 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_72 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_66 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_47 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_66 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_47)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_75 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_72)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_76 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_66)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_72 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_76)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_47 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_76)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_76 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_76)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_76 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_72)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_76 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_lo_76)
node id_ctrl_decoder_decoded_andMatrixOutputs_2_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_76)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_77 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_77 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_77 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_77 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_77 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_76 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_73 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_67 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_48 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_28 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_67 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_28)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_28 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_73)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_76 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_67)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_77 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_67)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_73 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_77)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_48 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_77)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_77 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_77)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_77 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_73)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_77 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_lo_77)
node id_ctrl_decoder_decoded_andMatrixOutputs_15_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_77)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_78 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_78 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_78 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_78 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_78 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_77 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_74 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_68 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_49 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_29 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_26 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_23 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_23 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_22 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_23 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_23)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_68 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_22)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_22 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_26)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_29 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_49)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_77 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_22)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_78 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_68)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_26 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_77)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_74 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_74)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_23 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_78)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_49 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_78)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_78 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_23)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_78 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_74)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_78 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_lo_78)
node id_ctrl_decoder_decoded_andMatrixOutputs_176_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_78)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_79 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_79 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_79 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_79 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_79 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_78 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_75 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_69 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_50 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_30 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_27 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_24 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_24 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_23 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_19 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_24 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_23)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_69 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_19)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_23 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_24)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_30 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_30)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_78 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_23)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_79 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_69)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_19 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_69)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_27 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_78)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_75 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_19)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_24 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_79)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_50 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_79)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_79 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_24)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_79 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_75)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_79 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_lo_79)
node id_ctrl_decoder_decoded_andMatrixOutputs_172_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_79)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_80 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_80 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_80 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_80 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_80 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_79 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_76 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_79 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_79)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_80 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_76)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_76 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_80)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_80 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_80)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_80 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_76)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_80 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_lo_80)
node id_ctrl_decoder_decoded_andMatrixOutputs_76_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_80)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_81 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_81 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_81 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_81 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_81 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_80 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_77 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_70 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_51 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_31 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_28 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_25 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_25 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_28)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_70 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_25)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_31 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_70)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_80 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_51)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_81 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_70)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_28 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_81)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_77 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_80)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_51 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_81)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_81 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_81)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_81 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_77)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_81 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_lo_81)
node id_ctrl_decoder_decoded_andMatrixOutputs_87_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_81)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_82 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_82 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_82 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_82 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_82 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_81 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_78 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_71 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_52 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_32 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_29 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_26 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_25 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_24 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_20 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_26 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_24)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_71 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_20)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_24 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_26)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_32 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_32)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_81 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_24)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_82 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_71)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_20 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_71)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_29 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_81)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_78 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_20)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_25 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_82)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_52 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_82)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_82 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_25)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_82 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_78)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_82 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_lo_82)
node id_ctrl_decoder_decoded_andMatrixOutputs_144_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_82)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_83 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_83 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_83 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_83 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_83 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_82 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_79 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_72 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_53 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_33 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_30 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_27 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_26 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_25 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_21 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_27 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_25)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_72 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_21)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_25 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_27)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_33 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_33)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_82 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_25)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_83 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_72)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_21 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_72)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_30 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_82)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_79 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_21)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_26 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_83)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_53 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_83)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_83 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_26)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_83 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_79)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_83 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_lo_83)
node id_ctrl_decoder_decoded_andMatrixOutputs_36_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_83)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_84 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_84 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_84 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_84 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_84 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_83 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_80 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_73 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_54 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_34 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_31 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_28 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_27 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_26 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_28 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_27)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_73 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_26)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_26 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_34 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_54)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_83 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_26)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_84 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_73)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_31 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_83)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_80 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_80)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_27 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_84)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_54 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_84)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_84 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_27)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_84 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_80)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_84 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_lo_84)
node id_ctrl_decoder_decoded_andMatrixOutputs_41_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_84)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_85 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_85 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_85 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_85 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_85 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_84 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_81 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_74 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_55 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_35 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_32 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_29 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_28 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_27 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_29 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_28)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_74 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_27)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_27 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_32)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_35 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_55)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_84 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_27)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_85 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_74)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_32 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_84)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_81 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_81)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_28 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_85)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_55 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_85)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_85 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_28)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_85 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_81)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_85 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_lo_85)
node id_ctrl_decoder_decoded_andMatrixOutputs_8_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_85)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_86 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_86 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_86 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_86 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_86 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_85 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_82 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_75 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_56 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_36 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_33 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_30 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_29 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_28 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_22 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_30 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_28)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_75 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_22)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_28 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_30)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_36 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_36)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_85 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_28)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_86 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_75)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_22 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_75)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_33 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_85)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_82 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_22)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_29 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_86)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_56 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_86)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_86 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_29)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_86 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_82)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_86 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_lo_86)
node id_ctrl_decoder_decoded_andMatrixOutputs_104_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_86)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_87 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_87 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_87 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_87 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_87 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_86 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_83 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_76 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_57 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_37 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_34 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_31 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_30 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_29 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_23 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_31 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_29)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_76 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_23)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_29 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_37 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_37)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_86 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_29)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_87 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_76)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_23 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_76)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_34 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_86)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_83 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_23)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_30 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_87)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_57 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_87)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_87 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_30)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_87 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_83)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_87 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_lo_87)
node id_ctrl_decoder_decoded_andMatrixOutputs_73_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_87)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_88 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_88 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_88 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_88 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_88 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_87 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_84 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_77 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_58 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_38 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_35 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_32 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_31 = bits(id_ctrl_decoder_decoded_plaInput, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_30 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_24 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_6 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_2 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_2)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_32 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_24)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_77 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_6)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_30 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_38 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_35)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_87 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_30)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_88 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_77)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_24 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_58)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_35 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_84)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_84 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_24)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_31 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_88)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_88)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_58 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_88)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_88 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_31)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_88 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_84)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_88 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_lo_88)
node id_ctrl_decoder_decoded_andMatrixOutputs_189_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_88)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_89 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_89 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_89 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_89 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_89 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_88 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_85 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_78 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_59 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_39 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_36 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_33 = bits(id_ctrl_decoder_decoded_plaInput, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_32 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_31 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_25 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_7 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_7)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_33 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_78 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_7)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_31 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_33)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_39 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_39)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_88 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_89 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_78)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_25 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_78)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_36 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_88)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_85 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_25)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_32 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_89)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_59 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_89)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_89 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_32)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_89 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_85)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_89 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_lo_89)
node id_ctrl_decoder_decoded_andMatrixOutputs_28_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_89)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_90 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_90 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_90 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_90 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_90 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_89 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_86 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_79 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_60 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_40 = bits(id_ctrl_decoder_decoded_plaInput, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_37 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_34 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_33 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_34 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_34)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_79 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_33)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_40 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_60)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_89 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_40)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_90 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_79)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_37 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_89)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_86 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_86)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_33 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_90)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_60 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_90)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_90 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_33)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_90 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_86)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_90 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_lo_90)
node id_ctrl_decoder_decoded_andMatrixOutputs_0_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_90)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_91 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_91 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_91 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_91 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_91 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_90 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_87 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_80 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_61 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_41 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_38 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_35 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_34 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_32 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_26 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_8 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_3 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_2 = bits(id_ctrl_decoder_decoded_plaInput, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_2 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_2 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_2 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_2 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_2)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_2)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_35 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_2)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_80 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_8)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_8)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_32 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_3)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_34)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_41 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_32)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_90 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_32)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_91 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_80)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_26 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_38)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_80)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_38 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_61)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_87 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_26)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_91)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_34 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_90)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_91)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_61 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_91)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_91 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_34)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_91 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_87)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_91 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_lo_91)
node id_ctrl_decoder_decoded_andMatrixOutputs_60_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_91)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_92 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_92 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_92 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_92 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_92 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_91 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_88 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_81 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_62 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_42 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_39 = bits(id_ctrl_decoder_decoded_plaInput, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_36 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_35 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_33 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_27 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_36 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_33)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_81 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_27)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_33 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_36)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_42 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_42)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_91 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_33)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_92 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_81)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_27 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_81)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_39 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_91)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_88 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_27)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_35 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_92)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_62 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_92)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_92 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_35)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_92 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_88)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_92 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_lo_92)
node id_ctrl_decoder_decoded_andMatrixOutputs_48_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_92)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_93 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_93 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_93 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_93 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_93 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_92 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_89 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_82 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_63 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_43 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_40 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_37 = bits(id_ctrl_decoder_decoded_plaInput, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_36 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_34 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_28 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_9 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_9)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_37 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_34)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_82 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_9)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_34 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_37)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_43 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_43)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_92 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_34)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_93 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_82)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_28 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_82)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_40 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_92)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_89 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_28)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_36 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_93)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_63 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_93)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_93 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_36)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_93 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_89)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_93 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_lo_93)
node id_ctrl_decoder_decoded_andMatrixOutputs_167_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_93)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_94 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_94 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_94 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_94 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_94 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_93 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_90 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_83 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_64 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_44 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_41 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_38 = bits(id_ctrl_decoder_decoded_plaInput, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_37 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_35 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_29 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_10 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_10)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_38 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_35)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_83 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_10)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_35 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_38)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_44 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_44)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_93 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_35)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_94 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_83)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_29 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_83)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_41 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_93)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_90 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_29)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_37 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_94)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_64 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_94)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_94 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_37)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_94 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_90)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_94 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_lo_94)
node id_ctrl_decoder_decoded_andMatrixOutputs_163_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_94)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_95 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_95 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_95 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_95 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_95 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_94 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_91 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_84 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_65 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_45 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_42 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_39 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_38 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_36 = bits(id_ctrl_decoder_decoded_plaInput, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_30 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_11 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_4 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_4)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_39 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_30)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_84 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_11)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_36 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_38)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_45 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_42)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_94 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_36)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_95 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_84)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_30 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_65)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_42 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_91)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_91 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_30)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_38 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_95)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_95)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_65 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_95)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_95 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_38)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_95 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_91)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_95 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_lo_95)
node id_ctrl_decoder_decoded_andMatrixOutputs_137_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_95)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_96 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_96 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_96 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_96 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_96 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_95 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_92 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_85 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_66 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_46 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_43 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_40 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_39 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_37 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_31 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_12 = bits(id_ctrl_decoder_decoded_plaInput, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_5 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_3 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_3 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_3)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_40 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_5)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_85 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_12)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_37 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_40)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_46 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_39)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_95 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_37)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_96 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_85)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_31 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_46)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_92)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_43 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_85)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_92 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_31)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_39 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_96)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_96)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_66 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_96)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_96 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_39)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_96 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_92)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_96 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_lo_96)
node id_ctrl_decoder_decoded_andMatrixOutputs_74_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_96)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_97 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_97 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_97 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_97 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_97 = bits(id_ctrl_decoder_decoded_invInputs, 7, 7)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_96 = bits(id_ctrl_decoder_decoded_invInputs, 8, 8)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_93 = bits(id_ctrl_decoder_decoded_invInputs, 9, 9)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_86 = bits(id_ctrl_decoder_decoded_invInputs, 10, 10)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_67 = bits(id_ctrl_decoder_decoded_invInputs, 11, 11)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_47 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_44 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_41 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_40 = bits(id_ctrl_decoder_decoded_invInputs, 15, 15)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_38 = bits(id_ctrl_decoder_decoded_invInputs, 16, 16)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_32 = bits(id_ctrl_decoder_decoded_invInputs, 17, 17)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_13 = bits(id_ctrl_decoder_decoded_invInputs, 18, 18)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_6 = bits(id_ctrl_decoder_decoded_invInputs, 19, 19)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_4 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_4 = bits(id_ctrl_decoder_decoded_plaInput, 21, 21)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_3 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_3 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_3 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_2 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_2 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_2 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_2 = bits(id_ctrl_decoder_decoded_plaInput, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_2 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_2 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_2)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_2)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_2)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_2)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_41 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_2)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_86 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_13)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_3)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_38 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_3)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_4)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_13)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_47 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_2)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_96 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_38)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_97 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_86)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_40)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_32 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_38)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_44)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_67)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_44 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_2)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_93 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_32)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_96)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_40 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_93)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_97)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_97)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_67 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_2)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_97 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_40)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_97 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_93)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_97 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_lo_97)
node id_ctrl_decoder_decoded_andMatrixOutputs_59_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_97)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_98 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_98 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_98 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_98 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_98 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_97 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_94 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_87 = bits(id_ctrl_decoder_decoded_invInputs, 7, 7)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_68 = bits(id_ctrl_decoder_decoded_invInputs, 8, 8)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_48 = bits(id_ctrl_decoder_decoded_invInputs, 9, 9)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_45 = bits(id_ctrl_decoder_decoded_invInputs, 10, 10)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_42 = bits(id_ctrl_decoder_decoded_invInputs, 11, 11)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_41 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_39 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_33 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_14 = bits(id_ctrl_decoder_decoded_invInputs, 15, 15)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_7 = bits(id_ctrl_decoder_decoded_invInputs, 16, 16)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_5 = bits(id_ctrl_decoder_decoded_invInputs, 17, 17)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_5 = bits(id_ctrl_decoder_decoded_invInputs, 18, 18)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_4 = bits(id_ctrl_decoder_decoded_invInputs, 19, 19)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_4 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_4 = bits(id_ctrl_decoder_decoded_plaInput, 21, 21)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_3 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_3 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_3 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_3 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_3 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_3 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_1 = bits(id_ctrl_decoder_decoded_plaInput, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_1 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_1 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_1)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_14 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_1)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_3)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_3)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_42 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_3)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_87 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_14)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_3)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_4)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_39 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_1)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_4)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_5)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_48 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_3)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_97 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_39)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_98 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_87)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_14)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_39)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_33 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_1)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_42)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_48)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_45 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_3)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_94 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_33)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_87)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_97)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_41 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_1)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_98)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_98)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_68 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_3)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_98 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_41)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_98 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_94)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_98 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_lo_98)
node id_ctrl_decoder_decoded_andMatrixOutputs_152_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_98)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_99 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_99 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_99 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_99 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_99 = bits(id_ctrl_decoder_decoded_invInputs, 7, 7)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_98 = bits(id_ctrl_decoder_decoded_invInputs, 8, 8)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_95 = bits(id_ctrl_decoder_decoded_invInputs, 9, 9)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_88 = bits(id_ctrl_decoder_decoded_invInputs, 10, 10)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_69 = bits(id_ctrl_decoder_decoded_invInputs, 11, 11)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_49 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_46 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_43 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_42 = bits(id_ctrl_decoder_decoded_invInputs, 15, 15)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_40 = bits(id_ctrl_decoder_decoded_invInputs, 16, 16)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_34 = bits(id_ctrl_decoder_decoded_invInputs, 17, 17)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_15 = bits(id_ctrl_decoder_decoded_invInputs, 18, 18)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_8 = bits(id_ctrl_decoder_decoded_invInputs, 19, 19)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_6 = bits(id_ctrl_decoder_decoded_plaInput, 20, 20)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_6 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_5 = bits(id_ctrl_decoder_decoded_plaInput, 22, 22)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_5 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_5 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_4 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_4 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_4 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_4 = bits(id_ctrl_decoder_decoded_plaInput, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_4 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_4 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_4)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_4)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_4)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_4)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_43 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_4)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_88 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_15)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_5)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_40 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_5)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_6)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_15)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_49 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_4)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_98 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_40)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_99 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_88)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_42)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_34 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_40)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_46)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_69)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_46 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_4)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_95 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_34)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_98)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_42 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_95)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_99)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_99)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_69 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_4)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_99 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_42)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_99 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_95)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_99 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_lo_99)
node id_ctrl_decoder_decoded_andMatrixOutputs_47_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_99)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_100 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_100 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_100 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_100 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_100 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_99 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_96 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_89 = bits(id_ctrl_decoder_decoded_invInputs, 7, 7)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_70 = bits(id_ctrl_decoder_decoded_invInputs, 8, 8)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_50 = bits(id_ctrl_decoder_decoded_invInputs, 9, 9)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_47 = bits(id_ctrl_decoder_decoded_invInputs, 10, 10)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_44 = bits(id_ctrl_decoder_decoded_invInputs, 11, 11)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_43 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_41 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_35 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_16 = bits(id_ctrl_decoder_decoded_invInputs, 15, 15)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_9 = bits(id_ctrl_decoder_decoded_invInputs, 16, 16)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_7 = bits(id_ctrl_decoder_decoded_invInputs, 17, 17)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_7 = bits(id_ctrl_decoder_decoded_invInputs, 18, 18)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_6 = bits(id_ctrl_decoder_decoded_invInputs, 19, 19)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_6 = bits(id_ctrl_decoder_decoded_plaInput, 20, 20)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_6 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_5 = bits(id_ctrl_decoder_decoded_plaInput, 22, 22)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_5 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_5 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_5 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_5 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_5 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_2 = bits(id_ctrl_decoder_decoded_plaInput, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_2 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_2 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_2)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_2)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_5)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_5)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_44 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_5)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_89 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_16)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_5)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_6)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_41 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_2)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_6)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_7)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_50 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_5)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_99 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_41)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_100 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_89)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_16)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_41)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_35 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_2)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_44)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_50)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_47 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_5)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_96 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_35)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_89)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_99)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_43 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_2)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_100)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_100)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_70 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_5)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_100 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_43)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_100 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_96)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_100 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_lo_100)
node id_ctrl_decoder_decoded_andMatrixOutputs_103_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_100)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_101 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_101 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_101 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_101 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_101 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_100 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_97 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_90 = bits(id_ctrl_decoder_decoded_invInputs, 7, 7)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_71 = bits(id_ctrl_decoder_decoded_invInputs, 8, 8)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_51 = bits(id_ctrl_decoder_decoded_invInputs, 9, 9)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_48 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_45 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_44 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_42 = bits(id_ctrl_decoder_decoded_plaInput, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_36 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_17 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_10 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_17 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_10)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_45 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_36)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_90 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_17)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_42 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_44)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_51 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_48)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_100 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_42)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_101 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_90)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_36 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_71)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_48 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_97)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_97 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_36)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_44 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_101)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_101)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_71 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_101)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_101 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_44)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_101 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_97)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_101 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_lo_101)
node id_ctrl_decoder_decoded_andMatrixOutputs_83_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_101)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_102 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_102 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_102 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_102 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_102 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_101 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_98 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_91 = bits(id_ctrl_decoder_decoded_invInputs, 7, 7)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_72 = bits(id_ctrl_decoder_decoded_invInputs, 8, 8)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_52 = bits(id_ctrl_decoder_decoded_invInputs, 9, 9)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_49 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_46 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_45 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_43 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_37 = bits(id_ctrl_decoder_decoded_plaInput, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_18 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_11 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_8 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_18 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_8)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_46 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_18)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_91 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_18)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_43 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_43)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_49)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_52 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_46)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_101 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_43)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_102 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_91)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_37 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_72)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_49 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_98)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_98 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_37)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_45 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_102)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_102)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_72 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_102)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_102 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_45)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_102 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_98)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_102 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_lo_102)
node id_ctrl_decoder_decoded_andMatrixOutputs_31_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_102)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_103 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_103 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_103 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_103 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_103 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_102 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_99 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_92 = bits(id_ctrl_decoder_decoded_invInputs, 7, 7)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_73 = bits(id_ctrl_decoder_decoded_invInputs, 8, 8)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_53 = bits(id_ctrl_decoder_decoded_invInputs, 9, 9)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_50 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_47 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_46 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_44 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_38 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_19 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_12 = bits(id_ctrl_decoder_decoded_plaInput, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_9 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_8 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_7 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_19 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_7)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_12)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_47 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_9)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_92 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_19)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_44 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_38)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_47)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_53 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_46)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_102 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_44)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_103 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_92)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_38 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_53)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_99)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_50 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_92)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_99 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_38)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_46 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_103)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_103)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_73 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_103)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_103 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_46)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_103 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_99)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_103 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_lo_103)
node id_ctrl_decoder_decoded_andMatrixOutputs_13_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_103)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_104 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_104 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_104 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_104 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_104 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_103 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_100 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_93 = bits(id_ctrl_decoder_decoded_invInputs, 7, 7)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_74 = bits(id_ctrl_decoder_decoded_invInputs, 8, 8)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_54 = bits(id_ctrl_decoder_decoded_invInputs, 9, 9)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_51 = bits(id_ctrl_decoder_decoded_invInputs, 10, 10)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_48 = bits(id_ctrl_decoder_decoded_invInputs, 11, 11)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_47 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_45 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_39 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_20 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_13 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_10 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_9 = bits(id_ctrl_decoder_decoded_plaInput, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_8 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_7 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_7 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_20 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_7)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_9)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_48 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_8)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_93 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_20)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_20)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_45 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_13)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_47)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_54 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_45)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_103 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_45)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_104 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_93)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_39 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_51)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_93)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_51 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_74)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_100 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_39)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_104, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_104)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_47 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_103)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_104, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_104)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_74 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_104)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_104 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_47)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_104 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_100)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_104 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_lo_104)
node id_ctrl_decoder_decoded_andMatrixOutputs_111_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_104)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_105 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_105 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_105 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_105 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_105 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_104 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_101 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_94 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_75 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_55 = bits(id_ctrl_decoder_decoded_plaInput, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_52 = bits(id_ctrl_decoder_decoded_plaInput, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_49 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_48 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_46 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_49 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_48)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_94 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_46)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_46 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_52)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_55 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_75)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_104 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_46)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_105 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_94)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_52 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_104)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_101 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_101)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_48 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_105)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_75 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_105)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_105 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_48)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_105 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_101)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_105 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_lo_105)
node id_ctrl_decoder_decoded_andMatrixOutputs_65_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_105)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_106 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_106 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_106 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_106 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_106 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_105 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_102 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_95 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_76 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_56 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_53 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_50 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_49 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_47 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_50 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_49)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_95 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_47)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_47 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_53)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_56 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_76)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_105 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_47)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_106 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_95)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_53 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_105)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_102 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_102)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_49 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_106)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_76 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_106)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_106 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_49)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_106 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_102)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_106 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_lo_106)
node id_ctrl_decoder_decoded_andMatrixOutputs_124_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_106)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_107 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_107 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_107 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_107 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_107 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_106 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_103 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_96 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_77 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_57 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_54 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_51 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_50 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_48 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_51 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_50)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_96 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_48)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_48 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_54)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_57 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_77)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_106 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_48)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_107 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_96)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_54 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_106)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_103 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_103)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_50 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_107)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_77 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_107)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_107 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_50)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_107 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_103)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_107 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_lo_107)
node id_ctrl_decoder_decoded_andMatrixOutputs_50_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_107)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_108 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_108 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_108 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_108 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_108 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_107 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_104 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_97 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_78 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_58 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_55 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_52 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_51 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_49 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_52 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_51)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_97 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_49)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_49 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_55)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_58 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_78)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_107 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_49)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_108 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_97)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_55 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_107)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_104 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_104)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_51 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_108)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_78 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_108)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_108 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_51)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_108 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_104)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_108 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_lo_108)
node id_ctrl_decoder_decoded_andMatrixOutputs_6_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_108)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_109 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_109 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_109 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_109 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_109 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_108 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_105 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_98 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_79 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_59 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_56 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_53 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_52 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_50 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_53 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_52)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_98 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_50)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_50 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_56)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_59 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_79)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_108 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_50)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_109 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_98)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_56 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_108)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_105 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_105)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_52 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_109)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_79 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_109)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_109 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_52)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_109 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_105)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_109 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_lo_109)
node id_ctrl_decoder_decoded_andMatrixOutputs_134_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_109)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_110 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_110 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_110 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_110 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_110 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_109 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_106 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_99 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_80 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_60 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_57 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_54 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_53 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_51 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_54 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_53)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_99 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_51)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_51 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_57)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_60 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_80)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_109 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_51)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_110 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_99)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_57 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_109)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_106 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_106)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_53 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_110)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_80 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_110)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_110 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_53)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_110 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_106)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_110 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_lo_110)
node id_ctrl_decoder_decoded_andMatrixOutputs_153_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_110)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_111 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_111 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_111 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_111 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_111 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_110 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_107 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_100 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_81 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_61 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_58 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_55 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_54 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_52 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_55 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_54)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_100 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_52)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_52 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_58)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_61 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_81)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_110 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_52)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_111 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_100)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_58 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_110)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_107 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_107)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_54 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_111)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_81 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_111)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_111 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_54)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_111 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_107)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_111 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_lo_111)
node id_ctrl_decoder_decoded_andMatrixOutputs_109_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_111)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_112 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_112 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_112 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_112 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_112 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_111 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_108 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_101 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_82 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_62 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_59 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_56 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_55 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_53 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_40 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_56 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_53)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_101 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_40)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_53 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_56)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_62 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_62)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_111 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_53)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_112 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_101)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_40 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_101)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_59 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_111)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_108 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_40)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_55 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_112)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_82 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_112)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_112 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_55)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_112 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_108)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_112 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_lo_112)
node id_ctrl_decoder_decoded_andMatrixOutputs_187_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_112)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_113 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_113 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_113 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_113 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_113 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_112 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_109 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_102 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_83 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_63 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_60 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_57 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_56 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_54 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_41 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_57 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_54)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_102 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_41)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_54 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_57)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_63 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_63)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_112 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_54)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_113 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_102)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_41 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_102)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_60 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_112)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_109 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_41)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_56 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_113)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_83 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_113)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_113 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_56)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_113 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_109)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_113 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_lo_113)
node id_ctrl_decoder_decoded_andMatrixOutputs_45_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_113)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_114 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_114 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_114 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_114 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_114 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_113 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_110 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_103 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_84 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_64 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_61 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_58 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_58 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_61)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_103 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_58)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_64 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_103)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_113 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_84)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_114 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_103)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_61 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_114)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_110 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_113)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_84 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_114)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_114 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_114)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_114 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_110)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_114 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_lo_114)
node id_ctrl_decoder_decoded_andMatrixOutputs_79_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_114)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_115 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_115 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_115 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_115 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_115 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_114 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_111 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_104 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_85 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_65 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_62 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_59 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_57 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_55 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_42 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_59 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_55)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_104 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_42)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_55 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_59)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_65 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_65)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_114 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_55)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_115 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_104)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_42 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_104)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_62 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_114)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_111 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_42)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_57 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_115)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_85 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_115)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_115 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_57)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_115 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_111)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_115 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_lo_115)
node id_ctrl_decoder_decoded_andMatrixOutputs_159_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_115)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_116 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_116 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_116 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_116 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_116 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_115 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_112 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_105 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_86 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_66 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_63 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_60 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_58 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_56 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_43 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_60 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_56)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_105 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_43)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_56 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_60)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_66 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_66)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_115 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_56)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_116 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_105)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_43 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_105)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_63 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_115)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_112 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_43)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_58 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_116)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_86 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_116)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_116 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_58)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_116 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_112)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_116 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_lo_116)
node id_ctrl_decoder_decoded_andMatrixOutputs_34_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_116)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_117 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_117 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_117 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_117 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_117 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_116 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_113 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_106 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_87 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_67 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_64 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_61 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_59 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_57 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_44 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_61 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_57)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_106 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_44)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_57 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_61)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_67 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_67)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_116 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_57)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_117 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_106)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_44 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_106)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_64 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_116)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_113 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_44)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_59 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_117)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_87 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_117)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_117 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_59)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_117 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_113)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_117 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_lo_117)
node id_ctrl_decoder_decoded_andMatrixOutputs_86_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_117)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_118 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_118 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_118 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_118 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_118 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_117 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_114 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_107 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_88 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_68 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_65 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_62 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_60 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_58 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_45 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_62 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_58)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_107 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_45)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_58 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_62)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_68 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_68)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_117 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_58)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_118 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_107)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_45 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_107)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_65 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_117)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_114 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_45)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_60 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_118)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_88 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_118)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_118 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_60)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_118 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_114)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_118 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_lo_118)
node id_ctrl_decoder_decoded_andMatrixOutputs_10_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_118)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_119 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_119 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_119 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_119 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_119 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_118 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_115 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_108 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_89 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_69 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_66 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_63 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_61 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_59 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_46 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_63 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_59)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_108 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_46)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_59 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_63)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_69 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_69)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_118 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_59)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_119 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_108)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_46 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_108)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_66 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_118)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_115 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_46)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_61 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_119)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_89 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_119)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_119 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_61)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_119 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_115)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_119 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_lo_119)
node id_ctrl_decoder_decoded_andMatrixOutputs_93_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_119)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_120 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_120 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_120 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_120 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_120 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_119 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_116 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_109 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_90 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_70 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_67 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_64 = bits(id_ctrl_decoder_decoded_plaInput, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_62 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_60 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_47 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_64 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_60)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_109 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_47)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_60 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_64)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_70 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_70)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_119 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_60)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_120 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_109)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_47 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_109)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_67 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_119)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_116 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_47)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_62 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_120)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_90 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_120)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_120 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_62)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_120 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_116)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_120 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_lo_120)
node id_ctrl_decoder_decoded_andMatrixOutputs_180_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_120)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_121 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_121 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_121 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_121 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_121 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_120 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_117 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_110 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_91 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_71 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_68 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_65 = bits(id_ctrl_decoder_decoded_plaInput, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_63 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_61 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_48 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_21 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_21 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_21)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_65 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_61)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_110 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_21)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_61 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_65)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_71 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_71)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_120 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_61)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_121 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_110)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_48 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_110)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_68 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_120)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_117 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_48)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_63 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_121)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_91 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_121)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_121 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_63)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_121 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_117)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_121 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_lo_121)
node id_ctrl_decoder_decoded_andMatrixOutputs_43_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_121)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_122 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_122 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_122 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_122 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_122 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_121 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_118 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_111 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_92 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_72 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_69 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_66 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_64 = bits(id_ctrl_decoder_decoded_plaInput, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_62 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_49 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_22 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_22 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_22)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_66 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_62)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_111 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_22)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_62 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_66)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_72 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_72)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_121 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_62)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_122 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_111)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_49 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_111)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_69 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_121)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_118 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_49)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_64 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_122)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_92 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_122)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_122 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_64)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_122 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_118)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_122 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_lo_122)
node id_ctrl_decoder_decoded_andMatrixOutputs_135_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_122)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_123 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_123 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_123 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_123 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_123 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_122 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_119 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_112 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_93 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_73 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_70 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_67 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_65 = bits(id_ctrl_decoder_decoded_plaInput, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_63 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_50 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_23 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_14 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_23 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_14)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_67 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_50)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_112 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_23)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_63 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_65)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_73 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_70)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_122 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_63)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_123 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_112)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_50 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_93)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_70 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_119)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_119 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_50)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_65 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_123)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_14 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_123)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_93 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_123)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_123 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_65)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_123 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_119)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_123 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_lo_123)
node id_ctrl_decoder_decoded_andMatrixOutputs_3_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_123)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_124 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_124 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_124 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_124 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_124 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_123 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_120 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_113 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_94 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_74 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_71 = bits(id_ctrl_decoder_decoded_plaInput, 20, 20)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_68 = bits(id_ctrl_decoder_decoded_plaInput, 21, 21)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_66 = bits(id_ctrl_decoder_decoded_plaInput, 22, 22)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_64 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_51 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_24 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_15 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_11 = bits(id_ctrl_decoder_decoded_plaInput, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_10 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_9 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_8 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_8 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_24 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_8)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_10)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_68 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_9)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_113 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_24)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_24)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_64 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_15)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_66)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_74 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_64)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_123 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_64)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_124 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_113)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_51 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_71)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_113)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_71 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_94)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_120 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_51)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_124)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_66 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_123)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_124)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_94 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_124)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_124 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_66)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_124 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_120)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_124 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_lo_124)
node id_ctrl_decoder_decoded_andMatrixOutputs_188_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_124)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_125 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_125 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_125 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_125 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_125 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_124 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_121 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_114 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_95 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_75 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_72 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_69 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_67 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_65 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_52 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_25 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_25 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_25)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_69 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_65)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_114 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_25)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_65 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_69)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_75 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_75)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_124 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_65)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_125 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_114)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_52 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_114)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_72 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_124)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_121 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_52)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_67 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_125)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_95 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_125)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_125 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_67)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_125 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_121)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_125 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_lo_125)
node id_ctrl_decoder_decoded_andMatrixOutputs_4_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_125)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_126 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_126 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_126 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_126 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_126 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_125 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_122 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_115 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_96 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_76 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_73 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_70 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_68 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_66 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_53 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_26 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_26 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_26)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_70 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_66)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_115 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_26)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_66 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_70)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_76 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_76)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_125 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_66)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_126 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_115)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_53 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_115)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_73 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_125)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_122 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_53)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_68 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_126)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_96 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_126)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_126 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_68)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_126 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_122)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_126 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_lo_126)
node id_ctrl_decoder_decoded_andMatrixOutputs_25_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_126)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_127 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_127 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_127 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_127 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_127 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_126 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_123 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_116 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_97 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_77 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_74 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_71 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_71 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_74)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_116 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_71)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_77 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_116)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_126 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_97)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_127 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_116)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_74 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_127, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_127)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_123 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_126)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_97 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_127, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_127)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_127 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_127)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_127 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_123)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_127 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_lo_127)
node id_ctrl_decoder_decoded_andMatrixOutputs_58_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_127)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_128 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_128 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_128 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_128 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_128 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_127 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_124 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_117 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_98 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_78 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_75 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_72 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_69 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_67 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_54 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_72 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_67)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_117 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_54)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_67 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_72)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_78 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_78)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_127 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_67)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_128 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_117)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_54 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_117)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_75 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_127)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_124 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_54)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_69 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_128)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_98 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_128)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_128 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_69)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_128 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_124)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_128 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_lo_128)
node id_ctrl_decoder_decoded_andMatrixOutputs_147_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_128)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_129 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_129 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_129 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_129 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_129 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_128 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_125 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_118 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_99 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_79 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_76 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_73 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_70 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_68 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_55 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_27 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_27 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_27)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_73 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_68)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_118 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_27)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_68 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_73)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_79 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_79)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_128 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_68)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_129 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_118)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_55 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_118)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_76 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_128)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_125 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_55)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_70 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_129)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_99 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_129)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_129 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_70)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_129 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_125)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_129 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_lo_129)
node id_ctrl_decoder_decoded_andMatrixOutputs_27_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_129)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_130 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_130 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_130 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_130 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_130 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_129 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_126 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_119 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_100 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_80 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_77 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_74 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_71 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_69 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_56 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_74 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_69)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_119 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_56)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_69 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_74)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_80 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_80)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_129 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_69)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_130 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_119)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_56 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_119)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_77 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_129)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_126 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_56)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_71 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_130)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_100 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_130)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_130 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_71)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_130 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_126)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_130 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_lo_130)
node id_ctrl_decoder_decoded_andMatrixOutputs_52_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_130)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_131 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_131 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_131 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_131 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_131 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_130 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_127 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_120 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_101 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_81 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_78 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_75 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_72 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_70 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_57 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_75 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_70)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_120 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_57)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_70 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_75)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_81 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_81)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_130 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_70)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_131 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_120)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_57 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_127, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_120)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_78 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_130)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_127 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_57)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_72 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_131)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_101 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_131)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_131 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_72)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_131 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_127)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_131 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_lo_131)
node id_ctrl_decoder_decoded_andMatrixOutputs_138_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_131)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_132 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_132 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_132 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_132 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_132 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_131 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_128 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_121 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_102 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_82 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_79 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_76 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_73 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_71 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_58 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_28 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_28 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_28)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_76 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_71)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_121 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_28)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_71 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_76)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_82 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_82)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_131 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_71)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_132 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_121)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_58 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_121)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_79 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_131)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_128 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_58)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_73 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_132)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_102 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_132)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_132 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_73)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_132 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_128)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_132 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_lo_132)
node id_ctrl_decoder_decoded_andMatrixOutputs_178_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_132)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_133 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_133 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_133 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_133 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_133 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_132 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_129 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_122 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_103 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_83 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_80 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_77 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_74 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_72 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_59 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_77 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_72)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_122 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_59)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_72 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_77)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_83 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_83)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_132 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_72)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_133 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_122)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_59 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_122)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_80 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_132)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_129 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_59)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_74 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_133)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_103 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_133)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_133 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_74)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_133 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_129)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_133 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_lo_133)
node id_ctrl_decoder_decoded_andMatrixOutputs_173_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_133)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_134 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_134 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_134 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_134 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_134 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_133 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_130 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_123 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_104 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_84 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_81 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_78 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_75 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_73 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_60 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_29 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_29 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_29)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_78 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_73)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_123 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_29)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_73 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_78)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_84 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_104, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_84)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_133 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_73)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_134 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_123)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_60 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_123)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_81 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_133)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_130 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_60)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_75 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_134)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_104 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_134)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_134 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_75)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_134 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_130)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_134 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_lo_134)
node id_ctrl_decoder_decoded_andMatrixOutputs_120_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_134)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_135 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_135 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_135 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_135 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_135 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_134 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_131 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_124 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_105 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_85 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_82 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_79 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_76 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_74 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_61 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_30 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_30 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_30)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_79 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_74)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_124 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_30)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_74 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_79)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_85 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_85)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_134 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_74)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_135 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_124)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_61 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_124)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_82 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_134)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_131 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_61)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_76 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_135)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_105 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_135)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_135 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_76)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_135 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_131)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_135 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_lo_135)
node id_ctrl_decoder_decoded_andMatrixOutputs_19_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_135)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_136 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_136 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_136 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_136 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_136 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_135 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_132 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_125 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_106 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_86 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_83 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_80 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_77 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_75 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_62 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_80 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_75)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_125 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_62)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_75 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_80)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_86 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_86)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_135 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_75)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_136 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_125)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_62 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_125)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_83 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_135)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_132 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_62)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_77 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_136)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_106 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_136)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_136 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_77)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_136 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_132)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_136 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_lo_136)
node id_ctrl_decoder_decoded_andMatrixOutputs_64_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_136)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_137 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_137 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_137 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_137 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_137 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_136 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_133 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_126 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_107 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_87 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_84 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_81 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_78 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_76 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_63 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_31 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_31 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_81 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_76)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_126 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_76 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_81)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_87 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_87)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_136 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_76)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_137 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_126)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_63 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_126)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_84 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_137, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_136)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_133 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_63)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_78 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_137, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_137)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_107 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_137, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_137)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_137 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_78)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_137 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_133)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_137 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_lo_137)
node id_ctrl_decoder_decoded_andMatrixOutputs_142_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_137)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_138 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_138 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_138 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_138 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_138 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_137 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_134 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_127 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_108 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_88 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_85 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_82 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_79 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_77 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_64 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_32 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_32 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_32)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_82 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_77)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_127 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_32)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_77 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_82)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_88 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_88)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_137 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_77)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_138 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_127)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_64 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_127)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_85 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_138, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_137)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_134 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_64)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_79 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_138, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_138)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_108 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_138, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_138)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_138 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_79)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_138 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_134)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_138 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_lo_138)
node id_ctrl_decoder_decoded_andMatrixOutputs_11_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_138)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_139 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_139 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_139 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_139 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_139 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_138 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_135 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_128 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_109 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_89 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_86 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_83 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_80 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_78 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_65 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_33 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_16 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_33 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_16)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_83 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_65)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_128 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_33)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_78 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_80)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_89 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_86)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_138 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_78)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_139 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_128)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_65 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_109)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_86 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_138, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_135)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_135 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_65)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_80 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_139, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_139)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_139, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_139)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_109 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_139)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_139 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_80)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_139 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_135)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_139 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_lo_139)
node id_ctrl_decoder_decoded_andMatrixOutputs_46_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_139)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_140 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_140 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_140 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_140 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_140 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_139 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_136 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_129 = bits(id_ctrl_decoder_decoded_plaInput, 20, 20)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_110 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_90 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_87 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_84 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_81 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_79 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_66 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_34 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_17 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_34 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_17)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_84 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_66)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_129 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_34)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_79 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_81)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_90 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_87)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_139 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_79)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_140 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_129)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_66 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_110)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_87 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_139, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_136)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_136 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_66)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_81 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_140, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_140)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_17 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_140, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_140)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_110 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_140)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_140 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_81)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_140 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_136)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_140 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_lo_140)
node id_ctrl_decoder_decoded_andMatrixOutputs_141_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_140)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_141 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_141 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_141 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_141 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_141 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_140 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_137 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_130 = bits(id_ctrl_decoder_decoded_plaInput, 20, 20)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_111 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_91 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_88 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_85 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_82 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_80 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_67 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_35 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_18 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_12 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_35 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_12)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_85 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_35)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_130 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_35)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_80 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_80)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_88)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_91 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_85)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_140 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_80)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_141 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_130)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_67 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_111)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_88 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_140, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_137)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_137 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_67)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_82 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_141, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_141)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_18 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_141, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_141)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_111 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_141)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_141 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_82)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_141 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_141, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_137)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_141 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_141, id_ctrl_decoder_decoded_andMatrixOutputs_lo_141)
node id_ctrl_decoder_decoded_andMatrixOutputs_114_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_141)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_142 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_142 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_142 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_142 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_142 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_141 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_138 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_131 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_112 = bits(id_ctrl_decoder_decoded_plaInput, 21, 21)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_92 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_89 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_86 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_83 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_81 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_68 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_36 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_19 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_36 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_19)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_86 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_68)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_131 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_36)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_81 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_83)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_92 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_89)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_141 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_81)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_142 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_141, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_131)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_68 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_112)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_89 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_141, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_138)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_138 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_68)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_83 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_142)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_19 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_142)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_112 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_142)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_142 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_83)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_142 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_142, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_138)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_142 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_142, id_ctrl_decoder_decoded_andMatrixOutputs_lo_142)
node id_ctrl_decoder_decoded_andMatrixOutputs_70_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_142)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_143 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_143 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_143 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_143 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_143 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_142 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_139 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_132 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_113 = bits(id_ctrl_decoder_decoded_plaInput, 21, 21)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_93 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_90 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_87 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_84 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_82 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_69 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_37 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_20 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_13 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_37 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_13)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_87 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_37)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_132 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_37)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_82 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_82)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_90)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_93 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_87)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_142 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_82)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_143 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_142, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_132)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_69 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_113)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_90 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_139)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_139 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_69)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_84 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_143)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_20 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_143)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_113 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_143)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_143 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_84)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_143 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_143, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_139)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_143 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_143, id_ctrl_decoder_decoded_andMatrixOutputs_lo_143)
node id_ctrl_decoder_decoded_andMatrixOutputs_72_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_143)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_144 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_144 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_144 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_144 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_144 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_143 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_140 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_133 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_114 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_94 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_91 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_88 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_85 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_83 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_70 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_38 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_21 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_38 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_21)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_88 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_70)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_133 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_38)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_83 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_85)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_94 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_91)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_143 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_83)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_144 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_143, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_133)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_70 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_114)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_91 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_140)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_140 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_70)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_85 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_144)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_21 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_144)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_114 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_144)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_144 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_85)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_144 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_144, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_140)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_144 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_144, id_ctrl_decoder_decoded_andMatrixOutputs_lo_144)
node id_ctrl_decoder_decoded_andMatrixOutputs_174_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_144)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_145 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_145 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_145 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_145 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_145 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_144 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_141 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_134 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_115 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_95 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_92 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_89 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_86 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_84 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_71 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_39 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_22 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_14 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_39 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_14)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_89 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_39)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_134 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_39)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_84 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_84)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_14 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_92)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_95 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_89)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_144 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_84)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_145 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_144, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_134)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_71 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_115)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_92 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_141)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_141 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_71)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_86 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_145, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_145)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_22 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_145, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_145)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_115 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_145)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_145 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_86)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_145 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_145, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_141)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_145 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_145, id_ctrl_decoder_decoded_andMatrixOutputs_lo_145)
node id_ctrl_decoder_decoded_andMatrixOutputs_81_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_145)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_146 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_146 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_146 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_146 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_146 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_145 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_142 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_135 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_116 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_96 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_93 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_90 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_87 = bits(id_ctrl_decoder_decoded_plaInput, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_85 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_72 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_40 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_23 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_40 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_23)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_90 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_72)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_135 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_40)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_85 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_87)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_96 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_93)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_145 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_85)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_146 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_145, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_135)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_72 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_116)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_93 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_145, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_142)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_142 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_72)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_87 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_146)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_23 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_146)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_116 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_146)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_146 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_87)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_146 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_146, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_142)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_146 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_146, id_ctrl_decoder_decoded_andMatrixOutputs_lo_146)
node id_ctrl_decoder_decoded_andMatrixOutputs_130_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_146)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_147 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_147 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_147 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_147 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_147 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_146 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_143 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_136 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_117 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_97 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_94 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_91 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_88 = bits(id_ctrl_decoder_decoded_plaInput, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_86 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_73 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_41 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_24 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_15 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_41 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_15)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_91 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_41)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_136 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_41)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_86 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_86)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_94)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_97 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_91)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_146 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_86)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_147 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_146, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_136)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_73 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_117)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_94 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_143)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_143 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_73)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_88 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_147, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_147)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_24 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_147, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_147)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_117 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_147)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_147 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_88)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_147 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_147, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_143)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_147 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_147, id_ctrl_decoder_decoded_andMatrixOutputs_lo_147)
node id_ctrl_decoder_decoded_andMatrixOutputs_157_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_147)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_148 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_148 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_148 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_148 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_148 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_147 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_144 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_137 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_118 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_98 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_95 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_92 = bits(id_ctrl_decoder_decoded_plaInput, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_89 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_87 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_74 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_92 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_87)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_137 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_74)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_87 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_92)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_98 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_98)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_147 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_87)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_148 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_147, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_137)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_74 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_137)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_95 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_147)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_144 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_74)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_89 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_148)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_118 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_148)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_148 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_89)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_148 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_148, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_144)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_148 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_148, id_ctrl_decoder_decoded_andMatrixOutputs_lo_148)
node id_ctrl_decoder_decoded_andMatrixOutputs_68_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_148)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_149 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_149 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_149 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_149 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_149 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_148 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_145 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_138 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_119 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_99 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_96 = bits(id_ctrl_decoder_decoded_plaInput, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_93 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_90 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_88 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_75 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_93 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_88)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_138 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_75)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_88 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_93)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_99 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_99)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_148 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_88)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_149 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_148, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_138)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_75 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_145, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_138)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_96 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_149, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_148)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_145 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_75)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_90 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_149, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_149)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_119 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_149, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_149)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_149 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_90)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_149 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_149, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_145)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_149 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_149, id_ctrl_decoder_decoded_andMatrixOutputs_lo_149)
node id_ctrl_decoder_decoded_andMatrixOutputs_42_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_149)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_150 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_150 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_150 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_150 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_150 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_149 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_146 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_139 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_120 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_100 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_97 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_94 = bits(id_ctrl_decoder_decoded_plaInput, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_91 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_89 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_76 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_42 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_42 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_42)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_94 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_89)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_139 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_42)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_89 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_94)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_100 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_100)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_149 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_89)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_150 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_149, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_139)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_76 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_139)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_97 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_150, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_149)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_146 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_76)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_91 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_150, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_150)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_120 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_150, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_150)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_150 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_91)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_150 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_150, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_146)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_150 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_150, id_ctrl_decoder_decoded_andMatrixOutputs_lo_150)
node id_ctrl_decoder_decoded_andMatrixOutputs_54_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_150)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_151 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_151 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_151 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_151 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_151 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_150 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_147 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_140 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_121 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_101 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_98 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_95 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_92 = bits(id_ctrl_decoder_decoded_plaInput, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_90 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_77 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_43 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_43 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_43)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_95 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_90)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_140 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_43)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_90 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_95)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_101 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_101)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_150 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_90)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_151 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_150, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_140)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_77 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_147, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_140)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_98 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_151, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_150)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_147 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_77)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_92 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_151, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_151)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_121 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_151, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_151)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_151 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_92)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_151 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_151, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_147)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_151 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_151, id_ctrl_decoder_decoded_andMatrixOutputs_lo_151)
node id_ctrl_decoder_decoded_andMatrixOutputs_63_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_151)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_152 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_152 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_152 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_152 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_152 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_151 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_148 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_141 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_122 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_102 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_99 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_96 = bits(id_ctrl_decoder_decoded_plaInput, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_93 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_91 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_78 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_44 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_44 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_44)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_96 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_91)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_141 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_44)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_91 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_96)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_102 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_102)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_151 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_91)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_152 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_151, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_141)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_78 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_141)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_99 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_152, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_151)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_148 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_78)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_93 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_152, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_152)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_122 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_152, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_152)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_152 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_93)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_152 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_152, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_148)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_152 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_152, id_ctrl_decoder_decoded_andMatrixOutputs_lo_152)
node id_ctrl_decoder_decoded_andMatrixOutputs_69_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_152)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_153 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_153 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_153 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_153 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_153 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_152 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_149 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_142 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_123 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_103 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_100 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_97 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_94 = bits(id_ctrl_decoder_decoded_plaInput, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_92 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_79 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_45 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_25 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_45 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_25)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_97 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_79)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_142 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_45)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_92 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_94)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_103 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_100)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_152 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_92)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_153 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_152, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_142)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_79 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_123)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_100 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_152, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_149)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_149 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_79)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_94 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_153, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_153)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_25 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_153, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_153)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_123 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_153)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_153 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_94)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_153 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_153, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_149)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_153 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_153, id_ctrl_decoder_decoded_andMatrixOutputs_lo_153)
node id_ctrl_decoder_decoded_andMatrixOutputs_183_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_153)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_154 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_154 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_154 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_154 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_154 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_153 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_150 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_143 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_124 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_104 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_101 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_98 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_95 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_93 = bits(id_ctrl_decoder_decoded_plaInput, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_80 = bits(id_ctrl_decoder_decoded_plaInput, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_46 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_26 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_16 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_46 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_16)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_98 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_46)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_143 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_46)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_93 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_93)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_104, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_101)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_104 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_98)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_153 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_93)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_154 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_153, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_143)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_80 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_124)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_101 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_153, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_150)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_150 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_80)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_95 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_154, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_154)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_26 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_154, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_154)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_124 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_154)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_154 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_95)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_154 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_154, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_150)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_154 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_154, id_ctrl_decoder_decoded_andMatrixOutputs_lo_154)
node id_ctrl_decoder_decoded_andMatrixOutputs_51_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_154)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_155 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_155 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_155 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_155 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_155 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_154 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_151 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_144 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_125 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_105 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_102 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_99 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_96 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_94 = bits(id_ctrl_decoder_decoded_plaInput, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_81 = bits(id_ctrl_decoder_decoded_plaInput, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_47 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_27 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_17 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_47 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_17)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_99 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_47)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_144 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_47)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_94 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_94)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_17 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_102)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_105 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_99)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_154 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_94)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_155 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_154, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_144)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_81 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_125)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_102 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_154, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_151)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_151 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_81)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_96 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_155, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_155)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_27 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_155, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_155)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_125 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_155)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_155 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_96)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_155 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_155, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_151)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_155 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_155, id_ctrl_decoder_decoded_andMatrixOutputs_lo_155)
node id_ctrl_decoder_decoded_andMatrixOutputs_136_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_155)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_156 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_156 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_156 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_156 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_156 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_155 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_152 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_145 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_126 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_106 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_103 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_100 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_97 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_95 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_82 = bits(id_ctrl_decoder_decoded_plaInput, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_48 = bits(id_ctrl_decoder_decoded_plaInput, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_28 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_18 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_11 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_48 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_11)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_100 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_28)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_145 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_48)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_95 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_82)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_18 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_100)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_106 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_97)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_155 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_95)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_156 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_155, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_145)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_82 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_106)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_155, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_152)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_103 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_145)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_152 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_82)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_97 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_156, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_156)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_28 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_156, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_156)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_126 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_156)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_156 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_97)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_156 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_156, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_152)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_156 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_156, id_ctrl_decoder_decoded_andMatrixOutputs_lo_156)
node id_ctrl_decoder_decoded_andMatrixOutputs_127_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_156)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_157 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_157 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_157 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_157 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_157 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_156 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_153 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_146 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_127 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_107 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_104 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_101 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_98 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_96 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_83 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_49 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_29 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_49 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_29)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_101 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_83)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_146 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_49)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_96 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_98)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_107 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_104)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_156 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_96)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_157 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_156, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_146)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_83 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_127)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_104 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_156, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_153)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_153 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_83)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_98 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_157, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_157)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_29 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_157, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_157)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_127 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_157)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_157 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_98)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_157 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_157, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_153)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_157 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_157, id_ctrl_decoder_decoded_andMatrixOutputs_lo_157)
node id_ctrl_decoder_decoded_andMatrixOutputs_151_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_157)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_158 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_158 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_158 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_158 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_158 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_157 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_154 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_147 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_128 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_108 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_105 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_102 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_99 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_97 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_84 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_50 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_30 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_50 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_30)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_102 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_84)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_147 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_50)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_97 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_99)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_108 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_105)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_157 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_97)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_158 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_157, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_147)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_84 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_147, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_128)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_105 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_157, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_154)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_154 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_84)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_99 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_158, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_158)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_30 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_158, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_158)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_128 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_158)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_158 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_99)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_158 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_158, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_154)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_158 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_158, id_ctrl_decoder_decoded_andMatrixOutputs_lo_158)
node id_ctrl_decoder_decoded_andMatrixOutputs_1_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_158)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_159 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_159 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_159 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_159 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_159 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_158 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_155 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_148 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_129 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_109 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_106 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_103 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_100 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_98 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_85 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_51 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_31 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_51 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_103 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_85)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_148 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_51)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_98 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_100)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_109 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_106)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_158 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_98)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_159 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_158, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_148)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_85 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_129)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_106 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_158, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_155)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_155 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_85)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_100 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_159, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_159)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_31 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_159, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_159)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_129 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_159)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_159 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_100)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_159 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_159, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_155)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_159 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_159, id_ctrl_decoder_decoded_andMatrixOutputs_lo_159)
node id_ctrl_decoder_decoded_andMatrixOutputs_100_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_159)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_160 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_160 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_160 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_160 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_160 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_159 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_156 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_149 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_130 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_110 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_107 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_104 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_101 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_99 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_86 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_52 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_32 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_19 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_12 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_10 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_52 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_10)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_32)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_104 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_19)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_149 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_52)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_99 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_86)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_19 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_104)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_110 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_101)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_159 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_99)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_160 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_159, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_149)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_86 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_110)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_159, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_156)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_107 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_149)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_156 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_86)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_101 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_160, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_160)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_32 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_160, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_160)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_130 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_160)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_160 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_101)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_160 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_160, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_156)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_160 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_160, id_ctrl_decoder_decoded_andMatrixOutputs_lo_160)
node id_ctrl_decoder_decoded_andMatrixOutputs_106_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_160)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_161 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_161 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_161 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_161 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_161 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_160 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_157 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_150 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_131 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_111 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_108 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_105 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_102 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_100 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_87 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_53 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_33 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_20 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_13 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_11 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_53 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_11)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_33)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_105 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_20)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_150 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_53)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_100 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_87)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_20 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_105)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_111 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_102)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_160 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_100)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_161 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_160, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_150)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_87 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_111)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_160, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_157)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_108 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_150)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_157 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_87)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_102 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_161, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_161)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_33 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_161, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_161)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_131 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_161)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_161 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_102)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_161 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_161, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_157)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_161 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_161, id_ctrl_decoder_decoded_andMatrixOutputs_lo_161)
node id_ctrl_decoder_decoded_andMatrixOutputs_186_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_161)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_162 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_162 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_162 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_162 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_162 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_161 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_158 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_151 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_132 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_112 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_109 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_106 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_103 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_101 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_88 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_54 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_34 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_21 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_14 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_12 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_9 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_54 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_9)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_21)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_106 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_14)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_151 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_54)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_101 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_54)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_21 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_103)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_112 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_101)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_161 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_101)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_162 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_161, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_151)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_88 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_109)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_14 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_158, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_151)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_109 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_132)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_158 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_88)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_162, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_162)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_103 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_161)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_34 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_162, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_162)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_132 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_162)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_162 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_103)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_162 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_162, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_158)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_162 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_162, id_ctrl_decoder_decoded_andMatrixOutputs_lo_162)
node id_ctrl_decoder_decoded_andMatrixOutputs_18_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_162)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_163 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_163 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_163 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_163 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_163 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_162 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_159 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_152 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_133 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_113 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_110 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_107 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_104 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_102 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_89 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_55 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_35 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_22 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_15 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_13 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_55 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_13)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_35)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_107 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_22)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_152 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_55)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_102 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_89)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_22 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_107)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_113 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_104)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_162 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_102)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_163 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_162, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_152)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_89 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_113)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_162, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_159)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_110 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_152)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_159 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_89)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_104 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_163, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_163)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_35 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_163, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_163)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_133 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_163)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_163 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_104)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_163 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_163, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_159)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_163 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_163, id_ctrl_decoder_decoded_andMatrixOutputs_lo_163)
node id_ctrl_decoder_decoded_andMatrixOutputs_108_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_163)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_164 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_164 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_164 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_164 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_164 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_163 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_160 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_153 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_134 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_114 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_111 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_108 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_105 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_103 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_90 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_108 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_103)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_153 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_90)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_103 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_108)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_114 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_114)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_163 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_103)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_164 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_163, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_153)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_90 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_160, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_153)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_111 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_164, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_163)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_160 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_90)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_105 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_164, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_164)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_134 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_164, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_164)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_164 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_105)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_164 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_164, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_160)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_164 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_164, id_ctrl_decoder_decoded_andMatrixOutputs_lo_164)
node id_ctrl_decoder_decoded_andMatrixOutputs_89_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_164)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_165 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_165 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_165 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_165 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_165 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_164 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_161 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_154 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_135 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_115 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_112 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_109 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_106 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_104 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_91 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_56 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_56 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_56)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_109 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_104)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_154 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_56)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_104 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_109)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_115 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_115)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_164 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_104)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_165 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_164, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_154)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_91 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_161, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_154)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_112 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_165, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_164)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_161 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_91)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_106 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_165, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_165)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_135 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_165, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_165)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_165 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_106)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_165 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_165, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_161)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_165 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_165, id_ctrl_decoder_decoded_andMatrixOutputs_lo_165)
node id_ctrl_decoder_decoded_andMatrixOutputs_62_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_165)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_166 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_166 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_166 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_166 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_166 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_165 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_162 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_155 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_136 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_116 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_113 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_110 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_107 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_105 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_92 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_57 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_57 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_57)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_110 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_105)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_155 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_57)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_105 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_110)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_116 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_116)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_165 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_105)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_166 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_165, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_155)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_92 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_162, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_155)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_113 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_166, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_165)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_162 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_92)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_107 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_166, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_166)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_136 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_166, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_166)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_166 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_107)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_166 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_166, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_162)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_166 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_166, id_ctrl_decoder_decoded_andMatrixOutputs_lo_166)
node id_ctrl_decoder_decoded_andMatrixOutputs_149_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_166)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_167 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_167 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_167 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_167 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_167 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_166 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_163 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_156 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_137 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_117 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_114 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_111 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_108 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_106 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_93 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_58 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_58 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_58)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_111 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_106)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_156 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_58)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_106 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_111)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_117 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_137, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_117)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_166 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_106)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_167 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_166, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_156)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_93 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_163, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_156)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_114 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_167, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_166)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_163 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_93)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_108 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_167, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_167)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_137 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_167, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_167)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_167 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_108)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_167 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_167, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_163)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_167 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_167, id_ctrl_decoder_decoded_andMatrixOutputs_lo_167)
node id_ctrl_decoder_decoded_andMatrixOutputs_171_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_167)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_168 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_168 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_168 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_168 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_168 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_167 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_164 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_157 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_138 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_118 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_115 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_112 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_109 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_107 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_94 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_59 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_59 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_59)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_112 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_107)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_157 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_59)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_107 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_112)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_118 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_138, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_118)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_167 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_107)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_168 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_167, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_157)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_94 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_164, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_157)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_115 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_168, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_167)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_164 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_94)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_109 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_168, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_168)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_138 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_168, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_168)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_168 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_109)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_168 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_168, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_164)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_168 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_168, id_ctrl_decoder_decoded_andMatrixOutputs_lo_168)
node id_ctrl_decoder_decoded_andMatrixOutputs_37_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_168)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_169 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_169 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_169 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_169 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_169 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_168 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_165 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_158 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_139 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_119 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_116 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_113 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_110 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_108 = bits(id_ctrl_decoder_decoded_plaInput, 23, 23)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_95 = bits(id_ctrl_decoder_decoded_plaInput, 24, 24)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_60 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_36 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_23 = bits(id_ctrl_decoder_decoded_plaInput, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_16 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_14 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_10 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_9 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_60 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_9)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_14 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_16)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_113 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_14)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_158 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_60)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_60)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_108 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_36)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_23 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_110)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_119 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_108)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_168 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_108)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_169 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_168, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_158)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_95 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_116)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_165, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_158)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_116 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_139)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_165 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_95)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_169, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_169)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_110 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_168)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_36 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_169, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_169)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_139 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_169)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_169 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_110)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_169 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_169, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_165)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_169 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_169, id_ctrl_decoder_decoded_andMatrixOutputs_lo_169)
node id_ctrl_decoder_decoded_andMatrixOutputs_122_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_169)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_170 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_170 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_170 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_170 = bits(id_ctrl_decoder_decoded_invInputs, 7, 7)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_170 = bits(id_ctrl_decoder_decoded_invInputs, 8, 8)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_169 = bits(id_ctrl_decoder_decoded_invInputs, 9, 9)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_166 = bits(id_ctrl_decoder_decoded_invInputs, 10, 10)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_159 = bits(id_ctrl_decoder_decoded_invInputs, 11, 11)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_140 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_120 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_117 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_114 = bits(id_ctrl_decoder_decoded_invInputs, 15, 15)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_111 = bits(id_ctrl_decoder_decoded_invInputs, 16, 16)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_109 = bits(id_ctrl_decoder_decoded_invInputs, 17, 17)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_96 = bits(id_ctrl_decoder_decoded_invInputs, 18, 18)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_61 = bits(id_ctrl_decoder_decoded_invInputs, 19, 19)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_37 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_24 = bits(id_ctrl_decoder_decoded_plaInput, 21, 21)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_17 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_15 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_11 = bits(id_ctrl_decoder_decoded_plaInput, 24, 24)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_10 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_6 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_6 = bits(id_ctrl_decoder_decoded_plaInput, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_6 = bits(id_ctrl_decoder_decoded_plaInput, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_6 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_6 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_6 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_6)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_61 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_6)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_6)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_6)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_114 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_6)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_159 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_61)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_15)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_109 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_11)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_24)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_24 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_61)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_120 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_6)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_169 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_109)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_170 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_169, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_159)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_111)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_96 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_109)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_117)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_17 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_159, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_140)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_117 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_6)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_166 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_96)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_170, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_169)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_111 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_166)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_170, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_170)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_37 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_170, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_170)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_140 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_6)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_170 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_111)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_170 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_170, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_166)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_170 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_170, id_ctrl_decoder_decoded_andMatrixOutputs_lo_170)
node id_ctrl_decoder_decoded_andMatrixOutputs_82_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_170)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_171 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_171 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_171 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_171 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_171 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_170 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_167 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_160 = bits(id_ctrl_decoder_decoded_invInputs, 7, 7)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_141 = bits(id_ctrl_decoder_decoded_invInputs, 8, 8)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_121 = bits(id_ctrl_decoder_decoded_invInputs, 9, 9)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_118 = bits(id_ctrl_decoder_decoded_invInputs, 10, 10)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_115 = bits(id_ctrl_decoder_decoded_invInputs, 11, 11)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_112 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_110 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_97 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_62 = bits(id_ctrl_decoder_decoded_invInputs, 15, 15)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_38 = bits(id_ctrl_decoder_decoded_invInputs, 16, 16)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_25 = bits(id_ctrl_decoder_decoded_invInputs, 17, 17)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_18 = bits(id_ctrl_decoder_decoded_invInputs, 18, 18)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_16 = bits(id_ctrl_decoder_decoded_invInputs, 19, 19)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_12 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_11 = bits(id_ctrl_decoder_decoded_plaInput, 21, 21)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_7 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_7 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_7 = bits(id_ctrl_decoder_decoded_plaInput, 24, 24)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_7 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_7 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_7 = bits(id_ctrl_decoder_decoded_plaInput, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_3 = bits(id_ctrl_decoder_decoded_plaInput, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_3 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_3 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_31 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_3)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_62 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_7)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_7)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_115 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_7)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_160 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_62)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_7)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_11)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_110 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_3)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_16)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_25 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_25)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_121 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_7)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_170 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_110)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_171 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_170, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_160)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_62)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_110)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_97 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_3)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_115)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_18 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_141, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_121)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_118 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_7)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_167 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_97)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_167, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_160)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_171, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_170)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_112 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_3)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_171, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_171)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_38 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_171, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_171)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_141 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_7)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_171 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_141, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_112)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_171 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_171, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_167)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_171 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_171, id_ctrl_decoder_decoded_andMatrixOutputs_lo_171)
node id_ctrl_decoder_decoded_andMatrixOutputs_119_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_171)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_172 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_172 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_172 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_172 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_172 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_171 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_168 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_161 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_142 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_122 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_119 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_116 = bits(id_ctrl_decoder_decoded_plaInput, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_116 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_119)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_161 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_116)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_122 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_168, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_161)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_171 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_142)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_172 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_171, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_161)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_119 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_172, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_172)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_168 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_171)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_142 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_172, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_172)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_172 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_172)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_172 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_172, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_168)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_172 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_172, id_ctrl_decoder_decoded_andMatrixOutputs_lo_172)
node id_ctrl_decoder_decoded_andMatrixOutputs_169_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_172)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_173 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_173 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_173 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_173 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_173 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_172 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_169 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_162 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_143 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_123 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_120 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_117 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_113 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_111 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_98 = bits(id_ctrl_decoder_decoded_plaInput, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_117 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_111)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_162 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_98)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_111 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_117)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_123 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_123)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_172 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_111)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_173 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_172, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_162)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_98 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_169, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_162)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_120 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_173, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_172)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_169 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_98)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_113 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_173, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_173)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_143 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_173, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_173)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_173 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_143, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_113)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_173 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_173, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_169)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_173 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_173, id_ctrl_decoder_decoded_andMatrixOutputs_lo_173)
node id_ctrl_decoder_decoded_andMatrixOutputs_57_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_173)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_174 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_174 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_174 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_174 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_174 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_173 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_170 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_163 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_144 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_124 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_121 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_118 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_114 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_112 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_99 = bits(id_ctrl_decoder_decoded_plaInput, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_118 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_112)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_163 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_99)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_112 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_118)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_124 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_124)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_173 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_112)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_174 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_173, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_163)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_99 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_170, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_163)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_121 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_174, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_173)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_170 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_99)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_114 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_174, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_174)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_144 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_174, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_174)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_174 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_144, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_114)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_174 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_174, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_170)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_174 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_174, id_ctrl_decoder_decoded_andMatrixOutputs_lo_174)
node id_ctrl_decoder_decoded_andMatrixOutputs_80_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_174)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_175 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_175 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_175 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_175 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_175 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_174 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_171 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_164 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_145 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_125 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_122 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_119 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_115 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_113 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_100 = bits(id_ctrl_decoder_decoded_plaInput, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_119 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_113)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_164 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_100)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_113 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_119)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_125 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_145, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_125)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_174 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_113)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_175 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_174, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_164)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_100 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_171, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_164)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_122 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_175, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_174)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_171 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_100)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_115 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_175, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_175)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_145 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_175, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_175)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_175 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_145, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_115)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_175 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_175, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_171)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_175 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_175, id_ctrl_decoder_decoded_andMatrixOutputs_lo_175)
node id_ctrl_decoder_decoded_andMatrixOutputs_166_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_175)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_176 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_176 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_176 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_176 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_176 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_175 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_172 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_165 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_146 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_126 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_123 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_120 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_116 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_114 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_101 = bits(id_ctrl_decoder_decoded_plaInput, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_120 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_114)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_165 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_101)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_114 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_120)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_126 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_126)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_175 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_114)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_176 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_175, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_165)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_101 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_172, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_165)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_123 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_176, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_175)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_172 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_101)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_116 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_176, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_176)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_146 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_176, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_176)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_176 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_146, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_116)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_176 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_176, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_172)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_176 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_176, id_ctrl_decoder_decoded_andMatrixOutputs_lo_176)
node id_ctrl_decoder_decoded_andMatrixOutputs_154_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_176)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_177 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_177 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_177 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_177 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_177 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_176 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_173 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_166 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_147 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_127 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_124 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_121 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_117 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_115 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_102 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_63 = bits(id_ctrl_decoder_decoded_plaInput, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_63 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_63)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_121 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_115)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_166 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_63)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_115 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_121)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_127 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_147, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_127)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_176 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_115)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_177 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_176, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_166)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_102 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_173, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_166)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_124 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_177, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_176)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_173 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_102)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_117 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_177, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_177)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_147 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_177, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_177)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_177 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_147, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_117)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_177 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_177, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_173)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_177 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_177, id_ctrl_decoder_decoded_andMatrixOutputs_lo_177)
node id_ctrl_decoder_decoded_andMatrixOutputs_192_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_177)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_178 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_178 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_178 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_178 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_178 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_177 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_174 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_167 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_148 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_128 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_125 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_122 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_118 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_116 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_103 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_64 = bits(id_ctrl_decoder_decoded_plaInput, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_64 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_64)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_122 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_116)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_167 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_64)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_116 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_122)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_128 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_128)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_177 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_116)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_178 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_177, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_167)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_103 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_174, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_167)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_125 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_178, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_177)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_174 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_103)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_118 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_178, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_178)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_148 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_178, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_178)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_178 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_148, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_118)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_178 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_178, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_174)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_178 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_178, id_ctrl_decoder_decoded_andMatrixOutputs_lo_178)
node id_ctrl_decoder_decoded_andMatrixOutputs_38_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_178)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_179 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_179 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_179 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_179 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_179 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_178 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_175 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_168 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_149 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_129 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_126 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_123 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_119 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_117 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_104 = bits(id_ctrl_decoder_decoded_plaInput, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_123 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_117)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_168 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_104)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_117 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_123)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_129 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_149, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_129)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_178 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_117)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_179 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_178, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_168)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_104 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_175, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_168)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_126 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_179, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_178)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_175 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_104)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_119 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_179, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_179)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_149 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_179, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_179)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_179 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_149, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_119)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_179 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_179, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_175)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_179 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_179, id_ctrl_decoder_decoded_andMatrixOutputs_lo_179)
node id_ctrl_decoder_decoded_andMatrixOutputs_158_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_179)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_180 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_180 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_180 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_180 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_180 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_179 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_176 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_169 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_150 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_130 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_127 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_124 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_120 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_118 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_105 = bits(id_ctrl_decoder_decoded_plaInput, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_124 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_118)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_169 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_105)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_118 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_127, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_124)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_130 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_150, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_130)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_179 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_118)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_180 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_179, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_169)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_105 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_176, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_169)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_127 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_180, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_179)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_176 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_105)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_120 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_180, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_180)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_150 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_180, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_180)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_180 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_150, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_120)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_180 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_180, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_176)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_180 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_180, id_ctrl_decoder_decoded_andMatrixOutputs_lo_180)
node id_ctrl_decoder_decoded_andMatrixOutputs_110_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_180)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_181 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_181 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_181 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_181 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_181 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_180 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_177 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_170 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_151 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_131 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_128 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_125 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_121 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_119 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_106 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_65 = bits(id_ctrl_decoder_decoded_plaInput, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_65 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_65)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_125 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_119)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_170 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_65)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_119 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_125)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_131 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_151, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_131)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_180 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_119)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_181 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_180, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_170)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_106 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_177, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_170)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_128 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_181, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_180)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_177 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_106)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_121 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_181, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_181)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_151 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_181, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_181)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_181 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_151, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_121)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_181 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_181, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_177)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_181 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_181, id_ctrl_decoder_decoded_andMatrixOutputs_lo_181)
node id_ctrl_decoder_decoded_andMatrixOutputs_23_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_181)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_182 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_182 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_182 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_182 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_182 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_181 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_178 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_171 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_152 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_132 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_129 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_126 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_122 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_120 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_107 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_66 = bits(id_ctrl_decoder_decoded_plaInput, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_66 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_66)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_126 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_120)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_171 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_66)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_120 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_126)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_132 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_152, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_132)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_181 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_120)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_182 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_181, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_171)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_107 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_178, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_171)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_129 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_182, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_181)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_178 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_107)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_122 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_182, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_182)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_152 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_182, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_182)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_182 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_152, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_122)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_182 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_182, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_178)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_182 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_182, id_ctrl_decoder_decoded_andMatrixOutputs_lo_182)
node id_ctrl_decoder_decoded_andMatrixOutputs_101_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_182)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_183 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_183 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_183 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_183 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_183 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_182 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_179 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_172 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_153 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_133 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_130 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_127 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_123 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_121 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_108 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_67 = bits(id_ctrl_decoder_decoded_plaInput, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_67 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_67)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_127 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_121)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_172 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_67)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_121 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_127)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_133 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_153, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_133)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_182 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_121)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_183 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_182, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_172)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_108 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_179, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_172)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_130 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_183, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_182)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_179 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_108)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_123 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_183, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_183)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_153 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_183, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_183)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_183 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_153, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_123)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_183 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_183, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_179)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_183 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_183, id_ctrl_decoder_decoded_andMatrixOutputs_lo_183)
node id_ctrl_decoder_decoded_andMatrixOutputs_118_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_183)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_184 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_184 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_184 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_184 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_184 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_183 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_180 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_173 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_154 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_134 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_131 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_128 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_124 = bits(id_ctrl_decoder_decoded_plaInput, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_122 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_109 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_68 = bits(id_ctrl_decoder_decoded_plaInput, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_68 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_68)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_128 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_122)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_173 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_68)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_122 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_128)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_134 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_154, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_134)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_183 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_122)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_184 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_183, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_173)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_109 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_180, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_173)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_131 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_184, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_183)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_180 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_109)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_124 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_184, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_184)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_154 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_184, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_184)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_184 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_154, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_124)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_184 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_184, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_180)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_184 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_184, id_ctrl_decoder_decoded_andMatrixOutputs_lo_184)
node id_ctrl_decoder_decoded_andMatrixOutputs_116_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_184)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_185 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_185 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_185 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_185 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_185 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_184 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_181 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_174 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_155 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_135 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_132 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_129 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_125 = bits(id_ctrl_decoder_decoded_plaInput, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_123 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_110 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_69 = bits(id_ctrl_decoder_decoded_plaInput, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_69 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_69)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_129 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_123)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_174 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_69)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_123 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_129)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_135 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_155, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_135)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_184 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_123)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_185 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_184, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_174)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_110 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_181, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_174)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_132 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_185, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_184)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_181 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_110)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_125 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_185, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_185)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_155 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_185, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_185)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_185 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_155, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_125)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_185 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_185, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_181)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_185 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_185, id_ctrl_decoder_decoded_andMatrixOutputs_lo_185)
node id_ctrl_decoder_decoded_andMatrixOutputs_156_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_185)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_186 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_186 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_186 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_186 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_186 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_185 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_182 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_175 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_156 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_136 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_133 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_130 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_126 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_124 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_111 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_70 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_39 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_26 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_19 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_17 = bits(id_ctrl_decoder_decoded_plaInput, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_70 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_17)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_17 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_39)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_130 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_26)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_175 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_70)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_124 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_111)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_26 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_130)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_136 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_126)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_185 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_124)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_186 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_185, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_175)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_111 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_156, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_136)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_19 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_185, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_182)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_133 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_175)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_182 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_111)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_126 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_186, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_186)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_39 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_186, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_186)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_156 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_186)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_186 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_156, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_126)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_186 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_186, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_182)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_186 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_186, id_ctrl_decoder_decoded_andMatrixOutputs_lo_186)
node id_ctrl_decoder_decoded_andMatrixOutputs_113_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_186)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_187 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_187 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_187 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_187 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_187 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_186 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_183 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_176 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_157 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_137 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_134 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_131 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_127 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_125 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_112 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_71 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_40 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_27 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_20 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_18 = bits(id_ctrl_decoder_decoded_plaInput, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_71 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_18)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_18 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_40)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_131 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_27)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_176 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_71)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_125 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_112)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_27 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_131)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_137 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_127)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_186 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_125)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_187 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_186, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_176)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_112 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_157, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_137)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_20 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_186, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_183)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_134 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_176)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_183 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_112)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_127 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_187, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_187)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_40 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_187, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_187)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_157 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_187)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_187 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_157, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_127)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_187 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_187, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_183)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_187 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_187, id_ctrl_decoder_decoded_andMatrixOutputs_lo_187)
node id_ctrl_decoder_decoded_andMatrixOutputs_107_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_187)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_188 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_188 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_188 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_188 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_188 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_187 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_184 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_177 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_158 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_138 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_135 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_132 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_128 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_126 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_113 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_72 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_41 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_28 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_21 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_19 = bits(id_ctrl_decoder_decoded_plaInput, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_72 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_19)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_19 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_41)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_132 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_28)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_177 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_72)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_126 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_113)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_28 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_132)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_138 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_128)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_187 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_126)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_188 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_187, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_177)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_113 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_158, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_138)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_21 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_187, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_184)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_135 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_177)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_184 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_113)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_128 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_188, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_188)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_41 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_188, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_188)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_158 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_188)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_188 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_158, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_128)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_188 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_188, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_184)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_188 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_188, id_ctrl_decoder_decoded_andMatrixOutputs_lo_188)
node id_ctrl_decoder_decoded_andMatrixOutputs_84_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_188)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_189 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_189 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_189 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_189 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_189 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_188 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_185 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_178 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_159 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_139 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_136 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_133 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_129 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_127 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_114 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_73 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_42 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_29 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_22 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_20 = bits(id_ctrl_decoder_decoded_plaInput, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_73 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_20)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_20 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_42)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_133 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_29)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_178 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_73)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_127 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_127, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_114)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_29 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_133)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_139 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_129)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_188 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_127)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_189 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_188, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_178)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_114 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_159, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_139)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_22 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_188, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_185)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_136 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_178)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_185 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_114)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_129 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_189, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_189)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_42 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_189, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_189)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_159 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_189)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_189 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_159, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_129)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_189 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_189, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_185)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_189 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_189, id_ctrl_decoder_decoded_andMatrixOutputs_lo_189)
node id_ctrl_decoder_decoded_andMatrixOutputs_33_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_189)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_190 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_190 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_190 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_190 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_190 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_189 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_186 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_179 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_160 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_140 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_137 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_134 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_130 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_128 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_115 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_74 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_43 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_30 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_23 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_21 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_13 = bits(id_ctrl_decoder_decoded_plaInput, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_74 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_13)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_21 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_30)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_134 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_23)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_179 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_74)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_128 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_74)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_30 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_130)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_140 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_128)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_189 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_128)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_190 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_189, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_179)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_115 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_140, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_137)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_23 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_186, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_179)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_137 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_160)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_186 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_115)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_190, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_190)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_130 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_189)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_43 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_190, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_190)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_160 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_190)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_190 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_160, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_130)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_190 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_190, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_186)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_190 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_190, id_ctrl_decoder_decoded_andMatrixOutputs_lo_190)
node id_ctrl_decoder_decoded_andMatrixOutputs_85_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_190)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_191 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_191 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_191 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_191 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_191 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_190 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_187 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_180 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_161 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_141 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_138 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_135 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_131 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_129 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_116 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_75 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_44 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_31 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_24 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_22 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_14 = bits(id_ctrl_decoder_decoded_plaInput, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_75 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_14)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_22 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_135 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_24)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_180 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_75)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_129 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_75)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_31 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_131)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_141 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_129)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_190 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_141, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_129)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_191 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_190, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_180)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_116 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_141, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_138)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_24 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_187, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_180)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_138 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_161)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_187 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_116)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_14 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_191, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_191)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_131 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_190)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_44 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_191, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_191)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_161 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_191)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_191 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_161, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_131)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_191 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_191, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_187)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_191 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_191, id_ctrl_decoder_decoded_andMatrixOutputs_lo_191)
node id_ctrl_decoder_decoded_andMatrixOutputs_40_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_191)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_192 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_192 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_192 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_192 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_192 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_191 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_188 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_181 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_162 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_142 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_139 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_136 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_132 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_130 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_117 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_76 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_45 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_32 = bits(id_ctrl_decoder_decoded_plaInput, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_25 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_23 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_15 = bits(id_ctrl_decoder_decoded_plaInput, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_76 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_15)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_23 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_32)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_136 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_25)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_181 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_76)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_130 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_76)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_32 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_132)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_142 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_130)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_191 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_142, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_130)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_192 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_191, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_181)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_117 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_139)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_25 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_188, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_181)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_139 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_162)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_188 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_117)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_192, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_192)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_132 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_191)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_45 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_192, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_192)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_162 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_192)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_192 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_162, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_132)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_192 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_192, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_188)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_192 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_192, id_ctrl_decoder_decoded_andMatrixOutputs_lo_192)
node id_ctrl_decoder_decoded_andMatrixOutputs_12_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_192)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_193 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_193 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_193 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_193 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_193 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_192 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_189 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_182 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_163 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_143 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_140 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_137 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_133 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_131 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_118 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_77 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_46 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_33 = bits(id_ctrl_decoder_decoded_plaInput, 28, 28)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_26 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_24 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30)
node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_16 = bits(id_ctrl_decoder_decoded_plaInput, 31, 31)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_77 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_16)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_24 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_33)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_137 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_26)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_182 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_77)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_131 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_77)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_33 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_137, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_133)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_143 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_131)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_192 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_143, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_131)
node id_ctrl_decoder_decoded_andMatrixOutputs_lo_193 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_192, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_182)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_118 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_140)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_26 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_189, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_182)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_140 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_163)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_189 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_118)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_193, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_193)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_133 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_192)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_46 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_193, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_193)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_163 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_193)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_193 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_163, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_133)
node id_ctrl_decoder_decoded_andMatrixOutputs_hi_193 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_193, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_189)
node _id_ctrl_decoder_decoded_andMatrixOutputs_T_193 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_193, id_ctrl_decoder_decoded_andMatrixOutputs_lo_193)
node id_ctrl_decoder_decoded_andMatrixOutputs_75_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_193)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_118_2, id_ctrl_decoder_decoded_andMatrixOutputs_85_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_40_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_114_2, id_ctrl_decoder_decoded_andMatrixOutputs_174_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_127_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_86_2, id_ctrl_decoder_decoded_andMatrixOutputs_10_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_93_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_148_2, id_ctrl_decoder_decoded_andMatrixOutputs_76_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_87_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_1 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_14_2, id_ctrl_decoder_decoded_andMatrixOutputs_0_2)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_2 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_137_2)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_3 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_2)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_4 = orr(id_ctrl_decoder_decoded_andMatrixOutputs_117_2)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_5 = orr(id_ctrl_decoder_decoded_andMatrixOutputs_21_2)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_6 = orr(id_ctrl_decoder_decoded_andMatrixOutputs_185_2)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_7 = orr(id_ctrl_decoder_decoded_andMatrixOutputs_155_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_47_2, id_ctrl_decoder_decoded_andMatrixOutputs_83_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_1 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_82_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_155_2, id_ctrl_decoder_decoded_andMatrixOutputs_59_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_55_2, id_ctrl_decoder_decoded_andMatrixOutputs_185_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_2 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_1)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_8 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_lo_1)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_9 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_8)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_84_2, id_ctrl_decoder_decoded_andMatrixOutputs_33_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_154_2, id_ctrl_decoder_decoded_andMatrixOutputs_23_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_101_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_57_2, id_ctrl_decoder_decoded_andMatrixOutputs_80_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_166_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_100_2, id_ctrl_decoder_decoded_andMatrixOutputs_89_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_122_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_1 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_1 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_69_2, id_ctrl_decoder_decoded_andMatrixOutputs_151_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_1_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_52_2, id_ctrl_decoder_decoded_andMatrixOutputs_173_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_42_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_180_2, id_ctrl_decoder_decoded_andMatrixOutputs_135_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_188_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_137_2, id_ctrl_decoder_decoded_andMatrixOutputs_159_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_34_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_1 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_2 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_2 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_1)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_0_2, id_ctrl_decoder_decoded_andMatrixOutputs_60_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_41_2, id_ctrl_decoder_decoded_andMatrixOutputs_8_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_28_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_14_2, id_ctrl_decoder_decoded_andMatrixOutputs_155_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_126_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_105_2, id_ctrl_decoder_decoded_andMatrixOutputs_185_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_17_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_1 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_2 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_191_2, id_ctrl_decoder_decoded_andMatrixOutputs_164_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_121_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_7_2, id_ctrl_decoder_decoded_andMatrixOutputs_98_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_71_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_96_2, id_ctrl_decoder_decoded_andMatrixOutputs_35_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_190_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_99_2, id_ctrl_decoder_decoded_andMatrixOutputs_9_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_139_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_1 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_2 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_3 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_2)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_10 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_2)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_11 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_10)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_176_2, id_ctrl_decoder_decoded_andMatrixOutputs_172_2)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_12 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_8_2)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_13 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_12)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_12_2, id_ctrl_decoder_decoded_andMatrixOutputs_75_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_116_2, id_ctrl_decoder_decoded_andMatrixOutputs_156_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_2 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_1)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_51_2, id_ctrl_decoder_decoded_andMatrixOutputs_136_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_72_2, id_ctrl_decoder_decoded_andMatrixOutputs_81_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_2 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_157_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_3 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_1)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_3 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_45_2, id_ctrl_decoder_decoded_andMatrixOutputs_114_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_153_2, id_ctrl_decoder_decoded_andMatrixOutputs_109_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_2 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_187_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_3 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_1)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_77_2, id_ctrl_decoder_decoded_andMatrixOutputs_92_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_181_2, id_ctrl_decoder_decoded_andMatrixOutputs_20_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_2 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_22_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_3 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_1)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_5 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_3)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_14 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_3)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_15 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_14)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_16 = orr(id_ctrl_decoder_decoded_andMatrixOutputs_181_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_109_2, id_ctrl_decoder_decoded_andMatrixOutputs_51_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_3 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_136_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_6_2, id_ctrl_decoder_decoded_andMatrixOutputs_134_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_4 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_153_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_4 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_3)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_123_2, id_ctrl_decoder_decoded_andMatrixOutputs_124_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_4 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_50_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_22_2, id_ctrl_decoder_decoded_andMatrixOutputs_160_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_181_2, id_ctrl_decoder_decoded_andMatrixOutputs_20_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_4 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_6 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_4)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_17 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_4)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_18 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_17)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_84_2, id_ctrl_decoder_decoded_andMatrixOutputs_33_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_23_2, id_ctrl_decoder_decoded_andMatrixOutputs_101_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_4 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_51_2, id_ctrl_decoder_decoded_andMatrixOutputs_136_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_70_2, id_ctrl_decoder_decoded_andMatrixOutputs_174_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_4 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_130_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_5 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_5 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_4)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_109_2, id_ctrl_decoder_decoded_andMatrixOutputs_141_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_6_2, id_ctrl_decoder_decoded_andMatrixOutputs_134_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_4 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_153_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_5 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_124_2, id_ctrl_decoder_decoded_andMatrixOutputs_50_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_181_2, id_ctrl_decoder_decoded_andMatrixOutputs_20_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_4 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_22_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_5 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_3)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_7 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_5)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_19 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_lo_5)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_20 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_19)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_65_2, id_ctrl_decoder_decoded_andMatrixOutputs_79_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_128_2, id_ctrl_decoder_decoded_andMatrixOutputs_165_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_8 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_177_2)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_21 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_lo_6)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_22 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_21)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_137_2, id_ctrl_decoder_decoded_andMatrixOutputs_65_2)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_23 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_58_2)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_24 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_23)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_83_2, id_ctrl_decoder_decoded_andMatrixOutputs_169_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_0_2, id_ctrl_decoder_decoded_andMatrixOutputs_137_2)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_25 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_lo_7)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_26 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_25)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_27 = orr(id_ctrl_decoder_decoded_andMatrixOutputs_14_2)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_28 = orr(id_ctrl_decoder_decoded_andMatrixOutputs_83_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_74_2, id_ctrl_decoder_decoded_andMatrixOutputs_111_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_14_2, id_ctrl_decoder_decoded_andMatrixOutputs_0_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_8 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_5)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_30_2, id_ctrl_decoder_decoded_andMatrixOutputs_140_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_102_2, id_ctrl_decoder_decoded_andMatrixOutputs_9_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_7 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_29_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_11 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_6)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_29 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_lo_8)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_30 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_29)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_142_2, id_ctrl_decoder_decoded_andMatrixOutputs_46_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_6 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_149_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_167_2, id_ctrl_decoder_decoded_andMatrixOutputs_138_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_104_2, id_ctrl_decoder_decoded_andMatrixOutputs_28_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_7 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_3)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_9 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_6)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_15_2, id_ctrl_decoder_decoded_andMatrixOutputs_144_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_94_2, id_ctrl_decoder_decoded_andMatrixOutputs_125_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_7 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_3)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_56_2, id_ctrl_decoder_decoded_andMatrixOutputs_179_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_121_2, id_ctrl_decoder_decoded_andMatrixOutputs_105_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_8 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_4)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_12 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_7)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_31 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_lo_9)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_32 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_31)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_64_2, id_ctrl_decoder_decoded_andMatrixOutputs_142_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_138_2, id_ctrl_decoder_decoded_andMatrixOutputs_173_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_7 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_3)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_25_2, id_ctrl_decoder_decoded_andMatrixOutputs_52_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_43_2, id_ctrl_decoder_decoded_andMatrixOutputs_3_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_6 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_4_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_8 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_4)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_10 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_7)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_73_2, id_ctrl_decoder_decoded_andMatrixOutputs_163_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_168_2, id_ctrl_decoder_decoded_andMatrixOutputs_36_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_8 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_4)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_112_2, id_ctrl_decoder_decoded_andMatrixOutputs_170_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_39_2, id_ctrl_decoder_decoded_andMatrixOutputs_115_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_7 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_162_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_9 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_5)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_13 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_8)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_33 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_lo_10)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_34 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_33)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_180_2, id_ctrl_decoder_decoded_andMatrixOutputs_135_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_5_2, id_ctrl_decoder_decoded_andMatrixOutputs_41_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_9 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_8_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_11 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_8)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_150_2, id_ctrl_decoder_decoded_andMatrixOutputs_161_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_9 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_133_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_17_2, id_ctrl_decoder_decoded_andMatrixOutputs_132_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_10 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_44_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_14 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_9)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_35 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_lo_11)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_36 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_35)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_54_2, id_ctrl_decoder_decoded_andMatrixOutputs_183_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_147_2, id_ctrl_decoder_decoded_andMatrixOutputs_178_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_10 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_19_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_12 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_9)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_48_2, id_ctrl_decoder_decoded_andMatrixOutputs_25_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_129_2, id_ctrl_decoder_decoded_andMatrixOutputs_49_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_11 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_161_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_15 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_10)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_37 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_lo_12)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_38 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_37)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_171_2, id_ctrl_decoder_decoded_andMatrixOutputs_37_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_10 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_122_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_108_2, id_ctrl_decoder_decoded_andMatrixOutputs_89_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_106_2, id_ctrl_decoder_decoded_andMatrixOutputs_186_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_11 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_5)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_13 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_10)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_11_2, id_ctrl_decoder_decoded_andMatrixOutputs_42_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_11 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_69_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_188_2, id_ctrl_decoder_decoded_andMatrixOutputs_27_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_60_2, id_ctrl_decoder_decoded_andMatrixOutputs_48_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_12 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_6)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_16 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_11)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_39 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_lo_13)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_40 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_39)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_62_2, id_ctrl_decoder_decoded_andMatrixOutputs_122_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_151_2, id_ctrl_decoder_decoded_andMatrixOutputs_18_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_4 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_1)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_42_2, id_ctrl_decoder_decoded_andMatrixOutputs_69_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_135_2, id_ctrl_decoder_decoded_andMatrixOutputs_188_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_1 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_52_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_8 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_11 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_4)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_34_2, id_ctrl_decoder_decoded_andMatrixOutputs_180_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_83_2, id_ctrl_decoder_decoded_andMatrixOutputs_159_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_6 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_1)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_60_2, id_ctrl_decoder_decoded_andMatrixOutputs_137_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_189_2, id_ctrl_decoder_decoded_andMatrixOutputs_28_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_4 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_0_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_10 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_1)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_12 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_6)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_14 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_11)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_161_2, id_ctrl_decoder_decoded_andMatrixOutputs_41_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_155_2, id_ctrl_decoder_decoded_andMatrixOutputs_126_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_5 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_1)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_17_2, id_ctrl_decoder_decoded_andMatrixOutputs_14_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_121_2, id_ctrl_decoder_decoded_andMatrixOutputs_95_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_3 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_140_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_9 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_1)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_12 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_5)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_164_2, id_ctrl_decoder_decoded_andMatrixOutputs_30_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_7_2, id_ctrl_decoder_decoded_andMatrixOutputs_131_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_7 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_1)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_35_2, id_ctrl_decoder_decoded_andMatrixOutputs_78_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_99_2, id_ctrl_decoder_decoded_andMatrixOutputs_9_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_4 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_29_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_11 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_1)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_13 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_7)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_17 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_12)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_41 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_lo_14)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_42 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_41)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_66_2, id_ctrl_decoder_decoded_andMatrixOutputs_146_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_18 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_97_2, id_ctrl_decoder_decoded_andMatrixOutputs_164_2)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_43 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_lo_15)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_44 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_43)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_45 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_35_2, id_ctrl_decoder_decoded_andMatrixOutputs_164_2)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_46 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_45)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_100_2, id_ctrl_decoder_decoded_andMatrixOutputs_122_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_42_2, id_ctrl_decoder_decoded_andMatrixOutputs_151_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_9 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_1_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_12 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_5)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_188_2, id_ctrl_decoder_decoded_andMatrixOutputs_52_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_7 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_120_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_28_2, id_ctrl_decoder_decoded_andMatrixOutputs_60_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_11 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_180_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_13 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_7)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_16 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_12)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_91_2, id_ctrl_decoder_decoded_andMatrixOutputs_2_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_24_2, id_ctrl_decoder_decoded_andMatrixOutputs_53_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_10 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_17_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_13 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_6)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_191_2, id_ctrl_decoder_decoded_andMatrixOutputs_26_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_8 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_61_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_99_2, id_ctrl_decoder_decoded_andMatrixOutputs_9_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_12 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_96_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_14 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_8)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_19 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_13)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_47 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_19, id_ctrl_decoder_decoded_orMatrixOutputs_lo_16)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_48 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_47)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_12_2, id_ctrl_decoder_decoded_andMatrixOutputs_75_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_122_2, id_ctrl_decoder_decoded_andMatrixOutputs_116_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_2 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_156_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_6 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_1_2, id_ctrl_decoder_decoded_andMatrixOutputs_100_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_2 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_89_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_42_2, id_ctrl_decoder_decoded_andMatrixOutputs_69_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_3 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_151_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_10 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_13 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_6)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_52_2, id_ctrl_decoder_decoded_andMatrixOutputs_173_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_180_2, id_ctrl_decoder_decoded_andMatrixOutputs_135_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_3 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_188_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_8 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_31_2, id_ctrl_decoder_decoded_andMatrixOutputs_159_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_2 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_34_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_0_2, id_ctrl_decoder_decoded_andMatrixOutputs_60_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_6 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_137_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_12 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_14 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_8)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_17 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_13)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_8_2, id_ctrl_decoder_decoded_andMatrixOutputs_28_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_126_2, id_ctrl_decoder_decoded_andMatrixOutputs_161_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_2 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_41_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_7 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_17_2, id_ctrl_decoder_decoded_andMatrixOutputs_14_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_2 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_184_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_105_2, id_ctrl_decoder_decoded_andMatrixOutputs_16_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_5 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_140_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_11 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_14 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_7)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_30_2, id_ctrl_decoder_decoded_andMatrixOutputs_121_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_98_2, id_ctrl_decoder_decoded_andMatrixOutputs_71_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_3 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_131_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_9 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_96_2, id_ctrl_decoder_decoded_andMatrixOutputs_190_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_2 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_7_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_99_2, id_ctrl_decoder_decoded_andMatrixOutputs_9_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_6 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_29_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_13 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_15 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_9)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_20 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_14)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_49 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_20, id_ctrl_decoder_decoded_orMatrixOutputs_lo_17)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_50 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_49)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_28_2, id_ctrl_decoder_decoded_andMatrixOutputs_159_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_18 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_34_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_182_2, id_ctrl_decoder_decoded_andMatrixOutputs_164_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_21 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_189_2)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_51 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_21, id_ctrl_decoder_decoded_orMatrixOutputs_lo_18)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_52 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_51)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_1_2, id_ctrl_decoder_decoded_andMatrixOutputs_100_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_7 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_122_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_120_2, id_ctrl_decoder_decoded_andMatrixOutputs_42_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_11 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_151_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_14 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_7)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_180_2, id_ctrl_decoder_decoded_andMatrixOutputs_188_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_9 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_52_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_2_2, id_ctrl_decoder_decoded_andMatrixOutputs_28_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_13 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_60_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_16 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_9)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_19 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_14)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_140_2, id_ctrl_decoder_decoded_andMatrixOutputs_17_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_8 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_91_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_30_2, id_ctrl_decoder_decoded_andMatrixOutputs_61_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_12 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_24_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_15 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_8)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_35_2, id_ctrl_decoder_decoded_andMatrixOutputs_191_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_10 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_164_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_29_2, id_ctrl_decoder_decoded_andMatrixOutputs_96_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_99_2, id_ctrl_decoder_decoded_andMatrixOutputs_9_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_14 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_3)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_17 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_10)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_22 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_15)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_53 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_22, id_ctrl_decoder_decoded_orMatrixOutputs_lo_19)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_54 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_53)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_89_2, id_ctrl_decoder_decoded_andMatrixOutputs_122_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_1_2, id_ctrl_decoder_decoded_andMatrixOutputs_100_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_8 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_3)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_142_2, id_ctrl_decoder_decoded_andMatrixOutputs_151_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_138_2, id_ctrl_decoder_decoded_andMatrixOutputs_173_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_12 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_3)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_15 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_8)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_188_2, id_ctrl_decoder_decoded_andMatrixOutputs_52_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_159_2, id_ctrl_decoder_decoded_andMatrixOutputs_34_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_10 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_28_2, id_ctrl_decoder_decoded_andMatrixOutputs_60_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_146_2, id_ctrl_decoder_decoded_andMatrixOutputs_41_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_8 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_8_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_14 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_17 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_10)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_20 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_15)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_126_2, id_ctrl_decoder_decoded_andMatrixOutputs_66_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_140_2, id_ctrl_decoder_decoded_andMatrixOutputs_17_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_9 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_3)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_121_2, id_ctrl_decoder_decoded_andMatrixOutputs_105_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_97_2, id_ctrl_decoder_decoded_andMatrixOutputs_131_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_7 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_30_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_13 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_3)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_16 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_9)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_98_2, id_ctrl_decoder_decoded_andMatrixOutputs_71_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_190_2, id_ctrl_decoder_decoded_andMatrixOutputs_7_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_11 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_3)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_96_2, id_ctrl_decoder_decoded_andMatrixOutputs_35_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_99_2, id_ctrl_decoder_decoded_andMatrixOutputs_9_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_8 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_29_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_15 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_4)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_18 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_11)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_23 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_16)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_55 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_23, id_ctrl_decoder_decoded_orMatrixOutputs_lo_20)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_56 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_55)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_21 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_68_2, id_ctrl_decoder_decoded_andMatrixOutputs_63_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_24 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_180_2, id_ctrl_decoder_decoded_andMatrixOutputs_135_2)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_57 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_24, id_ctrl_decoder_decoded_orMatrixOutputs_lo_21)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_58 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_57)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_12_2, id_ctrl_decoder_decoded_andMatrixOutputs_75_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_122_2, id_ctrl_decoder_decoded_andMatrixOutputs_116_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_5 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_156_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_9 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_1_2, id_ctrl_decoder_decoded_andMatrixOutputs_100_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_4 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_89_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_42_2, id_ctrl_decoder_decoded_andMatrixOutputs_69_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_6 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_151_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_13 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_4)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_16 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_9)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_52_2, id_ctrl_decoder_decoded_andMatrixOutputs_173_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_180_2, id_ctrl_decoder_decoded_andMatrixOutputs_135_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_6 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_188_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_11 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_4)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_31_2, id_ctrl_decoder_decoded_andMatrixOutputs_159_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_4 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_34_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_0_2, id_ctrl_decoder_decoded_andMatrixOutputs_60_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_9 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_137_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_15 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_4)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_18 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_11)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_22 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_16)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_8_2, id_ctrl_decoder_decoded_andMatrixOutputs_28_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_126_2, id_ctrl_decoder_decoded_andMatrixOutputs_161_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_5 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_41_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_10 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_17_2, id_ctrl_decoder_decoded_andMatrixOutputs_14_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_4 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_184_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_105_2, id_ctrl_decoder_decoded_andMatrixOutputs_16_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_8 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_140_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_14 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_4)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_17 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_10)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_30_2, id_ctrl_decoder_decoded_andMatrixOutputs_121_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_98_2, id_ctrl_decoder_decoded_andMatrixOutputs_71_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_6 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_131_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_12 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_4)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_96_2, id_ctrl_decoder_decoded_andMatrixOutputs_190_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_5 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_7_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_99_2, id_ctrl_decoder_decoded_andMatrixOutputs_9_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_9 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_29_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_16 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_5)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_19 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_12)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_25 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_19, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_17)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_59 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_25, id_ctrl_decoder_decoded_orMatrixOutputs_lo_22)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_60 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_59)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_69_2, id_ctrl_decoder_decoded_andMatrixOutputs_89_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_159_2, id_ctrl_decoder_decoded_andMatrixOutputs_34_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_14 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_135_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_17 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_10)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_0_2, id_ctrl_decoder_decoded_andMatrixOutputs_137_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_12 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_13_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_41_2, id_ctrl_decoder_decoded_andMatrixOutputs_8_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_16 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_28_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_19 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_12)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_23 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_19, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_17)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_161_2, id_ctrl_decoder_decoded_andMatrixOutputs_88_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_71_2, id_ctrl_decoder_decoded_andMatrixOutputs_14_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_15 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_126_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_18 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_11)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_7_2, id_ctrl_decoder_decoded_andMatrixOutputs_98_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_13 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_32_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_128_2, id_ctrl_decoder_decoded_andMatrixOutputs_67_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_17 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_190_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_20 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_13)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_26 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_20, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_18)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_61 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_26, id_ctrl_decoder_decoded_orMatrixOutputs_lo_23)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_62 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_61)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_63 = orr(id_ctrl_decoder_decoded_andMatrixOutputs_191_2)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_64 = orr(id_ctrl_decoder_decoded_andMatrixOutputs_164_2)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_65 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_97_2, id_ctrl_decoder_decoded_andMatrixOutputs_161_2)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_66 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_65)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_158_2, id_ctrl_decoder_decoded_andMatrixOutputs_110_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_136_2, id_ctrl_decoder_decoded_andMatrixOutputs_192_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_15 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_38_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_18 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_11)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_130_2, id_ctrl_decoder_decoded_andMatrixOutputs_51_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_141_2, id_ctrl_decoder_decoded_andMatrixOutputs_70_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_17 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_174_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_20 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_13)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_24 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_20, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_18)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_153_2, id_ctrl_decoder_decoded_andMatrixOutputs_109_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_50_2, id_ctrl_decoder_decoded_andMatrixOutputs_6_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_16 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_134_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_19 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_12)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_175_2, id_ctrl_decoder_decoded_andMatrixOutputs_193_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_14 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_124_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_181_2, id_ctrl_decoder_decoded_andMatrixOutputs_20_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_18 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_22_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_21 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_14)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_27 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_21, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_19)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_67 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_27, id_ctrl_decoder_decoded_orMatrixOutputs_lo_24)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_68 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_67)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_84_2, id_ctrl_decoder_decoded_andMatrixOutputs_33_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_113_2, id_ctrl_decoder_decoded_andMatrixOutputs_107_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_5 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_lo)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_158_2, id_ctrl_decoder_decoded_andMatrixOutputs_110_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_122_2, id_ctrl_decoder_decoded_andMatrixOutputs_119_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_6 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_12 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_5)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_108_2, id_ctrl_decoder_decoded_andMatrixOutputs_89_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_106_2, id_ctrl_decoder_decoded_andMatrixOutputs_186_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_5 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_lo)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_51_2, id_ctrl_decoder_decoded_andMatrixOutputs_136_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_130_2, id_ctrl_decoder_decoded_andMatrixOutputs_42_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_4 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_69_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_9 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_16 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_5)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_19 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_12)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_70_2, id_ctrl_decoder_decoded_andMatrixOutputs_174_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_173_2, id_ctrl_decoder_decoded_andMatrixOutputs_141_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_5 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_lo)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_188_2, id_ctrl_decoder_decoded_andMatrixOutputs_52_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_180_2, id_ctrl_decoder_decoded_andMatrixOutputs_135_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_8 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_14 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_5)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_159_2, id_ctrl_decoder_decoded_andMatrixOutputs_34_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_153_2, id_ctrl_decoder_decoded_andMatrixOutputs_109_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_5 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_lo)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_6_2, id_ctrl_decoder_decoded_andMatrixOutputs_134_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_111_2, id_ctrl_decoder_decoded_andMatrixOutputs_124_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_5 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_50_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_12 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_18 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_5)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_21 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_14)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_25 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_21, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_19)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_152_2, id_ctrl_decoder_decoded_andMatrixOutputs_103_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_60_2, id_ctrl_decoder_decoded_andMatrixOutputs_74_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_5 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_lo)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_28_2, id_ctrl_decoder_decoded_andMatrixOutputs_0_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_41_2, id_ctrl_decoder_decoded_andMatrixOutputs_8_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_6 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_lo)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_13 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_5)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_126_2, id_ctrl_decoder_decoded_andMatrixOutputs_161_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_14_2, id_ctrl_decoder_decoded_andMatrixOutputs_155_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_5 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_lo)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_140_2, id_ctrl_decoder_decoded_andMatrixOutputs_17_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_121_2, id_ctrl_decoder_decoded_andMatrixOutputs_105_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_5 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_95_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_11 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_17 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_5)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_20 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_13)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_90_2, id_ctrl_decoder_decoded_andMatrixOutputs_30_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_131_2, id_ctrl_decoder_decoded_andMatrixOutputs_164_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_5 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_lo)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_20_2, id_ctrl_decoder_decoded_andMatrixOutputs_22_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_71_2, id_ctrl_decoder_decoded_andMatrixOutputs_145_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_3 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_143_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_9 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_15 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_5)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_7_2, id_ctrl_decoder_decoded_andMatrixOutputs_98_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_35_2, id_ctrl_decoder_decoded_andMatrixOutputs_190_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_6 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_117_2, id_ctrl_decoder_decoded_andMatrixOutputs_96_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_99_2, id_ctrl_decoder_decoded_andMatrixOutputs_9_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_5 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_29_2)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_12 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_19 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_6)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_22 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_19, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_15)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_28 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_22, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_20)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_69 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_28, id_ctrl_decoder_decoded_orMatrixOutputs_lo_25)
node _id_ctrl_decoder_decoded_orMatrixOutputs_T_70 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_69)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_6 = cat(_id_ctrl_decoder_decoded_orMatrixOutputs_T_3, _id_ctrl_decoder_decoded_orMatrixOutputs_T_1)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_4 = cat(_id_ctrl_decoder_decoded_orMatrixOutputs_T_6, _id_ctrl_decoder_decoded_orMatrixOutputs_T_5)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_7 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_4)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_13 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_6)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_6 = cat(_id_ctrl_decoder_decoded_orMatrixOutputs_T_9, _id_ctrl_decoder_decoded_orMatrixOutputs_T_7)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_5 = cat(UInt<1>(0h0), _id_ctrl_decoder_decoded_orMatrixOutputs_T_13)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_10 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_5, _id_ctrl_decoder_decoded_orMatrixOutputs_T_11)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_17 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_6)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_20 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_13)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_6 = cat(_id_ctrl_decoder_decoded_orMatrixOutputs_T_16, _id_ctrl_decoder_decoded_orMatrixOutputs_T_15)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_4 = cat(_id_ctrl_decoder_decoded_orMatrixOutputs_T_22, _id_ctrl_decoder_decoded_orMatrixOutputs_T_20)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_9 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_18)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_15 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_6)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_4 = cat(_id_ctrl_decoder_decoded_orMatrixOutputs_T_27, _id_ctrl_decoder_decoded_orMatrixOutputs_T_26)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_6 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_24)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_6 = cat(_id_ctrl_decoder_decoded_orMatrixOutputs_T_32, _id_ctrl_decoder_decoded_orMatrixOutputs_T_30)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_13 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_6, _id_ctrl_decoder_decoded_orMatrixOutputs_T_28)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_19 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_6)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_22 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_19, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_15)
node id_ctrl_decoder_decoded_orMatrixOutputs_lo_26 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_22, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_20)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_6 = cat(_id_ctrl_decoder_decoded_orMatrixOutputs_T_36, _id_ctrl_decoder_decoded_orMatrixOutputs_T_34)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_4 = cat(_id_ctrl_decoder_decoded_orMatrixOutputs_T_42, _id_ctrl_decoder_decoded_orMatrixOutputs_T_40)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_7 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_38)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_14 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_6)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_6 = cat(_id_ctrl_decoder_decoded_orMatrixOutputs_T_46, _id_ctrl_decoder_decoded_orMatrixOutputs_T_44)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_6 = cat(_id_ctrl_decoder_decoded_orMatrixOutputs_T_52, _id_ctrl_decoder_decoded_orMatrixOutputs_T_50)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_12 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_6, _id_ctrl_decoder_decoded_orMatrixOutputs_T_48)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_18 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_6)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_21 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_14)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_6 = cat(_id_ctrl_decoder_decoded_orMatrixOutputs_T_56, _id_ctrl_decoder_decoded_orMatrixOutputs_T_54)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_4 = cat(_id_ctrl_decoder_decoded_orMatrixOutputs_T_62, _id_ctrl_decoder_decoded_orMatrixOutputs_T_60)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_10 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_58)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_16 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_6)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_4 = cat(_id_ctrl_decoder_decoded_orMatrixOutputs_T_66, _id_ctrl_decoder_decoded_orMatrixOutputs_T_64)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_7 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_63)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_6 = cat(_id_ctrl_decoder_decoded_orMatrixOutputs_T_70, _id_ctrl_decoder_decoded_orMatrixOutputs_T_68)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_13 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_6, UInt<1>(0h0))
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_20 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_7)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_23 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_20, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_16)
node id_ctrl_decoder_decoded_orMatrixOutputs_hi_29 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_23, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_21)
node id_ctrl_decoder_decoded_orMatrixOutputs = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_29, id_ctrl_decoder_decoded_orMatrixOutputs_lo_26)
node _id_ctrl_decoder_decoded_invMatrixOutputs_T = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 0, 0)
node _id_ctrl_decoder_decoded_invMatrixOutputs_T_1 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 1, 1)
node _id_ctrl_decoder_decoded_invMatrixOutputs_T_2 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 2, 2)
node _id_ctrl_decoder_decoded_invMatrixOutputs_T_3 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 3, 3)
node _id_ctrl_decoder_decoded_invMatrixOutputs_T_4 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 4, 4)
node _id_ctrl_decoder_decoded_invMatrixOutputs_T_5 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 5, 5)
node _id_ctrl_decoder_decoded_invMatrixOutputs_T_6 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 6, 6)
node _id_ctrl_decoder_decoded_invMatrixOutputs_T_7 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 7, 7)
node _id_ctrl_decoder_decoded_invMatrixOutputs_T_8 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 8, 8)
node _id_ctrl_decoder_decoded_invMatrixOutputs_T_9 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 9, 9)
node _id_ctrl_decoder_decoded_invMatrixOutputs_T_10 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 10, 10)
node _id_ctrl_decoder_decoded_invMatrixOutputs_T_11 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 11, 11)
node _id_ctrl_decoder_decoded_invMatrixOutputs_T_12 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 12, 12)
node _id_ctrl_decoder_decoded_invMatrixOutputs_T_13 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 13, 13)
node _id_ctrl_decoder_decoded_invMatrixOutputs_T_14 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 14, 14)
node _id_ctrl_decoder_decoded_invMatrixOutputs_T_15 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 15, 15)
node _id_ctrl_decoder_decoded_invMatrixOutputs_T_16 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 16, 16)
node _id_ctrl_decoder_decoded_invMatrixOutputs_T_17 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 17, 17)
node _id_ctrl_decoder_decoded_invMatrixOutputs_T_18 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 18, 18)
node _id_ctrl_decoder_decoded_invMatrixOutputs_T_19 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 19, 19)
node _id_ctrl_decoder_decoded_invMatrixOutputs_T_20 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 20, 20)
node _id_ctrl_decoder_decoded_invMatrixOutputs_T_21 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 21, 21)
node _id_ctrl_decoder_decoded_invMatrixOutputs_T_22 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 22, 22)
node _id_ctrl_decoder_decoded_invMatrixOutputs_T_23 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 23, 23)
node _id_ctrl_decoder_decoded_invMatrixOutputs_T_24 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 24, 24)
node _id_ctrl_decoder_decoded_invMatrixOutputs_T_25 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 25, 25)
node _id_ctrl_decoder_decoded_invMatrixOutputs_T_26 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 26, 26)
node _id_ctrl_decoder_decoded_invMatrixOutputs_T_27 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 27, 27)
node _id_ctrl_decoder_decoded_invMatrixOutputs_T_28 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 28, 28)
node _id_ctrl_decoder_decoded_invMatrixOutputs_T_29 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 29, 29)
node _id_ctrl_decoder_decoded_invMatrixOutputs_T_30 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 30, 30)
node _id_ctrl_decoder_decoded_invMatrixOutputs_T_31 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 31, 31)
node _id_ctrl_decoder_decoded_invMatrixOutputs_T_32 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 32, 32)
node _id_ctrl_decoder_decoded_invMatrixOutputs_T_33 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 33, 33)
node _id_ctrl_decoder_decoded_invMatrixOutputs_T_34 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 34, 34)
node _id_ctrl_decoder_decoded_invMatrixOutputs_T_35 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 35, 35)
node _id_ctrl_decoder_decoded_invMatrixOutputs_T_36 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 36, 36)
node _id_ctrl_decoder_decoded_invMatrixOutputs_T_37 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 37, 37)
node _id_ctrl_decoder_decoded_invMatrixOutputs_T_38 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 38, 38)
node _id_ctrl_decoder_decoded_invMatrixOutputs_T_39 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 39, 39)
node _id_ctrl_decoder_decoded_invMatrixOutputs_T_40 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 40, 40)
node _id_ctrl_decoder_decoded_invMatrixOutputs_T_41 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 41, 41)
node id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo = cat(_id_ctrl_decoder_decoded_invMatrixOutputs_T_1, _id_ctrl_decoder_decoded_invMatrixOutputs_T)
node id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_hi = cat(_id_ctrl_decoder_decoded_invMatrixOutputs_T_4, _id_ctrl_decoder_decoded_invMatrixOutputs_T_3)
node id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi = cat(id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_2)
node id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo = cat(id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo)
node id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo = cat(_id_ctrl_decoder_decoded_invMatrixOutputs_T_6, _id_ctrl_decoder_decoded_invMatrixOutputs_T_5)
node id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_hi = cat(_id_ctrl_decoder_decoded_invMatrixOutputs_T_9, _id_ctrl_decoder_decoded_invMatrixOutputs_T_8)
node id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi = cat(id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_7)
node id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi = cat(id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo)
node id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo = cat(id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo)
node id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo = cat(_id_ctrl_decoder_decoded_invMatrixOutputs_T_11, _id_ctrl_decoder_decoded_invMatrixOutputs_T_10)
node id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_hi = cat(_id_ctrl_decoder_decoded_invMatrixOutputs_T_14, _id_ctrl_decoder_decoded_invMatrixOutputs_T_13)
node id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi = cat(id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_12)
node id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo = cat(id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo)
node id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo_hi = cat(_id_ctrl_decoder_decoded_invMatrixOutputs_T_17, _id_ctrl_decoder_decoded_invMatrixOutputs_T_16)
node id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo = cat(id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_15)
node id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_hi = cat(_id_ctrl_decoder_decoded_invMatrixOutputs_T_20, _id_ctrl_decoder_decoded_invMatrixOutputs_T_19)
node id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi = cat(id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_18)
node id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi = cat(id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo)
node id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi = cat(id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo)
node id_ctrl_decoder_decoded_invMatrixOutputs_lo = cat(id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo)
node id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo = cat(_id_ctrl_decoder_decoded_invMatrixOutputs_T_22, _id_ctrl_decoder_decoded_invMatrixOutputs_T_21)
node id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_hi = cat(_id_ctrl_decoder_decoded_invMatrixOutputs_T_25, _id_ctrl_decoder_decoded_invMatrixOutputs_T_24)
node id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi = cat(id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_23)
node id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo = cat(id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo)
node id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo = cat(_id_ctrl_decoder_decoded_invMatrixOutputs_T_27, _id_ctrl_decoder_decoded_invMatrixOutputs_T_26)
node id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_hi = cat(_id_ctrl_decoder_decoded_invMatrixOutputs_T_30, _id_ctrl_decoder_decoded_invMatrixOutputs_T_29)
node id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi = cat(id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_28)
node id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi = cat(id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo)
node id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo = cat(id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo)
node id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo = cat(_id_ctrl_decoder_decoded_invMatrixOutputs_T_32, _id_ctrl_decoder_decoded_invMatrixOutputs_T_31)
node id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_hi = cat(_id_ctrl_decoder_decoded_invMatrixOutputs_T_35, _id_ctrl_decoder_decoded_invMatrixOutputs_T_34)
node id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi = cat(id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_33)
node id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo = cat(id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo)
node id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_hi = cat(_id_ctrl_decoder_decoded_invMatrixOutputs_T_38, _id_ctrl_decoder_decoded_invMatrixOutputs_T_37)
node id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo = cat(id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_36)
node id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_hi = cat(_id_ctrl_decoder_decoded_invMatrixOutputs_T_41, _id_ctrl_decoder_decoded_invMatrixOutputs_T_40)
node id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi = cat(id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_39)
node id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi = cat(id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo)
node id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi = cat(id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo)
node id_ctrl_decoder_decoded_invMatrixOutputs_hi = cat(id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo)
node id_ctrl_decoder_decoded_invMatrixOutputs = cat(id_ctrl_decoder_decoded_invMatrixOutputs_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo)
connect id_ctrl_decoder_decoded, id_ctrl_decoder_decoded_invMatrixOutputs
connect id_ctrl_decoder_decoded_plaInput, ibuf.io.inst[0].bits.inst.bits
node id_ctrl_decoder_0 = bits(id_ctrl_decoder_decoded, 41, 41)
node id_ctrl_decoder_1 = bits(id_ctrl_decoder_decoded, 40, 40)
node id_ctrl_decoder_2 = bits(id_ctrl_decoder_decoded, 39, 39)
node id_ctrl_decoder_3 = bits(id_ctrl_decoder_decoded, 38, 38)
node id_ctrl_decoder_4 = bits(id_ctrl_decoder_decoded, 37, 37)
node id_ctrl_decoder_5 = bits(id_ctrl_decoder_decoded, 36, 36)
node id_ctrl_decoder_6 = bits(id_ctrl_decoder_decoded, 35, 35)
node id_ctrl_decoder_7 = bits(id_ctrl_decoder_decoded, 34, 34)
node id_ctrl_decoder_8 = bits(id_ctrl_decoder_decoded, 33, 31)
node id_ctrl_decoder_9 = bits(id_ctrl_decoder_decoded, 30, 29)
node id_ctrl_decoder_10 = bits(id_ctrl_decoder_decoded, 28, 26)
node id_ctrl_decoder_11 = bits(id_ctrl_decoder_decoded, 25, 25)
node id_ctrl_decoder_12 = bits(id_ctrl_decoder_decoded, 24, 20)
node id_ctrl_decoder_13 = bits(id_ctrl_decoder_decoded, 19, 19)
node id_ctrl_decoder_14 = bits(id_ctrl_decoder_decoded, 18, 14)
node id_ctrl_decoder_15 = bits(id_ctrl_decoder_decoded, 13, 13)
node id_ctrl_decoder_16 = bits(id_ctrl_decoder_decoded, 12, 12)
node id_ctrl_decoder_17 = bits(id_ctrl_decoder_decoded, 11, 11)
node id_ctrl_decoder_18 = bits(id_ctrl_decoder_decoded, 10, 10)
node id_ctrl_decoder_19 = bits(id_ctrl_decoder_decoded, 9, 9)
node id_ctrl_decoder_20 = bits(id_ctrl_decoder_decoded, 8, 8)
node id_ctrl_decoder_21 = bits(id_ctrl_decoder_decoded, 7, 7)
node id_ctrl_decoder_22 = bits(id_ctrl_decoder_decoded, 6, 4)
node id_ctrl_decoder_23 = bits(id_ctrl_decoder_decoded, 3, 3)
node id_ctrl_decoder_24 = bits(id_ctrl_decoder_decoded, 2, 2)
node id_ctrl_decoder_25 = bits(id_ctrl_decoder_decoded, 1, 1)
node id_ctrl_decoder_26 = bits(id_ctrl_decoder_decoded, 0, 0)
connect id_ctrl.legal, id_ctrl_decoder_0
connect id_ctrl.fp, id_ctrl_decoder_1
connect id_ctrl.rocc, id_ctrl_decoder_2
connect id_ctrl.branch, id_ctrl_decoder_3
connect id_ctrl.jal, id_ctrl_decoder_4
connect id_ctrl.jalr, id_ctrl_decoder_5
connect id_ctrl.rxs2, id_ctrl_decoder_6
connect id_ctrl.rxs1, id_ctrl_decoder_7
connect id_ctrl.sel_alu2, id_ctrl_decoder_8
connect id_ctrl.sel_alu1, id_ctrl_decoder_9
connect id_ctrl.sel_imm, id_ctrl_decoder_10
connect id_ctrl.alu_dw, id_ctrl_decoder_11
connect id_ctrl.alu_fn, id_ctrl_decoder_12
connect id_ctrl.mem, id_ctrl_decoder_13
connect id_ctrl.mem_cmd, id_ctrl_decoder_14
connect id_ctrl.rfs1, id_ctrl_decoder_15
connect id_ctrl.rfs2, id_ctrl_decoder_16
connect id_ctrl.rfs3, id_ctrl_decoder_17
connect id_ctrl.wfd, id_ctrl_decoder_18
connect id_ctrl.mul, id_ctrl_decoder_19
connect id_ctrl.div, id_ctrl_decoder_20
connect id_ctrl.wxd, id_ctrl_decoder_21
connect id_ctrl.csr, id_ctrl_decoder_22
connect id_ctrl.fence_i, id_ctrl_decoder_23
connect id_ctrl.fence, id_ctrl_decoder_24
connect id_ctrl.amo, id_ctrl_decoder_25
connect id_ctrl.dp, id_ctrl_decoder_26
node id_raddr3 = bits(ibuf.io.inst[0].bits.inst.rs3, 4, 0)
node id_raddr2 = bits(ibuf.io.inst[0].bits.inst.rs2, 4, 0)
node id_raddr1 = bits(ibuf.io.inst[0].bits.inst.rs1, 4, 0)
node id_waddr = bits(ibuf.io.inst[0].bits.inst.rd, 4, 0)
wire id_load_use : UInt<1>
regreset id_reg_fence : UInt<1>, clock, reset, UInt<1>(0h0)
cmem rf : UInt<64> [31]
wire id_rs_0 : UInt
node _id_rs_T = eq(id_raddr1, UInt<1>(0h0))
node _id_rs_T_1 = and(UInt<1>(0h0), _id_rs_T)
node _id_rs_T_2 = bits(id_raddr1, 4, 0)
node _id_rs_T_3 = not(_id_rs_T_2)
infer mport id_rs_MPORT = rf[_id_rs_T_3], clock
node _id_rs_T_4 = mux(_id_rs_T_1, UInt<1>(0h0), id_rs_MPORT)
connect id_rs_0, _id_rs_T_4
wire id_rs_1 : UInt
node _id_rs_T_5 = eq(id_raddr2, UInt<1>(0h0))
node _id_rs_T_6 = and(UInt<1>(0h0), _id_rs_T_5)
node _id_rs_T_7 = bits(id_raddr2, 4, 0)
node _id_rs_T_8 = not(_id_rs_T_7)
infer mport id_rs_MPORT_1 = rf[_id_rs_T_8], clock
node _id_rs_T_9 = mux(_id_rs_T_6, UInt<1>(0h0), id_rs_MPORT_1)
connect id_rs_1, _id_rs_T_9
wire ctrl_killd : UInt<1>
node _id_npc_T = asSInt(ibuf.io.pc)
node _id_npc_sign_T = eq(UInt<3>(0h3), UInt<3>(0h5))
node _id_npc_sign_T_1 = bits(ibuf.io.inst[0].bits.inst.bits, 31, 31)
node _id_npc_sign_T_2 = asSInt(_id_npc_sign_T_1)
node id_npc_sign = mux(_id_npc_sign_T, asSInt(UInt<1>(0h0)), _id_npc_sign_T_2)
node _id_npc_b30_20_T = eq(UInt<3>(0h3), UInt<3>(0h2))
node _id_npc_b30_20_T_1 = bits(ibuf.io.inst[0].bits.inst.bits, 30, 20)
node _id_npc_b30_20_T_2 = asSInt(_id_npc_b30_20_T_1)
node id_npc_b30_20 = mux(_id_npc_b30_20_T, _id_npc_b30_20_T_2, id_npc_sign)
node _id_npc_b19_12_T = neq(UInt<3>(0h3), UInt<3>(0h2))
node _id_npc_b19_12_T_1 = neq(UInt<3>(0h3), UInt<3>(0h3))
node _id_npc_b19_12_T_2 = and(_id_npc_b19_12_T, _id_npc_b19_12_T_1)
node _id_npc_b19_12_T_3 = bits(ibuf.io.inst[0].bits.inst.bits, 19, 12)
node _id_npc_b19_12_T_4 = asSInt(_id_npc_b19_12_T_3)
node id_npc_b19_12 = mux(_id_npc_b19_12_T_2, id_npc_sign, _id_npc_b19_12_T_4)
node _id_npc_b11_T = eq(UInt<3>(0h3), UInt<3>(0h2))
node _id_npc_b11_T_1 = eq(UInt<3>(0h3), UInt<3>(0h5))
node _id_npc_b11_T_2 = or(_id_npc_b11_T, _id_npc_b11_T_1)
node _id_npc_b11_T_3 = eq(UInt<3>(0h3), UInt<3>(0h3))
node _id_npc_b11_T_4 = bits(ibuf.io.inst[0].bits.inst.bits, 20, 20)
node _id_npc_b11_T_5 = asSInt(_id_npc_b11_T_4)
node _id_npc_b11_T_6 = eq(UInt<3>(0h3), UInt<3>(0h1))
node _id_npc_b11_T_7 = bits(ibuf.io.inst[0].bits.inst.bits, 7, 7)
node _id_npc_b11_T_8 = asSInt(_id_npc_b11_T_7)
node _id_npc_b11_T_9 = mux(_id_npc_b11_T_6, _id_npc_b11_T_8, id_npc_sign)
node _id_npc_b11_T_10 = mux(_id_npc_b11_T_3, _id_npc_b11_T_5, _id_npc_b11_T_9)
node id_npc_b11 = mux(_id_npc_b11_T_2, asSInt(UInt<1>(0h0)), _id_npc_b11_T_10)
node _id_npc_b10_5_T = eq(UInt<3>(0h3), UInt<3>(0h2))
node _id_npc_b10_5_T_1 = eq(UInt<3>(0h3), UInt<3>(0h5))
node _id_npc_b10_5_T_2 = or(_id_npc_b10_5_T, _id_npc_b10_5_T_1)
node _id_npc_b10_5_T_3 = bits(ibuf.io.inst[0].bits.inst.bits, 30, 25)
node id_npc_b10_5 = mux(_id_npc_b10_5_T_2, UInt<1>(0h0), _id_npc_b10_5_T_3)
node _id_npc_b4_1_T = eq(UInt<3>(0h3), UInt<3>(0h2))
node _id_npc_b4_1_T_1 = eq(UInt<3>(0h3), UInt<3>(0h0))
node _id_npc_b4_1_T_2 = eq(UInt<3>(0h3), UInt<3>(0h1))
node _id_npc_b4_1_T_3 = or(_id_npc_b4_1_T_1, _id_npc_b4_1_T_2)
node _id_npc_b4_1_T_4 = bits(ibuf.io.inst[0].bits.inst.bits, 11, 8)
node _id_npc_b4_1_T_5 = eq(UInt<3>(0h3), UInt<3>(0h5))
node _id_npc_b4_1_T_6 = bits(ibuf.io.inst[0].bits.inst.bits, 19, 16)
node _id_npc_b4_1_T_7 = bits(ibuf.io.inst[0].bits.inst.bits, 24, 21)
node _id_npc_b4_1_T_8 = mux(_id_npc_b4_1_T_5, _id_npc_b4_1_T_6, _id_npc_b4_1_T_7)
node _id_npc_b4_1_T_9 = mux(_id_npc_b4_1_T_3, _id_npc_b4_1_T_4, _id_npc_b4_1_T_8)
node id_npc_b4_1 = mux(_id_npc_b4_1_T, UInt<1>(0h0), _id_npc_b4_1_T_9)
node _id_npc_b0_T = eq(UInt<3>(0h3), UInt<3>(0h0))
node _id_npc_b0_T_1 = bits(ibuf.io.inst[0].bits.inst.bits, 7, 7)
node _id_npc_b0_T_2 = eq(UInt<3>(0h3), UInt<3>(0h4))
node _id_npc_b0_T_3 = bits(ibuf.io.inst[0].bits.inst.bits, 20, 20)
node _id_npc_b0_T_4 = eq(UInt<3>(0h3), UInt<3>(0h5))
node _id_npc_b0_T_5 = bits(ibuf.io.inst[0].bits.inst.bits, 15, 15)
node _id_npc_b0_T_6 = mux(_id_npc_b0_T_4, _id_npc_b0_T_5, UInt<1>(0h0))
node _id_npc_b0_T_7 = mux(_id_npc_b0_T_2, _id_npc_b0_T_3, _id_npc_b0_T_6)
node id_npc_b0 = mux(_id_npc_b0_T, _id_npc_b0_T_1, _id_npc_b0_T_7)
node id_npc_lo_hi = cat(id_npc_b10_5, id_npc_b4_1)
node id_npc_lo = cat(id_npc_lo_hi, id_npc_b0)
node id_npc_hi_lo_lo = asUInt(id_npc_b11)
node id_npc_hi_lo_hi = asUInt(id_npc_b19_12)
node id_npc_hi_lo = cat(id_npc_hi_lo_hi, id_npc_hi_lo_lo)
node id_npc_hi_hi_lo = asUInt(id_npc_b30_20)
node id_npc_hi_hi_hi = asUInt(id_npc_sign)
node id_npc_hi_hi = cat(id_npc_hi_hi_hi, id_npc_hi_hi_lo)
node id_npc_hi = cat(id_npc_hi_hi, id_npc_hi_lo)
node _id_npc_T_1 = cat(id_npc_hi, id_npc_lo)
node _id_npc_T_2 = asSInt(_id_npc_T_1)
node _id_npc_T_3 = add(_id_npc_T, _id_npc_T_2)
node _id_npc_T_4 = tail(_id_npc_T_3, 1)
node _id_npc_T_5 = asSInt(_id_npc_T_4)
node id_npc = asUInt(_id_npc_T_5)
inst csr of CSRFile
connect csr.clock, clock
connect csr.reset, reset
node _id_csr_en_T = eq(id_ctrl.csr, UInt<3>(0h6))
node _id_csr_en_T_1 = eq(id_ctrl.csr, UInt<3>(0h7))
node _id_csr_en_T_2 = eq(id_ctrl.csr, UInt<3>(0h5))
node _id_csr_en_T_3 = or(_id_csr_en_T, _id_csr_en_T_1)
node id_csr_en = or(_id_csr_en_T_3, _id_csr_en_T_2)
node id_system_insn = eq(id_ctrl.csr, UInt<3>(0h4))
node _id_csr_ren_T = eq(id_ctrl.csr, UInt<3>(0h6))
node _id_csr_ren_T_1 = eq(id_ctrl.csr, UInt<3>(0h7))
node _id_csr_ren_T_2 = or(_id_csr_ren_T, _id_csr_ren_T_1)
node _id_csr_ren_T_3 = eq(ibuf.io.inst[0].bits.inst.rs1, UInt<1>(0h0))
node id_csr_ren = and(_id_csr_ren_T_2, _id_csr_ren_T_3)
node _id_csr_T = and(id_system_insn, id_ctrl.mem)
node _id_csr_T_1 = mux(id_csr_ren, UInt<3>(0h2), id_ctrl.csr)
node id_csr = mux(_id_csr_T, UInt<3>(0h0), _id_csr_T_1)
node _id_csr_flush_T = eq(id_csr_ren, UInt<1>(0h0))
node _id_csr_flush_T_1 = and(id_csr_en, _id_csr_flush_T)
node _id_csr_flush_T_2 = and(_id_csr_flush_T_1, csr.io.decode[0].write_flush)
node id_csr_flush = or(id_system_insn, _id_csr_flush_T_2)
node _id_set_vconfig_T = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>(0h8000707f))
node _id_set_vconfig_T_1 = eq(UInt<15>(0h7057), _id_set_vconfig_T)
node _id_set_vconfig_T_2 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>(0hc000707f))
node _id_set_vconfig_T_3 = eq(UInt<32>(0hc0007057), _id_set_vconfig_T_2)
node _id_set_vconfig_T_4 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>(0hfe00707f))
node _id_set_vconfig_T_5 = eq(UInt<32>(0h80007057), _id_set_vconfig_T_4)
node _id_set_vconfig_T_6 = or(_id_set_vconfig_T_1, _id_set_vconfig_T_3)
node _id_set_vconfig_T_7 = or(_id_set_vconfig_T_6, _id_set_vconfig_T_5)
node id_set_vconfig = and(_id_set_vconfig_T_7, UInt<1>(0h0))
connect id_ctrl.vec, UInt<1>(0h0)
node _id_illegal_insn_T = eq(id_ctrl.legal, UInt<1>(0h0))
node _id_illegal_insn_T_1 = or(id_ctrl.mul, id_ctrl.div)
node _id_illegal_insn_T_2 = bits(csr.io.status.isa, 12, 12)
node _id_illegal_insn_T_3 = eq(_id_illegal_insn_T_2, UInt<1>(0h0))
node _id_illegal_insn_T_4 = and(_id_illegal_insn_T_1, _id_illegal_insn_T_3)
node _id_illegal_insn_T_5 = or(_id_illegal_insn_T, _id_illegal_insn_T_4)
node _id_illegal_insn_T_6 = bits(csr.io.status.isa, 0, 0)
node _id_illegal_insn_T_7 = eq(_id_illegal_insn_T_6, UInt<1>(0h0))
node _id_illegal_insn_T_8 = and(id_ctrl.amo, _id_illegal_insn_T_7)
node _id_illegal_insn_T_9 = or(_id_illegal_insn_T_5, _id_illegal_insn_T_8)
node _id_illegal_insn_T_10 = eq(id_ctrl.vec, UInt<1>(0h0))
node _id_illegal_insn_T_11 = and(io.fpu.illegal_rm, _id_illegal_insn_T_10)
node _id_illegal_insn_T_12 = or(csr.io.decode[0].fp_illegal, _id_illegal_insn_T_11)
node _id_illegal_insn_T_13 = and(id_ctrl.fp, _id_illegal_insn_T_12)
node _id_illegal_insn_T_14 = or(_id_illegal_insn_T_9, _id_illegal_insn_T_13)
node _id_illegal_insn_T_15 = or(csr.io.decode[0].vector_illegal, UInt<1>(0h0))
node _id_illegal_insn_T_16 = and(id_ctrl.vec, _id_illegal_insn_T_15)
node _id_illegal_insn_T_17 = or(_id_illegal_insn_T_14, _id_illegal_insn_T_16)
node _id_illegal_insn_T_18 = bits(csr.io.status.isa, 3, 3)
node _id_illegal_insn_T_19 = eq(_id_illegal_insn_T_18, UInt<1>(0h0))
node _id_illegal_insn_T_20 = and(id_ctrl.dp, _id_illegal_insn_T_19)
node _id_illegal_insn_T_21 = or(_id_illegal_insn_T_17, _id_illegal_insn_T_20)
node _id_illegal_insn_T_22 = bits(csr.io.status.isa, 2, 2)
node _id_illegal_insn_T_23 = eq(_id_illegal_insn_T_22, UInt<1>(0h0))
node _id_illegal_insn_T_24 = and(ibuf.io.inst[0].bits.rvc, _id_illegal_insn_T_23)
node _id_illegal_insn_T_25 = or(_id_illegal_insn_T_21, _id_illegal_insn_T_24)
node _id_illegal_insn_T_26 = and(UInt<1>(0h0), id_ctrl.rxs2)
node _id_illegal_insn_T_27 = or(_id_illegal_insn_T_25, _id_illegal_insn_T_26)
node _id_illegal_insn_T_28 = and(UInt<1>(0h0), id_ctrl.rxs1)
node _id_illegal_insn_T_29 = or(_id_illegal_insn_T_27, _id_illegal_insn_T_28)
node _id_illegal_insn_T_30 = and(UInt<1>(0h0), id_ctrl.wxd)
node _id_illegal_insn_T_31 = or(_id_illegal_insn_T_29, _id_illegal_insn_T_30)
node _id_illegal_insn_T_32 = and(id_ctrl.rocc, csr.io.decode[0].rocc_illegal)
node _id_illegal_insn_T_33 = or(_id_illegal_insn_T_31, _id_illegal_insn_T_32)
node _id_illegal_insn_T_34 = eq(id_csr_ren, UInt<1>(0h0))
node _id_illegal_insn_T_35 = and(_id_illegal_insn_T_34, csr.io.decode[0].write_illegal)
node _id_illegal_insn_T_36 = or(csr.io.decode[0].read_illegal, _id_illegal_insn_T_35)
node _id_illegal_insn_T_37 = and(id_csr_en, _id_illegal_insn_T_36)
node _id_illegal_insn_T_38 = or(_id_illegal_insn_T_33, _id_illegal_insn_T_37)
node _id_illegal_insn_T_39 = eq(ibuf.io.inst[0].bits.rvc, UInt<1>(0h0))
node _id_illegal_insn_T_40 = and(id_system_insn, csr.io.decode[0].system_illegal)
node _id_illegal_insn_T_41 = and(_id_illegal_insn_T_39, _id_illegal_insn_T_40)
node id_illegal_insn = or(_id_illegal_insn_T_38, _id_illegal_insn_T_41)
node _id_virtual_insn_T = eq(id_csr_ren, UInt<1>(0h0))
node _id_virtual_insn_T_1 = and(_id_virtual_insn_T, csr.io.decode[0].write_illegal)
node _id_virtual_insn_T_2 = eq(_id_virtual_insn_T_1, UInt<1>(0h0))
node _id_virtual_insn_T_3 = and(id_csr_en, _id_virtual_insn_T_2)
node _id_virtual_insn_T_4 = and(_id_virtual_insn_T_3, csr.io.decode[0].virtual_access_illegal)
node _id_virtual_insn_T_5 = eq(ibuf.io.inst[0].bits.rvc, UInt<1>(0h0))
node _id_virtual_insn_T_6 = and(_id_virtual_insn_T_5, id_system_insn)
node _id_virtual_insn_T_7 = and(_id_virtual_insn_T_6, csr.io.decode[0].virtual_system_illegal)
node _id_virtual_insn_T_8 = or(_id_virtual_insn_T_4, _id_virtual_insn_T_7)
node id_virtual_insn = and(id_ctrl.legal, _id_virtual_insn_T_8)
node id_amo_aq = bits(ibuf.io.inst[0].bits.inst.bits, 26, 26)
node id_amo_rl = bits(ibuf.io.inst[0].bits.inst.bits, 25, 25)
node id_fence_pred = bits(ibuf.io.inst[0].bits.inst.bits, 27, 24)
node id_fence_succ = bits(ibuf.io.inst[0].bits.inst.bits, 23, 20)
node _id_fence_next_T = and(id_ctrl.amo, id_amo_aq)
node id_fence_next = or(id_ctrl.fence, _id_fence_next_T)
node _id_mem_busy_T = eq(io.dmem.ordered, UInt<1>(0h0))
node id_mem_busy = or(_id_mem_busy_T, io.dmem.req.valid)
node _T = eq(id_mem_busy, UInt<1>(0h0))
when _T :
connect id_reg_fence, UInt<1>(0h0)
node _id_rocc_busy_T = and(ex_reg_valid, ex_ctrl.rocc)
node _id_rocc_busy_T_1 = or(io.rocc.busy, _id_rocc_busy_T)
node _id_rocc_busy_T_2 = and(mem_reg_valid, mem_ctrl.rocc)
node _id_rocc_busy_T_3 = or(_id_rocc_busy_T_1, _id_rocc_busy_T_2)
node _id_rocc_busy_T_4 = and(wb_reg_valid, wb_ctrl.rocc)
node _id_rocc_busy_T_5 = or(_id_rocc_busy_T_3, _id_rocc_busy_T_4)
node id_rocc_busy = and(UInt<1>(0h0), _id_rocc_busy_T_5)
node _id_csr_rocc_write_T = and(UInt<1>(0h0), id_csr_en)
node _id_csr_rocc_write_T_1 = eq(id_csr_ren, UInt<1>(0h0))
node id_csr_rocc_write = and(_id_csr_rocc_write_T, _id_csr_rocc_write_T_1)
node _id_do_fence_T = or(id_ctrl.fence, id_csr_rocc_write)
node _id_do_fence_T_1 = and(id_rocc_busy, _id_do_fence_T)
node _id_do_fence_T_2 = and(UInt<1>(0h0), id_ctrl.fence)
node _id_do_fence_T_3 = or(_id_do_fence_T_1, _id_do_fence_T_2)
node _id_do_fence_T_4 = and(id_ctrl.amo, id_amo_rl)
node _id_do_fence_T_5 = or(_id_do_fence_T_4, id_ctrl.fence_i)
node _id_do_fence_T_6 = or(id_ctrl.mem, id_ctrl.rocc)
node _id_do_fence_T_7 = and(id_reg_fence, _id_do_fence_T_6)
node _id_do_fence_T_8 = or(_id_do_fence_T_5, _id_do_fence_T_7)
node _id_do_fence_T_9 = and(id_mem_busy, _id_do_fence_T_8)
node _id_do_fence_T_10 = or(_id_do_fence_T_3, _id_do_fence_T_9)
wire id_do_fence : UInt<1>
connect id_do_fence, _id_do_fence_T_10
inst bpu of BreakpointUnit
connect bpu.clock, clock
connect bpu.reset, reset
connect bpu.io.status.uie, csr.io.status.uie
connect bpu.io.status.sie, csr.io.status.sie
connect bpu.io.status.hie, csr.io.status.hie
connect bpu.io.status.mie, csr.io.status.mie
connect bpu.io.status.upie, csr.io.status.upie
connect bpu.io.status.spie, csr.io.status.spie
connect bpu.io.status.ube, csr.io.status.ube
connect bpu.io.status.mpie, csr.io.status.mpie
connect bpu.io.status.spp, csr.io.status.spp
connect bpu.io.status.vs, csr.io.status.vs
connect bpu.io.status.mpp, csr.io.status.mpp
connect bpu.io.status.fs, csr.io.status.fs
connect bpu.io.status.xs, csr.io.status.xs
connect bpu.io.status.mprv, csr.io.status.mprv
connect bpu.io.status.sum, csr.io.status.sum
connect bpu.io.status.mxr, csr.io.status.mxr
connect bpu.io.status.tvm, csr.io.status.tvm
connect bpu.io.status.tw, csr.io.status.tw
connect bpu.io.status.tsr, csr.io.status.tsr
connect bpu.io.status.zero1, csr.io.status.zero1
connect bpu.io.status.sd_rv32, csr.io.status.sd_rv32
connect bpu.io.status.uxl, csr.io.status.uxl
connect bpu.io.status.sxl, csr.io.status.sxl
connect bpu.io.status.sbe, csr.io.status.sbe
connect bpu.io.status.mbe, csr.io.status.mbe
connect bpu.io.status.gva, csr.io.status.gva
connect bpu.io.status.mpv, csr.io.status.mpv
connect bpu.io.status.zero2, csr.io.status.zero2
connect bpu.io.status.sd, csr.io.status.sd
connect bpu.io.status.v, csr.io.status.v
connect bpu.io.status.prv, csr.io.status.prv
connect bpu.io.status.dv, csr.io.status.dv
connect bpu.io.status.dprv, csr.io.status.dprv
connect bpu.io.status.isa, csr.io.status.isa
connect bpu.io.status.wfi, csr.io.status.wfi
connect bpu.io.status.cease, csr.io.status.cease
connect bpu.io.status.debug, csr.io.status.debug
connect bpu.io.bp[0].textra.sselect, csr.io.bp[0].textra.sselect
connect bpu.io.bp[0].textra.pad1, csr.io.bp[0].textra.pad1
connect bpu.io.bp[0].textra.svalue, csr.io.bp[0].textra.svalue
connect bpu.io.bp[0].textra.pad2, csr.io.bp[0].textra.pad2
connect bpu.io.bp[0].textra.mselect, csr.io.bp[0].textra.mselect
connect bpu.io.bp[0].textra.mvalue, csr.io.bp[0].textra.mvalue
connect bpu.io.bp[0].address, csr.io.bp[0].address
connect bpu.io.bp[0].control.r, csr.io.bp[0].control.r
connect bpu.io.bp[0].control.w, csr.io.bp[0].control.w
connect bpu.io.bp[0].control.x, csr.io.bp[0].control.x
connect bpu.io.bp[0].control.u, csr.io.bp[0].control.u
connect bpu.io.bp[0].control.s, csr.io.bp[0].control.s
connect bpu.io.bp[0].control.h, csr.io.bp[0].control.h
connect bpu.io.bp[0].control.m, csr.io.bp[0].control.m
connect bpu.io.bp[0].control.tmatch, csr.io.bp[0].control.tmatch
connect bpu.io.bp[0].control.zero, csr.io.bp[0].control.zero
connect bpu.io.bp[0].control.chain, csr.io.bp[0].control.chain
connect bpu.io.bp[0].control.action, csr.io.bp[0].control.action
connect bpu.io.bp[0].control.reserved, csr.io.bp[0].control.reserved
connect bpu.io.bp[0].control.maskmax, csr.io.bp[0].control.maskmax
connect bpu.io.bp[0].control.dmode, csr.io.bp[0].control.dmode
connect bpu.io.bp[0].control.ttype, csr.io.bp[0].control.ttype
connect bpu.io.pc, ibuf.io.pc
connect bpu.io.ea, mem_reg_wdata
connect bpu.io.mcontext, csr.io.mcontext
connect bpu.io.scontext, csr.io.scontext
node _T_1 = or(csr.io.interrupt, bpu.io.debug_if)
node _T_2 = or(_T_1, bpu.io.xcpt_if)
node _T_3 = or(_T_2, ibuf.io.inst[0].bits.xcpt0.pf.inst)
node _T_4 = or(_T_3, ibuf.io.inst[0].bits.xcpt0.gf.inst)
node _T_5 = or(_T_4, ibuf.io.inst[0].bits.xcpt0.ae.inst)
node _T_6 = or(_T_5, ibuf.io.inst[0].bits.xcpt1.pf.inst)
node _T_7 = or(_T_6, ibuf.io.inst[0].bits.xcpt1.gf.inst)
node _T_8 = or(_T_7, ibuf.io.inst[0].bits.xcpt1.ae.inst)
node _T_9 = or(_T_8, id_virtual_insn)
node _T_10 = or(_T_9, id_illegal_insn)
wire id_xcpt : UInt<1>
connect id_xcpt, _T_10
node _T_11 = mux(id_virtual_insn, UInt<5>(0h16), UInt<2>(0h2))
node _T_12 = mux(ibuf.io.inst[0].bits.xcpt1.ae.inst, UInt<1>(0h1), _T_11)
node _T_13 = mux(ibuf.io.inst[0].bits.xcpt1.gf.inst, UInt<5>(0h14), _T_12)
node _T_14 = mux(ibuf.io.inst[0].bits.xcpt1.pf.inst, UInt<4>(0hc), _T_13)
node _T_15 = mux(ibuf.io.inst[0].bits.xcpt0.ae.inst, UInt<1>(0h1), _T_14)
node _T_16 = mux(ibuf.io.inst[0].bits.xcpt0.gf.inst, UInt<5>(0h14), _T_15)
node _T_17 = mux(ibuf.io.inst[0].bits.xcpt0.pf.inst, UInt<4>(0hc), _T_16)
node _T_18 = mux(bpu.io.xcpt_if, UInt<2>(0h3), _T_17)
node _T_19 = mux(bpu.io.debug_if, UInt<4>(0he), _T_18)
node _T_20 = mux(csr.io.interrupt, csr.io.interrupt_cause, _T_19)
wire id_cause : UInt
connect id_cause, _T_20
node _T_21 = eq(id_cause, UInt<4>(0he))
node _T_22 = and(id_xcpt, _T_21)
node _T_23 = eq(id_cause, UInt<2>(0h3))
node _T_24 = and(id_xcpt, _T_23)
node _T_25 = eq(id_cause, UInt<1>(0h1))
node _T_26 = and(id_xcpt, _T_25)
node _T_27 = eq(id_cause, UInt<2>(0h2))
node _T_28 = and(id_xcpt, _T_27)
node _T_29 = eq(id_cause, UInt<4>(0hc))
node _T_30 = and(id_xcpt, _T_29)
node dcache_bypass_data = bits(io.dmem.resp.bits.data_word_bypass, 63, 0)
node _ex_waddr_T = bits(ex_reg_inst, 11, 7)
node ex_waddr = and(_ex_waddr_T, UInt<5>(0h1f))
node _mem_waddr_T = bits(mem_reg_inst, 11, 7)
node mem_waddr = and(_mem_waddr_T, UInt<5>(0h1f))
node _wb_waddr_T = bits(wb_reg_inst, 11, 7)
node wb_waddr = and(_wb_waddr_T, UInt<5>(0h1f))
node bypass_sources_1_1 = and(ex_reg_valid, ex_ctrl.wxd)
node _bypass_sources_T = and(mem_reg_valid, mem_ctrl.wxd)
node _bypass_sources_T_1 = eq(mem_ctrl.mem, UInt<1>(0h0))
node bypass_sources_2_1 = and(_bypass_sources_T, _bypass_sources_T_1)
node bypass_sources_3_1 = and(mem_reg_valid, mem_ctrl.wxd)
node _id_bypass_src_T = eq(UInt<1>(0h0), id_raddr1)
node id_bypass_src_0_0 = and(UInt<1>(0h1), _id_bypass_src_T)
node _id_bypass_src_T_1 = eq(ex_waddr, id_raddr1)
node id_bypass_src_0_1 = and(bypass_sources_1_1, _id_bypass_src_T_1)
node _id_bypass_src_T_2 = eq(mem_waddr, id_raddr1)
node id_bypass_src_0_2 = and(bypass_sources_2_1, _id_bypass_src_T_2)
node _id_bypass_src_T_3 = eq(mem_waddr, id_raddr1)
node id_bypass_src_0_3 = and(bypass_sources_3_1, _id_bypass_src_T_3)
node _id_bypass_src_T_4 = eq(UInt<1>(0h0), id_raddr2)
node id_bypass_src_1_0 = and(UInt<1>(0h1), _id_bypass_src_T_4)
node _id_bypass_src_T_5 = eq(ex_waddr, id_raddr2)
node id_bypass_src_1_1 = and(bypass_sources_1_1, _id_bypass_src_T_5)
node _id_bypass_src_T_6 = eq(mem_waddr, id_raddr2)
node id_bypass_src_1_2 = and(bypass_sources_2_1, _id_bypass_src_T_6)
node _id_bypass_src_T_7 = eq(mem_waddr, id_raddr2)
node id_bypass_src_1_3 = and(bypass_sources_3_1, _id_bypass_src_T_7)
reg ex_reg_rs_bypass : UInt<1>[2], clock
reg ex_reg_rs_lsb : UInt<2>[2], clock
reg ex_reg_rs_msb : UInt[2], clock
node _ex_rs_T = eq(ex_reg_rs_lsb[0], UInt<1>(0h1))
node _ex_rs_T_1 = mux(_ex_rs_T, mem_reg_wdata, UInt<1>(0h0))
node _ex_rs_T_2 = eq(ex_reg_rs_lsb[0], UInt<2>(0h2))
node _ex_rs_T_3 = mux(_ex_rs_T_2, wb_reg_wdata, _ex_rs_T_1)
node _ex_rs_T_4 = eq(ex_reg_rs_lsb[0], UInt<2>(0h3))
node _ex_rs_T_5 = mux(_ex_rs_T_4, dcache_bypass_data, _ex_rs_T_3)
node _ex_rs_T_6 = cat(ex_reg_rs_msb[0], ex_reg_rs_lsb[0])
node ex_rs_0 = mux(ex_reg_rs_bypass[0], _ex_rs_T_5, _ex_rs_T_6)
node _ex_rs_T_7 = eq(ex_reg_rs_lsb[1], UInt<1>(0h1))
node _ex_rs_T_8 = mux(_ex_rs_T_7, mem_reg_wdata, UInt<1>(0h0))
node _ex_rs_T_9 = eq(ex_reg_rs_lsb[1], UInt<2>(0h2))
node _ex_rs_T_10 = mux(_ex_rs_T_9, wb_reg_wdata, _ex_rs_T_8)
node _ex_rs_T_11 = eq(ex_reg_rs_lsb[1], UInt<2>(0h3))
node _ex_rs_T_12 = mux(_ex_rs_T_11, dcache_bypass_data, _ex_rs_T_10)
node _ex_rs_T_13 = cat(ex_reg_rs_msb[1], ex_reg_rs_lsb[1])
node ex_rs_1 = mux(ex_reg_rs_bypass[1], _ex_rs_T_12, _ex_rs_T_13)
node _ex_imm_sign_T = eq(ex_ctrl.sel_imm, UInt<3>(0h5))
node _ex_imm_sign_T_1 = bits(ex_reg_inst, 31, 31)
node _ex_imm_sign_T_2 = asSInt(_ex_imm_sign_T_1)
node ex_imm_sign = mux(_ex_imm_sign_T, asSInt(UInt<1>(0h0)), _ex_imm_sign_T_2)
node _ex_imm_b30_20_T = eq(ex_ctrl.sel_imm, UInt<3>(0h2))
node _ex_imm_b30_20_T_1 = bits(ex_reg_inst, 30, 20)
node _ex_imm_b30_20_T_2 = asSInt(_ex_imm_b30_20_T_1)
node ex_imm_b30_20 = mux(_ex_imm_b30_20_T, _ex_imm_b30_20_T_2, ex_imm_sign)
node _ex_imm_b19_12_T = neq(ex_ctrl.sel_imm, UInt<3>(0h2))
node _ex_imm_b19_12_T_1 = neq(ex_ctrl.sel_imm, UInt<3>(0h3))
node _ex_imm_b19_12_T_2 = and(_ex_imm_b19_12_T, _ex_imm_b19_12_T_1)
node _ex_imm_b19_12_T_3 = bits(ex_reg_inst, 19, 12)
node _ex_imm_b19_12_T_4 = asSInt(_ex_imm_b19_12_T_3)
node ex_imm_b19_12 = mux(_ex_imm_b19_12_T_2, ex_imm_sign, _ex_imm_b19_12_T_4)
node _ex_imm_b11_T = eq(ex_ctrl.sel_imm, UInt<3>(0h2))
node _ex_imm_b11_T_1 = eq(ex_ctrl.sel_imm, UInt<3>(0h5))
node _ex_imm_b11_T_2 = or(_ex_imm_b11_T, _ex_imm_b11_T_1)
node _ex_imm_b11_T_3 = eq(ex_ctrl.sel_imm, UInt<3>(0h3))
node _ex_imm_b11_T_4 = bits(ex_reg_inst, 20, 20)
node _ex_imm_b11_T_5 = asSInt(_ex_imm_b11_T_4)
node _ex_imm_b11_T_6 = eq(ex_ctrl.sel_imm, UInt<3>(0h1))
node _ex_imm_b11_T_7 = bits(ex_reg_inst, 7, 7)
node _ex_imm_b11_T_8 = asSInt(_ex_imm_b11_T_7)
node _ex_imm_b11_T_9 = mux(_ex_imm_b11_T_6, _ex_imm_b11_T_8, ex_imm_sign)
node _ex_imm_b11_T_10 = mux(_ex_imm_b11_T_3, _ex_imm_b11_T_5, _ex_imm_b11_T_9)
node ex_imm_b11 = mux(_ex_imm_b11_T_2, asSInt(UInt<1>(0h0)), _ex_imm_b11_T_10)
node _ex_imm_b10_5_T = eq(ex_ctrl.sel_imm, UInt<3>(0h2))
node _ex_imm_b10_5_T_1 = eq(ex_ctrl.sel_imm, UInt<3>(0h5))
node _ex_imm_b10_5_T_2 = or(_ex_imm_b10_5_T, _ex_imm_b10_5_T_1)
node _ex_imm_b10_5_T_3 = bits(ex_reg_inst, 30, 25)
node ex_imm_b10_5 = mux(_ex_imm_b10_5_T_2, UInt<1>(0h0), _ex_imm_b10_5_T_3)
node _ex_imm_b4_1_T = eq(ex_ctrl.sel_imm, UInt<3>(0h2))
node _ex_imm_b4_1_T_1 = eq(ex_ctrl.sel_imm, UInt<3>(0h0))
node _ex_imm_b4_1_T_2 = eq(ex_ctrl.sel_imm, UInt<3>(0h1))
node _ex_imm_b4_1_T_3 = or(_ex_imm_b4_1_T_1, _ex_imm_b4_1_T_2)
node _ex_imm_b4_1_T_4 = bits(ex_reg_inst, 11, 8)
node _ex_imm_b4_1_T_5 = eq(ex_ctrl.sel_imm, UInt<3>(0h5))
node _ex_imm_b4_1_T_6 = bits(ex_reg_inst, 19, 16)
node _ex_imm_b4_1_T_7 = bits(ex_reg_inst, 24, 21)
node _ex_imm_b4_1_T_8 = mux(_ex_imm_b4_1_T_5, _ex_imm_b4_1_T_6, _ex_imm_b4_1_T_7)
node _ex_imm_b4_1_T_9 = mux(_ex_imm_b4_1_T_3, _ex_imm_b4_1_T_4, _ex_imm_b4_1_T_8)
node ex_imm_b4_1 = mux(_ex_imm_b4_1_T, UInt<1>(0h0), _ex_imm_b4_1_T_9)
node _ex_imm_b0_T = eq(ex_ctrl.sel_imm, UInt<3>(0h0))
node _ex_imm_b0_T_1 = bits(ex_reg_inst, 7, 7)
node _ex_imm_b0_T_2 = eq(ex_ctrl.sel_imm, UInt<3>(0h4))
node _ex_imm_b0_T_3 = bits(ex_reg_inst, 20, 20)
node _ex_imm_b0_T_4 = eq(ex_ctrl.sel_imm, UInt<3>(0h5))
node _ex_imm_b0_T_5 = bits(ex_reg_inst, 15, 15)
node _ex_imm_b0_T_6 = mux(_ex_imm_b0_T_4, _ex_imm_b0_T_5, UInt<1>(0h0))
node _ex_imm_b0_T_7 = mux(_ex_imm_b0_T_2, _ex_imm_b0_T_3, _ex_imm_b0_T_6)
node ex_imm_b0 = mux(_ex_imm_b0_T, _ex_imm_b0_T_1, _ex_imm_b0_T_7)
node ex_imm_lo_hi = cat(ex_imm_b10_5, ex_imm_b4_1)
node ex_imm_lo = cat(ex_imm_lo_hi, ex_imm_b0)
node ex_imm_hi_lo_lo = asUInt(ex_imm_b11)
node ex_imm_hi_lo_hi = asUInt(ex_imm_b19_12)
node ex_imm_hi_lo = cat(ex_imm_hi_lo_hi, ex_imm_hi_lo_lo)
node ex_imm_hi_hi_lo = asUInt(ex_imm_b30_20)
node ex_imm_hi_hi_hi = asUInt(ex_imm_sign)
node ex_imm_hi_hi = cat(ex_imm_hi_hi_hi, ex_imm_hi_hi_lo)
node ex_imm_hi = cat(ex_imm_hi_hi, ex_imm_hi_lo)
node _ex_imm_T = cat(ex_imm_hi, ex_imm_lo)
node ex_imm = asSInt(_ex_imm_T)
node _ex_rs1shl_T = bits(ex_reg_inst, 3, 3)
node _ex_rs1shl_T_1 = bits(ex_rs_0, 31, 0)
node _ex_rs1shl_T_2 = mux(_ex_rs1shl_T, _ex_rs1shl_T_1, ex_rs_0)
node _ex_rs1shl_T_3 = bits(ex_reg_inst, 14, 13)
node ex_rs1shl = dshl(_ex_rs1shl_T_2, _ex_rs1shl_T_3)
node _ex_op1_T = asSInt(ex_rs_0)
node _ex_op1_T_1 = asSInt(ex_reg_pc)
node _ex_op1_T_2 = asSInt(ex_rs1shl)
node _ex_op1_T_3 = eq(UInt<2>(0h1), ex_ctrl.sel_alu1)
node _ex_op1_T_4 = mux(_ex_op1_T_3, _ex_op1_T, asSInt(UInt<1>(0h0)))
node _ex_op1_T_5 = eq(UInt<2>(0h2), ex_ctrl.sel_alu1)
node _ex_op1_T_6 = mux(_ex_op1_T_5, _ex_op1_T_1, _ex_op1_T_4)
node _ex_op1_T_7 = eq(UInt<2>(0h3), ex_ctrl.sel_alu1)
node ex_op1 = mux(_ex_op1_T_7, _ex_op1_T_2, _ex_op1_T_6)
node _ex_op2_oh_T = bits(ex_ctrl.sel_alu2, 0, 0)
node _ex_op2_oh_T_1 = shr(ex_reg_inst, 20)
node _ex_op2_oh_T_2 = mux(_ex_op2_oh_T, _ex_op2_oh_T_1, ex_rs_1)
node _ex_op2_oh_T_3 = bits(_ex_op2_oh_T_2, 5, 0)
node _ex_op2_oh_T_4 = dshl(UInt<1>(0h1), _ex_op2_oh_T_3)
node ex_op2_oh = asSInt(_ex_op2_oh_T_4)
node _ex_op2_T = asSInt(ex_rs_1)
node _ex_op2_T_1 = mux(ex_reg_rvc, asSInt(UInt<3>(0h2)), asSInt(UInt<4>(0h4)))
node _ex_op2_T_2 = eq(UInt<3>(0h2), ex_ctrl.sel_alu2)
node _ex_op2_T_3 = mux(_ex_op2_T_2, _ex_op2_T, asSInt(UInt<1>(0h0)))
node _ex_op2_T_4 = eq(UInt<3>(0h3), ex_ctrl.sel_alu2)
node _ex_op2_T_5 = mux(_ex_op2_T_4, ex_imm, _ex_op2_T_3)
node _ex_op2_T_6 = eq(UInt<3>(0h1), ex_ctrl.sel_alu2)
node _ex_op2_T_7 = mux(_ex_op2_T_6, _ex_op2_T_1, _ex_op2_T_5)
node _ex_op2_T_8 = eq(UInt<3>(0h4), ex_ctrl.sel_alu2)
node _ex_op2_T_9 = mux(_ex_op2_T_8, ex_op2_oh, _ex_op2_T_7)
node _ex_op2_T_10 = eq(UInt<3>(0h5), ex_ctrl.sel_alu2)
node ex_op2 = mux(_ex_op2_T_10, ex_op2_oh, _ex_op2_T_9)
inst alu of ALU
connect alu.clock, clock
connect alu.reset, reset
connect alu.io.dw, ex_ctrl.alu_dw
connect alu.io.fn, ex_ctrl.alu_fn
node _alu_io_in2_T = asUInt(ex_op2)
connect alu.io.in2, _alu_io_in2_T
node _alu_io_in1_T = asUInt(ex_op1)
connect alu.io.in1, _alu_io_in1_T
inst div of MulDiv
connect div.clock, clock
connect div.reset, reset
node _div_io_req_valid_T = and(ex_reg_valid, ex_ctrl.div)
connect div.io.req.valid, _div_io_req_valid_T
connect div.io.req.bits.dw, ex_ctrl.alu_dw
connect div.io.req.bits.fn, ex_ctrl.alu_fn
connect div.io.req.bits.in1, ex_rs_0
connect div.io.req.bits.in2, ex_rs_1
connect div.io.req.bits.tag, ex_waddr
node _ex_reg_valid_T = eq(ctrl_killd, UInt<1>(0h0))
connect ex_reg_valid, _ex_reg_valid_T
node _ex_reg_replay_T = eq(take_pc_mem_wb, UInt<1>(0h0))
node _ex_reg_replay_T_1 = and(_ex_reg_replay_T, ibuf.io.inst[0].valid)
node _ex_reg_replay_T_2 = and(_ex_reg_replay_T_1, ibuf.io.inst[0].bits.replay)
connect ex_reg_replay, _ex_reg_replay_T_2
node _ex_reg_xcpt_T = eq(ctrl_killd, UInt<1>(0h0))
node _ex_reg_xcpt_T_1 = and(_ex_reg_xcpt_T, id_xcpt)
connect ex_reg_xcpt, _ex_reg_xcpt_T_1
node _ex_reg_xcpt_interrupt_T = eq(take_pc_mem_wb, UInt<1>(0h0))
node _ex_reg_xcpt_interrupt_T_1 = and(_ex_reg_xcpt_interrupt_T, ibuf.io.inst[0].valid)
node _ex_reg_xcpt_interrupt_T_2 = and(_ex_reg_xcpt_interrupt_T_1, csr.io.interrupt)
connect ex_reg_xcpt_interrupt, _ex_reg_xcpt_interrupt_T_2
node _T_31 = eq(ctrl_killd, UInt<1>(0h0))
when _T_31 :
connect ex_ctrl, id_ctrl
connect ex_reg_rvc, ibuf.io.inst[0].bits.rvc
connect ex_ctrl.csr, id_csr
node _T_32 = eq(id_fence_succ, UInt<1>(0h0))
node _T_33 = and(id_ctrl.fence, _T_32)
when _T_33 :
connect id_reg_pause, UInt<1>(0h1)
when id_fence_next :
connect id_reg_fence, UInt<1>(0h1)
when id_xcpt :
connect ex_ctrl.alu_fn, UInt<1>(0h0)
connect ex_ctrl.alu_dw, UInt<1>(0h1)
connect ex_ctrl.sel_alu1, UInt<2>(0h1)
connect ex_ctrl.sel_alu2, UInt<3>(0h0)
node hi = cat(ibuf.io.inst[0].bits.xcpt1.pf.inst, ibuf.io.inst[0].bits.xcpt1.gf.inst)
node _T_34 = cat(hi, ibuf.io.inst[0].bits.xcpt1.ae.inst)
node _T_35 = orr(_T_34)
when _T_35 :
connect ex_ctrl.sel_alu1, UInt<2>(0h2)
connect ex_ctrl.sel_alu2, UInt<3>(0h1)
connect ex_reg_rvc, UInt<1>(0h1)
node hi_1 = cat(ibuf.io.inst[0].bits.xcpt0.pf.inst, ibuf.io.inst[0].bits.xcpt0.gf.inst)
node _T_36 = cat(hi_1, ibuf.io.inst[0].bits.xcpt0.ae.inst)
node _T_37 = orr(_T_36)
node _T_38 = or(bpu.io.xcpt_if, _T_37)
when _T_38 :
connect ex_ctrl.sel_alu1, UInt<2>(0h2)
connect ex_ctrl.sel_alu2, UInt<3>(0h0)
node _ex_reg_flush_pipe_T = or(id_ctrl.fence_i, id_csr_flush)
connect ex_reg_flush_pipe, _ex_reg_flush_pipe_T
connect ex_reg_load_use, id_load_use
node _ex_reg_hls_T = and(UInt<1>(0h0), id_system_insn)
node _ex_reg_hls_T_1 = eq(id_ctrl.mem_cmd, UInt<1>(0h0))
node _ex_reg_hls_T_2 = eq(id_ctrl.mem_cmd, UInt<1>(0h1))
node _ex_reg_hls_T_3 = eq(id_ctrl.mem_cmd, UInt<5>(0h10))
node _ex_reg_hls_T_4 = or(_ex_reg_hls_T_1, _ex_reg_hls_T_2)
node _ex_reg_hls_T_5 = or(_ex_reg_hls_T_4, _ex_reg_hls_T_3)
node _ex_reg_hls_T_6 = and(_ex_reg_hls_T, _ex_reg_hls_T_5)
connect ex_reg_hls, _ex_reg_hls_T_6
node _ex_reg_mem_size_T = and(UInt<1>(0h0), id_system_insn)
node _ex_reg_mem_size_T_1 = bits(ibuf.io.inst[0].bits.inst.bits, 27, 26)
node _ex_reg_mem_size_T_2 = bits(ibuf.io.inst[0].bits.inst.bits, 13, 12)
node _ex_reg_mem_size_T_3 = mux(_ex_reg_mem_size_T, _ex_reg_mem_size_T_1, _ex_reg_mem_size_T_2)
connect ex_reg_mem_size, _ex_reg_mem_size_T_3
node _T_39 = eq(id_ctrl.mem_cmd, UInt<5>(0h14))
node _T_40 = eq(id_ctrl.mem_cmd, UInt<5>(0h15))
node _T_41 = eq(id_ctrl.mem_cmd, UInt<5>(0h16))
node _T_42 = eq(id_ctrl.mem_cmd, UInt<3>(0h5))
node _T_43 = or(_T_39, _T_40)
node _T_44 = or(_T_43, _T_41)
node _T_45 = or(_T_44, _T_42)
when _T_45 :
node _ex_reg_mem_size_T_4 = neq(id_raddr2, UInt<1>(0h0))
node _ex_reg_mem_size_T_5 = neq(id_raddr1, UInt<1>(0h0))
node _ex_reg_mem_size_T_6 = cat(_ex_reg_mem_size_T_4, _ex_reg_mem_size_T_5)
connect ex_reg_mem_size, _ex_reg_mem_size_T_6
node _T_46 = eq(id_ctrl.mem_cmd, UInt<5>(0h14))
node _T_47 = and(_T_46, csr.io.status.v)
when _T_47 :
connect ex_ctrl.mem_cmd, UInt<5>(0h15)
node _do_bypass_T = or(id_bypass_src_0_0, id_bypass_src_0_1)
node _do_bypass_T_1 = or(_do_bypass_T, id_bypass_src_0_2)
node do_bypass = or(_do_bypass_T_1, id_bypass_src_0_3)
node _bypass_src_T = mux(id_bypass_src_0_2, UInt<2>(0h2), UInt<2>(0h3))
node _bypass_src_T_1 = mux(id_bypass_src_0_1, UInt<1>(0h1), _bypass_src_T)
node bypass_src = mux(id_bypass_src_0_0, UInt<1>(0h0), _bypass_src_T_1)
connect ex_reg_rs_bypass[0], do_bypass
connect ex_reg_rs_lsb[0], bypass_src
node _T_48 = eq(do_bypass, UInt<1>(0h0))
node _T_49 = and(id_ctrl.rxs1, _T_48)
when _T_49 :
node _ex_reg_rs_lsb_0_T = bits(id_rs_0, 1, 0)
connect ex_reg_rs_lsb[0], _ex_reg_rs_lsb_0_T
node _ex_reg_rs_msb_0_T = shr(id_rs_0, 2)
connect ex_reg_rs_msb[0], _ex_reg_rs_msb_0_T
node _do_bypass_T_2 = or(id_bypass_src_1_0, id_bypass_src_1_1)
node _do_bypass_T_3 = or(_do_bypass_T_2, id_bypass_src_1_2)
node do_bypass_1 = or(_do_bypass_T_3, id_bypass_src_1_3)
node _bypass_src_T_2 = mux(id_bypass_src_1_2, UInt<2>(0h2), UInt<2>(0h3))
node _bypass_src_T_3 = mux(id_bypass_src_1_1, UInt<1>(0h1), _bypass_src_T_2)
node bypass_src_1 = mux(id_bypass_src_1_0, UInt<1>(0h0), _bypass_src_T_3)
connect ex_reg_rs_bypass[1], do_bypass_1
connect ex_reg_rs_lsb[1], bypass_src_1
node _T_50 = eq(do_bypass_1, UInt<1>(0h0))
node _T_51 = and(id_ctrl.rxs2, _T_50)
when _T_51 :
node _ex_reg_rs_lsb_1_T = bits(id_rs_1, 1, 0)
connect ex_reg_rs_lsb[1], _ex_reg_rs_lsb_1_T
node _ex_reg_rs_msb_1_T = shr(id_rs_1, 2)
connect ex_reg_rs_msb[1], _ex_reg_rs_msb_1_T
node _T_52 = or(id_illegal_insn, id_virtual_insn)
when _T_52 :
node _inst_T = bits(ibuf.io.inst[0].bits.raw, 15, 0)
node inst = mux(ibuf.io.inst[0].bits.rvc, _inst_T, ibuf.io.inst[0].bits.raw)
connect ex_reg_rs_bypass[0], UInt<1>(0h0)
node _ex_reg_rs_lsb_0_T_1 = bits(inst, 1, 0)
connect ex_reg_rs_lsb[0], _ex_reg_rs_lsb_0_T_1
node _ex_reg_rs_msb_0_T_1 = shr(inst, 2)
connect ex_reg_rs_msb[0], _ex_reg_rs_msb_0_T_1
node _T_53 = eq(ctrl_killd, UInt<1>(0h0))
node _T_54 = or(_T_53, csr.io.interrupt)
node _T_55 = or(_T_54, ibuf.io.inst[0].bits.replay)
when _T_55 :
connect ex_reg_cause, id_cause
connect ex_reg_inst, ibuf.io.inst[0].bits.inst.bits
connect ex_reg_raw_inst, ibuf.io.inst[0].bits.raw
connect ex_reg_pc, ibuf.io.pc
connect ex_reg_btb_resp, ibuf.io.btb_resp
connect ex_reg_wphit[0], bpu.io.bpwatch[0].ivalid[0]
node _ex_reg_set_vconfig_T = eq(id_xcpt, UInt<1>(0h0))
node _ex_reg_set_vconfig_T_1 = and(id_set_vconfig, _ex_reg_set_vconfig_T)
connect ex_reg_set_vconfig, _ex_reg_set_vconfig_T_1
node _ex_pc_valid_T = or(ex_reg_valid, ex_reg_replay)
node ex_pc_valid = or(_ex_pc_valid_T, ex_reg_xcpt_interrupt)
node _wb_dcache_miss_T = eq(io.dmem.resp.valid, UInt<1>(0h0))
node wb_dcache_miss = and(wb_ctrl.mem, _wb_dcache_miss_T)
node _replay_ex_structural_T = eq(io.dmem.req.ready, UInt<1>(0h0))
node _replay_ex_structural_T_1 = and(ex_ctrl.mem, _replay_ex_structural_T)
node _replay_ex_structural_T_2 = eq(div.io.req.ready, UInt<1>(0h0))
node _replay_ex_structural_T_3 = and(ex_ctrl.div, _replay_ex_structural_T_2)
node _replay_ex_structural_T_4 = or(_replay_ex_structural_T_1, _replay_ex_structural_T_3)
node _replay_ex_structural_T_5 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _replay_ex_structural_T_6 = and(ex_ctrl.vec, _replay_ex_structural_T_5)
node replay_ex_structural = or(_replay_ex_structural_T_4, _replay_ex_structural_T_6)
node replay_ex_load_use = and(wb_dcache_miss, ex_reg_load_use)
node _replay_ex_T = or(replay_ex_structural, replay_ex_load_use)
node _replay_ex_T_1 = and(ex_reg_valid, _replay_ex_T)
node replay_ex = or(ex_reg_replay, _replay_ex_T_1)
node _ctrl_killx_T = or(take_pc_mem_wb, replay_ex)
node _ctrl_killx_T_1 = eq(ex_reg_valid, UInt<1>(0h0))
node ctrl_killx = or(_ctrl_killx_T, _ctrl_killx_T_1)
node _ex_slow_bypass_T = eq(ex_ctrl.mem_cmd, UInt<3>(0h7))
node _ex_slow_bypass_T_1 = lt(ex_reg_mem_size, UInt<2>(0h2))
node ex_slow_bypass = or(_ex_slow_bypass_T, _ex_slow_bypass_T_1)
node _ex_sfence_T = and(UInt<1>(0h1), ex_ctrl.mem)
node _ex_sfence_T_1 = eq(ex_ctrl.mem_cmd, UInt<5>(0h14))
node _ex_sfence_T_2 = eq(ex_ctrl.mem_cmd, UInt<5>(0h15))
node _ex_sfence_T_3 = or(_ex_sfence_T_1, _ex_sfence_T_2)
node _ex_sfence_T_4 = eq(ex_ctrl.mem_cmd, UInt<5>(0h16))
node _ex_sfence_T_5 = or(_ex_sfence_T_3, _ex_sfence_T_4)
node ex_sfence = and(_ex_sfence_T, _ex_sfence_T_5)
node _T_56 = or(ex_reg_xcpt_interrupt, ex_reg_xcpt)
wire ex_xcpt : UInt<1>
connect ex_xcpt, _T_56
wire ex_cause : UInt
connect ex_cause, ex_reg_cause
node _T_57 = eq(ex_cause, UInt<4>(0he))
node _T_58 = and(ex_xcpt, _T_57)
node _T_59 = eq(ex_cause, UInt<2>(0h3))
node _T_60 = and(ex_xcpt, _T_59)
node _T_61 = eq(ex_cause, UInt<1>(0h1))
node _T_62 = and(ex_xcpt, _T_61)
node _T_63 = eq(ex_cause, UInt<2>(0h2))
node _T_64 = and(ex_xcpt, _T_63)
node _T_65 = eq(ex_cause, UInt<4>(0hc))
node _T_66 = and(ex_xcpt, _T_65)
node _mem_pc_valid_T = or(mem_reg_valid, mem_reg_replay)
node mem_pc_valid = or(_mem_pc_valid_T, mem_reg_xcpt_interrupt)
node _mem_br_target_T = asSInt(mem_reg_pc)
node _mem_br_target_T_1 = and(mem_ctrl.branch, mem_br_taken)
node _mem_br_target_sign_T = eq(UInt<3>(0h1), UInt<3>(0h5))
node _mem_br_target_sign_T_1 = bits(mem_reg_inst, 31, 31)
node _mem_br_target_sign_T_2 = asSInt(_mem_br_target_sign_T_1)
node mem_br_target_sign = mux(_mem_br_target_sign_T, asSInt(UInt<1>(0h0)), _mem_br_target_sign_T_2)
node _mem_br_target_b30_20_T = eq(UInt<3>(0h1), UInt<3>(0h2))
node _mem_br_target_b30_20_T_1 = bits(mem_reg_inst, 30, 20)
node _mem_br_target_b30_20_T_2 = asSInt(_mem_br_target_b30_20_T_1)
node mem_br_target_b30_20 = mux(_mem_br_target_b30_20_T, _mem_br_target_b30_20_T_2, mem_br_target_sign)
node _mem_br_target_b19_12_T = neq(UInt<3>(0h1), UInt<3>(0h2))
node _mem_br_target_b19_12_T_1 = neq(UInt<3>(0h1), UInt<3>(0h3))
node _mem_br_target_b19_12_T_2 = and(_mem_br_target_b19_12_T, _mem_br_target_b19_12_T_1)
node _mem_br_target_b19_12_T_3 = bits(mem_reg_inst, 19, 12)
node _mem_br_target_b19_12_T_4 = asSInt(_mem_br_target_b19_12_T_3)
node mem_br_target_b19_12 = mux(_mem_br_target_b19_12_T_2, mem_br_target_sign, _mem_br_target_b19_12_T_4)
node _mem_br_target_b11_T = eq(UInt<3>(0h1), UInt<3>(0h2))
node _mem_br_target_b11_T_1 = eq(UInt<3>(0h1), UInt<3>(0h5))
node _mem_br_target_b11_T_2 = or(_mem_br_target_b11_T, _mem_br_target_b11_T_1)
node _mem_br_target_b11_T_3 = eq(UInt<3>(0h1), UInt<3>(0h3))
node _mem_br_target_b11_T_4 = bits(mem_reg_inst, 20, 20)
node _mem_br_target_b11_T_5 = asSInt(_mem_br_target_b11_T_4)
node _mem_br_target_b11_T_6 = eq(UInt<3>(0h1), UInt<3>(0h1))
node _mem_br_target_b11_T_7 = bits(mem_reg_inst, 7, 7)
node _mem_br_target_b11_T_8 = asSInt(_mem_br_target_b11_T_7)
node _mem_br_target_b11_T_9 = mux(_mem_br_target_b11_T_6, _mem_br_target_b11_T_8, mem_br_target_sign)
node _mem_br_target_b11_T_10 = mux(_mem_br_target_b11_T_3, _mem_br_target_b11_T_5, _mem_br_target_b11_T_9)
node mem_br_target_b11 = mux(_mem_br_target_b11_T_2, asSInt(UInt<1>(0h0)), _mem_br_target_b11_T_10)
node _mem_br_target_b10_5_T = eq(UInt<3>(0h1), UInt<3>(0h2))
node _mem_br_target_b10_5_T_1 = eq(UInt<3>(0h1), UInt<3>(0h5))
node _mem_br_target_b10_5_T_2 = or(_mem_br_target_b10_5_T, _mem_br_target_b10_5_T_1)
node _mem_br_target_b10_5_T_3 = bits(mem_reg_inst, 30, 25)
node mem_br_target_b10_5 = mux(_mem_br_target_b10_5_T_2, UInt<1>(0h0), _mem_br_target_b10_5_T_3)
node _mem_br_target_b4_1_T = eq(UInt<3>(0h1), UInt<3>(0h2))
node _mem_br_target_b4_1_T_1 = eq(UInt<3>(0h1), UInt<3>(0h0))
node _mem_br_target_b4_1_T_2 = eq(UInt<3>(0h1), UInt<3>(0h1))
node _mem_br_target_b4_1_T_3 = or(_mem_br_target_b4_1_T_1, _mem_br_target_b4_1_T_2)
node _mem_br_target_b4_1_T_4 = bits(mem_reg_inst, 11, 8)
node _mem_br_target_b4_1_T_5 = eq(UInt<3>(0h1), UInt<3>(0h5))
node _mem_br_target_b4_1_T_6 = bits(mem_reg_inst, 19, 16)
node _mem_br_target_b4_1_T_7 = bits(mem_reg_inst, 24, 21)
node _mem_br_target_b4_1_T_8 = mux(_mem_br_target_b4_1_T_5, _mem_br_target_b4_1_T_6, _mem_br_target_b4_1_T_7)
node _mem_br_target_b4_1_T_9 = mux(_mem_br_target_b4_1_T_3, _mem_br_target_b4_1_T_4, _mem_br_target_b4_1_T_8)
node mem_br_target_b4_1 = mux(_mem_br_target_b4_1_T, UInt<1>(0h0), _mem_br_target_b4_1_T_9)
node _mem_br_target_b0_T = eq(UInt<3>(0h1), UInt<3>(0h0))
node _mem_br_target_b0_T_1 = bits(mem_reg_inst, 7, 7)
node _mem_br_target_b0_T_2 = eq(UInt<3>(0h1), UInt<3>(0h4))
node _mem_br_target_b0_T_3 = bits(mem_reg_inst, 20, 20)
node _mem_br_target_b0_T_4 = eq(UInt<3>(0h1), UInt<3>(0h5))
node _mem_br_target_b0_T_5 = bits(mem_reg_inst, 15, 15)
node _mem_br_target_b0_T_6 = mux(_mem_br_target_b0_T_4, _mem_br_target_b0_T_5, UInt<1>(0h0))
node _mem_br_target_b0_T_7 = mux(_mem_br_target_b0_T_2, _mem_br_target_b0_T_3, _mem_br_target_b0_T_6)
node mem_br_target_b0 = mux(_mem_br_target_b0_T, _mem_br_target_b0_T_1, _mem_br_target_b0_T_7)
node mem_br_target_lo_hi = cat(mem_br_target_b10_5, mem_br_target_b4_1)
node mem_br_target_lo = cat(mem_br_target_lo_hi, mem_br_target_b0)
node mem_br_target_hi_lo_lo = asUInt(mem_br_target_b11)
node mem_br_target_hi_lo_hi = asUInt(mem_br_target_b19_12)
node mem_br_target_hi_lo = cat(mem_br_target_hi_lo_hi, mem_br_target_hi_lo_lo)
node mem_br_target_hi_hi_lo = asUInt(mem_br_target_b30_20)
node mem_br_target_hi_hi_hi = asUInt(mem_br_target_sign)
node mem_br_target_hi_hi = cat(mem_br_target_hi_hi_hi, mem_br_target_hi_hi_lo)
node mem_br_target_hi = cat(mem_br_target_hi_hi, mem_br_target_hi_lo)
node _mem_br_target_T_2 = cat(mem_br_target_hi, mem_br_target_lo)
node _mem_br_target_T_3 = asSInt(_mem_br_target_T_2)
node _mem_br_target_sign_T_3 = eq(UInt<3>(0h3), UInt<3>(0h5))
node _mem_br_target_sign_T_4 = bits(mem_reg_inst, 31, 31)
node _mem_br_target_sign_T_5 = asSInt(_mem_br_target_sign_T_4)
node mem_br_target_sign_1 = mux(_mem_br_target_sign_T_3, asSInt(UInt<1>(0h0)), _mem_br_target_sign_T_5)
node _mem_br_target_b30_20_T_3 = eq(UInt<3>(0h3), UInt<3>(0h2))
node _mem_br_target_b30_20_T_4 = bits(mem_reg_inst, 30, 20)
node _mem_br_target_b30_20_T_5 = asSInt(_mem_br_target_b30_20_T_4)
node mem_br_target_b30_20_1 = mux(_mem_br_target_b30_20_T_3, _mem_br_target_b30_20_T_5, mem_br_target_sign_1)
node _mem_br_target_b19_12_T_5 = neq(UInt<3>(0h3), UInt<3>(0h2))
node _mem_br_target_b19_12_T_6 = neq(UInt<3>(0h3), UInt<3>(0h3))
node _mem_br_target_b19_12_T_7 = and(_mem_br_target_b19_12_T_5, _mem_br_target_b19_12_T_6)
node _mem_br_target_b19_12_T_8 = bits(mem_reg_inst, 19, 12)
node _mem_br_target_b19_12_T_9 = asSInt(_mem_br_target_b19_12_T_8)
node mem_br_target_b19_12_1 = mux(_mem_br_target_b19_12_T_7, mem_br_target_sign_1, _mem_br_target_b19_12_T_9)
node _mem_br_target_b11_T_11 = eq(UInt<3>(0h3), UInt<3>(0h2))
node _mem_br_target_b11_T_12 = eq(UInt<3>(0h3), UInt<3>(0h5))
node _mem_br_target_b11_T_13 = or(_mem_br_target_b11_T_11, _mem_br_target_b11_T_12)
node _mem_br_target_b11_T_14 = eq(UInt<3>(0h3), UInt<3>(0h3))
node _mem_br_target_b11_T_15 = bits(mem_reg_inst, 20, 20)
node _mem_br_target_b11_T_16 = asSInt(_mem_br_target_b11_T_15)
node _mem_br_target_b11_T_17 = eq(UInt<3>(0h3), UInt<3>(0h1))
node _mem_br_target_b11_T_18 = bits(mem_reg_inst, 7, 7)
node _mem_br_target_b11_T_19 = asSInt(_mem_br_target_b11_T_18)
node _mem_br_target_b11_T_20 = mux(_mem_br_target_b11_T_17, _mem_br_target_b11_T_19, mem_br_target_sign_1)
node _mem_br_target_b11_T_21 = mux(_mem_br_target_b11_T_14, _mem_br_target_b11_T_16, _mem_br_target_b11_T_20)
node mem_br_target_b11_1 = mux(_mem_br_target_b11_T_13, asSInt(UInt<1>(0h0)), _mem_br_target_b11_T_21)
node _mem_br_target_b10_5_T_4 = eq(UInt<3>(0h3), UInt<3>(0h2))
node _mem_br_target_b10_5_T_5 = eq(UInt<3>(0h3), UInt<3>(0h5))
node _mem_br_target_b10_5_T_6 = or(_mem_br_target_b10_5_T_4, _mem_br_target_b10_5_T_5)
node _mem_br_target_b10_5_T_7 = bits(mem_reg_inst, 30, 25)
node mem_br_target_b10_5_1 = mux(_mem_br_target_b10_5_T_6, UInt<1>(0h0), _mem_br_target_b10_5_T_7)
node _mem_br_target_b4_1_T_10 = eq(UInt<3>(0h3), UInt<3>(0h2))
node _mem_br_target_b4_1_T_11 = eq(UInt<3>(0h3), UInt<3>(0h0))
node _mem_br_target_b4_1_T_12 = eq(UInt<3>(0h3), UInt<3>(0h1))
node _mem_br_target_b4_1_T_13 = or(_mem_br_target_b4_1_T_11, _mem_br_target_b4_1_T_12)
node _mem_br_target_b4_1_T_14 = bits(mem_reg_inst, 11, 8)
node _mem_br_target_b4_1_T_15 = eq(UInt<3>(0h3), UInt<3>(0h5))
node _mem_br_target_b4_1_T_16 = bits(mem_reg_inst, 19, 16)
node _mem_br_target_b4_1_T_17 = bits(mem_reg_inst, 24, 21)
node _mem_br_target_b4_1_T_18 = mux(_mem_br_target_b4_1_T_15, _mem_br_target_b4_1_T_16, _mem_br_target_b4_1_T_17)
node _mem_br_target_b4_1_T_19 = mux(_mem_br_target_b4_1_T_13, _mem_br_target_b4_1_T_14, _mem_br_target_b4_1_T_18)
node mem_br_target_b4_1_1 = mux(_mem_br_target_b4_1_T_10, UInt<1>(0h0), _mem_br_target_b4_1_T_19)
node _mem_br_target_b0_T_8 = eq(UInt<3>(0h3), UInt<3>(0h0))
node _mem_br_target_b0_T_9 = bits(mem_reg_inst, 7, 7)
node _mem_br_target_b0_T_10 = eq(UInt<3>(0h3), UInt<3>(0h4))
node _mem_br_target_b0_T_11 = bits(mem_reg_inst, 20, 20)
node _mem_br_target_b0_T_12 = eq(UInt<3>(0h3), UInt<3>(0h5))
node _mem_br_target_b0_T_13 = bits(mem_reg_inst, 15, 15)
node _mem_br_target_b0_T_14 = mux(_mem_br_target_b0_T_12, _mem_br_target_b0_T_13, UInt<1>(0h0))
node _mem_br_target_b0_T_15 = mux(_mem_br_target_b0_T_10, _mem_br_target_b0_T_11, _mem_br_target_b0_T_14)
node mem_br_target_b0_1 = mux(_mem_br_target_b0_T_8, _mem_br_target_b0_T_9, _mem_br_target_b0_T_15)
node mem_br_target_lo_hi_1 = cat(mem_br_target_b10_5_1, mem_br_target_b4_1_1)
node mem_br_target_lo_1 = cat(mem_br_target_lo_hi_1, mem_br_target_b0_1)
node mem_br_target_hi_lo_lo_1 = asUInt(mem_br_target_b11_1)
node mem_br_target_hi_lo_hi_1 = asUInt(mem_br_target_b19_12_1)
node mem_br_target_hi_lo_1 = cat(mem_br_target_hi_lo_hi_1, mem_br_target_hi_lo_lo_1)
node mem_br_target_hi_hi_lo_1 = asUInt(mem_br_target_b30_20_1)
node mem_br_target_hi_hi_hi_1 = asUInt(mem_br_target_sign_1)
node mem_br_target_hi_hi_1 = cat(mem_br_target_hi_hi_hi_1, mem_br_target_hi_hi_lo_1)
node mem_br_target_hi_1 = cat(mem_br_target_hi_hi_1, mem_br_target_hi_lo_1)
node _mem_br_target_T_4 = cat(mem_br_target_hi_1, mem_br_target_lo_1)
node _mem_br_target_T_5 = asSInt(_mem_br_target_T_4)
node _mem_br_target_T_6 = mux(mem_reg_rvc, asSInt(UInt<3>(0h2)), asSInt(UInt<4>(0h4)))
node _mem_br_target_T_7 = mux(mem_ctrl.jal, _mem_br_target_T_5, _mem_br_target_T_6)
node _mem_br_target_T_8 = mux(_mem_br_target_T_1, _mem_br_target_T_3, _mem_br_target_T_7)
node _mem_br_target_T_9 = add(_mem_br_target_T, _mem_br_target_T_8)
node _mem_br_target_T_10 = tail(_mem_br_target_T_9, 1)
node mem_br_target = asSInt(_mem_br_target_T_10)
node _mem_npc_T = or(mem_ctrl.jalr, mem_reg_sfence)
node _mem_npc_a_T = shr(mem_reg_wdata, 39)
node mem_npc_a = asSInt(_mem_npc_a_T)
node _mem_npc_msb_T = eq(mem_npc_a, asSInt(UInt<1>(0h0)))
node _mem_npc_msb_T_1 = eq(mem_npc_a, asSInt(UInt<1>(0h1)))
node _mem_npc_msb_T_2 = or(_mem_npc_msb_T, _mem_npc_msb_T_1)
node _mem_npc_msb_T_3 = bits(mem_reg_wdata, 39, 39)
node _mem_npc_msb_T_4 = bits(mem_reg_wdata, 38, 38)
node _mem_npc_msb_T_5 = eq(_mem_npc_msb_T_4, UInt<1>(0h0))
node mem_npc_msb = mux(_mem_npc_msb_T_2, _mem_npc_msb_T_3, _mem_npc_msb_T_5)
node _mem_npc_T_1 = bits(mem_reg_wdata, 38, 0)
node _mem_npc_T_2 = cat(mem_npc_msb, _mem_npc_T_1)
node _mem_npc_T_3 = asSInt(_mem_npc_T_2)
node _mem_npc_T_4 = mux(_mem_npc_T, _mem_npc_T_3, mem_br_target)
node _mem_npc_T_5 = and(_mem_npc_T_4, asSInt(UInt<2>(0h2)))
node _mem_npc_T_6 = asSInt(_mem_npc_T_5)
node mem_npc = asUInt(_mem_npc_T_6)
node _mem_wrong_npc_T = neq(mem_npc, ex_reg_pc)
node _mem_wrong_npc_T_1 = or(ibuf.io.inst[0].valid, ibuf.io.imem.valid)
node _mem_wrong_npc_T_2 = neq(mem_npc, ibuf.io.pc)
node _mem_wrong_npc_T_3 = mux(_mem_wrong_npc_T_1, _mem_wrong_npc_T_2, UInt<1>(0h1))
node mem_wrong_npc = mux(ex_pc_valid, _mem_wrong_npc_T, _mem_wrong_npc_T_3)
node _mem_npc_misaligned_T = bits(csr.io.status.isa, 2, 2)
node _mem_npc_misaligned_T_1 = eq(_mem_npc_misaligned_T, UInt<1>(0h0))
node _mem_npc_misaligned_T_2 = bits(mem_npc, 1, 1)
node _mem_npc_misaligned_T_3 = and(_mem_npc_misaligned_T_1, _mem_npc_misaligned_T_2)
node _mem_npc_misaligned_T_4 = eq(mem_reg_sfence, UInt<1>(0h0))
node mem_npc_misaligned = and(_mem_npc_misaligned_T_3, _mem_npc_misaligned_T_4)
node _mem_int_wdata_T = eq(mem_reg_xcpt, UInt<1>(0h0))
node _mem_int_wdata_T_1 = xor(mem_ctrl.jalr, mem_npc_misaligned)
node _mem_int_wdata_T_2 = and(_mem_int_wdata_T, _mem_int_wdata_T_1)
node _mem_int_wdata_T_3 = asSInt(mem_reg_wdata)
node _mem_int_wdata_T_4 = mux(_mem_int_wdata_T_2, mem_br_target, _mem_int_wdata_T_3)
node mem_int_wdata = asUInt(_mem_int_wdata_T_4)
node _mem_cfi_T = or(mem_ctrl.branch, mem_ctrl.jalr)
node mem_cfi = or(_mem_cfi_T, mem_ctrl.jal)
node _mem_cfi_taken_T = and(mem_ctrl.branch, mem_br_taken)
node _mem_cfi_taken_T_1 = or(_mem_cfi_taken_T, mem_ctrl.jalr)
node mem_cfi_taken = or(_mem_cfi_taken_T_1, mem_ctrl.jal)
node _mem_direction_misprediction_T = and(UInt<1>(0h1), mem_reg_btb_resp.taken)
node _mem_direction_misprediction_T_1 = neq(mem_br_taken, _mem_direction_misprediction_T)
node mem_direction_misprediction = and(mem_ctrl.branch, _mem_direction_misprediction_T_1)
node _take_pc_mem_T = eq(mem_reg_xcpt, UInt<1>(0h0))
node _take_pc_mem_T_1 = and(mem_reg_valid, _take_pc_mem_T)
node _take_pc_mem_T_2 = or(mem_wrong_npc, mem_reg_sfence)
node _take_pc_mem_T_3 = and(_take_pc_mem_T_1, _take_pc_mem_T_2)
connect take_pc_mem, _take_pc_mem_T_3
node _mem_reg_valid_T = eq(ctrl_killx, UInt<1>(0h0))
connect mem_reg_valid, _mem_reg_valid_T
node _mem_reg_replay_T = eq(take_pc_mem_wb, UInt<1>(0h0))
node _mem_reg_replay_T_1 = and(_mem_reg_replay_T, replay_ex)
connect mem_reg_replay, _mem_reg_replay_T_1
node _mem_reg_xcpt_T = eq(ctrl_killx, UInt<1>(0h0))
node _mem_reg_xcpt_T_1 = and(_mem_reg_xcpt_T, ex_xcpt)
connect mem_reg_xcpt, _mem_reg_xcpt_T_1
node _mem_reg_xcpt_interrupt_T = eq(take_pc_mem_wb, UInt<1>(0h0))
node _mem_reg_xcpt_interrupt_T_1 = and(_mem_reg_xcpt_interrupt_T, ex_reg_xcpt_interrupt)
connect mem_reg_xcpt_interrupt, _mem_reg_xcpt_interrupt_T_1
node _T_67 = and(mem_reg_valid, mem_reg_flush_pipe)
when _T_67 :
connect mem_reg_sfence, UInt<1>(0h0)
else :
when ex_pc_valid :
connect mem_ctrl, ex_ctrl
connect mem_reg_rvc, ex_reg_rvc
node _mem_reg_load_T = eq(ex_ctrl.mem_cmd, UInt<1>(0h0))
node _mem_reg_load_T_1 = eq(ex_ctrl.mem_cmd, UInt<5>(0h10))
node _mem_reg_load_T_2 = eq(ex_ctrl.mem_cmd, UInt<3>(0h6))
node _mem_reg_load_T_3 = eq(ex_ctrl.mem_cmd, UInt<3>(0h7))
node _mem_reg_load_T_4 = or(_mem_reg_load_T, _mem_reg_load_T_1)
node _mem_reg_load_T_5 = or(_mem_reg_load_T_4, _mem_reg_load_T_2)
node _mem_reg_load_T_6 = or(_mem_reg_load_T_5, _mem_reg_load_T_3)
node _mem_reg_load_T_7 = eq(ex_ctrl.mem_cmd, UInt<3>(0h4))
node _mem_reg_load_T_8 = eq(ex_ctrl.mem_cmd, UInt<4>(0h9))
node _mem_reg_load_T_9 = eq(ex_ctrl.mem_cmd, UInt<4>(0ha))
node _mem_reg_load_T_10 = eq(ex_ctrl.mem_cmd, UInt<4>(0hb))
node _mem_reg_load_T_11 = or(_mem_reg_load_T_7, _mem_reg_load_T_8)
node _mem_reg_load_T_12 = or(_mem_reg_load_T_11, _mem_reg_load_T_9)
node _mem_reg_load_T_13 = or(_mem_reg_load_T_12, _mem_reg_load_T_10)
node _mem_reg_load_T_14 = eq(ex_ctrl.mem_cmd, UInt<4>(0h8))
node _mem_reg_load_T_15 = eq(ex_ctrl.mem_cmd, UInt<4>(0hc))
node _mem_reg_load_T_16 = eq(ex_ctrl.mem_cmd, UInt<4>(0hd))
node _mem_reg_load_T_17 = eq(ex_ctrl.mem_cmd, UInt<4>(0he))
node _mem_reg_load_T_18 = eq(ex_ctrl.mem_cmd, UInt<4>(0hf))
node _mem_reg_load_T_19 = or(_mem_reg_load_T_14, _mem_reg_load_T_15)
node _mem_reg_load_T_20 = or(_mem_reg_load_T_19, _mem_reg_load_T_16)
node _mem_reg_load_T_21 = or(_mem_reg_load_T_20, _mem_reg_load_T_17)
node _mem_reg_load_T_22 = or(_mem_reg_load_T_21, _mem_reg_load_T_18)
node _mem_reg_load_T_23 = or(_mem_reg_load_T_13, _mem_reg_load_T_22)
node _mem_reg_load_T_24 = or(_mem_reg_load_T_6, _mem_reg_load_T_23)
node _mem_reg_load_T_25 = and(ex_ctrl.mem, _mem_reg_load_T_24)
connect mem_reg_load, _mem_reg_load_T_25
node _mem_reg_store_T = eq(ex_ctrl.mem_cmd, UInt<1>(0h1))
node _mem_reg_store_T_1 = eq(ex_ctrl.mem_cmd, UInt<5>(0h11))
node _mem_reg_store_T_2 = or(_mem_reg_store_T, _mem_reg_store_T_1)
node _mem_reg_store_T_3 = eq(ex_ctrl.mem_cmd, UInt<3>(0h7))
node _mem_reg_store_T_4 = or(_mem_reg_store_T_2, _mem_reg_store_T_3)
node _mem_reg_store_T_5 = eq(ex_ctrl.mem_cmd, UInt<3>(0h4))
node _mem_reg_store_T_6 = eq(ex_ctrl.mem_cmd, UInt<4>(0h9))
node _mem_reg_store_T_7 = eq(ex_ctrl.mem_cmd, UInt<4>(0ha))
node _mem_reg_store_T_8 = eq(ex_ctrl.mem_cmd, UInt<4>(0hb))
node _mem_reg_store_T_9 = or(_mem_reg_store_T_5, _mem_reg_store_T_6)
node _mem_reg_store_T_10 = or(_mem_reg_store_T_9, _mem_reg_store_T_7)
node _mem_reg_store_T_11 = or(_mem_reg_store_T_10, _mem_reg_store_T_8)
node _mem_reg_store_T_12 = eq(ex_ctrl.mem_cmd, UInt<4>(0h8))
node _mem_reg_store_T_13 = eq(ex_ctrl.mem_cmd, UInt<4>(0hc))
node _mem_reg_store_T_14 = eq(ex_ctrl.mem_cmd, UInt<4>(0hd))
node _mem_reg_store_T_15 = eq(ex_ctrl.mem_cmd, UInt<4>(0he))
node _mem_reg_store_T_16 = eq(ex_ctrl.mem_cmd, UInt<4>(0hf))
node _mem_reg_store_T_17 = or(_mem_reg_store_T_12, _mem_reg_store_T_13)
node _mem_reg_store_T_18 = or(_mem_reg_store_T_17, _mem_reg_store_T_14)
node _mem_reg_store_T_19 = or(_mem_reg_store_T_18, _mem_reg_store_T_15)
node _mem_reg_store_T_20 = or(_mem_reg_store_T_19, _mem_reg_store_T_16)
node _mem_reg_store_T_21 = or(_mem_reg_store_T_11, _mem_reg_store_T_20)
node _mem_reg_store_T_22 = or(_mem_reg_store_T_4, _mem_reg_store_T_21)
node _mem_reg_store_T_23 = and(ex_ctrl.mem, _mem_reg_store_T_22)
connect mem_reg_store, _mem_reg_store_T_23
connect mem_reg_sfence, ex_sfence
connect mem_reg_btb_resp, ex_reg_btb_resp
connect mem_reg_flush_pipe, ex_reg_flush_pipe
connect mem_reg_slow_bypass, ex_slow_bypass
connect mem_reg_wphit, ex_reg_wphit
connect mem_reg_set_vconfig, ex_reg_set_vconfig
connect mem_reg_cause, ex_cause
connect mem_reg_inst, ex_reg_inst
connect mem_reg_raw_inst, ex_reg_raw_inst
connect mem_reg_mem_size, ex_reg_mem_size
connect mem_reg_hls_or_dv, io.dmem.req.bits.dv
connect mem_reg_pc, ex_reg_pc
node _mem_reg_wdata_T = mux(ex_reg_set_vconfig, alu.io.out, alu.io.out)
connect mem_reg_wdata, _mem_reg_wdata_T
connect mem_br_taken, alu.io.cmp_out
node _T_68 = or(ex_ctrl.mem, ex_ctrl.rocc)
node _T_69 = or(_T_68, ex_sfence)
node _T_70 = and(ex_ctrl.rxs2, _T_69)
when _T_70 :
node size = mux(ex_ctrl.rocc, UInt<2>(0h3), ex_reg_mem_size)
wire mem_reg_rs2_size : UInt<2>
connect mem_reg_rs2_size, size
node mem_reg_rs2_dat_padded = pad(ex_rs_1, 64)
node _mem_reg_rs2_T = eq(mem_reg_rs2_size, UInt<1>(0h0))
node _mem_reg_rs2_T_1 = bits(mem_reg_rs2_dat_padded, 7, 0)
node _mem_reg_rs2_T_2 = cat(_mem_reg_rs2_T_1, _mem_reg_rs2_T_1)
node _mem_reg_rs2_T_3 = cat(_mem_reg_rs2_T_2, _mem_reg_rs2_T_2)
node _mem_reg_rs2_T_4 = cat(_mem_reg_rs2_T_3, _mem_reg_rs2_T_3)
node _mem_reg_rs2_T_5 = eq(mem_reg_rs2_size, UInt<1>(0h1))
node _mem_reg_rs2_T_6 = bits(mem_reg_rs2_dat_padded, 15, 0)
node _mem_reg_rs2_T_7 = cat(_mem_reg_rs2_T_6, _mem_reg_rs2_T_6)
node _mem_reg_rs2_T_8 = cat(_mem_reg_rs2_T_7, _mem_reg_rs2_T_7)
node _mem_reg_rs2_T_9 = eq(mem_reg_rs2_size, UInt<2>(0h2))
node _mem_reg_rs2_T_10 = bits(mem_reg_rs2_dat_padded, 31, 0)
node _mem_reg_rs2_T_11 = cat(_mem_reg_rs2_T_10, _mem_reg_rs2_T_10)
node _mem_reg_rs2_T_12 = mux(_mem_reg_rs2_T_9, _mem_reg_rs2_T_11, mem_reg_rs2_dat_padded)
node _mem_reg_rs2_T_13 = mux(_mem_reg_rs2_T_5, _mem_reg_rs2_T_8, _mem_reg_rs2_T_12)
node _mem_reg_rs2_T_14 = mux(_mem_reg_rs2_T, _mem_reg_rs2_T_4, _mem_reg_rs2_T_13)
connect mem_reg_rs2, _mem_reg_rs2_T_14
node _T_71 = and(ex_ctrl.jalr, csr.io.status.debug)
when _T_71 :
connect mem_ctrl.fence_i, UInt<1>(0h1)
connect mem_reg_flush_pipe, UInt<1>(0h1)
node _mem_breakpoint_T = and(mem_reg_load, bpu.io.xcpt_ld)
node _mem_breakpoint_T_1 = and(mem_reg_store, bpu.io.xcpt_st)
node mem_breakpoint = or(_mem_breakpoint_T, _mem_breakpoint_T_1)
node _mem_debug_breakpoint_T = and(mem_reg_load, bpu.io.debug_ld)
node _mem_debug_breakpoint_T_1 = and(mem_reg_store, bpu.io.debug_st)
node mem_debug_breakpoint = or(_mem_debug_breakpoint_T, _mem_debug_breakpoint_T_1)
node _T_72 = or(mem_debug_breakpoint, mem_breakpoint)
wire mem_ldst_xcpt : UInt<1>
connect mem_ldst_xcpt, _T_72
node _T_73 = mux(mem_debug_breakpoint, UInt<4>(0he), UInt<2>(0h3))
wire mem_ldst_cause : UInt
connect mem_ldst_cause, _T_73
node _T_74 = or(mem_reg_xcpt_interrupt, mem_reg_xcpt)
node _T_75 = and(mem_reg_valid, mem_npc_misaligned)
node _T_76 = and(mem_reg_valid, mem_ldst_xcpt)
node _T_77 = or(_T_74, _T_75)
node _T_78 = or(_T_77, _T_76)
wire mem_xcpt : UInt<1>
connect mem_xcpt, _T_78
node _T_79 = mux(_T_75, UInt<1>(0h0), mem_ldst_cause)
node _T_80 = mux(_T_74, mem_reg_cause, _T_79)
wire mem_cause : UInt
connect mem_cause, _T_80
node _T_81 = eq(mem_cause, UInt<4>(0he))
node _T_82 = and(mem_xcpt, _T_81)
node _T_83 = eq(mem_cause, UInt<2>(0h3))
node _T_84 = and(mem_xcpt, _T_83)
node _T_85 = eq(mem_cause, UInt<1>(0h1))
node _T_86 = and(mem_xcpt, _T_85)
node _T_87 = eq(mem_cause, UInt<2>(0h2))
node _T_88 = and(mem_xcpt, _T_87)
node _T_89 = eq(mem_cause, UInt<4>(0hc))
node _T_90 = and(mem_xcpt, _T_89)
node _T_91 = eq(mem_cause, UInt<1>(0h0))
node _T_92 = and(mem_xcpt, _T_91)
node _dcache_kill_mem_T = and(mem_reg_valid, mem_ctrl.wxd)
node dcache_kill_mem = and(_dcache_kill_mem_T, io.dmem.replay_next)
node _fpu_kill_mem_T = and(mem_reg_valid, mem_ctrl.fp)
node fpu_kill_mem = and(_fpu_kill_mem_T, io.fpu.nack_mem)
node _vec_kill_mem_T = and(mem_reg_valid, mem_ctrl.mem)
node vec_kill_mem = and(_vec_kill_mem_T, UInt<1>(0h0))
node vec_kill_all = and(mem_reg_valid, UInt<1>(0h0))
node _replay_mem_T = or(dcache_kill_mem, mem_reg_replay)
node _replay_mem_T_1 = or(_replay_mem_T, fpu_kill_mem)
node _replay_mem_T_2 = or(_replay_mem_T_1, vec_kill_mem)
node replay_mem = or(_replay_mem_T_2, vec_kill_all)
node _killm_common_T = or(dcache_kill_mem, take_pc_wb)
node _killm_common_T_1 = or(_killm_common_T, mem_reg_xcpt)
node _killm_common_T_2 = eq(mem_reg_valid, UInt<1>(0h0))
node killm_common = or(_killm_common_T_1, _killm_common_T_2)
node _div_io_kill_T = and(div.io.req.ready, div.io.req.valid)
reg div_io_kill_REG : UInt<1>, clock
connect div_io_kill_REG, _div_io_kill_T
node _div_io_kill_T_1 = and(killm_common, div_io_kill_REG)
connect div.io.kill, _div_io_kill_T_1
node _ctrl_killm_T = or(killm_common, mem_xcpt)
node _ctrl_killm_T_1 = or(_ctrl_killm_T, fpu_kill_mem)
node ctrl_killm = or(_ctrl_killm_T_1, vec_kill_mem)
node _wb_reg_valid_T = eq(ctrl_killm, UInt<1>(0h0))
connect wb_reg_valid, _wb_reg_valid_T
node _wb_reg_replay_T = eq(take_pc_wb, UInt<1>(0h0))
node _wb_reg_replay_T_1 = and(replay_mem, _wb_reg_replay_T)
connect wb_reg_replay, _wb_reg_replay_T_1
node _wb_reg_xcpt_T = eq(take_pc_wb, UInt<1>(0h0))
node _wb_reg_xcpt_T_1 = and(mem_xcpt, _wb_reg_xcpt_T)
node _wb_reg_xcpt_T_2 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _wb_reg_xcpt_T_3 = and(_wb_reg_xcpt_T_1, _wb_reg_xcpt_T_2)
connect wb_reg_xcpt, _wb_reg_xcpt_T_3
node _wb_reg_flush_pipe_T = eq(ctrl_killm, UInt<1>(0h0))
node _wb_reg_flush_pipe_T_1 = and(_wb_reg_flush_pipe_T, mem_reg_flush_pipe)
connect wb_reg_flush_pipe, _wb_reg_flush_pipe_T_1
when mem_pc_valid :
connect wb_ctrl, mem_ctrl
connect wb_reg_sfence, mem_reg_sfence
node _wb_reg_wdata_T = eq(mem_reg_xcpt, UInt<1>(0h0))
node _wb_reg_wdata_T_1 = and(_wb_reg_wdata_T, mem_ctrl.fp)
node _wb_reg_wdata_T_2 = and(_wb_reg_wdata_T_1, mem_ctrl.wxd)
node _wb_reg_wdata_T_3 = mux(_wb_reg_wdata_T_2, io.fpu.toint_data, mem_int_wdata)
connect wb_reg_wdata, _wb_reg_wdata_T_3
node _T_93 = or(mem_ctrl.rocc, mem_reg_sfence)
node _T_94 = or(_T_93, mem_reg_set_vconfig)
when _T_94 :
connect wb_reg_rs2, mem_reg_rs2
connect wb_reg_cause, mem_cause
connect wb_reg_inst, mem_reg_inst
connect wb_reg_raw_inst, mem_reg_raw_inst
connect wb_reg_mem_size, mem_reg_mem_size
connect wb_reg_hls_or_dv, mem_reg_hls_or_dv
node _wb_reg_hfence_v_T = eq(mem_ctrl.mem_cmd, UInt<5>(0h15))
connect wb_reg_hfence_v, _wb_reg_hfence_v_T
node _wb_reg_hfence_g_T = eq(mem_ctrl.mem_cmd, UInt<5>(0h16))
connect wb_reg_hfence_g, _wb_reg_hfence_g_T
connect wb_reg_pc, mem_reg_pc
node _T_95 = and(bpu.io.bpwatch[0].rvalid[0], mem_reg_load)
node _T_96 = and(bpu.io.bpwatch[0].wvalid[0], mem_reg_store)
node _T_97 = or(_T_95, _T_96)
node _T_98 = or(mem_reg_wphit[0], _T_97)
connect wb_reg_wphit[0], _T_98
connect wb_reg_set_vconfig, mem_reg_set_vconfig
node _T_99 = and(wb_reg_valid, wb_ctrl.mem)
node _T_100 = and(_T_99, io.dmem.s2_xcpt.pf.st)
node _T_101 = and(wb_reg_valid, wb_ctrl.mem)
node _T_102 = and(_T_101, io.dmem.s2_xcpt.pf.ld)
node _T_103 = and(wb_reg_valid, wb_ctrl.mem)
node _T_104 = and(_T_103, io.dmem.s2_xcpt.gf.st)
node _T_105 = and(wb_reg_valid, wb_ctrl.mem)
node _T_106 = and(_T_105, io.dmem.s2_xcpt.gf.ld)
node _T_107 = and(wb_reg_valid, wb_ctrl.mem)
node _T_108 = and(_T_107, io.dmem.s2_xcpt.ae.st)
node _T_109 = and(wb_reg_valid, wb_ctrl.mem)
node _T_110 = and(_T_109, io.dmem.s2_xcpt.ae.ld)
node _T_111 = and(wb_reg_valid, wb_ctrl.mem)
node _T_112 = and(_T_111, io.dmem.s2_xcpt.ma.st)
node _T_113 = and(wb_reg_valid, wb_ctrl.mem)
node _T_114 = and(_T_113, io.dmem.s2_xcpt.ma.ld)
node _T_115 = or(wb_reg_xcpt, _T_100)
node _T_116 = or(_T_115, _T_102)
node _T_117 = or(_T_116, _T_104)
node _T_118 = or(_T_117, _T_106)
node _T_119 = or(_T_118, _T_108)
node _T_120 = or(_T_119, _T_110)
node _T_121 = or(_T_120, _T_112)
node _T_122 = or(_T_121, _T_114)
wire wb_xcpt : UInt<1>
connect wb_xcpt, _T_122
node _T_123 = mux(_T_112, UInt<3>(0h6), UInt<3>(0h4))
node _T_124 = mux(_T_110, UInt<3>(0h5), _T_123)
node _T_125 = mux(_T_108, UInt<3>(0h7), _T_124)
node _T_126 = mux(_T_106, UInt<5>(0h15), _T_125)
node _T_127 = mux(_T_104, UInt<5>(0h17), _T_126)
node _T_128 = mux(_T_102, UInt<4>(0hd), _T_127)
node _T_129 = mux(_T_100, UInt<4>(0hf), _T_128)
node _T_130 = mux(wb_reg_xcpt, wb_reg_cause, _T_129)
wire wb_cause : UInt
connect wb_cause, _T_130
node _T_131 = eq(wb_cause, UInt<3>(0h6))
node _T_132 = and(wb_xcpt, _T_131)
node _T_133 = eq(wb_cause, UInt<3>(0h4))
node _T_134 = and(wb_xcpt, _T_133)
node _T_135 = eq(wb_cause, UInt<3>(0h7))
node _T_136 = and(wb_xcpt, _T_135)
node _T_137 = eq(wb_cause, UInt<3>(0h5))
node _T_138 = and(wb_xcpt, _T_137)
node _T_139 = eq(wb_cause, UInt<4>(0hf))
node _T_140 = and(wb_xcpt, _T_139)
node _T_141 = eq(wb_cause, UInt<4>(0hd))
node _T_142 = and(wb_xcpt, _T_141)
node _wb_pc_valid_T = or(wb_reg_valid, wb_reg_replay)
node wb_pc_valid = or(_wb_pc_valid_T, wb_reg_xcpt)
node wb_wxd = and(wb_reg_valid, wb_ctrl.wxd)
node _wb_set_sboard_T = or(wb_ctrl.div, wb_dcache_miss)
node _wb_set_sboard_T_1 = or(_wb_set_sboard_T, wb_ctrl.rocc)
node wb_set_sboard = or(_wb_set_sboard_T_1, wb_ctrl.vec)
node replay_wb_common = or(io.dmem.s2_nack, wb_reg_replay)
node _replay_wb_rocc_T = and(wb_reg_valid, wb_ctrl.rocc)
node _replay_wb_rocc_T_1 = eq(io.rocc.cmd.ready, UInt<1>(0h0))
node replay_wb_rocc = and(_replay_wb_rocc_T, _replay_wb_rocc_T_1)
node replay_wb_csr = and(wb_reg_valid, csr.io.rw_stall)
node replay_wb_vec = and(wb_reg_valid, UInt<1>(0h0))
node _replay_wb_T = or(replay_wb_common, replay_wb_rocc)
node _replay_wb_T_1 = or(_replay_wb_T, replay_wb_csr)
node replay_wb = or(_replay_wb_T_1, replay_wb_vec)
node _take_pc_wb_T = or(replay_wb, wb_xcpt)
node _take_pc_wb_T_1 = or(_take_pc_wb_T, csr.io.eret)
node _take_pc_wb_T_2 = or(_take_pc_wb_T_1, wb_reg_flush_pipe)
connect take_pc_wb, _take_pc_wb_T_2
node _dmem_resp_xpu_T = bits(io.dmem.resp.bits.tag, 0, 0)
node dmem_resp_xpu = eq(_dmem_resp_xpu_T, UInt<1>(0h0))
node dmem_resp_fpu = bits(io.dmem.resp.bits.tag, 0, 0)
node dmem_resp_waddr = bits(io.dmem.resp.bits.tag, 5, 1)
node dmem_resp_valid = and(io.dmem.resp.valid, io.dmem.resp.bits.has_data)
node dmem_resp_replay = and(dmem_resp_valid, io.dmem.resp.bits.replay)
inst ll_arb of Arbiter3_LLWB
connect ll_arb.clock, clock
connect ll_arb.reset, reset
connect ll_arb.io.in[0].valid, UInt<1>(0h0)
connect ll_arb.io.in[1].valid, UInt<1>(0h0)
connect ll_arb.io.in[2].valid, UInt<1>(0h0)
invalidate ll_arb.io.in[0].bits.tag
invalidate ll_arb.io.in[0].bits.data
invalidate ll_arb.io.in[1].bits.tag
invalidate ll_arb.io.in[1].bits.data
invalidate ll_arb.io.in[2].bits.tag
invalidate ll_arb.io.in[2].bits.data
wire ll_wdata : UInt
connect ll_wdata, ll_arb.io.out.bits.data
wire ll_waddr : UInt
connect ll_waddr, ll_arb.io.out.bits.tag
node _ll_wen_T = and(ll_arb.io.out.ready, ll_arb.io.out.valid)
wire ll_wen : UInt<1>
connect ll_wen, _ll_wen_T
node _ll_arb_io_out_ready_T = eq(wb_wxd, UInt<1>(0h0))
connect ll_arb.io.out.ready, _ll_arb_io_out_ready_T
connect div.io.resp.ready, ll_arb.io.in[0].ready
connect ll_arb.io.in[0].valid, div.io.resp.valid
connect ll_arb.io.in[0].bits.data, div.io.resp.bits.data
connect ll_arb.io.in[0].bits.tag, div.io.resp.bits.tag
connect io.rocc.resp.ready, UInt<1>(0h0)
connect io.rocc.mem.req.ready, UInt<1>(0h0)
invalidate io.rocc.mem.clock_enabled
invalidate io.rocc.mem.keep_clock_enabled
invalidate io.rocc.mem.perf.storeBufferEmptyAfterStore
invalidate io.rocc.mem.perf.storeBufferEmptyAfterLoad
invalidate io.rocc.mem.perf.canAcceptLoadThenLoad
invalidate io.rocc.mem.perf.canAcceptStoreThenRMW
invalidate io.rocc.mem.perf.canAcceptStoreThenLoad
invalidate io.rocc.mem.perf.blocked
invalidate io.rocc.mem.perf.tlbMiss
invalidate io.rocc.mem.perf.grant
invalidate io.rocc.mem.perf.release
invalidate io.rocc.mem.perf.acquire
invalidate io.rocc.mem.store_pending
invalidate io.rocc.mem.ordered
invalidate io.rocc.mem.s2_gpa_is_pte
invalidate io.rocc.mem.s2_gpa
invalidate io.rocc.mem.s2_xcpt.ae.st
invalidate io.rocc.mem.s2_xcpt.ae.ld
invalidate io.rocc.mem.s2_xcpt.gf.st
invalidate io.rocc.mem.s2_xcpt.gf.ld
invalidate io.rocc.mem.s2_xcpt.pf.st
invalidate io.rocc.mem.s2_xcpt.pf.ld
invalidate io.rocc.mem.s2_xcpt.ma.st
invalidate io.rocc.mem.s2_xcpt.ma.ld
invalidate io.rocc.mem.replay_next
invalidate io.rocc.mem.resp.bits.store_data
invalidate io.rocc.mem.resp.bits.data_raw
invalidate io.rocc.mem.resp.bits.data_word_bypass
invalidate io.rocc.mem.resp.bits.has_data
invalidate io.rocc.mem.resp.bits.replay
invalidate io.rocc.mem.resp.bits.mask
invalidate io.rocc.mem.resp.bits.data
invalidate io.rocc.mem.resp.bits.dv
invalidate io.rocc.mem.resp.bits.dprv
invalidate io.rocc.mem.resp.bits.signed
invalidate io.rocc.mem.resp.bits.size
invalidate io.rocc.mem.resp.bits.cmd
invalidate io.rocc.mem.resp.bits.tag
invalidate io.rocc.mem.resp.bits.addr
invalidate io.rocc.mem.resp.valid
invalidate io.rocc.mem.s2_paddr
invalidate io.rocc.mem.s2_uncached
invalidate io.rocc.mem.s2_kill
invalidate io.rocc.mem.s2_nack_cause_raw
invalidate io.rocc.mem.s2_nack
invalidate io.rocc.mem.s1_data.mask
invalidate io.rocc.mem.s1_data.data
invalidate io.rocc.mem.s1_kill
invalidate io.rocc.mem.req.bits.mask
invalidate io.rocc.mem.req.bits.data
invalidate io.rocc.mem.req.bits.no_xcpt
invalidate io.rocc.mem.req.bits.no_alloc
invalidate io.rocc.mem.req.bits.no_resp
invalidate io.rocc.mem.req.bits.phys
invalidate io.rocc.mem.req.bits.dv
invalidate io.rocc.mem.req.bits.dprv
invalidate io.rocc.mem.req.bits.signed
invalidate io.rocc.mem.req.bits.size
invalidate io.rocc.mem.req.bits.cmd
invalidate io.rocc.mem.req.bits.tag
invalidate io.rocc.mem.req.bits.addr
invalidate io.rocc.mem.req.valid
invalidate io.rocc.mem.req.ready
node _T_143 = and(dmem_resp_replay, dmem_resp_xpu)
when _T_143 :
connect ll_arb.io.out.ready, UInt<1>(0h0)
connect ll_waddr, dmem_resp_waddr
connect ll_wen, UInt<1>(0h1)
node _wb_valid_T = eq(replay_wb, UInt<1>(0h0))
node _wb_valid_T_1 = and(wb_reg_valid, _wb_valid_T)
node _wb_valid_T_2 = eq(wb_xcpt, UInt<1>(0h0))
node wb_valid = and(_wb_valid_T_1, _wb_valid_T_2)
node wb_wen = and(wb_valid, wb_ctrl.wxd)
node rf_wen = or(wb_wen, ll_wen)
node rf_waddr = mux(ll_wen, ll_waddr, wb_waddr)
node _rf_wdata_T = and(dmem_resp_valid, dmem_resp_xpu)
node _rf_wdata_T_1 = bits(io.dmem.resp.bits.data, 63, 0)
node _rf_wdata_T_2 = neq(wb_ctrl.csr, UInt<3>(0h0))
node _rf_wdata_T_3 = mux(wb_ctrl.mul, wb_reg_wdata, wb_reg_wdata)
node _rf_wdata_T_4 = mux(_rf_wdata_T_2, csr.io.rw.rdata, _rf_wdata_T_3)
node _rf_wdata_T_5 = mux(ll_wen, ll_wdata, _rf_wdata_T_4)
node rf_wdata = mux(_rf_wdata_T, _rf_wdata_T_1, _rf_wdata_T_5)
when rf_wen :
node _T_144 = neq(rf_waddr, UInt<1>(0h0))
when _T_144 :
node _T_145 = bits(rf_waddr, 4, 0)
node _T_146 = not(_T_145)
infer mport MPORT = rf[_T_146], clock
connect MPORT, rf_wdata
node _T_147 = eq(rf_waddr, id_raddr1)
when _T_147 :
connect id_rs_0, rf_wdata
node _T_148 = eq(rf_waddr, id_raddr2)
when _T_148 :
connect id_rs_1, rf_wdata
connect csr.io.ungated_clock, clock
connect csr.io.decode[0].inst, ibuf.io.inst[0].bits.inst.bits
connect csr.io.exception, wb_xcpt
connect csr.io.cause, wb_cause
connect csr.io.retire, wb_valid
node _csr_io_inst_0_T = bits(wb_reg_raw_inst, 1, 0)
node _csr_io_inst_0_T_1 = andr(_csr_io_inst_0_T)
node _csr_io_inst_0_T_2 = shr(wb_reg_inst, 16)
node _csr_io_inst_0_T_3 = mux(_csr_io_inst_0_T_1, _csr_io_inst_0_T_2, UInt<1>(0h0))
node _csr_io_inst_0_T_4 = bits(wb_reg_raw_inst, 15, 0)
node _csr_io_inst_0_T_5 = cat(_csr_io_inst_0_T_3, _csr_io_inst_0_T_4)
connect csr.io.inst[0], _csr_io_inst_0_T_5
connect csr.io.interrupts.seip, io.interrupts.seip
connect csr.io.interrupts.meip, io.interrupts.meip
connect csr.io.interrupts.msip, io.interrupts.msip
connect csr.io.interrupts.mtip, io.interrupts.mtip
connect csr.io.interrupts.debug, io.interrupts.debug
connect csr.io.hartid, io.hartid
connect io.fpu.fcsr_rm, csr.io.fcsr_rm
node _csr_io_fcsr_flags_valid_T = or(io.fpu.fcsr_flags.valid, UInt<1>(0h0))
connect csr.io.fcsr_flags.valid, _csr_io_fcsr_flags_valid_T
node _csr_io_fcsr_flags_bits_T = mux(io.fpu.fcsr_flags.valid, UInt<5>(0h1f), UInt<5>(0h0))
node _csr_io_fcsr_flags_bits_T_1 = and(io.fpu.fcsr_flags.bits, _csr_io_fcsr_flags_bits_T)
node _csr_io_fcsr_flags_bits_T_2 = mux(UInt<1>(0h0), UInt<5>(0h1f), UInt<5>(0h0))
node _csr_io_fcsr_flags_bits_T_3 = and(UInt<5>(0h0), _csr_io_fcsr_flags_bits_T_2)
node _csr_io_fcsr_flags_bits_T_4 = or(_csr_io_fcsr_flags_bits_T_1, _csr_io_fcsr_flags_bits_T_3)
connect csr.io.fcsr_flags.bits, _csr_io_fcsr_flags_bits_T_4
node _io_fpu_time_T = bits(csr.io.time, 31, 0)
connect io.fpu.time, _io_fpu_time_T
connect io.fpu.hartid, io.hartid
connect csr.io.rocc_interrupt, io.rocc.interrupt
connect csr.io.pc, wb_reg_pc
node tval_dmem_addr = eq(wb_reg_xcpt, UInt<1>(0h0))
node _tval_any_addr_T = eq(wb_reg_cause, UInt<2>(0h3))
node _tval_any_addr_T_1 = eq(wb_reg_cause, UInt<1>(0h1))
node _tval_any_addr_T_2 = eq(wb_reg_cause, UInt<4>(0hc))
node _tval_any_addr_T_3 = eq(wb_reg_cause, UInt<5>(0h14))
node _tval_any_addr_T_4 = or(_tval_any_addr_T, _tval_any_addr_T_1)
node _tval_any_addr_T_5 = or(_tval_any_addr_T_4, _tval_any_addr_T_2)
node _tval_any_addr_T_6 = or(_tval_any_addr_T_5, _tval_any_addr_T_3)
node tval_any_addr = or(tval_dmem_addr, _tval_any_addr_T_6)
node tval_inst = eq(wb_reg_cause, UInt<2>(0h2))
node _tval_valid_T = or(tval_any_addr, tval_inst)
node tval_valid = and(wb_xcpt, _tval_valid_T)
node _csr_io_gva_T = and(tval_any_addr, csr.io.status.v)
node _csr_io_gva_T_1 = and(tval_dmem_addr, wb_reg_hls_or_dv)
node _csr_io_gva_T_2 = or(_csr_io_gva_T, _csr_io_gva_T_1)
node _csr_io_gva_T_3 = and(wb_xcpt, _csr_io_gva_T_2)
connect csr.io.gva, _csr_io_gva_T_3
node _csr_io_tval_a_T = shr(wb_reg_wdata, 39)
node csr_io_tval_a = asSInt(_csr_io_tval_a_T)
node _csr_io_tval_msb_T = eq(csr_io_tval_a, asSInt(UInt<1>(0h0)))
node _csr_io_tval_msb_T_1 = eq(csr_io_tval_a, asSInt(UInt<1>(0h1)))
node _csr_io_tval_msb_T_2 = or(_csr_io_tval_msb_T, _csr_io_tval_msb_T_1)
node _csr_io_tval_msb_T_3 = bits(wb_reg_wdata, 39, 39)
node _csr_io_tval_msb_T_4 = bits(wb_reg_wdata, 38, 38)
node _csr_io_tval_msb_T_5 = eq(_csr_io_tval_msb_T_4, UInt<1>(0h0))
node csr_io_tval_msb = mux(_csr_io_tval_msb_T_2, _csr_io_tval_msb_T_3, _csr_io_tval_msb_T_5)
node _csr_io_tval_T = bits(wb_reg_wdata, 38, 0)
node _csr_io_tval_T_1 = cat(csr_io_tval_msb, _csr_io_tval_T)
node _csr_io_tval_T_2 = mux(tval_valid, _csr_io_tval_T_1, UInt<1>(0h0))
connect csr.io.tval, _csr_io_tval_T_2
node _htval_valid_imem_T = eq(wb_reg_cause, UInt<5>(0h14))
node htval_valid_imem = and(wb_reg_xcpt, _htval_valid_imem_T)
node htval_imem = mux(htval_valid_imem, io.imem.gpa.bits, UInt<1>(0h0))
node _T_149 = eq(htval_valid_imem, UInt<1>(0h0))
node _T_150 = or(_T_149, io.imem.gpa.valid)
node _T_151 = asUInt(reset)
node _T_152 = eq(_T_151, UInt<1>(0h0))
when _T_152 :
node _T_153 = eq(_T_150, UInt<1>(0h0))
when _T_153 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at RocketCore.scala:855 assert(!htval_valid_imem || io.imem.gpa.valid)\n") : printf
assert(clock, _T_150, UInt<1>(0h1), "") : assert
node _htval_valid_dmem_T = and(wb_xcpt, tval_dmem_addr)
node _htval_valid_dmem_T_1 = cat(io.dmem.s2_xcpt.gf.ld, io.dmem.s2_xcpt.gf.st)
node _htval_valid_dmem_T_2 = orr(_htval_valid_dmem_T_1)
node _htval_valid_dmem_T_3 = and(_htval_valid_dmem_T, _htval_valid_dmem_T_2)
node _htval_valid_dmem_T_4 = cat(io.dmem.s2_xcpt.pf.ld, io.dmem.s2_xcpt.pf.st)
node _htval_valid_dmem_T_5 = orr(_htval_valid_dmem_T_4)
node _htval_valid_dmem_T_6 = eq(_htval_valid_dmem_T_5, UInt<1>(0h0))
node htval_valid_dmem = and(_htval_valid_dmem_T_3, _htval_valid_dmem_T_6)
node htval_dmem = mux(htval_valid_dmem, io.dmem.s2_gpa, UInt<1>(0h0))
node _htval_T = or(htval_dmem, htval_imem)
node htval = shr(_htval_T, 0)
node _mhtinst_read_pseudo_T = and(io.imem.gpa_is_pte, htval_valid_imem)
node _mhtinst_read_pseudo_T_1 = and(io.dmem.s2_gpa_is_pte, htval_valid_dmem)
node mhtinst_read_pseudo = or(_mhtinst_read_pseudo_T, _mhtinst_read_pseudo_T_1)
connect csr.io.htval, htval
connect csr.io.mhtinst_read_pseudo, mhtinst_read_pseudo
connect io.ptw.ptbr, csr.io.ptbr
connect io.ptw.hgatp, csr.io.hgatp
connect io.ptw.vsatp, csr.io.vsatp
connect csr.io.customCSRs[0].sdata, io.ptw.customCSRs.csrs[0].sdata
connect csr.io.customCSRs[0].set, io.ptw.customCSRs.csrs[0].set
connect csr.io.customCSRs[0].stall, io.ptw.customCSRs.csrs[0].stall
connect io.ptw.customCSRs.csrs[0].value, csr.io.customCSRs[0].value
connect io.ptw.customCSRs.csrs[0].wdata, csr.io.customCSRs[0].wdata
connect io.ptw.customCSRs.csrs[0].wen, csr.io.customCSRs[0].wen
connect io.ptw.customCSRs.csrs[0].ren, csr.io.customCSRs[0].ren
connect csr.io.customCSRs[1].sdata, io.ptw.customCSRs.csrs[1].sdata
connect csr.io.customCSRs[1].set, io.ptw.customCSRs.csrs[1].set
connect csr.io.customCSRs[1].stall, io.ptw.customCSRs.csrs[1].stall
connect io.ptw.customCSRs.csrs[1].value, csr.io.customCSRs[1].value
connect io.ptw.customCSRs.csrs[1].wdata, csr.io.customCSRs[1].wdata
connect io.ptw.customCSRs.csrs[1].wen, csr.io.customCSRs[1].wen
connect io.ptw.customCSRs.csrs[1].ren, csr.io.customCSRs[1].ren
connect csr.io.customCSRs[2].sdata, io.ptw.customCSRs.csrs[2].sdata
connect csr.io.customCSRs[2].set, io.ptw.customCSRs.csrs[2].set
connect csr.io.customCSRs[2].stall, io.ptw.customCSRs.csrs[2].stall
connect io.ptw.customCSRs.csrs[2].value, csr.io.customCSRs[2].value
connect io.ptw.customCSRs.csrs[2].wdata, csr.io.customCSRs[2].wdata
connect io.ptw.customCSRs.csrs[2].wen, csr.io.customCSRs[2].wen
connect io.ptw.customCSRs.csrs[2].ren, csr.io.customCSRs[2].ren
connect csr.io.customCSRs[3].sdata, io.ptw.customCSRs.csrs[3].sdata
connect csr.io.customCSRs[3].set, io.ptw.customCSRs.csrs[3].set
connect csr.io.customCSRs[3].stall, io.ptw.customCSRs.csrs[3].stall
connect io.ptw.customCSRs.csrs[3].value, csr.io.customCSRs[3].value
connect io.ptw.customCSRs.csrs[3].wdata, csr.io.customCSRs[3].wdata
connect io.ptw.customCSRs.csrs[3].wen, csr.io.customCSRs[3].wen
connect io.ptw.customCSRs.csrs[3].ren, csr.io.customCSRs[3].ren
connect io.ptw.status, csr.io.status
connect io.ptw.hstatus, csr.io.hstatus
connect io.ptw.gstatus, csr.io.gstatus
connect io.ptw.pmp, csr.io.pmp
node _csr_io_rw_addr_T = bits(wb_reg_inst, 31, 20)
connect csr.io.rw.addr, _csr_io_rw_addr_T
node _csr_io_rw_cmd_T = mux(wb_reg_valid, UInt<1>(0h0), UInt<3>(0h4))
node _csr_io_rw_cmd_T_1 = not(_csr_io_rw_cmd_T)
node _csr_io_rw_cmd_T_2 = and(wb_ctrl.csr, _csr_io_rw_cmd_T_1)
connect csr.io.rw.cmd, _csr_io_rw_cmd_T_2
connect csr.io.rw.wdata, wb_reg_wdata
connect io.trace.time, csr.io.time
connect io.trace.insns, csr.io.trace
connect io.trace.insns, csr.io.trace
connect io.bpwatch[0].valid[0], wb_reg_wphit[0]
connect io.bpwatch[0].action, csr.io.bp[0].control.action
connect io.bpwatch[0].rvalid[0], UInt<1>(0h0)
connect io.bpwatch[0].wvalid[0], UInt<1>(0h0)
connect io.bpwatch[0].ivalid[0], UInt<1>(0h0)
node _hazard_targets_T = neq(id_raddr1, UInt<1>(0h0))
node hazard_targets_0_1 = and(id_ctrl.rxs1, _hazard_targets_T)
node _hazard_targets_T_1 = neq(id_raddr2, UInt<1>(0h0))
node hazard_targets_1_1 = and(id_ctrl.rxs2, _hazard_targets_T_1)
node _hazard_targets_T_2 = neq(id_waddr, UInt<1>(0h0))
node hazard_targets_2_1 = and(id_ctrl.wxd, _hazard_targets_T_2)
regreset _r : UInt<32>, clock, reset, UInt<32>(0h0)
node _r_T = shr(_r, 1)
node r = shl(_r_T, 1)
node _T_154 = dshl(UInt<1>(0h1), ll_waddr)
node _T_155 = mux(ll_wen, _T_154, UInt<1>(0h0))
node _T_156 = not(_T_155)
node _T_157 = and(r, _T_156)
node _T_158 = or(UInt<1>(0h0), ll_wen)
when _T_158 :
connect _r, _T_157
node _id_sboard_hazard_T = dshr(r, id_raddr1)
node _id_sboard_hazard_T_1 = bits(_id_sboard_hazard_T, 0, 0)
node _id_sboard_hazard_T_2 = eq(ll_waddr, id_raddr1)
node _id_sboard_hazard_T_3 = and(ll_wen, _id_sboard_hazard_T_2)
node _id_sboard_hazard_T_4 = eq(_id_sboard_hazard_T_3, UInt<1>(0h0))
node _id_sboard_hazard_T_5 = and(_id_sboard_hazard_T_1, _id_sboard_hazard_T_4)
node _id_sboard_hazard_T_6 = and(hazard_targets_0_1, _id_sboard_hazard_T_5)
node _id_sboard_hazard_T_7 = dshr(r, id_raddr2)
node _id_sboard_hazard_T_8 = bits(_id_sboard_hazard_T_7, 0, 0)
node _id_sboard_hazard_T_9 = eq(ll_waddr, id_raddr2)
node _id_sboard_hazard_T_10 = and(ll_wen, _id_sboard_hazard_T_9)
node _id_sboard_hazard_T_11 = eq(_id_sboard_hazard_T_10, UInt<1>(0h0))
node _id_sboard_hazard_T_12 = and(_id_sboard_hazard_T_8, _id_sboard_hazard_T_11)
node _id_sboard_hazard_T_13 = and(hazard_targets_1_1, _id_sboard_hazard_T_12)
node _id_sboard_hazard_T_14 = dshr(r, id_waddr)
node _id_sboard_hazard_T_15 = bits(_id_sboard_hazard_T_14, 0, 0)
node _id_sboard_hazard_T_16 = eq(ll_waddr, id_waddr)
node _id_sboard_hazard_T_17 = and(ll_wen, _id_sboard_hazard_T_16)
node _id_sboard_hazard_T_18 = eq(_id_sboard_hazard_T_17, UInt<1>(0h0))
node _id_sboard_hazard_T_19 = and(_id_sboard_hazard_T_15, _id_sboard_hazard_T_18)
node _id_sboard_hazard_T_20 = and(hazard_targets_2_1, _id_sboard_hazard_T_19)
node _id_sboard_hazard_T_21 = or(_id_sboard_hazard_T_6, _id_sboard_hazard_T_13)
node id_sboard_hazard = or(_id_sboard_hazard_T_21, _id_sboard_hazard_T_20)
node _T_159 = and(wb_set_sboard, wb_wen)
node _T_160 = dshl(UInt<1>(0h1), wb_waddr)
node _T_161 = mux(_T_159, _T_160, UInt<1>(0h0))
node _T_162 = or(_T_157, _T_161)
node _T_163 = or(_T_158, _T_159)
when _T_163 :
connect _r, _T_162
node _ex_cannot_bypass_T = neq(ex_ctrl.csr, UInt<3>(0h0))
node _ex_cannot_bypass_T_1 = or(_ex_cannot_bypass_T, ex_ctrl.jalr)
node _ex_cannot_bypass_T_2 = or(_ex_cannot_bypass_T_1, ex_ctrl.mem)
node _ex_cannot_bypass_T_3 = or(_ex_cannot_bypass_T_2, ex_ctrl.mul)
node _ex_cannot_bypass_T_4 = or(_ex_cannot_bypass_T_3, ex_ctrl.div)
node _ex_cannot_bypass_T_5 = or(_ex_cannot_bypass_T_4, ex_ctrl.fp)
node _ex_cannot_bypass_T_6 = or(_ex_cannot_bypass_T_5, ex_ctrl.rocc)
node ex_cannot_bypass = or(_ex_cannot_bypass_T_6, ex_ctrl.vec)
node _data_hazard_ex_T = eq(id_raddr1, ex_waddr)
node _data_hazard_ex_T_1 = and(hazard_targets_0_1, _data_hazard_ex_T)
node _data_hazard_ex_T_2 = eq(id_raddr2, ex_waddr)
node _data_hazard_ex_T_3 = and(hazard_targets_1_1, _data_hazard_ex_T_2)
node _data_hazard_ex_T_4 = eq(id_waddr, ex_waddr)
node _data_hazard_ex_T_5 = and(hazard_targets_2_1, _data_hazard_ex_T_4)
node _data_hazard_ex_T_6 = or(_data_hazard_ex_T_1, _data_hazard_ex_T_3)
node _data_hazard_ex_T_7 = or(_data_hazard_ex_T_6, _data_hazard_ex_T_5)
node data_hazard_ex = and(ex_ctrl.wxd, _data_hazard_ex_T_7)
node _fp_data_hazard_ex_T = and(id_ctrl.fp, ex_ctrl.wfd)
node _fp_data_hazard_ex_T_1 = eq(id_raddr1, ex_waddr)
node _fp_data_hazard_ex_T_2 = and(io.fpu.dec.ren1, _fp_data_hazard_ex_T_1)
node _fp_data_hazard_ex_T_3 = eq(id_raddr2, ex_waddr)
node _fp_data_hazard_ex_T_4 = and(io.fpu.dec.ren2, _fp_data_hazard_ex_T_3)
node _fp_data_hazard_ex_T_5 = eq(id_raddr3, ex_waddr)
node _fp_data_hazard_ex_T_6 = and(io.fpu.dec.ren3, _fp_data_hazard_ex_T_5)
node _fp_data_hazard_ex_T_7 = eq(id_waddr, ex_waddr)
node _fp_data_hazard_ex_T_8 = and(io.fpu.dec.wen, _fp_data_hazard_ex_T_7)
node _fp_data_hazard_ex_T_9 = or(_fp_data_hazard_ex_T_2, _fp_data_hazard_ex_T_4)
node _fp_data_hazard_ex_T_10 = or(_fp_data_hazard_ex_T_9, _fp_data_hazard_ex_T_6)
node _fp_data_hazard_ex_T_11 = or(_fp_data_hazard_ex_T_10, _fp_data_hazard_ex_T_8)
node fp_data_hazard_ex = and(_fp_data_hazard_ex_T, _fp_data_hazard_ex_T_11)
node _id_ex_hazard_T = and(data_hazard_ex, ex_cannot_bypass)
node _id_ex_hazard_T_1 = or(_id_ex_hazard_T, fp_data_hazard_ex)
node id_ex_hazard = and(ex_reg_valid, _id_ex_hazard_T_1)
node mem_mem_cmd_bh = and(UInt<1>(0h1), mem_reg_slow_bypass)
node _mem_cannot_bypass_T = neq(mem_ctrl.csr, UInt<3>(0h0))
node _mem_cannot_bypass_T_1 = and(mem_ctrl.mem, mem_mem_cmd_bh)
node _mem_cannot_bypass_T_2 = or(_mem_cannot_bypass_T, _mem_cannot_bypass_T_1)
node _mem_cannot_bypass_T_3 = or(_mem_cannot_bypass_T_2, mem_ctrl.mul)
node _mem_cannot_bypass_T_4 = or(_mem_cannot_bypass_T_3, mem_ctrl.div)
node _mem_cannot_bypass_T_5 = or(_mem_cannot_bypass_T_4, mem_ctrl.fp)
node _mem_cannot_bypass_T_6 = or(_mem_cannot_bypass_T_5, mem_ctrl.rocc)
node mem_cannot_bypass = or(_mem_cannot_bypass_T_6, mem_ctrl.vec)
node _data_hazard_mem_T = eq(id_raddr1, mem_waddr)
node _data_hazard_mem_T_1 = and(hazard_targets_0_1, _data_hazard_mem_T)
node _data_hazard_mem_T_2 = eq(id_raddr2, mem_waddr)
node _data_hazard_mem_T_3 = and(hazard_targets_1_1, _data_hazard_mem_T_2)
node _data_hazard_mem_T_4 = eq(id_waddr, mem_waddr)
node _data_hazard_mem_T_5 = and(hazard_targets_2_1, _data_hazard_mem_T_4)
node _data_hazard_mem_T_6 = or(_data_hazard_mem_T_1, _data_hazard_mem_T_3)
node _data_hazard_mem_T_7 = or(_data_hazard_mem_T_6, _data_hazard_mem_T_5)
node data_hazard_mem = and(mem_ctrl.wxd, _data_hazard_mem_T_7)
node _fp_data_hazard_mem_T = and(id_ctrl.fp, mem_ctrl.wfd)
node _fp_data_hazard_mem_T_1 = eq(id_raddr1, mem_waddr)
node _fp_data_hazard_mem_T_2 = and(io.fpu.dec.ren1, _fp_data_hazard_mem_T_1)
node _fp_data_hazard_mem_T_3 = eq(id_raddr2, mem_waddr)
node _fp_data_hazard_mem_T_4 = and(io.fpu.dec.ren2, _fp_data_hazard_mem_T_3)
node _fp_data_hazard_mem_T_5 = eq(id_raddr3, mem_waddr)
node _fp_data_hazard_mem_T_6 = and(io.fpu.dec.ren3, _fp_data_hazard_mem_T_5)
node _fp_data_hazard_mem_T_7 = eq(id_waddr, mem_waddr)
node _fp_data_hazard_mem_T_8 = and(io.fpu.dec.wen, _fp_data_hazard_mem_T_7)
node _fp_data_hazard_mem_T_9 = or(_fp_data_hazard_mem_T_2, _fp_data_hazard_mem_T_4)
node _fp_data_hazard_mem_T_10 = or(_fp_data_hazard_mem_T_9, _fp_data_hazard_mem_T_6)
node _fp_data_hazard_mem_T_11 = or(_fp_data_hazard_mem_T_10, _fp_data_hazard_mem_T_8)
node fp_data_hazard_mem = and(_fp_data_hazard_mem_T, _fp_data_hazard_mem_T_11)
node _id_mem_hazard_T = and(data_hazard_mem, mem_cannot_bypass)
node _id_mem_hazard_T_1 = or(_id_mem_hazard_T, fp_data_hazard_mem)
node id_mem_hazard = and(mem_reg_valid, _id_mem_hazard_T_1)
node _id_load_use_T = and(mem_reg_valid, data_hazard_mem)
node _id_load_use_T_1 = and(_id_load_use_T, mem_ctrl.mem)
connect id_load_use, _id_load_use_T_1
node _id_vconfig_hazard_T = and(ex_reg_valid, ex_reg_set_vconfig)
node _id_vconfig_hazard_T_1 = and(mem_reg_valid, mem_reg_set_vconfig)
node _id_vconfig_hazard_T_2 = or(_id_vconfig_hazard_T, _id_vconfig_hazard_T_1)
node _id_vconfig_hazard_T_3 = and(wb_reg_valid, wb_reg_set_vconfig)
node _id_vconfig_hazard_T_4 = or(_id_vconfig_hazard_T_2, _id_vconfig_hazard_T_3)
node id_vconfig_hazard = and(id_ctrl.vec, _id_vconfig_hazard_T_4)
node _data_hazard_wb_T = eq(id_raddr1, wb_waddr)
node _data_hazard_wb_T_1 = and(hazard_targets_0_1, _data_hazard_wb_T)
node _data_hazard_wb_T_2 = eq(id_raddr2, wb_waddr)
node _data_hazard_wb_T_3 = and(hazard_targets_1_1, _data_hazard_wb_T_2)
node _data_hazard_wb_T_4 = eq(id_waddr, wb_waddr)
node _data_hazard_wb_T_5 = and(hazard_targets_2_1, _data_hazard_wb_T_4)
node _data_hazard_wb_T_6 = or(_data_hazard_wb_T_1, _data_hazard_wb_T_3)
node _data_hazard_wb_T_7 = or(_data_hazard_wb_T_6, _data_hazard_wb_T_5)
node data_hazard_wb = and(wb_ctrl.wxd, _data_hazard_wb_T_7)
node _fp_data_hazard_wb_T = and(id_ctrl.fp, wb_ctrl.wfd)
node _fp_data_hazard_wb_T_1 = eq(id_raddr1, wb_waddr)
node _fp_data_hazard_wb_T_2 = and(io.fpu.dec.ren1, _fp_data_hazard_wb_T_1)
node _fp_data_hazard_wb_T_3 = eq(id_raddr2, wb_waddr)
node _fp_data_hazard_wb_T_4 = and(io.fpu.dec.ren2, _fp_data_hazard_wb_T_3)
node _fp_data_hazard_wb_T_5 = eq(id_raddr3, wb_waddr)
node _fp_data_hazard_wb_T_6 = and(io.fpu.dec.ren3, _fp_data_hazard_wb_T_5)
node _fp_data_hazard_wb_T_7 = eq(id_waddr, wb_waddr)
node _fp_data_hazard_wb_T_8 = and(io.fpu.dec.wen, _fp_data_hazard_wb_T_7)
node _fp_data_hazard_wb_T_9 = or(_fp_data_hazard_wb_T_2, _fp_data_hazard_wb_T_4)
node _fp_data_hazard_wb_T_10 = or(_fp_data_hazard_wb_T_9, _fp_data_hazard_wb_T_6)
node _fp_data_hazard_wb_T_11 = or(_fp_data_hazard_wb_T_10, _fp_data_hazard_wb_T_8)
node fp_data_hazard_wb = and(_fp_data_hazard_wb_T, _fp_data_hazard_wb_T_11)
node _id_wb_hazard_T = and(data_hazard_wb, wb_set_sboard)
node _id_wb_hazard_T_1 = or(_id_wb_hazard_T, fp_data_hazard_wb)
node id_wb_hazard = and(wb_reg_valid, _id_wb_hazard_T_1)
regreset _id_stall_fpu_r : UInt<32>, clock, reset, UInt<32>(0h0)
node _id_stall_fpu_T = or(wb_dcache_miss, wb_ctrl.vec)
node _id_stall_fpu_T_1 = and(_id_stall_fpu_T, wb_ctrl.wfd)
node _id_stall_fpu_T_2 = or(_id_stall_fpu_T_1, io.fpu.sboard_set)
node _id_stall_fpu_T_3 = and(_id_stall_fpu_T_2, wb_valid)
node _id_stall_fpu_T_4 = dshl(UInt<1>(0h1), wb_waddr)
node _id_stall_fpu_T_5 = mux(_id_stall_fpu_T_3, _id_stall_fpu_T_4, UInt<1>(0h0))
node _id_stall_fpu_T_6 = or(_id_stall_fpu_r, _id_stall_fpu_T_5)
node _id_stall_fpu_T_7 = or(UInt<1>(0h0), _id_stall_fpu_T_3)
when _id_stall_fpu_T_7 :
connect _id_stall_fpu_r, _id_stall_fpu_T_6
node _id_stall_fpu_T_8 = and(dmem_resp_replay, dmem_resp_fpu)
node _id_stall_fpu_T_9 = or(_id_stall_fpu_T_8, UInt<1>(0h0))
node _id_stall_fpu_T_10 = dshl(UInt<1>(0h1), io.fpu.ll_resp_tag)
node _id_stall_fpu_T_11 = mux(_id_stall_fpu_T_9, _id_stall_fpu_T_10, UInt<1>(0h0))
node _id_stall_fpu_T_12 = not(_id_stall_fpu_T_11)
node _id_stall_fpu_T_13 = and(_id_stall_fpu_T_6, _id_stall_fpu_T_12)
node _id_stall_fpu_T_14 = or(_id_stall_fpu_T_7, _id_stall_fpu_T_9)
when _id_stall_fpu_T_14 :
connect _id_stall_fpu_r, _id_stall_fpu_T_13
node _id_stall_fpu_T_15 = dshl(UInt<1>(0h1), io.fpu.sboard_clra)
node _id_stall_fpu_T_16 = mux(io.fpu.sboard_clr, _id_stall_fpu_T_15, UInt<1>(0h0))
node _id_stall_fpu_T_17 = not(_id_stall_fpu_T_16)
node _id_stall_fpu_T_18 = and(_id_stall_fpu_T_13, _id_stall_fpu_T_17)
node _id_stall_fpu_T_19 = or(_id_stall_fpu_T_14, io.fpu.sboard_clr)
when _id_stall_fpu_T_19 :
connect _id_stall_fpu_r, _id_stall_fpu_T_18
node _id_stall_fpu_T_20 = dshr(_id_stall_fpu_r, id_raddr1)
node _id_stall_fpu_T_21 = bits(_id_stall_fpu_T_20, 0, 0)
node _id_stall_fpu_T_22 = and(io.fpu.dec.ren1, _id_stall_fpu_T_21)
node _id_stall_fpu_T_23 = dshr(_id_stall_fpu_r, id_raddr2)
node _id_stall_fpu_T_24 = bits(_id_stall_fpu_T_23, 0, 0)
node _id_stall_fpu_T_25 = and(io.fpu.dec.ren2, _id_stall_fpu_T_24)
node _id_stall_fpu_T_26 = dshr(_id_stall_fpu_r, id_raddr3)
node _id_stall_fpu_T_27 = bits(_id_stall_fpu_T_26, 0, 0)
node _id_stall_fpu_T_28 = and(io.fpu.dec.ren3, _id_stall_fpu_T_27)
node _id_stall_fpu_T_29 = dshr(_id_stall_fpu_r, id_waddr)
node _id_stall_fpu_T_30 = bits(_id_stall_fpu_T_29, 0, 0)
node _id_stall_fpu_T_31 = and(io.fpu.dec.wen, _id_stall_fpu_T_30)
node _id_stall_fpu_T_32 = or(_id_stall_fpu_T_22, _id_stall_fpu_T_25)
node _id_stall_fpu_T_33 = or(_id_stall_fpu_T_32, _id_stall_fpu_T_28)
node id_stall_fpu = or(_id_stall_fpu_T_33, _id_stall_fpu_T_31)
reg dcache_blocked_blocked : UInt<1>, clock
node _dcache_blocked_blocked_T = eq(io.dmem.req.ready, UInt<1>(0h0))
node _dcache_blocked_blocked_T_1 = and(_dcache_blocked_blocked_T, io.dmem.clock_enabled)
node _dcache_blocked_blocked_T_2 = eq(io.dmem.perf.grant, UInt<1>(0h0))
node _dcache_blocked_blocked_T_3 = and(_dcache_blocked_blocked_T_1, _dcache_blocked_blocked_T_2)
node _dcache_blocked_blocked_T_4 = or(dcache_blocked_blocked, io.dmem.req.valid)
node _dcache_blocked_blocked_T_5 = or(_dcache_blocked_blocked_T_4, io.dmem.s2_nack)
node _dcache_blocked_blocked_T_6 = and(_dcache_blocked_blocked_T_3, _dcache_blocked_blocked_T_5)
connect dcache_blocked_blocked, _dcache_blocked_blocked_T_6
node _dcache_blocked_T = eq(io.dmem.perf.grant, UInt<1>(0h0))
node dcache_blocked = and(dcache_blocked_blocked, _dcache_blocked_T)
reg rocc_blocked : UInt<1>, clock
node _rocc_blocked_T = eq(wb_xcpt, UInt<1>(0h0))
node _rocc_blocked_T_1 = eq(io.rocc.cmd.ready, UInt<1>(0h0))
node _rocc_blocked_T_2 = and(_rocc_blocked_T, _rocc_blocked_T_1)
node _rocc_blocked_T_3 = or(io.rocc.cmd.valid, rocc_blocked)
node _rocc_blocked_T_4 = and(_rocc_blocked_T_2, _rocc_blocked_T_3)
connect rocc_blocked, _rocc_blocked_T_4
node _ctrl_stalld_T = or(id_ex_hazard, id_mem_hazard)
node _ctrl_stalld_T_1 = or(_ctrl_stalld_T, id_wb_hazard)
node _ctrl_stalld_T_2 = or(_ctrl_stalld_T_1, id_sboard_hazard)
node _ctrl_stalld_T_3 = or(_ctrl_stalld_T_2, id_vconfig_hazard)
node _ctrl_stalld_T_4 = or(ex_reg_valid, mem_reg_valid)
node _ctrl_stalld_T_5 = or(_ctrl_stalld_T_4, wb_reg_valid)
node _ctrl_stalld_T_6 = and(csr.io.singleStep, _ctrl_stalld_T_5)
node _ctrl_stalld_T_7 = or(_ctrl_stalld_T_3, _ctrl_stalld_T_6)
node _ctrl_stalld_T_8 = and(id_csr_en, csr.io.decode[0].fp_csr)
node _ctrl_stalld_T_9 = eq(io.fpu.fcsr_rdy, UInt<1>(0h0))
node _ctrl_stalld_T_10 = and(_ctrl_stalld_T_8, _ctrl_stalld_T_9)
node _ctrl_stalld_T_11 = or(_ctrl_stalld_T_7, _ctrl_stalld_T_10)
node _ctrl_stalld_T_12 = and(id_csr_en, csr.io.decode[0].vector_csr)
node _ctrl_stalld_T_13 = and(_ctrl_stalld_T_12, UInt<1>(0h0))
node _ctrl_stalld_T_14 = or(_ctrl_stalld_T_11, _ctrl_stalld_T_13)
node _ctrl_stalld_T_15 = and(id_ctrl.fp, id_stall_fpu)
node _ctrl_stalld_T_16 = or(_ctrl_stalld_T_14, _ctrl_stalld_T_15)
node _ctrl_stalld_T_17 = and(id_ctrl.mem, dcache_blocked)
node _ctrl_stalld_T_18 = or(_ctrl_stalld_T_16, _ctrl_stalld_T_17)
node _ctrl_stalld_T_19 = and(id_ctrl.rocc, rocc_blocked)
node _ctrl_stalld_T_20 = or(_ctrl_stalld_T_18, _ctrl_stalld_T_19)
node _ctrl_stalld_T_21 = eq(wb_wxd, UInt<1>(0h0))
node _ctrl_stalld_T_22 = and(div.io.resp.valid, _ctrl_stalld_T_21)
node _ctrl_stalld_T_23 = or(div.io.req.ready, _ctrl_stalld_T_22)
node _ctrl_stalld_T_24 = eq(_ctrl_stalld_T_23, UInt<1>(0h0))
node _ctrl_stalld_T_25 = or(_ctrl_stalld_T_24, div.io.req.valid)
node _ctrl_stalld_T_26 = and(id_ctrl.div, _ctrl_stalld_T_25)
node _ctrl_stalld_T_27 = or(_ctrl_stalld_T_20, _ctrl_stalld_T_26)
node _ctrl_stalld_T_28 = eq(clock_en, UInt<1>(0h0))
node _ctrl_stalld_T_29 = or(_ctrl_stalld_T_27, _ctrl_stalld_T_28)
node _ctrl_stalld_T_30 = or(_ctrl_stalld_T_29, id_do_fence)
node _ctrl_stalld_T_31 = or(_ctrl_stalld_T_30, csr.io.csr_stall)
node _ctrl_stalld_T_32 = or(_ctrl_stalld_T_31, id_reg_pause)
node ctrl_stalld = or(_ctrl_stalld_T_32, io.traceStall)
node _ctrl_killd_T = eq(ibuf.io.inst[0].valid, UInt<1>(0h0))
node _ctrl_killd_T_1 = or(_ctrl_killd_T, ibuf.io.inst[0].bits.replay)
node _ctrl_killd_T_2 = or(_ctrl_killd_T_1, take_pc_mem_wb)
node _ctrl_killd_T_3 = or(_ctrl_killd_T_2, ctrl_stalld)
node _ctrl_killd_T_4 = or(_ctrl_killd_T_3, csr.io.interrupt)
connect ctrl_killd, _ctrl_killd_T_4
connect io.imem.req.valid, take_pc_mem_wb
node _io_imem_req_bits_speculative_T = eq(take_pc_wb, UInt<1>(0h0))
connect io.imem.req.bits.speculative, _io_imem_req_bits_speculative_T
node _io_imem_req_bits_pc_T = or(wb_xcpt, csr.io.eret)
node _io_imem_req_bits_pc_T_1 = mux(replay_wb, wb_reg_pc, mem_npc)
node _io_imem_req_bits_pc_T_2 = mux(_io_imem_req_bits_pc_T, csr.io.evec, _io_imem_req_bits_pc_T_1)
connect io.imem.req.bits.pc, _io_imem_req_bits_pc_T_2
node _io_imem_flush_icache_T = and(wb_reg_valid, wb_ctrl.fence_i)
node _io_imem_flush_icache_T_1 = eq(io.dmem.s2_nack, UInt<1>(0h0))
node _io_imem_flush_icache_T_2 = and(_io_imem_flush_icache_T, _io_imem_flush_icache_T_1)
connect io.imem.flush_icache, _io_imem_flush_icache_T_2
node _io_imem_might_request_imem_might_request_reg_T = or(ex_pc_valid, mem_pc_valid)
node _io_imem_might_request_imem_might_request_reg_T_1 = bits(io.ptw.customCSRs.csrs[0].value, 1, 1)
node _io_imem_might_request_imem_might_request_reg_T_2 = or(_io_imem_might_request_imem_might_request_reg_T, _io_imem_might_request_imem_might_request_reg_T_1)
node _io_imem_might_request_imem_might_request_reg_T_3 = or(_io_imem_might_request_imem_might_request_reg_T_2, UInt<1>(0h0))
connect imem_might_request_reg, _io_imem_might_request_imem_might_request_reg_T_3
connect io.imem.might_request, imem_might_request_reg
node _io_imem_progress_T = eq(replay_wb_common, UInt<1>(0h0))
node _io_imem_progress_T_1 = and(wb_reg_valid, _io_imem_progress_T)
reg io_imem_progress_REG : UInt<1>, clock
connect io_imem_progress_REG, _io_imem_progress_T_1
connect io.imem.progress, io_imem_progress_REG
node _io_imem_sfence_valid_T = and(wb_reg_valid, wb_reg_sfence)
connect io.imem.sfence.valid, _io_imem_sfence_valid_T
node _io_imem_sfence_bits_rs1_T = bits(wb_reg_mem_size, 0, 0)
connect io.imem.sfence.bits.rs1, _io_imem_sfence_bits_rs1_T
node _io_imem_sfence_bits_rs2_T = bits(wb_reg_mem_size, 1, 1)
connect io.imem.sfence.bits.rs2, _io_imem_sfence_bits_rs2_T
connect io.imem.sfence.bits.addr, wb_reg_wdata
connect io.imem.sfence.bits.asid, wb_reg_rs2
connect io.imem.sfence.bits.hv, wb_reg_hfence_v
connect io.imem.sfence.bits.hg, wb_reg_hfence_g
connect io.ptw.sfence.bits.hg, io.imem.sfence.bits.hg
connect io.ptw.sfence.bits.hv, io.imem.sfence.bits.hv
connect io.ptw.sfence.bits.asid, io.imem.sfence.bits.asid
connect io.ptw.sfence.bits.addr, io.imem.sfence.bits.addr
connect io.ptw.sfence.bits.rs2, io.imem.sfence.bits.rs2
connect io.ptw.sfence.bits.rs1, io.imem.sfence.bits.rs1
connect io.ptw.sfence.valid, io.imem.sfence.valid
node _ibuf_io_inst_0_ready_T = eq(ctrl_stalld, UInt<1>(0h0))
connect ibuf.io.inst[0].ready, _ibuf_io_inst_0_ready_T
node _io_imem_btb_update_valid_T = eq(take_pc_wb, UInt<1>(0h0))
node _io_imem_btb_update_valid_T_1 = and(mem_reg_valid, _io_imem_btb_update_valid_T)
node _io_imem_btb_update_valid_T_2 = and(_io_imem_btb_update_valid_T_1, mem_wrong_npc)
node _io_imem_btb_update_valid_T_3 = eq(mem_cfi, UInt<1>(0h0))
node _io_imem_btb_update_valid_T_4 = or(_io_imem_btb_update_valid_T_3, mem_cfi_taken)
node _io_imem_btb_update_valid_T_5 = and(_io_imem_btb_update_valid_T_2, _io_imem_btb_update_valid_T_4)
connect io.imem.btb_update.valid, _io_imem_btb_update_valid_T_5
connect io.imem.btb_update.bits.isValid, mem_cfi
node _io_imem_btb_update_bits_cfiType_T = or(mem_ctrl.jal, mem_ctrl.jalr)
node _io_imem_btb_update_bits_cfiType_T_1 = bits(mem_waddr, 0, 0)
node _io_imem_btb_update_bits_cfiType_T_2 = and(_io_imem_btb_update_bits_cfiType_T, _io_imem_btb_update_bits_cfiType_T_1)
node _io_imem_btb_update_bits_cfiType_T_3 = bits(mem_reg_inst, 19, 15)
node _io_imem_btb_update_bits_cfiType_T_4 = and(_io_imem_btb_update_bits_cfiType_T_3, UInt<5>(0h1f))
node _io_imem_btb_update_bits_cfiType_T_5 = and(_io_imem_btb_update_bits_cfiType_T_4, UInt<5>(0h1b))
node _io_imem_btb_update_bits_cfiType_T_6 = eq(UInt<1>(0h1), _io_imem_btb_update_bits_cfiType_T_5)
node _io_imem_btb_update_bits_cfiType_T_7 = and(mem_ctrl.jalr, _io_imem_btb_update_bits_cfiType_T_6)
node _io_imem_btb_update_bits_cfiType_T_8 = or(mem_ctrl.jal, mem_ctrl.jalr)
node _io_imem_btb_update_bits_cfiType_T_9 = mux(_io_imem_btb_update_bits_cfiType_T_8, UInt<1>(0h1), UInt<1>(0h0))
node _io_imem_btb_update_bits_cfiType_T_10 = mux(_io_imem_btb_update_bits_cfiType_T_7, UInt<2>(0h3), _io_imem_btb_update_bits_cfiType_T_9)
node _io_imem_btb_update_bits_cfiType_T_11 = mux(_io_imem_btb_update_bits_cfiType_T_2, UInt<2>(0h2), _io_imem_btb_update_bits_cfiType_T_10)
connect io.imem.btb_update.bits.cfiType, _io_imem_btb_update_bits_cfiType_T_11
connect io.imem.btb_update.bits.target, io.imem.req.bits.pc
node _io_imem_btb_update_bits_br_pc_T = mux(mem_reg_rvc, UInt<1>(0h0), UInt<2>(0h2))
node _io_imem_btb_update_bits_br_pc_T_1 = add(mem_reg_pc, _io_imem_btb_update_bits_br_pc_T)
node _io_imem_btb_update_bits_br_pc_T_2 = tail(_io_imem_btb_update_bits_br_pc_T_1, 1)
connect io.imem.btb_update.bits.br_pc, _io_imem_btb_update_bits_br_pc_T_2
node _io_imem_btb_update_bits_pc_T = not(io.imem.btb_update.bits.br_pc)
node _io_imem_btb_update_bits_pc_T_1 = or(_io_imem_btb_update_bits_pc_T, UInt<2>(0h3))
node _io_imem_btb_update_bits_pc_T_2 = not(_io_imem_btb_update_bits_pc_T_1)
connect io.imem.btb_update.bits.pc, _io_imem_btb_update_bits_pc_T_2
connect io.imem.btb_update.bits.prediction, mem_reg_btb_resp
invalidate io.imem.btb_update.bits.taken
node _io_imem_bht_update_valid_T = eq(take_pc_wb, UInt<1>(0h0))
node _io_imem_bht_update_valid_T_1 = and(mem_reg_valid, _io_imem_bht_update_valid_T)
connect io.imem.bht_update.valid, _io_imem_bht_update_valid_T_1
connect io.imem.bht_update.bits.pc, io.imem.btb_update.bits.pc
connect io.imem.bht_update.bits.taken, mem_br_taken
connect io.imem.bht_update.bits.mispredict, mem_wrong_npc
connect io.imem.bht_update.bits.branch, mem_ctrl.branch
connect io.imem.bht_update.bits.prediction, mem_reg_btb_resp.bht
invalidate io.imem.ras_update.bits.returnAddr
invalidate io.imem.ras_update.bits.cfiType
invalidate io.imem.ras_update.valid
node _io_fpu_valid_T = eq(ctrl_killd, UInt<1>(0h0))
node _io_fpu_valid_T_1 = and(_io_fpu_valid_T, id_ctrl.fp)
connect io.fpu.valid, _io_fpu_valid_T_1
connect io.fpu.killx, ctrl_killx
connect io.fpu.killm, killm_common
connect io.fpu.inst, ibuf.io.inst[0].bits.inst.bits
connect io.fpu.fromint_data, ex_rs_0
node _io_fpu_ll_resp_val_T = and(dmem_resp_valid, dmem_resp_fpu)
connect io.fpu.ll_resp_val, _io_fpu_ll_resp_val_T
connect io.fpu.ll_resp_data, io.dmem.resp.bits.data
connect io.fpu.ll_resp_type, io.dmem.resp.bits.size
connect io.fpu.ll_resp_tag, dmem_resp_waddr
node _io_fpu_keep_clock_enabled_T = bits(io.ptw.customCSRs.csrs[0].value, 2, 2)
connect io.fpu.keep_clock_enabled, _io_fpu_keep_clock_enabled_T
connect io.fpu.v_sew, UInt<1>(0h0)
node _io_dmem_req_valid_T = and(ex_reg_valid, ex_ctrl.mem)
connect io.dmem.req.valid, _io_dmem_req_valid_T
node ex_dcache_tag = cat(ex_waddr, ex_ctrl.fp)
connect io.dmem.req.bits.tag, ex_dcache_tag
connect io.dmem.req.bits.cmd, ex_ctrl.mem_cmd
connect io.dmem.req.bits.size, ex_reg_mem_size
node _io_dmem_req_bits_signed_T = bits(ex_reg_inst, 20, 20)
node _io_dmem_req_bits_signed_T_1 = bits(ex_reg_inst, 14, 14)
node _io_dmem_req_bits_signed_T_2 = mux(ex_reg_hls, _io_dmem_req_bits_signed_T, _io_dmem_req_bits_signed_T_1)
node _io_dmem_req_bits_signed_T_3 = eq(_io_dmem_req_bits_signed_T_2, UInt<1>(0h0))
connect io.dmem.req.bits.signed, _io_dmem_req_bits_signed_T_3
connect io.dmem.req.bits.phys, UInt<1>(0h0)
node _io_dmem_req_bits_addr_a_T = shr(ex_rs_0, 39)
node io_dmem_req_bits_addr_a = asSInt(_io_dmem_req_bits_addr_a_T)
node _io_dmem_req_bits_addr_msb_T = eq(io_dmem_req_bits_addr_a, asSInt(UInt<1>(0h0)))
node _io_dmem_req_bits_addr_msb_T_1 = eq(io_dmem_req_bits_addr_a, asSInt(UInt<1>(0h1)))
node _io_dmem_req_bits_addr_msb_T_2 = or(_io_dmem_req_bits_addr_msb_T, _io_dmem_req_bits_addr_msb_T_1)
node _io_dmem_req_bits_addr_msb_T_3 = bits(alu.io.adder_out, 39, 39)
node _io_dmem_req_bits_addr_msb_T_4 = bits(alu.io.adder_out, 38, 38)
node _io_dmem_req_bits_addr_msb_T_5 = eq(_io_dmem_req_bits_addr_msb_T_4, UInt<1>(0h0))
node io_dmem_req_bits_addr_msb = mux(_io_dmem_req_bits_addr_msb_T_2, _io_dmem_req_bits_addr_msb_T_3, _io_dmem_req_bits_addr_msb_T_5)
node _io_dmem_req_bits_addr_T = bits(alu.io.adder_out, 38, 0)
node _io_dmem_req_bits_addr_T_1 = cat(io_dmem_req_bits_addr_msb, _io_dmem_req_bits_addr_T)
connect io.dmem.req.bits.addr, _io_dmem_req_bits_addr_T_1
node _io_dmem_req_bits_dprv_T = mux(ex_reg_hls, csr.io.hstatus.spvp, csr.io.status.dprv)
connect io.dmem.req.bits.dprv, _io_dmem_req_bits_dprv_T
node _io_dmem_req_bits_dv_T = or(ex_reg_hls, csr.io.status.dv)
connect io.dmem.req.bits.dv, _io_dmem_req_bits_dv_T
node _io_dmem_req_bits_no_resp_T = eq(ex_ctrl.mem_cmd, UInt<1>(0h0))
node _io_dmem_req_bits_no_resp_T_1 = eq(ex_ctrl.mem_cmd, UInt<5>(0h10))
node _io_dmem_req_bits_no_resp_T_2 = eq(ex_ctrl.mem_cmd, UInt<3>(0h6))
node _io_dmem_req_bits_no_resp_T_3 = eq(ex_ctrl.mem_cmd, UInt<3>(0h7))
node _io_dmem_req_bits_no_resp_T_4 = or(_io_dmem_req_bits_no_resp_T, _io_dmem_req_bits_no_resp_T_1)
node _io_dmem_req_bits_no_resp_T_5 = or(_io_dmem_req_bits_no_resp_T_4, _io_dmem_req_bits_no_resp_T_2)
node _io_dmem_req_bits_no_resp_T_6 = or(_io_dmem_req_bits_no_resp_T_5, _io_dmem_req_bits_no_resp_T_3)
node _io_dmem_req_bits_no_resp_T_7 = eq(ex_ctrl.mem_cmd, UInt<3>(0h4))
node _io_dmem_req_bits_no_resp_T_8 = eq(ex_ctrl.mem_cmd, UInt<4>(0h9))
node _io_dmem_req_bits_no_resp_T_9 = eq(ex_ctrl.mem_cmd, UInt<4>(0ha))
node _io_dmem_req_bits_no_resp_T_10 = eq(ex_ctrl.mem_cmd, UInt<4>(0hb))
node _io_dmem_req_bits_no_resp_T_11 = or(_io_dmem_req_bits_no_resp_T_7, _io_dmem_req_bits_no_resp_T_8)
node _io_dmem_req_bits_no_resp_T_12 = or(_io_dmem_req_bits_no_resp_T_11, _io_dmem_req_bits_no_resp_T_9)
node _io_dmem_req_bits_no_resp_T_13 = or(_io_dmem_req_bits_no_resp_T_12, _io_dmem_req_bits_no_resp_T_10)
node _io_dmem_req_bits_no_resp_T_14 = eq(ex_ctrl.mem_cmd, UInt<4>(0h8))
node _io_dmem_req_bits_no_resp_T_15 = eq(ex_ctrl.mem_cmd, UInt<4>(0hc))
node _io_dmem_req_bits_no_resp_T_16 = eq(ex_ctrl.mem_cmd, UInt<4>(0hd))
node _io_dmem_req_bits_no_resp_T_17 = eq(ex_ctrl.mem_cmd, UInt<4>(0he))
node _io_dmem_req_bits_no_resp_T_18 = eq(ex_ctrl.mem_cmd, UInt<4>(0hf))
node _io_dmem_req_bits_no_resp_T_19 = or(_io_dmem_req_bits_no_resp_T_14, _io_dmem_req_bits_no_resp_T_15)
node _io_dmem_req_bits_no_resp_T_20 = or(_io_dmem_req_bits_no_resp_T_19, _io_dmem_req_bits_no_resp_T_16)
node _io_dmem_req_bits_no_resp_T_21 = or(_io_dmem_req_bits_no_resp_T_20, _io_dmem_req_bits_no_resp_T_17)
node _io_dmem_req_bits_no_resp_T_22 = or(_io_dmem_req_bits_no_resp_T_21, _io_dmem_req_bits_no_resp_T_18)
node _io_dmem_req_bits_no_resp_T_23 = or(_io_dmem_req_bits_no_resp_T_13, _io_dmem_req_bits_no_resp_T_22)
node _io_dmem_req_bits_no_resp_T_24 = or(_io_dmem_req_bits_no_resp_T_6, _io_dmem_req_bits_no_resp_T_23)
node _io_dmem_req_bits_no_resp_T_25 = eq(_io_dmem_req_bits_no_resp_T_24, UInt<1>(0h0))
node _io_dmem_req_bits_no_resp_T_26 = eq(ex_ctrl.fp, UInt<1>(0h0))
node _io_dmem_req_bits_no_resp_T_27 = eq(ex_waddr, UInt<1>(0h0))
node _io_dmem_req_bits_no_resp_T_28 = and(_io_dmem_req_bits_no_resp_T_26, _io_dmem_req_bits_no_resp_T_27)
node _io_dmem_req_bits_no_resp_T_29 = or(_io_dmem_req_bits_no_resp_T_25, _io_dmem_req_bits_no_resp_T_28)
connect io.dmem.req.bits.no_resp, _io_dmem_req_bits_no_resp_T_29
invalidate io.dmem.req.bits.no_alloc
invalidate io.dmem.req.bits.no_xcpt
invalidate io.dmem.req.bits.data
invalidate io.dmem.req.bits.mask
node _io_dmem_s1_data_data_T = mux(mem_ctrl.fp, io.fpu.store_data, mem_reg_rs2)
connect io.dmem.s1_data.data, _io_dmem_s1_data_data_T
invalidate io.dmem.s1_data.mask
node _io_dmem_s1_kill_T = or(killm_common, mem_ldst_xcpt)
node _io_dmem_s1_kill_T_1 = or(_io_dmem_s1_kill_T, fpu_kill_mem)
node _io_dmem_s1_kill_T_2 = or(_io_dmem_s1_kill_T_1, vec_kill_mem)
connect io.dmem.s1_kill, _io_dmem_s1_kill_T_2
connect io.dmem.s2_kill, UInt<1>(0h0)
node _io_dmem_keep_clock_enabled_T = and(ibuf.io.inst[0].valid, id_ctrl.mem)
node _io_dmem_keep_clock_enabled_T_1 = eq(csr.io.csr_stall, UInt<1>(0h0))
node _io_dmem_keep_clock_enabled_T_2 = and(_io_dmem_keep_clock_enabled_T, _io_dmem_keep_clock_enabled_T_1)
connect io.dmem.keep_clock_enabled, _io_dmem_keep_clock_enabled_T_2
node _io_rocc_cmd_valid_T = and(wb_reg_valid, wb_ctrl.rocc)
node _io_rocc_cmd_valid_T_1 = eq(replay_wb_common, UInt<1>(0h0))
node _io_rocc_cmd_valid_T_2 = and(_io_rocc_cmd_valid_T, _io_rocc_cmd_valid_T_1)
connect io.rocc.cmd.valid, _io_rocc_cmd_valid_T_2
node _io_rocc_exception_T = orr(csr.io.status.xs)
node _io_rocc_exception_T_1 = and(wb_xcpt, _io_rocc_exception_T)
connect io.rocc.exception, _io_rocc_exception_T_1
connect io.rocc.cmd.bits.status, csr.io.status
wire _io_rocc_cmd_bits_inst_WIRE : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}
wire _io_rocc_cmd_bits_inst_WIRE_1 : UInt<32>
connect _io_rocc_cmd_bits_inst_WIRE_1, wb_reg_inst
node _io_rocc_cmd_bits_inst_T = bits(_io_rocc_cmd_bits_inst_WIRE_1, 6, 0)
connect _io_rocc_cmd_bits_inst_WIRE.opcode, _io_rocc_cmd_bits_inst_T
node _io_rocc_cmd_bits_inst_T_1 = bits(_io_rocc_cmd_bits_inst_WIRE_1, 11, 7)
connect _io_rocc_cmd_bits_inst_WIRE.rd, _io_rocc_cmd_bits_inst_T_1
node _io_rocc_cmd_bits_inst_T_2 = bits(_io_rocc_cmd_bits_inst_WIRE_1, 12, 12)
connect _io_rocc_cmd_bits_inst_WIRE.xs2, _io_rocc_cmd_bits_inst_T_2
node _io_rocc_cmd_bits_inst_T_3 = bits(_io_rocc_cmd_bits_inst_WIRE_1, 13, 13)
connect _io_rocc_cmd_bits_inst_WIRE.xs1, _io_rocc_cmd_bits_inst_T_3
node _io_rocc_cmd_bits_inst_T_4 = bits(_io_rocc_cmd_bits_inst_WIRE_1, 14, 14)
connect _io_rocc_cmd_bits_inst_WIRE.xd, _io_rocc_cmd_bits_inst_T_4
node _io_rocc_cmd_bits_inst_T_5 = bits(_io_rocc_cmd_bits_inst_WIRE_1, 19, 15)
connect _io_rocc_cmd_bits_inst_WIRE.rs1, _io_rocc_cmd_bits_inst_T_5
node _io_rocc_cmd_bits_inst_T_6 = bits(_io_rocc_cmd_bits_inst_WIRE_1, 24, 20)
connect _io_rocc_cmd_bits_inst_WIRE.rs2, _io_rocc_cmd_bits_inst_T_6
node _io_rocc_cmd_bits_inst_T_7 = bits(_io_rocc_cmd_bits_inst_WIRE_1, 31, 25)
connect _io_rocc_cmd_bits_inst_WIRE.funct, _io_rocc_cmd_bits_inst_T_7
connect io.rocc.cmd.bits.inst, _io_rocc_cmd_bits_inst_WIRE
connect io.rocc.cmd.bits.rs1, wb_reg_wdata
connect io.rocc.cmd.bits.rs2, wb_reg_rs2
node _unpause_T = bits(csr.io.time, 4, 0)
node _unpause_T_1 = eq(_unpause_T, UInt<1>(0h0))
node _unpause_T_2 = or(_unpause_T_1, csr.io.inhibit_cycle)
node _unpause_T_3 = or(_unpause_T_2, io.dmem.perf.release)
node unpause = or(_unpause_T_3, take_pc_mem_wb)
when unpause :
connect id_reg_pause, UInt<1>(0h0)
node _io_cease_T = eq(clock_en_reg, UInt<1>(0h0))
node _io_cease_T_1 = and(csr.io.status.cease, _io_cease_T)
connect io.cease, _io_cease_T_1
connect io.wfi, csr.io.status.wfi
reg icache_blocked_REG : UInt<1>, clock
connect icache_blocked_REG, io.imem.resp.valid
node _icache_blocked_T = or(io.imem.resp.valid, icache_blocked_REG)
node icache_blocked = eq(_icache_blocked_T, UInt<1>(0h0))
wire coreMonitorBundle : { clock : Clock, reset : UInt<1>, excpt : UInt<1>, priv_mode : UInt<3>, hartid : UInt<64>, timer : UInt<32>, valid : UInt<1>, pc : UInt<64>, wrdst : UInt<5>, wrdata : UInt<64>, wrenx : UInt<1>, wrenf : UInt<1>, rd0src : UInt<5>, rd0val : UInt<64>, rd1src : UInt<5>, rd1val : UInt<64>, inst : UInt<32>}
connect coreMonitorBundle.clock, clock
connect coreMonitorBundle.reset, reset
connect coreMonitorBundle.hartid, io.hartid
node _coreMonitorBundle_timer_T = bits(csr.io.time, 31, 0)
connect coreMonitorBundle.timer, _coreMonitorBundle_timer_T
node _coreMonitorBundle_valid_T = eq(csr.io.trace[0].exception, UInt<1>(0h0))
node _coreMonitorBundle_valid_T_1 = and(csr.io.trace[0].valid, _coreMonitorBundle_valid_T)
connect coreMonitorBundle.valid, _coreMonitorBundle_valid_T_1
node _coreMonitorBundle_pc_T = bits(csr.io.trace[0].iaddr, 39, 0)
node _coreMonitorBundle_pc_T_1 = bits(_coreMonitorBundle_pc_T, 39, 39)
node _coreMonitorBundle_pc_T_2 = mux(_coreMonitorBundle_pc_T_1, UInt<24>(0hffffff), UInt<24>(0h0))
node _coreMonitorBundle_pc_T_3 = cat(_coreMonitorBundle_pc_T_2, _coreMonitorBundle_pc_T)
connect coreMonitorBundle.pc, _coreMonitorBundle_pc_T_3
node _coreMonitorBundle_wrenx_T = eq(wb_set_sboard, UInt<1>(0h0))
node _coreMonitorBundle_wrenx_T_1 = and(wb_wen, _coreMonitorBundle_wrenx_T)
connect coreMonitorBundle.wrenx, _coreMonitorBundle_wrenx_T_1
connect coreMonitorBundle.wrenf, UInt<1>(0h0)
connect coreMonitorBundle.wrdst, wb_waddr
connect coreMonitorBundle.wrdata, rf_wdata
node _coreMonitorBundle_rd0src_T = bits(wb_reg_inst, 19, 15)
connect coreMonitorBundle.rd0src, _coreMonitorBundle_rd0src_T
reg coreMonitorBundle_rd0val_REG : UInt, clock
connect coreMonitorBundle_rd0val_REG, ex_rs_0
reg coreMonitorBundle_rd0val_REG_1 : UInt, clock
connect coreMonitorBundle_rd0val_REG_1, coreMonitorBundle_rd0val_REG
connect coreMonitorBundle.rd0val, coreMonitorBundle_rd0val_REG_1
node _coreMonitorBundle_rd1src_T = bits(wb_reg_inst, 24, 20)
connect coreMonitorBundle.rd1src, _coreMonitorBundle_rd1src_T
reg coreMonitorBundle_rd1val_REG : UInt, clock
connect coreMonitorBundle_rd1val_REG, ex_rs_1
reg coreMonitorBundle_rd1val_REG_1 : UInt, clock
connect coreMonitorBundle_rd1val_REG_1, coreMonitorBundle_rd1val_REG
connect coreMonitorBundle.rd1val, coreMonitorBundle_rd1val_REG_1
connect coreMonitorBundle.inst, csr.io.trace[0].insn
connect coreMonitorBundle.excpt, csr.io.trace[0].exception
connect coreMonitorBundle.priv_mode, csr.io.trace[0].priv
when csr.io.trace[0].valid :
node _T_164 = or(wb_ctrl.wxd, wb_ctrl.wfd)
node _T_165 = mux(_T_164, coreMonitorBundle.wrdst, UInt<1>(0h0))
node _T_166 = mux(coreMonitorBundle.wrenx, coreMonitorBundle.wrdata, UInt<1>(0h0))
node _T_167 = or(wb_ctrl.rxs1, wb_ctrl.rfs1)
node _T_168 = mux(_T_167, coreMonitorBundle.rd0src, UInt<1>(0h0))
node _T_169 = or(wb_ctrl.rxs1, wb_ctrl.rfs1)
node _T_170 = mux(_T_169, coreMonitorBundle.rd0val, UInt<1>(0h0))
node _T_171 = or(wb_ctrl.rxs2, wb_ctrl.rfs2)
node _T_172 = mux(_T_171, coreMonitorBundle.rd1src, UInt<1>(0h0))
node _T_173 = or(wb_ctrl.rxs2, wb_ctrl.rfs2)
node _T_174 = mux(_T_173, coreMonitorBundle.rd1val, UInt<1>(0h0))
node _T_175 = asUInt(reset)
node _T_176 = eq(_T_175, UInt<1>(0h0))
when _T_176 :
printf(clock, UInt<1>(0h1), "C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n", io.hartid, coreMonitorBundle.timer, coreMonitorBundle.valid, coreMonitorBundle.pc, _T_165, _T_166, coreMonitorBundle.wrenx, _T_168, _T_170, _T_172, _T_174, coreMonitorBundle.inst, coreMonitorBundle.inst) : printf_1
wire xrfWriteBundle : { clock : Clock, reset : UInt<1>, excpt : UInt<1>, priv_mode : UInt<3>, hartid : UInt<64>, timer : UInt<32>, valid : UInt<1>, pc : UInt<64>, wrdst : UInt<5>, wrdata : UInt<64>, wrenx : UInt<1>, wrenf : UInt<1>, rd0src : UInt<5>, rd0val : UInt<64>, rd1src : UInt<5>, rd1val : UInt<64>, inst : UInt<32>}
connect xrfWriteBundle.clock, clock
connect xrfWriteBundle.reset, reset
connect xrfWriteBundle.hartid, io.hartid
node _xrfWriteBundle_timer_T = bits(csr.io.time, 31, 0)
connect xrfWriteBundle.timer, _xrfWriteBundle_timer_T
connect xrfWriteBundle.valid, UInt<1>(0h0)
connect xrfWriteBundle.pc, UInt<1>(0h0)
connect xrfWriteBundle.wrdst, rf_waddr
node _xrfWriteBundle_wrenx_T = and(csr.io.trace[0].valid, wb_wen)
node _xrfWriteBundle_wrenx_T_1 = eq(wb_waddr, rf_waddr)
node _xrfWriteBundle_wrenx_T_2 = and(_xrfWriteBundle_wrenx_T, _xrfWriteBundle_wrenx_T_1)
node _xrfWriteBundle_wrenx_T_3 = eq(_xrfWriteBundle_wrenx_T_2, UInt<1>(0h0))
node _xrfWriteBundle_wrenx_T_4 = and(rf_wen, _xrfWriteBundle_wrenx_T_3)
connect xrfWriteBundle.wrenx, _xrfWriteBundle_wrenx_T_4
connect xrfWriteBundle.wrenf, UInt<1>(0h0)
connect xrfWriteBundle.wrdata, rf_wdata
connect xrfWriteBundle.rd0src, UInt<1>(0h0)
connect xrfWriteBundle.rd0val, UInt<1>(0h0)
connect xrfWriteBundle.rd1src, UInt<1>(0h0)
connect xrfWriteBundle.rd1val, UInt<1>(0h0)
connect xrfWriteBundle.inst, UInt<1>(0h0)
connect xrfWriteBundle.excpt, UInt<1>(0h0)
connect xrfWriteBundle.priv_mode, csr.io.trace[0].priv
inst PlusArgTimeout of PlusArgTimeout
connect PlusArgTimeout.clock, clock
connect PlusArgTimeout.reset, reset
connect PlusArgTimeout.io.count, csr.io.time | module Rocket( // @[RocketCore.scala:153:7]
input clock, // @[RocketCore.scala:153:7]
input reset, // @[RocketCore.scala:153:7]
input io_hartid, // @[RocketCore.scala:134:14]
input io_interrupts_debug, // @[RocketCore.scala:134:14]
input io_interrupts_mtip, // @[RocketCore.scala:134:14]
input io_interrupts_msip, // @[RocketCore.scala:134:14]
input io_interrupts_meip, // @[RocketCore.scala:134:14]
input io_interrupts_seip, // @[RocketCore.scala:134:14]
output io_imem_might_request, // @[RocketCore.scala:134:14]
output io_imem_req_valid, // @[RocketCore.scala:134:14]
output [39:0] io_imem_req_bits_pc, // @[RocketCore.scala:134:14]
output io_imem_req_bits_speculative, // @[RocketCore.scala:134:14]
output io_imem_sfence_valid, // @[RocketCore.scala:134:14]
output io_imem_sfence_bits_rs1, // @[RocketCore.scala:134:14]
output io_imem_sfence_bits_rs2, // @[RocketCore.scala:134:14]
output [38:0] io_imem_sfence_bits_addr, // @[RocketCore.scala:134:14]
output io_imem_sfence_bits_asid, // @[RocketCore.scala:134:14]
output io_imem_sfence_bits_hv, // @[RocketCore.scala:134:14]
output io_imem_sfence_bits_hg, // @[RocketCore.scala:134:14]
output io_imem_resp_ready, // @[RocketCore.scala:134:14]
input io_imem_resp_valid, // @[RocketCore.scala:134:14]
input [1:0] io_imem_resp_bits_btb_cfiType, // @[RocketCore.scala:134:14]
input io_imem_resp_bits_btb_taken, // @[RocketCore.scala:134:14]
input [1:0] io_imem_resp_bits_btb_mask, // @[RocketCore.scala:134:14]
input io_imem_resp_bits_btb_bridx, // @[RocketCore.scala:134:14]
input [38:0] io_imem_resp_bits_btb_target, // @[RocketCore.scala:134:14]
input [4:0] io_imem_resp_bits_btb_entry, // @[RocketCore.scala:134:14]
input [7:0] io_imem_resp_bits_btb_bht_history, // @[RocketCore.scala:134:14]
input io_imem_resp_bits_btb_bht_value, // @[RocketCore.scala:134:14]
input [39:0] io_imem_resp_bits_pc, // @[RocketCore.scala:134:14]
input [31:0] io_imem_resp_bits_data, // @[RocketCore.scala:134:14]
input [1:0] io_imem_resp_bits_mask, // @[RocketCore.scala:134:14]
input io_imem_resp_bits_xcpt_pf_inst, // @[RocketCore.scala:134:14]
input io_imem_resp_bits_xcpt_gf_inst, // @[RocketCore.scala:134:14]
input io_imem_resp_bits_xcpt_ae_inst, // @[RocketCore.scala:134:14]
input io_imem_resp_bits_replay, // @[RocketCore.scala:134:14]
input io_imem_gpa_valid, // @[RocketCore.scala:134:14]
input [39:0] io_imem_gpa_bits, // @[RocketCore.scala:134:14]
input io_imem_gpa_is_pte, // @[RocketCore.scala:134:14]
output io_imem_btb_update_valid, // @[RocketCore.scala:134:14]
output [1:0] io_imem_btb_update_bits_prediction_cfiType, // @[RocketCore.scala:134:14]
output io_imem_btb_update_bits_prediction_taken, // @[RocketCore.scala:134:14]
output [1:0] io_imem_btb_update_bits_prediction_mask, // @[RocketCore.scala:134:14]
output io_imem_btb_update_bits_prediction_bridx, // @[RocketCore.scala:134:14]
output [38:0] io_imem_btb_update_bits_prediction_target, // @[RocketCore.scala:134:14]
output [4:0] io_imem_btb_update_bits_prediction_entry, // @[RocketCore.scala:134:14]
output [7:0] io_imem_btb_update_bits_prediction_bht_history, // @[RocketCore.scala:134:14]
output io_imem_btb_update_bits_prediction_bht_value, // @[RocketCore.scala:134:14]
output [38:0] io_imem_btb_update_bits_pc, // @[RocketCore.scala:134:14]
output [38:0] io_imem_btb_update_bits_target, // @[RocketCore.scala:134:14]
output io_imem_btb_update_bits_isValid, // @[RocketCore.scala:134:14]
output [38:0] io_imem_btb_update_bits_br_pc, // @[RocketCore.scala:134:14]
output [1:0] io_imem_btb_update_bits_cfiType, // @[RocketCore.scala:134:14]
output io_imem_bht_update_valid, // @[RocketCore.scala:134:14]
output [7:0] io_imem_bht_update_bits_prediction_history, // @[RocketCore.scala:134:14]
output io_imem_bht_update_bits_prediction_value, // @[RocketCore.scala:134:14]
output [38:0] io_imem_bht_update_bits_pc, // @[RocketCore.scala:134:14]
output io_imem_bht_update_bits_branch, // @[RocketCore.scala:134:14]
output io_imem_bht_update_bits_taken, // @[RocketCore.scala:134:14]
output io_imem_bht_update_bits_mispredict, // @[RocketCore.scala:134:14]
output io_imem_flush_icache, // @[RocketCore.scala:134:14]
input [39:0] io_imem_npc, // @[RocketCore.scala:134:14]
input io_imem_perf_acquire, // @[RocketCore.scala:134:14]
input io_imem_perf_tlbMiss, // @[RocketCore.scala:134:14]
output io_imem_progress, // @[RocketCore.scala:134:14]
input io_dmem_req_ready, // @[RocketCore.scala:134:14]
output io_dmem_req_valid, // @[RocketCore.scala:134:14]
output [39:0] io_dmem_req_bits_addr, // @[RocketCore.scala:134:14]
output [6:0] io_dmem_req_bits_tag, // @[RocketCore.scala:134:14]
output [4:0] io_dmem_req_bits_cmd, // @[RocketCore.scala:134:14]
output [1:0] io_dmem_req_bits_size, // @[RocketCore.scala:134:14]
output io_dmem_req_bits_signed, // @[RocketCore.scala:134:14]
output [1:0] io_dmem_req_bits_dprv, // @[RocketCore.scala:134:14]
output io_dmem_req_bits_dv, // @[RocketCore.scala:134:14]
output io_dmem_req_bits_no_resp, // @[RocketCore.scala:134:14]
output io_dmem_s1_kill, // @[RocketCore.scala:134:14]
output [63:0] io_dmem_s1_data_data, // @[RocketCore.scala:134:14]
input io_dmem_s2_nack, // @[RocketCore.scala:134:14]
input io_dmem_s2_nack_cause_raw, // @[RocketCore.scala:134:14]
input io_dmem_s2_uncached, // @[RocketCore.scala:134:14]
input [31:0] io_dmem_s2_paddr, // @[RocketCore.scala:134:14]
input io_dmem_resp_valid, // @[RocketCore.scala:134:14]
input [39:0] io_dmem_resp_bits_addr, // @[RocketCore.scala:134:14]
input [6:0] io_dmem_resp_bits_tag, // @[RocketCore.scala:134:14]
input [4:0] io_dmem_resp_bits_cmd, // @[RocketCore.scala:134:14]
input [1:0] io_dmem_resp_bits_size, // @[RocketCore.scala:134:14]
input io_dmem_resp_bits_signed, // @[RocketCore.scala:134:14]
input [1:0] io_dmem_resp_bits_dprv, // @[RocketCore.scala:134:14]
input io_dmem_resp_bits_dv, // @[RocketCore.scala:134:14]
input [63:0] io_dmem_resp_bits_data, // @[RocketCore.scala:134:14]
input [7:0] io_dmem_resp_bits_mask, // @[RocketCore.scala:134:14]
input io_dmem_resp_bits_replay, // @[RocketCore.scala:134:14]
input io_dmem_resp_bits_has_data, // @[RocketCore.scala:134:14]
input [63:0] io_dmem_resp_bits_data_word_bypass, // @[RocketCore.scala:134:14]
input [63:0] io_dmem_resp_bits_data_raw, // @[RocketCore.scala:134:14]
input [63:0] io_dmem_resp_bits_store_data, // @[RocketCore.scala:134:14]
input io_dmem_replay_next, // @[RocketCore.scala:134:14]
input io_dmem_s2_xcpt_ma_ld, // @[RocketCore.scala:134:14]
input io_dmem_s2_xcpt_ma_st, // @[RocketCore.scala:134:14]
input io_dmem_s2_xcpt_pf_ld, // @[RocketCore.scala:134:14]
input io_dmem_s2_xcpt_pf_st, // @[RocketCore.scala:134:14]
input io_dmem_s2_xcpt_ae_ld, // @[RocketCore.scala:134:14]
input io_dmem_s2_xcpt_ae_st, // @[RocketCore.scala:134:14]
input [39:0] io_dmem_s2_gpa, // @[RocketCore.scala:134:14]
input io_dmem_ordered, // @[RocketCore.scala:134:14]
input io_dmem_store_pending, // @[RocketCore.scala:134:14]
input io_dmem_perf_acquire, // @[RocketCore.scala:134:14]
input io_dmem_perf_release, // @[RocketCore.scala:134:14]
input io_dmem_perf_grant, // @[RocketCore.scala:134:14]
input io_dmem_perf_tlbMiss, // @[RocketCore.scala:134:14]
input io_dmem_perf_blocked, // @[RocketCore.scala:134:14]
input io_dmem_perf_canAcceptStoreThenLoad, // @[RocketCore.scala:134:14]
input io_dmem_perf_canAcceptStoreThenRMW, // @[RocketCore.scala:134:14]
input io_dmem_perf_canAcceptLoadThenLoad, // @[RocketCore.scala:134:14]
input io_dmem_perf_storeBufferEmptyAfterLoad, // @[RocketCore.scala:134:14]
input io_dmem_perf_storeBufferEmptyAfterStore, // @[RocketCore.scala:134:14]
output io_dmem_keep_clock_enabled, // @[RocketCore.scala:134:14]
output [3:0] io_ptw_ptbr_mode, // @[RocketCore.scala:134:14]
output [43:0] io_ptw_ptbr_ppn, // @[RocketCore.scala:134:14]
output io_ptw_sfence_valid, // @[RocketCore.scala:134:14]
output io_ptw_sfence_bits_rs1, // @[RocketCore.scala:134:14]
output io_ptw_sfence_bits_rs2, // @[RocketCore.scala:134:14]
output [38:0] io_ptw_sfence_bits_addr, // @[RocketCore.scala:134:14]
output io_ptw_sfence_bits_asid, // @[RocketCore.scala:134:14]
output io_ptw_sfence_bits_hv, // @[RocketCore.scala:134:14]
output io_ptw_sfence_bits_hg, // @[RocketCore.scala:134:14]
output io_ptw_status_debug, // @[RocketCore.scala:134:14]
output io_ptw_status_cease, // @[RocketCore.scala:134:14]
output io_ptw_status_wfi, // @[RocketCore.scala:134:14]
output [31:0] io_ptw_status_isa, // @[RocketCore.scala:134:14]
output [1:0] io_ptw_status_dprv, // @[RocketCore.scala:134:14]
output io_ptw_status_dv, // @[RocketCore.scala:134:14]
output [1:0] io_ptw_status_prv, // @[RocketCore.scala:134:14]
output io_ptw_status_v, // @[RocketCore.scala:134:14]
output io_ptw_status_sd, // @[RocketCore.scala:134:14]
output io_ptw_status_mpv, // @[RocketCore.scala:134:14]
output io_ptw_status_gva, // @[RocketCore.scala:134:14]
output io_ptw_status_tsr, // @[RocketCore.scala:134:14]
output io_ptw_status_tw, // @[RocketCore.scala:134:14]
output io_ptw_status_tvm, // @[RocketCore.scala:134:14]
output io_ptw_status_mxr, // @[RocketCore.scala:134:14]
output io_ptw_status_sum, // @[RocketCore.scala:134:14]
output io_ptw_status_mprv, // @[RocketCore.scala:134:14]
output [1:0] io_ptw_status_fs, // @[RocketCore.scala:134:14]
output [1:0] io_ptw_status_mpp, // @[RocketCore.scala:134:14]
output io_ptw_status_spp, // @[RocketCore.scala:134:14]
output io_ptw_status_mpie, // @[RocketCore.scala:134:14]
output io_ptw_status_spie, // @[RocketCore.scala:134:14]
output io_ptw_status_mie, // @[RocketCore.scala:134:14]
output io_ptw_status_sie, // @[RocketCore.scala:134:14]
output io_ptw_hstatus_spvp, // @[RocketCore.scala:134:14]
output io_ptw_hstatus_spv, // @[RocketCore.scala:134:14]
output io_ptw_hstatus_gva, // @[RocketCore.scala:134:14]
output io_ptw_gstatus_debug, // @[RocketCore.scala:134:14]
output io_ptw_gstatus_cease, // @[RocketCore.scala:134:14]
output io_ptw_gstatus_wfi, // @[RocketCore.scala:134:14]
output [31:0] io_ptw_gstatus_isa, // @[RocketCore.scala:134:14]
output [1:0] io_ptw_gstatus_dprv, // @[RocketCore.scala:134:14]
output io_ptw_gstatus_dv, // @[RocketCore.scala:134:14]
output [1:0] io_ptw_gstatus_prv, // @[RocketCore.scala:134:14]
output io_ptw_gstatus_v, // @[RocketCore.scala:134:14]
output io_ptw_gstatus_sd, // @[RocketCore.scala:134:14]
output [22:0] io_ptw_gstatus_zero2, // @[RocketCore.scala:134:14]
output io_ptw_gstatus_mpv, // @[RocketCore.scala:134:14]
output io_ptw_gstatus_gva, // @[RocketCore.scala:134:14]
output io_ptw_gstatus_mbe, // @[RocketCore.scala:134:14]
output io_ptw_gstatus_sbe, // @[RocketCore.scala:134:14]
output [1:0] io_ptw_gstatus_sxl, // @[RocketCore.scala:134:14]
output [7:0] io_ptw_gstatus_zero1, // @[RocketCore.scala:134:14]
output io_ptw_gstatus_tsr, // @[RocketCore.scala:134:14]
output io_ptw_gstatus_tw, // @[RocketCore.scala:134:14]
output io_ptw_gstatus_tvm, // @[RocketCore.scala:134:14]
output io_ptw_gstatus_mxr, // @[RocketCore.scala:134:14]
output io_ptw_gstatus_sum, // @[RocketCore.scala:134:14]
output io_ptw_gstatus_mprv, // @[RocketCore.scala:134:14]
output [1:0] io_ptw_gstatus_fs, // @[RocketCore.scala:134:14]
output [1:0] io_ptw_gstatus_mpp, // @[RocketCore.scala:134:14]
output [1:0] io_ptw_gstatus_vs, // @[RocketCore.scala:134:14]
output io_ptw_gstatus_spp, // @[RocketCore.scala:134:14]
output io_ptw_gstatus_mpie, // @[RocketCore.scala:134:14]
output io_ptw_gstatus_ube, // @[RocketCore.scala:134:14]
output io_ptw_gstatus_spie, // @[RocketCore.scala:134:14]
output io_ptw_gstatus_upie, // @[RocketCore.scala:134:14]
output io_ptw_gstatus_mie, // @[RocketCore.scala:134:14]
output io_ptw_gstatus_hie, // @[RocketCore.scala:134:14]
output io_ptw_gstatus_sie, // @[RocketCore.scala:134:14]
output io_ptw_gstatus_uie, // @[RocketCore.scala:134:14]
output io_ptw_pmp_0_cfg_l, // @[RocketCore.scala:134:14]
output [1:0] io_ptw_pmp_0_cfg_a, // @[RocketCore.scala:134:14]
output io_ptw_pmp_0_cfg_x, // @[RocketCore.scala:134:14]
output io_ptw_pmp_0_cfg_w, // @[RocketCore.scala:134:14]
output io_ptw_pmp_0_cfg_r, // @[RocketCore.scala:134:14]
output [29:0] io_ptw_pmp_0_addr, // @[RocketCore.scala:134:14]
output [31:0] io_ptw_pmp_0_mask, // @[RocketCore.scala:134:14]
output io_ptw_pmp_1_cfg_l, // @[RocketCore.scala:134:14]
output [1:0] io_ptw_pmp_1_cfg_a, // @[RocketCore.scala:134:14]
output io_ptw_pmp_1_cfg_x, // @[RocketCore.scala:134:14]
output io_ptw_pmp_1_cfg_w, // @[RocketCore.scala:134:14]
output io_ptw_pmp_1_cfg_r, // @[RocketCore.scala:134:14]
output [29:0] io_ptw_pmp_1_addr, // @[RocketCore.scala:134:14]
output [31:0] io_ptw_pmp_1_mask, // @[RocketCore.scala:134:14]
output io_ptw_pmp_2_cfg_l, // @[RocketCore.scala:134:14]
output [1:0] io_ptw_pmp_2_cfg_a, // @[RocketCore.scala:134:14]
output io_ptw_pmp_2_cfg_x, // @[RocketCore.scala:134:14]
output io_ptw_pmp_2_cfg_w, // @[RocketCore.scala:134:14]
output io_ptw_pmp_2_cfg_r, // @[RocketCore.scala:134:14]
output [29:0] io_ptw_pmp_2_addr, // @[RocketCore.scala:134:14]
output [31:0] io_ptw_pmp_2_mask, // @[RocketCore.scala:134:14]
output io_ptw_pmp_3_cfg_l, // @[RocketCore.scala:134:14]
output [1:0] io_ptw_pmp_3_cfg_a, // @[RocketCore.scala:134:14]
output io_ptw_pmp_3_cfg_x, // @[RocketCore.scala:134:14]
output io_ptw_pmp_3_cfg_w, // @[RocketCore.scala:134:14]
output io_ptw_pmp_3_cfg_r, // @[RocketCore.scala:134:14]
output [29:0] io_ptw_pmp_3_addr, // @[RocketCore.scala:134:14]
output [31:0] io_ptw_pmp_3_mask, // @[RocketCore.scala:134:14]
output io_ptw_pmp_4_cfg_l, // @[RocketCore.scala:134:14]
output [1:0] io_ptw_pmp_4_cfg_a, // @[RocketCore.scala:134:14]
output io_ptw_pmp_4_cfg_x, // @[RocketCore.scala:134:14]
output io_ptw_pmp_4_cfg_w, // @[RocketCore.scala:134:14]
output io_ptw_pmp_4_cfg_r, // @[RocketCore.scala:134:14]
output [29:0] io_ptw_pmp_4_addr, // @[RocketCore.scala:134:14]
output [31:0] io_ptw_pmp_4_mask, // @[RocketCore.scala:134:14]
output io_ptw_pmp_5_cfg_l, // @[RocketCore.scala:134:14]
output [1:0] io_ptw_pmp_5_cfg_a, // @[RocketCore.scala:134:14]
output io_ptw_pmp_5_cfg_x, // @[RocketCore.scala:134:14]
output io_ptw_pmp_5_cfg_w, // @[RocketCore.scala:134:14]
output io_ptw_pmp_5_cfg_r, // @[RocketCore.scala:134:14]
output [29:0] io_ptw_pmp_5_addr, // @[RocketCore.scala:134:14]
output [31:0] io_ptw_pmp_5_mask, // @[RocketCore.scala:134:14]
output io_ptw_pmp_6_cfg_l, // @[RocketCore.scala:134:14]
output [1:0] io_ptw_pmp_6_cfg_a, // @[RocketCore.scala:134:14]
output io_ptw_pmp_6_cfg_x, // @[RocketCore.scala:134:14]
output io_ptw_pmp_6_cfg_w, // @[RocketCore.scala:134:14]
output io_ptw_pmp_6_cfg_r, // @[RocketCore.scala:134:14]
output [29:0] io_ptw_pmp_6_addr, // @[RocketCore.scala:134:14]
output [31:0] io_ptw_pmp_6_mask, // @[RocketCore.scala:134:14]
output io_ptw_pmp_7_cfg_l, // @[RocketCore.scala:134:14]
output [1:0] io_ptw_pmp_7_cfg_a, // @[RocketCore.scala:134:14]
output io_ptw_pmp_7_cfg_x, // @[RocketCore.scala:134:14]
output io_ptw_pmp_7_cfg_w, // @[RocketCore.scala:134:14]
output io_ptw_pmp_7_cfg_r, // @[RocketCore.scala:134:14]
output [29:0] io_ptw_pmp_7_addr, // @[RocketCore.scala:134:14]
output [31:0] io_ptw_pmp_7_mask, // @[RocketCore.scala:134:14]
input io_ptw_perf_pte_miss, // @[RocketCore.scala:134:14]
input io_ptw_perf_pte_hit, // @[RocketCore.scala:134:14]
output io_ptw_customCSRs_csrs_0_ren, // @[RocketCore.scala:134:14]
output io_ptw_customCSRs_csrs_0_wen, // @[RocketCore.scala:134:14]
output [63:0] io_ptw_customCSRs_csrs_0_wdata, // @[RocketCore.scala:134:14]
output [63:0] io_ptw_customCSRs_csrs_0_value, // @[RocketCore.scala:134:14]
output io_ptw_customCSRs_csrs_1_ren, // @[RocketCore.scala:134:14]
output io_ptw_customCSRs_csrs_1_wen, // @[RocketCore.scala:134:14]
output [63:0] io_ptw_customCSRs_csrs_1_wdata, // @[RocketCore.scala:134:14]
output [63:0] io_ptw_customCSRs_csrs_1_value, // @[RocketCore.scala:134:14]
output io_ptw_customCSRs_csrs_2_ren, // @[RocketCore.scala:134:14]
output io_ptw_customCSRs_csrs_2_wen, // @[RocketCore.scala:134:14]
output [63:0] io_ptw_customCSRs_csrs_2_wdata, // @[RocketCore.scala:134:14]
output [63:0] io_ptw_customCSRs_csrs_2_value, // @[RocketCore.scala:134:14]
output io_ptw_customCSRs_csrs_3_ren, // @[RocketCore.scala:134:14]
output io_ptw_customCSRs_csrs_3_wen, // @[RocketCore.scala:134:14]
output [63:0] io_ptw_customCSRs_csrs_3_wdata, // @[RocketCore.scala:134:14]
output [63:0] io_ptw_customCSRs_csrs_3_value, // @[RocketCore.scala:134:14]
input io_ptw_clock_enabled, // @[RocketCore.scala:134:14]
output io_fpu_hartid, // @[RocketCore.scala:134:14]
output [63:0] io_fpu_time, // @[RocketCore.scala:134:14]
output [31:0] io_fpu_inst, // @[RocketCore.scala:134:14]
output [63:0] io_fpu_fromint_data, // @[RocketCore.scala:134:14]
output [2:0] io_fpu_fcsr_rm, // @[RocketCore.scala:134:14]
input io_fpu_fcsr_flags_valid, // @[RocketCore.scala:134:14]
input [4:0] io_fpu_fcsr_flags_bits, // @[RocketCore.scala:134:14]
input [63:0] io_fpu_store_data, // @[RocketCore.scala:134:14]
input [63:0] io_fpu_toint_data, // @[RocketCore.scala:134:14]
output io_fpu_ll_resp_val, // @[RocketCore.scala:134:14]
output [2:0] io_fpu_ll_resp_type, // @[RocketCore.scala:134:14]
output [4:0] io_fpu_ll_resp_tag, // @[RocketCore.scala:134:14]
output [63:0] io_fpu_ll_resp_data, // @[RocketCore.scala:134:14]
output io_fpu_valid, // @[RocketCore.scala:134:14]
input io_fpu_fcsr_rdy, // @[RocketCore.scala:134:14]
input io_fpu_nack_mem, // @[RocketCore.scala:134:14]
input io_fpu_illegal_rm, // @[RocketCore.scala:134:14]
output io_fpu_killx, // @[RocketCore.scala:134:14]
output io_fpu_killm, // @[RocketCore.scala:134:14]
input io_fpu_dec_ldst, // @[RocketCore.scala:134:14]
input io_fpu_dec_wen, // @[RocketCore.scala:134:14]
input io_fpu_dec_ren1, // @[RocketCore.scala:134:14]
input io_fpu_dec_ren2, // @[RocketCore.scala:134:14]
input io_fpu_dec_ren3, // @[RocketCore.scala:134:14]
input io_fpu_dec_swap12, // @[RocketCore.scala:134:14]
input io_fpu_dec_swap23, // @[RocketCore.scala:134:14]
input [1:0] io_fpu_dec_typeTagIn, // @[RocketCore.scala:134:14]
input [1:0] io_fpu_dec_typeTagOut, // @[RocketCore.scala:134:14]
input io_fpu_dec_fromint, // @[RocketCore.scala:134:14]
input io_fpu_dec_toint, // @[RocketCore.scala:134:14]
input io_fpu_dec_fastpipe, // @[RocketCore.scala:134:14]
input io_fpu_dec_fma, // @[RocketCore.scala:134:14]
input io_fpu_dec_div, // @[RocketCore.scala:134:14]
input io_fpu_dec_sqrt, // @[RocketCore.scala:134:14]
input io_fpu_dec_wflags, // @[RocketCore.scala:134:14]
input io_fpu_dec_vec, // @[RocketCore.scala:134:14]
input io_fpu_sboard_set, // @[RocketCore.scala:134:14]
input io_fpu_sboard_clr, // @[RocketCore.scala:134:14]
input [4:0] io_fpu_sboard_clra, // @[RocketCore.scala:134:14]
output io_fpu_keep_clock_enabled, // @[RocketCore.scala:134:14]
output io_trace_insns_0_valid, // @[RocketCore.scala:134:14]
output [39:0] io_trace_insns_0_iaddr, // @[RocketCore.scala:134:14]
output [31:0] io_trace_insns_0_insn, // @[RocketCore.scala:134:14]
output [2:0] io_trace_insns_0_priv, // @[RocketCore.scala:134:14]
output io_trace_insns_0_exception, // @[RocketCore.scala:134:14]
output io_trace_insns_0_interrupt, // @[RocketCore.scala:134:14]
output [63:0] io_trace_insns_0_cause, // @[RocketCore.scala:134:14]
output [39:0] io_trace_insns_0_tval, // @[RocketCore.scala:134:14]
output [63:0] io_trace_time, // @[RocketCore.scala:134:14]
output io_bpwatch_0_valid_0, // @[RocketCore.scala:134:14]
output [2:0] io_bpwatch_0_action, // @[RocketCore.scala:134:14]
output io_wfi // @[RocketCore.scala:134:14]
);
wire ll_arb_io_out_ready; // @[RocketCore.scala:782:23, :809:44, :810:25]
wire id_ctrl_fence; // @[RocketCore.scala:321:21]
wire id_ctrl_rocc; // @[RocketCore.scala:321:21]
wire io_imem_sfence_bits_hg_0; // @[RocketCore.scala:153:7]
wire io_imem_sfence_bits_hv_0; // @[RocketCore.scala:153:7]
wire io_imem_sfence_bits_asid_0; // @[RocketCore.scala:153:7]
wire [38:0] io_imem_sfence_bits_addr_0; // @[RocketCore.scala:153:7]
wire io_imem_sfence_bits_rs2_0; // @[RocketCore.scala:153:7]
wire io_imem_sfence_bits_rs1_0; // @[RocketCore.scala:153:7]
wire io_imem_sfence_valid_0; // @[RocketCore.scala:153:7]
wire [38:0] io_imem_btb_update_bits_pc_0; // @[RocketCore.scala:153:7]
wire _ll_arb_io_in_0_ready; // @[RocketCore.scala:776:22]
wire _ll_arb_io_out_valid; // @[RocketCore.scala:776:22]
wire [4:0] _ll_arb_io_out_bits_tag; // @[RocketCore.scala:776:22]
wire _div_io_req_ready; // @[RocketCore.scala:511:19]
wire _div_io_resp_valid; // @[RocketCore.scala:511:19]
wire [63:0] _div_io_resp_bits_data; // @[RocketCore.scala:511:19]
wire [4:0] _div_io_resp_bits_tag; // @[RocketCore.scala:511:19]
wire [63:0] _alu_io_adder_out; // @[RocketCore.scala:504:19]
wire _alu_io_cmp_out; // @[RocketCore.scala:504:19]
wire _bpu_io_xcpt_if; // @[RocketCore.scala:414:19]
wire _bpu_io_xcpt_ld; // @[RocketCore.scala:414:19]
wire _bpu_io_xcpt_st; // @[RocketCore.scala:414:19]
wire _bpu_io_debug_if; // @[RocketCore.scala:414:19]
wire _bpu_io_debug_ld; // @[RocketCore.scala:414:19]
wire _bpu_io_debug_st; // @[RocketCore.scala:414:19]
wire _bpu_io_bpwatch_0_rvalid_0; // @[RocketCore.scala:414:19]
wire _bpu_io_bpwatch_0_wvalid_0; // @[RocketCore.scala:414:19]
wire _bpu_io_bpwatch_0_ivalid_0; // @[RocketCore.scala:414:19]
wire [63:0] _csr_io_rw_rdata; // @[RocketCore.scala:341:19]
wire _csr_io_decode_0_fp_illegal; // @[RocketCore.scala:341:19]
wire _csr_io_decode_0_fp_csr; // @[RocketCore.scala:341:19]
wire _csr_io_decode_0_read_illegal; // @[RocketCore.scala:341:19]
wire _csr_io_decode_0_write_illegal; // @[RocketCore.scala:341:19]
wire _csr_io_decode_0_write_flush; // @[RocketCore.scala:341:19]
wire _csr_io_decode_0_system_illegal; // @[RocketCore.scala:341:19]
wire _csr_io_decode_0_virtual_access_illegal; // @[RocketCore.scala:341:19]
wire _csr_io_decode_0_virtual_system_illegal; // @[RocketCore.scala:341:19]
wire _csr_io_csr_stall; // @[RocketCore.scala:341:19]
wire _csr_io_eret; // @[RocketCore.scala:341:19]
wire _csr_io_singleStep; // @[RocketCore.scala:341:19]
wire _csr_io_status_debug; // @[RocketCore.scala:341:19]
wire _csr_io_status_cease; // @[RocketCore.scala:341:19]
wire _csr_io_status_wfi; // @[RocketCore.scala:341:19]
wire [31:0] _csr_io_status_isa; // @[RocketCore.scala:341:19]
wire [1:0] _csr_io_status_dprv; // @[RocketCore.scala:341:19]
wire _csr_io_status_dv; // @[RocketCore.scala:341:19]
wire [1:0] _csr_io_status_prv; // @[RocketCore.scala:341:19]
wire _csr_io_status_v; // @[RocketCore.scala:341:19]
wire _csr_io_status_sd; // @[RocketCore.scala:341:19]
wire _csr_io_status_mpv; // @[RocketCore.scala:341:19]
wire _csr_io_status_gva; // @[RocketCore.scala:341:19]
wire _csr_io_status_tsr; // @[RocketCore.scala:341:19]
wire _csr_io_status_tw; // @[RocketCore.scala:341:19]
wire _csr_io_status_tvm; // @[RocketCore.scala:341:19]
wire _csr_io_status_mxr; // @[RocketCore.scala:341:19]
wire _csr_io_status_sum; // @[RocketCore.scala:341:19]
wire _csr_io_status_mprv; // @[RocketCore.scala:341:19]
wire [1:0] _csr_io_status_fs; // @[RocketCore.scala:341:19]
wire [1:0] _csr_io_status_mpp; // @[RocketCore.scala:341:19]
wire _csr_io_status_spp; // @[RocketCore.scala:341:19]
wire _csr_io_status_mpie; // @[RocketCore.scala:341:19]
wire _csr_io_status_spie; // @[RocketCore.scala:341:19]
wire _csr_io_status_mie; // @[RocketCore.scala:341:19]
wire _csr_io_status_sie; // @[RocketCore.scala:341:19]
wire [39:0] _csr_io_evec; // @[RocketCore.scala:341:19]
wire [63:0] _csr_io_time; // @[RocketCore.scala:341:19]
wire _csr_io_interrupt; // @[RocketCore.scala:341:19]
wire [63:0] _csr_io_interrupt_cause; // @[RocketCore.scala:341:19]
wire _csr_io_bp_0_control_dmode; // @[RocketCore.scala:341:19]
wire _csr_io_bp_0_control_action; // @[RocketCore.scala:341:19]
wire [1:0] _csr_io_bp_0_control_tmatch; // @[RocketCore.scala:341:19]
wire _csr_io_bp_0_control_m; // @[RocketCore.scala:341:19]
wire _csr_io_bp_0_control_s; // @[RocketCore.scala:341:19]
wire _csr_io_bp_0_control_u; // @[RocketCore.scala:341:19]
wire _csr_io_bp_0_control_x; // @[RocketCore.scala:341:19]
wire _csr_io_bp_0_control_w; // @[RocketCore.scala:341:19]
wire _csr_io_bp_0_control_r; // @[RocketCore.scala:341:19]
wire [38:0] _csr_io_bp_0_address; // @[RocketCore.scala:341:19]
wire [47:0] _csr_io_bp_0_textra_pad2; // @[RocketCore.scala:341:19]
wire _csr_io_bp_0_textra_pad1; // @[RocketCore.scala:341:19]
wire _csr_io_inhibit_cycle; // @[RocketCore.scala:341:19]
wire _csr_io_trace_0_valid; // @[RocketCore.scala:341:19]
wire [39:0] _csr_io_trace_0_iaddr; // @[RocketCore.scala:341:19]
wire [31:0] _csr_io_trace_0_insn; // @[RocketCore.scala:341:19]
wire [2:0] _csr_io_trace_0_priv; // @[RocketCore.scala:341:19]
wire _csr_io_trace_0_exception; // @[RocketCore.scala:341:19]
wire [39:0] _ibuf_io_pc; // @[RocketCore.scala:311:20]
wire [1:0] _ibuf_io_btb_resp_cfiType; // @[RocketCore.scala:311:20]
wire _ibuf_io_btb_resp_taken; // @[RocketCore.scala:311:20]
wire [1:0] _ibuf_io_btb_resp_mask; // @[RocketCore.scala:311:20]
wire _ibuf_io_btb_resp_bridx; // @[RocketCore.scala:311:20]
wire [38:0] _ibuf_io_btb_resp_target; // @[RocketCore.scala:311:20]
wire [4:0] _ibuf_io_btb_resp_entry; // @[RocketCore.scala:311:20]
wire [7:0] _ibuf_io_btb_resp_bht_history; // @[RocketCore.scala:311:20]
wire _ibuf_io_btb_resp_bht_value; // @[RocketCore.scala:311:20]
wire _ibuf_io_inst_0_valid; // @[RocketCore.scala:311:20]
wire _ibuf_io_inst_0_bits_xcpt0_pf_inst; // @[RocketCore.scala:311:20]
wire _ibuf_io_inst_0_bits_xcpt0_gf_inst; // @[RocketCore.scala:311:20]
wire _ibuf_io_inst_0_bits_xcpt0_ae_inst; // @[RocketCore.scala:311:20]
wire _ibuf_io_inst_0_bits_xcpt1_pf_inst; // @[RocketCore.scala:311:20]
wire _ibuf_io_inst_0_bits_xcpt1_gf_inst; // @[RocketCore.scala:311:20]
wire _ibuf_io_inst_0_bits_xcpt1_ae_inst; // @[RocketCore.scala:311:20]
wire _ibuf_io_inst_0_bits_replay; // @[RocketCore.scala:311:20]
wire _ibuf_io_inst_0_bits_rvc; // @[RocketCore.scala:311:20]
wire [31:0] _ibuf_io_inst_0_bits_inst_bits; // @[RocketCore.scala:311:20]
wire [4:0] _ibuf_io_inst_0_bits_inst_rs1; // @[RocketCore.scala:311:20]
wire [31:0] _ibuf_io_inst_0_bits_raw; // @[RocketCore.scala:311:20]
wire io_hartid_0 = io_hartid; // @[RocketCore.scala:153:7]
wire io_interrupts_debug_0 = io_interrupts_debug; // @[RocketCore.scala:153:7]
wire io_interrupts_mtip_0 = io_interrupts_mtip; // @[RocketCore.scala:153:7]
wire io_interrupts_msip_0 = io_interrupts_msip; // @[RocketCore.scala:153:7]
wire io_interrupts_meip_0 = io_interrupts_meip; // @[RocketCore.scala:153:7]
wire io_interrupts_seip_0 = io_interrupts_seip; // @[RocketCore.scala:153:7]
wire io_imem_resp_valid_0 = io_imem_resp_valid; // @[RocketCore.scala:153:7]
wire [1:0] io_imem_resp_bits_btb_cfiType_0 = io_imem_resp_bits_btb_cfiType; // @[RocketCore.scala:153:7]
wire io_imem_resp_bits_btb_taken_0 = io_imem_resp_bits_btb_taken; // @[RocketCore.scala:153:7]
wire [1:0] io_imem_resp_bits_btb_mask_0 = io_imem_resp_bits_btb_mask; // @[RocketCore.scala:153:7]
wire io_imem_resp_bits_btb_bridx_0 = io_imem_resp_bits_btb_bridx; // @[RocketCore.scala:153:7]
wire [38:0] io_imem_resp_bits_btb_target_0 = io_imem_resp_bits_btb_target; // @[RocketCore.scala:153:7]
wire [4:0] io_imem_resp_bits_btb_entry_0 = io_imem_resp_bits_btb_entry; // @[RocketCore.scala:153:7]
wire [7:0] io_imem_resp_bits_btb_bht_history_0 = io_imem_resp_bits_btb_bht_history; // @[RocketCore.scala:153:7]
wire io_imem_resp_bits_btb_bht_value_0 = io_imem_resp_bits_btb_bht_value; // @[RocketCore.scala:153:7]
wire [39:0] io_imem_resp_bits_pc_0 = io_imem_resp_bits_pc; // @[RocketCore.scala:153:7]
wire [31:0] io_imem_resp_bits_data_0 = io_imem_resp_bits_data; // @[RocketCore.scala:153:7]
wire [1:0] io_imem_resp_bits_mask_0 = io_imem_resp_bits_mask; // @[RocketCore.scala:153:7]
wire io_imem_resp_bits_xcpt_pf_inst_0 = io_imem_resp_bits_xcpt_pf_inst; // @[RocketCore.scala:153:7]
wire io_imem_resp_bits_xcpt_gf_inst_0 = io_imem_resp_bits_xcpt_gf_inst; // @[RocketCore.scala:153:7]
wire io_imem_resp_bits_xcpt_ae_inst_0 = io_imem_resp_bits_xcpt_ae_inst; // @[RocketCore.scala:153:7]
wire io_imem_resp_bits_replay_0 = io_imem_resp_bits_replay; // @[RocketCore.scala:153:7]
wire io_imem_gpa_valid_0 = io_imem_gpa_valid; // @[RocketCore.scala:153:7]
wire [39:0] io_imem_gpa_bits_0 = io_imem_gpa_bits; // @[RocketCore.scala:153:7]
wire io_imem_gpa_is_pte_0 = io_imem_gpa_is_pte; // @[RocketCore.scala:153:7]
wire [39:0] io_imem_npc_0 = io_imem_npc; // @[RocketCore.scala:153:7]
wire io_imem_perf_acquire_0 = io_imem_perf_acquire; // @[RocketCore.scala:153:7]
wire io_imem_perf_tlbMiss_0 = io_imem_perf_tlbMiss; // @[RocketCore.scala:153:7]
wire io_dmem_req_ready_0 = io_dmem_req_ready; // @[RocketCore.scala:153:7]
wire io_dmem_s2_nack_0 = io_dmem_s2_nack; // @[RocketCore.scala:153:7]
wire io_dmem_s2_nack_cause_raw_0 = io_dmem_s2_nack_cause_raw; // @[RocketCore.scala:153:7]
wire io_dmem_s2_uncached_0 = io_dmem_s2_uncached; // @[RocketCore.scala:153:7]
wire [31:0] io_dmem_s2_paddr_0 = io_dmem_s2_paddr; // @[RocketCore.scala:153:7]
wire io_dmem_resp_valid_0 = io_dmem_resp_valid; // @[RocketCore.scala:153:7]
wire [39:0] io_dmem_resp_bits_addr_0 = io_dmem_resp_bits_addr; // @[RocketCore.scala:153:7]
wire [6:0] io_dmem_resp_bits_tag_0 = io_dmem_resp_bits_tag; // @[RocketCore.scala:153:7]
wire [4:0] io_dmem_resp_bits_cmd_0 = io_dmem_resp_bits_cmd; // @[RocketCore.scala:153:7]
wire [1:0] io_dmem_resp_bits_size_0 = io_dmem_resp_bits_size; // @[RocketCore.scala:153:7]
wire io_dmem_resp_bits_signed_0 = io_dmem_resp_bits_signed; // @[RocketCore.scala:153:7]
wire [1:0] io_dmem_resp_bits_dprv_0 = io_dmem_resp_bits_dprv; // @[RocketCore.scala:153:7]
wire io_dmem_resp_bits_dv_0 = io_dmem_resp_bits_dv; // @[RocketCore.scala:153:7]
wire [63:0] io_dmem_resp_bits_data_0 = io_dmem_resp_bits_data; // @[RocketCore.scala:153:7]
wire [7:0] io_dmem_resp_bits_mask_0 = io_dmem_resp_bits_mask; // @[RocketCore.scala:153:7]
wire io_dmem_resp_bits_replay_0 = io_dmem_resp_bits_replay; // @[RocketCore.scala:153:7]
wire io_dmem_resp_bits_has_data_0 = io_dmem_resp_bits_has_data; // @[RocketCore.scala:153:7]
wire [63:0] io_dmem_resp_bits_data_word_bypass_0 = io_dmem_resp_bits_data_word_bypass; // @[RocketCore.scala:153:7]
wire [63:0] io_dmem_resp_bits_data_raw_0 = io_dmem_resp_bits_data_raw; // @[RocketCore.scala:153:7]
wire [63:0] io_dmem_resp_bits_store_data_0 = io_dmem_resp_bits_store_data; // @[RocketCore.scala:153:7]
wire io_dmem_replay_next_0 = io_dmem_replay_next; // @[RocketCore.scala:153:7]
wire io_dmem_s2_xcpt_ma_ld_0 = io_dmem_s2_xcpt_ma_ld; // @[RocketCore.scala:153:7]
wire io_dmem_s2_xcpt_ma_st_0 = io_dmem_s2_xcpt_ma_st; // @[RocketCore.scala:153:7]
wire io_dmem_s2_xcpt_pf_ld_0 = io_dmem_s2_xcpt_pf_ld; // @[RocketCore.scala:153:7]
wire io_dmem_s2_xcpt_pf_st_0 = io_dmem_s2_xcpt_pf_st; // @[RocketCore.scala:153:7]
wire io_dmem_s2_xcpt_ae_ld_0 = io_dmem_s2_xcpt_ae_ld; // @[RocketCore.scala:153:7]
wire io_dmem_s2_xcpt_ae_st_0 = io_dmem_s2_xcpt_ae_st; // @[RocketCore.scala:153:7]
wire [39:0] io_dmem_s2_gpa_0 = io_dmem_s2_gpa; // @[RocketCore.scala:153:7]
wire io_dmem_ordered_0 = io_dmem_ordered; // @[RocketCore.scala:153:7]
wire io_dmem_store_pending_0 = io_dmem_store_pending; // @[RocketCore.scala:153:7]
wire io_dmem_perf_acquire_0 = io_dmem_perf_acquire; // @[RocketCore.scala:153:7]
wire io_dmem_perf_release_0 = io_dmem_perf_release; // @[RocketCore.scala:153:7]
wire io_dmem_perf_grant_0 = io_dmem_perf_grant; // @[RocketCore.scala:153:7]
wire io_dmem_perf_tlbMiss_0 = io_dmem_perf_tlbMiss; // @[RocketCore.scala:153:7]
wire io_dmem_perf_blocked_0 = io_dmem_perf_blocked; // @[RocketCore.scala:153:7]
wire io_dmem_perf_canAcceptStoreThenLoad_0 = io_dmem_perf_canAcceptStoreThenLoad; // @[RocketCore.scala:153:7]
wire io_dmem_perf_canAcceptStoreThenRMW_0 = io_dmem_perf_canAcceptStoreThenRMW; // @[RocketCore.scala:153:7]
wire io_dmem_perf_canAcceptLoadThenLoad_0 = io_dmem_perf_canAcceptLoadThenLoad; // @[RocketCore.scala:153:7]
wire io_dmem_perf_storeBufferEmptyAfterLoad_0 = io_dmem_perf_storeBufferEmptyAfterLoad; // @[RocketCore.scala:153:7]
wire io_dmem_perf_storeBufferEmptyAfterStore_0 = io_dmem_perf_storeBufferEmptyAfterStore; // @[RocketCore.scala:153:7]
wire io_ptw_perf_pte_miss_0 = io_ptw_perf_pte_miss; // @[RocketCore.scala:153:7]
wire io_ptw_perf_pte_hit_0 = io_ptw_perf_pte_hit; // @[RocketCore.scala:153:7]
wire io_ptw_clock_enabled_0 = io_ptw_clock_enabled; // @[RocketCore.scala:153:7]
wire io_fpu_fcsr_flags_valid_0 = io_fpu_fcsr_flags_valid; // @[RocketCore.scala:153:7]
wire [4:0] io_fpu_fcsr_flags_bits_0 = io_fpu_fcsr_flags_bits; // @[RocketCore.scala:153:7]
wire [63:0] io_fpu_store_data_0 = io_fpu_store_data; // @[RocketCore.scala:153:7]
wire [63:0] io_fpu_toint_data_0 = io_fpu_toint_data; // @[RocketCore.scala:153:7]
wire io_fpu_fcsr_rdy_0 = io_fpu_fcsr_rdy; // @[RocketCore.scala:153:7]
wire io_fpu_nack_mem_0 = io_fpu_nack_mem; // @[RocketCore.scala:153:7]
wire io_fpu_illegal_rm_0 = io_fpu_illegal_rm; // @[RocketCore.scala:153:7]
wire io_fpu_dec_ldst_0 = io_fpu_dec_ldst; // @[RocketCore.scala:153:7]
wire io_fpu_dec_wen_0 = io_fpu_dec_wen; // @[RocketCore.scala:153:7]
wire io_fpu_dec_ren1_0 = io_fpu_dec_ren1; // @[RocketCore.scala:153:7]
wire io_fpu_dec_ren2_0 = io_fpu_dec_ren2; // @[RocketCore.scala:153:7]
wire io_fpu_dec_ren3_0 = io_fpu_dec_ren3; // @[RocketCore.scala:153:7]
wire io_fpu_dec_swap12_0 = io_fpu_dec_swap12; // @[RocketCore.scala:153:7]
wire io_fpu_dec_swap23_0 = io_fpu_dec_swap23; // @[RocketCore.scala:153:7]
wire [1:0] io_fpu_dec_typeTagIn_0 = io_fpu_dec_typeTagIn; // @[RocketCore.scala:153:7]
wire [1:0] io_fpu_dec_typeTagOut_0 = io_fpu_dec_typeTagOut; // @[RocketCore.scala:153:7]
wire io_fpu_dec_fromint_0 = io_fpu_dec_fromint; // @[RocketCore.scala:153:7]
wire io_fpu_dec_toint_0 = io_fpu_dec_toint; // @[RocketCore.scala:153:7]
wire io_fpu_dec_fastpipe_0 = io_fpu_dec_fastpipe; // @[RocketCore.scala:153:7]
wire io_fpu_dec_fma_0 = io_fpu_dec_fma; // @[RocketCore.scala:153:7]
wire io_fpu_dec_div_0 = io_fpu_dec_div; // @[RocketCore.scala:153:7]
wire io_fpu_dec_sqrt_0 = io_fpu_dec_sqrt; // @[RocketCore.scala:153:7]
wire io_fpu_dec_wflags_0 = io_fpu_dec_wflags; // @[RocketCore.scala:153:7]
wire io_fpu_dec_vec_0 = io_fpu_dec_vec; // @[RocketCore.scala:153:7]
wire io_fpu_sboard_set_0 = io_fpu_sboard_set; // @[RocketCore.scala:153:7]
wire io_fpu_sboard_clr_0 = io_fpu_sboard_clr; // @[RocketCore.scala:153:7]
wire [4:0] io_fpu_sboard_clra_0 = io_fpu_sboard_clra; // @[RocketCore.scala:153:7]
wire coreMonitorBundle_clock = clock; // @[RocketCore.scala:1186:31]
wire coreMonitorBundle_reset = reset; // @[RocketCore.scala:1186:31]
wire xrfWriteBundle_clock = clock; // @[RocketCore.scala:1249:28]
wire xrfWriteBundle_reset = reset; // @[RocketCore.scala:1249:28]
wire io_imem_clock_enabled = 1'h1; // @[RocketCore.scala:153:7]
wire io_dmem_clock_enabled = 1'h1; // @[RocketCore.scala:153:7]
wire clock_en = 1'h1; // @[RocketCore.scala:153:7, :163:29]
wire _id_npc_b19_12_T = 1'h1; // @[RocketCore.scala:153:7, :1343:26]
wire _id_npc_b11_T_3 = 1'h1; // @[RocketCore.scala:153:7, :1345:23]
wire _id_illegal_insn_T_10 = 1'h1; // @[RocketCore.scala:153:7, :384:73]
wire _id_illegal_insn_T_15 = 1'h1; // @[RocketCore.scala:153:7, :385:55]
wire _mem_br_target_b19_12_T = 1'h1; // @[RocketCore.scala:153:7, :1343:26]
wire _mem_br_target_b19_12_T_1 = 1'h1; // @[RocketCore.scala:153:7, :1343:43]
wire _mem_br_target_b19_12_T_2 = 1'h1; // @[RocketCore.scala:153:7, :1343:36]
wire _mem_br_target_b11_T_6 = 1'h1; // @[RocketCore.scala:153:7, :1346:23]
wire _mem_br_target_b4_1_T_2 = 1'h1; // @[RocketCore.scala:153:7, :1349:41]
wire _mem_br_target_b4_1_T_3 = 1'h1; // @[RocketCore.scala:153:7, :1349:34]
wire _mem_br_target_b19_12_T_5 = 1'h1; // @[RocketCore.scala:153:7, :1343:26]
wire _mem_br_target_b11_T_14 = 1'h1; // @[RocketCore.scala:153:7, :1345:23]
wire _wb_reg_xcpt_T_2 = 1'h1; // @[RocketCore.scala:153:7, :707:45]
wire _replay_wb_rocc_T_1 = 1'h1; // @[RocketCore.scala:153:7, :758:56]
wire _rocc_blocked_T_1 = 1'h1; // @[RocketCore.scala:153:7, :1029:31]
wire io_imem_btb_update_bits_taken = 1'h0; // @[RocketCore.scala:153:7]
wire io_imem_ras_update_valid = 1'h0; // @[RocketCore.scala:153:7]
wire io_dmem_req_bits_phys = 1'h0; // @[RocketCore.scala:153:7]
wire io_dmem_req_bits_no_alloc = 1'h0; // @[RocketCore.scala:153:7]
wire io_dmem_req_bits_no_xcpt = 1'h0; // @[RocketCore.scala:153:7]
wire io_dmem_s2_kill = 1'h0; // @[RocketCore.scala:153:7]
wire io_dmem_s2_xcpt_gf_ld = 1'h0; // @[RocketCore.scala:153:7]
wire io_dmem_s2_xcpt_gf_st = 1'h0; // @[RocketCore.scala:153:7]
wire io_dmem_s2_gpa_is_pte = 1'h0; // @[RocketCore.scala:153:7]
wire io_ptw_status_mbe = 1'h0; // @[RocketCore.scala:153:7]
wire io_ptw_status_sbe = 1'h0; // @[RocketCore.scala:153:7]
wire io_ptw_status_sd_rv32 = 1'h0; // @[RocketCore.scala:153:7]
wire io_ptw_status_ube = 1'h0; // @[RocketCore.scala:153:7]
wire io_ptw_status_upie = 1'h0; // @[RocketCore.scala:153:7]
wire io_ptw_status_hie = 1'h0; // @[RocketCore.scala:153:7]
wire io_ptw_status_uie = 1'h0; // @[RocketCore.scala:153:7]
wire io_ptw_hstatus_vtsr = 1'h0; // @[RocketCore.scala:153:7]
wire io_ptw_hstatus_vtw = 1'h0; // @[RocketCore.scala:153:7]
wire io_ptw_hstatus_vtvm = 1'h0; // @[RocketCore.scala:153:7]
wire io_ptw_hstatus_hu = 1'h0; // @[RocketCore.scala:153:7]
wire io_ptw_hstatus_vsbe = 1'h0; // @[RocketCore.scala:153:7]
wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[RocketCore.scala:153:7]
wire io_ptw_perf_l2miss = 1'h0; // @[RocketCore.scala:153:7]
wire io_ptw_perf_l2hit = 1'h0; // @[RocketCore.scala:153:7]
wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[RocketCore.scala:153:7]
wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[RocketCore.scala:153:7]
wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[RocketCore.scala:153:7]
wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[RocketCore.scala:153:7]
wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[RocketCore.scala:153:7]
wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[RocketCore.scala:153:7]
wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[RocketCore.scala:153:7]
wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_ready = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_bits_status_mbe = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_bits_status_sbe = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_bits_status_sd_rv32 = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_bits_status_ube = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_bits_status_upie = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_bits_status_hie = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_bits_status_uie = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_resp_ready = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_resp_valid = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_req_ready = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_req_valid = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_req_bits_signed = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_req_bits_dv = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_req_bits_phys = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_req_bits_no_resp = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_req_bits_no_alloc = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_req_bits_no_xcpt = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_s1_kill = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_s2_nack = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_s2_nack_cause_raw = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_s2_kill = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_s2_uncached = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_resp_valid = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_resp_bits_signed = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_resp_bits_dv = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_resp_bits_replay = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_resp_bits_has_data = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_replay_next = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_s2_xcpt_ma_ld = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_s2_xcpt_ma_st = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_s2_xcpt_pf_ld = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_s2_xcpt_pf_st = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_s2_xcpt_gf_ld = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_s2_xcpt_gf_st = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_s2_xcpt_ae_ld = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_s2_xcpt_ae_st = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_s2_gpa_is_pte = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_ordered = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_store_pending = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_perf_acquire = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_perf_release = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_perf_grant = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_perf_tlbMiss = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_perf_blocked = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_perf_canAcceptStoreThenLoad = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_perf_canAcceptStoreThenRMW = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_perf_canAcceptLoadThenLoad = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_perf_storeBufferEmptyAfterLoad = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_perf_storeBufferEmptyAfterStore = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_keep_clock_enabled = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_clock_enabled = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_busy = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_interrupt = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_exception = 1'h0; // @[RocketCore.scala:153:7]
wire io_bpwatch_0_rvalid_0 = 1'h0; // @[RocketCore.scala:153:7]
wire io_bpwatch_0_wvalid_0 = 1'h0; // @[RocketCore.scala:153:7]
wire io_bpwatch_0_ivalid_0 = 1'h0; // @[RocketCore.scala:153:7]
wire io_cease = 1'h0; // @[RocketCore.scala:153:7]
wire io_traceStall = 1'h0; // @[RocketCore.scala:153:7]
wire _hits_WIRE_0 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_1 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_2 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_3 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_4 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_5 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_6 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_7 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_8 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_9 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_10 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_11 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_12 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_13 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_14 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_15 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_16 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_17 = 1'h0; // @[Events.scala:13:33]
wire hits_0 = 1'h0; // @[Events.scala:13:25]
wire hits_1 = 1'h0; // @[Events.scala:13:25]
wire hits_2 = 1'h0; // @[Events.scala:13:25]
wire hits_3 = 1'h0; // @[Events.scala:13:25]
wire hits_4 = 1'h0; // @[Events.scala:13:25]
wire hits_5 = 1'h0; // @[Events.scala:13:25]
wire hits_6 = 1'h0; // @[Events.scala:13:25]
wire hits_7 = 1'h0; // @[Events.scala:13:25]
wire hits_8 = 1'h0; // @[Events.scala:13:25]
wire hits_9 = 1'h0; // @[Events.scala:13:25]
wire hits_10 = 1'h0; // @[Events.scala:13:25]
wire hits_11 = 1'h0; // @[Events.scala:13:25]
wire hits_12 = 1'h0; // @[Events.scala:13:25]
wire hits_13 = 1'h0; // @[Events.scala:13:25]
wire hits_14 = 1'h0; // @[Events.scala:13:25]
wire hits_15 = 1'h0; // @[Events.scala:13:25]
wire hits_16 = 1'h0; // @[Events.scala:13:25]
wire hits_17 = 1'h0; // @[Events.scala:13:25]
wire _hits_WIRE_1_0 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_1_1 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_1_2 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_1_3 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_1_4 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_1_5 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_1_6 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_1_7 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_1_8 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_1_9 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_1_10 = 1'h0; // @[Events.scala:13:33]
wire hits_1_0 = 1'h0; // @[Events.scala:13:25]
wire hits_1_1 = 1'h0; // @[Events.scala:13:25]
wire hits_1_2 = 1'h0; // @[Events.scala:13:25]
wire hits_1_3 = 1'h0; // @[Events.scala:13:25]
wire hits_1_4 = 1'h0; // @[Events.scala:13:25]
wire hits_1_5 = 1'h0; // @[Events.scala:13:25]
wire hits_1_6 = 1'h0; // @[Events.scala:13:25]
wire hits_1_7 = 1'h0; // @[Events.scala:13:25]
wire hits_1_8 = 1'h0; // @[Events.scala:13:25]
wire hits_1_9 = 1'h0; // @[Events.scala:13:25]
wire hits_1_10 = 1'h0; // @[Events.scala:13:25]
wire _hits_WIRE_2_0 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_2_1 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_2_2 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_2_3 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_2_4 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_2_5 = 1'h0; // @[Events.scala:13:33]
wire hits_2_0 = 1'h0; // @[Events.scala:13:25]
wire hits_2_1 = 1'h0; // @[Events.scala:13:25]
wire hits_2_2 = 1'h0; // @[Events.scala:13:25]
wire hits_2_3 = 1'h0; // @[Events.scala:13:25]
wire hits_2_4 = 1'h0; // @[Events.scala:13:25]
wire hits_2_5 = 1'h0; // @[Events.scala:13:25]
wire id_ctrl_vec = 1'h0; // @[RocketCore.scala:321:21]
wire _id_rs_T_1 = 1'h0; // @[RocketCore.scala:1326:33]
wire _id_rs_T_6 = 1'h0; // @[RocketCore.scala:1326:33]
wire _id_npc_sign_T = 1'h0; // @[RocketCore.scala:1341:24]
wire _id_npc_b30_20_T = 1'h0; // @[RocketCore.scala:1342:26]
wire _id_npc_b19_12_T_1 = 1'h0; // @[RocketCore.scala:1343:43]
wire _id_npc_b19_12_T_2 = 1'h0; // @[RocketCore.scala:1343:36]
wire _id_npc_b11_T = 1'h0; // @[RocketCore.scala:1344:23]
wire _id_npc_b11_T_1 = 1'h0; // @[RocketCore.scala:1344:40]
wire _id_npc_b11_T_2 = 1'h0; // @[RocketCore.scala:1344:33]
wire _id_npc_b11_T_6 = 1'h0; // @[RocketCore.scala:1346:23]
wire _id_npc_b10_5_T = 1'h0; // @[RocketCore.scala:1347:25]
wire _id_npc_b10_5_T_1 = 1'h0; // @[RocketCore.scala:1347:42]
wire _id_npc_b10_5_T_2 = 1'h0; // @[RocketCore.scala:1347:35]
wire _id_npc_b4_1_T = 1'h0; // @[RocketCore.scala:1348:24]
wire _id_npc_b4_1_T_1 = 1'h0; // @[RocketCore.scala:1349:24]
wire _id_npc_b4_1_T_2 = 1'h0; // @[RocketCore.scala:1349:41]
wire _id_npc_b4_1_T_3 = 1'h0; // @[RocketCore.scala:1349:34]
wire _id_npc_b4_1_T_5 = 1'h0; // @[RocketCore.scala:1350:24]
wire _id_npc_b0_T = 1'h0; // @[RocketCore.scala:1351:22]
wire _id_npc_b0_T_2 = 1'h0; // @[RocketCore.scala:1352:22]
wire _id_npc_b0_T_4 = 1'h0; // @[RocketCore.scala:1353:22]
wire _id_npc_b0_T_6 = 1'h0; // @[RocketCore.scala:1353:17]
wire _id_npc_b0_T_7 = 1'h0; // @[RocketCore.scala:1352:17]
wire id_npc_b0 = 1'h0; // @[RocketCore.scala:1351:17]
wire id_set_vconfig = 1'h0; // @[RocketCore.scala:347:120]
wire _id_illegal_insn_T_16 = 1'h0; // @[RocketCore.scala:385:19]
wire _id_illegal_insn_T_26 = 1'h0; // @[RocketCore.scala:388:23]
wire _id_illegal_insn_T_28 = 1'h0; // @[RocketCore.scala:389:23]
wire _id_illegal_insn_T_30 = 1'h0; // @[RocketCore.scala:390:22]
wire id_rocc_busy = 1'h0; // @[RocketCore.scala:405:34]
wire _id_csr_rocc_write_T = 1'h0; // @[RocketCore.scala:408:87]
wire id_csr_rocc_write = 1'h0; // @[RocketCore.scala:408:100]
wire _id_do_fence_T_1 = 1'h0; // @[RocketCore.scala:410:46]
wire _id_do_fence_T_2 = 1'h0; // @[RocketCore.scala:411:17]
wire _id_do_fence_T_3 = 1'h0; // @[RocketCore.scala:410:86]
wire _ex_reg_hls_T = 1'h0; // @[RocketCore.scala:553:37]
wire _ex_reg_hls_T_6 = 1'h0; // @[RocketCore.scala:553:55]
wire _ex_reg_mem_size_T = 1'h0; // @[RocketCore.scala:554:46]
wire _ex_reg_set_vconfig_T_1 = 1'h0; // @[RocketCore.scala:591:42]
wire _replay_ex_structural_T_5 = 1'h0; // @[RocketCore.scala:599:45]
wire _replay_ex_structural_T_6 = 1'h0; // @[RocketCore.scala:599:42]
wire _mem_br_target_sign_T = 1'h0; // @[RocketCore.scala:1341:24]
wire _mem_br_target_b30_20_T = 1'h0; // @[RocketCore.scala:1342:26]
wire _mem_br_target_b11_T = 1'h0; // @[RocketCore.scala:1344:23]
wire _mem_br_target_b11_T_1 = 1'h0; // @[RocketCore.scala:1344:40]
wire _mem_br_target_b11_T_2 = 1'h0; // @[RocketCore.scala:1344:33]
wire _mem_br_target_b11_T_3 = 1'h0; // @[RocketCore.scala:1345:23]
wire _mem_br_target_b10_5_T = 1'h0; // @[RocketCore.scala:1347:25]
wire _mem_br_target_b10_5_T_1 = 1'h0; // @[RocketCore.scala:1347:42]
wire _mem_br_target_b10_5_T_2 = 1'h0; // @[RocketCore.scala:1347:35]
wire _mem_br_target_b4_1_T = 1'h0; // @[RocketCore.scala:1348:24]
wire _mem_br_target_b4_1_T_1 = 1'h0; // @[RocketCore.scala:1349:24]
wire _mem_br_target_b4_1_T_5 = 1'h0; // @[RocketCore.scala:1350:24]
wire _mem_br_target_b0_T = 1'h0; // @[RocketCore.scala:1351:22]
wire _mem_br_target_b0_T_2 = 1'h0; // @[RocketCore.scala:1352:22]
wire _mem_br_target_b0_T_4 = 1'h0; // @[RocketCore.scala:1353:22]
wire _mem_br_target_b0_T_6 = 1'h0; // @[RocketCore.scala:1353:17]
wire _mem_br_target_b0_T_7 = 1'h0; // @[RocketCore.scala:1352:17]
wire mem_br_target_b0 = 1'h0; // @[RocketCore.scala:1351:17]
wire _mem_br_target_sign_T_3 = 1'h0; // @[RocketCore.scala:1341:24]
wire _mem_br_target_b30_20_T_3 = 1'h0; // @[RocketCore.scala:1342:26]
wire _mem_br_target_b19_12_T_6 = 1'h0; // @[RocketCore.scala:1343:43]
wire _mem_br_target_b19_12_T_7 = 1'h0; // @[RocketCore.scala:1343:36]
wire _mem_br_target_b11_T_11 = 1'h0; // @[RocketCore.scala:1344:23]
wire _mem_br_target_b11_T_12 = 1'h0; // @[RocketCore.scala:1344:40]
wire _mem_br_target_b11_T_13 = 1'h0; // @[RocketCore.scala:1344:33]
wire _mem_br_target_b11_T_17 = 1'h0; // @[RocketCore.scala:1346:23]
wire _mem_br_target_b10_5_T_4 = 1'h0; // @[RocketCore.scala:1347:25]
wire _mem_br_target_b10_5_T_5 = 1'h0; // @[RocketCore.scala:1347:42]
wire _mem_br_target_b10_5_T_6 = 1'h0; // @[RocketCore.scala:1347:35]
wire _mem_br_target_b4_1_T_10 = 1'h0; // @[RocketCore.scala:1348:24]
wire _mem_br_target_b4_1_T_11 = 1'h0; // @[RocketCore.scala:1349:24]
wire _mem_br_target_b4_1_T_12 = 1'h0; // @[RocketCore.scala:1349:41]
wire _mem_br_target_b4_1_T_13 = 1'h0; // @[RocketCore.scala:1349:34]
wire _mem_br_target_b4_1_T_15 = 1'h0; // @[RocketCore.scala:1350:24]
wire _mem_br_target_b0_T_8 = 1'h0; // @[RocketCore.scala:1351:22]
wire _mem_br_target_b0_T_10 = 1'h0; // @[RocketCore.scala:1352:22]
wire _mem_br_target_b0_T_12 = 1'h0; // @[RocketCore.scala:1353:22]
wire _mem_br_target_b0_T_14 = 1'h0; // @[RocketCore.scala:1353:17]
wire _mem_br_target_b0_T_15 = 1'h0; // @[RocketCore.scala:1352:17]
wire mem_br_target_b0_1 = 1'h0; // @[RocketCore.scala:1351:17]
wire vec_kill_mem = 1'h0; // @[RocketCore.scala:697:52]
wire vec_kill_all = 1'h0; // @[RocketCore.scala:698:36]
wire replay_wb_csr = 1'h0; // @[RocketCore.scala:759:42]
wire replay_wb_vec = 1'h0; // @[RocketCore.scala:760:36]
wire _htval_valid_dmem_T_2 = 1'h0; // @[RocketCore.scala:857:83]
wire _htval_valid_dmem_T_3 = 1'h0; // @[RocketCore.scala:857:54]
wire htval_valid_dmem = 1'h0; // @[RocketCore.scala:857:87]
wire _mhtinst_read_pseudo_T_1 = 1'h0; // @[RocketCore.scala:862:98]
wire _id_vconfig_hazard_T = 1'h0; // @[RocketCore.scala:1003:19]
wire id_vconfig_hazard = 1'h0; // @[RocketCore.scala:1002:39]
wire _ctrl_stalld_T_12 = 1'h0; // @[RocketCore.scala:1036:15]
wire _ctrl_stalld_T_13 = 1'h0; // @[RocketCore.scala:1036:46]
wire _ctrl_stalld_T_28 = 1'h0; // @[RocketCore.scala:1041:5]
wire _io_rocc_exception_T = 1'h0; // @[RocketCore.scala:1157:52]
wire _io_rocc_exception_T_1 = 1'h0; // @[RocketCore.scala:1157:32]
wire _io_cease_T = 1'h0; // @[RocketCore.scala:1166:38]
wire _io_cease_T_1 = 1'h0; // @[RocketCore.scala:1166:35]
wire coreMonitorBundle_wrenf = 1'h0; // @[RocketCore.scala:1186:31]
wire xrfWriteBundle_excpt = 1'h0; // @[RocketCore.scala:1249:28]
wire xrfWriteBundle_valid = 1'h0; // @[RocketCore.scala:1249:28]
wire xrfWriteBundle_wrenf = 1'h0; // @[RocketCore.scala:1249:28]
wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[RocketCore.scala:153:7]
wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[RocketCore.scala:153:7]
wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[RocketCore.scala:153:7]
wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[RocketCore.scala:153:7]
wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[RocketCore.scala:153:7]
wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[RocketCore.scala:153:7]
wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[RocketCore.scala:153:7]
wire [22:0] io_ptw_status_zero2 = 23'h0; // @[RocketCore.scala:153:7]
wire [22:0] io_rocc_cmd_bits_status_zero2 = 23'h0; // @[RocketCore.scala:153:7]
wire [7:0] io_dmem_req_bits_mask = 8'h0; // @[RocketCore.scala:153:7]
wire [7:0] io_dmem_s1_data_mask = 8'h0; // @[RocketCore.scala:153:7]
wire [7:0] io_ptw_status_zero1 = 8'h0; // @[RocketCore.scala:153:7]
wire [7:0] io_rocc_cmd_bits_status_zero1 = 8'h0; // @[RocketCore.scala:153:7]
wire [7:0] io_rocc_mem_req_bits_mask = 8'h0; // @[RocketCore.scala:153:7]
wire [7:0] io_rocc_mem_s1_data_mask = 8'h0; // @[RocketCore.scala:153:7]
wire [7:0] io_rocc_mem_resp_bits_mask = 8'h0; // @[RocketCore.scala:153:7]
wire [1:0] io_imem_ras_update_bits_cfiType = 2'h0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_status_xs = 2'h0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_status_vs = 2'h0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[RocketCore.scala:153:7]
wire [1:0] io_rocc_cmd_bits_status_xs = 2'h0; // @[RocketCore.scala:153:7]
wire [1:0] io_rocc_cmd_bits_status_vs = 2'h0; // @[RocketCore.scala:153:7]
wire [1:0] io_rocc_mem_req_bits_size = 2'h0; // @[RocketCore.scala:153:7]
wire [1:0] io_rocc_mem_req_bits_dprv = 2'h0; // @[RocketCore.scala:153:7]
wire [1:0] io_rocc_mem_resp_bits_size = 2'h0; // @[RocketCore.scala:153:7]
wire [1:0] io_rocc_mem_resp_bits_dprv = 2'h0; // @[RocketCore.scala:153:7]
wire [1:0] _htval_valid_dmem_T_1 = 2'h0; // @[RocketCore.scala:857:76]
wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[RocketCore.scala:153:7]
wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[RocketCore.scala:153:7]
wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[RocketCore.scala:153:7]
wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[RocketCore.scala:153:7]
wire [4:0] io_rocc_resp_bits_rd = 5'h0; // @[RocketCore.scala:153:7]
wire [4:0] io_rocc_mem_req_bits_cmd = 5'h0; // @[RocketCore.scala:153:7]
wire [4:0] io_rocc_mem_resp_bits_cmd = 5'h0; // @[RocketCore.scala:153:7]
wire [4:0] _csr_io_fcsr_flags_bits_T_2 = 5'h0; // @[RocketCore.scala:839:116]
wire [4:0] _csr_io_fcsr_flags_bits_T_3 = 5'h0; // @[RocketCore.scala:839:110]
wire [4:0] xrfWriteBundle_rd0src = 5'h0; // @[RocketCore.scala:1249:28]
wire [4:0] xrfWriteBundle_rd1src = 5'h0; // @[RocketCore.scala:1249:28]
wire [39:0] io_rocc_mem_req_bits_addr = 40'h0; // @[RocketCore.scala:153:7]
wire [39:0] io_rocc_mem_resp_bits_addr = 40'h0; // @[RocketCore.scala:153:7]
wire [39:0] io_rocc_mem_s2_gpa = 40'h0; // @[RocketCore.scala:153:7]
wire [39:0] htval_dmem = 40'h0; // @[RocketCore.scala:858:25]
wire [31:0] io_reset_vector = 32'h0; // @[RocketCore.scala:153:7]
wire [31:0] io_rocc_mem_s2_paddr = 32'h0; // @[RocketCore.scala:153:7]
wire [31:0] xrfWriteBundle_inst = 32'h0; // @[RocketCore.scala:1249:28]
wire [38:0] io_imem_ras_update_bits_returnAddr = 39'h0; // @[RocketCore.scala:153:7]
wire [63:0] io_dmem_req_bits_data = 64'h0; // @[RocketCore.scala:153:7]
wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[RocketCore.scala:153:7]
wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[RocketCore.scala:153:7]
wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[RocketCore.scala:153:7]
wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[RocketCore.scala:153:7]
wire [63:0] io_rocc_resp_bits_data = 64'h0; // @[RocketCore.scala:153:7]
wire [63:0] io_rocc_mem_req_bits_data = 64'h0; // @[RocketCore.scala:153:7]
wire [63:0] io_rocc_mem_s1_data_data = 64'h0; // @[RocketCore.scala:153:7]
wire [63:0] io_rocc_mem_resp_bits_data = 64'h0; // @[RocketCore.scala:153:7]
wire [63:0] io_rocc_mem_resp_bits_data_word_bypass = 64'h0; // @[RocketCore.scala:153:7]
wire [63:0] io_rocc_mem_resp_bits_data_raw = 64'h0; // @[RocketCore.scala:153:7]
wire [63:0] io_rocc_mem_resp_bits_store_data = 64'h0; // @[RocketCore.scala:153:7]
wire [63:0] xrfWriteBundle_pc = 64'h0; // @[RocketCore.scala:1249:28]
wire [63:0] xrfWriteBundle_rd0val = 64'h0; // @[RocketCore.scala:1249:28]
wire [63:0] xrfWriteBundle_rd1val = 64'h0; // @[RocketCore.scala:1249:28]
wire [1:0] io_ptw_status_sxl = 2'h2; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_status_uxl = 2'h2; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_hstatus_vsxl = 2'h2; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_gstatus_uxl = 2'h2; // @[RocketCore.scala:153:7]
wire [1:0] io_rocc_cmd_bits_status_sxl = 2'h2; // @[RocketCore.scala:153:7]
wire [1:0] io_rocc_cmd_bits_status_uxl = 2'h2; // @[RocketCore.scala:153:7]
wire [2:0] io_fpu_v_sew = 3'h0; // @[RocketCore.scala:153:7]
wire [6:0] io_rocc_mem_req_bits_tag = 7'h0; // @[RocketCore.scala:153:7]
wire [6:0] io_rocc_mem_resp_bits_tag = 7'h0; // @[RocketCore.scala:153:7]
wire io_fpu_hartid_0 = io_hartid_0; // @[RocketCore.scala:153:7]
wire take_pc_mem_wb; // @[RocketCore.scala:307:35]
wire [39:0] _io_imem_req_bits_pc_T_2; // @[RocketCore.scala:1051:8]
wire _io_imem_req_bits_speculative_T; // @[RocketCore.scala:1049:35]
wire _io_imem_sfence_valid_T; // @[RocketCore.scala:1060:40]
wire io_ptw_sfence_valid_0 = io_imem_sfence_valid_0; // @[RocketCore.scala:153:7]
wire _io_imem_sfence_bits_rs1_T; // @[RocketCore.scala:1061:45]
wire io_ptw_sfence_bits_rs1_0 = io_imem_sfence_bits_rs1_0; // @[RocketCore.scala:153:7]
wire _io_imem_sfence_bits_rs2_T; // @[RocketCore.scala:1062:45]
wire io_ptw_sfence_bits_rs2_0 = io_imem_sfence_bits_rs2_0; // @[RocketCore.scala:153:7]
wire [38:0] io_ptw_sfence_bits_addr_0 = io_imem_sfence_bits_addr_0; // @[RocketCore.scala:153:7]
wire io_ptw_sfence_bits_asid_0 = io_imem_sfence_bits_asid_0; // @[RocketCore.scala:153:7]
wire io_ptw_sfence_bits_hv_0 = io_imem_sfence_bits_hv_0; // @[RocketCore.scala:153:7]
wire io_ptw_sfence_bits_hg_0 = io_imem_sfence_bits_hg_0; // @[RocketCore.scala:153:7]
wire _io_imem_btb_update_valid_T_5; // @[RocketCore.scala:1071:77]
wire [38:0] _io_imem_btb_update_bits_pc_T_2; // @[RocketCore.scala:1080:33]
wire [38:0] io_imem_bht_update_bits_pc_0 = io_imem_btb_update_bits_pc_0; // @[RocketCore.scala:153:7]
wire mem_cfi; // @[RocketCore.scala:625:50]
wire [1:0] _io_imem_btb_update_bits_cfiType_T_11; // @[RocketCore.scala:1074:8]
wire _io_imem_bht_update_valid_T_1; // @[RocketCore.scala:1084:45]
wire mem_wrong_npc; // @[RocketCore.scala:621:8]
wire _io_imem_flush_icache_T_2; // @[RocketCore.scala:1054:59]
wire _io_dmem_req_valid_T; // @[RocketCore.scala:1130:41]
wire [39:0] _io_dmem_req_bits_addr_T_1; // @[RocketCore.scala:1295:8]
wire _io_dmem_req_bits_signed_T_3; // @[RocketCore.scala:1136:30]
wire [1:0] _io_dmem_req_bits_dprv_T; // @[RocketCore.scala:1140:31]
wire _io_dmem_req_bits_dv_T; // @[RocketCore.scala:1141:37]
wire _io_dmem_req_bits_no_resp_T_29; // @[RocketCore.scala:1142:56]
wire _io_dmem_s1_kill_T_2; // @[RocketCore.scala:1151:68]
wire [63:0] _io_dmem_s1_data_data_T; // @[RocketCore.scala:1148:63]
wire [63:0] io_fpu_ll_resp_data_0 = io_dmem_resp_bits_data_0; // @[RocketCore.scala:153:7]
wire [63:0] _rf_wdata_T_1 = io_dmem_resp_bits_data_0; // @[RocketCore.scala:153:7, :819:78]
wire [63:0] dcache_bypass_data = io_dmem_resp_bits_data_word_bypass_0; // @[RocketCore.scala:153:7, :449:62]
wire _io_dmem_keep_clock_enabled_T_2; // @[RocketCore.scala:1154:70]
wire [63:0] ex_rs_0; // @[RocketCore.scala:469:14]
wire _csr_io_fcsr_flags_valid_T = io_fpu_fcsr_flags_valid_0; // @[RocketCore.scala:153:7, :838:54]
wire _io_fpu_ll_resp_val_T; // @[RocketCore.scala:1099:41]
wire [4:0] dmem_resp_waddr; // @[RocketCore.scala:767:46]
wire _io_fpu_valid_T_1; // @[RocketCore.scala:1094:31]
wire _id_illegal_insn_T_11 = io_fpu_illegal_rm_0; // @[RocketCore.scala:153:7, :384:70]
wire ctrl_killx; // @[RocketCore.scala:602:48]
wire killm_common; // @[RocketCore.scala:700:68]
wire _io_fpu_keep_clock_enabled_T; // @[CustomCSRs.scala:45:59]
wire _io_rocc_cmd_valid_T_2; // @[RocketCore.scala:1156:53]
wire [6:0] _io_rocc_cmd_bits_inst_WIRE_funct; // @[RocketCore.scala:1159:48]
wire [4:0] _io_rocc_cmd_bits_inst_WIRE_rs2; // @[RocketCore.scala:1159:48]
wire [4:0] _io_rocc_cmd_bits_inst_WIRE_rs1; // @[RocketCore.scala:1159:48]
wire _io_rocc_cmd_bits_inst_WIRE_xd; // @[RocketCore.scala:1159:48]
wire _io_rocc_cmd_bits_inst_WIRE_xs1; // @[RocketCore.scala:1159:48]
wire _io_rocc_cmd_bits_inst_WIRE_xs2; // @[RocketCore.scala:1159:48]
wire [4:0] _io_rocc_cmd_bits_inst_WIRE_rd; // @[RocketCore.scala:1159:48]
wire [6:0] _io_rocc_cmd_bits_inst_WIRE_opcode; // @[RocketCore.scala:1159:48]
wire [39:0] io_imem_req_bits_pc_0; // @[RocketCore.scala:153:7]
wire io_imem_req_bits_speculative_0; // @[RocketCore.scala:153:7]
wire io_imem_req_valid_0; // @[RocketCore.scala:153:7]
wire io_imem_resp_ready_0; // @[RocketCore.scala:153:7]
wire [7:0] io_imem_btb_update_bits_prediction_bht_history_0; // @[RocketCore.scala:153:7]
wire io_imem_btb_update_bits_prediction_bht_value_0; // @[RocketCore.scala:153:7]
wire [1:0] io_imem_btb_update_bits_prediction_cfiType_0; // @[RocketCore.scala:153:7]
wire io_imem_btb_update_bits_prediction_taken_0; // @[RocketCore.scala:153:7]
wire [1:0] io_imem_btb_update_bits_prediction_mask_0; // @[RocketCore.scala:153:7]
wire io_imem_btb_update_bits_prediction_bridx_0; // @[RocketCore.scala:153:7]
wire [38:0] io_imem_btb_update_bits_prediction_target_0; // @[RocketCore.scala:153:7]
wire [4:0] io_imem_btb_update_bits_prediction_entry_0; // @[RocketCore.scala:153:7]
wire [38:0] io_imem_btb_update_bits_target_0; // @[RocketCore.scala:153:7]
wire io_imem_btb_update_bits_isValid_0; // @[RocketCore.scala:153:7]
wire [38:0] io_imem_btb_update_bits_br_pc_0; // @[RocketCore.scala:153:7]
wire [1:0] io_imem_btb_update_bits_cfiType_0; // @[RocketCore.scala:153:7]
wire io_imem_btb_update_valid_0; // @[RocketCore.scala:153:7]
wire [7:0] io_imem_bht_update_bits_prediction_history_0; // @[RocketCore.scala:153:7]
wire io_imem_bht_update_bits_prediction_value_0; // @[RocketCore.scala:153:7]
wire io_imem_bht_update_bits_branch_0; // @[RocketCore.scala:153:7]
wire io_imem_bht_update_bits_taken_0; // @[RocketCore.scala:153:7]
wire io_imem_bht_update_bits_mispredict_0; // @[RocketCore.scala:153:7]
wire io_imem_bht_update_valid_0; // @[RocketCore.scala:153:7]
wire io_imem_might_request_0; // @[RocketCore.scala:153:7]
wire io_imem_flush_icache_0; // @[RocketCore.scala:153:7]
wire io_imem_progress_0; // @[RocketCore.scala:153:7]
wire [39:0] io_dmem_req_bits_addr_0; // @[RocketCore.scala:153:7]
wire [6:0] io_dmem_req_bits_tag_0; // @[RocketCore.scala:153:7]
wire [4:0] io_dmem_req_bits_cmd_0; // @[RocketCore.scala:153:7]
wire [1:0] io_dmem_req_bits_size_0; // @[RocketCore.scala:153:7]
wire io_dmem_req_bits_signed_0; // @[RocketCore.scala:153:7]
wire [1:0] io_dmem_req_bits_dprv_0; // @[RocketCore.scala:153:7]
wire io_dmem_req_bits_dv_0; // @[RocketCore.scala:153:7]
wire io_dmem_req_bits_no_resp_0; // @[RocketCore.scala:153:7]
wire io_dmem_req_valid_0; // @[RocketCore.scala:153:7]
wire [63:0] io_dmem_s1_data_data_0; // @[RocketCore.scala:153:7]
wire io_dmem_s1_kill_0; // @[RocketCore.scala:153:7]
wire io_dmem_keep_clock_enabled_0; // @[RocketCore.scala:153:7]
wire [3:0] io_ptw_ptbr_mode_0; // @[RocketCore.scala:153:7]
wire [43:0] io_ptw_ptbr_ppn_0; // @[RocketCore.scala:153:7]
wire io_ptw_status_debug_0; // @[RocketCore.scala:153:7]
wire io_ptw_status_cease_0; // @[RocketCore.scala:153:7]
wire io_ptw_status_wfi_0; // @[RocketCore.scala:153:7]
wire [31:0] io_ptw_status_isa_0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_status_dprv_0; // @[RocketCore.scala:153:7]
wire io_ptw_status_dv_0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_status_prv_0; // @[RocketCore.scala:153:7]
wire io_ptw_status_v_0; // @[RocketCore.scala:153:7]
wire io_ptw_status_sd_0; // @[RocketCore.scala:153:7]
wire io_ptw_status_mpv_0; // @[RocketCore.scala:153:7]
wire io_ptw_status_gva_0; // @[RocketCore.scala:153:7]
wire io_ptw_status_tsr_0; // @[RocketCore.scala:153:7]
wire io_ptw_status_tw_0; // @[RocketCore.scala:153:7]
wire io_ptw_status_tvm_0; // @[RocketCore.scala:153:7]
wire io_ptw_status_mxr_0; // @[RocketCore.scala:153:7]
wire io_ptw_status_sum_0; // @[RocketCore.scala:153:7]
wire io_ptw_status_mprv_0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_status_fs_0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_status_mpp_0; // @[RocketCore.scala:153:7]
wire io_ptw_status_spp_0; // @[RocketCore.scala:153:7]
wire io_ptw_status_mpie_0; // @[RocketCore.scala:153:7]
wire io_ptw_status_spie_0; // @[RocketCore.scala:153:7]
wire io_ptw_status_mie_0; // @[RocketCore.scala:153:7]
wire io_ptw_status_sie_0; // @[RocketCore.scala:153:7]
wire io_ptw_hstatus_spvp_0; // @[RocketCore.scala:153:7]
wire io_ptw_hstatus_spv_0; // @[RocketCore.scala:153:7]
wire io_ptw_hstatus_gva_0; // @[RocketCore.scala:153:7]
wire io_ptw_gstatus_debug_0; // @[RocketCore.scala:153:7]
wire io_ptw_gstatus_cease_0; // @[RocketCore.scala:153:7]
wire io_ptw_gstatus_wfi_0; // @[RocketCore.scala:153:7]
wire [31:0] io_ptw_gstatus_isa_0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_gstatus_dprv_0; // @[RocketCore.scala:153:7]
wire io_ptw_gstatus_dv_0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_gstatus_prv_0; // @[RocketCore.scala:153:7]
wire io_ptw_gstatus_v_0; // @[RocketCore.scala:153:7]
wire io_ptw_gstatus_sd_0; // @[RocketCore.scala:153:7]
wire [22:0] io_ptw_gstatus_zero2_0; // @[RocketCore.scala:153:7]
wire io_ptw_gstatus_mpv_0; // @[RocketCore.scala:153:7]
wire io_ptw_gstatus_gva_0; // @[RocketCore.scala:153:7]
wire io_ptw_gstatus_mbe_0; // @[RocketCore.scala:153:7]
wire io_ptw_gstatus_sbe_0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_gstatus_sxl_0; // @[RocketCore.scala:153:7]
wire [7:0] io_ptw_gstatus_zero1_0; // @[RocketCore.scala:153:7]
wire io_ptw_gstatus_tsr_0; // @[RocketCore.scala:153:7]
wire io_ptw_gstatus_tw_0; // @[RocketCore.scala:153:7]
wire io_ptw_gstatus_tvm_0; // @[RocketCore.scala:153:7]
wire io_ptw_gstatus_mxr_0; // @[RocketCore.scala:153:7]
wire io_ptw_gstatus_sum_0; // @[RocketCore.scala:153:7]
wire io_ptw_gstatus_mprv_0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_gstatus_fs_0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_gstatus_mpp_0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_gstatus_vs_0; // @[RocketCore.scala:153:7]
wire io_ptw_gstatus_spp_0; // @[RocketCore.scala:153:7]
wire io_ptw_gstatus_mpie_0; // @[RocketCore.scala:153:7]
wire io_ptw_gstatus_ube_0; // @[RocketCore.scala:153:7]
wire io_ptw_gstatus_spie_0; // @[RocketCore.scala:153:7]
wire io_ptw_gstatus_upie_0; // @[RocketCore.scala:153:7]
wire io_ptw_gstatus_mie_0; // @[RocketCore.scala:153:7]
wire io_ptw_gstatus_hie_0; // @[RocketCore.scala:153:7]
wire io_ptw_gstatus_sie_0; // @[RocketCore.scala:153:7]
wire io_ptw_gstatus_uie_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_0_cfg_l_0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_pmp_0_cfg_a_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_0_cfg_x_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_0_cfg_w_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_0_cfg_r_0; // @[RocketCore.scala:153:7]
wire [29:0] io_ptw_pmp_0_addr_0; // @[RocketCore.scala:153:7]
wire [31:0] io_ptw_pmp_0_mask_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_1_cfg_l_0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_pmp_1_cfg_a_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_1_cfg_x_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_1_cfg_w_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_1_cfg_r_0; // @[RocketCore.scala:153:7]
wire [29:0] io_ptw_pmp_1_addr_0; // @[RocketCore.scala:153:7]
wire [31:0] io_ptw_pmp_1_mask_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_2_cfg_l_0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_pmp_2_cfg_a_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_2_cfg_x_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_2_cfg_w_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_2_cfg_r_0; // @[RocketCore.scala:153:7]
wire [29:0] io_ptw_pmp_2_addr_0; // @[RocketCore.scala:153:7]
wire [31:0] io_ptw_pmp_2_mask_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_3_cfg_l_0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_pmp_3_cfg_a_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_3_cfg_x_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_3_cfg_w_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_3_cfg_r_0; // @[RocketCore.scala:153:7]
wire [29:0] io_ptw_pmp_3_addr_0; // @[RocketCore.scala:153:7]
wire [31:0] io_ptw_pmp_3_mask_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_4_cfg_l_0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_pmp_4_cfg_a_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_4_cfg_x_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_4_cfg_w_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_4_cfg_r_0; // @[RocketCore.scala:153:7]
wire [29:0] io_ptw_pmp_4_addr_0; // @[RocketCore.scala:153:7]
wire [31:0] io_ptw_pmp_4_mask_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_5_cfg_l_0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_pmp_5_cfg_a_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_5_cfg_x_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_5_cfg_w_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_5_cfg_r_0; // @[RocketCore.scala:153:7]
wire [29:0] io_ptw_pmp_5_addr_0; // @[RocketCore.scala:153:7]
wire [31:0] io_ptw_pmp_5_mask_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_6_cfg_l_0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_pmp_6_cfg_a_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_6_cfg_x_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_6_cfg_w_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_6_cfg_r_0; // @[RocketCore.scala:153:7]
wire [29:0] io_ptw_pmp_6_addr_0; // @[RocketCore.scala:153:7]
wire [31:0] io_ptw_pmp_6_mask_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_7_cfg_l_0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_pmp_7_cfg_a_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_7_cfg_x_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_7_cfg_w_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_7_cfg_r_0; // @[RocketCore.scala:153:7]
wire [29:0] io_ptw_pmp_7_addr_0; // @[RocketCore.scala:153:7]
wire [31:0] io_ptw_pmp_7_mask_0; // @[RocketCore.scala:153:7]
wire io_ptw_customCSRs_csrs_0_ren_0; // @[RocketCore.scala:153:7]
wire io_ptw_customCSRs_csrs_0_wen_0; // @[RocketCore.scala:153:7]
wire [63:0] io_ptw_customCSRs_csrs_0_wdata_0; // @[RocketCore.scala:153:7]
wire [63:0] io_ptw_customCSRs_csrs_0_value_0; // @[RocketCore.scala:153:7]
wire io_ptw_customCSRs_csrs_1_ren_0; // @[RocketCore.scala:153:7]
wire io_ptw_customCSRs_csrs_1_wen_0; // @[RocketCore.scala:153:7]
wire [63:0] io_ptw_customCSRs_csrs_1_wdata_0; // @[RocketCore.scala:153:7]
wire [63:0] io_ptw_customCSRs_csrs_1_value_0; // @[RocketCore.scala:153:7]
wire io_ptw_customCSRs_csrs_2_ren_0; // @[RocketCore.scala:153:7]
wire io_ptw_customCSRs_csrs_2_wen_0; // @[RocketCore.scala:153:7]
wire [63:0] io_ptw_customCSRs_csrs_2_wdata_0; // @[RocketCore.scala:153:7]
wire [63:0] io_ptw_customCSRs_csrs_2_value_0; // @[RocketCore.scala:153:7]
wire io_ptw_customCSRs_csrs_3_ren_0; // @[RocketCore.scala:153:7]
wire io_ptw_customCSRs_csrs_3_wen_0; // @[RocketCore.scala:153:7]
wire [63:0] io_ptw_customCSRs_csrs_3_wdata_0; // @[RocketCore.scala:153:7]
wire [63:0] io_ptw_customCSRs_csrs_3_value_0; // @[RocketCore.scala:153:7]
wire [63:0] io_fpu_time_0; // @[RocketCore.scala:153:7]
wire [31:0] io_fpu_inst_0; // @[RocketCore.scala:153:7]
wire [63:0] io_fpu_fromint_data_0; // @[RocketCore.scala:153:7]
wire [2:0] io_fpu_fcsr_rm_0; // @[RocketCore.scala:153:7]
wire io_fpu_ll_resp_val_0; // @[RocketCore.scala:153:7]
wire [2:0] io_fpu_ll_resp_type_0; // @[RocketCore.scala:153:7]
wire [4:0] io_fpu_ll_resp_tag_0; // @[RocketCore.scala:153:7]
wire io_fpu_valid_0; // @[RocketCore.scala:153:7]
wire io_fpu_killx_0; // @[RocketCore.scala:153:7]
wire io_fpu_killm_0; // @[RocketCore.scala:153:7]
wire io_fpu_keep_clock_enabled_0; // @[RocketCore.scala:153:7]
wire [6:0] io_rocc_cmd_bits_inst_funct; // @[RocketCore.scala:153:7]
wire [4:0] io_rocc_cmd_bits_inst_rs2; // @[RocketCore.scala:153:7]
wire [4:0] io_rocc_cmd_bits_inst_rs1; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_bits_inst_xd; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_bits_inst_xs1; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_bits_inst_xs2; // @[RocketCore.scala:153:7]
wire [4:0] io_rocc_cmd_bits_inst_rd; // @[RocketCore.scala:153:7]
wire [6:0] io_rocc_cmd_bits_inst_opcode; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_bits_status_debug; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_bits_status_cease; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_bits_status_wfi; // @[RocketCore.scala:153:7]
wire [31:0] io_rocc_cmd_bits_status_isa; // @[RocketCore.scala:153:7]
wire [1:0] io_rocc_cmd_bits_status_dprv; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_bits_status_dv; // @[RocketCore.scala:153:7]
wire [1:0] io_rocc_cmd_bits_status_prv; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_bits_status_v; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_bits_status_sd; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_bits_status_mpv; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_bits_status_gva; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_bits_status_tsr; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_bits_status_tw; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_bits_status_tvm; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_bits_status_mxr; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_bits_status_sum; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_bits_status_mprv; // @[RocketCore.scala:153:7]
wire [1:0] io_rocc_cmd_bits_status_fs; // @[RocketCore.scala:153:7]
wire [1:0] io_rocc_cmd_bits_status_mpp; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_bits_status_spp; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_bits_status_mpie; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_bits_status_spie; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_bits_status_mie; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_bits_status_sie; // @[RocketCore.scala:153:7]
wire [63:0] io_rocc_cmd_bits_rs1; // @[RocketCore.scala:153:7]
wire [63:0] io_rocc_cmd_bits_rs2; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_valid; // @[RocketCore.scala:153:7]
wire io_trace_insns_0_valid_0; // @[RocketCore.scala:153:7]
wire [39:0] io_trace_insns_0_iaddr_0; // @[RocketCore.scala:153:7]
wire [31:0] io_trace_insns_0_insn_0; // @[RocketCore.scala:153:7]
wire [2:0] io_trace_insns_0_priv_0; // @[RocketCore.scala:153:7]
wire io_trace_insns_0_exception_0; // @[RocketCore.scala:153:7]
wire io_trace_insns_0_interrupt_0; // @[RocketCore.scala:153:7]
wire [63:0] io_trace_insns_0_cause_0; // @[RocketCore.scala:153:7]
wire [39:0] io_trace_insns_0_tval_0; // @[RocketCore.scala:153:7]
wire [63:0] io_trace_time_0; // @[RocketCore.scala:153:7]
wire io_bpwatch_0_valid_0_0; // @[RocketCore.scala:153:7]
wire [2:0] io_bpwatch_0_action_0; // @[RocketCore.scala:153:7]
wire io_wfi_0; // @[RocketCore.scala:153:7]
reg id_reg_pause; // @[RocketCore.scala:161:25]
reg imem_might_request_reg; // @[RocketCore.scala:162:35]
assign io_imem_might_request_0 = imem_might_request_reg; // @[RocketCore.scala:153:7, :162:35]
reg ex_ctrl_legal; // @[RocketCore.scala:243:20]
reg ex_ctrl_fp; // @[RocketCore.scala:243:20]
reg ex_ctrl_rocc; // @[RocketCore.scala:243:20]
reg ex_ctrl_branch; // @[RocketCore.scala:243:20]
reg ex_ctrl_jal; // @[RocketCore.scala:243:20]
reg ex_ctrl_jalr; // @[RocketCore.scala:243:20]
reg ex_ctrl_rxs2; // @[RocketCore.scala:243:20]
reg ex_ctrl_rxs1; // @[RocketCore.scala:243:20]
reg [2:0] ex_ctrl_sel_alu2; // @[RocketCore.scala:243:20]
reg [1:0] ex_ctrl_sel_alu1; // @[RocketCore.scala:243:20]
reg [2:0] ex_ctrl_sel_imm; // @[RocketCore.scala:243:20]
reg ex_ctrl_alu_dw; // @[RocketCore.scala:243:20]
reg [4:0] ex_ctrl_alu_fn; // @[RocketCore.scala:243:20]
reg ex_ctrl_mem; // @[RocketCore.scala:243:20]
wire _ex_sfence_T = ex_ctrl_mem; // @[RocketCore.scala:243:20, :605:29]
reg [4:0] ex_ctrl_mem_cmd; // @[RocketCore.scala:243:20]
assign io_dmem_req_bits_cmd_0 = ex_ctrl_mem_cmd; // @[RocketCore.scala:153:7, :243:20]
reg ex_ctrl_rfs1; // @[RocketCore.scala:243:20]
reg ex_ctrl_rfs2; // @[RocketCore.scala:243:20]
reg ex_ctrl_rfs3; // @[RocketCore.scala:243:20]
reg ex_ctrl_wfd; // @[RocketCore.scala:243:20]
reg ex_ctrl_mul; // @[RocketCore.scala:243:20]
reg ex_ctrl_div; // @[RocketCore.scala:243:20]
reg ex_ctrl_wxd; // @[RocketCore.scala:243:20]
reg [2:0] ex_ctrl_csr; // @[RocketCore.scala:243:20]
reg ex_ctrl_fence_i; // @[RocketCore.scala:243:20]
reg ex_ctrl_fence; // @[RocketCore.scala:243:20]
reg ex_ctrl_amo; // @[RocketCore.scala:243:20]
reg ex_ctrl_dp; // @[RocketCore.scala:243:20]
reg mem_ctrl_legal; // @[RocketCore.scala:244:21]
reg mem_ctrl_fp; // @[RocketCore.scala:244:21]
reg mem_ctrl_rocc; // @[RocketCore.scala:244:21]
reg mem_ctrl_branch; // @[RocketCore.scala:244:21]
assign io_imem_bht_update_bits_branch_0 = mem_ctrl_branch; // @[RocketCore.scala:153:7, :244:21]
reg mem_ctrl_jal; // @[RocketCore.scala:244:21]
reg mem_ctrl_jalr; // @[RocketCore.scala:244:21]
reg mem_ctrl_rxs2; // @[RocketCore.scala:244:21]
reg mem_ctrl_rxs1; // @[RocketCore.scala:244:21]
reg [2:0] mem_ctrl_sel_alu2; // @[RocketCore.scala:244:21]
reg [1:0] mem_ctrl_sel_alu1; // @[RocketCore.scala:244:21]
reg [2:0] mem_ctrl_sel_imm; // @[RocketCore.scala:244:21]
reg mem_ctrl_alu_dw; // @[RocketCore.scala:244:21]
reg [4:0] mem_ctrl_alu_fn; // @[RocketCore.scala:244:21]
reg mem_ctrl_mem; // @[RocketCore.scala:244:21]
reg [4:0] mem_ctrl_mem_cmd; // @[RocketCore.scala:244:21]
reg mem_ctrl_rfs1; // @[RocketCore.scala:244:21]
reg mem_ctrl_rfs2; // @[RocketCore.scala:244:21]
reg mem_ctrl_rfs3; // @[RocketCore.scala:244:21]
reg mem_ctrl_wfd; // @[RocketCore.scala:244:21]
reg mem_ctrl_mul; // @[RocketCore.scala:244:21]
reg mem_ctrl_div; // @[RocketCore.scala:244:21]
reg mem_ctrl_wxd; // @[RocketCore.scala:244:21]
reg [2:0] mem_ctrl_csr; // @[RocketCore.scala:244:21]
reg mem_ctrl_fence_i; // @[RocketCore.scala:244:21]
reg mem_ctrl_fence; // @[RocketCore.scala:244:21]
reg mem_ctrl_amo; // @[RocketCore.scala:244:21]
reg mem_ctrl_dp; // @[RocketCore.scala:244:21]
reg mem_ctrl_vec; // @[RocketCore.scala:244:21]
reg wb_ctrl_legal; // @[RocketCore.scala:245:20]
reg wb_ctrl_fp; // @[RocketCore.scala:245:20]
reg wb_ctrl_rocc; // @[RocketCore.scala:245:20]
reg wb_ctrl_branch; // @[RocketCore.scala:245:20]
reg wb_ctrl_jal; // @[RocketCore.scala:245:20]
reg wb_ctrl_jalr; // @[RocketCore.scala:245:20]
reg wb_ctrl_rxs2; // @[RocketCore.scala:245:20]
reg wb_ctrl_rxs1; // @[RocketCore.scala:245:20]
reg [2:0] wb_ctrl_sel_alu2; // @[RocketCore.scala:245:20]
reg [1:0] wb_ctrl_sel_alu1; // @[RocketCore.scala:245:20]
reg [2:0] wb_ctrl_sel_imm; // @[RocketCore.scala:245:20]
reg wb_ctrl_alu_dw; // @[RocketCore.scala:245:20]
reg [4:0] wb_ctrl_alu_fn; // @[RocketCore.scala:245:20]
reg wb_ctrl_mem; // @[RocketCore.scala:245:20]
reg [4:0] wb_ctrl_mem_cmd; // @[RocketCore.scala:245:20]
reg wb_ctrl_rfs1; // @[RocketCore.scala:245:20]
reg wb_ctrl_rfs2; // @[RocketCore.scala:245:20]
reg wb_ctrl_rfs3; // @[RocketCore.scala:245:20]
reg wb_ctrl_wfd; // @[RocketCore.scala:245:20]
reg wb_ctrl_mul; // @[RocketCore.scala:245:20]
reg wb_ctrl_div; // @[RocketCore.scala:245:20]
reg wb_ctrl_wxd; // @[RocketCore.scala:245:20]
reg [2:0] wb_ctrl_csr; // @[RocketCore.scala:245:20]
reg wb_ctrl_fence_i; // @[RocketCore.scala:245:20]
reg wb_ctrl_fence; // @[RocketCore.scala:245:20]
reg wb_ctrl_amo; // @[RocketCore.scala:245:20]
reg wb_ctrl_dp; // @[RocketCore.scala:245:20]
reg wb_ctrl_vec; // @[RocketCore.scala:245:20]
reg ex_reg_xcpt_interrupt; // @[RocketCore.scala:247:35]
reg ex_reg_valid; // @[RocketCore.scala:248:35]
reg ex_reg_rvc; // @[RocketCore.scala:249:35]
reg [1:0] ex_reg_btb_resp_cfiType; // @[RocketCore.scala:250:35]
reg ex_reg_btb_resp_taken; // @[RocketCore.scala:250:35]
reg [1:0] ex_reg_btb_resp_mask; // @[RocketCore.scala:250:35]
reg ex_reg_btb_resp_bridx; // @[RocketCore.scala:250:35]
reg [38:0] ex_reg_btb_resp_target; // @[RocketCore.scala:250:35]
reg [4:0] ex_reg_btb_resp_entry; // @[RocketCore.scala:250:35]
reg [7:0] ex_reg_btb_resp_bht_history; // @[RocketCore.scala:250:35]
reg ex_reg_btb_resp_bht_value; // @[RocketCore.scala:250:35]
reg ex_reg_xcpt; // @[RocketCore.scala:251:35]
reg ex_reg_flush_pipe; // @[RocketCore.scala:252:35]
reg ex_reg_load_use; // @[RocketCore.scala:253:35]
reg [63:0] ex_reg_cause; // @[RocketCore.scala:254:35]
wire [63:0] ex_cause = ex_reg_cause; // @[RocketCore.scala:254:35, :1278:50]
reg ex_reg_replay; // @[RocketCore.scala:255:26]
reg [39:0] ex_reg_pc; // @[RocketCore.scala:256:22]
wire [39:0] _ex_op1_T_1 = ex_reg_pc; // @[RocketCore.scala:256:22, :474:24]
reg [1:0] ex_reg_mem_size; // @[RocketCore.scala:257:28]
assign io_dmem_req_bits_size_0 = ex_reg_mem_size; // @[RocketCore.scala:153:7, :257:28]
reg [31:0] ex_reg_inst; // @[RocketCore.scala:259:24]
reg [31:0] ex_reg_raw_inst; // @[RocketCore.scala:260:28]
reg ex_reg_wphit_0; // @[RocketCore.scala:261:36]
reg mem_reg_xcpt_interrupt; // @[RocketCore.scala:264:36]
reg mem_reg_valid; // @[RocketCore.scala:265:36]
reg mem_reg_rvc; // @[RocketCore.scala:266:36]
reg [1:0] mem_reg_btb_resp_cfiType; // @[RocketCore.scala:267:36]
assign io_imem_btb_update_bits_prediction_cfiType_0 = mem_reg_btb_resp_cfiType; // @[RocketCore.scala:153:7, :267:36]
reg mem_reg_btb_resp_taken; // @[RocketCore.scala:267:36]
assign io_imem_btb_update_bits_prediction_taken_0 = mem_reg_btb_resp_taken; // @[RocketCore.scala:153:7, :267:36]
wire _mem_direction_misprediction_T = mem_reg_btb_resp_taken; // @[RocketCore.scala:267:36, :627:85]
reg [1:0] mem_reg_btb_resp_mask; // @[RocketCore.scala:267:36]
assign io_imem_btb_update_bits_prediction_mask_0 = mem_reg_btb_resp_mask; // @[RocketCore.scala:153:7, :267:36]
reg mem_reg_btb_resp_bridx; // @[RocketCore.scala:267:36]
assign io_imem_btb_update_bits_prediction_bridx_0 = mem_reg_btb_resp_bridx; // @[RocketCore.scala:153:7, :267:36]
reg [38:0] mem_reg_btb_resp_target; // @[RocketCore.scala:267:36]
assign io_imem_btb_update_bits_prediction_target_0 = mem_reg_btb_resp_target; // @[RocketCore.scala:153:7, :267:36]
reg [4:0] mem_reg_btb_resp_entry; // @[RocketCore.scala:267:36]
assign io_imem_btb_update_bits_prediction_entry_0 = mem_reg_btb_resp_entry; // @[RocketCore.scala:153:7, :267:36]
reg [7:0] mem_reg_btb_resp_bht_history; // @[RocketCore.scala:267:36]
assign io_imem_btb_update_bits_prediction_bht_history_0 = mem_reg_btb_resp_bht_history; // @[RocketCore.scala:153:7, :267:36]
assign io_imem_bht_update_bits_prediction_history_0 = mem_reg_btb_resp_bht_history; // @[RocketCore.scala:153:7, :267:36]
reg mem_reg_btb_resp_bht_value; // @[RocketCore.scala:267:36]
assign io_imem_btb_update_bits_prediction_bht_value_0 = mem_reg_btb_resp_bht_value; // @[RocketCore.scala:153:7, :267:36]
assign io_imem_bht_update_bits_prediction_value_0 = mem_reg_btb_resp_bht_value; // @[RocketCore.scala:153:7, :267:36]
reg mem_reg_xcpt; // @[RocketCore.scala:268:36]
reg mem_reg_replay; // @[RocketCore.scala:269:36]
reg mem_reg_flush_pipe; // @[RocketCore.scala:270:36]
reg [63:0] mem_reg_cause; // @[RocketCore.scala:271:36]
reg mem_reg_slow_bypass; // @[RocketCore.scala:272:36]
wire mem_mem_cmd_bh = mem_reg_slow_bypass; // @[RocketCore.scala:272:36, :995:41]
reg mem_reg_load; // @[RocketCore.scala:273:36]
reg mem_reg_store; // @[RocketCore.scala:274:36]
reg mem_reg_set_vconfig; // @[RocketCore.scala:275:36]
reg mem_reg_sfence; // @[RocketCore.scala:276:27]
reg [39:0] mem_reg_pc; // @[RocketCore.scala:277:23]
wire [39:0] _mem_br_target_T = mem_reg_pc; // @[RocketCore.scala:277:23, :615:34]
reg [31:0] mem_reg_inst; // @[RocketCore.scala:278:25]
reg [1:0] mem_reg_mem_size; // @[RocketCore.scala:279:29]
reg mem_reg_hls_or_dv; // @[RocketCore.scala:280:30]
reg [31:0] mem_reg_raw_inst; // @[RocketCore.scala:281:29]
reg [63:0] mem_reg_wdata; // @[RocketCore.scala:282:26]
wire [63:0] _mem_int_wdata_T_3 = mem_reg_wdata; // @[RocketCore.scala:282:26, :624:111]
reg [63:0] mem_reg_rs2; // @[RocketCore.scala:283:24]
reg mem_br_taken; // @[RocketCore.scala:284:25]
assign io_imem_bht_update_bits_taken_0 = mem_br_taken; // @[RocketCore.scala:153:7, :284:25]
wire _take_pc_mem_T_3; // @[RocketCore.scala:629:49]
wire take_pc_mem; // @[RocketCore.scala:285:25]
reg mem_reg_wphit_0; // @[RocketCore.scala:286:35]
reg wb_reg_valid; // @[RocketCore.scala:288:35]
reg wb_reg_xcpt; // @[RocketCore.scala:289:35]
reg wb_reg_replay; // @[RocketCore.scala:290:35]
reg wb_reg_flush_pipe; // @[RocketCore.scala:291:35]
reg [63:0] wb_reg_cause; // @[RocketCore.scala:292:35]
reg wb_reg_set_vconfig; // @[RocketCore.scala:293:35]
reg wb_reg_sfence; // @[RocketCore.scala:294:26]
reg [39:0] wb_reg_pc; // @[RocketCore.scala:295:22]
reg [1:0] wb_reg_mem_size; // @[RocketCore.scala:296:28]
reg wb_reg_hls_or_dv; // @[RocketCore.scala:297:29]
reg wb_reg_hfence_v; // @[RocketCore.scala:298:28]
assign io_imem_sfence_bits_hv_0 = wb_reg_hfence_v; // @[RocketCore.scala:153:7, :298:28]
reg wb_reg_hfence_g; // @[RocketCore.scala:299:28]
assign io_imem_sfence_bits_hg_0 = wb_reg_hfence_g; // @[RocketCore.scala:153:7, :299:28]
reg [31:0] wb_reg_inst; // @[RocketCore.scala:300:24]
wire [31:0] _io_rocc_cmd_bits_inst_WIRE_1 = wb_reg_inst; // @[RocketCore.scala:300:24, :1159:48]
reg [31:0] wb_reg_raw_inst; // @[RocketCore.scala:301:28]
reg [63:0] wb_reg_wdata; // @[RocketCore.scala:302:25]
assign io_rocc_cmd_bits_rs1 = wb_reg_wdata; // @[RocketCore.scala:153:7, :302:25]
wire [63:0] _rf_wdata_T_3 = wb_reg_wdata; // @[RocketCore.scala:302:25, :822:21]
reg [63:0] wb_reg_rs2; // @[RocketCore.scala:303:23]
assign io_rocc_cmd_bits_rs2 = wb_reg_rs2; // @[RocketCore.scala:153:7, :303:23]
wire _take_pc_wb_T_2; // @[RocketCore.scala:762:53]
wire take_pc_wb; // @[RocketCore.scala:304:24]
reg wb_reg_wphit_0; // @[RocketCore.scala:305:35]
assign io_bpwatch_0_valid_0_0 = wb_reg_wphit_0; // @[RocketCore.scala:153:7, :305:35]
assign take_pc_mem_wb = take_pc_wb | take_pc_mem; // @[RocketCore.scala:285:25, :304:24, :307:35]
assign io_imem_req_valid_0 = take_pc_mem_wb; // @[RocketCore.scala:153:7, :307:35]
wire id_ctrl_decoder_0; // @[Decode.scala:50:77]
wire id_ctrl_decoder_1; // @[Decode.scala:50:77]
wire id_ctrl_decoder_2; // @[Decode.scala:50:77]
wire id_ctrl_decoder_3; // @[Decode.scala:50:77]
wire _id_illegal_insn_T_32 = id_ctrl_rocc; // @[RocketCore.scala:321:21, :391:18]
wire id_ctrl_decoder_4; // @[Decode.scala:50:77]
wire id_ctrl_decoder_5; // @[Decode.scala:50:77]
wire id_ctrl_decoder_6; // @[Decode.scala:50:77]
wire id_ctrl_decoder_7; // @[Decode.scala:50:77]
wire [2:0] id_ctrl_decoder_8; // @[Decode.scala:50:77]
wire [1:0] id_ctrl_decoder_9; // @[Decode.scala:50:77]
wire [2:0] id_ctrl_decoder_10; // @[Decode.scala:50:77]
wire id_ctrl_decoder_11; // @[Decode.scala:50:77]
wire [4:0] id_ctrl_decoder_12; // @[Decode.scala:50:77]
wire id_ctrl_decoder_13; // @[Decode.scala:50:77]
wire [4:0] id_ctrl_decoder_14; // @[Decode.scala:50:77]
wire id_ctrl_decoder_15; // @[Decode.scala:50:77]
wire id_ctrl_decoder_16; // @[Decode.scala:50:77]
wire id_ctrl_decoder_17; // @[Decode.scala:50:77]
wire id_ctrl_decoder_18; // @[Decode.scala:50:77]
wire id_ctrl_decoder_19; // @[Decode.scala:50:77]
wire id_ctrl_decoder_20; // @[Decode.scala:50:77]
wire id_ctrl_decoder_21; // @[Decode.scala:50:77]
wire [2:0] id_ctrl_decoder_22; // @[Decode.scala:50:77]
wire id_ctrl_decoder_23; // @[Decode.scala:50:77]
wire id_ctrl_decoder_24; // @[Decode.scala:50:77]
wire id_ctrl_decoder_25; // @[Decode.scala:50:77]
wire _id_do_fence_T = id_ctrl_fence; // @[RocketCore.scala:321:21, :410:64]
wire id_ctrl_decoder_26; // @[Decode.scala:50:77]
wire id_ctrl_legal; // @[RocketCore.scala:321:21]
wire id_ctrl_fp; // @[RocketCore.scala:321:21]
wire id_ctrl_branch; // @[RocketCore.scala:321:21]
wire id_ctrl_jal; // @[RocketCore.scala:321:21]
wire id_ctrl_jalr; // @[RocketCore.scala:321:21]
wire id_ctrl_rxs2; // @[RocketCore.scala:321:21]
wire id_ctrl_rxs1; // @[RocketCore.scala:321:21]
wire [2:0] id_ctrl_sel_alu2; // @[RocketCore.scala:321:21]
wire [1:0] id_ctrl_sel_alu1; // @[RocketCore.scala:321:21]
wire [2:0] id_ctrl_sel_imm; // @[RocketCore.scala:321:21]
wire id_ctrl_alu_dw; // @[RocketCore.scala:321:21]
wire [4:0] id_ctrl_alu_fn; // @[RocketCore.scala:321:21]
wire id_ctrl_mem; // @[RocketCore.scala:321:21]
wire [4:0] id_ctrl_mem_cmd; // @[RocketCore.scala:321:21]
wire id_ctrl_rfs1; // @[RocketCore.scala:321:21]
wire id_ctrl_rfs2; // @[RocketCore.scala:321:21]
wire id_ctrl_rfs3; // @[RocketCore.scala:321:21]
wire id_ctrl_wfd; // @[RocketCore.scala:321:21]
wire id_ctrl_mul; // @[RocketCore.scala:321:21]
wire id_ctrl_div; // @[RocketCore.scala:321:21]
wire id_ctrl_wxd; // @[RocketCore.scala:321:21]
wire [2:0] id_ctrl_csr; // @[RocketCore.scala:321:21]
wire id_ctrl_fence_i; // @[RocketCore.scala:321:21]
wire id_ctrl_amo; // @[RocketCore.scala:321:21]
wire id_ctrl_dp; // @[RocketCore.scala:321:21]
wire [31:0] id_ctrl_decoder_decoded_plaInput; // @[pla.scala:77:22]
wire [31:0] id_ctrl_decoder_decoded_invInputs = ~id_ctrl_decoder_decoded_plaInput; // @[pla.scala:77:22, :78:21]
wire [41:0] id_ctrl_decoder_decoded_invMatrixOutputs; // @[pla.scala:120:37]
wire [41:0] id_ctrl_decoder_decoded; // @[pla.scala:81:23]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_66 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_67 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_68 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_69 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_70 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_71 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_72 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_73 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_74 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_75 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_76 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_77 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_78 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_79 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_80 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_81 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_82 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_83 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_84 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_85 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_86 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_87 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_88 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_89 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_90 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_91 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_92 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_93 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_94 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_95 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_96 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_97 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_98 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_99 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_100 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_101 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_102 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_103 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_104 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_105 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_106 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_107 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_108 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_109 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_110 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_111 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_112 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_113 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_114 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_115 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_116 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_117 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_118 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_119 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_120 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_121 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_122 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_123 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_124 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_125 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_126 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_127 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_128 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_129 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_130 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_131 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_132 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_133 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_134 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_135 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_136 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_137 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_138 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_139 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_140 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_141 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_142 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_143 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_144 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_145 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_146 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_147 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_148 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_149 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_150 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_151 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_152 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_153 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_154 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_155 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_156 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_157 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_158 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_159 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_160 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_161 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_162 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_163 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_164 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_165 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_166 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_167 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_168 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_169 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_171 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_172 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_173 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_174 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_175 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_176 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_177 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_178 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_179 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_180 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_181 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_182 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_183 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_184 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_185 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_186 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_187 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_188 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_189 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_190 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_191 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_192 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_193 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_66 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_67 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_68 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_69 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_70 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_71 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_72 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_73 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_74 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_75 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_76 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_77 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_78 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_79 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_80 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_81 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_82 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_83 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_84 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_85 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_86 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_87 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_88 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_89 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_90 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_91 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_92 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_93 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_94 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_95 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_96 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_98 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_100 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_101 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_102 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_103 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_104 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_105 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_106 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_107 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_108 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_109 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_110 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_111 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_112 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_113 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_114 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_115 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_116 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_117 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_118 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_119 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_120 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_121 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_122 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_123 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_124 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_125 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_126 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_127 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_128 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_129 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_130 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_131 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_132 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_133 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_134 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_135 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_136 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_137 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_138 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_139 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_140 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_141 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_142 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_143 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_144 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_145 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_146 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_147 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_148 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_149 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_150 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_151 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_152 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_153 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_154 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_155 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_156 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_157 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_158 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_159 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_160 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_161 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_162 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_163 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_164 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_165 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_166 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_167 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_168 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_169 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_171 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_172 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_173 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_174 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_175 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_176 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_177 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_178 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_179 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_180 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_181 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_182 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_183 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_184 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_185 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_186 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_187 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_188 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_189 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_190 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_191 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_192 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_193 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_66 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_67 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_68 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_69 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_70 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_71 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_72 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_73 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_74 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_75 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_76 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_77 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_78 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_79 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_81 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_82 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_83 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_84 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_85 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_86 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_87 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_88 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_89 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_91 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_92 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_93 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_94 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_98 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_100 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_101 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_102 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_103 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_104 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_106 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_107 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_108 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_109 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_110 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_111 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_112 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_113 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_115 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_116 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_117 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_118 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_119 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_120 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_121 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_122 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_123 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_124 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_125 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_126 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_128 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_129 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_130 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_131 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_132 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_133 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_134 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_135 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_136 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_137 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_138 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_139 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_140 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_141 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_142 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_143 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_144 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_145 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_146 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_147 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_148 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_149 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_150 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_151 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_152 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_153 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_154 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_155 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_156 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_157 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_158 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_159 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_160 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_161 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_162 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_163 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_164 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_165 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_166 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_167 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_168 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_169 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_171 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_173 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_174 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_175 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_176 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_177 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_178 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_179 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_180 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_181 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_182 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_183 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_184 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_185 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_186 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_187 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_188 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_189 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_190 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_191 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_192 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_193 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_68 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_69 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_70 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_71 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_72 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_73 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_74 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_75 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_76 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_77 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_78 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_81 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_82 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_83 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_84 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_92 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_93 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_94 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_98 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_100 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_101 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_102 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_103 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_104 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_106 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_107 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_108 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_109 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_110 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_111 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_112 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_113 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_117 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_118 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_119 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_120 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_121 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_122 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_123 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_124 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_125 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_128 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_129 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_130 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_131 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_132 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_137 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_138 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_139 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_140 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_141 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_142 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_143 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_144 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_145 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_146 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_147 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_148 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_149 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_150 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_151 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_152 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_153 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_154 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_155 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_156 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_157 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_160 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_162 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_165 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_167 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_169 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_171 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_173 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_174 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_175 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_176 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_177 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_178 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_179 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_180 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_181 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_182 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_183 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_184 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_185 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_186 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_187 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_188 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_189 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_190 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_191 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_192 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_193 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_46 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_47 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_48 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_57 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_59 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_71 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_76 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_80 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_80 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_88 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_105 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_106 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_107 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_108 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_109 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_110 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_111 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_112 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_116 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_117 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_118 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_119 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_120 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_123 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_129 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_130 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_131 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_133 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_139 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_140 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_141 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_142 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_143 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_144 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_145 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_146 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_147 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_148 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_149 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_153 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_154 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_155 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_156 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_158 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_159 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_159 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_161 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_161 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_163 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_166 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_168 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_172 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_173 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_174 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_175 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_176 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_177 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_178 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_179 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_180 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_181 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_182 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_183 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_184 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_185 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_186 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_187 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_188 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_189 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_190 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_191 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_192 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_15 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_28 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_29 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_31 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_33 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_35 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_44 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_45 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_43 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_44 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_45 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_49 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_47 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_48 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_49 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_50 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_56 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_54 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_55 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_56 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_57 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_58 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_63 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_64 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_65 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_66 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_64 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_68 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_69 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_73 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_74 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_78 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_78 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_79 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_80 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_84 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_85 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_86 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_84 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_85 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_86 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_87 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_88 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_89 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_90 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_91 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_92 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_101 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_110 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_114 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_115 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_116 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_117 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_118 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_119 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_120 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_121 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_125 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_123 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_124 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_125 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_126 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_127 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_128 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_132 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_130 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_134 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_135 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_133 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_134 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_135 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_144 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_145 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_146 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_147 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_148 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_149 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_153 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_157 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_158 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_156 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_160 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_158 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_162 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_163 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_161 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_165 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_163 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_167 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_165 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_168 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_7 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_12 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_20 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_18 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_9 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_7 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_50 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_75 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_77 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_80 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_47 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_41 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_49 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_43 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_50 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_47 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_95 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_97 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_101 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_102 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_111 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_112 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_106 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_114 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_122 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_118 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_128 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_140 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_112 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_162 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_164 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_175 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_176 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_179 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_181 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_182 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53]
wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T = {id_ctrl_decoder_decoded_andMatrixOutputs_hi, id_ctrl_decoder_decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_99_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_57 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_63 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_70 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_75 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_80 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_90 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_95 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_96 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_105 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_114 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_127 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_172 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53]
wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_102_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_1 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_3 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_4 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_2 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_8 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_10 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_7 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_15 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_16 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_17 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_12 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_8 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_6 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_16 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_25 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_18 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_27 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_20 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_31 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_22 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_33 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_54 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_55 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_56 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_57 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_69 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_58 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_59 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_61 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_82 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_44 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_39 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_46 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_41 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_47 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_45 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_96 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_98 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_99 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_100 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_107 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_108 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_90 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_91 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_92 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_93 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_94 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_95 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_115 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_100 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_101 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_102 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_122 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_104 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_124 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_125 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_107 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_118 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_119 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_120 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_121 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_122 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_123 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_130 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_150 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_132 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_152 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_153 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_135 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_155 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_137 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_157 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_139 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_120 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_110 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_163 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_165 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_156 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_157 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_177 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_178 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_160 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_180 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_162 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_163 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_1}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53]
wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_9_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_2 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_1 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_5 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_6 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_3 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_5 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_11 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_5 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_10 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_11 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_8 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_6 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_6 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_25 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_21 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_22 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_15 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_11 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_29 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_21 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_23 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_40 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_35 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_36 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_24 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_25 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_40 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_26 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_27 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_29 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_30 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_31 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_38 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_39 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_60 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_66 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_41 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_33 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_43 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_35 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_49 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_46 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_39 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_75 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_76 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_77 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_78 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_79 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_80 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_81 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_82 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_83 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_84 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_87 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_88 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_89 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_70 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_71 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_72 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_73 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_96 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_97 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_98 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_100 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_101 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_103 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_110 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_131 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_112 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_133 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_136 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_117 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_97 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_142 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_143 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_144 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_145 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_146 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_136 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_137 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_158 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_159 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_140 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_161 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_142 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_143 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53]
wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_29_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_2}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53]
wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_139_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_90 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_95 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_96 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_105 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_114 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_127 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_172 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_65 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_66 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_88 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_89 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_90 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_91 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_95 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_96 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_105 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_114 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_127 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_133 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_134 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_135 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_168 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_172 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_3}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53]
wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_117_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_4 = id_ctrl_decoder_decoded_andMatrixOutputs_117_2; // @[pla.scala:98:70, :114:36]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_56 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_58 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_59 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_60 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_61 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_62 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_64 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_65 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_66 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_67 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_68 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_71 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_72 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_73 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_76 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_77 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_78 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_79 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_81 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_82 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_83 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_84 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_85 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_86 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_87 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_88 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_89 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_91 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_92 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_93 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_94 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_97 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_98 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_99 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_100 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_101 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_102 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_103 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_104 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_106 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_107 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_108 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_109 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_110 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_111 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_112 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_113 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_115 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_116 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_117 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_118 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_119 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_120 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_121 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_122 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_123 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_124 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_125 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_126 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_128 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_129 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_130 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_131 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_132 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_133 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_134 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_135 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_136 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_137 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_138 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_139 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_140 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_141 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_142 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_143 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_144 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_145 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_146 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_147 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_148 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_149 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_150 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_151 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_152 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_153 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_154 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_155 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_156 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_157 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_158 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_159 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_160 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_161 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_162 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_163 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_164 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_165 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_166 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_167 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_168 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_169 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_170 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_171 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_173 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_174 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_175 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_176 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_177 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_178 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_179 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_180 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_181 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_182 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_183 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_184 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_185 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_186 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_187 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_188 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_189 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_190 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_191 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_192 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_193 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_4}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53]
wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_96_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7}; // @[pla.scala:90:45, :98:53]
wire [5:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_35_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53]
wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_182_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_40 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_42 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_50 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_51 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_52 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_53 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_54 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_55 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_58 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_60 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_61 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_62 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_67 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_67 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_69 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_69 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_70 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_72 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_74 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_74 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_75 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_77 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_79 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_81 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_82 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_83 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_85 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_86 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_87 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_87 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_89 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_90 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_91 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_92 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_93 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_94 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_95 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_97 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_97 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_99 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_99 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_100 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_101 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_102 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_103 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_104 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_113 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_115 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_116 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_121 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_122 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_124 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_126 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_126 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_127 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_128 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_136 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_136 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_137 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_138 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_150 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_151 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_152 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_164 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_164 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_166 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_170 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_170 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_171 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_5}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_5}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53]
wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_128_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_6}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_6}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_9}; // @[pla.scala:98:53]
wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_67_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_1 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_6 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_5 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_13 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_1 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_19 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_15 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_28 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_18 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_35 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_23 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_24 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_25 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_35 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_8 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_2 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_3 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_4 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_5 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_56 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_57 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_60 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_62 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_85 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_86 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_69 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_70 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_24 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_75 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_76 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_98 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_79 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_83 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_81 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_85 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_86 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_84 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_88 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_86 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_81 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_82 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_90 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_91 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_98 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_102 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_100 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_95 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_104 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_105 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_106 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_99 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_100 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_88 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_102 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_134 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_115 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_116 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_118 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_123 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_124 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_117 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_126 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_128 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_131 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_70 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_113 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_76 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_1 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_9 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_3 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_4 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_5 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_14 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_1 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_17 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_13 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_14 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_13 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_17 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_16 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_19 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_20 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_36 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_22 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_21 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_22 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_23 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_26 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_27 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_49 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_30 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_76 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_51 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_32 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_33 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_34 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_55 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_36 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_37 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_32 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_36 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_3 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_42 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_40 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_41 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_2 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_3 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_4 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_5 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_45 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_45 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_38 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_13 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_58 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_59 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_61 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_63 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_65 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_66 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_64 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_65 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_66 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_67 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_68 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_66 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_67 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_15 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_72 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_73 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_78 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_76 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_77 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_78 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_79 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_80 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_78 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_82 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_83 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_81 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_85 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_83 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_83 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_84 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_85 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_86 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_95 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_99 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_97 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_95 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_99 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_97 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_96 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_95 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_101 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_102 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_103 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_86 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_87 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_54 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_89 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_114 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_112 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_113 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_114 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_115 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_36 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_6 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_7 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_125 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_126 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_118 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_127 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_129 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_127 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_132 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_71 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_114 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_43 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_75 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_77 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_1 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_4 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_3 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_4 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_1 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_12 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_11 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_12 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_11 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_16 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_15 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_13 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_17 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_18 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_21 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_20 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_18 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_19 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_20 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_24 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_25 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_29 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_27 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_29 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_30 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_35 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_33 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_34 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_38 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_31 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_2 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_3 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_4 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_5 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_44 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_43 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_19 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_10 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_53 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_54 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_55 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_56 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_59 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_60 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_64 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_62 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_63 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_61 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_62 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_69 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_70 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_77 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_75 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_73 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_74 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_76 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_77 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_75 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_79 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_80 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_82 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_80 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_79 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_80 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_81 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_82 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_83 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_84 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_85 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_86 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_98 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_99 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_100 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_52 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_53 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_34 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_55 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_111 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_109 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_110 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_111 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_112 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_122 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_120 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_121 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_122 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_123 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_115 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_116 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_123 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_124 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_125 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_126 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_123 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_128 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_129 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_39 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_40 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_72 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_73 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_30 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_44 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_45 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_46 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_1 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_2 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_3 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_4 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_5 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_1 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_10 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_9 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_10 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_11 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_14 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_12 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_13 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_14 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_15 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_19 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_17 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_18 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_19 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_20 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_21 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_22 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_26 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_24 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_26 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_27 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_31 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_32 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_30 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_31 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_30 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_32 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_2 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_36 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_36 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_37 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_50 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_51 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_52 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_53 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_57 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_58 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_56 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_57 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_61 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_59 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_60 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_59 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_60 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_63 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_62 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_63 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_62 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_63 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_10 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_67 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_68 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_74 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_72 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_70 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_71 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_75 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_73 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_74 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_73 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_76 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_77 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_78 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_79 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_78 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_66 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_67 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_68 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_69 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_70 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_71 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_72 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_73 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_89 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_93 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_91 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_90 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_93 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_92 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_96 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_97 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_98 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_32 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_33 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_21 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_35 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_108 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_106 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_107 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_108 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_109 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_16 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_119 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_117 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_118 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_119 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_120 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_121 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_122 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_41 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_42 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_31 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_1 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_2 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_3 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_4 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_4 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_8 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_9 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_8 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_9 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_10 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_10 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_12 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_12 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_14 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_15 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_16 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_17 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_17 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_18 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_19 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_21 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_22 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_23 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_24 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_31 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_25 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_26 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_28 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_29 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_29 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_30 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_24 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_31 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_37 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_2 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_35 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_34 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_35 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_30 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_5 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_36 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_18 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_9 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_8 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_49 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_65 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_66 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_69 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_68 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_72 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_71 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_74 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_76 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_77 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_65 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_34 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_35 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_36 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_37 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_38 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_39 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_40 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_41 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_90 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_89 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_91 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_79 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_46 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_47 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_28 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_119 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_120 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_119 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_120 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_121 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_122 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_123 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_1 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_2 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_2 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_3 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_6 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_7 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_7 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_7 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_8 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_3 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_10 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_4 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_12 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_14 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_15 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_13 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_14 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_5 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_16 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_17 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_18 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_22 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_19 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_25 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_20 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_21 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_26 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_27 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_22 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_23 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_2 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_7 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_33 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_2 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_27 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_9 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_10 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_4 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_3 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_2 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_1 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_4 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_2 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_10 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_8 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_7 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_7 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_46 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_51 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_52 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_40 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_41 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_42 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_43 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_46 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_47 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_21 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_22 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_14 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_8 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_25 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_26 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_54 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_27 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_56 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_57 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_28 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_59 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_29 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_30 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_62 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_31 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_32 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_16 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_12 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_13 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_14 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_15 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_74 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_75 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_42 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_43 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_44 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_25 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_16 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_17 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_11 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_29 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_30 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_31 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_10 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_11 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_9 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_13 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_90 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_56 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_57 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_58 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_59 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_9 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_6 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_31 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_7}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_10}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_78_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_1}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_1}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_8}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_8}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_11}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_lo_12}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_190_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_2 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_2 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_3 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_4 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_6 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_7 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_8 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_8 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_9 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_9 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_11 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_11 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_13 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_16 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_16 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_15 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_20 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_21 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_23 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_23 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_28 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_24 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_25 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_27 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_28 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_28 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_29 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_6 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_25 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_34 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_2 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_33 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_28 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_29 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_11 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_3 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_2 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_1 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_4 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_2 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_17 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_11 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_8 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_7 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_48 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_47 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_48 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_49 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_50 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_53 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_54 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_53 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_54 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_55 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_56 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_44 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_45 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_59 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_48 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_23 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_8 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_111 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_112 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_113 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_114 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_2}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_4}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_2}; // @[pla.scala:91:29, :98:53]
wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_9}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_2}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_12}; // @[pla.scala:98:53]
wire [12:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_lo_13}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_7_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_2}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_3}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_2}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_10}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_10}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_2}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_3}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_13}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_lo_14}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_98_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_14; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_3}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_4}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_4}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_3}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_11}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_11}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_3}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_4}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_14}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_lo_15}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_32_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_15; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_4}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_5}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_5}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_4}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_12}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_12}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_4}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_5}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_15}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_lo_16}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_71_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_16; // @[pla.scala:98:{53,70}]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_16 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_17 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_18 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_19 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_21 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_22 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_24 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_37 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_41 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_39 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_51 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_52 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_59 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_68 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_66 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_67 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_73 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_71 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_72 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_80 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_77 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_97 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_94 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_99 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_96 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_97 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_98 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_99 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_100 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_102 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_103 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_104 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_105 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_106 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_107 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_108 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_109 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_113 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_114 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_115 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_136 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_137 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_138 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_139 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_140 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_141 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_142 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_143 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_150 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_151 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_152 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_170 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_167 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_169 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_170 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_171 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_172 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_173 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_174 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_175 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_176 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_177 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_178 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_179 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_180 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_181 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_182 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_183 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_184 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_185 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_186 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_187 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_188 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_189 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17}; // @[pla.scala:91:29, :98:53]
wire [4:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_lo_17}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_181_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_17; // @[pla.scala:98:{53,70}]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_16 = id_ctrl_decoder_decoded_andMatrixOutputs_181_2; // @[pla.scala:98:70, :114:36]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18}; // @[pla.scala:91:29, :98:53]
wire [5:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_lo_18}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_145_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_18; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19}; // @[pla.scala:91:29, :98:53]
wire [5:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_lo_19}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_143_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_19; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_6}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_13}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_8}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_13}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20}; // @[pla.scala:91:29, :98:53]
wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_16}; // @[pla.scala:98:53]
wire [10:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_lo_20}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_20_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_20; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_14}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_9}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_14}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21}; // @[pla.scala:91:29, :98:53]
wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_17}; // @[pla.scala:98:53]
wire [10:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_lo_21}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_22_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_21; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_15}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_15}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_18}; // @[pla.scala:98:53]
wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_lo_22}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_97_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_22; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_10}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_19}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_16}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_19}; // @[pla.scala:98:53]
wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_lo_23}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_39_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_23; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_11}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_20}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_17}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_20}; // @[pla.scala:98:53]
wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_lo_24}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_131_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_24; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_8}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_21}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_18}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_18}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_21}; // @[pla.scala:98:53]
wire [9:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_lo_25}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_191_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_25; // @[pla.scala:98:{53,70}]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_63 = id_ctrl_decoder_decoded_andMatrixOutputs_191_2; // @[pla.scala:98:70, :114:36]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_22}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_22}; // @[pla.scala:98:53]
wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_lo_26}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_164_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_26; // @[pla.scala:98:{53,70}]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_64 = id_ctrl_decoder_decoded_andMatrixOutputs_164_2; // @[pla.scala:98:70, :114:36]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_20 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_97 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_87 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_99 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_89 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_90 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_91 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_92 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_93 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_170 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_160 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_14 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_96 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_68 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_98 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_70 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_71 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_72 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_73 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_74 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_170 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_141 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_23 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_10 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_93 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_48 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_95 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_50 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_51 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_52 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_53 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_54 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_169 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_121 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_19 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_9 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_86 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_45 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_88 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_47 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_51 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_166 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_118 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_13 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_7 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_67 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_42 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_69 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_44 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_48 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_159 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_115 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_6 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_2 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_40 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_14 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_42 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_16 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_114 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_62 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_5 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_1 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_38 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_7 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_40 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_9 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_111 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_38 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_5 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_1 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_32 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_5 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_34 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_7 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_109 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_25 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_1 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_1 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_13 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_5 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_15 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_7 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_96 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_18 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_1 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_6 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_4 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_8 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_6 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_61 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_16 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_1 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_35 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_65 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_43 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_6 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_6 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_110 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_111 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_135 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_136 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_124 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_125 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_126 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_146 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_155 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_107 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_113 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_113 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_147 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_148 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_130 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_131 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_135 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_136 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_134 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_138 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_136 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_137 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_1 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_34 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_45 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_40 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_3 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_3 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_90 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_91 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_92 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_93 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_114 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_115 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_116 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_117 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_104 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_105 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_106 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_147 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_148 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_108 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_106 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_110 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_110 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_17 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_7 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_127 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_128 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_168 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_169 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_170 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_171 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_172 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_173 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_174 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_126 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_127 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_132 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_133 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_130 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_135 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_132 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_133 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_1 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_32 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_42 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_39 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_3 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_3 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_5 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_5 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_64 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_87 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_88 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_89 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_90 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_94 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_95 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_96 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_97 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_101 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_102 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_103 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_127 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_128 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_129 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_104 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_105 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_103 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_107 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_15 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_7 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_124 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_125 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_149 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_150 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_151 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_152 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_153 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_154 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_155 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_124 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_125 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_128 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_129 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_128 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_131 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_130 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_131 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_1 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_26 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_39 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_37 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_3 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_3 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_5 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_5 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_51 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_84 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_85 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_86 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_87 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_91 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_92 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_93 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_94 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_98 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_99 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_100 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_107 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_108 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_109 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_101 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_102 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_101 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_104 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_121 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_122 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_129 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_130 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_131 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_132 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_133 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_134 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_135 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_111 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_112 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_126 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_127 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_115 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_129 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_117 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_118 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_1}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_1}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_5}; // @[pla.scala:98:53]
wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_19}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_6}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_5}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_8}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_13}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_5}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_23}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_6}; // @[pla.scala:98:53]
wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_23}; // @[pla.scala:98:53]
wire [27:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_lo_27}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_55_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_27; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_1}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_1}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_2}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_1}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_1}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_1}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_6}; // @[pla.scala:98:53]
wire [14:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_20}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_6}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_10}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_1}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_6}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_20}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_1}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_7}; // @[pla.scala:98:53]
wire [15:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_24}; // @[pla.scala:98:53]
wire [30:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_lo_28}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_90_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_28; // @[pla.scala:98:{53,70}]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_26 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_27 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_23 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_24 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_30 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_26 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_32 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_28 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_34 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_30 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_36 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_32 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_38 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_34 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_53 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_48 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_49 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_60 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_61 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_62 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_63 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_58 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_65 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_60 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_61 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_67 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_71 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_82 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_78 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_83 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_109 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_110 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_111 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_112 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_113 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_119 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_120 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_121 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_129 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_123 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_131 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_132 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_126 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_137 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_138 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_139 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_140 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_141 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_142 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_149 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_157 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_151 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_159 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_160 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_154 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_162 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_156 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_164 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_158 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_25}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_25}; // @[pla.scala:98:53]
wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_lo_29}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_30_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_29; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_21}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_21}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_26}; // @[pla.scala:98:53]
wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_lo_30}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_26_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_30; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_22}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_22}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_27}; // @[pla.scala:98:53]
wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_lo_31}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_175_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_31; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_15}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_28}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_23}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_28}; // @[pla.scala:98:53]
wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_lo_32}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_77_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_32; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_11}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_29}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_24}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_24}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_29}; // @[pla.scala:98:53]
wire [9:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_lo_33}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_21_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_33; // @[pla.scala:98:{53,70}]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_5 = id_ctrl_decoder_decoded_andMatrixOutputs_21_2; // @[pla.scala:98:70, :114:36]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_8}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_10}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_17}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_7}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_25}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_30}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_8}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_30}; // @[pla.scala:98:53]
wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_lo_34}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_121_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_34; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_8}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_9}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_13}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_8}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_26}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_26}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_7}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_9}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_31}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_lo_35}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_61_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_35; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_9}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_8}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_10}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_14}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_9}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_27}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_27}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_8}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_10}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_32}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_lo_36}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_105_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_36; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_10}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_3}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_11}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_15}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_10}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_28}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_28}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_9}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_11}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_33}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_lo_37}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_24_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_37; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_29}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_29}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_34}; // @[pla.scala:98:53]
wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_lo_38}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_165_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_38; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_21}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_35}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_30}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_35}; // @[pla.scala:98:53]
wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_lo_39}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_160_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_39; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_31}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_31}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_36}; // @[pla.scala:98:53]
wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_lo_40}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_95_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_40; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_22}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_37}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_32}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_37}; // @[pla.scala:98:53]
wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_lo_41}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_56_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_41; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_23}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_38}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_33}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_38}; // @[pla.scala:98:53]
wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_lo_42}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_16_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_42; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_34}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_42}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_34}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_39}; // @[pla.scala:98:53]
wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_lo_43}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_185_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_43; // @[pla.scala:98:{53,70}]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_6 = id_ctrl_decoder_decoded_andMatrixOutputs_185_2; // @[pla.scala:98:70, :114:36]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_43 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_41 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_42 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_37 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_38 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_39 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_46 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_41 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_42 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_43 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_44 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_45 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_46 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_47 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_32 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_33 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_62 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_63 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_70 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_65 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_66 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_48 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_72 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_83 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_79 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_85 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_94 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_103 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_104 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_116 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_127 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_109 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_161 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_43}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_40}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_40}; // @[pla.scala:98:53]
wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_lo_44}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_140_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_44; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_35}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_44}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_35}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_41}; // @[pla.scala:98:53]
wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_lo_45}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_53_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_45; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_36}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_45}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_36}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_42}; // @[pla.scala:98:53]
wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_lo_46}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_193_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_46; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_24}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_43}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_37}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_43}; // @[pla.scala:98:53]
wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_lo_47}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_92_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_47; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_38}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_47}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_38}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_44}; // @[pla.scala:98:53]
wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_lo_48}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_17_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_48; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_25}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_45}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_39}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_45}; // @[pla.scala:98:53]
wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_lo_49}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_129_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_49; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_40}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_49}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_40}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_46}; // @[pla.scala:98:53]
wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_lo_50}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_177_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_50; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_26}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_47}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_41}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_47}; // @[pla.scala:98:53]
wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_lo_51}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_123_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_51; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_14}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_42}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_27}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_42}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_51}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52}; // @[pla.scala:90:45, :98:53]
wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_48}; // @[pla.scala:98:53]
wire [10:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_lo_52}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_14_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_52; // @[pla.scala:98:{53,70}]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_27 = id_ctrl_decoder_decoded_andMatrixOutputs_14_2; // @[pla.scala:98:70, :114:36]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_11}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_10}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_12}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_17}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_11}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_43}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_43}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_52}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_10}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_12}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_49}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_lo_53}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_132_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_53; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_4}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_12}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_4}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_13}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_18}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_12}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_44}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_44}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_53}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_11}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_13}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_50}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_lo_54}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_49_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_54; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_45}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_54}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_45}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_51}; // @[pla.scala:98:53]
wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_lo_55}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_155_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_55; // @[pla.scala:98:{53,70}]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_7 = id_ctrl_decoder_decoded_andMatrixOutputs_155_2; // @[pla.scala:98:70, :114:36]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_30}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_52}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_46}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_56}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_52}; // @[pla.scala:98:53]
wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_lo_56}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_184_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_56; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_31}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_53}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_47}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_57}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_53}; // @[pla.scala:98:53]
wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_lo_57}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_148_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_57; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_32}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_54}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_48}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_58}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_54}; // @[pla.scala:98:53]
wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_lo_58}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_115_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_58; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_13}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_12}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_14}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_19}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_13}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_49}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_49}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_58}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_12}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_14}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_55}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_lo_59}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_162_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_59; // @[pla.scala:98:{53,70}]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_34 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_51 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_52 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_53 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_37 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_38 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_39 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_40 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_41 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_59 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_42 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_43 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_44 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_45 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_64 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_46 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_47 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_28 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_73 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_81 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_75 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_76 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_41 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_81 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_63 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_64 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_105 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_74 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_117 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_99 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_80 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_81 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_82 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_103 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_84 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_105 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_106 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_87 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_108 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_89 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_117 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_138 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_119 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_34}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_56}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_50}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_60}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_56}; // @[pla.scala:98:53]
wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_lo_60}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_44_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_60; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_15}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_14}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_18}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_35}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_14}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_51}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_60}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_57}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_15}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_57}; // @[pla.scala:98:53]
wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_lo_61}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_126_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_61; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_16}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_15}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_19}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_36}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_15}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_52}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_61}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_58}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_16}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_58}; // @[pla.scala:98:53]
wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_lo_62}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_150_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_62; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_53}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_62}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_53}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_59}; // @[pla.scala:98:53]
wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_lo_63}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_161_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_63; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_16}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_13}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_17}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_22}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_16}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_54}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_54}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_63}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_13}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_17}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_60}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_lo_64}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_133_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_64; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_17}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_14}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_18}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_23}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_17}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_55}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_55}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_64}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_14}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_65}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_18}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_61}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_lo_65}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_179_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_65; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_5}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_18}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_5}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_19}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_24}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_18}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_56}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_56}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_65}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_15}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_66}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_66}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_19}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_62}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_lo_66}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_5_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_66; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_19}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_16}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_20}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_25}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_19}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_57}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_57}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_66}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_16}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_67}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_67}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_20}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_63}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_lo_67}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_88_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_67; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_20}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_17}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_21}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_26}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_20}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_58}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_58}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_67}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_17}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_68}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_68}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_21}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_64}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_lo_68}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_94_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_68; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_59}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_68}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_59}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_69}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_69}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_65}; // @[pla.scala:98:53]
wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_lo_69}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_66_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_69; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_42}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_66}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_60}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_70}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_70}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_70}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_66}; // @[pla.scala:98:53]
wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_lo_70}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_125_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_70; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_43}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_67}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_61}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_71}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_71}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_71}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_67}; // @[pla.scala:98:53]
wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_lo_71}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_91_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_71; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_44}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_68}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_62}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_72}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_72}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_72}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_68}; // @[pla.scala:98:53]
wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_lo_72}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_112_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_72; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_21}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_18}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_22}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_27}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_21}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_63}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_63}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_72}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_18}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_73}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_73}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_22}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_69}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_lo_73}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_170_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_73; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_64}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_73}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_64}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_74}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_74}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_70}; // @[pla.scala:98:53]
wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_lo_74}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_146_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_74; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_46}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_71}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_65}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_75}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_75}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_75}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_71}; // @[pla.scala:98:53]
wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_lo_75}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_168_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_75; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_47}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_72}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_66}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_76}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_76}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_76}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_72}; // @[pla.scala:98:53]
wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_lo_76}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_2_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_76; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_28}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_73}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_67}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_67}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_77}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_77}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_77}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_73}; // @[pla.scala:98:53]
wire [9:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_lo_77}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_15_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_77; // @[pla.scala:98:{53,70}]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_68 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_50 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_79 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_70 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_52 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_53 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_54 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_74 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_56 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_57 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_62 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_43 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_44 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_48 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_46 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_44 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_20 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_67 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_68 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_69 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_88 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_89 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_97 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_60 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_10 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_7 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_130 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_74 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_116 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_23}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_22}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_26}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_49}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_22}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_68}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_77}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_74}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_78}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_78}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_23}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_74}; // @[pla.scala:98:53]
wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_lo_78}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_176_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_78; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_23}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_19}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_24}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_30}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_23}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_69}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_69}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_78}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_19}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_79}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_79}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_24}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_75}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_lo_79}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_172_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_79; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_79}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_76}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_80}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_80}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_76}; // @[pla.scala:98:53]
wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_lo_80}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_76_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_80; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_28}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_25}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_70}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_51}; // @[pla.scala:91:29, :98:53]
wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_70}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_81}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_80}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_81}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_81}; // @[pla.scala:91:29, :98:53]
wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_77}; // @[pla.scala:98:53]
wire [11:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_lo_81}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_87_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_81; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_24}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_20}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_26}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_32}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_24}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_71}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_71}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_81}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_20}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_82}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_82}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_25}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_78}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_lo_82}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_144_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_82; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_25}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_21}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_27}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_33}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_25}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_72}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_72}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_82}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_21}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_83}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_83}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_26}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_79}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_lo_83}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_36_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_83; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_27}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_26}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_31}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_54}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_26}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_73}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_83}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_80}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_84}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_84}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_27}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_80}; // @[pla.scala:98:53]
wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_lo_84}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_41_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_84; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_28}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_27}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_32}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_55}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_27}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_74}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_84}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_81}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_85}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_85}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_28}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_81}; // @[pla.scala:98:53]
wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_lo_85}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_8_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_85; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_28}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_22}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_30}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_36}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_28}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_75}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_75}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_85}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_22}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_86}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_86}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_29}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_82}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_lo_86}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_104_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_86; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_29}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_23}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_31}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_37}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_29}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_76}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_76}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_86}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_23}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_87}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_87}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_30}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_83}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_lo_87}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_73_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_87; // @[pla.scala:98:{53,70}]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_31 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_33 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_40 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_2 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_39 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_37 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_38 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_55 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_64 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_65 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_64 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_65 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_11 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_92 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_96 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_94 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_92 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_96 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_94 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_93 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_94 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_82 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_23 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_6 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_7 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_24}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_6}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_31}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_35}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_30}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_77}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_58}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_84}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_24}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_88}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_88}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_88}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_31}; // @[pla.scala:98:53]
wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_84}; // @[pla.scala:98:53]
wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_lo_88}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_189_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_88; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_31}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_7}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_33}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_39}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_31}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_78}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_78}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_88}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_25}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_89}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_89}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_32}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_85}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_lo_89}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_28_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_89; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_34}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_33}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_60}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_40}; // @[pla.scala:90:45, :98:53]
wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_79}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_89}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_86}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_90}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_90}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_33}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_86}; // @[pla.scala:98:53]
wire [12:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_lo_90}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_0_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_90; // @[pla.scala:98:{53,70}]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_38 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_84 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_46 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_4 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_4 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_131 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_132 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_133 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_134 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_143 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_144 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_145 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_154 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_111 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_109 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_116 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_37 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_12 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_166 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_167 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_133 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_134 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_138 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_139 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_137 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_141 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_139 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_140 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_2}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_2}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_8}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_8}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_34}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_32}; // @[pla.scala:91:29, :98:53]
wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_32}; // @[pla.scala:98:53]
wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_80}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_38}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_80}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_61}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_26}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_91}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_90}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_91}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_91}; // @[pla.scala:91:29, :98:53]
wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_34}; // @[pla.scala:98:53]
wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_87}; // @[pla.scala:98:53]
wire [21:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_lo_91}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_60_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_91; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_33}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_27}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_36}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_42}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_33}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_81}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_81}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_91}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_27}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_92}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_92}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_35}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_88}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_lo_92}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_48_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_92; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_9}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_34}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_9}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_37}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_43}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_34}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_82}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_82}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_92}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_28}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_93}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_93}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_36}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_89}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_lo_93}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_167_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_93; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_10}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_35}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_10}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_38}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_44}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_35}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_83}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_83}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_93}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_29}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_94}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_94}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_37}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_90}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_lo_94}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_163_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_94; // @[pla.scala:98:{53,70}]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_36 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_12 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_2 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_1 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_4 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_2 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_42 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_37 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_12 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_9 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_52 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_80 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_81 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_48 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_6 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_3 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_124 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_125 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_32 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_33 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_4}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_30}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_11}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_38}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_42}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_36}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_84}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_65}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_91}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_30}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_95}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_95}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_95}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_38}; // @[pla.scala:98:53]
wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_91}; // @[pla.scala:98:53]
wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_lo_95}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_137_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_95; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_5}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_12}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_31}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_40}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_39}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_37}; // @[pla.scala:98:53]
wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_85}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_46}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_92}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_85}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_31}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_96}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_96}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_96}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_39}; // @[pla.scala:98:53]
wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_92}; // @[pla.scala:98:53]
wire [18:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_lo_96}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_74_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_96; // @[pla.scala:98:{53,70}]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_4 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_4 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_68 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_112 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_113 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_24 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_11 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_2}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_2}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_2}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_13}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_3}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_4}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_13}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_2}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_38}; // @[pla.scala:98:53]
wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_86}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_40}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_38}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_44}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_67}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_2}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_32}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_96}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_93}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_97}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_97}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_2}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_40}; // @[pla.scala:98:53]
wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_93}; // @[pla.scala:98:53]
wire [27:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_lo_97}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_59_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_97; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_1}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_3}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_3}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_14}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_4}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_1}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_4}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_5}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_3}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_39}; // @[pla.scala:98:53]
wire [14:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_87}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_14}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_39}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_1}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_42}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_48}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_3}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_33}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_87}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_97}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_1}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_98}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_98}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_3}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_41}; // @[pla.scala:98:53]
wire [15:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_94}; // @[pla.scala:98:53]
wire [30:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_lo_98}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_152_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_98; // @[pla.scala:98:{53,70}]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_6 = id_ctrl_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_6 = id_ctrl_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_71 = id_ctrl_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_129 = id_ctrl_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_130 = id_ctrl_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_5 = id_ctrl_decoder_decoded_plaInput[22]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_5 = id_ctrl_decoder_decoded_plaInput[22]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_66 = id_ctrl_decoder_decoded_plaInput[22]; // @[pla.scala:77:22, :90:45]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_4}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_4}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_4}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_4}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_4}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_15}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_5}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_5}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_6}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_15}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_4}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_40}; // @[pla.scala:98:53]
wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_88}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_42}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_40}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_46}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_69}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_4}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_34}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_98}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_95}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_99}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_99}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_4}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_42}; // @[pla.scala:98:53]
wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_95}; // @[pla.scala:98:53]
wire [27:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_lo_99}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_47_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_99; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_2}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_5}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_5}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_5}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_16}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_5}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_6}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_2}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_6}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_7}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_5}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_41}; // @[pla.scala:98:53]
wire [14:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_89}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_16}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_41}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_2}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_44}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_50}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_5}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_35}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_89}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_99}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_2}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_100}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_100}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_5}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_43}; // @[pla.scala:98:53]
wire [15:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_96}; // @[pla.scala:98:53]
wire [30:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_lo_100}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_103_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_100; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_10}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_36}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_17}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_44}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_48}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_42}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_90}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_71}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_97}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_36}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_101}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_101}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_101}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_44}; // @[pla.scala:98:53]
wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_97}; // @[pla.scala:98:53]
wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_lo_101}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_83_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_101; // @[pla.scala:98:{53,70}]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_28 = id_ctrl_decoder_decoded_andMatrixOutputs_83_2; // @[pla.scala:98:70, :114:36]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_8}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_18}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_18}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_43}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_49}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_46}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_43}; // @[pla.scala:98:53]
wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_91}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_72}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_98}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_37}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_102}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_102}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_102}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_45}; // @[pla.scala:98:53]
wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_98}; // @[pla.scala:98:53]
wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_lo_102}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_31_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_102; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_12}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_9}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_19}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_38}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_47}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_46}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_44}; // @[pla.scala:98:53]
wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_92}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_53}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_99}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_92}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_38}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_103}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_103}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_103}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_46}; // @[pla.scala:98:53]
wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_99}; // @[pla.scala:98:53]
wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_lo_103}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_13_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_103; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_9}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_8}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_20}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_20}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_13}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_47}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_45}; // @[pla.scala:91:29, :98:53]
wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_45}; // @[pla.scala:98:53]
wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_93}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_51}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_93}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_74}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_39}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_104, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_104}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_103}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_104, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_104}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_104}; // @[pla.scala:91:29, :98:53]
wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_47}; // @[pla.scala:98:53]
wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_100}; // @[pla.scala:98:53]
wire [21:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_lo_104}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_111_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_104; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_48}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_46}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_52}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_75}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_46}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_94}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_104}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_101}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_105}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_105}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_48}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_101}; // @[pla.scala:98:53]
wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_lo_105}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_65_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_105; // @[pla.scala:98:{53,70}]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_49 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_50 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_51 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_52 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_54 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_55 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_55 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_56 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_58 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_57 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_58 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_57 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_58 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_61 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_60 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_61 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_49 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_50 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_9 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_83 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_84 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_85 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_19 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_20 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_14 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_22 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_105 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_104 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_105 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_106 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_107 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_14 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_6 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_3 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_113 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_114 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_115 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_116 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_26 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_27 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_28 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_29 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_23 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_24 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_25 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_26 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_49}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_47}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_53}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_76}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_47}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_95}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_105}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_102}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_106}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_106}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_49}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_102}; // @[pla.scala:98:53]
wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_lo_106}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_124_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_106; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_50}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_48}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_54}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_77}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_48}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_96}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_106}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_103}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_107}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_107}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_50}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_103}; // @[pla.scala:98:53]
wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_lo_107}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_50_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_107; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_51}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_49}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_55}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_78}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_49}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_97}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_107}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_104}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_108}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_108}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_51}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_104}; // @[pla.scala:98:53]
wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_lo_108}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_6_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_108; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_52}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_50}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_56}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_79}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_50}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_98}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_108}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_105}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_109}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_109}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_52}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_105}; // @[pla.scala:98:53]
wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_lo_109}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_134_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_109; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_53}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_51}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_57}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_80}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_51}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_99}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_109}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_106}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_110}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_110}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_53}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_106}; // @[pla.scala:98:53]
wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_lo_110}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_153_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_110; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_54}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_52}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_58}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_81}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_52}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_100}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_110}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_107}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_111}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_111}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_54}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_107}; // @[pla.scala:98:53]
wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_lo_111}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_109_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_111; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_53}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_40}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_56}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_62}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_53}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_101}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_101}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_111}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_40}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_112}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_112}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_55}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_108}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_lo_112}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_187_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_112; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_54}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_41}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_57}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_63}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_54}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_102}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_102}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_112}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_41}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_113}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_113}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_56}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_109}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_lo_113}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_45_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_113; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_61}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_58}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_103}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_84}; // @[pla.scala:91:29, :98:53]
wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_103}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_114}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_113}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_114}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_114}; // @[pla.scala:90:45, :98:53]
wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_110}; // @[pla.scala:98:53]
wire [11:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_lo_114}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_79_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_114; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_55}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_42}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_59}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_65}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_55}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_104}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_104}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_114}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_42}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_115}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_115}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_57}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_111}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_lo_115}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_159_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_115; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_56}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_43}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_60}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_66}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_56}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_105}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_105}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_115}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_43}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_116}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_116}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_58}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_112}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_lo_116}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_34_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_116; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_57}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_44}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_61}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_67}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_57}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_106}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_106}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_116}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_44}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_117}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_117}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_59}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_113}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_lo_117}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_86_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_117; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_58}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_45}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_62}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_68}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_58}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_107}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_107}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_117}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_45}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_118}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_118}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_60}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_114}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_lo_118}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_10_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_118; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_59}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_46}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_63}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_69}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_59}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_108}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_108}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_118}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_46}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_119}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_119}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_61}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_115}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_lo_119}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_93_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_119; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_60}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_47}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_64}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_70}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_60}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_109}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_109}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_119}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_47}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_120}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_120}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_62}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_116}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_lo_120}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_180_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_120; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_21}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_61}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_21}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_65}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_71}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_61}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_110}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_110}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_120}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_48}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_121}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_121}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_63}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_117}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_lo_121}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_43_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_121; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_22}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_62}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_22}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_66}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_72}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_62}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_111}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_111}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_121}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_49}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_122}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_122}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_64}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_118}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_lo_122}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_135_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_122; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_14}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_50}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_23}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_65}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_70}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_63}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_112}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_93}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_119}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_50}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_123}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_123}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_123}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_65}; // @[pla.scala:98:53]
wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_119}; // @[pla.scala:98:53]
wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_lo_123}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_3_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_123; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_8}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_10}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_9}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_24}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_24}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_15}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_66}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_64}; // @[pla.scala:91:29, :98:53]
wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_64}; // @[pla.scala:98:53]
wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_113}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_71}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_113}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_94}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_51}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_124}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_123}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_124}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_124}; // @[pla.scala:91:29, :98:53]
wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_66}; // @[pla.scala:98:53]
wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_120}; // @[pla.scala:98:53]
wire [21:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_lo_124}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_188_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_124; // @[pla.scala:98:{53,70}]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_52 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_53 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_71 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_67 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_55 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_69 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_70 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_58 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_72 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_60 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_61 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_75 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_63 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_64 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_33 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_17 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_18 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_19 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_20 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_21 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_22 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_23 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_24 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_87 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_88 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_76 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_77 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_78 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_45 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_26 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_27 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_18 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_49 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_50 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_51 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_12 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_13 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_12 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_15 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_103 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_91 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_92 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_93 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_94 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_10 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_6 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_3 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_102 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_103 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_117 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_118 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_106 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_107 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_108 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_109 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_110 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_19 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_20 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_21 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_22 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_21 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_22 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_23 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_24 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_25}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_65}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_25}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_69}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_75}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_65}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_114}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_114}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_124}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_52}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_125}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_125}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_67}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_121}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_lo_125}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_4_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_125; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_26}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_66}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_26}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_70}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_76}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_66}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_115}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_115}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_125}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_53}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_126}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_126}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_68}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_122}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_lo_126}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_25_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_126; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_74}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_71}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_116}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_97}; // @[pla.scala:91:29, :98:53]
wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_116}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_127, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_127}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_126}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_127, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_127}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_127}; // @[pla.scala:90:45, :98:53]
wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_123}; // @[pla.scala:98:53]
wire [11:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_lo_127}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_58_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_127; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_67}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_54}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_72}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_78}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_67}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_117}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_117}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_127}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_54}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_128}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_128}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_69}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_124}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_lo_128}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_147_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_128; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_27}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_68}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_27}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_73}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_79}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_68}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_118}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_118}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_128}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_55}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_129}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_129}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_70}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_125}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_lo_129}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_27_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_129; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_69}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_56}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_74}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_80}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_69}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_119}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_119}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_129}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_56}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_130}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_130}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_71}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_126}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_lo_130}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_52_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_130; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_70}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_57}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_75}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_81}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_70}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_120}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_127, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_120}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_130}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_57}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_131}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_131}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_72}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_127}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_lo_131}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_138_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_131; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_28}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_71}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_28}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_76}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_82}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_71}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_121}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_121}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_131}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_58}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_132}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_132}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_73}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_128}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_lo_132}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_178_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_132; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_72}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_59}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_77}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_83}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_72}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_122}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_122}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_132}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_59}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_133}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_133}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_74}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_129}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_lo_133}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_173_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_133; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_29}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_73}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_29}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_78}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_104, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_84}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_73}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_123}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_123}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_133}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_60}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_134}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_134}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_75}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_130}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_lo_134}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_120_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_134; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_30}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_74}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_30}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_79}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_85}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_74}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_124}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_124}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_134}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_61}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_135}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_135}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_76}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_131}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_lo_135}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_19_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_135; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_75}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_62}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_80}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_86}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_75}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_125}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_125}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_135}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_62}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_136}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_136}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_77}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_132}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_lo_136}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_64_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_136; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_31}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_76}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_31}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_81}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_87}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_76}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_126}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_126}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_137, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_136}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_63}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_137, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_137}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_137, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_137}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_78}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_133}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_lo_137}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_142_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_137; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_32}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_77}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_32}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_82}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_88}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_77}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_127}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_127}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_138, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_137}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_64}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_138, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_138}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_138, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_138}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_79}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_134}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_lo_138}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_11_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_138; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_16}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_65}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_33}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_80}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_86}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_78}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_128}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_109}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_138, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_135}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_65}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_139, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_139}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_139, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_139}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_139}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_80}; // @[pla.scala:98:53]
wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_135}; // @[pla.scala:98:53]
wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_lo_139}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_46_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_139; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_17}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_66}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_34}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_81}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_87}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_79}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_129}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_110}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_139, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_136}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_66}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_140, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_140}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_140, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_140}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_140}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_81}; // @[pla.scala:98:53]
wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_136}; // @[pla.scala:98:53]
wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_lo_140}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_141_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_140; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_12}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_35}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_35}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_80}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_88}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_85}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_80}; // @[pla.scala:98:53]
wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_130}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_111}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_140, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_137}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_67}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_141, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_141}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_141, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_141}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_141}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_82}; // @[pla.scala:98:53]
wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_141, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_137}; // @[pla.scala:98:53]
wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_141, id_ctrl_decoder_decoded_andMatrixOutputs_lo_141}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_114_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_141; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_19}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_68}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_36}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_83}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_89}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_81}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_141, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_131}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_112}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_141, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_138}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_68}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_142}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_142}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_142}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_83}; // @[pla.scala:98:53]
wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_142, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_138}; // @[pla.scala:98:53]
wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_142, id_ctrl_decoder_decoded_andMatrixOutputs_lo_142}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_70_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_142; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_13}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_37}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_37}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_82}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_90}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_87}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_82}; // @[pla.scala:98:53]
wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_142, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_132}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_113}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_139}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_69}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_143}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_143}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_143}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_84}; // @[pla.scala:98:53]
wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_143, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_139}; // @[pla.scala:98:53]
wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_143, id_ctrl_decoder_decoded_andMatrixOutputs_lo_143}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_72_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_143; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_21}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_70}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_38}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_85}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_91}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_83}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_143, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_133}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_114}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_140}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_70}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_144}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_144}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_144}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_85}; // @[pla.scala:98:53]
wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_144, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_140}; // @[pla.scala:98:53]
wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_144, id_ctrl_decoder_decoded_andMatrixOutputs_lo_144}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_174_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_144; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_14}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_39}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_39}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_84}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_92}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_89}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_84}; // @[pla.scala:98:53]
wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_144, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_134}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_115}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_141}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_71}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_145, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_145}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_145, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_145}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_145}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_86}; // @[pla.scala:98:53]
wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_145, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_141}; // @[pla.scala:98:53]
wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_145, id_ctrl_decoder_decoded_andMatrixOutputs_lo_145}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_81_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_145; // @[pla.scala:98:{53,70}]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_87 = id_ctrl_decoder_decoded_plaInput[26]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_88 = id_ctrl_decoder_decoded_plaInput[26]; // @[pla.scala:77:22, :90:45]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_23}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_72}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_40}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_87}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_93}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_85}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_145, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_135}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_116}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_145, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_142}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_72}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_146}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_146}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_146}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_87}; // @[pla.scala:98:53]
wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_146, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_142}; // @[pla.scala:98:53]
wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_146, id_ctrl_decoder_decoded_andMatrixOutputs_lo_146}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_130_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_146; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_15}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_41}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_41}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_86}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_94}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_91}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_86}; // @[pla.scala:98:53]
wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_146, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_136}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_117}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_143}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_73}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_147, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_147}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_147, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_147}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_147}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_88}; // @[pla.scala:98:53]
wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_147, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_143}; // @[pla.scala:98:53]
wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_147, id_ctrl_decoder_decoded_andMatrixOutputs_lo_147}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_157_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_147; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_87}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_74}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_92}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_98}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_87}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_147, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_137}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_137}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_147}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_74}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_148}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_148}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_89}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_148, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_144}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_148, id_ctrl_decoder_decoded_andMatrixOutputs_lo_148}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_68_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_148; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_88}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_75}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_93}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_99}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_88}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_148, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_138}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_145, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_138}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_149, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_148}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_75}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_149, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_149}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_149, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_149}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_90}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_149, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_145}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_149, id_ctrl_decoder_decoded_andMatrixOutputs_lo_149}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_42_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_149; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_42}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_89}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_42}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_94}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_100}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_89}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_149, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_139}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_139}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_150, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_149}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_76}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_150, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_150}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_150, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_150}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_91}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_150, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_146}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_150, id_ctrl_decoder_decoded_andMatrixOutputs_lo_150}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_54_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_150; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_43}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_90}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_43}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_95}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_101}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_90}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_150, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_140}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_147, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_140}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_151, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_150}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_77}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_151, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_151}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_151, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_151}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_92}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_151, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_147}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_151, id_ctrl_decoder_decoded_andMatrixOutputs_lo_151}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_63_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_151; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_44}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_91}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_44}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_96}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_102}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_91}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_151, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_141}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_141}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_152, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_151}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_78}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_152, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_152}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_152, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_152}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_93}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_152, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_148}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_152, id_ctrl_decoder_decoded_andMatrixOutputs_lo_152}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_69_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_152; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_25}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_79}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_45}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_94}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_100}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_92}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_152, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_142}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_123}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_152, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_149}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_79}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_153, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_153}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_153, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_153}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_153}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_94}; // @[pla.scala:98:53]
wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_153, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_149}; // @[pla.scala:98:53]
wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_153, id_ctrl_decoder_decoded_andMatrixOutputs_lo_153}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_183_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_153; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_16}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_46}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_46}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_93}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_104, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_101}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_98}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_93}; // @[pla.scala:98:53]
wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_153, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_143}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_124}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_153, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_150}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_80}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_154, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_154}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_154, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_154}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_154}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_95}; // @[pla.scala:98:53]
wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_154, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_150}; // @[pla.scala:98:53]
wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_154, id_ctrl_decoder_decoded_andMatrixOutputs_lo_154}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_51_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_154; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_17}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_47}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_47}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_94}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_102}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_99}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_94}; // @[pla.scala:98:53]
wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_154, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_144}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_125}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_154, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_151}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_81}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_155, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_155}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_155, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_155}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_155}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_96}; // @[pla.scala:98:53]
wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_155, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_151}; // @[pla.scala:98:53]
wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_155, id_ctrl_decoder_decoded_andMatrixOutputs_lo_155}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_136_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_155; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_11}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_28}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_48}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_82}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_100}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_97}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_95}; // @[pla.scala:98:53]
wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_155, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_145}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_106}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_155, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_152}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_145}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_82}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_156, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_156}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_156, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_156}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_156}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_97}; // @[pla.scala:98:53]
wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_156, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_152}; // @[pla.scala:98:53]
wire [18:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_156, id_ctrl_decoder_decoded_andMatrixOutputs_lo_156}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_127_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_156; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_29}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_83}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_49}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_98}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_104}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_96}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_156, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_146}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_127}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_156, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_153}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_83}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_157, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_157}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_157, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_157}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_157}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_98}; // @[pla.scala:98:53]
wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_157, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_153}; // @[pla.scala:98:53]
wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_157, id_ctrl_decoder_decoded_andMatrixOutputs_lo_157}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_151_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_157; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_30}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_84}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_50}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_99}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_105}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_97}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_157, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_147}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_147, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_128}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_157, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_154}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_84}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_158, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_158}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_158, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_158}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_158}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_99}; // @[pla.scala:98:53]
wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_158, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_154}; // @[pla.scala:98:53]
wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_158, id_ctrl_decoder_decoded_andMatrixOutputs_lo_158}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_1_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_158; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_31}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_85}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_51}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_100}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_106}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_98}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_158, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_148}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_129}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_158, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_155}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_85}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_159, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_159}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_159, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_159}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_159}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_100}; // @[pla.scala:98:53]
wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_159, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_155}; // @[pla.scala:98:53]
wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_159, id_ctrl_decoder_decoded_andMatrixOutputs_lo_159}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_100_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_159; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_10}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_32}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_19}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_52}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_86}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_104}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_101}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_99}; // @[pla.scala:98:53]
wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_159, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_149}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_110}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_159, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_156}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_149}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_86}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_160, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_160}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_160, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_160}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_160}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_101}; // @[pla.scala:98:53]
wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_160, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_156}; // @[pla.scala:98:53]
wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_160, id_ctrl_decoder_decoded_andMatrixOutputs_lo_160}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_106_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_160; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_11}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_33}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_20}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_53}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_87}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_105}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_102}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_100}; // @[pla.scala:98:53]
wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_160, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_150}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_111}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_160, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_157}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_150}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_87}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_161, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_161}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_161, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_161}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_161}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_102}; // @[pla.scala:98:53]
wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_161, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_157}; // @[pla.scala:98:53]
wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_161, id_ctrl_decoder_decoded_andMatrixOutputs_lo_161}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_186_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_161; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_9}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_21}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_14}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_54}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_54}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_103}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_101}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_101}; // @[pla.scala:98:53]
wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_161, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_151}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_109}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_158, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_151}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_132}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_88}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_162, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_162}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_161}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_162, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_162}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_162}; // @[pla.scala:91:29, :98:53]
wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_103}; // @[pla.scala:98:53]
wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_162, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_158}; // @[pla.scala:98:53]
wire [20:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_162, id_ctrl_decoder_decoded_andMatrixOutputs_lo_162}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_18_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_162; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_13}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_35}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_22}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_55}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_89}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_107}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_104}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_102}; // @[pla.scala:98:53]
wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_162, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_152}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_113}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_162, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_159}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_152}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_89}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_163, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_163}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_163, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_163}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_163}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_104}; // @[pla.scala:98:53]
wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_163, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_159}; // @[pla.scala:98:53]
wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_163, id_ctrl_decoder_decoded_andMatrixOutputs_lo_163}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_108_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_163; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_103}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_90}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_108}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_114}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_103}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_163, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_153}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_160, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_153}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_164, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_163}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_90}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_164, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_164}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_164, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_164}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_105}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_164, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_160}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_164, id_ctrl_decoder_decoded_andMatrixOutputs_lo_164}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_89_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_164; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_56}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_104}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_56}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_109}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_115}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_104}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_164, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_154}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_161, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_154}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_165, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_164}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_91}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_165, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_165}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_165, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_165}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_106}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_165, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_161}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_165, id_ctrl_decoder_decoded_andMatrixOutputs_lo_165}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_62_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_165; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_57}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_105}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_57}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_110}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_116}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_105}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_165, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_155}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_162, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_155}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_166, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_165}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_92}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_166, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_166}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_166, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_166}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_107}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_166, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_162}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_166, id_ctrl_decoder_decoded_andMatrixOutputs_lo_166}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_149_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_166; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_58}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_106}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_58}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_111}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_137, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_117}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_106}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_166, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_156}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_163, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_156}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_167, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_166}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_93}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_167, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_167}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_167, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_167}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_108}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_167, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_163}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_167, id_ctrl_decoder_decoded_andMatrixOutputs_lo_167}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_171_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_167; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_59}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_107}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_59}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_112}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_138, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_118}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_107}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_167, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_157}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_164, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_157}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_168, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_167}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_94}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_168, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_168}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_168, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_168}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_109}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_168, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_164}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_168, id_ctrl_decoder_decoded_andMatrixOutputs_lo_168}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_37_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_168; // @[pla.scala:98:{53,70}]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_108 = id_ctrl_decoder_decoded_plaInput[23]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_95 = id_ctrl_decoder_decoded_plaInput[24]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_11 = id_ctrl_decoder_decoded_plaInput[24]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_7 = id_ctrl_decoder_decoded_plaInput[24]; // @[pla.scala:77:22, :90:45]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_9}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_16}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_14}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_60}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_60}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_36}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_110}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_108}; // @[pla.scala:90:45, :98:53]
wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_108}; // @[pla.scala:98:53]
wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_168, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_158}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_116}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_165, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_158}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_139}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_95}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_169, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_169}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_168}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_169, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_169}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_169}; // @[pla.scala:91:29, :98:53]
wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_110}; // @[pla.scala:98:53]
wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_169, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_165}; // @[pla.scala:98:53]
wire [21:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_169, id_ctrl_decoder_decoded_andMatrixOutputs_lo_169}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_122_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_169; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_6}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_6}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_6}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_6}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_6}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_61}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_15}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_11}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_24}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_61}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_6}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_109}; // @[pla.scala:98:53]
wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_169, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_159}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_111}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_109}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_117}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_159, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_140}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_6}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_96}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_170, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_169}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_166}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_170, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_170}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_170, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_170}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_6}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_111}; // @[pla.scala:98:53]
wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_170, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_166}; // @[pla.scala:98:53]
wire [27:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_170, id_ctrl_decoder_decoded_andMatrixOutputs_lo_170}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_82_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_170; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_31}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_3}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_7}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_7}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_7}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_62}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_11}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_3}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_16}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_25}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_7}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_110}; // @[pla.scala:98:53]
wire [15:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_170, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_160}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_62}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_110}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_3}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_115}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_141, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_121}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_7}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_97}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_167, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_160}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_171, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_170}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_3}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_171, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_171}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_171, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_171}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_7}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_141, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_112}; // @[pla.scala:98:53]
wire [15:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_171, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_167}; // @[pla.scala:98:53]
wire [31:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_171, id_ctrl_decoder_decoded_andMatrixOutputs_lo_171}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_119_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_171; // @[pla.scala:98:{53,70}]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_116 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_98 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_99 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_100 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_101 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_63 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_64 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_104 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_105 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_65 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_66 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_67 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_68 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_69 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_17 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_18 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_19 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_20 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_13 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_14 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_15 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_16 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_119}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_116}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_168, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_161}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_142}; // @[pla.scala:91:29, :98:53]
wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_171, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_161}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_172, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_172}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_171}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_172, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_172}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_172}; // @[pla.scala:90:45, :98:53]
wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_172, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_168}; // @[pla.scala:98:53]
wire [11:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_172, id_ctrl_decoder_decoded_andMatrixOutputs_lo_172}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_169_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_172; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_111}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_98}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_117}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_123}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_111}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_172, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_162}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_169, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_162}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_173, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_172}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_98}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_173, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_173}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_173, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_173}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_143, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_113}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_173, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_169}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_173, id_ctrl_decoder_decoded_andMatrixOutputs_lo_173}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_57_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_173; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_112}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_99}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_118}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_124}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_112}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_173, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_163}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_170, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_163}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_174, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_173}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_99}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_174, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_174}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_174, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_174}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_144, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_114}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_174, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_170}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_174, id_ctrl_decoder_decoded_andMatrixOutputs_lo_174}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_80_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_174; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_113}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_100}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_119}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_145, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_125}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_113}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_174, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_164}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_171, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_164}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_175, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_174}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_100}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_175, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_175}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_175, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_175}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_145, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_115}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_175, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_171}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_175, id_ctrl_decoder_decoded_andMatrixOutputs_lo_175}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_166_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_175; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_114}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_101}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_120}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_126}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_114}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_175, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_165}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_172, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_165}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_176, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_175}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_101}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_176, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_176}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_176, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_176}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_146, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_116}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_176, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_172}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_176, id_ctrl_decoder_decoded_andMatrixOutputs_lo_176}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_154_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_176; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_63}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_115}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_63}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_121}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_147, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_127}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_115}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_176, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_166}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_173, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_166}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_177, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_176}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_102}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_177, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_177}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_177, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_177}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_147, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_117}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_177, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_173}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_177, id_ctrl_decoder_decoded_andMatrixOutputs_lo_177}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_192_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_177; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_64}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_116}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_64}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_122}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_128}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_116}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_177, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_167}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_174, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_167}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_178, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_177}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_103}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_178, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_178}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_178, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_178}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_148, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_118}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_178, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_174}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_178, id_ctrl_decoder_decoded_andMatrixOutputs_lo_178}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_38_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_178; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_117}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_104}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_123}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_149, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_129}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_117}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_178, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_168}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_175, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_168}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_179, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_178}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_104}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_179, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_179}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_179, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_179}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_149, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_119}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_179, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_175}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_179, id_ctrl_decoder_decoded_andMatrixOutputs_lo_179}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_158_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_179; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_118}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_105}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_127, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_124}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_150, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_130}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_118}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_179, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_169}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_176, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_169}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_180, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_179}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_105}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_180, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_180}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_180, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_180}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_150, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_120}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_180, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_176}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_180, id_ctrl_decoder_decoded_andMatrixOutputs_lo_180}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_110_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_180; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_65}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_119}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_65}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_125}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_151, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_131}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_119}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_180, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_170}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_177, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_170}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_181, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_180}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_106}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_181, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_181}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_181, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_181}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_151, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_121}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_181, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_177}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_181, id_ctrl_decoder_decoded_andMatrixOutputs_lo_181}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_23_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_181; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_66}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_120}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_66}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_126}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_152, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_132}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_120}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_181, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_171}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_178, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_171}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_182, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_181}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_107}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_182, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_182}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_182, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_182}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_152, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_122}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_182, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_178}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_182, id_ctrl_decoder_decoded_andMatrixOutputs_lo_182}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_101_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_182; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_67}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_121}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_67}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_127}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_153, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_133}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_121}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_183 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_182, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_172}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_179, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_172}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_183, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_182}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_108}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_183, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_183}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_183, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_183}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_183 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_153, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_123}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_183 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_183, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_179}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_183 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_183, id_ctrl_decoder_decoded_andMatrixOutputs_lo_183}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_118_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_183; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_68}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_122}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_68}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_128}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_154, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_134}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_183 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_122}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_184 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_183, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_173}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_180, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_173}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_184, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_183}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_109}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_184, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_184}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_184, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_184}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_184 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_154, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_124}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_184 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_184, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_180}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_184 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_184, id_ctrl_decoder_decoded_andMatrixOutputs_lo_184}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_116_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_184; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_69}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_123}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_69}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_129}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_155, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_135}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_184 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_123}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_185 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_184, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_174}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_181, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_174}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_185, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_184}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_110}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_185, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_185}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_185, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_185}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_185 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_155, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_125}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_185 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_185, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_181}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_185 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_185, id_ctrl_decoder_decoded_andMatrixOutputs_lo_185}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_156_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_185; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_17}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_39}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_26}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_70}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_111}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_130}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_126}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_185 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_124}; // @[pla.scala:98:53]
wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_186 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_185, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_175}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_156, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_136}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_185, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_182}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_175}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_111}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_186, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_186}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_186, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_186}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_186}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_186 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_156, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_126}; // @[pla.scala:98:53]
wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_186 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_186, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_182}; // @[pla.scala:98:53]
wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_186 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_186, id_ctrl_decoder_decoded_andMatrixOutputs_lo_186}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_113_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_186; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_18}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_40}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_27}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_71}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_112}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_131}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_127}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_186 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_125}; // @[pla.scala:98:53]
wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_187 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_186, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_176}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_157, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_137}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_186, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_183}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_176}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_183 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_112}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_187, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_187}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_187, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_187}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_187}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_187 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_157, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_127}; // @[pla.scala:98:53]
wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_187 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_187, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_183}; // @[pla.scala:98:53]
wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_187 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_187, id_ctrl_decoder_decoded_andMatrixOutputs_lo_187}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_107_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_187; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_19}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_41}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_28}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_72}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_113}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_132}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_128}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_187 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_126}; // @[pla.scala:98:53]
wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_188 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_187, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_177}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_158, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_138}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_187, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_184}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_177}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_184 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_113}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_188, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_188}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_188, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_188}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_188}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_188 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_158, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_128}; // @[pla.scala:98:53]
wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_188 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_188, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_184}; // @[pla.scala:98:53]
wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_188 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_188, id_ctrl_decoder_decoded_andMatrixOutputs_lo_188}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_84_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_188; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_20}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_42}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_29}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_73}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_127, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_114}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_133}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_129}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_188 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_127}; // @[pla.scala:98:53]
wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_189 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_188, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_178}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_159, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_139}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_188, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_185}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_178}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_185 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_114}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_189, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_189}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_189, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_189}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_189}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_189 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_159, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_129}; // @[pla.scala:98:53]
wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_189 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_189, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_185}; // @[pla.scala:98:53]
wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_189 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_189, id_ctrl_decoder_decoded_andMatrixOutputs_lo_189}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_33_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_189; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_13}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_30}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_23}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_74}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_74}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_130}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_128}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_189 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_128}; // @[pla.scala:98:53]
wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_190 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_189, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_179}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_140, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_137}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_186, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_179}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_160}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_186 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_115}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_190, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_190}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_189}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_190, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_190}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_190}; // @[pla.scala:91:29, :98:53]
wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_190 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_160, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_130}; // @[pla.scala:98:53]
wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_190 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_190, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_186}; // @[pla.scala:98:53]
wire [20:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_190 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_190, id_ctrl_decoder_decoded_andMatrixOutputs_lo_190}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_85_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_190; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_14}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_31}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_24}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_75}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_75}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_131}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_129}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_190 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_141, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_129}; // @[pla.scala:98:53]
wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_191 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_190, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_180}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_141, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_138}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_187, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_180}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_161}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_187 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_116}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_191, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_191}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_190}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_191, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_191}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_191}; // @[pla.scala:91:29, :98:53]
wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_191 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_161, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_131}; // @[pla.scala:98:53]
wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_191 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_191, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_187}; // @[pla.scala:98:53]
wire [20:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_191 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_191, id_ctrl_decoder_decoded_andMatrixOutputs_lo_191}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_40_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_191; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_15}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_32}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_25}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_76}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_76}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_132}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_130}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_191 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_142, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_130}; // @[pla.scala:98:53]
wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_192 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_191, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_181}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_139}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_188, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_181}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_162}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_188 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_117}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_192, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_192}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_191}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_192, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_192}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_192}; // @[pla.scala:91:29, :98:53]
wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_192 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_162, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_132}; // @[pla.scala:98:53]
wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_192 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_192, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_188}; // @[pla.scala:98:53]
wire [20:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_192 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_192, id_ctrl_decoder_decoded_andMatrixOutputs_lo_192}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_12_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_192; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_16}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_33}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_26}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_77}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_77}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_137, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_133}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_131}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_192 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_143, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_131}; // @[pla.scala:98:53]
wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_193 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_192, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_182}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_140}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_189, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_182}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_163}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_189 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_118}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_193, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_193}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_192}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_193, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_193}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_193}; // @[pla.scala:91:29, :98:53]
wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_193 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_163, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_133}; // @[pla.scala:98:53]
wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_193 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_193, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_189}; // @[pla.scala:98:53]
wire [20:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_193 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_193, id_ctrl_decoder_decoded_andMatrixOutputs_lo_193}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_75_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_193; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_118_2, id_ctrl_decoder_decoded_andMatrixOutputs_85_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_40_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_114_2, id_ctrl_decoder_decoded_andMatrixOutputs_174_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_127_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_86_2, id_ctrl_decoder_decoded_andMatrixOutputs_10_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_93_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_148_2, id_ctrl_decoder_decoded_andMatrixOutputs_76_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_87_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:114:19]
wire [11:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T = {id_ctrl_decoder_decoded_orMatrixOutputs_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo}; // @[pla.scala:114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_1 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T; // @[pla.scala:114:{19,36}]
wire [1:0] _GEN = {id_ctrl_decoder_decoded_andMatrixOutputs_14_2, id_ctrl_decoder_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_1; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_1 = _GEN; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_6; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_6 = _GEN; // @[pla.scala:114:19]
wire [2:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_3 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_2; // @[pla.scala:114:{19,36}]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_47_2, id_ctrl_decoder_decoded_andMatrixOutputs_83_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_82_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_155_2, id_ctrl_decoder_decoded_andMatrixOutputs_59_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_55_2, id_ctrl_decoder_decoded_andMatrixOutputs_185_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_1}; // @[pla.scala:114:19]
wire [6:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_lo_1}; // @[pla.scala:114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_9 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_8; // @[pla.scala:114:{19,36}]
wire [1:0] _GEN_0 = {id_ctrl_decoder_decoded_andMatrixOutputs_84_2, id_ctrl_decoder_decoded_andMatrixOutputs_33_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo = _GEN_0; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_2; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_2 = _GEN_0; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_lo; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_lo = _GEN_0; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_154_2, id_ctrl_decoder_decoded_andMatrixOutputs_23_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_101_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_57_2, id_ctrl_decoder_decoded_andMatrixOutputs_80_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_166_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_100_2, id_ctrl_decoder_decoded_andMatrixOutputs_89_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:114:19]
wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_69_2, id_ctrl_decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_1_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _GEN_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_52_2, id_ctrl_decoder_decoded_andMatrixOutputs_173_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi = _GEN_1; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_2; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_2 = _GEN_1; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_4; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_4 = _GEN_1; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_42_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:114:19]
wire [1:0] _GEN_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_180_2, id_ctrl_decoder_decoded_andMatrixOutputs_135_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi = _GEN_2; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_8; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_8 = _GEN_2; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1 = _GEN_2; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_24; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_24 = _GEN_2; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_2; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_2 = _GEN_2; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_3; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_3 = _GEN_2; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_188_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_137_2, id_ctrl_decoder_decoded_andMatrixOutputs_159_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:114:19]
wire [11:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo}; // @[pla.scala:114:19]
wire [22:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_1}; // @[pla.scala:114:19]
wire [1:0] _GEN_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_0_2, id_ctrl_decoder_decoded_andMatrixOutputs_60_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo = _GEN_3; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2 = _GEN_3; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_4; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_4 = _GEN_3; // @[pla.scala:114:19]
wire [1:0] _GEN_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_41_2, id_ctrl_decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi = _GEN_4; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_10; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_10 = _GEN_4; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_3; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_3 = _GEN_4; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:114:19]
wire [1:0] _GEN_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_14_2, id_ctrl_decoder_decoded_andMatrixOutputs_155_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi = _GEN_5; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_3; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_3 = _GEN_5; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_126_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_105_2, id_ctrl_decoder_decoded_andMatrixOutputs_185_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_17_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:114:19]
wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_191_2, id_ctrl_decoder_decoded_andMatrixOutputs_164_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_121_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _GEN_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_7_2, id_ctrl_decoder_decoded_andMatrixOutputs_98_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi = _GEN_6; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_7; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_7 = _GEN_6; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo = _GEN_6; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_71_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:114:19]
wire [1:0] _GEN_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_96_2, id_ctrl_decoder_decoded_andMatrixOutputs_35_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi = _GEN_7; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_4; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_4 = _GEN_7; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_190_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _GEN_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_99_2, id_ctrl_decoder_decoded_andMatrixOutputs_9_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi = _GEN_8; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1 = _GEN_8; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_5; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_5 = _GEN_8; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2 = _GEN_8; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7 = _GEN_8; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_3; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_3 = _GEN_8; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_4; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_4 = _GEN_8; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi = _GEN_8; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_139_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:114:19]
wire [11:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo}; // @[pla.scala:114:19]
wire [22:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_2}; // @[pla.scala:114:19]
wire [45:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_2}; // @[pla.scala:114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_11 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_10; // @[pla.scala:114:{19,36}]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_176_2, id_ctrl_decoder_decoded_andMatrixOutputs_172_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_13 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_12; // @[pla.scala:114:{19,36}]
wire [1:0] _GEN_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_12_2, id_ctrl_decoder_decoded_andMatrixOutputs_75_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_1; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_1 = _GEN_9; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2 = _GEN_9; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4 = _GEN_9; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_116_2, id_ctrl_decoder_decoded_andMatrixOutputs_156_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_1}; // @[pla.scala:114:19]
wire [1:0] _GEN_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_51_2, id_ctrl_decoder_decoded_andMatrixOutputs_136_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_1; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_1 = _GEN_10; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_2; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_2 = _GEN_10; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo = _GEN_10; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_72_2, id_ctrl_decoder_decoded_andMatrixOutputs_81_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_157_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:114:19]
wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_2}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_45_2, id_ctrl_decoder_decoded_andMatrixOutputs_114_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _GEN_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_153_2, id_ctrl_decoder_decoded_andMatrixOutputs_109_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1 = _GEN_11; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_12; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_12 = _GEN_11; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_3; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_3 = _GEN_11; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_187_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_77_2, id_ctrl_decoder_decoded_andMatrixOutputs_92_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _GEN_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_181_2, id_ctrl_decoder_decoded_andMatrixOutputs_20_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1 = _GEN_12; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_3; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_3 = _GEN_12; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2 = _GEN_12; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_11; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_11 = _GEN_12; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_22_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:114:19]
wire [9:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_3}; // @[pla.scala:114:19]
wire [18:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_3}; // @[pla.scala:114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_15 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_14; // @[pla.scala:114:{19,36}]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_109_2, id_ctrl_decoder_decoded_andMatrixOutputs_51_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_136_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _GEN_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_6_2, id_ctrl_decoder_decoded_andMatrixOutputs_134_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_3; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_3 = _GEN_13; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2 = _GEN_13; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo = _GEN_13; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_153_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_3}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_123_2, id_ctrl_decoder_decoded_andMatrixOutputs_124_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_50_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_22_2, id_ctrl_decoder_decoded_andMatrixOutputs_160_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_2}; // @[pla.scala:114:19]
wire [6:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_4}; // @[pla.scala:114:19]
wire [12:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_4}; // @[pla.scala:114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_18 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_17; // @[pla.scala:114:{19,36}]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_23_2, id_ctrl_decoder_decoded_andMatrixOutputs_101_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_2}; // @[pla.scala:114:19]
wire [1:0] _GEN_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_70_2, id_ctrl_decoder_decoded_andMatrixOutputs_174_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2 = _GEN_14; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_lo; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_lo = _GEN_14; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_130_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_2}; // @[pla.scala:114:19]
wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_4}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_109_2, id_ctrl_decoder_decoded_andMatrixOutputs_141_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_153_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_2}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_124_2, id_ctrl_decoder_decoded_andMatrixOutputs_50_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_22_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_3}; // @[pla.scala:114:19]
wire [9:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_5}; // @[pla.scala:114:19]
wire [18:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_lo_5}; // @[pla.scala:114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_20 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_19; // @[pla.scala:114:{19,36}]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_65_2, id_ctrl_decoder_decoded_andMatrixOutputs_79_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_128_2, id_ctrl_decoder_decoded_andMatrixOutputs_165_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_177_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_21 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_lo_6}; // @[pla.scala:114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_22 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_21; // @[pla.scala:114:{19,36}]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_137_2, id_ctrl_decoder_decoded_andMatrixOutputs_65_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_23 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_58_2}; // @[pla.scala:98:70, :114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_24 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_23; // @[pla.scala:114:{19,36}]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_83_2, id_ctrl_decoder_decoded_andMatrixOutputs_169_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _GEN_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_0_2, id_ctrl_decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_10; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_10 = _GEN_15; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_7; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_7 = _GEN_15; // @[pla.scala:114:19]
wire [3:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_25 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_lo_7}; // @[pla.scala:114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_26 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_25; // @[pla.scala:114:{19,36}]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_74_2, id_ctrl_decoder_decoded_andMatrixOutputs_111_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_5}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_30_2, id_ctrl_decoder_decoded_andMatrixOutputs_140_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_102_2, id_ctrl_decoder_decoded_andMatrixOutputs_9_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_6}; // @[pla.scala:114:19]
wire [8:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_29 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_lo_8}; // @[pla.scala:114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_30 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_29; // @[pla.scala:114:{19,36}]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_142_2, id_ctrl_decoder_decoded_andMatrixOutputs_46_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_149_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_167_2, id_ctrl_decoder_decoded_andMatrixOutputs_138_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_104_2, id_ctrl_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_3}; // @[pla.scala:114:19]
wire [6:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_6}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_15_2, id_ctrl_decoder_decoded_andMatrixOutputs_144_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_94_2, id_ctrl_decoder_decoded_andMatrixOutputs_125_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_3}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_56_2, id_ctrl_decoder_decoded_andMatrixOutputs_179_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _GEN_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_121_2, id_ctrl_decoder_decoded_andMatrixOutputs_105_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_6; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_6 = _GEN_16; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_3; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_3 = _GEN_16; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi = _GEN_16; // @[pla.scala:114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_4}; // @[pla.scala:114:19]
wire [7:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_7}; // @[pla.scala:114:19]
wire [14:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_31 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_lo_9}; // @[pla.scala:114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_32 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_31; // @[pla.scala:114:{19,36}]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_64_2, id_ctrl_decoder_decoded_andMatrixOutputs_142_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _GEN_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_138_2, id_ctrl_decoder_decoded_andMatrixOutputs_173_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_6; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_6 = _GEN_17; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5 = _GEN_17; // @[pla.scala:114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_3}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_25_2, id_ctrl_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_43_2, id_ctrl_decoder_decoded_andMatrixOutputs_3_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_4_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_4}; // @[pla.scala:114:19]
wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_7}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_73_2, id_ctrl_decoder_decoded_andMatrixOutputs_163_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_168_2, id_ctrl_decoder_decoded_andMatrixOutputs_36_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_4}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_112_2, id_ctrl_decoder_decoded_andMatrixOutputs_170_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_39_2, id_ctrl_decoder_decoded_andMatrixOutputs_115_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_162_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_5}; // @[pla.scala:114:19]
wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_8}; // @[pla.scala:114:19]
wire [17:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_33 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_lo_10}; // @[pla.scala:114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_34 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_33; // @[pla.scala:114:{19,36}]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_5_2, id_ctrl_decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_8}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_150_2, id_ctrl_decoder_decoded_andMatrixOutputs_161_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_133_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_17_2, id_ctrl_decoder_decoded_andMatrixOutputs_132_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_44_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_9}; // @[pla.scala:114:19]
wire [10:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_35 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_lo_11}; // @[pla.scala:114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_36 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_35; // @[pla.scala:114:{19,36}]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_54_2, id_ctrl_decoder_decoded_andMatrixOutputs_183_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_147_2, id_ctrl_decoder_decoded_andMatrixOutputs_178_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_19_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_9}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_48_2, id_ctrl_decoder_decoded_andMatrixOutputs_25_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_129_2, id_ctrl_decoder_decoded_andMatrixOutputs_49_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_161_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_10}; // @[pla.scala:114:19]
wire [9:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_37 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_lo_12}; // @[pla.scala:114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_38 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_37; // @[pla.scala:114:{19,36}]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_171_2, id_ctrl_decoder_decoded_andMatrixOutputs_37_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _GEN_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_108_2, id_ctrl_decoder_decoded_andMatrixOutputs_89_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_5; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_5 = _GEN_18; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_lo; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_lo = _GEN_18; // @[pla.scala:114:19]
wire [1:0] _GEN_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_106_2, id_ctrl_decoder_decoded_andMatrixOutputs_186_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_9; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_9 = _GEN_19; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_3; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_3 = _GEN_19; // @[pla.scala:114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_5}; // @[pla.scala:114:19]
wire [6:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_10}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_11_2, id_ctrl_decoder_decoded_andMatrixOutputs_42_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_69_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_188_2, id_ctrl_decoder_decoded_andMatrixOutputs_27_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_60_2, id_ctrl_decoder_decoded_andMatrixOutputs_48_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_6}; // @[pla.scala:114:19]
wire [6:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_11}; // @[pla.scala:114:19]
wire [13:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_39 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_lo_13}; // @[pla.scala:114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_40 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_39; // @[pla.scala:114:{19,36}]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_62_2, id_ctrl_decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_151_2, id_ctrl_decoder_decoded_andMatrixOutputs_18_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_1}; // @[pla.scala:114:19]
wire [1:0] _GEN_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_42_2, id_ctrl_decoder_decoded_andMatrixOutputs_69_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1 = _GEN_20; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_2; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_2 = _GEN_20; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_3; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_3 = _GEN_20; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_135_2, id_ctrl_decoder_decoded_andMatrixOutputs_188_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1}; // @[pla.scala:114:19]
wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_4}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_34_2, id_ctrl_decoder_decoded_andMatrixOutputs_180_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_83_2, id_ctrl_decoder_decoded_andMatrixOutputs_159_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_1}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_60_2, id_ctrl_decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_189_2, id_ctrl_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_1}; // @[pla.scala:114:19]
wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_6}; // @[pla.scala:114:19]
wire [17:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_11}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_161_2, id_ctrl_decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_155_2, id_ctrl_decoder_decoded_andMatrixOutputs_126_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_1}; // @[pla.scala:114:19]
wire [1:0] _GEN_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_17_2, id_ctrl_decoder_decoded_andMatrixOutputs_14_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_1; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_1 = _GEN_21; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_1; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_1 = _GEN_21; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_2; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_2 = _GEN_21; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_121_2, id_ctrl_decoder_decoded_andMatrixOutputs_95_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_140_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_1}; // @[pla.scala:114:19]
wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_5}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_164_2, id_ctrl_decoder_decoded_andMatrixOutputs_30_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_7_2, id_ctrl_decoder_decoded_andMatrixOutputs_131_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_1}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_35_2, id_ctrl_decoder_decoded_andMatrixOutputs_78_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_1}; // @[pla.scala:114:19]
wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_7}; // @[pla.scala:114:19]
wire [17:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_12}; // @[pla.scala:114:19]
wire [35:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_41 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_lo_14}; // @[pla.scala:114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_42 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_41; // @[pla.scala:114:{19,36}]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_66_2, id_ctrl_decoder_decoded_andMatrixOutputs_146_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_97_2, id_ctrl_decoder_decoded_andMatrixOutputs_164_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_43 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_lo_15}; // @[pla.scala:114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_44 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_43; // @[pla.scala:114:{19,36}]
wire [1:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_35_2, id_ctrl_decoder_decoded_andMatrixOutputs_164_2}; // @[pla.scala:98:70, :114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_46 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_45; // @[pla.scala:114:{19,36}]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_100_2, id_ctrl_decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_42_2, id_ctrl_decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_1_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_5}; // @[pla.scala:114:19]
wire [1:0] _GEN_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_188_2, id_ctrl_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2 = _GEN_22; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3 = _GEN_22; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo = _GEN_22; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_120_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _GEN_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_28_2, id_ctrl_decoder_decoded_andMatrixOutputs_60_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_5; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_5 = _GEN_23; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3 = _GEN_23; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_180_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_7}; // @[pla.scala:114:19]
wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_12}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_91_2, id_ctrl_decoder_decoded_andMatrixOutputs_2_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_24_2, id_ctrl_decoder_decoded_andMatrixOutputs_53_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_17_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_6}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_191_2, id_ctrl_decoder_decoded_andMatrixOutputs_26_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_61_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_96_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_8}; // @[pla.scala:114:19]
wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_13}; // @[pla.scala:114:19]
wire [21:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_47 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_19, id_ctrl_decoder_decoded_orMatrixOutputs_lo_16}; // @[pla.scala:114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_48 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_47; // @[pla.scala:114:{19,36}]
wire [1:0] _GEN_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_122_2, id_ctrl_decoder_decoded_andMatrixOutputs_116_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1 = _GEN_24; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_2; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_2 = _GEN_24; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_156_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2}; // @[pla.scala:114:19]
wire [1:0] _GEN_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_1_2, id_ctrl_decoder_decoded_andMatrixOutputs_100_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_1; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_1 = _GEN_25; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_3; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_3 = _GEN_25; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_4; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_4 = _GEN_25; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_2; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_2 = _GEN_25; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_89_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_2}; // @[pla.scala:114:19]
wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_6}; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_188_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_2}; // @[pla.scala:114:19]
wire [1:0] _GEN_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_31_2, id_ctrl_decoder_decoded_andMatrixOutputs_159_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_1; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_1 = _GEN_26; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_2; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_2 = _GEN_26; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_2}; // @[pla.scala:114:19]
wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_8}; // @[pla.scala:114:19]
wire [21:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_13}; // @[pla.scala:114:19]
wire [1:0] _GEN_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_8_2, id_ctrl_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_2; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_2 = _GEN_27; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4 = _GEN_27; // @[pla.scala:114:19]
wire [1:0] _GEN_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_126_2, id_ctrl_decoder_decoded_andMatrixOutputs_161_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1 = _GEN_28; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_2; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_2 = _GEN_28; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_lo; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_lo = _GEN_28; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_2}; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_184_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _GEN_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_105_2, id_ctrl_decoder_decoded_andMatrixOutputs_16_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_2; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_2 = _GEN_29; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_4; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_4 = _GEN_29; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_140_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_2}; // @[pla.scala:114:19]
wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_7}; // @[pla.scala:114:19]
wire [1:0] _GEN_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_30_2, id_ctrl_decoder_decoded_andMatrixOutputs_121_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_2; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_2 = _GEN_30; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_4; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_4 = _GEN_30; // @[pla.scala:114:19]
wire [1:0] _GEN_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_98_2, id_ctrl_decoder_decoded_andMatrixOutputs_71_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1 = _GEN_31; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_3; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_3 = _GEN_31; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_2; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_2 = _GEN_31; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_131_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_2}; // @[pla.scala:114:19]
wire [1:0] _GEN_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_96_2, id_ctrl_decoder_decoded_andMatrixOutputs_190_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1 = _GEN_32; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_2; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_2 = _GEN_32; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_2}; // @[pla.scala:114:19]
wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_9}; // @[pla.scala:114:19]
wire [21:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_14}; // @[pla.scala:114:19]
wire [43:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_49 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_20, id_ctrl_decoder_decoded_orMatrixOutputs_lo_17}; // @[pla.scala:114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_50 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_49; // @[pla.scala:114:{19,36}]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_28_2, id_ctrl_decoder_decoded_andMatrixOutputs_159_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_182_2, id_ctrl_decoder_decoded_andMatrixOutputs_164_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_21 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_189_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_51 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_21, id_ctrl_decoder_decoded_orMatrixOutputs_lo_18}; // @[pla.scala:114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_52 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_51; // @[pla.scala:114:{19,36}]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_120_2, id_ctrl_decoder_decoded_andMatrixOutputs_42_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_7}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_180_2, id_ctrl_decoder_decoded_andMatrixOutputs_188_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_2_2, id_ctrl_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_60_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_9}; // @[pla.scala:114:19]
wire [11:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_14}; // @[pla.scala:114:19]
wire [1:0] _GEN_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_140_2, id_ctrl_decoder_decoded_andMatrixOutputs_17_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_3; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_3 = _GEN_33; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_4; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_4 = _GEN_33; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo = _GEN_33; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_91_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_30_2, id_ctrl_decoder_decoded_andMatrixOutputs_61_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_24_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_8}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_35_2, id_ctrl_decoder_decoded_andMatrixOutputs_191_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_164_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_29_2, id_ctrl_decoder_decoded_andMatrixOutputs_96_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_3}; // @[pla.scala:114:19]
wire [6:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_10}; // @[pla.scala:114:19]
wire [12:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_22 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_15}; // @[pla.scala:114:19]
wire [24:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_53 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_22, id_ctrl_decoder_decoded_orMatrixOutputs_lo_19}; // @[pla.scala:114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_54 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_53; // @[pla.scala:114:{19,36}]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_89_2, id_ctrl_decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_3}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_142_2, id_ctrl_decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_3}; // @[pla.scala:114:19]
wire [7:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_8}; // @[pla.scala:114:19]
wire [1:0] _GEN_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_159_2, id_ctrl_decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5 = _GEN_34; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_7; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_7 = _GEN_34; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_lo; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_lo = _GEN_34; // @[pla.scala:114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_146_2, id_ctrl_decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3}; // @[pla.scala:114:19]
wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_10}; // @[pla.scala:114:19]
wire [16:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_15}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_126_2, id_ctrl_decoder_decoded_andMatrixOutputs_66_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_3}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_97_2, id_ctrl_decoder_decoded_andMatrixOutputs_131_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_30_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_3}; // @[pla.scala:114:19]
wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_9}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_190_2, id_ctrl_decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_3}; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_4}; // @[pla.scala:114:19]
wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_11}; // @[pla.scala:114:19]
wire [17:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_23 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_16}; // @[pla.scala:114:19]
wire [34:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_55 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_23, id_ctrl_decoder_decoded_orMatrixOutputs_lo_20}; // @[pla.scala:114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_56 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_55; // @[pla.scala:114:{19,36}]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_68_2, id_ctrl_decoder_decoded_andMatrixOutputs_63_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_57 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_24, id_ctrl_decoder_decoded_orMatrixOutputs_lo_21}; // @[pla.scala:114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_58 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_57; // @[pla.scala:114:{19,36}]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_156_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4}; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_89_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_4}; // @[pla.scala:114:19]
wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_9}; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_188_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_4}; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_4}; // @[pla.scala:114:19]
wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_11}; // @[pla.scala:114:19]
wire [21:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_22 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_16}; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4}; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_184_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_140_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_4}; // @[pla.scala:114:19]
wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_10}; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_131_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_4}; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_5}; // @[pla.scala:114:19]
wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_12}; // @[pla.scala:114:19]
wire [21:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_25 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_19, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_17}; // @[pla.scala:114:19]
wire [43:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_59 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_25, id_ctrl_decoder_decoded_orMatrixOutputs_lo_22}; // @[pla.scala:114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_60 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_59; // @[pla.scala:114:{19,36}]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_69_2, id_ctrl_decoder_decoded_andMatrixOutputs_89_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_135_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_10}; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_13_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_12}; // @[pla.scala:114:19]
wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_23 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_19, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_17}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_161_2, id_ctrl_decoder_decoded_andMatrixOutputs_88_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_71_2, id_ctrl_decoder_decoded_andMatrixOutputs_14_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_126_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_11}; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_32_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_128_2, id_ctrl_decoder_decoded_andMatrixOutputs_67_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_190_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_13}; // @[pla.scala:114:19]
wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_26 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_20, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_18}; // @[pla.scala:114:19]
wire [21:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_61 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_26, id_ctrl_decoder_decoded_orMatrixOutputs_lo_23}; // @[pla.scala:114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_62 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_61; // @[pla.scala:114:{19,36}]
wire [1:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_97_2, id_ctrl_decoder_decoded_andMatrixOutputs_161_2}; // @[pla.scala:98:70, :114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_66 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_65; // @[pla.scala:114:{19,36}]
wire [1:0] _GEN_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_158_2, id_ctrl_decoder_decoded_andMatrixOutputs_110_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_11; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_11 = _GEN_35; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo = _GEN_35; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_136_2, id_ctrl_decoder_decoded_andMatrixOutputs_192_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_38_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_11}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_130_2, id_ctrl_decoder_decoded_andMatrixOutputs_51_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_141_2, id_ctrl_decoder_decoded_andMatrixOutputs_70_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_174_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_13}; // @[pla.scala:114:19]
wire [9:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_24 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_20, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_18}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_50_2, id_ctrl_decoder_decoded_andMatrixOutputs_6_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_134_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_12}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_175_2, id_ctrl_decoder_decoded_andMatrixOutputs_193_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_124_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_22_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_21 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_14}; // @[pla.scala:114:19]
wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_27 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_21, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_19}; // @[pla.scala:114:19]
wire [20:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_67 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_27, id_ctrl_decoder_decoded_orMatrixOutputs_lo_24}; // @[pla.scala:114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_68 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_67; // @[pla.scala:114:{19,36}]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_113_2, id_ctrl_decoder_decoded_andMatrixOutputs_107_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_lo}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_122_2, id_ctrl_decoder_decoded_andMatrixOutputs_119_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo}; // @[pla.scala:114:19]
wire [7:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_5}; // @[pla.scala:114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_lo}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_130_2, id_ctrl_decoder_decoded_andMatrixOutputs_42_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_69_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo}; // @[pla.scala:114:19]
wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_5}; // @[pla.scala:114:19]
wire [16:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_12}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_173_2, id_ctrl_decoder_decoded_andMatrixOutputs_141_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_lo}; // @[pla.scala:114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo}; // @[pla.scala:114:19]
wire [7:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_5}; // @[pla.scala:114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_lo}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_111_2, id_ctrl_decoder_decoded_andMatrixOutputs_124_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_50_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo}; // @[pla.scala:114:19]
wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_5}; // @[pla.scala:114:19]
wire [16:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_21 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_14}; // @[pla.scala:114:19]
wire [33:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_25 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_21, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_19}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_152_2, id_ctrl_decoder_decoded_andMatrixOutputs_103_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_60_2, id_ctrl_decoder_decoded_andMatrixOutputs_74_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_lo}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_28_2, id_ctrl_decoder_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_lo}; // @[pla.scala:114:19]
wire [7:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_5}; // @[pla.scala:114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_lo}; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_95_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo}; // @[pla.scala:114:19]
wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_5}; // @[pla.scala:114:19]
wire [16:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_13}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_90_2, id_ctrl_decoder_decoded_andMatrixOutputs_30_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_131_2, id_ctrl_decoder_decoded_andMatrixOutputs_164_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_lo}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_20_2, id_ctrl_decoder_decoded_andMatrixOutputs_22_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_71_2, id_ctrl_decoder_decoded_andMatrixOutputs_145_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_143_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo}; // @[pla.scala:114:19]
wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_5}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_35_2, id_ctrl_decoder_decoded_andMatrixOutputs_190_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_117_2, id_ctrl_decoder_decoded_andMatrixOutputs_96_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo}; // @[pla.scala:114:19]
wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_6}; // @[pla.scala:114:19]
wire [17:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_22 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_19, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_15}; // @[pla.scala:114:19]
wire [34:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_28 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_22, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_20}; // @[pla.scala:114:19]
wire [68:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_69 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_28, id_ctrl_decoder_decoded_orMatrixOutputs_lo_25}; // @[pla.scala:114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_70 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_69; // @[pla.scala:114:{19,36}]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_3, _id_ctrl_decoder_decoded_orMatrixOutputs_T_1}; // @[pla.scala:102:36, :114:36]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_4 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_6, _id_ctrl_decoder_decoded_orMatrixOutputs_T_5}; // @[pla.scala:102:36, :114:36]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_4}; // @[pla.scala:102:36, :114:36]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_6}; // @[pla.scala:102:36]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_9, _id_ctrl_decoder_decoded_orMatrixOutputs_T_7}; // @[pla.scala:102:36, :114:36]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_5 = {1'h0, _id_ctrl_decoder_decoded_orMatrixOutputs_T_13}; // @[pla.scala:102:36, :114:36]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_5, _id_ctrl_decoder_decoded_orMatrixOutputs_T_11}; // @[pla.scala:102:36, :114:36]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_6}; // @[pla.scala:102:36]
wire [9:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_13}; // @[pla.scala:102:36]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_16, _id_ctrl_decoder_decoded_orMatrixOutputs_T_15}; // @[pla.scala:102:36, :114:36]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_4 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_22, _id_ctrl_decoder_decoded_orMatrixOutputs_T_20}; // @[pla.scala:102:36, :114:36]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_18}; // @[pla.scala:102:36, :114:36]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_6}; // @[pla.scala:102:36]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_4 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_27, _id_ctrl_decoder_decoded_orMatrixOutputs_T_26}; // @[pla.scala:102:36, :114:36]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_24}; // @[pla.scala:102:36, :114:36]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_32, _id_ctrl_decoder_decoded_orMatrixOutputs_T_30}; // @[pla.scala:102:36, :114:36]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_6, _id_ctrl_decoder_decoded_orMatrixOutputs_T_28}; // @[pla.scala:102:36, :114:36]
wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_6}; // @[pla.scala:102:36]
wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_22 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_19, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_15}; // @[pla.scala:102:36]
wire [20:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_26 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_22, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_20}; // @[pla.scala:102:36]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_36, _id_ctrl_decoder_decoded_orMatrixOutputs_T_34}; // @[pla.scala:102:36, :114:36]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_4 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_42, _id_ctrl_decoder_decoded_orMatrixOutputs_T_40}; // @[pla.scala:102:36, :114:36]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_38}; // @[pla.scala:102:36, :114:36]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_6}; // @[pla.scala:102:36]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_46, _id_ctrl_decoder_decoded_orMatrixOutputs_T_44}; // @[pla.scala:102:36, :114:36]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_52, _id_ctrl_decoder_decoded_orMatrixOutputs_T_50}; // @[pla.scala:102:36, :114:36]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_6, _id_ctrl_decoder_decoded_orMatrixOutputs_T_48}; // @[pla.scala:102:36, :114:36]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_6}; // @[pla.scala:102:36]
wire [9:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_21 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_14}; // @[pla.scala:102:36]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_56, _id_ctrl_decoder_decoded_orMatrixOutputs_T_54}; // @[pla.scala:102:36, :114:36]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_4 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_62, _id_ctrl_decoder_decoded_orMatrixOutputs_T_60}; // @[pla.scala:102:36, :114:36]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_58}; // @[pla.scala:102:36, :114:36]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_6}; // @[pla.scala:102:36]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_4 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_66, _id_ctrl_decoder_decoded_orMatrixOutputs_T_64}; // @[pla.scala:102:36, :114:36]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_63}; // @[pla.scala:102:36, :114:36]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_70, _id_ctrl_decoder_decoded_orMatrixOutputs_T_68}; // @[pla.scala:102:36, :114:36]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_6, 1'h0}; // @[pla.scala:102:36]
wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_7}; // @[pla.scala:102:36]
wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_23 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_20, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_16}; // @[pla.scala:102:36]
wire [20:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_29 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_23, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_21}; // @[pla.scala:102:36]
wire [41:0] id_ctrl_decoder_decoded_orMatrixOutputs = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_29, id_ctrl_decoder_decoded_orMatrixOutputs_lo_26}; // @[pla.scala:102:36]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T = id_ctrl_decoder_decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_1 = id_ctrl_decoder_decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_2 = id_ctrl_decoder_decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_3 = id_ctrl_decoder_decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_4 = id_ctrl_decoder_decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_5 = id_ctrl_decoder_decoded_orMatrixOutputs[5]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_6 = id_ctrl_decoder_decoded_orMatrixOutputs[6]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_7 = id_ctrl_decoder_decoded_orMatrixOutputs[7]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_8 = id_ctrl_decoder_decoded_orMatrixOutputs[8]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_9 = id_ctrl_decoder_decoded_orMatrixOutputs[9]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_10 = id_ctrl_decoder_decoded_orMatrixOutputs[10]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_11 = id_ctrl_decoder_decoded_orMatrixOutputs[11]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_12 = id_ctrl_decoder_decoded_orMatrixOutputs[12]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_13 = id_ctrl_decoder_decoded_orMatrixOutputs[13]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_14 = id_ctrl_decoder_decoded_orMatrixOutputs[14]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_15 = id_ctrl_decoder_decoded_orMatrixOutputs[15]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_16 = id_ctrl_decoder_decoded_orMatrixOutputs[16]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_17 = id_ctrl_decoder_decoded_orMatrixOutputs[17]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_18 = id_ctrl_decoder_decoded_orMatrixOutputs[18]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_19 = id_ctrl_decoder_decoded_orMatrixOutputs[19]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_20 = id_ctrl_decoder_decoded_orMatrixOutputs[20]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_21 = id_ctrl_decoder_decoded_orMatrixOutputs[21]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_22 = id_ctrl_decoder_decoded_orMatrixOutputs[22]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_23 = id_ctrl_decoder_decoded_orMatrixOutputs[23]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_24 = id_ctrl_decoder_decoded_orMatrixOutputs[24]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_25 = id_ctrl_decoder_decoded_orMatrixOutputs[25]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_26 = id_ctrl_decoder_decoded_orMatrixOutputs[26]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_27 = id_ctrl_decoder_decoded_orMatrixOutputs[27]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_28 = id_ctrl_decoder_decoded_orMatrixOutputs[28]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_29 = id_ctrl_decoder_decoded_orMatrixOutputs[29]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_30 = id_ctrl_decoder_decoded_orMatrixOutputs[30]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_31 = id_ctrl_decoder_decoded_orMatrixOutputs[31]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_32 = id_ctrl_decoder_decoded_orMatrixOutputs[32]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_33 = id_ctrl_decoder_decoded_orMatrixOutputs[33]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_34 = id_ctrl_decoder_decoded_orMatrixOutputs[34]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_35 = id_ctrl_decoder_decoded_orMatrixOutputs[35]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_36 = id_ctrl_decoder_decoded_orMatrixOutputs[36]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_37 = id_ctrl_decoder_decoded_orMatrixOutputs[37]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_38 = id_ctrl_decoder_decoded_orMatrixOutputs[38]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_39 = id_ctrl_decoder_decoded_orMatrixOutputs[39]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_40 = id_ctrl_decoder_decoded_orMatrixOutputs[40]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_41 = id_ctrl_decoder_decoded_orMatrixOutputs[41]; // @[pla.scala:102:36, :124:31]
wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_1, _id_ctrl_decoder_decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31]
wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_4, _id_ctrl_decoder_decoded_invMatrixOutputs_T_3}; // @[pla.scala:120:37, :124:31]
wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_2}; // @[pla.scala:120:37, :124:31]
wire [4:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_6, _id_ctrl_decoder_decoded_invMatrixOutputs_T_5}; // @[pla.scala:120:37, :124:31]
wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_9, _id_ctrl_decoder_decoded_invMatrixOutputs_T_8}; // @[pla.scala:120:37, :124:31]
wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_7}; // @[pla.scala:120:37, :124:31]
wire [4:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:120:37]
wire [9:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_11, _id_ctrl_decoder_decoded_invMatrixOutputs_T_10}; // @[pla.scala:120:37, :124:31]
wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_14, _id_ctrl_decoder_decoded_invMatrixOutputs_T_13}; // @[pla.scala:120:37, :124:31]
wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_12}; // @[pla.scala:120:37, :124:31]
wire [4:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_17, _id_ctrl_decoder_decoded_invMatrixOutputs_T_16}; // @[pla.scala:120:37, :124:31]
wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_15}; // @[pla.scala:120:37, :124:31]
wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_20, _id_ctrl_decoder_decoded_invMatrixOutputs_T_19}; // @[pla.scala:120:37, :124:31]
wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_18}; // @[pla.scala:120:37, :124:31]
wire [5:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:120:37]
wire [10:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo}; // @[pla.scala:120:37]
wire [20:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo}; // @[pla.scala:120:37]
wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_22, _id_ctrl_decoder_decoded_invMatrixOutputs_T_21}; // @[pla.scala:120:37, :124:31]
wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_25, _id_ctrl_decoder_decoded_invMatrixOutputs_T_24}; // @[pla.scala:120:37, :124:31]
wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_23}; // @[pla.scala:120:37, :124:31]
wire [4:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_27, _id_ctrl_decoder_decoded_invMatrixOutputs_T_26}; // @[pla.scala:120:37, :124:31]
wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_30, _id_ctrl_decoder_decoded_invMatrixOutputs_T_29}; // @[pla.scala:120:37, :124:31]
wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_28}; // @[pla.scala:120:37, :124:31]
wire [4:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:120:37]
wire [9:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_32, _id_ctrl_decoder_decoded_invMatrixOutputs_T_31}; // @[pla.scala:120:37, :124:31]
wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_35, _id_ctrl_decoder_decoded_invMatrixOutputs_T_34}; // @[pla.scala:120:37, :124:31]
wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_33}; // @[pla.scala:120:37, :124:31]
wire [4:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_38, _id_ctrl_decoder_decoded_invMatrixOutputs_T_37}; // @[pla.scala:120:37, :124:31]
wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_36}; // @[pla.scala:120:37, :124:31]
wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_41, _id_ctrl_decoder_decoded_invMatrixOutputs_T_40}; // @[pla.scala:120:37, :124:31]
wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_39}; // @[pla.scala:120:37, :124:31]
wire [5:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:120:37]
wire [10:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo}; // @[pla.scala:120:37]
wire [20:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo}; // @[pla.scala:120:37]
assign id_ctrl_decoder_decoded_invMatrixOutputs = {id_ctrl_decoder_decoded_invMatrixOutputs_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37]
assign id_ctrl_decoder_decoded = id_ctrl_decoder_decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37]
assign id_ctrl_decoder_0 = id_ctrl_decoder_decoded[41]; // @[pla.scala:81:23]
assign id_ctrl_legal = id_ctrl_decoder_0; // @[RocketCore.scala:321:21]
assign id_ctrl_decoder_1 = id_ctrl_decoder_decoded[40]; // @[pla.scala:81:23]
assign id_ctrl_fp = id_ctrl_decoder_1; // @[RocketCore.scala:321:21]
assign id_ctrl_decoder_2 = id_ctrl_decoder_decoded[39]; // @[pla.scala:81:23]
assign id_ctrl_rocc = id_ctrl_decoder_2; // @[RocketCore.scala:321:21]
assign id_ctrl_decoder_3 = id_ctrl_decoder_decoded[38]; // @[pla.scala:81:23]
assign id_ctrl_branch = id_ctrl_decoder_3; // @[RocketCore.scala:321:21]
assign id_ctrl_decoder_4 = id_ctrl_decoder_decoded[37]; // @[pla.scala:81:23]
assign id_ctrl_jal = id_ctrl_decoder_4; // @[RocketCore.scala:321:21]
assign id_ctrl_decoder_5 = id_ctrl_decoder_decoded[36]; // @[pla.scala:81:23]
assign id_ctrl_jalr = id_ctrl_decoder_5; // @[RocketCore.scala:321:21]
assign id_ctrl_decoder_6 = id_ctrl_decoder_decoded[35]; // @[pla.scala:81:23]
assign id_ctrl_rxs2 = id_ctrl_decoder_6; // @[RocketCore.scala:321:21]
assign id_ctrl_decoder_7 = id_ctrl_decoder_decoded[34]; // @[pla.scala:81:23]
assign id_ctrl_rxs1 = id_ctrl_decoder_7; // @[RocketCore.scala:321:21]
assign id_ctrl_decoder_8 = id_ctrl_decoder_decoded[33:31]; // @[pla.scala:81:23]
assign id_ctrl_sel_alu2 = id_ctrl_decoder_8; // @[RocketCore.scala:321:21]
assign id_ctrl_decoder_9 = id_ctrl_decoder_decoded[30:29]; // @[pla.scala:81:23]
assign id_ctrl_sel_alu1 = id_ctrl_decoder_9; // @[RocketCore.scala:321:21]
assign id_ctrl_decoder_10 = id_ctrl_decoder_decoded[28:26]; // @[pla.scala:81:23]
assign id_ctrl_sel_imm = id_ctrl_decoder_10; // @[RocketCore.scala:321:21]
assign id_ctrl_decoder_11 = id_ctrl_decoder_decoded[25]; // @[pla.scala:81:23]
assign id_ctrl_alu_dw = id_ctrl_decoder_11; // @[RocketCore.scala:321:21]
assign id_ctrl_decoder_12 = id_ctrl_decoder_decoded[24:20]; // @[pla.scala:81:23]
assign id_ctrl_alu_fn = id_ctrl_decoder_12; // @[RocketCore.scala:321:21]
assign id_ctrl_decoder_13 = id_ctrl_decoder_decoded[19]; // @[pla.scala:81:23]
assign id_ctrl_mem = id_ctrl_decoder_13; // @[RocketCore.scala:321:21]
assign id_ctrl_decoder_14 = id_ctrl_decoder_decoded[18:14]; // @[pla.scala:81:23]
assign id_ctrl_mem_cmd = id_ctrl_decoder_14; // @[RocketCore.scala:321:21]
assign id_ctrl_decoder_15 = id_ctrl_decoder_decoded[13]; // @[pla.scala:81:23]
assign id_ctrl_rfs1 = id_ctrl_decoder_15; // @[RocketCore.scala:321:21]
assign id_ctrl_decoder_16 = id_ctrl_decoder_decoded[12]; // @[pla.scala:81:23]
assign id_ctrl_rfs2 = id_ctrl_decoder_16; // @[RocketCore.scala:321:21]
assign id_ctrl_decoder_17 = id_ctrl_decoder_decoded[11]; // @[pla.scala:81:23]
assign id_ctrl_rfs3 = id_ctrl_decoder_17; // @[RocketCore.scala:321:21]
assign id_ctrl_decoder_18 = id_ctrl_decoder_decoded[10]; // @[pla.scala:81:23]
assign id_ctrl_wfd = id_ctrl_decoder_18; // @[RocketCore.scala:321:21]
assign id_ctrl_decoder_19 = id_ctrl_decoder_decoded[9]; // @[pla.scala:81:23]
assign id_ctrl_mul = id_ctrl_decoder_19; // @[RocketCore.scala:321:21]
assign id_ctrl_decoder_20 = id_ctrl_decoder_decoded[8]; // @[pla.scala:81:23]
assign id_ctrl_div = id_ctrl_decoder_20; // @[RocketCore.scala:321:21]
assign id_ctrl_decoder_21 = id_ctrl_decoder_decoded[7]; // @[pla.scala:81:23]
assign id_ctrl_wxd = id_ctrl_decoder_21; // @[RocketCore.scala:321:21]
assign id_ctrl_decoder_22 = id_ctrl_decoder_decoded[6:4]; // @[pla.scala:81:23]
assign id_ctrl_csr = id_ctrl_decoder_22; // @[RocketCore.scala:321:21]
assign id_ctrl_decoder_23 = id_ctrl_decoder_decoded[3]; // @[pla.scala:81:23]
assign id_ctrl_fence_i = id_ctrl_decoder_23; // @[RocketCore.scala:321:21]
assign id_ctrl_decoder_24 = id_ctrl_decoder_decoded[2]; // @[pla.scala:81:23]
assign id_ctrl_fence = id_ctrl_decoder_24; // @[RocketCore.scala:321:21]
assign id_ctrl_decoder_25 = id_ctrl_decoder_decoded[1]; // @[pla.scala:81:23]
assign id_ctrl_amo = id_ctrl_decoder_25; // @[RocketCore.scala:321:21]
assign id_ctrl_decoder_26 = id_ctrl_decoder_decoded[0]; // @[pla.scala:81:23]
assign id_ctrl_dp = id_ctrl_decoder_26; // @[RocketCore.scala:321:21]
wire [4:0] id_raddr3; // @[RocketCore.scala:326:72]
wire [4:0] id_raddr2; // @[RocketCore.scala:326:72]
wire [4:0] _id_rs_T_7 = id_raddr2; // @[RocketCore.scala:326:72, :1320:44]
wire [4:0] id_raddr1; // @[RocketCore.scala:326:72]
wire [4:0] _id_rs_T_2 = id_raddr1; // @[RocketCore.scala:326:72, :1320:44]
wire [4:0] id_waddr; // @[RocketCore.scala:326:72]
wire _id_load_use_T_1; // @[RocketCore.scala:1001:51]
wire id_load_use; // @[RocketCore.scala:332:25]
reg id_reg_fence; // @[RocketCore.scala:333:29]
wire [63:0] id_rs_0; // @[RocketCore.scala:1325:26]
wire _id_rs_T = ~(|id_raddr1); // @[RocketCore.scala:326:72, :1326:41]
wire [4:0] _id_rs_T_3 = ~_id_rs_T_2; // @[RocketCore.scala:1320:{39,44}]
wire [63:0] id_rs_1; // @[RocketCore.scala:1325:26]
wire _id_rs_T_5 = ~(|id_raddr2); // @[RocketCore.scala:326:72, :1326:41]
wire [4:0] _id_rs_T_8 = ~_id_rs_T_7; // @[RocketCore.scala:1320:{39,44}]
wire _ctrl_killd_T_4; // @[RocketCore.scala:1046:104]
wire ctrl_killd; // @[RocketCore.scala:338:24]
wire _id_npc_sign_T_1 = _ibuf_io_inst_0_bits_inst_bits[31]; // @[RocketCore.scala:311:20, :1341:44]
wire _id_npc_sign_T_2 = _id_npc_sign_T_1; // @[RocketCore.scala:1341:{44,49}]
wire id_npc_sign = _id_npc_sign_T_2; // @[RocketCore.scala:1341:{19,49}]
wire _id_npc_b11_T_9 = id_npc_sign; // @[RocketCore.scala:1341:19, :1346:18]
wire id_npc_hi_hi_hi = id_npc_sign; // @[RocketCore.scala:1341:19, :1355:8]
wire [10:0] _id_npc_b30_20_T_1 = _ibuf_io_inst_0_bits_inst_bits[30:20]; // @[RocketCore.scala:311:20, :1342:41]
wire [10:0] _id_npc_b30_20_T_2 = _id_npc_b30_20_T_1; // @[RocketCore.scala:1342:{41,49}]
wire [10:0] id_npc_b30_20 = {11{id_npc_sign}}; // @[RocketCore.scala:1341:19, :1342:21]
wire [10:0] id_npc_hi_hi_lo = id_npc_b30_20; // @[RocketCore.scala:1342:21, :1355:8]
wire [7:0] _id_npc_b19_12_T_3 = _ibuf_io_inst_0_bits_inst_bits[19:12]; // @[RocketCore.scala:311:20, :1343:65]
wire [7:0] _id_npc_b19_12_T_4 = _id_npc_b19_12_T_3; // @[RocketCore.scala:1343:{65,73}]
wire [7:0] id_npc_b19_12 = _id_npc_b19_12_T_4; // @[RocketCore.scala:1343:{21,73}]
wire [7:0] id_npc_hi_lo_hi = id_npc_b19_12; // @[RocketCore.scala:1343:21, :1355:8]
wire _id_npc_b11_T_4 = _ibuf_io_inst_0_bits_inst_bits[20]; // @[RocketCore.scala:311:20, :1345:39]
wire _id_npc_b0_T_3 = _ibuf_io_inst_0_bits_inst_bits[20]; // @[RocketCore.scala:311:20, :1345:39, :1352:37]
wire _id_npc_b11_T_5 = _id_npc_b11_T_4; // @[RocketCore.scala:1345:{39,44}]
wire _id_npc_b11_T_10 = _id_npc_b11_T_5; // @[RocketCore.scala:1345:{18,44}]
wire _id_npc_b11_T_7 = _ibuf_io_inst_0_bits_inst_bits[7]; // @[RocketCore.scala:311:20, :1346:39]
wire _id_npc_b0_T_1 = _ibuf_io_inst_0_bits_inst_bits[7]; // @[RocketCore.scala:311:20, :1346:39, :1351:37]
wire _id_npc_b11_T_8 = _id_npc_b11_T_7; // @[RocketCore.scala:1346:{39,43}]
wire id_npc_b11 = _id_npc_b11_T_10; // @[RocketCore.scala:1344:18, :1345:18]
wire id_npc_hi_lo_lo = id_npc_b11; // @[RocketCore.scala:1344:18, :1355:8]
wire [5:0] _id_npc_b10_5_T_3 = _ibuf_io_inst_0_bits_inst_bits[30:25]; // @[RocketCore.scala:311:20, :1347:62]
wire [5:0] id_npc_b10_5 = _id_npc_b10_5_T_3; // @[RocketCore.scala:1347:{20,62}]
wire [3:0] _id_npc_b4_1_T_4 = _ibuf_io_inst_0_bits_inst_bits[11:8]; // @[RocketCore.scala:311:20, :1349:57]
wire [3:0] _id_npc_b4_1_T_6 = _ibuf_io_inst_0_bits_inst_bits[19:16]; // @[RocketCore.scala:311:20, :1350:39]
wire [3:0] _id_npc_b4_1_T_7 = _ibuf_io_inst_0_bits_inst_bits[24:21]; // @[RocketCore.scala:311:20, :1350:52]
wire [3:0] _id_npc_b4_1_T_8 = _id_npc_b4_1_T_7; // @[RocketCore.scala:1350:{19,52}]
wire [3:0] _id_npc_b4_1_T_9 = _id_npc_b4_1_T_8; // @[RocketCore.scala:1349:19, :1350:19]
wire [3:0] id_npc_b4_1 = _id_npc_b4_1_T_9; // @[RocketCore.scala:1348:19, :1349:19]
wire _id_npc_b0_T_5 = _ibuf_io_inst_0_bits_inst_bits[15]; // @[RocketCore.scala:311:20, :1353:37]
wire [9:0] id_npc_lo_hi = {id_npc_b10_5, id_npc_b4_1}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8]
wire [10:0] id_npc_lo = {id_npc_lo_hi, 1'h0}; // @[RocketCore.scala:1355:8]
wire [8:0] id_npc_hi_lo = {id_npc_hi_lo_hi, id_npc_hi_lo_lo}; // @[RocketCore.scala:1355:8]
wire [11:0] id_npc_hi_hi = {id_npc_hi_hi_hi, id_npc_hi_hi_lo}; // @[RocketCore.scala:1355:8]
wire [20:0] id_npc_hi = {id_npc_hi_hi, id_npc_hi_lo}; // @[RocketCore.scala:1355:8]
wire [31:0] _id_npc_T_1 = {id_npc_hi, id_npc_lo}; // @[RocketCore.scala:1355:8]
wire [31:0] _id_npc_T_2 = _id_npc_T_1; // @[RocketCore.scala:1355:{8,53}]
wire [39:0] _id_npc_T; // @[RocketCore.scala:339:28]
wire [40:0] _id_npc_T_3 = {_id_npc_T[39], _id_npc_T} + {{9{_id_npc_T_2[31]}}, _id_npc_T_2}; // @[RocketCore.scala:339:{28,35}, :1355:53]
wire [39:0] _id_npc_T_4 = _id_npc_T_3[39:0]; // @[RocketCore.scala:339:35]
wire [39:0] _id_npc_T_5 = _id_npc_T_4; // @[RocketCore.scala:339:35]
wire [39:0] id_npc = _id_npc_T_5; // @[RocketCore.scala:339:{35,65}]
wire _GEN_36 = id_ctrl_csr == 3'h6; // @[package.scala:16:47]
wire _id_csr_en_T; // @[package.scala:16:47]
assign _id_csr_en_T = _GEN_36; // @[package.scala:16:47]
wire _id_csr_ren_T; // @[package.scala:16:47]
assign _id_csr_ren_T = _GEN_36; // @[package.scala:16:47]
wire _id_csr_en_T_1 = &id_ctrl_csr; // @[package.scala:16:47]
wire _id_csr_en_T_2 = id_ctrl_csr == 3'h5; // @[package.scala:16:47]
wire _id_csr_en_T_3 = _id_csr_en_T | _id_csr_en_T_1; // @[package.scala:16:47, :81:59]
wire id_csr_en = _id_csr_en_T_3 | _id_csr_en_T_2; // @[package.scala:16:47, :81:59]
wire id_system_insn = id_ctrl_csr == 3'h4; // @[RocketCore.scala:321:21, :343:36]
wire _id_csr_ren_T_1 = &id_ctrl_csr; // @[package.scala:16:47]
wire _id_csr_ren_T_2 = _id_csr_ren_T | _id_csr_ren_T_1; // @[package.scala:16:47, :81:59]
wire _id_csr_ren_T_3 = _ibuf_io_inst_0_bits_inst_rs1 == 5'h0; // @[RocketCore.scala:311:20, :344:81]
wire id_csr_ren = _id_csr_ren_T_2 & _id_csr_ren_T_3; // @[package.scala:81:59]
wire _id_csr_T = id_system_insn & id_ctrl_mem; // @[RocketCore.scala:321:21, :343:36, :345:35]
wire [2:0] _id_csr_T_1 = id_csr_ren ? 3'h2 : id_ctrl_csr; // @[RocketCore.scala:321:21, :344:54, :345:61]
wire [2:0] id_csr = _id_csr_T ? 3'h0 : _id_csr_T_1; // @[RocketCore.scala:345:{19,35,61}]
wire _id_csr_flush_T = ~id_csr_ren; // @[RocketCore.scala:344:54, :346:54]
wire _id_csr_flush_T_1 = id_csr_en & _id_csr_flush_T; // @[package.scala:81:59]
wire _id_csr_flush_T_2 = _id_csr_flush_T_1 & _csr_io_decode_0_write_flush; // @[RocketCore.scala:341:19, :346:{51,66}]
wire id_csr_flush = id_system_insn | _id_csr_flush_T_2; // @[RocketCore.scala:343:36, :346:{37,66}]
wire [31:0] _id_set_vconfig_T = _ibuf_io_inst_0_bits_inst_bits & 32'h8000707F; // @[RocketCore.scala:311:20, :347:100]
wire _id_set_vconfig_T_1 = _id_set_vconfig_T == 32'h7057; // @[RocketCore.scala:347:100]
wire [31:0] _id_set_vconfig_T_2 = _ibuf_io_inst_0_bits_inst_bits & 32'hC000707F; // @[RocketCore.scala:311:20, :347:100]
wire _id_set_vconfig_T_3 = _id_set_vconfig_T_2 == 32'hC0007057; // @[RocketCore.scala:347:100]
wire [31:0] _id_set_vconfig_T_4 = _ibuf_io_inst_0_bits_inst_bits & 32'hFE00707F; // @[RocketCore.scala:311:20, :347:100]
wire _id_set_vconfig_T_5 = _id_set_vconfig_T_4 == 32'h80007057; // @[RocketCore.scala:347:100]
wire _id_set_vconfig_T_6 = _id_set_vconfig_T_1 | _id_set_vconfig_T_3; // @[package.scala:81:59]
wire _id_set_vconfig_T_7 = _id_set_vconfig_T_6 | _id_set_vconfig_T_5; // @[package.scala:81:59]
wire _id_illegal_insn_T = ~id_ctrl_legal; // @[RocketCore.scala:321:21, :381:25]
wire _id_illegal_insn_T_1 = id_ctrl_mul | id_ctrl_div; // @[RocketCore.scala:321:21, :382:18]
wire _id_illegal_insn_T_2 = _csr_io_status_isa[12]; // @[RocketCore.scala:341:19, :382:55]
wire _id_illegal_insn_T_3 = ~_id_illegal_insn_T_2; // @[RocketCore.scala:382:{37,55}]
wire _id_illegal_insn_T_4 = _id_illegal_insn_T_1 & _id_illegal_insn_T_3; // @[RocketCore.scala:382:{18,34,37}]
wire _id_illegal_insn_T_5 = _id_illegal_insn_T | _id_illegal_insn_T_4; // @[RocketCore.scala:381:{25,40}, :382:34]
wire _id_illegal_insn_T_6 = _csr_io_status_isa[0]; // @[RocketCore.scala:341:19, :383:38]
wire _id_illegal_insn_T_7 = ~_id_illegal_insn_T_6; // @[RocketCore.scala:383:{20,38}]
wire _id_illegal_insn_T_8 = id_ctrl_amo & _id_illegal_insn_T_7; // @[RocketCore.scala:321:21, :383:{17,20}]
wire _id_illegal_insn_T_9 = _id_illegal_insn_T_5 | _id_illegal_insn_T_8; // @[RocketCore.scala:381:40, :382:65, :383:17]
wire _id_illegal_insn_T_12 = _csr_io_decode_0_fp_illegal | _id_illegal_insn_T_11; // @[RocketCore.scala:341:19, :384:{48,70}]
wire _id_illegal_insn_T_13 = id_ctrl_fp & _id_illegal_insn_T_12; // @[RocketCore.scala:321:21, :384:{16,48}]
wire _id_illegal_insn_T_14 = _id_illegal_insn_T_9 | _id_illegal_insn_T_13; // @[RocketCore.scala:382:65, :383:48, :384:16]
wire _id_illegal_insn_T_17 = _id_illegal_insn_T_14; // @[RocketCore.scala:383:48, :384:88]
wire _id_illegal_insn_T_18 = _csr_io_status_isa[3]; // @[RocketCore.scala:341:19, :386:37]
wire _id_illegal_insn_T_19 = ~_id_illegal_insn_T_18; // @[RocketCore.scala:386:{19,37}]
wire _id_illegal_insn_T_20 = id_ctrl_dp & _id_illegal_insn_T_19; // @[RocketCore.scala:321:21, :386:{16,19}]
wire _id_illegal_insn_T_21 = _id_illegal_insn_T_17 | _id_illegal_insn_T_20; // @[RocketCore.scala:384:88, :385:118, :386:16]
wire _id_illegal_insn_T_22 = _csr_io_status_isa[2]; // @[RocketCore.scala:341:19, :387:51]
wire _mem_npc_misaligned_T = _csr_io_status_isa[2]; // @[RocketCore.scala:341:19, :387:51, :623:46]
wire _id_illegal_insn_T_23 = ~_id_illegal_insn_T_22; // @[RocketCore.scala:387:{33,51}]
wire _id_illegal_insn_T_24 = _ibuf_io_inst_0_bits_rvc & _id_illegal_insn_T_23; // @[RocketCore.scala:311:20, :387:{30,33}]
wire _id_illegal_insn_T_25 = _id_illegal_insn_T_21 | _id_illegal_insn_T_24; // @[RocketCore.scala:385:118, :386:47, :387:30]
wire _id_illegal_insn_T_27 = _id_illegal_insn_T_25; // @[RocketCore.scala:386:47, :387:61]
wire _id_illegal_insn_T_29 = _id_illegal_insn_T_27; // @[RocketCore.scala:387:61, :388:39]
wire _id_illegal_insn_T_31 = _id_illegal_insn_T_29; // @[RocketCore.scala:388:39, :389:39]
wire _id_illegal_insn_T_33 = _id_illegal_insn_T_31 | _id_illegal_insn_T_32; // @[RocketCore.scala:389:39, :390:37, :391:18]
wire _id_illegal_insn_T_34 = ~id_csr_ren; // @[RocketCore.scala:344:54, :346:54, :392:52]
wire _id_illegal_insn_T_35 = _id_illegal_insn_T_34 & _csr_io_decode_0_write_illegal; // @[RocketCore.scala:341:19, :392:{52,64}]
wire _id_illegal_insn_T_36 = _csr_io_decode_0_read_illegal | _id_illegal_insn_T_35; // @[RocketCore.scala:341:19, :392:{49,64}]
wire _id_illegal_insn_T_37 = id_csr_en & _id_illegal_insn_T_36; // @[package.scala:81:59]
wire _id_illegal_insn_T_38 = _id_illegal_insn_T_33 | _id_illegal_insn_T_37; // @[RocketCore.scala:390:37, :391:51, :392:15]
wire _id_illegal_insn_T_39 = ~_ibuf_io_inst_0_bits_rvc; // @[RocketCore.scala:311:20, :393:5]
wire _id_illegal_insn_T_40 = id_system_insn & _csr_io_decode_0_system_illegal; // @[RocketCore.scala:341:19, :343:36, :393:50]
wire _id_illegal_insn_T_41 = _id_illegal_insn_T_39 & _id_illegal_insn_T_40; // @[RocketCore.scala:393:{5,31,50}]
wire id_illegal_insn = _id_illegal_insn_T_38 | _id_illegal_insn_T_41; // @[RocketCore.scala:391:51, :392:99, :393:31]
wire _id_virtual_insn_T = ~id_csr_ren; // @[RocketCore.scala:344:54, :346:54, :395:22]
wire _id_virtual_insn_T_1 = _id_virtual_insn_T & _csr_io_decode_0_write_illegal; // @[RocketCore.scala:341:19, :395:{22,34}]
wire _id_virtual_insn_T_2 = ~_id_virtual_insn_T_1; // @[RocketCore.scala:395:{20,34}]
wire _id_virtual_insn_T_3 = id_csr_en & _id_virtual_insn_T_2; // @[package.scala:81:59]
wire _id_virtual_insn_T_4 = _id_virtual_insn_T_3 & _csr_io_decode_0_virtual_access_illegal; // @[RocketCore.scala:341:19, :395:{17,69}]
wire _id_virtual_insn_T_5 = ~_ibuf_io_inst_0_bits_rvc; // @[RocketCore.scala:311:20, :393:5, :396:7]
wire _id_virtual_insn_T_6 = _id_virtual_insn_T_5 & id_system_insn; // @[RocketCore.scala:343:36, :396:{7,33}]
wire _id_virtual_insn_T_7 = _id_virtual_insn_T_6 & _csr_io_decode_0_virtual_system_illegal; // @[RocketCore.scala:341:19, :396:{33,51}]
wire _id_virtual_insn_T_8 = _id_virtual_insn_T_4 | _id_virtual_insn_T_7; // @[RocketCore.scala:395:{69,113}, :396:51]
wire id_virtual_insn = id_ctrl_legal & _id_virtual_insn_T_8; // @[RocketCore.scala:321:21, :394:39, :395:113]
wire id_amo_aq = _ibuf_io_inst_0_bits_inst_bits[26]; // @[RocketCore.scala:311:20, :398:29]
wire id_amo_rl = _ibuf_io_inst_0_bits_inst_bits[25]; // @[RocketCore.scala:311:20, :399:29]
wire [3:0] id_fence_pred = _ibuf_io_inst_0_bits_inst_bits[27:24]; // @[RocketCore.scala:311:20, :400:33]
wire [3:0] id_fence_succ = _ibuf_io_inst_0_bits_inst_bits[23:20]; // @[RocketCore.scala:311:20, :401:33]
wire _id_fence_next_T = id_ctrl_amo & id_amo_aq; // @[RocketCore.scala:321:21, :398:29, :402:52]
wire id_fence_next = id_ctrl_fence | _id_fence_next_T; // @[RocketCore.scala:321:21, :402:{37,52}]
wire _id_mem_busy_T = ~io_dmem_ordered_0; // @[RocketCore.scala:153:7, :403:21]
wire id_mem_busy = _id_mem_busy_T | io_dmem_req_valid_0; // @[RocketCore.scala:153:7, :403:{21,38}]
wire _id_rocc_busy_T = ex_reg_valid & ex_ctrl_rocc; // @[RocketCore.scala:243:20, :248:35, :406:35]
wire _id_rocc_busy_T_1 = _id_rocc_busy_T; // @[RocketCore.scala:406:{19,35}]
wire _id_rocc_busy_T_2 = mem_reg_valid & mem_ctrl_rocc; // @[RocketCore.scala:244:21, :265:36, :407:20]
wire _id_rocc_busy_T_3 = _id_rocc_busy_T_1 | _id_rocc_busy_T_2; // @[RocketCore.scala:406:{19,51}, :407:20]
wire _GEN_37 = wb_reg_valid & wb_ctrl_rocc; // @[RocketCore.scala:245:20, :288:35, :407:53]
wire _id_rocc_busy_T_4; // @[RocketCore.scala:407:53]
assign _id_rocc_busy_T_4 = _GEN_37; // @[RocketCore.scala:407:53]
wire _replay_wb_rocc_T; // @[RocketCore.scala:758:37]
assign _replay_wb_rocc_T = _GEN_37; // @[RocketCore.scala:407:53, :758:37]
wire _io_rocc_cmd_valid_T; // @[RocketCore.scala:1156:37]
assign _io_rocc_cmd_valid_T = _GEN_37; // @[RocketCore.scala:407:53, :1156:37]
wire _id_rocc_busy_T_5 = _id_rocc_busy_T_3 | _id_rocc_busy_T_4; // @[RocketCore.scala:406:51, :407:{37,53}]
wire _id_csr_rocc_write_T_1 = ~id_csr_ren; // @[RocketCore.scala:344:54, :346:54, :408:103]
wire _id_do_fence_T_4 = id_ctrl_amo & id_amo_rl; // @[RocketCore.scala:321:21, :399:29, :412:33]
wire _id_do_fence_T_5 = _id_do_fence_T_4 | id_ctrl_fence_i; // @[RocketCore.scala:321:21, :412:{33,46}]
wire _id_do_fence_T_6 = id_ctrl_mem | id_ctrl_rocc; // @[RocketCore.scala:321:21, :412:97]
wire _id_do_fence_T_7 = id_reg_fence & _id_do_fence_T_6; // @[RocketCore.scala:333:29, :412:{81,97}]
wire _id_do_fence_T_8 = _id_do_fence_T_5 | _id_do_fence_T_7; // @[RocketCore.scala:412:{46,65,81}]
wire _id_do_fence_T_9 = id_mem_busy & _id_do_fence_T_8; // @[RocketCore.scala:403:38, :412:{17,65}]
wire _id_do_fence_T_10 = _id_do_fence_T_9; // @[RocketCore.scala:411:34, :412:17]
wire id_do_fence = _id_do_fence_T_10; // @[RocketCore.scala:410:32, :411:34]
wire [38:0] _mem_npc_T_1 = mem_reg_wdata[38:0]; // @[RocketCore.scala:282:26, :418:13, :1295:16]
wire id_xcpt = _csr_io_interrupt | _bpu_io_debug_if | _bpu_io_xcpt_if | _ibuf_io_inst_0_bits_xcpt0_pf_inst | _ibuf_io_inst_0_bits_xcpt0_gf_inst | _ibuf_io_inst_0_bits_xcpt0_ae_inst | _ibuf_io_inst_0_bits_xcpt1_pf_inst | _ibuf_io_inst_0_bits_xcpt1_gf_inst | _ibuf_io_inst_0_bits_xcpt1_ae_inst | id_virtual_insn | id_illegal_insn; // @[RocketCore.scala:311:20, :341:19, :392:99, :394:39, :414:19, :1278:{14,35}]
wire [63:0] id_cause = _csr_io_interrupt ? _csr_io_interrupt_cause : {59'h0, _bpu_io_debug_if ? 5'hE : _bpu_io_xcpt_if ? 5'h3 : _ibuf_io_inst_0_bits_xcpt0_pf_inst ? 5'hC : _ibuf_io_inst_0_bits_xcpt0_gf_inst ? 5'h14 : _ibuf_io_inst_0_bits_xcpt0_ae_inst ? 5'h1 : _ibuf_io_inst_0_bits_xcpt1_pf_inst ? 5'hC : _ibuf_io_inst_0_bits_xcpt1_gf_inst ? 5'h14 : _ibuf_io_inst_0_bits_xcpt1_ae_inst ? 5'h1 : id_virtual_insn ? 5'h16 : 5'h2}; // @[Mux.scala:50:70]
wire [4:0] _ex_waddr_T = ex_reg_inst[11:7]; // @[RocketCore.scala:259:24, :453:29]
wire [4:0] ex_waddr = _ex_waddr_T; // @[RocketCore.scala:453:{29,36}]
wire [4:0] _mem_waddr_T = mem_reg_inst[11:7]; // @[RocketCore.scala:278:25, :454:31]
wire [4:0] mem_waddr = _mem_waddr_T; // @[RocketCore.scala:454:{31,38}]
wire [4:0] _wb_waddr_T = wb_reg_inst[11:7]; // @[RocketCore.scala:300:24, :455:29]
wire [4:0] wb_waddr = _wb_waddr_T; // @[RocketCore.scala:455:{29,36}]
wire [4:0] coreMonitorBundle_wrdst = wb_waddr; // @[RocketCore.scala:455:36, :1186:31]
wire bypass_sources_1_1 = ex_reg_valid & ex_ctrl_wxd; // @[RocketCore.scala:243:20, :248:35, :458:19]
wire _GEN_38 = mem_reg_valid & mem_ctrl_wxd; // @[RocketCore.scala:244:21, :265:36, :459:20]
wire _bypass_sources_T; // @[RocketCore.scala:459:20]
assign _bypass_sources_T = _GEN_38; // @[RocketCore.scala:459:20]
wire bypass_sources_3_1; // @[RocketCore.scala:460:20]
assign bypass_sources_3_1 = _GEN_38; // @[RocketCore.scala:459:20, :460:20]
wire _dcache_kill_mem_T; // @[RocketCore.scala:695:39]
assign _dcache_kill_mem_T = _GEN_38; // @[RocketCore.scala:459:20, :695:39]
wire _bypass_sources_T_1 = ~mem_ctrl_mem; // @[RocketCore.scala:244:21, :459:39]
wire bypass_sources_2_1 = _bypass_sources_T & _bypass_sources_T_1; // @[RocketCore.scala:459:{20,36,39}]
wire _id_bypass_src_T = ~(|id_raddr1); // @[RocketCore.scala:326:72, :461:82, :1326:41]
wire id_bypass_src_0_0 = _id_bypass_src_T; // @[RocketCore.scala:461:{74,82}]
wire _GEN_39 = ex_waddr == id_raddr1; // @[RocketCore.scala:326:72, :453:36, :461:82]
wire _id_bypass_src_T_1; // @[RocketCore.scala:461:82]
assign _id_bypass_src_T_1 = _GEN_39; // @[RocketCore.scala:461:82]
wire _data_hazard_ex_T; // @[RocketCore.scala:989:70]
assign _data_hazard_ex_T = _GEN_39; // @[RocketCore.scala:461:82, :989:70]
wire _fp_data_hazard_ex_T_1; // @[RocketCore.scala:990:90]
assign _fp_data_hazard_ex_T_1 = _GEN_39; // @[RocketCore.scala:461:82, :990:90]
wire id_bypass_src_0_1 = bypass_sources_1_1 & _id_bypass_src_T_1; // @[RocketCore.scala:458:19, :461:{74,82}]
wire _GEN_40 = mem_waddr == id_raddr1; // @[RocketCore.scala:326:72, :454:38, :461:82]
wire _id_bypass_src_T_2; // @[RocketCore.scala:461:82]
assign _id_bypass_src_T_2 = _GEN_40; // @[RocketCore.scala:461:82]
wire _id_bypass_src_T_3; // @[RocketCore.scala:461:82]
assign _id_bypass_src_T_3 = _GEN_40; // @[RocketCore.scala:461:82]
wire _data_hazard_mem_T; // @[RocketCore.scala:998:72]
assign _data_hazard_mem_T = _GEN_40; // @[RocketCore.scala:461:82, :998:72]
wire _fp_data_hazard_mem_T_1; // @[RocketCore.scala:999:92]
assign _fp_data_hazard_mem_T_1 = _GEN_40; // @[RocketCore.scala:461:82, :999:92]
wire id_bypass_src_0_2 = bypass_sources_2_1 & _id_bypass_src_T_2; // @[RocketCore.scala:459:36, :461:{74,82}]
wire id_bypass_src_0_3 = bypass_sources_3_1 & _id_bypass_src_T_3; // @[RocketCore.scala:460:20, :461:{74,82}]
wire _id_bypass_src_T_4 = ~(|id_raddr2); // @[RocketCore.scala:326:72, :461:82, :1326:41]
wire id_bypass_src_1_0 = _id_bypass_src_T_4; // @[RocketCore.scala:461:{74,82}]
wire _GEN_41 = ex_waddr == id_raddr2; // @[RocketCore.scala:326:72, :453:36, :461:82]
wire _id_bypass_src_T_5; // @[RocketCore.scala:461:82]
assign _id_bypass_src_T_5 = _GEN_41; // @[RocketCore.scala:461:82]
wire _data_hazard_ex_T_2; // @[RocketCore.scala:989:70]
assign _data_hazard_ex_T_2 = _GEN_41; // @[RocketCore.scala:461:82, :989:70]
wire _fp_data_hazard_ex_T_3; // @[RocketCore.scala:990:90]
assign _fp_data_hazard_ex_T_3 = _GEN_41; // @[RocketCore.scala:461:82, :990:90]
wire id_bypass_src_1_1 = bypass_sources_1_1 & _id_bypass_src_T_5; // @[RocketCore.scala:458:19, :461:{74,82}]
wire _GEN_42 = mem_waddr == id_raddr2; // @[RocketCore.scala:326:72, :454:38, :461:82]
wire _id_bypass_src_T_6; // @[RocketCore.scala:461:82]
assign _id_bypass_src_T_6 = _GEN_42; // @[RocketCore.scala:461:82]
wire _id_bypass_src_T_7; // @[RocketCore.scala:461:82]
assign _id_bypass_src_T_7 = _GEN_42; // @[RocketCore.scala:461:82]
wire _data_hazard_mem_T_2; // @[RocketCore.scala:998:72]
assign _data_hazard_mem_T_2 = _GEN_42; // @[RocketCore.scala:461:82, :998:72]
wire _fp_data_hazard_mem_T_3; // @[RocketCore.scala:999:92]
assign _fp_data_hazard_mem_T_3 = _GEN_42; // @[RocketCore.scala:461:82, :999:92]
wire id_bypass_src_1_2 = bypass_sources_2_1 & _id_bypass_src_T_6; // @[RocketCore.scala:459:36, :461:{74,82}]
wire id_bypass_src_1_3 = bypass_sources_3_1 & _id_bypass_src_T_7; // @[RocketCore.scala:460:20, :461:{74,82}]
reg ex_reg_rs_bypass_0; // @[RocketCore.scala:465:29]
reg ex_reg_rs_bypass_1; // @[RocketCore.scala:465:29]
reg [1:0] ex_reg_rs_lsb_0; // @[RocketCore.scala:466:26]
reg [1:0] ex_reg_rs_lsb_1; // @[RocketCore.scala:466:26]
reg [61:0] ex_reg_rs_msb_0; // @[RocketCore.scala:467:26]
reg [61:0] ex_reg_rs_msb_1; // @[RocketCore.scala:467:26]
wire _ex_rs_T = ex_reg_rs_lsb_0 == 2'h1; // @[package.scala:39:86]
wire [63:0] _ex_rs_T_1 = _ex_rs_T ? mem_reg_wdata : 64'h0; // @[package.scala:39:{76,86}]
wire _ex_rs_T_2 = ex_reg_rs_lsb_0 == 2'h2; // @[package.scala:39:86]
wire [63:0] _ex_rs_T_3 = _ex_rs_T_2 ? wb_reg_wdata : _ex_rs_T_1; // @[package.scala:39:{76,86}]
wire _ex_rs_T_4 = &ex_reg_rs_lsb_0; // @[package.scala:39:86]
wire [63:0] _ex_rs_T_5 = _ex_rs_T_4 ? dcache_bypass_data : _ex_rs_T_3; // @[package.scala:39:{76,86}]
wire [63:0] _ex_rs_T_6 = {ex_reg_rs_msb_0, ex_reg_rs_lsb_0}; // @[RocketCore.scala:466:26, :467:26, :469:69]
assign ex_rs_0 = ex_reg_rs_bypass_0 ? _ex_rs_T_5 : _ex_rs_T_6; // @[package.scala:39:76]
assign io_fpu_fromint_data_0 = ex_rs_0; // @[RocketCore.scala:153:7, :469:14]
wire [63:0] _ex_op1_T = ex_rs_0; // @[RocketCore.scala:469:14, :473:24]
wire _ex_rs_T_7 = ex_reg_rs_lsb_1 == 2'h1; // @[package.scala:39:86]
wire [63:0] _ex_rs_T_8 = _ex_rs_T_7 ? mem_reg_wdata : 64'h0; // @[package.scala:39:{76,86}]
wire _ex_rs_T_9 = ex_reg_rs_lsb_1 == 2'h2; // @[package.scala:39:86]
wire [63:0] _ex_rs_T_10 = _ex_rs_T_9 ? wb_reg_wdata : _ex_rs_T_8; // @[package.scala:39:{76,86}]
wire _ex_rs_T_11 = &ex_reg_rs_lsb_1; // @[package.scala:39:86]
wire [63:0] _ex_rs_T_12 = _ex_rs_T_11 ? dcache_bypass_data : _ex_rs_T_10; // @[package.scala:39:{76,86}]
wire [63:0] _ex_rs_T_13 = {ex_reg_rs_msb_1, ex_reg_rs_lsb_1}; // @[RocketCore.scala:466:26, :467:26, :469:69]
wire [63:0] ex_rs_1 = ex_reg_rs_bypass_1 ? _ex_rs_T_12 : _ex_rs_T_13; // @[package.scala:39:76]
wire [63:0] _ex_op2_T = ex_rs_1; // @[RocketCore.scala:469:14, :479:24]
wire [63:0] mem_reg_rs2_dat_padded = ex_rs_1; // @[RocketCore.scala:469:14]
wire _GEN_43 = ex_ctrl_sel_imm == 3'h5; // @[RocketCore.scala:243:20, :1341:24]
wire _ex_imm_sign_T; // @[RocketCore.scala:1341:24]
assign _ex_imm_sign_T = _GEN_43; // @[RocketCore.scala:1341:24]
wire _ex_imm_b11_T_1; // @[RocketCore.scala:1344:40]
assign _ex_imm_b11_T_1 = _GEN_43; // @[RocketCore.scala:1341:24, :1344:40]
wire _ex_imm_b10_5_T_1; // @[RocketCore.scala:1347:42]
assign _ex_imm_b10_5_T_1 = _GEN_43; // @[RocketCore.scala:1341:24, :1347:42]
wire _ex_imm_b4_1_T_5; // @[RocketCore.scala:1350:24]
assign _ex_imm_b4_1_T_5 = _GEN_43; // @[RocketCore.scala:1341:24, :1350:24]
wire _ex_imm_b0_T_4; // @[RocketCore.scala:1353:22]
assign _ex_imm_b0_T_4 = _GEN_43; // @[RocketCore.scala:1341:24, :1353:22]
wire _ex_imm_sign_T_1 = ex_reg_inst[31]; // @[RocketCore.scala:259:24, :1341:44]
wire _ex_imm_sign_T_2 = _ex_imm_sign_T_1; // @[RocketCore.scala:1341:{44,49}]
wire ex_imm_sign = ~_ex_imm_sign_T & _ex_imm_sign_T_2; // @[RocketCore.scala:1341:{19,24,49}]
wire ex_imm_hi_hi_hi = ex_imm_sign; // @[RocketCore.scala:1341:19, :1355:8]
wire _GEN_44 = ex_ctrl_sel_imm == 3'h2; // @[RocketCore.scala:243:20, :1342:26]
wire _ex_imm_b30_20_T; // @[RocketCore.scala:1342:26]
assign _ex_imm_b30_20_T = _GEN_44; // @[RocketCore.scala:1342:26]
wire _ex_imm_b11_T; // @[RocketCore.scala:1344:23]
assign _ex_imm_b11_T = _GEN_44; // @[RocketCore.scala:1342:26, :1344:23]
wire _ex_imm_b10_5_T; // @[RocketCore.scala:1347:25]
assign _ex_imm_b10_5_T = _GEN_44; // @[RocketCore.scala:1342:26, :1347:25]
wire _ex_imm_b4_1_T; // @[RocketCore.scala:1348:24]
assign _ex_imm_b4_1_T = _GEN_44; // @[RocketCore.scala:1342:26, :1348:24]
wire [10:0] _ex_imm_b30_20_T_1 = ex_reg_inst[30:20]; // @[RocketCore.scala:259:24, :1342:41]
wire [10:0] _ex_imm_b30_20_T_2 = _ex_imm_b30_20_T_1; // @[RocketCore.scala:1342:{41,49}]
wire [10:0] ex_imm_b30_20 = _ex_imm_b30_20_T ? _ex_imm_b30_20_T_2 : {11{ex_imm_sign}}; // @[RocketCore.scala:1341:19, :1342:{21,26,49}]
wire [10:0] ex_imm_hi_hi_lo = ex_imm_b30_20; // @[RocketCore.scala:1342:21, :1355:8]
wire _ex_imm_b19_12_T = ex_ctrl_sel_imm != 3'h2; // @[RocketCore.scala:243:20, :1343:26]
wire _ex_imm_b19_12_T_1 = ex_ctrl_sel_imm != 3'h3; // @[RocketCore.scala:243:20, :1343:43]
wire _ex_imm_b19_12_T_2 = _ex_imm_b19_12_T & _ex_imm_b19_12_T_1; // @[RocketCore.scala:1343:{26,36,43}]
wire [7:0] _ex_imm_b19_12_T_3 = ex_reg_inst[19:12]; // @[RocketCore.scala:259:24, :1343:65]
wire [7:0] _ex_imm_b19_12_T_4 = _ex_imm_b19_12_T_3; // @[RocketCore.scala:1343:{65,73}]
wire [7:0] ex_imm_b19_12 = _ex_imm_b19_12_T_2 ? {8{ex_imm_sign}} : _ex_imm_b19_12_T_4; // @[RocketCore.scala:1341:19, :1343:{21,36,73}]
wire [7:0] ex_imm_hi_lo_hi = ex_imm_b19_12; // @[RocketCore.scala:1343:21, :1355:8]
wire _ex_imm_b11_T_2 = _ex_imm_b11_T | _ex_imm_b11_T_1; // @[RocketCore.scala:1344:{23,33,40}]
wire _ex_imm_b11_T_3 = ex_ctrl_sel_imm == 3'h3; // @[RocketCore.scala:243:20, :1345:23]
wire _ex_imm_b11_T_4 = ex_reg_inst[20]; // @[RocketCore.scala:259:24, :1345:39]
wire _ex_imm_b0_T_3 = ex_reg_inst[20]; // @[RocketCore.scala:259:24, :1345:39, :1352:37]
wire _io_dmem_req_bits_signed_T = ex_reg_inst[20]; // @[RocketCore.scala:259:24, :1136:58, :1345:39]
wire _ex_imm_b11_T_5 = _ex_imm_b11_T_4; // @[RocketCore.scala:1345:{39,44}]
wire _GEN_45 = ex_ctrl_sel_imm == 3'h1; // @[RocketCore.scala:243:20, :1346:23]
wire _ex_imm_b11_T_6; // @[RocketCore.scala:1346:23]
assign _ex_imm_b11_T_6 = _GEN_45; // @[RocketCore.scala:1346:23]
wire _ex_imm_b4_1_T_2; // @[RocketCore.scala:1349:41]
assign _ex_imm_b4_1_T_2 = _GEN_45; // @[RocketCore.scala:1346:23, :1349:41]
wire _ex_imm_b11_T_7 = ex_reg_inst[7]; // @[RocketCore.scala:259:24, :1346:39]
wire _ex_imm_b0_T_1 = ex_reg_inst[7]; // @[RocketCore.scala:259:24, :1346:39, :1351:37]
wire _ex_imm_b11_T_8 = _ex_imm_b11_T_7; // @[RocketCore.scala:1346:{39,43}]
wire _ex_imm_b11_T_9 = _ex_imm_b11_T_6 ? _ex_imm_b11_T_8 : ex_imm_sign; // @[RocketCore.scala:1341:19, :1346:{18,23,43}]
wire _ex_imm_b11_T_10 = _ex_imm_b11_T_3 ? _ex_imm_b11_T_5 : _ex_imm_b11_T_9; // @[RocketCore.scala:1345:{18,23,44}, :1346:18]
wire ex_imm_b11 = ~_ex_imm_b11_T_2 & _ex_imm_b11_T_10; // @[RocketCore.scala:1344:{18,33}, :1345:18]
wire ex_imm_hi_lo_lo = ex_imm_b11; // @[RocketCore.scala:1344:18, :1355:8]
wire _ex_imm_b10_5_T_2 = _ex_imm_b10_5_T | _ex_imm_b10_5_T_1; // @[RocketCore.scala:1347:{25,35,42}]
wire [5:0] _ex_imm_b10_5_T_3 = ex_reg_inst[30:25]; // @[RocketCore.scala:259:24, :1347:62]
wire [5:0] ex_imm_b10_5 = _ex_imm_b10_5_T_2 ? 6'h0 : _ex_imm_b10_5_T_3; // @[RocketCore.scala:1347:{20,35,62}]
wire _GEN_46 = ex_ctrl_sel_imm == 3'h0; // @[RocketCore.scala:243:20, :1349:24]
wire _ex_imm_b4_1_T_1; // @[RocketCore.scala:1349:24]
assign _ex_imm_b4_1_T_1 = _GEN_46; // @[RocketCore.scala:1349:24]
wire _ex_imm_b0_T; // @[RocketCore.scala:1351:22]
assign _ex_imm_b0_T = _GEN_46; // @[RocketCore.scala:1349:24, :1351:22]
wire _ex_imm_b4_1_T_3 = _ex_imm_b4_1_T_1 | _ex_imm_b4_1_T_2; // @[RocketCore.scala:1349:{24,34,41}]
wire [3:0] _ex_imm_b4_1_T_4 = ex_reg_inst[11:8]; // @[RocketCore.scala:259:24, :1349:57]
wire [3:0] _ex_imm_b4_1_T_6 = ex_reg_inst[19:16]; // @[RocketCore.scala:259:24, :1350:39]
wire [3:0] _ex_imm_b4_1_T_7 = ex_reg_inst[24:21]; // @[RocketCore.scala:259:24, :1350:52]
wire [3:0] _ex_imm_b4_1_T_8 = _ex_imm_b4_1_T_5 ? _ex_imm_b4_1_T_6 : _ex_imm_b4_1_T_7; // @[RocketCore.scala:1350:{19,24,39,52}]
wire [3:0] _ex_imm_b4_1_T_9 = _ex_imm_b4_1_T_3 ? _ex_imm_b4_1_T_4 : _ex_imm_b4_1_T_8; // @[RocketCore.scala:1349:{19,34,57}, :1350:19]
wire [3:0] ex_imm_b4_1 = _ex_imm_b4_1_T ? 4'h0 : _ex_imm_b4_1_T_9; // @[RocketCore.scala:1348:{19,24}, :1349:19]
wire _ex_imm_b0_T_2 = ex_ctrl_sel_imm == 3'h4; // @[RocketCore.scala:243:20, :1352:22]
wire _ex_imm_b0_T_5 = ex_reg_inst[15]; // @[RocketCore.scala:259:24, :1353:37]
wire _ex_imm_b0_T_6 = _ex_imm_b0_T_4 & _ex_imm_b0_T_5; // @[RocketCore.scala:1353:{17,22,37}]
wire _ex_imm_b0_T_7 = _ex_imm_b0_T_2 ? _ex_imm_b0_T_3 : _ex_imm_b0_T_6; // @[RocketCore.scala:1352:{17,22,37}, :1353:17]
wire ex_imm_b0 = _ex_imm_b0_T ? _ex_imm_b0_T_1 : _ex_imm_b0_T_7; // @[RocketCore.scala:1351:{17,22,37}, :1352:17]
wire [9:0] ex_imm_lo_hi = {ex_imm_b10_5, ex_imm_b4_1}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8]
wire [10:0] ex_imm_lo = {ex_imm_lo_hi, ex_imm_b0}; // @[RocketCore.scala:1351:17, :1355:8]
wire [8:0] ex_imm_hi_lo = {ex_imm_hi_lo_hi, ex_imm_hi_lo_lo}; // @[RocketCore.scala:1355:8]
wire [11:0] ex_imm_hi_hi = {ex_imm_hi_hi_hi, ex_imm_hi_hi_lo}; // @[RocketCore.scala:1355:8]
wire [20:0] ex_imm_hi = {ex_imm_hi_hi, ex_imm_hi_lo}; // @[RocketCore.scala:1355:8]
wire [31:0] _ex_imm_T = {ex_imm_hi, ex_imm_lo}; // @[RocketCore.scala:1355:8]
wire [31:0] ex_imm = _ex_imm_T; // @[RocketCore.scala:1355:{8,53}]
wire _ex_rs1shl_T = ex_reg_inst[3]; // @[RocketCore.scala:259:24, :471:34]
wire [31:0] _ex_rs1shl_T_1 = ex_rs_0[31:0]; // @[RocketCore.scala:469:14, :471:47]
wire [63:0] _ex_rs1shl_T_2 = _ex_rs1shl_T ? {32'h0, _ex_rs1shl_T_1} : ex_rs_0; // @[RocketCore.scala:469:14, :471:{22,34,47}]
wire [1:0] _ex_rs1shl_T_3 = ex_reg_inst[14:13]; // @[RocketCore.scala:259:24, :471:79]
wire [66:0] ex_rs1shl = {3'h0, _ex_rs1shl_T_2} << _ex_rs1shl_T_3; // @[RocketCore.scala:471:{22,65,79}]
wire [66:0] _ex_op1_T_2 = ex_rs1shl; // @[RocketCore.scala:471:65, :475:54]
wire _ex_op1_T_3 = ex_ctrl_sel_alu1 == 2'h1; // @[RocketCore.scala:243:20, :472:48]
wire [63:0] _ex_op1_T_4 = _ex_op1_T_3 ? _ex_op1_T : 64'h0; // @[RocketCore.scala:472:48, :473:24]
wire _ex_op1_T_5 = ex_ctrl_sel_alu1 == 2'h2; // @[RocketCore.scala:243:20, :472:48]
wire [63:0] _ex_op1_T_6 = _ex_op1_T_5 ? {{24{_ex_op1_T_1[39]}}, _ex_op1_T_1} : _ex_op1_T_4; // @[RocketCore.scala:472:48, :474:24]
wire _ex_op1_T_7 = &ex_ctrl_sel_alu1; // @[RocketCore.scala:243:20, :472:48]
wire [66:0] ex_op1 = _ex_op1_T_7 ? _ex_op1_T_2 : {{3{_ex_op1_T_6[63]}}, _ex_op1_T_6}; // @[RocketCore.scala:472:48, :475:54]
wire [66:0] _alu_io_in1_T = ex_op1; // @[RocketCore.scala:472:48, :508:24]
wire _ex_op2_oh_T = ex_ctrl_sel_alu2[0]; // @[RocketCore.scala:243:20, :477:48]
wire [11:0] _ex_op2_oh_T_1 = ex_reg_inst[31:20]; // @[RocketCore.scala:259:24, :477:66]
wire [63:0] _ex_op2_oh_T_2 = _ex_op2_oh_T ? {52'h0, _ex_op2_oh_T_1} : ex_rs_1; // @[RocketCore.scala:469:14, :477:{31,48,66}]
wire [5:0] _ex_op2_oh_T_3 = _ex_op2_oh_T_2[5:0]; // @[RocketCore.scala:477:{31,90}]
wire [63:0] _ex_op2_oh_T_4 = 64'h1 << _ex_op2_oh_T_3; // @[OneHot.scala:58:35]
wire [63:0] ex_op2_oh = _ex_op2_oh_T_4; // @[OneHot.scala:58:35]
wire [3:0] _ex_op2_T_1 = ex_reg_rvc ? 4'h2 : 4'h4; // @[RocketCore.scala:249:35, :481:19]
wire _ex_op2_T_2 = ex_ctrl_sel_alu2 == 3'h2; // @[RocketCore.scala:243:20, :478:48]
wire [63:0] _ex_op2_T_3 = _ex_op2_T_2 ? _ex_op2_T : 64'h0; // @[RocketCore.scala:478:48, :479:24]
wire _ex_op2_T_4 = ex_ctrl_sel_alu2 == 3'h3; // @[RocketCore.scala:243:20, :478:48]
wire [63:0] _ex_op2_T_5 = _ex_op2_T_4 ? {{32{ex_imm[31]}}, ex_imm} : _ex_op2_T_3; // @[RocketCore.scala:478:48, :1355:53]
wire _ex_op2_T_6 = ex_ctrl_sel_alu2 == 3'h1; // @[RocketCore.scala:243:20, :478:48]
wire [63:0] _ex_op2_T_7 = _ex_op2_T_6 ? {{60{_ex_op2_T_1[3]}}, _ex_op2_T_1} : _ex_op2_T_5; // @[RocketCore.scala:478:48, :481:19]
wire _ex_op2_T_8 = ex_ctrl_sel_alu2 == 3'h4; // @[RocketCore.scala:243:20, :478:48]
wire [63:0] _ex_op2_T_9 = _ex_op2_T_8 ? ex_op2_oh : _ex_op2_T_7; // @[RocketCore.scala:477:112, :478:48]
wire _ex_op2_T_10 = ex_ctrl_sel_alu2 == 3'h5; // @[RocketCore.scala:243:20, :478:48]
wire [63:0] ex_op2 = _ex_op2_T_10 ? ex_op2_oh : _ex_op2_T_9; // @[RocketCore.scala:477:112, :478:48]
wire [63:0] _alu_io_in2_T = ex_op2; // @[RocketCore.scala:478:48, :507:24]
wire _div_io_req_valid_T = ex_reg_valid & ex_ctrl_div; // @[RocketCore.scala:243:20, :248:35, :512:36]
wire _ex_reg_valid_T = ~ctrl_killd; // @[RocketCore.scala:338:24, :525:19]
wire _ex_reg_replay_T = ~take_pc_mem_wb; // @[RocketCore.scala:307:35, :526:20]
wire _ex_reg_replay_T_1 = _ex_reg_replay_T & _ibuf_io_inst_0_valid; // @[RocketCore.scala:311:20, :526:{20,29}]
wire _ex_reg_replay_T_2 = _ex_reg_replay_T_1 & _ibuf_io_inst_0_bits_replay; // @[RocketCore.scala:311:20, :526:{29,54}]
wire _ex_reg_xcpt_T = ~ctrl_killd; // @[RocketCore.scala:338:24, :525:19, :527:18]
wire _ex_reg_xcpt_T_1 = _ex_reg_xcpt_T & id_xcpt; // @[RocketCore.scala:527:{18,30}, :1278:14]
wire _ex_reg_xcpt_interrupt_T = ~take_pc_mem_wb; // @[RocketCore.scala:307:35, :526:20, :528:28]
wire _ex_reg_xcpt_interrupt_T_1 = _ex_reg_xcpt_interrupt_T & _ibuf_io_inst_0_valid; // @[RocketCore.scala:311:20, :528:{28,37}]
wire _ex_reg_xcpt_interrupt_T_2 = _ex_reg_xcpt_interrupt_T_1 & _csr_io_interrupt; // @[RocketCore.scala:341:19, :528:{37,62}]
wire [1:0] hi = {_ibuf_io_inst_0_bits_xcpt1_pf_inst, _ibuf_io_inst_0_bits_xcpt1_gf_inst}; // @[RocketCore.scala:311:20, :541:22]
wire [1:0] hi_1 = {_ibuf_io_inst_0_bits_xcpt0_pf_inst, _ibuf_io_inst_0_bits_xcpt0_gf_inst}; // @[RocketCore.scala:311:20, :546:40]
wire _ex_reg_flush_pipe_T = id_ctrl_fence_i | id_csr_flush; // @[RocketCore.scala:321:21, :346:37, :551:42]
wire _ex_reg_hls_T_1 = id_ctrl_mem_cmd == 5'h0; // @[package.scala:16:47]
wire _ex_reg_hls_T_2 = id_ctrl_mem_cmd == 5'h1; // @[package.scala:16:47]
wire _ex_reg_hls_T_3 = id_ctrl_mem_cmd == 5'h10; // @[package.scala:16:47]
wire _ex_reg_hls_T_4 = _ex_reg_hls_T_1 | _ex_reg_hls_T_2; // @[package.scala:16:47, :81:59]
wire _ex_reg_hls_T_5 = _ex_reg_hls_T_4 | _ex_reg_hls_T_3; // @[package.scala:16:47, :81:59]
wire [1:0] _ex_reg_mem_size_T_1 = _ibuf_io_inst_0_bits_inst_bits[27:26]; // @[RocketCore.scala:311:20, :554:75]
wire [1:0] _ex_reg_mem_size_T_2 = _ibuf_io_inst_0_bits_inst_bits[13:12]; // @[RocketCore.scala:311:20, :554:95]
wire [1:0] _ex_reg_mem_size_T_3 = _ex_reg_mem_size_T_2; // @[RocketCore.scala:554:{27,95}]
wire _ex_reg_mem_size_T_4 = |id_raddr2; // @[RocketCore.scala:326:72, :556:40, :1326:41]
wire _ex_reg_mem_size_T_5 = |id_raddr1; // @[RocketCore.scala:326:72, :556:59, :1326:41]
wire [1:0] _ex_reg_mem_size_T_6 = {_ex_reg_mem_size_T_4, _ex_reg_mem_size_T_5}; // @[RocketCore.scala:556:{29,40,59}]
wire _do_bypass_T = id_bypass_src_0_0 | id_bypass_src_0_1; // @[RocketCore.scala:461:74, :568:48]
wire _do_bypass_T_1 = _do_bypass_T | id_bypass_src_0_2; // @[RocketCore.scala:461:74, :568:48]
wire do_bypass = _do_bypass_T_1 | id_bypass_src_0_3; // @[RocketCore.scala:461:74, :568:48]
wire [1:0] _bypass_src_T = {1'h1, ~id_bypass_src_0_2}; // @[Mux.scala:50:70]
wire [1:0] _bypass_src_T_1 = id_bypass_src_0_1 ? 2'h1 : _bypass_src_T; // @[Mux.scala:50:70]
wire [1:0] bypass_src = id_bypass_src_0_0 ? 2'h0 : _bypass_src_T_1; // @[Mux.scala:50:70]
wire [1:0] _ex_reg_rs_lsb_0_T = id_rs_0[1:0]; // @[RocketCore.scala:573:37, :1325:26]
wire [61:0] _ex_reg_rs_msb_0_T = id_rs_0[63:2]; // @[RocketCore.scala:574:38, :1325:26]
wire _do_bypass_T_2 = id_bypass_src_1_0 | id_bypass_src_1_1; // @[RocketCore.scala:461:74, :568:48]
wire _do_bypass_T_3 = _do_bypass_T_2 | id_bypass_src_1_2; // @[RocketCore.scala:461:74, :568:48]
wire do_bypass_1 = _do_bypass_T_3 | id_bypass_src_1_3; // @[RocketCore.scala:461:74, :568:48]
wire [1:0] _bypass_src_T_2 = {1'h1, ~id_bypass_src_1_2}; // @[Mux.scala:50:70]
wire [1:0] _bypass_src_T_3 = id_bypass_src_1_1 ? 2'h1 : _bypass_src_T_2; // @[Mux.scala:50:70]
wire [1:0] bypass_src_1 = id_bypass_src_1_0 ? 2'h0 : _bypass_src_T_3; // @[Mux.scala:50:70]
wire [1:0] _ex_reg_rs_lsb_1_T = id_rs_1[1:0]; // @[RocketCore.scala:573:37, :1325:26]
wire [61:0] _ex_reg_rs_msb_1_T = id_rs_1[63:2]; // @[RocketCore.scala:574:38, :1325:26]
wire [15:0] _inst_T = _ibuf_io_inst_0_bits_raw[15:0]; // @[RocketCore.scala:311:20, :578:62]
wire [31:0] inst = _ibuf_io_inst_0_bits_rvc ? {16'h0, _inst_T} : _ibuf_io_inst_0_bits_raw; // @[RocketCore.scala:311:20, :578:{21,62}]
wire [1:0] _ex_reg_rs_lsb_0_T_1 = inst[1:0]; // @[RocketCore.scala:578:21, :580:31]
wire [29:0] _ex_reg_rs_msb_0_T_1 = inst[31:2]; // @[RocketCore.scala:578:21, :581:32]
wire _ex_reg_set_vconfig_T = ~id_xcpt; // @[RocketCore.scala:591:45, :1278:14]
wire _ex_pc_valid_T = ex_reg_valid | ex_reg_replay; // @[RocketCore.scala:248:35, :255:26, :595:34]
wire ex_pc_valid = _ex_pc_valid_T | ex_reg_xcpt_interrupt; // @[RocketCore.scala:247:35, :595:{34,51}]
wire _wb_dcache_miss_T = ~io_dmem_resp_valid_0; // @[RocketCore.scala:153:7, :596:39]
wire wb_dcache_miss = wb_ctrl_mem & _wb_dcache_miss_T; // @[RocketCore.scala:245:20, :596:{36,39}]
wire _replay_ex_structural_T = ~io_dmem_req_ready_0; // @[RocketCore.scala:153:7, :597:45]
wire _replay_ex_structural_T_1 = ex_ctrl_mem & _replay_ex_structural_T; // @[RocketCore.scala:243:20, :597:{42,45}]
wire _replay_ex_structural_T_2 = ~_div_io_req_ready; // @[RocketCore.scala:511:19, :598:45]
wire _replay_ex_structural_T_3 = ex_ctrl_div & _replay_ex_structural_T_2; // @[RocketCore.scala:243:20, :598:{42,45}]
wire _replay_ex_structural_T_4 = _replay_ex_structural_T_1 | _replay_ex_structural_T_3; // @[RocketCore.scala:597:{42,64}, :598:42]
wire replay_ex_structural = _replay_ex_structural_T_4; // @[RocketCore.scala:597:64, :598:63]
wire replay_ex_load_use = wb_dcache_miss & ex_reg_load_use; // @[RocketCore.scala:253:35, :596:36, :600:43]
wire _replay_ex_T = replay_ex_structural | replay_ex_load_use; // @[RocketCore.scala:598:63, :600:43, :601:75]
wire _replay_ex_T_1 = ex_reg_valid & _replay_ex_T; // @[RocketCore.scala:248:35, :601:{50,75}]
wire replay_ex = ex_reg_replay | _replay_ex_T_1; // @[RocketCore.scala:255:26, :601:{33,50}]
wire _ctrl_killx_T = take_pc_mem_wb | replay_ex; // @[RocketCore.scala:307:35, :601:33, :602:35]
wire _ctrl_killx_T_1 = ~ex_reg_valid; // @[RocketCore.scala:248:35, :602:51]
assign ctrl_killx = _ctrl_killx_T | _ctrl_killx_T_1; // @[RocketCore.scala:602:{35,48,51}]
assign io_fpu_killx_0 = ctrl_killx; // @[RocketCore.scala:153:7, :602:48]
wire _GEN_47 = ex_ctrl_mem_cmd == 5'h7; // @[RocketCore.scala:243:20, :604:40]
wire _ex_slow_bypass_T; // @[RocketCore.scala:604:40]
assign _ex_slow_bypass_T = _GEN_47; // @[RocketCore.scala:604:40]
wire _mem_reg_load_T_3; // @[package.scala:16:47]
assign _mem_reg_load_T_3 = _GEN_47; // @[package.scala:16:47]
wire _mem_reg_store_T_3; // @[Consts.scala:90:66]
assign _mem_reg_store_T_3 = _GEN_47; // @[RocketCore.scala:604:40]
wire _io_dmem_req_bits_no_resp_T_3; // @[package.scala:16:47]
assign _io_dmem_req_bits_no_resp_T_3 = _GEN_47; // @[package.scala:16:47]
wire _ex_slow_bypass_T_1 = ~(ex_reg_mem_size[1]); // @[RocketCore.scala:257:28, :604:69]
wire ex_slow_bypass = _ex_slow_bypass_T | _ex_slow_bypass_T_1; // @[RocketCore.scala:604:{40,50,69}]
wire _ex_sfence_T_1 = ex_ctrl_mem_cmd == 5'h14; // @[RocketCore.scala:243:20, :605:64]
wire _ex_sfence_T_2 = ex_ctrl_mem_cmd == 5'h15; // @[RocketCore.scala:243:20, :605:96]
wire _ex_sfence_T_3 = _ex_sfence_T_1 | _ex_sfence_T_2; // @[RocketCore.scala:605:{64,77,96}]
wire _ex_sfence_T_4 = ex_ctrl_mem_cmd == 5'h16; // @[RocketCore.scala:243:20, :605:129]
wire _ex_sfence_T_5 = _ex_sfence_T_3 | _ex_sfence_T_4; // @[RocketCore.scala:605:{77,110,129}]
wire ex_sfence = _ex_sfence_T & _ex_sfence_T_5; // @[RocketCore.scala:605:{29,44,110}]
wire ex_xcpt = ex_reg_xcpt_interrupt | ex_reg_xcpt; // @[RocketCore.scala:247:35, :251:35, :608:28, :1278:14]
wire _mem_pc_valid_T = mem_reg_valid | mem_reg_replay; // @[RocketCore.scala:265:36, :269:36, :614:36]
wire mem_pc_valid = _mem_pc_valid_T | mem_reg_xcpt_interrupt; // @[RocketCore.scala:264:36, :614:{36,54}]
wire _GEN_48 = mem_ctrl_branch & mem_br_taken; // @[RocketCore.scala:244:21, :284:25, :616:25]
wire _mem_br_target_T_1; // @[RocketCore.scala:616:25]
assign _mem_br_target_T_1 = _GEN_48; // @[RocketCore.scala:616:25]
wire _mem_cfi_taken_T; // @[RocketCore.scala:626:40]
assign _mem_cfi_taken_T = _GEN_48; // @[RocketCore.scala:616:25, :626:40]
wire _mem_br_target_sign_T_1 = mem_reg_inst[31]; // @[RocketCore.scala:278:25, :1341:44]
wire _mem_br_target_sign_T_4 = mem_reg_inst[31]; // @[RocketCore.scala:278:25, :1341:44]
wire _mem_br_target_sign_T_2 = _mem_br_target_sign_T_1; // @[RocketCore.scala:1341:{44,49}]
wire mem_br_target_sign = _mem_br_target_sign_T_2; // @[RocketCore.scala:1341:{19,49}]
wire mem_br_target_hi_hi_hi = mem_br_target_sign; // @[RocketCore.scala:1341:19, :1355:8]
wire [10:0] _mem_br_target_b30_20_T_1 = mem_reg_inst[30:20]; // @[RocketCore.scala:278:25, :1342:41]
wire [10:0] _mem_br_target_b30_20_T_4 = mem_reg_inst[30:20]; // @[RocketCore.scala:278:25, :1342:41]
wire [10:0] _mem_br_target_b30_20_T_2 = _mem_br_target_b30_20_T_1; // @[RocketCore.scala:1342:{41,49}]
wire [10:0] mem_br_target_b30_20 = {11{mem_br_target_sign}}; // @[RocketCore.scala:1341:19, :1342:21]
wire [10:0] mem_br_target_hi_hi_lo = mem_br_target_b30_20; // @[RocketCore.scala:1342:21, :1355:8]
wire [7:0] _mem_br_target_b19_12_T_3 = mem_reg_inst[19:12]; // @[RocketCore.scala:278:25, :1343:65]
wire [7:0] _mem_br_target_b19_12_T_8 = mem_reg_inst[19:12]; // @[RocketCore.scala:278:25, :1343:65]
wire [7:0] _mem_br_target_b19_12_T_4 = _mem_br_target_b19_12_T_3; // @[RocketCore.scala:1343:{65,73}]
wire [7:0] mem_br_target_b19_12 = {8{mem_br_target_sign}}; // @[RocketCore.scala:1341:19, :1343:21]
wire [7:0] mem_br_target_hi_lo_hi = mem_br_target_b19_12; // @[RocketCore.scala:1343:21, :1355:8]
wire _mem_br_target_b11_T_4 = mem_reg_inst[20]; // @[RocketCore.scala:278:25, :1345:39]
wire _mem_br_target_b0_T_3 = mem_reg_inst[20]; // @[RocketCore.scala:278:25, :1345:39, :1352:37]
wire _mem_br_target_b11_T_15 = mem_reg_inst[20]; // @[RocketCore.scala:278:25, :1345:39]
wire _mem_br_target_b0_T_11 = mem_reg_inst[20]; // @[RocketCore.scala:278:25, :1345:39, :1352:37]
wire _mem_br_target_b11_T_5 = _mem_br_target_b11_T_4; // @[RocketCore.scala:1345:{39,44}]
wire _mem_br_target_b11_T_7 = mem_reg_inst[7]; // @[RocketCore.scala:278:25, :1346:39]
wire _mem_br_target_b0_T_1 = mem_reg_inst[7]; // @[RocketCore.scala:278:25, :1346:39, :1351:37]
wire _mem_br_target_b11_T_18 = mem_reg_inst[7]; // @[RocketCore.scala:278:25, :1346:39]
wire _mem_br_target_b0_T_9 = mem_reg_inst[7]; // @[RocketCore.scala:278:25, :1346:39, :1351:37]
wire _mem_br_target_b11_T_8 = _mem_br_target_b11_T_7; // @[RocketCore.scala:1346:{39,43}]
wire _mem_br_target_b11_T_9 = _mem_br_target_b11_T_8; // @[RocketCore.scala:1346:{18,43}]
wire _mem_br_target_b11_T_10 = _mem_br_target_b11_T_9; // @[RocketCore.scala:1345:18, :1346:18]
wire mem_br_target_b11 = _mem_br_target_b11_T_10; // @[RocketCore.scala:1344:18, :1345:18]
wire mem_br_target_hi_lo_lo = mem_br_target_b11; // @[RocketCore.scala:1344:18, :1355:8]
wire [5:0] _mem_br_target_b10_5_T_3 = mem_reg_inst[30:25]; // @[RocketCore.scala:278:25, :1347:62]
wire [5:0] _mem_br_target_b10_5_T_7 = mem_reg_inst[30:25]; // @[RocketCore.scala:278:25, :1347:62]
wire [5:0] mem_br_target_b10_5 = _mem_br_target_b10_5_T_3; // @[RocketCore.scala:1347:{20,62}]
wire [3:0] _mem_br_target_b4_1_T_4 = mem_reg_inst[11:8]; // @[RocketCore.scala:278:25, :1349:57]
wire [3:0] _mem_br_target_b4_1_T_14 = mem_reg_inst[11:8]; // @[RocketCore.scala:278:25, :1349:57]
wire [3:0] _mem_br_target_b4_1_T_9 = _mem_br_target_b4_1_T_4; // @[RocketCore.scala:1349:{19,57}]
wire [3:0] _mem_br_target_b4_1_T_6 = mem_reg_inst[19:16]; // @[RocketCore.scala:278:25, :1350:39]
wire [3:0] _mem_br_target_b4_1_T_16 = mem_reg_inst[19:16]; // @[RocketCore.scala:278:25, :1350:39]
wire [3:0] _mem_br_target_b4_1_T_7 = mem_reg_inst[24:21]; // @[RocketCore.scala:278:25, :1350:52]
wire [3:0] _mem_br_target_b4_1_T_17 = mem_reg_inst[24:21]; // @[RocketCore.scala:278:25, :1350:52]
wire [3:0] _mem_br_target_b4_1_T_8 = _mem_br_target_b4_1_T_7; // @[RocketCore.scala:1350:{19,52}]
wire [3:0] mem_br_target_b4_1 = _mem_br_target_b4_1_T_9; // @[RocketCore.scala:1348:19, :1349:19]
wire _mem_br_target_b0_T_5 = mem_reg_inst[15]; // @[RocketCore.scala:278:25, :1353:37]
wire _mem_br_target_b0_T_13 = mem_reg_inst[15]; // @[RocketCore.scala:278:25, :1353:37]
wire [9:0] mem_br_target_lo_hi = {mem_br_target_b10_5, mem_br_target_b4_1}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8]
wire [10:0] mem_br_target_lo = {mem_br_target_lo_hi, 1'h0}; // @[RocketCore.scala:1355:8]
wire [8:0] mem_br_target_hi_lo = {mem_br_target_hi_lo_hi, mem_br_target_hi_lo_lo}; // @[RocketCore.scala:1355:8]
wire [11:0] mem_br_target_hi_hi = {mem_br_target_hi_hi_hi, mem_br_target_hi_hi_lo}; // @[RocketCore.scala:1355:8]
wire [20:0] mem_br_target_hi = {mem_br_target_hi_hi, mem_br_target_hi_lo}; // @[RocketCore.scala:1355:8]
wire [31:0] _mem_br_target_T_2 = {mem_br_target_hi, mem_br_target_lo}; // @[RocketCore.scala:1355:8]
wire [31:0] _mem_br_target_T_3 = _mem_br_target_T_2; // @[RocketCore.scala:1355:{8,53}]
wire _mem_br_target_sign_T_5 = _mem_br_target_sign_T_4; // @[RocketCore.scala:1341:{44,49}]
wire mem_br_target_sign_1 = _mem_br_target_sign_T_5; // @[RocketCore.scala:1341:{19,49}]
wire _mem_br_target_b11_T_20 = mem_br_target_sign_1; // @[RocketCore.scala:1341:19, :1346:18]
wire mem_br_target_hi_hi_hi_1 = mem_br_target_sign_1; // @[RocketCore.scala:1341:19, :1355:8]
wire [10:0] _mem_br_target_b30_20_T_5 = _mem_br_target_b30_20_T_4; // @[RocketCore.scala:1342:{41,49}]
wire [10:0] mem_br_target_b30_20_1 = {11{mem_br_target_sign_1}}; // @[RocketCore.scala:1341:19, :1342:21]
wire [10:0] mem_br_target_hi_hi_lo_1 = mem_br_target_b30_20_1; // @[RocketCore.scala:1342:21, :1355:8]
wire [7:0] _mem_br_target_b19_12_T_9 = _mem_br_target_b19_12_T_8; // @[RocketCore.scala:1343:{65,73}]
wire [7:0] mem_br_target_b19_12_1 = _mem_br_target_b19_12_T_9; // @[RocketCore.scala:1343:{21,73}]
wire [7:0] mem_br_target_hi_lo_hi_1 = mem_br_target_b19_12_1; // @[RocketCore.scala:1343:21, :1355:8]
wire _mem_br_target_b11_T_16 = _mem_br_target_b11_T_15; // @[RocketCore.scala:1345:{39,44}]
wire _mem_br_target_b11_T_21 = _mem_br_target_b11_T_16; // @[RocketCore.scala:1345:{18,44}]
wire _mem_br_target_b11_T_19 = _mem_br_target_b11_T_18; // @[RocketCore.scala:1346:{39,43}]
wire mem_br_target_b11_1 = _mem_br_target_b11_T_21; // @[RocketCore.scala:1344:18, :1345:18]
wire mem_br_target_hi_lo_lo_1 = mem_br_target_b11_1; // @[RocketCore.scala:1344:18, :1355:8]
wire [5:0] mem_br_target_b10_5_1 = _mem_br_target_b10_5_T_7; // @[RocketCore.scala:1347:{20,62}]
wire [3:0] _mem_br_target_b4_1_T_18 = _mem_br_target_b4_1_T_17; // @[RocketCore.scala:1350:{19,52}]
wire [3:0] _mem_br_target_b4_1_T_19 = _mem_br_target_b4_1_T_18; // @[RocketCore.scala:1349:19, :1350:19]
wire [3:0] mem_br_target_b4_1_1 = _mem_br_target_b4_1_T_19; // @[RocketCore.scala:1348:19, :1349:19]
wire [9:0] mem_br_target_lo_hi_1 = {mem_br_target_b10_5_1, mem_br_target_b4_1_1}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8]
wire [10:0] mem_br_target_lo_1 = {mem_br_target_lo_hi_1, 1'h0}; // @[RocketCore.scala:1355:8]
wire [8:0] mem_br_target_hi_lo_1 = {mem_br_target_hi_lo_hi_1, mem_br_target_hi_lo_lo_1}; // @[RocketCore.scala:1355:8]
wire [11:0] mem_br_target_hi_hi_1 = {mem_br_target_hi_hi_hi_1, mem_br_target_hi_hi_lo_1}; // @[RocketCore.scala:1355:8]
wire [20:0] mem_br_target_hi_1 = {mem_br_target_hi_hi_1, mem_br_target_hi_lo_1}; // @[RocketCore.scala:1355:8]
wire [31:0] _mem_br_target_T_4 = {mem_br_target_hi_1, mem_br_target_lo_1}; // @[RocketCore.scala:1355:8]
wire [31:0] _mem_br_target_T_5 = _mem_br_target_T_4; // @[RocketCore.scala:1355:{8,53}]
wire [3:0] _mem_br_target_T_6 = mem_reg_rvc ? 4'h2 : 4'h4; // @[RocketCore.scala:266:36, :618:8]
wire [31:0] _mem_br_target_T_7 = mem_ctrl_jal ? _mem_br_target_T_5 : {{28{_mem_br_target_T_6[3]}}, _mem_br_target_T_6}; // @[RocketCore.scala:244:21, :617:8, :618:8, :1355:53]
wire [31:0] _mem_br_target_T_8 = _mem_br_target_T_1 ? _mem_br_target_T_3 : _mem_br_target_T_7; // @[RocketCore.scala:616:{8,25}, :617:8, :1355:53]
wire [40:0] _mem_br_target_T_9 = {_mem_br_target_T[39], _mem_br_target_T} + {{9{_mem_br_target_T_8[31]}}, _mem_br_target_T_8}; // @[RocketCore.scala:615:{34,41}, :616:8]
wire [39:0] _mem_br_target_T_10 = _mem_br_target_T_9[39:0]; // @[RocketCore.scala:615:41]
wire [39:0] mem_br_target = _mem_br_target_T_10; // @[RocketCore.scala:615:41]
wire _mem_npc_T = mem_ctrl_jalr | mem_reg_sfence; // @[RocketCore.scala:244:21, :276:27, :619:36]
wire [24:0] _mem_npc_a_T = mem_reg_wdata[63:39]; // @[RocketCore.scala:282:26, :1293:17]
wire [24:0] mem_npc_a = _mem_npc_a_T; // @[RocketCore.scala:1293:{17,23}]
wire _mem_npc_msb_T = mem_npc_a == 25'h0; // @[RocketCore.scala:1293:23, :1294:21]
wire _mem_npc_msb_T_1 = &mem_npc_a; // @[RocketCore.scala:1293:23, :1294:34]
wire _mem_npc_msb_T_2 = _mem_npc_msb_T | _mem_npc_msb_T_1; // @[RocketCore.scala:1294:{21,29,34}]
wire _mem_npc_msb_T_3 = mem_reg_wdata[39]; // @[RocketCore.scala:282:26, :1294:46]
wire _mem_npc_msb_T_4 = mem_reg_wdata[38]; // @[RocketCore.scala:282:26, :1294:54]
wire _mem_npc_msb_T_5 = ~_mem_npc_msb_T_4; // @[RocketCore.scala:1294:{51,54}]
wire mem_npc_msb = _mem_npc_msb_T_2 ? _mem_npc_msb_T_3 : _mem_npc_msb_T_5; // @[RocketCore.scala:1294:{18,29,46,51}]
wire [39:0] _mem_npc_T_2 = {mem_npc_msb, _mem_npc_T_1}; // @[RocketCore.scala:1294:18, :1295:{8,16}]
wire [39:0] _mem_npc_T_3 = _mem_npc_T_2; // @[RocketCore.scala:619:106, :1295:8]
wire [39:0] _mem_npc_T_4 = _mem_npc_T ? _mem_npc_T_3 : mem_br_target; // @[RocketCore.scala:615:41, :619:{21,36,106}]
wire [39:0] _mem_npc_T_5 = _mem_npc_T_4 & 40'hFFFFFFFFFE; // @[RocketCore.scala:619:{21,129}]
wire [39:0] _mem_npc_T_6 = _mem_npc_T_5; // @[RocketCore.scala:619:129]
wire [39:0] mem_npc = _mem_npc_T_6; // @[RocketCore.scala:619:{129,139}]
wire _mem_wrong_npc_T = mem_npc != ex_reg_pc; // @[RocketCore.scala:256:22, :619:139, :621:30]
wire _mem_wrong_npc_T_1 = _ibuf_io_inst_0_valid | io_imem_resp_valid_0; // @[RocketCore.scala:153:7, :311:20, :622:31]
wire _mem_wrong_npc_T_2 = mem_npc != _ibuf_io_pc; // @[RocketCore.scala:311:20, :619:139, :622:62]
wire _mem_wrong_npc_T_3 = ~_mem_wrong_npc_T_1 | _mem_wrong_npc_T_2; // @[RocketCore.scala:622:{8,31,62}]
assign mem_wrong_npc = ex_pc_valid ? _mem_wrong_npc_T : _mem_wrong_npc_T_3; // @[RocketCore.scala:595:51, :621:{8,30}, :622:8]
assign io_imem_bht_update_bits_mispredict_0 = mem_wrong_npc; // @[RocketCore.scala:153:7, :621:8]
wire _mem_npc_misaligned_T_1 = ~_mem_npc_misaligned_T; // @[RocketCore.scala:623:{28,46}]
wire _mem_npc_misaligned_T_2 = mem_npc[1]; // @[RocketCore.scala:619:139, :623:66]
wire _mem_npc_misaligned_T_3 = _mem_npc_misaligned_T_1 & _mem_npc_misaligned_T_2; // @[RocketCore.scala:623:{28,56,66}]
wire _mem_npc_misaligned_T_4 = ~mem_reg_sfence; // @[RocketCore.scala:276:27, :623:73]
wire mem_npc_misaligned = _mem_npc_misaligned_T_3 & _mem_npc_misaligned_T_4; // @[RocketCore.scala:623:{56,70,73}]
wire _mem_int_wdata_T = ~mem_reg_xcpt; // @[RocketCore.scala:268:36, :624:27]
wire _mem_int_wdata_T_1 = mem_ctrl_jalr ^ mem_npc_misaligned; // @[RocketCore.scala:244:21, :623:70, :624:59]
wire _mem_int_wdata_T_2 = _mem_int_wdata_T & _mem_int_wdata_T_1; // @[RocketCore.scala:624:{27,41,59}]
wire [63:0] _mem_int_wdata_T_4 = _mem_int_wdata_T_2 ? {{24{mem_br_target[39]}}, mem_br_target} : _mem_int_wdata_T_3; // @[RocketCore.scala:615:41, :624:{26,41,111}]
wire [63:0] mem_int_wdata = _mem_int_wdata_T_4; // @[RocketCore.scala:624:{26,119}]
wire _mem_cfi_T = mem_ctrl_branch | mem_ctrl_jalr; // @[RocketCore.scala:244:21, :625:33]
assign mem_cfi = _mem_cfi_T | mem_ctrl_jal; // @[RocketCore.scala:244:21, :625:{33,50}]
assign io_imem_btb_update_bits_isValid_0 = mem_cfi; // @[RocketCore.scala:153:7, :625:50]
wire _mem_cfi_taken_T_1 = _mem_cfi_taken_T | mem_ctrl_jalr; // @[RocketCore.scala:244:21, :626:{40,57}]
wire mem_cfi_taken = _mem_cfi_taken_T_1 | mem_ctrl_jal; // @[RocketCore.scala:244:21, :626:{57,74}]
wire _mem_direction_misprediction_T_1 = mem_br_taken != _mem_direction_misprediction_T; // @[RocketCore.scala:284:25, :627:{69,85}]
wire mem_direction_misprediction = mem_ctrl_branch & _mem_direction_misprediction_T_1; // @[RocketCore.scala:244:21, :627:{53,69}]
wire _take_pc_mem_T = ~mem_reg_xcpt; // @[RocketCore.scala:268:36, :624:27, :629:35]
wire _take_pc_mem_T_1 = mem_reg_valid & _take_pc_mem_T; // @[RocketCore.scala:265:36, :629:{32,35}]
wire _take_pc_mem_T_2 = mem_wrong_npc | mem_reg_sfence; // @[RocketCore.scala:276:27, :621:8, :629:71]
assign _take_pc_mem_T_3 = _take_pc_mem_T_1 & _take_pc_mem_T_2; // @[RocketCore.scala:629:{32,49,71}]
assign take_pc_mem = _take_pc_mem_T_3; // @[RocketCore.scala:285:25, :629:49]
wire _mem_reg_valid_T = ~ctrl_killx; // @[RocketCore.scala:602:48, :631:20]
wire _mem_reg_replay_T = ~take_pc_mem_wb; // @[RocketCore.scala:307:35, :526:20, :632:21]
wire _mem_reg_replay_T_1 = _mem_reg_replay_T & replay_ex; // @[RocketCore.scala:601:33, :632:{21,37}]
wire _mem_reg_xcpt_T = ~ctrl_killx; // @[RocketCore.scala:602:48, :631:20, :633:19]
wire _mem_reg_xcpt_T_1 = _mem_reg_xcpt_T & ex_xcpt; // @[RocketCore.scala:633:{19,31}, :1278:14]
wire _mem_reg_xcpt_interrupt_T = ~take_pc_mem_wb; // @[RocketCore.scala:307:35, :526:20, :634:29]
wire _mem_reg_xcpt_interrupt_T_1 = _mem_reg_xcpt_interrupt_T & ex_reg_xcpt_interrupt; // @[RocketCore.scala:247:35, :634:{29,45}]
wire _GEN_49 = ex_ctrl_mem_cmd == 5'h0; // @[package.scala:16:47]
wire _mem_reg_load_T; // @[package.scala:16:47]
assign _mem_reg_load_T = _GEN_49; // @[package.scala:16:47]
wire _io_dmem_req_bits_no_resp_T; // @[package.scala:16:47]
assign _io_dmem_req_bits_no_resp_T = _GEN_49; // @[package.scala:16:47]
wire _GEN_50 = ex_ctrl_mem_cmd == 5'h10; // @[package.scala:16:47]
wire _mem_reg_load_T_1; // @[package.scala:16:47]
assign _mem_reg_load_T_1 = _GEN_50; // @[package.scala:16:47]
wire _io_dmem_req_bits_no_resp_T_1; // @[package.scala:16:47]
assign _io_dmem_req_bits_no_resp_T_1 = _GEN_50; // @[package.scala:16:47]
wire _GEN_51 = ex_ctrl_mem_cmd == 5'h6; // @[package.scala:16:47]
wire _mem_reg_load_T_2; // @[package.scala:16:47]
assign _mem_reg_load_T_2 = _GEN_51; // @[package.scala:16:47]
wire _io_dmem_req_bits_no_resp_T_2; // @[package.scala:16:47]
assign _io_dmem_req_bits_no_resp_T_2 = _GEN_51; // @[package.scala:16:47]
wire _mem_reg_load_T_4 = _mem_reg_load_T | _mem_reg_load_T_1; // @[package.scala:16:47, :81:59]
wire _mem_reg_load_T_5 = _mem_reg_load_T_4 | _mem_reg_load_T_2; // @[package.scala:16:47, :81:59]
wire _mem_reg_load_T_6 = _mem_reg_load_T_5 | _mem_reg_load_T_3; // @[package.scala:16:47, :81:59]
wire _GEN_52 = ex_ctrl_mem_cmd == 5'h4; // @[package.scala:16:47]
wire _mem_reg_load_T_7; // @[package.scala:16:47]
assign _mem_reg_load_T_7 = _GEN_52; // @[package.scala:16:47]
wire _mem_reg_store_T_5; // @[package.scala:16:47]
assign _mem_reg_store_T_5 = _GEN_52; // @[package.scala:16:47]
wire _io_dmem_req_bits_no_resp_T_7; // @[package.scala:16:47]
assign _io_dmem_req_bits_no_resp_T_7 = _GEN_52; // @[package.scala:16:47]
wire _GEN_53 = ex_ctrl_mem_cmd == 5'h9; // @[package.scala:16:47]
wire _mem_reg_load_T_8; // @[package.scala:16:47]
assign _mem_reg_load_T_8 = _GEN_53; // @[package.scala:16:47]
wire _mem_reg_store_T_6; // @[package.scala:16:47]
assign _mem_reg_store_T_6 = _GEN_53; // @[package.scala:16:47]
wire _io_dmem_req_bits_no_resp_T_8; // @[package.scala:16:47]
assign _io_dmem_req_bits_no_resp_T_8 = _GEN_53; // @[package.scala:16:47]
wire _GEN_54 = ex_ctrl_mem_cmd == 5'hA; // @[package.scala:16:47]
wire _mem_reg_load_T_9; // @[package.scala:16:47]
assign _mem_reg_load_T_9 = _GEN_54; // @[package.scala:16:47]
wire _mem_reg_store_T_7; // @[package.scala:16:47]
assign _mem_reg_store_T_7 = _GEN_54; // @[package.scala:16:47]
wire _io_dmem_req_bits_no_resp_T_9; // @[package.scala:16:47]
assign _io_dmem_req_bits_no_resp_T_9 = _GEN_54; // @[package.scala:16:47]
wire _GEN_55 = ex_ctrl_mem_cmd == 5'hB; // @[package.scala:16:47]
wire _mem_reg_load_T_10; // @[package.scala:16:47]
assign _mem_reg_load_T_10 = _GEN_55; // @[package.scala:16:47]
wire _mem_reg_store_T_8; // @[package.scala:16:47]
assign _mem_reg_store_T_8 = _GEN_55; // @[package.scala:16:47]
wire _io_dmem_req_bits_no_resp_T_10; // @[package.scala:16:47]
assign _io_dmem_req_bits_no_resp_T_10 = _GEN_55; // @[package.scala:16:47]
wire _mem_reg_load_T_11 = _mem_reg_load_T_7 | _mem_reg_load_T_8; // @[package.scala:16:47, :81:59]
wire _mem_reg_load_T_12 = _mem_reg_load_T_11 | _mem_reg_load_T_9; // @[package.scala:16:47, :81:59]
wire _mem_reg_load_T_13 = _mem_reg_load_T_12 | _mem_reg_load_T_10; // @[package.scala:16:47, :81:59]
wire _GEN_56 = ex_ctrl_mem_cmd == 5'h8; // @[package.scala:16:47]
wire _mem_reg_load_T_14; // @[package.scala:16:47]
assign _mem_reg_load_T_14 = _GEN_56; // @[package.scala:16:47]
wire _mem_reg_store_T_12; // @[package.scala:16:47]
assign _mem_reg_store_T_12 = _GEN_56; // @[package.scala:16:47]
wire _io_dmem_req_bits_no_resp_T_14; // @[package.scala:16:47]
assign _io_dmem_req_bits_no_resp_T_14 = _GEN_56; // @[package.scala:16:47]
wire _GEN_57 = ex_ctrl_mem_cmd == 5'hC; // @[package.scala:16:47]
wire _mem_reg_load_T_15; // @[package.scala:16:47]
assign _mem_reg_load_T_15 = _GEN_57; // @[package.scala:16:47]
wire _mem_reg_store_T_13; // @[package.scala:16:47]
assign _mem_reg_store_T_13 = _GEN_57; // @[package.scala:16:47]
wire _io_dmem_req_bits_no_resp_T_15; // @[package.scala:16:47]
assign _io_dmem_req_bits_no_resp_T_15 = _GEN_57; // @[package.scala:16:47]
wire _GEN_58 = ex_ctrl_mem_cmd == 5'hD; // @[package.scala:16:47]
wire _mem_reg_load_T_16; // @[package.scala:16:47]
assign _mem_reg_load_T_16 = _GEN_58; // @[package.scala:16:47]
wire _mem_reg_store_T_14; // @[package.scala:16:47]
assign _mem_reg_store_T_14 = _GEN_58; // @[package.scala:16:47]
wire _io_dmem_req_bits_no_resp_T_16; // @[package.scala:16:47]
assign _io_dmem_req_bits_no_resp_T_16 = _GEN_58; // @[package.scala:16:47]
wire _GEN_59 = ex_ctrl_mem_cmd == 5'hE; // @[package.scala:16:47]
wire _mem_reg_load_T_17; // @[package.scala:16:47]
assign _mem_reg_load_T_17 = _GEN_59; // @[package.scala:16:47]
wire _mem_reg_store_T_15; // @[package.scala:16:47]
assign _mem_reg_store_T_15 = _GEN_59; // @[package.scala:16:47]
wire _io_dmem_req_bits_no_resp_T_17; // @[package.scala:16:47]
assign _io_dmem_req_bits_no_resp_T_17 = _GEN_59; // @[package.scala:16:47]
wire _GEN_60 = ex_ctrl_mem_cmd == 5'hF; // @[package.scala:16:47]
wire _mem_reg_load_T_18; // @[package.scala:16:47]
assign _mem_reg_load_T_18 = _GEN_60; // @[package.scala:16:47]
wire _mem_reg_store_T_16; // @[package.scala:16:47]
assign _mem_reg_store_T_16 = _GEN_60; // @[package.scala:16:47]
wire _io_dmem_req_bits_no_resp_T_18; // @[package.scala:16:47]
assign _io_dmem_req_bits_no_resp_T_18 = _GEN_60; // @[package.scala:16:47]
wire _mem_reg_load_T_19 = _mem_reg_load_T_14 | _mem_reg_load_T_15; // @[package.scala:16:47, :81:59]
wire _mem_reg_load_T_20 = _mem_reg_load_T_19 | _mem_reg_load_T_16; // @[package.scala:16:47, :81:59]
wire _mem_reg_load_T_21 = _mem_reg_load_T_20 | _mem_reg_load_T_17; // @[package.scala:16:47, :81:59]
wire _mem_reg_load_T_22 = _mem_reg_load_T_21 | _mem_reg_load_T_18; // @[package.scala:16:47, :81:59]
wire _mem_reg_load_T_23 = _mem_reg_load_T_13 | _mem_reg_load_T_22; // @[package.scala:81:59]
wire _mem_reg_load_T_24 = _mem_reg_load_T_6 | _mem_reg_load_T_23; // @[package.scala:81:59]
wire _mem_reg_load_T_25 = ex_ctrl_mem & _mem_reg_load_T_24; // @[RocketCore.scala:243:20, :643:33]
wire _mem_reg_store_T = ex_ctrl_mem_cmd == 5'h1; // @[RocketCore.scala:243:20]
wire _mem_reg_store_T_1 = ex_ctrl_mem_cmd == 5'h11; // @[RocketCore.scala:243:20]
wire _mem_reg_store_T_2 = _mem_reg_store_T | _mem_reg_store_T_1; // @[Consts.scala:90:{32,42,49}]
wire _mem_reg_store_T_4 = _mem_reg_store_T_2 | _mem_reg_store_T_3; // @[Consts.scala:90:{42,59,66}]
wire _mem_reg_store_T_9 = _mem_reg_store_T_5 | _mem_reg_store_T_6; // @[package.scala:16:47, :81:59]
wire _mem_reg_store_T_10 = _mem_reg_store_T_9 | _mem_reg_store_T_7; // @[package.scala:16:47, :81:59]
wire _mem_reg_store_T_11 = _mem_reg_store_T_10 | _mem_reg_store_T_8; // @[package.scala:16:47, :81:59]
wire _mem_reg_store_T_17 = _mem_reg_store_T_12 | _mem_reg_store_T_13; // @[package.scala:16:47, :81:59]
wire _mem_reg_store_T_18 = _mem_reg_store_T_17 | _mem_reg_store_T_14; // @[package.scala:16:47, :81:59]
wire _mem_reg_store_T_19 = _mem_reg_store_T_18 | _mem_reg_store_T_15; // @[package.scala:16:47, :81:59]
wire _mem_reg_store_T_20 = _mem_reg_store_T_19 | _mem_reg_store_T_16; // @[package.scala:16:47, :81:59]
wire _mem_reg_store_T_21 = _mem_reg_store_T_11 | _mem_reg_store_T_20; // @[package.scala:81:59]
wire _mem_reg_store_T_22 = _mem_reg_store_T_4 | _mem_reg_store_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _mem_reg_store_T_23 = ex_ctrl_mem & _mem_reg_store_T_22; // @[RocketCore.scala:243:20, :644:34]
wire [1:0] size = ex_ctrl_rocc ? 2'h3 : ex_reg_mem_size; // @[RocketCore.scala:243:20, :257:28, :664:21]
wire [1:0] mem_reg_rs2_size = size; // @[RocketCore.scala:664:21]
wire _mem_reg_rs2_T = mem_reg_rs2_size == 2'h0; // @[AMOALU.scala:11:18, :29:19]
wire [7:0] _mem_reg_rs2_T_1 = mem_reg_rs2_dat_padded[7:0]; // @[AMOALU.scala:13:27, :29:69]
wire [15:0] _mem_reg_rs2_T_2 = {2{_mem_reg_rs2_T_1}}; // @[AMOALU.scala:29:{32,69}]
wire [31:0] _mem_reg_rs2_T_3 = {2{_mem_reg_rs2_T_2}}; // @[AMOALU.scala:29:32]
wire [63:0] _mem_reg_rs2_T_4 = {2{_mem_reg_rs2_T_3}}; // @[AMOALU.scala:29:32]
wire _mem_reg_rs2_T_5 = mem_reg_rs2_size == 2'h1; // @[AMOALU.scala:11:18, :29:19]
wire [15:0] _mem_reg_rs2_T_6 = mem_reg_rs2_dat_padded[15:0]; // @[AMOALU.scala:13:27, :29:69]
wire [31:0] _mem_reg_rs2_T_7 = {2{_mem_reg_rs2_T_6}}; // @[AMOALU.scala:29:{32,69}]
wire [63:0] _mem_reg_rs2_T_8 = {2{_mem_reg_rs2_T_7}}; // @[AMOALU.scala:29:32]
wire _mem_reg_rs2_T_9 = mem_reg_rs2_size == 2'h2; // @[AMOALU.scala:11:18, :29:19]
wire [31:0] _mem_reg_rs2_T_10 = mem_reg_rs2_dat_padded[31:0]; // @[AMOALU.scala:13:27, :29:69]
wire [63:0] _mem_reg_rs2_T_11 = {2{_mem_reg_rs2_T_10}}; // @[AMOALU.scala:29:{32,69}]
wire [63:0] _mem_reg_rs2_T_12 = _mem_reg_rs2_T_9 ? _mem_reg_rs2_T_11 : mem_reg_rs2_dat_padded; // @[AMOALU.scala:13:27, :29:{13,19,32}]
wire [63:0] _mem_reg_rs2_T_13 = _mem_reg_rs2_T_5 ? _mem_reg_rs2_T_8 : _mem_reg_rs2_T_12; // @[AMOALU.scala:29:{13,19,32}]
wire [63:0] _mem_reg_rs2_T_14 = _mem_reg_rs2_T ? _mem_reg_rs2_T_4 : _mem_reg_rs2_T_13; // @[AMOALU.scala:29:{13,19,32}]
wire _mem_breakpoint_T = mem_reg_load & _bpu_io_xcpt_ld; // @[RocketCore.scala:273:36, :414:19, :677:38]
wire _mem_breakpoint_T_1 = mem_reg_store & _bpu_io_xcpt_st; // @[RocketCore.scala:274:36, :414:19, :677:75]
wire mem_breakpoint = _mem_breakpoint_T | _mem_breakpoint_T_1; // @[RocketCore.scala:677:{38,57,75}]
wire _mem_debug_breakpoint_T = mem_reg_load & _bpu_io_debug_ld; // @[RocketCore.scala:273:36, :414:19, :678:44]
wire _mem_debug_breakpoint_T_1 = mem_reg_store & _bpu_io_debug_st; // @[RocketCore.scala:274:36, :414:19, :678:82]
wire mem_debug_breakpoint = _mem_debug_breakpoint_T | _mem_debug_breakpoint_T_1; // @[RocketCore.scala:678:{44,64,82}]
wire mem_ldst_xcpt = mem_debug_breakpoint | mem_breakpoint; // @[RocketCore.scala:677:57, :678:64, :1278:{14,35}]
wire [3:0] mem_ldst_cause = mem_debug_breakpoint ? 4'hE : 4'h3; // @[Mux.scala:50:70]
wire _T_74 = mem_reg_xcpt_interrupt | mem_reg_xcpt; // @[RocketCore.scala:264:36, :268:36, :684:29]
wire _T_75 = mem_reg_valid & mem_npc_misaligned; // @[RocketCore.scala:265:36, :623:70, :685:20]
wire mem_xcpt = _T_74 | _T_75 | mem_reg_valid & mem_ldst_xcpt; // @[RocketCore.scala:265:36, :684:29, :685:20, :686:20, :1278:{14,35}]
wire [63:0] mem_cause = _T_74 ? mem_reg_cause : {60'h0, _T_75 ? 4'h0 : mem_ldst_cause}; // @[Mux.scala:50:70]
wire dcache_kill_mem = _dcache_kill_mem_T & io_dmem_replay_next_0; // @[RocketCore.scala:153:7, :695:{39,55}]
wire _fpu_kill_mem_T = mem_reg_valid & mem_ctrl_fp; // @[RocketCore.scala:244:21, :265:36, :696:36]
wire fpu_kill_mem = _fpu_kill_mem_T & io_fpu_nack_mem_0; // @[RocketCore.scala:153:7, :696:{36,51}]
wire _vec_kill_mem_T = mem_reg_valid & mem_ctrl_mem; // @[RocketCore.scala:244:21, :265:36, :697:36]
wire _replay_mem_T = dcache_kill_mem | mem_reg_replay; // @[RocketCore.scala:269:36, :695:55, :699:37]
wire _replay_mem_T_1 = _replay_mem_T | fpu_kill_mem; // @[RocketCore.scala:696:51, :699:{37,55}]
wire _replay_mem_T_2 = _replay_mem_T_1; // @[RocketCore.scala:699:{55,71}]
wire replay_mem = _replay_mem_T_2; // @[RocketCore.scala:699:{71,87}]
wire _killm_common_T = dcache_kill_mem | take_pc_wb; // @[RocketCore.scala:304:24, :695:55, :700:38]
wire _killm_common_T_1 = _killm_common_T | mem_reg_xcpt; // @[RocketCore.scala:268:36, :700:{38,52}]
wire _killm_common_T_2 = ~mem_reg_valid; // @[RocketCore.scala:265:36, :700:71]
assign killm_common = _killm_common_T_1 | _killm_common_T_2; // @[RocketCore.scala:700:{52,68,71}]
assign io_fpu_killm_0 = killm_common; // @[RocketCore.scala:153:7, :700:68]
wire _div_io_kill_T = _div_io_req_ready & _div_io_req_valid_T; // @[Decoupled.scala:51:35]
reg div_io_kill_REG; // @[RocketCore.scala:701:41]
wire _div_io_kill_T_1 = killm_common & div_io_kill_REG; // @[RocketCore.scala:700:68, :701:{31,41}]
wire _ctrl_killm_T = killm_common | mem_xcpt; // @[RocketCore.scala:700:68, :702:33, :1278:14]
wire _ctrl_killm_T_1 = _ctrl_killm_T | fpu_kill_mem; // @[RocketCore.scala:696:51, :702:{33,45}]
wire ctrl_killm = _ctrl_killm_T_1; // @[RocketCore.scala:702:{45,61}]
wire _wb_reg_valid_T = ~ctrl_killm; // @[RocketCore.scala:702:61, :705:19]
wire _wb_reg_replay_T = ~take_pc_wb; // @[RocketCore.scala:304:24, :706:34]
wire _wb_reg_replay_T_1 = replay_mem & _wb_reg_replay_T; // @[RocketCore.scala:699:87, :706:{31,34}]
wire _wb_reg_xcpt_T = ~take_pc_wb; // @[RocketCore.scala:304:24, :706:34, :707:30]
wire _wb_reg_xcpt_T_1 = mem_xcpt & _wb_reg_xcpt_T; // @[RocketCore.scala:707:{27,30}, :1278:14]
wire _wb_reg_xcpt_T_3 = _wb_reg_xcpt_T_1; // @[RocketCore.scala:707:{27,42}]
wire _wb_reg_flush_pipe_T = ~ctrl_killm; // @[RocketCore.scala:702:61, :705:19, :708:24]
wire _wb_reg_flush_pipe_T_1 = _wb_reg_flush_pipe_T & mem_reg_flush_pipe; // @[RocketCore.scala:270:36, :708:{24,36}]
wire _wb_reg_wdata_T = ~mem_reg_xcpt; // @[RocketCore.scala:268:36, :624:27, :712:25]
wire _wb_reg_wdata_T_1 = _wb_reg_wdata_T & mem_ctrl_fp; // @[RocketCore.scala:244:21, :712:{25,39}]
wire _wb_reg_wdata_T_2 = _wb_reg_wdata_T_1 & mem_ctrl_wxd; // @[RocketCore.scala:244:21, :712:{39,54}]
wire [63:0] _wb_reg_wdata_T_3 = _wb_reg_wdata_T_2 ? io_fpu_toint_data_0 : mem_int_wdata; // @[RocketCore.scala:153:7, :624:119, :712:{24,54}]
wire _wb_reg_hfence_v_T = mem_ctrl_mem_cmd == 5'h15; // @[RocketCore.scala:244:21, :721:41]
wire _wb_reg_hfence_g_T = mem_ctrl_mem_cmd == 5'h16; // @[RocketCore.scala:244:21, :722:41]
wire _T_113 = wb_reg_valid & wb_ctrl_mem; // @[RocketCore.scala:245:20, :288:35, :730:19]
wire _T_100 = _T_113 & io_dmem_s2_xcpt_pf_st_0; // @[RocketCore.scala:153:7, :730:{19,34}]
wire _T_102 = _T_113 & io_dmem_s2_xcpt_pf_ld_0; // @[RocketCore.scala:153:7, :730:19, :731:34]
wire _T_108 = _T_113 & io_dmem_s2_xcpt_ae_st_0; // @[RocketCore.scala:153:7, :730:19, :734:34]
wire _T_110 = _T_113 & io_dmem_s2_xcpt_ae_ld_0; // @[RocketCore.scala:153:7, :730:19, :735:34]
wire _T_112 = _T_113 & io_dmem_s2_xcpt_ma_st_0; // @[RocketCore.scala:153:7, :730:19, :736:34]
wire wb_xcpt = wb_reg_xcpt | _T_100 | _T_102 | _T_108 | _T_110 | _T_112 | _T_113 & io_dmem_s2_xcpt_ma_ld_0; // @[RocketCore.scala:153:7, :289:35, :730:{19,34}, :731:34, :734:34, :735:34, :736:34, :737:34, :1278:{14,35}]
wire [63:0] wb_cause = wb_reg_xcpt ? wb_reg_cause : {59'h0, _T_100 ? 5'hF : _T_102 ? 5'hD : {2'h0, _T_108 ? 3'h7 : _T_110 ? 3'h5 : {1'h1, _T_112, 1'h0}}}; // @[Mux.scala:50:70]
wire _wb_pc_valid_T = wb_reg_valid | wb_reg_replay; // @[RocketCore.scala:288:35, :290:35, :754:34]
wire wb_pc_valid = _wb_pc_valid_T | wb_reg_xcpt; // @[RocketCore.scala:289:35, :754:{34,51}]
wire wb_wxd = wb_reg_valid & wb_ctrl_wxd; // @[RocketCore.scala:245:20, :288:35, :755:29]
wire _wb_set_sboard_T = wb_ctrl_div | wb_dcache_miss; // @[RocketCore.scala:245:20, :596:36, :756:35]
wire _wb_set_sboard_T_1 = _wb_set_sboard_T | wb_ctrl_rocc; // @[RocketCore.scala:245:20, :756:{35,53}]
wire wb_set_sboard = _wb_set_sboard_T_1 | wb_ctrl_vec; // @[RocketCore.scala:245:20, :756:{53,69}]
wire replay_wb_common = io_dmem_s2_nack_0 | wb_reg_replay; // @[RocketCore.scala:153:7, :290:35, :757:42]
wire replay_wb_rocc = _replay_wb_rocc_T; // @[RocketCore.scala:758:{37,53}]
wire _replay_wb_T = replay_wb_common | replay_wb_rocc; // @[RocketCore.scala:757:42, :758:53, :761:36]
wire _replay_wb_T_1 = _replay_wb_T; // @[RocketCore.scala:761:{36,54}]
wire replay_wb = _replay_wb_T_1; // @[RocketCore.scala:761:{54,71}]
wire _take_pc_wb_T = replay_wb | wb_xcpt; // @[RocketCore.scala:761:71, :762:27, :1278:14]
wire _take_pc_wb_T_1 = _take_pc_wb_T | _csr_io_eret; // @[RocketCore.scala:341:19, :762:{27,38}]
assign _take_pc_wb_T_2 = _take_pc_wb_T_1 | wb_reg_flush_pipe; // @[RocketCore.scala:291:35, :762:{38,53}]
assign take_pc_wb = _take_pc_wb_T_2; // @[RocketCore.scala:304:24, :762:53]
wire _dmem_resp_xpu_T = io_dmem_resp_bits_tag_0[0]; // @[RocketCore.scala:153:7, :765:45]
wire dmem_resp_fpu = io_dmem_resp_bits_tag_0[0]; // @[RocketCore.scala:153:7, :765:45, :766:45]
wire dmem_resp_xpu = ~_dmem_resp_xpu_T; // @[RocketCore.scala:765:{23,45}]
assign dmem_resp_waddr = io_dmem_resp_bits_tag_0[5:1]; // @[RocketCore.scala:153:7, :767:46]
assign io_fpu_ll_resp_tag_0 = dmem_resp_waddr; // @[RocketCore.scala:153:7, :767:46]
wire dmem_resp_valid = io_dmem_resp_valid_0 & io_dmem_resp_bits_has_data_0; // @[RocketCore.scala:153:7, :768:44]
wire dmem_resp_replay = dmem_resp_valid & io_dmem_resp_bits_replay_0; // @[RocketCore.scala:153:7, :768:44, :769:42]
wire [63:0] ll_wdata; // @[RocketCore.scala:779:26]
wire [4:0] ll_waddr; // @[RocketCore.scala:780:26]
wire _ll_wen_T = ll_arb_io_out_ready & _ll_arb_io_out_valid; // @[Decoupled.scala:51:35]
wire ll_wen; // @[RocketCore.scala:781:24]
wire _ll_arb_io_out_ready_T = ~wb_wxd; // @[RocketCore.scala:755:29, :782:26]
wire _T_143 = dmem_resp_replay & dmem_resp_xpu; // @[RocketCore.scala:765:23, :769:42, :809:26]
assign ll_arb_io_out_ready = ~_T_143 & _ll_arb_io_out_ready_T; // @[RocketCore.scala:782:{23,26}, :809:{26,44}, :810:25]
assign ll_waddr = _T_143 ? dmem_resp_waddr : _ll_arb_io_out_bits_tag; // @[RocketCore.scala:767:46, :776:22, :780:26, :809:{26,44}, :811:14]
assign ll_wen = _T_143 | _ll_wen_T; // @[Decoupled.scala:51:35]
wire _wb_valid_T = ~replay_wb; // @[RocketCore.scala:761:71, :815:34]
wire _wb_valid_T_1 = wb_reg_valid & _wb_valid_T; // @[RocketCore.scala:288:35, :815:{31,34}]
wire _wb_valid_T_2 = ~wb_xcpt; // @[RocketCore.scala:815:48, :1278:14]
wire wb_valid = _wb_valid_T_1 & _wb_valid_T_2; // @[RocketCore.scala:815:{31,45,48}]
wire wb_wen = wb_valid & wb_ctrl_wxd; // @[RocketCore.scala:245:20, :815:45, :816:25]
wire rf_wen = wb_wen | ll_wen; // @[RocketCore.scala:781:24, :816:25, :817:23]
wire [4:0] rf_waddr = ll_wen ? ll_waddr : wb_waddr; // @[RocketCore.scala:455:36, :780:26, :781:24, :818:21]
wire [4:0] xrfWriteBundle_wrdst = rf_waddr; // @[RocketCore.scala:818:21, :1249:28]
wire _rf_wdata_T = dmem_resp_valid & dmem_resp_xpu; // @[RocketCore.scala:765:23, :768:44, :819:38]
wire _rf_wdata_T_2 = |wb_ctrl_csr; // @[RocketCore.scala:245:20, :821:34]
wire [63:0] _rf_wdata_T_4 = _rf_wdata_T_2 ? _csr_io_rw_rdata : _rf_wdata_T_3; // @[RocketCore.scala:341:19, :821:{21,34}, :822:21]
wire [63:0] _rf_wdata_T_5 = ll_wen ? ll_wdata : _rf_wdata_T_4; // @[RocketCore.scala:779:26, :781:24, :820:21, :821:21]
wire [63:0] rf_wdata = _rf_wdata_T ? _rf_wdata_T_1 : _rf_wdata_T_5; // @[RocketCore.scala:819:{21,38,78}, :820:21]
wire [63:0] coreMonitorBundle_wrdata = rf_wdata; // @[RocketCore.scala:819:21, :1186:31]
wire [63:0] xrfWriteBundle_wrdata = rf_wdata; // @[RocketCore.scala:819:21, :1249:28]
wire [63:0] _id_rs_T_4; // @[RocketCore.scala:1326:25]
assign id_rs_0 = rf_wen & (|rf_waddr) & rf_waddr == id_raddr1 ? rf_wdata : _id_rs_T_4; // @[RocketCore.scala:326:72, :817:23, :818:21, :819:21, :824:17, :1325:26, :1326:{19,25}, :1331:{16,25}, :1334:{20,31,39}]
wire [63:0] _id_rs_T_9; // @[RocketCore.scala:1326:25]
assign id_rs_1 = rf_wen & (|rf_waddr) & rf_waddr == id_raddr2 ? rf_wdata : _id_rs_T_9; // @[RocketCore.scala:326:72, :817:23, :818:21, :819:21, :824:17, :1325:26, :1326:{19,25}, :1331:{16,25}, :1334:{20,31,39}]
wire [1:0] _csr_io_inst_0_T = wb_reg_raw_inst[1:0]; // @[RocketCore.scala:301:28, :832:66]
wire _csr_io_inst_0_T_1 = &_csr_io_inst_0_T; // @[RocketCore.scala:832:{66,73}]
wire [15:0] _csr_io_inst_0_T_2 = wb_reg_inst[31:16]; // @[RocketCore.scala:300:24, :832:91]
wire [15:0] _csr_io_inst_0_T_3 = _csr_io_inst_0_T_1 ? _csr_io_inst_0_T_2 : 16'h0; // @[RocketCore.scala:832:{50,73,91}]
wire [15:0] _csr_io_inst_0_T_4 = wb_reg_raw_inst[15:0]; // @[RocketCore.scala:301:28, :832:119]
wire [31:0] _csr_io_inst_0_T_5 = {_csr_io_inst_0_T_3, _csr_io_inst_0_T_4}; // @[RocketCore.scala:832:{46,50,119}]
wire [4:0] _csr_io_fcsr_flags_bits_T = {5{io_fpu_fcsr_flags_valid_0}}; // @[RocketCore.scala:153:7, :839:59]
wire [4:0] _csr_io_fcsr_flags_bits_T_1 = io_fpu_fcsr_flags_bits_0 & _csr_io_fcsr_flags_bits_T; // @[RocketCore.scala:153:7, :839:{53,59}]
wire [4:0] _csr_io_fcsr_flags_bits_T_4 = _csr_io_fcsr_flags_bits_T_1; // @[RocketCore.scala:839:{53,89}]
wire [31:0] _io_fpu_time_T = _csr_io_time[31:0]; // @[RocketCore.scala:341:19, :840:29]
wire [31:0] _coreMonitorBundle_timer_T = _csr_io_time[31:0]; // @[RocketCore.scala:341:19, :840:29, :1191:41]
wire [31:0] _xrfWriteBundle_timer_T = _csr_io_time[31:0]; // @[RocketCore.scala:341:19, :840:29, :1254:38]
assign io_fpu_time_0 = {32'h0, _io_fpu_time_T}; // @[RocketCore.scala:153:7, :840:{15,29}]
wire tval_dmem_addr = ~wb_reg_xcpt; // @[RocketCore.scala:289:35, :845:24]
wire _tval_any_addr_T = wb_reg_cause == 64'h3; // @[package.scala:16:47]
wire _tval_any_addr_T_1 = wb_reg_cause == 64'h1; // @[package.scala:16:47]
wire _tval_any_addr_T_2 = wb_reg_cause == 64'hC; // @[package.scala:16:47]
wire _GEN_61 = wb_reg_cause == 64'h14; // @[package.scala:16:47]
wire _tval_any_addr_T_3; // @[package.scala:16:47]
assign _tval_any_addr_T_3 = _GEN_61; // @[package.scala:16:47]
wire _htval_valid_imem_T; // @[RocketCore.scala:853:56]
assign _htval_valid_imem_T = _GEN_61; // @[package.scala:16:47]
wire _tval_any_addr_T_4 = _tval_any_addr_T | _tval_any_addr_T_1; // @[package.scala:16:47, :81:59]
wire _tval_any_addr_T_5 = _tval_any_addr_T_4 | _tval_any_addr_T_2; // @[package.scala:16:47, :81:59]
wire _tval_any_addr_T_6 = _tval_any_addr_T_5 | _tval_any_addr_T_3; // @[package.scala:16:47, :81:59]
wire tval_any_addr = tval_dmem_addr | _tval_any_addr_T_6; // @[package.scala:81:59]
wire tval_inst = wb_reg_cause == 64'h2; // @[RocketCore.scala:292:35, :848:32]
wire _tval_valid_T = tval_any_addr | tval_inst; // @[RocketCore.scala:846:38, :848:32, :849:46]
wire tval_valid = wb_xcpt & _tval_valid_T; // @[RocketCore.scala:849:{28,46}, :1278:14]
wire _csr_io_gva_T = tval_any_addr & _csr_io_status_v; // @[RocketCore.scala:341:19, :846:38, :850:43]
wire _csr_io_gva_T_1 = tval_dmem_addr & wb_reg_hls_or_dv; // @[RocketCore.scala:297:29, :845:24, :850:80]
wire _csr_io_gva_T_2 = _csr_io_gva_T | _csr_io_gva_T_1; // @[RocketCore.scala:850:{43,62,80}]
wire _csr_io_gva_T_3 = wb_xcpt & _csr_io_gva_T_2; // @[RocketCore.scala:850:{25,62}, :1278:14]
wire [24:0] _csr_io_tval_a_T = wb_reg_wdata[63:39]; // @[RocketCore.scala:302:25, :1293:17]
wire [24:0] csr_io_tval_a = _csr_io_tval_a_T; // @[RocketCore.scala:1293:{17,23}]
wire _csr_io_tval_msb_T = csr_io_tval_a == 25'h0; // @[RocketCore.scala:1293:23, :1294:21]
wire _csr_io_tval_msb_T_1 = &csr_io_tval_a; // @[RocketCore.scala:1293:23, :1294:34]
wire _csr_io_tval_msb_T_2 = _csr_io_tval_msb_T | _csr_io_tval_msb_T_1; // @[RocketCore.scala:1294:{21,29,34}]
wire _csr_io_tval_msb_T_3 = wb_reg_wdata[39]; // @[RocketCore.scala:302:25, :1294:46]
wire _csr_io_tval_msb_T_4 = wb_reg_wdata[38]; // @[RocketCore.scala:302:25, :1294:54]
wire _csr_io_tval_msb_T_5 = ~_csr_io_tval_msb_T_4; // @[RocketCore.scala:1294:{51,54}]
wire csr_io_tval_msb = _csr_io_tval_msb_T_2 ? _csr_io_tval_msb_T_3 : _csr_io_tval_msb_T_5; // @[RocketCore.scala:1294:{18,29,46,51}]
assign io_imem_sfence_bits_addr_0 = wb_reg_wdata[38:0]; // @[RocketCore.scala:153:7, :302:25, :1295:16]
wire [38:0] _csr_io_tval_T = wb_reg_wdata[38:0]; // @[RocketCore.scala:302:25, :1295:16]
wire [39:0] _csr_io_tval_T_1 = {csr_io_tval_msb, _csr_io_tval_T}; // @[RocketCore.scala:1294:18, :1295:{8,16}]
wire [39:0] _csr_io_tval_T_2 = tval_valid ? _csr_io_tval_T_1 : 40'h0; // @[RocketCore.scala:849:28, :851:21, :1295:8]
wire htval_valid_imem = wb_reg_xcpt & _htval_valid_imem_T; // @[RocketCore.scala:289:35, :853:{40,56}]
wire [39:0] htval_imem = htval_valid_imem ? io_imem_gpa_bits_0 : 40'h0; // @[RocketCore.scala:153:7, :853:40, :854:25]
wire [39:0] _htval_T = htval_imem; // @[RocketCore.scala:854:25, :860:29]
wire _htval_valid_dmem_T = wb_xcpt & tval_dmem_addr; // @[RocketCore.scala:845:24, :857:36, :1278:14]
wire [1:0] _htval_valid_dmem_T_4 = {io_dmem_s2_xcpt_pf_ld_0, io_dmem_s2_xcpt_pf_st_0}; // @[RocketCore.scala:153:7, :857:110]
wire _htval_valid_dmem_T_5 = |_htval_valid_dmem_T_4; // @[RocketCore.scala:857:{110,117}]
wire _htval_valid_dmem_T_6 = ~_htval_valid_dmem_T_5; // @[RocketCore.scala:857:{90,117}]
wire [39:0] htval = _htval_T; // @[RocketCore.scala:860:{29,43}]
wire _mhtinst_read_pseudo_T = io_imem_gpa_is_pte_0 & htval_valid_imem; // @[RocketCore.scala:153:7, :853:40, :862:51]
wire mhtinst_read_pseudo = _mhtinst_read_pseudo_T; // @[RocketCore.scala:862:{51,72}]
wire [11:0] _csr_io_rw_addr_T = wb_reg_inst[31:20]; // @[RocketCore.scala:300:24, :909:32]
wire [2:0] _csr_io_rw_cmd_T = {~wb_reg_valid, 2'h0}; // @[RocketCore.scala:288:35]
wire [2:0] _csr_io_rw_cmd_T_1 = ~_csr_io_rw_cmd_T; // @[CSR.scala:183:{11,15}]
wire [2:0] _csr_io_rw_cmd_T_2 = wb_ctrl_csr & _csr_io_rw_cmd_T_1; // @[RocketCore.scala:245:20]
assign io_bpwatch_0_action_0 = {2'h0, _csr_io_bp_0_control_action}; // @[RocketCore.scala:153:7, :341:19, :962:18]
wire _hazard_targets_T = |id_raddr1; // @[RocketCore.scala:326:72, :969:55, :1326:41]
wire hazard_targets_0_1 = id_ctrl_rxs1 & _hazard_targets_T; // @[RocketCore.scala:321:21, :969:{42,55}]
wire _hazard_targets_T_1 = |id_raddr2; // @[RocketCore.scala:326:72, :970:55, :1326:41]
wire hazard_targets_1_1 = id_ctrl_rxs2 & _hazard_targets_T_1; // @[RocketCore.scala:321:21, :970:{42,55}]
wire _hazard_targets_T_2 = |id_waddr; // @[RocketCore.scala:326:72, :971:55]
wire hazard_targets_2_1 = id_ctrl_wxd & _hazard_targets_T_2; // @[RocketCore.scala:321:21, :971:{42,55}]
reg [31:0] _r; // @[RocketCore.scala:1305:29]
wire [30:0] _r_T = _r[31:1]; // @[RocketCore.scala:1305:29, :1306:35]
wire [31:0] r = {_r_T, 1'h0}; // @[RocketCore.scala:1306:{35,40}]
wire [31:0] _GEN_62 = {27'h0, id_raddr1}; // @[RocketCore.scala:326:72, :1302:35, :1309:58]
wire [31:0] _id_sboard_hazard_T = r >> _GEN_62; // @[RocketCore.scala:1302:35, :1306:40]
wire _id_sboard_hazard_T_1 = _id_sboard_hazard_T[0]; // @[RocketCore.scala:1302:35]
wire _id_sboard_hazard_T_2 = ll_waddr == id_raddr1; // @[RocketCore.scala:326:72, :780:26, :981:70]
wire _id_sboard_hazard_T_3 = ll_wen & _id_sboard_hazard_T_2; // @[RocketCore.scala:781:24, :981:{58,70}]
wire _id_sboard_hazard_T_4 = ~_id_sboard_hazard_T_3; // @[RocketCore.scala:981:58, :984:80]
wire _id_sboard_hazard_T_5 = _id_sboard_hazard_T_1 & _id_sboard_hazard_T_4; // @[RocketCore.scala:984:{77,80}, :1302:35]
wire _id_sboard_hazard_T_6 = hazard_targets_0_1 & _id_sboard_hazard_T_5; // @[RocketCore.scala:969:42, :984:77, :1287:27]
wire [31:0] _GEN_63 = {27'h0, id_raddr2}; // @[RocketCore.scala:326:72, :1302:35, :1309:58]
wire [31:0] _id_sboard_hazard_T_7 = r >> _GEN_63; // @[RocketCore.scala:1302:35, :1306:40]
wire _id_sboard_hazard_T_8 = _id_sboard_hazard_T_7[0]; // @[RocketCore.scala:1302:35]
wire _id_sboard_hazard_T_9 = ll_waddr == id_raddr2; // @[RocketCore.scala:326:72, :780:26, :981:70]
wire _id_sboard_hazard_T_10 = ll_wen & _id_sboard_hazard_T_9; // @[RocketCore.scala:781:24, :981:{58,70}]
wire _id_sboard_hazard_T_11 = ~_id_sboard_hazard_T_10; // @[RocketCore.scala:981:58, :984:80]
wire _id_sboard_hazard_T_12 = _id_sboard_hazard_T_8 & _id_sboard_hazard_T_11; // @[RocketCore.scala:984:{77,80}, :1302:35]
wire _id_sboard_hazard_T_13 = hazard_targets_1_1 & _id_sboard_hazard_T_12; // @[RocketCore.scala:970:42, :984:77, :1287:27]
wire [31:0] _GEN_64 = {27'h0, id_waddr}; // @[RocketCore.scala:326:72, :1302:35, :1309:58]
wire [31:0] _id_sboard_hazard_T_14 = r >> _GEN_64; // @[RocketCore.scala:1302:35, :1306:40]
wire _id_sboard_hazard_T_15 = _id_sboard_hazard_T_14[0]; // @[RocketCore.scala:1302:35]
wire _id_sboard_hazard_T_16 = ll_waddr == id_waddr; // @[RocketCore.scala:326:72, :780:26, :981:70]
wire _id_sboard_hazard_T_17 = ll_wen & _id_sboard_hazard_T_16; // @[RocketCore.scala:781:24, :981:{58,70}]
wire _id_sboard_hazard_T_18 = ~_id_sboard_hazard_T_17; // @[RocketCore.scala:981:58, :984:80]
wire _id_sboard_hazard_T_19 = _id_sboard_hazard_T_15 & _id_sboard_hazard_T_18; // @[RocketCore.scala:984:{77,80}, :1302:35]
wire _id_sboard_hazard_T_20 = hazard_targets_2_1 & _id_sboard_hazard_T_19; // @[RocketCore.scala:971:42, :984:77, :1287:27]
wire _id_sboard_hazard_T_21 = _id_sboard_hazard_T_6 | _id_sboard_hazard_T_13; // @[RocketCore.scala:1287:{27,50}]
wire id_sboard_hazard = _id_sboard_hazard_T_21 | _id_sboard_hazard_T_20; // @[RocketCore.scala:1287:{27,50}]
wire [31:0] _id_stall_fpu_T_4 = 32'h1 << wb_waddr; // @[RocketCore.scala:455:36, :1309:58]
wire _ex_cannot_bypass_T = |ex_ctrl_csr; // @[RocketCore.scala:243:20, :988:38]
wire _ex_cannot_bypass_T_1 = _ex_cannot_bypass_T | ex_ctrl_jalr; // @[RocketCore.scala:243:20, :988:{38,48}]
wire _ex_cannot_bypass_T_2 = _ex_cannot_bypass_T_1 | ex_ctrl_mem; // @[RocketCore.scala:243:20, :988:{48,64}]
wire _ex_cannot_bypass_T_3 = _ex_cannot_bypass_T_2 | ex_ctrl_mul; // @[RocketCore.scala:243:20, :988:{64,79}]
wire _ex_cannot_bypass_T_4 = _ex_cannot_bypass_T_3 | ex_ctrl_div; // @[RocketCore.scala:243:20, :988:{79,94}]
wire _ex_cannot_bypass_T_5 = _ex_cannot_bypass_T_4 | ex_ctrl_fp; // @[RocketCore.scala:243:20, :988:{94,109}]
wire _ex_cannot_bypass_T_6 = _ex_cannot_bypass_T_5 | ex_ctrl_rocc; // @[RocketCore.scala:243:20, :988:{109,123}]
wire ex_cannot_bypass = _ex_cannot_bypass_T_6; // @[RocketCore.scala:988:{123,139}]
wire _data_hazard_ex_T_1 = hazard_targets_0_1 & _data_hazard_ex_T; // @[RocketCore.scala:969:42, :989:70, :1287:27]
wire _data_hazard_ex_T_3 = hazard_targets_1_1 & _data_hazard_ex_T_2; // @[RocketCore.scala:970:42, :989:70, :1287:27]
wire _GEN_65 = id_waddr == ex_waddr; // @[RocketCore.scala:326:72, :453:36, :989:70]
wire _data_hazard_ex_T_4; // @[RocketCore.scala:989:70]
assign _data_hazard_ex_T_4 = _GEN_65; // @[RocketCore.scala:989:70]
wire _fp_data_hazard_ex_T_7; // @[RocketCore.scala:990:90]
assign _fp_data_hazard_ex_T_7 = _GEN_65; // @[RocketCore.scala:989:70, :990:90]
wire _data_hazard_ex_T_5 = hazard_targets_2_1 & _data_hazard_ex_T_4; // @[RocketCore.scala:971:42, :989:70, :1287:27]
wire _data_hazard_ex_T_6 = _data_hazard_ex_T_1 | _data_hazard_ex_T_3; // @[RocketCore.scala:1287:{27,50}]
wire _data_hazard_ex_T_7 = _data_hazard_ex_T_6 | _data_hazard_ex_T_5; // @[RocketCore.scala:1287:{27,50}]
wire data_hazard_ex = ex_ctrl_wxd & _data_hazard_ex_T_7; // @[RocketCore.scala:243:20, :989:36, :1287:50]
wire _fp_data_hazard_ex_T = id_ctrl_fp & ex_ctrl_wfd; // @[RocketCore.scala:243:20, :321:21, :990:38]
wire _fp_data_hazard_ex_T_2 = io_fpu_dec_ren1_0 & _fp_data_hazard_ex_T_1; // @[RocketCore.scala:153:7, :990:90, :1287:27]
wire _fp_data_hazard_ex_T_4 = io_fpu_dec_ren2_0 & _fp_data_hazard_ex_T_3; // @[RocketCore.scala:153:7, :990:90, :1287:27]
wire _fp_data_hazard_ex_T_5 = id_raddr3 == ex_waddr; // @[RocketCore.scala:326:72, :453:36, :990:90]
wire _fp_data_hazard_ex_T_6 = io_fpu_dec_ren3_0 & _fp_data_hazard_ex_T_5; // @[RocketCore.scala:153:7, :990:90, :1287:27]
wire _fp_data_hazard_ex_T_8 = io_fpu_dec_wen_0 & _fp_data_hazard_ex_T_7; // @[RocketCore.scala:153:7, :990:90, :1287:27]
wire _fp_data_hazard_ex_T_9 = _fp_data_hazard_ex_T_2 | _fp_data_hazard_ex_T_4; // @[RocketCore.scala:1287:{27,50}]
wire _fp_data_hazard_ex_T_10 = _fp_data_hazard_ex_T_9 | _fp_data_hazard_ex_T_6; // @[RocketCore.scala:1287:{27,50}]
wire _fp_data_hazard_ex_T_11 = _fp_data_hazard_ex_T_10 | _fp_data_hazard_ex_T_8; // @[RocketCore.scala:1287:{27,50}]
wire fp_data_hazard_ex = _fp_data_hazard_ex_T & _fp_data_hazard_ex_T_11; // @[RocketCore.scala:990:{38,53}, :1287:50]
wire _id_ex_hazard_T = data_hazard_ex & ex_cannot_bypass; // @[RocketCore.scala:988:139, :989:36, :991:54]
wire _id_ex_hazard_T_1 = _id_ex_hazard_T | fp_data_hazard_ex; // @[RocketCore.scala:990:53, :991:{54,74}]
wire id_ex_hazard = ex_reg_valid & _id_ex_hazard_T_1; // @[RocketCore.scala:248:35, :991:{35,74}]
wire _mem_cannot_bypass_T = |mem_ctrl_csr; // @[RocketCore.scala:244:21, :997:40]
wire _mem_cannot_bypass_T_1 = mem_ctrl_mem & mem_mem_cmd_bh; // @[RocketCore.scala:244:21, :995:41, :997:66]
wire _mem_cannot_bypass_T_2 = _mem_cannot_bypass_T | _mem_cannot_bypass_T_1; // @[RocketCore.scala:997:{40,50,66}]
wire _mem_cannot_bypass_T_3 = _mem_cannot_bypass_T_2 | mem_ctrl_mul; // @[RocketCore.scala:244:21, :997:{50,84}]
wire _mem_cannot_bypass_T_4 = _mem_cannot_bypass_T_3 | mem_ctrl_div; // @[RocketCore.scala:244:21, :997:{84,100}]
wire _mem_cannot_bypass_T_5 = _mem_cannot_bypass_T_4 | mem_ctrl_fp; // @[RocketCore.scala:244:21, :997:{100,116}]
wire _mem_cannot_bypass_T_6 = _mem_cannot_bypass_T_5 | mem_ctrl_rocc; // @[RocketCore.scala:244:21, :997:{116,131}]
wire mem_cannot_bypass = _mem_cannot_bypass_T_6 | mem_ctrl_vec; // @[RocketCore.scala:244:21, :997:{131,148}]
wire _data_hazard_mem_T_1 = hazard_targets_0_1 & _data_hazard_mem_T; // @[RocketCore.scala:969:42, :998:72, :1287:27]
wire _data_hazard_mem_T_3 = hazard_targets_1_1 & _data_hazard_mem_T_2; // @[RocketCore.scala:970:42, :998:72, :1287:27]
wire _GEN_66 = id_waddr == mem_waddr; // @[RocketCore.scala:326:72, :454:38, :998:72]
wire _data_hazard_mem_T_4; // @[RocketCore.scala:998:72]
assign _data_hazard_mem_T_4 = _GEN_66; // @[RocketCore.scala:998:72]
wire _fp_data_hazard_mem_T_7; // @[RocketCore.scala:999:92]
assign _fp_data_hazard_mem_T_7 = _GEN_66; // @[RocketCore.scala:998:72, :999:92]
wire _data_hazard_mem_T_5 = hazard_targets_2_1 & _data_hazard_mem_T_4; // @[RocketCore.scala:971:42, :998:72, :1287:27]
wire _data_hazard_mem_T_6 = _data_hazard_mem_T_1 | _data_hazard_mem_T_3; // @[RocketCore.scala:1287:{27,50}]
wire _data_hazard_mem_T_7 = _data_hazard_mem_T_6 | _data_hazard_mem_T_5; // @[RocketCore.scala:1287:{27,50}]
wire data_hazard_mem = mem_ctrl_wxd & _data_hazard_mem_T_7; // @[RocketCore.scala:244:21, :998:38, :1287:50]
wire _fp_data_hazard_mem_T = id_ctrl_fp & mem_ctrl_wfd; // @[RocketCore.scala:244:21, :321:21, :999:39]
wire _fp_data_hazard_mem_T_2 = io_fpu_dec_ren1_0 & _fp_data_hazard_mem_T_1; // @[RocketCore.scala:153:7, :999:92, :1287:27]
wire _fp_data_hazard_mem_T_4 = io_fpu_dec_ren2_0 & _fp_data_hazard_mem_T_3; // @[RocketCore.scala:153:7, :999:92, :1287:27]
wire _fp_data_hazard_mem_T_5 = id_raddr3 == mem_waddr; // @[RocketCore.scala:326:72, :454:38, :999:92]
wire _fp_data_hazard_mem_T_6 = io_fpu_dec_ren3_0 & _fp_data_hazard_mem_T_5; // @[RocketCore.scala:153:7, :999:92, :1287:27]
wire _fp_data_hazard_mem_T_8 = io_fpu_dec_wen_0 & _fp_data_hazard_mem_T_7; // @[RocketCore.scala:153:7, :999:92, :1287:27]
wire _fp_data_hazard_mem_T_9 = _fp_data_hazard_mem_T_2 | _fp_data_hazard_mem_T_4; // @[RocketCore.scala:1287:{27,50}]
wire _fp_data_hazard_mem_T_10 = _fp_data_hazard_mem_T_9 | _fp_data_hazard_mem_T_6; // @[RocketCore.scala:1287:{27,50}]
wire _fp_data_hazard_mem_T_11 = _fp_data_hazard_mem_T_10 | _fp_data_hazard_mem_T_8; // @[RocketCore.scala:1287:{27,50}]
wire fp_data_hazard_mem = _fp_data_hazard_mem_T & _fp_data_hazard_mem_T_11; // @[RocketCore.scala:999:{39,55}, :1287:50]
wire _id_mem_hazard_T = data_hazard_mem & mem_cannot_bypass; // @[RocketCore.scala:997:148, :998:38, :1000:57]
wire _id_mem_hazard_T_1 = _id_mem_hazard_T | fp_data_hazard_mem; // @[RocketCore.scala:999:55, :1000:{57,78}]
wire id_mem_hazard = mem_reg_valid & _id_mem_hazard_T_1; // @[RocketCore.scala:265:36, :1000:{37,78}]
wire _id_load_use_T = mem_reg_valid & data_hazard_mem; // @[RocketCore.scala:265:36, :998:38, :1001:32]
assign _id_load_use_T_1 = _id_load_use_T & mem_ctrl_mem; // @[RocketCore.scala:244:21, :1001:{32,51}]
assign id_load_use = _id_load_use_T_1; // @[RocketCore.scala:332:25, :1001:51]
wire _id_vconfig_hazard_T_1 = mem_reg_valid & mem_reg_set_vconfig; // @[RocketCore.scala:265:36, :275:36, :1004:20]
wire _id_vconfig_hazard_T_2 = _id_vconfig_hazard_T_1; // @[RocketCore.scala:1003:42, :1004:20]
wire _id_vconfig_hazard_T_3 = wb_reg_valid & wb_reg_set_vconfig; // @[RocketCore.scala:288:35, :293:35, :1005:19]
wire _id_vconfig_hazard_T_4 = _id_vconfig_hazard_T_2 | _id_vconfig_hazard_T_3; // @[RocketCore.scala:1003:42, :1004:44, :1005:19]
wire _GEN_67 = id_raddr1 == wb_waddr; // @[RocketCore.scala:326:72, :455:36, :1008:70]
wire _data_hazard_wb_T; // @[RocketCore.scala:1008:70]
assign _data_hazard_wb_T = _GEN_67; // @[RocketCore.scala:1008:70]
wire _fp_data_hazard_wb_T_1; // @[RocketCore.scala:1009:90]
assign _fp_data_hazard_wb_T_1 = _GEN_67; // @[RocketCore.scala:1008:70, :1009:90]
wire _data_hazard_wb_T_1 = hazard_targets_0_1 & _data_hazard_wb_T; // @[RocketCore.scala:969:42, :1008:70, :1287:27]
wire _GEN_68 = id_raddr2 == wb_waddr; // @[RocketCore.scala:326:72, :455:36, :1008:70]
wire _data_hazard_wb_T_2; // @[RocketCore.scala:1008:70]
assign _data_hazard_wb_T_2 = _GEN_68; // @[RocketCore.scala:1008:70]
wire _fp_data_hazard_wb_T_3; // @[RocketCore.scala:1009:90]
assign _fp_data_hazard_wb_T_3 = _GEN_68; // @[RocketCore.scala:1008:70, :1009:90]
wire _data_hazard_wb_T_3 = hazard_targets_1_1 & _data_hazard_wb_T_2; // @[RocketCore.scala:970:42, :1008:70, :1287:27]
wire _GEN_69 = id_waddr == wb_waddr; // @[RocketCore.scala:326:72, :455:36, :1008:70]
wire _data_hazard_wb_T_4; // @[RocketCore.scala:1008:70]
assign _data_hazard_wb_T_4 = _GEN_69; // @[RocketCore.scala:1008:70]
wire _fp_data_hazard_wb_T_7; // @[RocketCore.scala:1009:90]
assign _fp_data_hazard_wb_T_7 = _GEN_69; // @[RocketCore.scala:1008:70, :1009:90]
wire _data_hazard_wb_T_5 = hazard_targets_2_1 & _data_hazard_wb_T_4; // @[RocketCore.scala:971:42, :1008:70, :1287:27]
wire _data_hazard_wb_T_6 = _data_hazard_wb_T_1 | _data_hazard_wb_T_3; // @[RocketCore.scala:1287:{27,50}]
wire _data_hazard_wb_T_7 = _data_hazard_wb_T_6 | _data_hazard_wb_T_5; // @[RocketCore.scala:1287:{27,50}]
wire data_hazard_wb = wb_ctrl_wxd & _data_hazard_wb_T_7; // @[RocketCore.scala:245:20, :1008:36, :1287:50]
wire _fp_data_hazard_wb_T = id_ctrl_fp & wb_ctrl_wfd; // @[RocketCore.scala:245:20, :321:21, :1009:38]
wire _fp_data_hazard_wb_T_2 = io_fpu_dec_ren1_0 & _fp_data_hazard_wb_T_1; // @[RocketCore.scala:153:7, :1009:90, :1287:27]
wire _fp_data_hazard_wb_T_4 = io_fpu_dec_ren2_0 & _fp_data_hazard_wb_T_3; // @[RocketCore.scala:153:7, :1009:90, :1287:27]
wire _fp_data_hazard_wb_T_5 = id_raddr3 == wb_waddr; // @[RocketCore.scala:326:72, :455:36, :1009:90]
wire _fp_data_hazard_wb_T_6 = io_fpu_dec_ren3_0 & _fp_data_hazard_wb_T_5; // @[RocketCore.scala:153:7, :1009:90, :1287:27]
wire _fp_data_hazard_wb_T_8 = io_fpu_dec_wen_0 & _fp_data_hazard_wb_T_7; // @[RocketCore.scala:153:7, :1009:90, :1287:27]
wire _fp_data_hazard_wb_T_9 = _fp_data_hazard_wb_T_2 | _fp_data_hazard_wb_T_4; // @[RocketCore.scala:1287:{27,50}]
wire _fp_data_hazard_wb_T_10 = _fp_data_hazard_wb_T_9 | _fp_data_hazard_wb_T_6; // @[RocketCore.scala:1287:{27,50}]
wire _fp_data_hazard_wb_T_11 = _fp_data_hazard_wb_T_10 | _fp_data_hazard_wb_T_8; // @[RocketCore.scala:1287:{27,50}]
wire fp_data_hazard_wb = _fp_data_hazard_wb_T & _fp_data_hazard_wb_T_11; // @[RocketCore.scala:1009:{38,53}, :1287:50]
wire _id_wb_hazard_T = data_hazard_wb & wb_set_sboard; // @[RocketCore.scala:756:69, :1008:36, :1010:54]
wire _id_wb_hazard_T_1 = _id_wb_hazard_T | fp_data_hazard_wb; // @[RocketCore.scala:1009:53, :1010:{54,71}]
wire id_wb_hazard = wb_reg_valid & _id_wb_hazard_T_1; // @[RocketCore.scala:288:35, :1010:{35,71}]
reg [31:0] _id_stall_fpu_r; // @[RocketCore.scala:1305:29]
wire _id_stall_fpu_T = wb_dcache_miss | wb_ctrl_vec; // @[RocketCore.scala:245:20, :596:36, :1014:36]
wire _id_stall_fpu_T_1 = _id_stall_fpu_T & wb_ctrl_wfd; // @[RocketCore.scala:245:20, :1014:{36,52}]
wire _id_stall_fpu_T_2 = _id_stall_fpu_T_1 | io_fpu_sboard_set_0; // @[RocketCore.scala:153:7, :1014:{52,67}]
wire _id_stall_fpu_T_3 = _id_stall_fpu_T_2 & wb_valid; // @[RocketCore.scala:815:45, :1014:{67,89}]
wire _id_stall_fpu_T_7 = _id_stall_fpu_T_3; // @[RocketCore.scala:1014:89, :1312:17]
wire [31:0] _id_stall_fpu_T_5 = _id_stall_fpu_T_3 ? _id_stall_fpu_T_4 : 32'h0; // @[RocketCore.scala:1014:89, :1309:{49,58}]
wire [31:0] _id_stall_fpu_T_6 = _id_stall_fpu_r | _id_stall_fpu_T_5; // @[RocketCore.scala:1300:60, :1305:29, :1309:49]
wire _id_stall_fpu_T_8 = dmem_resp_replay & dmem_resp_fpu; // @[RocketCore.scala:766:45, :769:42, :1016:39]
wire _id_stall_fpu_T_9 = _id_stall_fpu_T_8; // @[RocketCore.scala:1016:{39,57}]
wire [31:0] _id_stall_fpu_T_10 = 32'h1 << io_fpu_ll_resp_tag_0; // @[RocketCore.scala:153:7, :1309:58]
wire [31:0] _id_stall_fpu_T_11 = _id_stall_fpu_T_9 ? _id_stall_fpu_T_10 : 32'h0; // @[RocketCore.scala:1016:57, :1309:{49,58}]
wire [31:0] _id_stall_fpu_T_12 = ~_id_stall_fpu_T_11; // @[RocketCore.scala:1301:64, :1309:49]
wire [31:0] _id_stall_fpu_T_13 = _id_stall_fpu_T_6 & _id_stall_fpu_T_12; // @[RocketCore.scala:1300:60, :1301:{62,64}]
wire _id_stall_fpu_T_14 = _id_stall_fpu_T_7 | _id_stall_fpu_T_9; // @[RocketCore.scala:1016:57, :1312:17]
wire [31:0] _id_stall_fpu_T_15 = 32'h1 << io_fpu_sboard_clra_0; // @[RocketCore.scala:153:7, :1309:58]
wire [31:0] _id_stall_fpu_T_16 = io_fpu_sboard_clr_0 ? _id_stall_fpu_T_15 : 32'h0; // @[RocketCore.scala:153:7, :1309:{49,58}]
wire [31:0] _id_stall_fpu_T_17 = ~_id_stall_fpu_T_16; // @[RocketCore.scala:1301:64, :1309:49]
wire [31:0] _id_stall_fpu_T_18 = _id_stall_fpu_T_13 & _id_stall_fpu_T_17; // @[RocketCore.scala:1301:{62,64}]
wire _id_stall_fpu_T_19 = _id_stall_fpu_T_14 | io_fpu_sboard_clr_0; // @[RocketCore.scala:153:7, :1312:17]
wire [31:0] _id_stall_fpu_T_20 = _id_stall_fpu_r >> _GEN_62; // @[RocketCore.scala:1302:35, :1305:29]
wire _id_stall_fpu_T_21 = _id_stall_fpu_T_20[0]; // @[RocketCore.scala:1302:35]
wire _id_stall_fpu_T_22 = io_fpu_dec_ren1_0 & _id_stall_fpu_T_21; // @[RocketCore.scala:153:7, :1287:27, :1302:35]
wire [31:0] _id_stall_fpu_T_23 = _id_stall_fpu_r >> _GEN_63; // @[RocketCore.scala:1302:35, :1305:29]
wire _id_stall_fpu_T_24 = _id_stall_fpu_T_23[0]; // @[RocketCore.scala:1302:35]
wire _id_stall_fpu_T_25 = io_fpu_dec_ren2_0 & _id_stall_fpu_T_24; // @[RocketCore.scala:153:7, :1287:27, :1302:35]
wire [31:0] _id_stall_fpu_T_26 = _id_stall_fpu_r >> id_raddr3; // @[RocketCore.scala:326:72, :1302:35, :1305:29]
wire _id_stall_fpu_T_27 = _id_stall_fpu_T_26[0]; // @[RocketCore.scala:1302:35]
wire _id_stall_fpu_T_28 = io_fpu_dec_ren3_0 & _id_stall_fpu_T_27; // @[RocketCore.scala:153:7, :1287:27, :1302:35]
wire [31:0] _id_stall_fpu_T_29 = _id_stall_fpu_r >> _GEN_64; // @[RocketCore.scala:1302:35, :1305:29]
wire _id_stall_fpu_T_30 = _id_stall_fpu_T_29[0]; // @[RocketCore.scala:1302:35]
wire _id_stall_fpu_T_31 = io_fpu_dec_wen_0 & _id_stall_fpu_T_30; // @[RocketCore.scala:153:7, :1287:27, :1302:35]
wire _id_stall_fpu_T_32 = _id_stall_fpu_T_22 | _id_stall_fpu_T_25; // @[RocketCore.scala:1287:{27,50}]
wire _id_stall_fpu_T_33 = _id_stall_fpu_T_32 | _id_stall_fpu_T_28; // @[RocketCore.scala:1287:{27,50}]
wire id_stall_fpu = _id_stall_fpu_T_33 | _id_stall_fpu_T_31; // @[RocketCore.scala:1287:{27,50}]
reg dcache_blocked_blocked; // @[RocketCore.scala:1024:22]
wire _dcache_blocked_blocked_T = ~io_dmem_req_ready_0; // @[RocketCore.scala:153:7, :597:45, :1025:16]
wire _dcache_blocked_blocked_T_1 = _dcache_blocked_blocked_T; // @[RocketCore.scala:1025:{16,35}]
wire _dcache_blocked_blocked_T_2 = ~io_dmem_perf_grant_0; // @[RocketCore.scala:153:7, :1025:63]
wire _dcache_blocked_blocked_T_3 = _dcache_blocked_blocked_T_1 & _dcache_blocked_blocked_T_2; // @[RocketCore.scala:1025:{35,60,63}]
wire _dcache_blocked_blocked_T_4 = dcache_blocked_blocked | io_dmem_req_valid_0; // @[RocketCore.scala:153:7, :1024:22, :1025:95]
wire _dcache_blocked_blocked_T_5 = _dcache_blocked_blocked_T_4 | io_dmem_s2_nack_0; // @[RocketCore.scala:153:7, :1025:{95,116}]
wire _dcache_blocked_blocked_T_6 = _dcache_blocked_blocked_T_3 & _dcache_blocked_blocked_T_5; // @[RocketCore.scala:1025:{60,83,116}]
wire _dcache_blocked_T = ~io_dmem_perf_grant_0; // @[RocketCore.scala:153:7, :1025:63, :1026:16]
wire dcache_blocked = dcache_blocked_blocked & _dcache_blocked_T; // @[RocketCore.scala:1024:22, :1026:{13,16}]
reg rocc_blocked; // @[RocketCore.scala:1028:25]
wire _rocc_blocked_T = ~wb_xcpt; // @[RocketCore.scala:815:48, :1029:19, :1278:14]
wire _rocc_blocked_T_2 = _rocc_blocked_T; // @[RocketCore.scala:1029:{19,28}]
wire _rocc_blocked_T_3 = io_rocc_cmd_valid | rocc_blocked; // @[RocketCore.scala:153:7, :1028:25, :1029:72]
wire _rocc_blocked_T_4 = _rocc_blocked_T_2 & _rocc_blocked_T_3; // @[RocketCore.scala:1029:{28,50,72}]
wire _ctrl_stalld_T = id_ex_hazard | id_mem_hazard; // @[RocketCore.scala:991:35, :1000:37, :1032:18]
wire _ctrl_stalld_T_1 = _ctrl_stalld_T | id_wb_hazard; // @[RocketCore.scala:1010:35, :1032:{18,35}]
wire _ctrl_stalld_T_2 = _ctrl_stalld_T_1 | id_sboard_hazard; // @[RocketCore.scala:1032:{35,51}, :1287:50]
wire _ctrl_stalld_T_3 = _ctrl_stalld_T_2; // @[RocketCore.scala:1032:{51,71}]
wire _ctrl_stalld_T_4 = ex_reg_valid | mem_reg_valid; // @[RocketCore.scala:248:35, :265:36, :1034:40]
wire _ctrl_stalld_T_5 = _ctrl_stalld_T_4 | wb_reg_valid; // @[RocketCore.scala:288:35, :1034:{40,57}]
wire _ctrl_stalld_T_6 = _csr_io_singleStep & _ctrl_stalld_T_5; // @[RocketCore.scala:341:19, :1034:{23,57}]
wire _ctrl_stalld_T_7 = _ctrl_stalld_T_3 | _ctrl_stalld_T_6; // @[RocketCore.scala:1032:71, :1033:23, :1034:23]
wire _ctrl_stalld_T_8 = id_csr_en & _csr_io_decode_0_fp_csr; // @[package.scala:81:59]
wire _ctrl_stalld_T_9 = ~io_fpu_fcsr_rdy_0; // @[RocketCore.scala:153:7, :1035:45]
wire _ctrl_stalld_T_10 = _ctrl_stalld_T_8 & _ctrl_stalld_T_9; // @[RocketCore.scala:1035:{15,42,45}]
wire _ctrl_stalld_T_11 = _ctrl_stalld_T_7 | _ctrl_stalld_T_10; // @[RocketCore.scala:1033:23, :1034:74, :1035:42]
wire _ctrl_stalld_T_14 = _ctrl_stalld_T_11; // @[RocketCore.scala:1034:74, :1035:62]
wire _ctrl_stalld_T_15 = id_ctrl_fp & id_stall_fpu; // @[RocketCore.scala:321:21, :1037:16, :1287:50]
wire _ctrl_stalld_T_16 = _ctrl_stalld_T_14 | _ctrl_stalld_T_15; // @[RocketCore.scala:1035:62, :1036:61, :1037:16]
wire _ctrl_stalld_T_17 = id_ctrl_mem & dcache_blocked; // @[RocketCore.scala:321:21, :1026:13, :1038:17]
wire _ctrl_stalld_T_18 = _ctrl_stalld_T_16 | _ctrl_stalld_T_17; // @[RocketCore.scala:1036:61, :1037:32, :1038:17]
wire _ctrl_stalld_T_19 = id_ctrl_rocc & rocc_blocked; // @[RocketCore.scala:321:21, :1028:25, :1039:18]
wire _ctrl_stalld_T_20 = _ctrl_stalld_T_18 | _ctrl_stalld_T_19; // @[RocketCore.scala:1037:32, :1038:35, :1039:18]
wire _ctrl_stalld_T_21 = ~wb_wxd; // @[RocketCore.scala:755:29, :782:26, :1040:65]
wire _ctrl_stalld_T_22 = _div_io_resp_valid & _ctrl_stalld_T_21; // @[RocketCore.scala:511:19, :1040:{62,65}]
wire _ctrl_stalld_T_23 = _div_io_req_ready | _ctrl_stalld_T_22; // @[RocketCore.scala:511:19, :1040:{40,62}]
wire _ctrl_stalld_T_24 = ~_ctrl_stalld_T_23; // @[RocketCore.scala:1040:{21,40}]
wire _ctrl_stalld_T_25 = _ctrl_stalld_T_24 | _div_io_req_valid_T; // @[RocketCore.scala:512:36, :1040:{21,75}]
wire _ctrl_stalld_T_26 = id_ctrl_div & _ctrl_stalld_T_25; // @[RocketCore.scala:321:21, :1040:{17,75}]
wire _ctrl_stalld_T_27 = _ctrl_stalld_T_20 | _ctrl_stalld_T_26; // @[RocketCore.scala:1038:35, :1039:34, :1040:17]
wire _ctrl_stalld_T_29 = _ctrl_stalld_T_27; // @[RocketCore.scala:1039:34, :1040:96]
wire _ctrl_stalld_T_30 = _ctrl_stalld_T_29 | id_do_fence; // @[RocketCore.scala:410:32, :1040:96, :1041:15]
wire _ctrl_stalld_T_31 = _ctrl_stalld_T_30 | _csr_io_csr_stall; // @[RocketCore.scala:341:19, :1041:15, :1042:17]
wire _ctrl_stalld_T_32 = _ctrl_stalld_T_31 | id_reg_pause; // @[RocketCore.scala:161:25, :1042:17, :1043:22]
wire ctrl_stalld = _ctrl_stalld_T_32; // @[RocketCore.scala:1043:22, :1044:18]
wire _ctrl_killd_T = ~_ibuf_io_inst_0_valid; // @[RocketCore.scala:311:20, :1046:17]
wire _ctrl_killd_T_1 = _ctrl_killd_T | _ibuf_io_inst_0_bits_replay; // @[RocketCore.scala:311:20, :1046:{17,40}]
wire _ctrl_killd_T_2 = _ctrl_killd_T_1 | take_pc_mem_wb; // @[RocketCore.scala:307:35, :1046:{40,71}]
wire _ctrl_killd_T_3 = _ctrl_killd_T_2 | ctrl_stalld; // @[RocketCore.scala:1044:18, :1046:{71,89}]
assign _ctrl_killd_T_4 = _ctrl_killd_T_3 | _csr_io_interrupt; // @[RocketCore.scala:341:19, :1046:{89,104}]
assign ctrl_killd = _ctrl_killd_T_4; // @[RocketCore.scala:338:24, :1046:104]
assign _io_imem_req_bits_speculative_T = ~take_pc_wb; // @[RocketCore.scala:304:24, :706:34, :1049:35]
assign io_imem_req_bits_speculative_0 = _io_imem_req_bits_speculative_T; // @[RocketCore.scala:153:7, :1049:35]
wire _io_imem_req_bits_pc_T = wb_xcpt | _csr_io_eret; // @[RocketCore.scala:341:19, :1051:17, :1278:14]
wire [39:0] _io_imem_req_bits_pc_T_1 = replay_wb ? wb_reg_pc : mem_npc; // @[RocketCore.scala:295:22, :619:139, :761:71, :1052:8]
assign _io_imem_req_bits_pc_T_2 = _io_imem_req_bits_pc_T ? _csr_io_evec : _io_imem_req_bits_pc_T_1; // @[RocketCore.scala:341:19, :1051:{8,17}, :1052:8]
assign io_imem_req_bits_pc_0 = _io_imem_req_bits_pc_T_2; // @[RocketCore.scala:153:7, :1051:8]
wire _io_imem_flush_icache_T = wb_reg_valid & wb_ctrl_fence_i; // @[RocketCore.scala:245:20, :288:35, :1054:40]
wire _io_imem_flush_icache_T_1 = ~io_dmem_s2_nack_0; // @[RocketCore.scala:153:7, :1054:62]
assign _io_imem_flush_icache_T_2 = _io_imem_flush_icache_T & _io_imem_flush_icache_T_1; // @[RocketCore.scala:1054:{40,59,62}]
assign io_imem_flush_icache_0 = _io_imem_flush_icache_T_2; // @[RocketCore.scala:153:7, :1054:59]
wire _io_imem_might_request_imem_might_request_reg_T = ex_pc_valid | mem_pc_valid; // @[RocketCore.scala:595:51, :614:54, :1056:43]
wire _io_imem_might_request_imem_might_request_reg_T_1 = io_ptw_customCSRs_csrs_0_value_0[1]; // @[CustomCSRs.scala:44:61]
wire _io_imem_might_request_imem_might_request_reg_T_2 = _io_imem_might_request_imem_might_request_reg_T | _io_imem_might_request_imem_might_request_reg_T_1; // @[CustomCSRs.scala:44:61]
wire _io_imem_might_request_imem_might_request_reg_T_3 = _io_imem_might_request_imem_might_request_reg_T_2; // @[RocketCore.scala:1056:{59,103}]
wire _io_imem_progress_T = ~replay_wb_common; // @[RocketCore.scala:757:42, :1059:47]
wire _io_imem_progress_T_1 = wb_reg_valid & _io_imem_progress_T; // @[RocketCore.scala:288:35, :1059:{44,47}]
reg io_imem_progress_REG; // @[RocketCore.scala:1059:30]
assign io_imem_progress_0 = io_imem_progress_REG; // @[RocketCore.scala:153:7, :1059:30]
assign _io_imem_sfence_valid_T = wb_reg_valid & wb_reg_sfence; // @[RocketCore.scala:288:35, :294:26, :1060:40]
assign io_imem_sfence_valid_0 = _io_imem_sfence_valid_T; // @[RocketCore.scala:153:7, :1060:40]
assign _io_imem_sfence_bits_rs1_T = wb_reg_mem_size[0]; // @[RocketCore.scala:296:28, :1061:45]
assign io_imem_sfence_bits_rs1_0 = _io_imem_sfence_bits_rs1_T; // @[RocketCore.scala:153:7, :1061:45]
assign _io_imem_sfence_bits_rs2_T = wb_reg_mem_size[1]; // @[RocketCore.scala:296:28, :1062:45]
assign io_imem_sfence_bits_rs2_0 = _io_imem_sfence_bits_rs2_T; // @[RocketCore.scala:153:7, :1062:45]
assign io_imem_sfence_bits_asid_0 = wb_reg_rs2[0]; // @[RocketCore.scala:153:7, :303:23, :1064:28]
wire _ibuf_io_inst_0_ready_T = ~ctrl_stalld; // @[RocketCore.scala:1044:18, :1069:28]
wire _io_imem_btb_update_valid_T = ~take_pc_wb; // @[RocketCore.scala:304:24, :706:34, :1071:48]
wire _io_imem_btb_update_valid_T_1 = mem_reg_valid & _io_imem_btb_update_valid_T; // @[RocketCore.scala:265:36, :1071:{45,48}]
wire _io_imem_btb_update_valid_T_2 = _io_imem_btb_update_valid_T_1 & mem_wrong_npc; // @[RocketCore.scala:621:8, :1071:{45,60}]
wire _io_imem_btb_update_valid_T_3 = ~mem_cfi; // @[RocketCore.scala:625:50, :1071:81]
wire _io_imem_btb_update_valid_T_4 = _io_imem_btb_update_valid_T_3 | mem_cfi_taken; // @[RocketCore.scala:626:74, :1071:{81,90}]
assign _io_imem_btb_update_valid_T_5 = _io_imem_btb_update_valid_T_2 & _io_imem_btb_update_valid_T_4; // @[RocketCore.scala:1071:{60,77,90}]
assign io_imem_btb_update_valid_0 = _io_imem_btb_update_valid_T_5; // @[RocketCore.scala:153:7, :1071:77]
wire _GEN_70 = mem_ctrl_jal | mem_ctrl_jalr; // @[RocketCore.scala:244:21, :1074:23]
wire _io_imem_btb_update_bits_cfiType_T; // @[RocketCore.scala:1074:23]
assign _io_imem_btb_update_bits_cfiType_T = _GEN_70; // @[RocketCore.scala:1074:23]
wire _io_imem_btb_update_bits_cfiType_T_8; // @[RocketCore.scala:1076:22]
assign _io_imem_btb_update_bits_cfiType_T_8 = _GEN_70; // @[RocketCore.scala:1074:23, :1076:22]
wire _io_imem_btb_update_bits_cfiType_T_1 = mem_waddr[0]; // @[RocketCore.scala:454:38, :1074:53]
wire _io_imem_btb_update_bits_cfiType_T_2 = _io_imem_btb_update_bits_cfiType_T & _io_imem_btb_update_bits_cfiType_T_1; // @[RocketCore.scala:1074:{23,41,53}]
wire [4:0] _io_imem_btb_update_bits_cfiType_T_3 = mem_reg_inst[19:15]; // @[RocketCore.scala:278:25, :1075:39]
wire [4:0] _io_imem_btb_update_bits_cfiType_T_4 = _io_imem_btb_update_bits_cfiType_T_3; // @[RocketCore.scala:1075:{39,47}]
wire [4:0] _io_imem_btb_update_bits_cfiType_T_5 = _io_imem_btb_update_bits_cfiType_T_4 & 5'h1B; // @[RocketCore.scala:1075:{47,64}]
wire _io_imem_btb_update_bits_cfiType_T_6 = _io_imem_btb_update_bits_cfiType_T_5 == 5'h1; // @[RocketCore.scala:1075:64]
wire _io_imem_btb_update_bits_cfiType_T_7 = mem_ctrl_jalr & _io_imem_btb_update_bits_cfiType_T_6; // @[RocketCore.scala:244:21, :1075:{23,64}]
wire _io_imem_btb_update_bits_cfiType_T_9 = _io_imem_btb_update_bits_cfiType_T_8; // @[RocketCore.scala:1076:{8,22}]
wire [1:0] _io_imem_btb_update_bits_cfiType_T_10 = _io_imem_btb_update_bits_cfiType_T_7 ? 2'h3 : {1'h0, _io_imem_btb_update_bits_cfiType_T_9}; // @[RocketCore.scala:1075:{8,23}, :1076:8]
assign _io_imem_btb_update_bits_cfiType_T_11 = _io_imem_btb_update_bits_cfiType_T_2 ? 2'h2 : _io_imem_btb_update_bits_cfiType_T_10; // @[RocketCore.scala:1074:{8,41}, :1075:8]
assign io_imem_btb_update_bits_cfiType_0 = _io_imem_btb_update_bits_cfiType_T_11; // @[RocketCore.scala:153:7, :1074:8]
assign io_imem_btb_update_bits_target_0 = io_imem_req_bits_pc_0[38:0]; // @[RocketCore.scala:153:7, :1078:34]
wire [1:0] _io_imem_btb_update_bits_br_pc_T = {~mem_reg_rvc, 1'h0}; // @[RocketCore.scala:266:36, :1079:74]
wire [40:0] _io_imem_btb_update_bits_br_pc_T_1 = {1'h0, mem_reg_pc} + {39'h0, _io_imem_btb_update_bits_br_pc_T}; // @[RocketCore.scala:277:23, :1079:{69,74}]
wire [39:0] _io_imem_btb_update_bits_br_pc_T_2 = _io_imem_btb_update_bits_br_pc_T_1[39:0]; // @[RocketCore.scala:1079:69]
assign io_imem_btb_update_bits_br_pc_0 = _io_imem_btb_update_bits_br_pc_T_2[38:0]; // @[RocketCore.scala:153:7, :1079:{33,69}]
wire [38:0] _io_imem_btb_update_bits_pc_T = ~io_imem_btb_update_bits_br_pc_0; // @[RocketCore.scala:153:7, :1080:35]
wire [38:0] _io_imem_btb_update_bits_pc_T_1 = {_io_imem_btb_update_bits_pc_T[38:2], 2'h3}; // @[RocketCore.scala:1080:{35,66}]
assign _io_imem_btb_update_bits_pc_T_2 = ~_io_imem_btb_update_bits_pc_T_1; // @[RocketCore.scala:1080:{33,66}]
assign io_imem_btb_update_bits_pc_0 = _io_imem_btb_update_bits_pc_T_2; // @[RocketCore.scala:153:7, :1080:33]
wire _io_imem_bht_update_valid_T = ~take_pc_wb; // @[RocketCore.scala:304:24, :706:34, :1084:48]
assign _io_imem_bht_update_valid_T_1 = mem_reg_valid & _io_imem_bht_update_valid_T; // @[RocketCore.scala:265:36, :1084:{45,48}]
assign io_imem_bht_update_valid_0 = _io_imem_bht_update_valid_T_1; // @[RocketCore.scala:153:7, :1084:45]
wire _io_fpu_valid_T = ~ctrl_killd; // @[RocketCore.scala:338:24, :525:19, :1094:19]
assign _io_fpu_valid_T_1 = _io_fpu_valid_T & id_ctrl_fp; // @[RocketCore.scala:321:21, :1094:{19,31}]
assign io_fpu_valid_0 = _io_fpu_valid_T_1; // @[RocketCore.scala:153:7, :1094:31]
assign _io_fpu_ll_resp_val_T = dmem_resp_valid & dmem_resp_fpu; // @[RocketCore.scala:766:45, :768:44, :1099:41]
assign io_fpu_ll_resp_val_0 = _io_fpu_ll_resp_val_T; // @[RocketCore.scala:153:7, :1099:41]
assign io_fpu_ll_resp_type_0 = {1'h0, io_dmem_resp_bits_size_0}; // @[RocketCore.scala:153:7, :1101:23]
assign _io_fpu_keep_clock_enabled_T = io_ptw_customCSRs_csrs_0_value_0[2]; // @[CustomCSRs.scala:45:59]
assign io_fpu_keep_clock_enabled_0 = _io_fpu_keep_clock_enabled_T; // @[CustomCSRs.scala:45:59]
assign _io_dmem_req_valid_T = ex_reg_valid & ex_ctrl_mem; // @[RocketCore.scala:243:20, :248:35, :1130:41]
assign io_dmem_req_valid_0 = _io_dmem_req_valid_T; // @[RocketCore.scala:153:7, :1130:41]
wire [5:0] ex_dcache_tag = {ex_waddr, ex_ctrl_fp}; // @[RocketCore.scala:243:20, :453:36, :1131:26]
assign io_dmem_req_bits_tag_0 = {1'h0, ex_dcache_tag}; // @[RocketCore.scala:153:7, :1131:26, :1133:25]
wire _io_dmem_req_bits_signed_T_1 = ex_reg_inst[14]; // @[RocketCore.scala:259:24, :1136:75]
wire _io_dmem_req_bits_signed_T_2 = _io_dmem_req_bits_signed_T_1; // @[RocketCore.scala:1136:{34,75}]
assign _io_dmem_req_bits_signed_T_3 = ~_io_dmem_req_bits_signed_T_2; // @[RocketCore.scala:1136:{30,34}]
assign io_dmem_req_bits_signed_0 = _io_dmem_req_bits_signed_T_3; // @[RocketCore.scala:153:7, :1136:30]
wire [24:0] _io_dmem_req_bits_addr_a_T = ex_rs_0[63:39]; // @[RocketCore.scala:469:14, :1293:17]
wire [24:0] io_dmem_req_bits_addr_a = _io_dmem_req_bits_addr_a_T; // @[RocketCore.scala:1293:{17,23}]
wire _io_dmem_req_bits_addr_msb_T = io_dmem_req_bits_addr_a == 25'h0; // @[RocketCore.scala:1293:23, :1294:21]
wire _io_dmem_req_bits_addr_msb_T_1 = &io_dmem_req_bits_addr_a; // @[RocketCore.scala:1293:23, :1294:34]
wire _io_dmem_req_bits_addr_msb_T_2 = _io_dmem_req_bits_addr_msb_T | _io_dmem_req_bits_addr_msb_T_1; // @[RocketCore.scala:1294:{21,29,34}]
wire _io_dmem_req_bits_addr_msb_T_3 = _alu_io_adder_out[39]; // @[RocketCore.scala:504:19, :1294:46]
wire _io_dmem_req_bits_addr_msb_T_4 = _alu_io_adder_out[38]; // @[RocketCore.scala:504:19, :1294:54]
wire _io_dmem_req_bits_addr_msb_T_5 = ~_io_dmem_req_bits_addr_msb_T_4; // @[RocketCore.scala:1294:{51,54}]
wire io_dmem_req_bits_addr_msb = _io_dmem_req_bits_addr_msb_T_2 ? _io_dmem_req_bits_addr_msb_T_3 : _io_dmem_req_bits_addr_msb_T_5; // @[RocketCore.scala:1294:{18,29,46,51}]
wire [38:0] _io_dmem_req_bits_addr_T = _alu_io_adder_out[38:0]; // @[RocketCore.scala:504:19, :1295:16]
assign _io_dmem_req_bits_addr_T_1 = {io_dmem_req_bits_addr_msb, _io_dmem_req_bits_addr_T}; // @[RocketCore.scala:1294:18, :1295:{8,16}]
assign io_dmem_req_bits_addr_0 = _io_dmem_req_bits_addr_T_1; // @[RocketCore.scala:153:7, :1295:8]
assign io_dmem_req_bits_dprv_0 = _io_dmem_req_bits_dprv_T; // @[RocketCore.scala:153:7, :1140:31]
assign io_dmem_req_bits_dv_0 = _io_dmem_req_bits_dv_T; // @[RocketCore.scala:153:7, :1141:37]
wire _io_dmem_req_bits_no_resp_T_4 = _io_dmem_req_bits_no_resp_T | _io_dmem_req_bits_no_resp_T_1; // @[package.scala:16:47, :81:59]
wire _io_dmem_req_bits_no_resp_T_5 = _io_dmem_req_bits_no_resp_T_4 | _io_dmem_req_bits_no_resp_T_2; // @[package.scala:16:47, :81:59]
wire _io_dmem_req_bits_no_resp_T_6 = _io_dmem_req_bits_no_resp_T_5 | _io_dmem_req_bits_no_resp_T_3; // @[package.scala:16:47, :81:59]
wire _io_dmem_req_bits_no_resp_T_11 = _io_dmem_req_bits_no_resp_T_7 | _io_dmem_req_bits_no_resp_T_8; // @[package.scala:16:47, :81:59]
wire _io_dmem_req_bits_no_resp_T_12 = _io_dmem_req_bits_no_resp_T_11 | _io_dmem_req_bits_no_resp_T_9; // @[package.scala:16:47, :81:59]
wire _io_dmem_req_bits_no_resp_T_13 = _io_dmem_req_bits_no_resp_T_12 | _io_dmem_req_bits_no_resp_T_10; // @[package.scala:16:47, :81:59]
wire _io_dmem_req_bits_no_resp_T_19 = _io_dmem_req_bits_no_resp_T_14 | _io_dmem_req_bits_no_resp_T_15; // @[package.scala:16:47, :81:59]
wire _io_dmem_req_bits_no_resp_T_20 = _io_dmem_req_bits_no_resp_T_19 | _io_dmem_req_bits_no_resp_T_16; // @[package.scala:16:47, :81:59]
wire _io_dmem_req_bits_no_resp_T_21 = _io_dmem_req_bits_no_resp_T_20 | _io_dmem_req_bits_no_resp_T_17; // @[package.scala:16:47, :81:59]
wire _io_dmem_req_bits_no_resp_T_22 = _io_dmem_req_bits_no_resp_T_21 | _io_dmem_req_bits_no_resp_T_18; // @[package.scala:16:47, :81:59]
wire _io_dmem_req_bits_no_resp_T_23 = _io_dmem_req_bits_no_resp_T_13 | _io_dmem_req_bits_no_resp_T_22; // @[package.scala:81:59]
wire _io_dmem_req_bits_no_resp_T_24 = _io_dmem_req_bits_no_resp_T_6 | _io_dmem_req_bits_no_resp_T_23; // @[package.scala:81:59]
wire _io_dmem_req_bits_no_resp_T_25 = ~_io_dmem_req_bits_no_resp_T_24; // @[RocketCore.scala:1142:31]
wire _io_dmem_req_bits_no_resp_T_26 = ~ex_ctrl_fp; // @[RocketCore.scala:243:20, :1142:60]
wire _io_dmem_req_bits_no_resp_T_27 = ex_waddr == 5'h0; // @[RocketCore.scala:453:36, :1142:84]
wire _io_dmem_req_bits_no_resp_T_28 = _io_dmem_req_bits_no_resp_T_26 & _io_dmem_req_bits_no_resp_T_27; // @[RocketCore.scala:1142:{60,72,84}]
assign _io_dmem_req_bits_no_resp_T_29 = _io_dmem_req_bits_no_resp_T_25 | _io_dmem_req_bits_no_resp_T_28; // @[RocketCore.scala:1142:{31,56,72}]
assign io_dmem_req_bits_no_resp_0 = _io_dmem_req_bits_no_resp_T_29; // @[RocketCore.scala:153:7, :1142:56]
assign _io_dmem_s1_data_data_T = mem_ctrl_fp ? io_fpu_store_data_0 : mem_reg_rs2; // @[RocketCore.scala:153:7, :244:21, :283:24, :1148:63]
assign io_dmem_s1_data_data_0 = _io_dmem_s1_data_data_T; // @[RocketCore.scala:153:7, :1148:63]
wire _io_dmem_s1_kill_T = killm_common | mem_ldst_xcpt; // @[RocketCore.scala:700:68, :1151:35, :1278:14]
wire _io_dmem_s1_kill_T_1 = _io_dmem_s1_kill_T | fpu_kill_mem; // @[RocketCore.scala:696:51, :1151:{35,52}]
assign _io_dmem_s1_kill_T_2 = _io_dmem_s1_kill_T_1; // @[RocketCore.scala:1151:{52,68}]
assign io_dmem_s1_kill_0 = _io_dmem_s1_kill_T_2; // @[RocketCore.scala:153:7, :1151:68]
wire _io_dmem_keep_clock_enabled_T = _ibuf_io_inst_0_valid & id_ctrl_mem; // @[RocketCore.scala:311:20, :321:21, :1154:55]
wire _io_dmem_keep_clock_enabled_T_1 = ~_csr_io_csr_stall; // @[RocketCore.scala:341:19, :1154:73]
assign _io_dmem_keep_clock_enabled_T_2 = _io_dmem_keep_clock_enabled_T & _io_dmem_keep_clock_enabled_T_1; // @[RocketCore.scala:1154:{55,70,73}]
assign io_dmem_keep_clock_enabled_0 = _io_dmem_keep_clock_enabled_T_2; // @[RocketCore.scala:153:7, :1154:70]
wire _io_rocc_cmd_valid_T_1 = ~replay_wb_common; // @[RocketCore.scala:757:42, :1059:47, :1156:56]
assign _io_rocc_cmd_valid_T_2 = _io_rocc_cmd_valid_T & _io_rocc_cmd_valid_T_1; // @[RocketCore.scala:1156:{37,53,56}]
assign io_rocc_cmd_valid = _io_rocc_cmd_valid_T_2; // @[RocketCore.scala:153:7, :1156:53]
wire [6:0] _io_rocc_cmd_bits_inst_T_7; // @[RocketCore.scala:1159:48]
assign io_rocc_cmd_bits_inst_funct = _io_rocc_cmd_bits_inst_WIRE_funct; // @[RocketCore.scala:153:7, :1159:48]
wire [4:0] _io_rocc_cmd_bits_inst_T_6; // @[RocketCore.scala:1159:48]
assign io_rocc_cmd_bits_inst_rs2 = _io_rocc_cmd_bits_inst_WIRE_rs2; // @[RocketCore.scala:153:7, :1159:48]
wire [4:0] _io_rocc_cmd_bits_inst_T_5; // @[RocketCore.scala:1159:48]
assign io_rocc_cmd_bits_inst_rs1 = _io_rocc_cmd_bits_inst_WIRE_rs1; // @[RocketCore.scala:153:7, :1159:48]
wire _io_rocc_cmd_bits_inst_T_4; // @[RocketCore.scala:1159:48]
assign io_rocc_cmd_bits_inst_xd = _io_rocc_cmd_bits_inst_WIRE_xd; // @[RocketCore.scala:153:7, :1159:48]
wire _io_rocc_cmd_bits_inst_T_3; // @[RocketCore.scala:1159:48]
assign io_rocc_cmd_bits_inst_xs1 = _io_rocc_cmd_bits_inst_WIRE_xs1; // @[RocketCore.scala:153:7, :1159:48]
wire _io_rocc_cmd_bits_inst_T_2; // @[RocketCore.scala:1159:48]
assign io_rocc_cmd_bits_inst_xs2 = _io_rocc_cmd_bits_inst_WIRE_xs2; // @[RocketCore.scala:153:7, :1159:48]
wire [4:0] _io_rocc_cmd_bits_inst_T_1; // @[RocketCore.scala:1159:48]
assign io_rocc_cmd_bits_inst_rd = _io_rocc_cmd_bits_inst_WIRE_rd; // @[RocketCore.scala:153:7, :1159:48]
wire [6:0] _io_rocc_cmd_bits_inst_T; // @[RocketCore.scala:1159:48]
assign io_rocc_cmd_bits_inst_opcode = _io_rocc_cmd_bits_inst_WIRE_opcode; // @[RocketCore.scala:153:7, :1159:48]
assign _io_rocc_cmd_bits_inst_T = _io_rocc_cmd_bits_inst_WIRE_1[6:0]; // @[RocketCore.scala:1159:48]
assign _io_rocc_cmd_bits_inst_WIRE_opcode = _io_rocc_cmd_bits_inst_T; // @[RocketCore.scala:1159:48]
assign _io_rocc_cmd_bits_inst_T_1 = _io_rocc_cmd_bits_inst_WIRE_1[11:7]; // @[RocketCore.scala:1159:48]
assign _io_rocc_cmd_bits_inst_WIRE_rd = _io_rocc_cmd_bits_inst_T_1; // @[RocketCore.scala:1159:48]
assign _io_rocc_cmd_bits_inst_T_2 = _io_rocc_cmd_bits_inst_WIRE_1[12]; // @[RocketCore.scala:1159:48]
assign _io_rocc_cmd_bits_inst_WIRE_xs2 = _io_rocc_cmd_bits_inst_T_2; // @[RocketCore.scala:1159:48]
assign _io_rocc_cmd_bits_inst_T_3 = _io_rocc_cmd_bits_inst_WIRE_1[13]; // @[RocketCore.scala:1159:48]
assign _io_rocc_cmd_bits_inst_WIRE_xs1 = _io_rocc_cmd_bits_inst_T_3; // @[RocketCore.scala:1159:48]
assign _io_rocc_cmd_bits_inst_T_4 = _io_rocc_cmd_bits_inst_WIRE_1[14]; // @[RocketCore.scala:1159:48]
assign _io_rocc_cmd_bits_inst_WIRE_xd = _io_rocc_cmd_bits_inst_T_4; // @[RocketCore.scala:1159:48]
assign _io_rocc_cmd_bits_inst_T_5 = _io_rocc_cmd_bits_inst_WIRE_1[19:15]; // @[RocketCore.scala:1159:48]
assign _io_rocc_cmd_bits_inst_WIRE_rs1 = _io_rocc_cmd_bits_inst_T_5; // @[RocketCore.scala:1159:48]
assign _io_rocc_cmd_bits_inst_T_6 = _io_rocc_cmd_bits_inst_WIRE_1[24:20]; // @[RocketCore.scala:1159:48]
assign _io_rocc_cmd_bits_inst_WIRE_rs2 = _io_rocc_cmd_bits_inst_T_6; // @[RocketCore.scala:1159:48]
assign _io_rocc_cmd_bits_inst_T_7 = _io_rocc_cmd_bits_inst_WIRE_1[31:25]; // @[RocketCore.scala:1159:48]
assign _io_rocc_cmd_bits_inst_WIRE_funct = _io_rocc_cmd_bits_inst_T_7; // @[RocketCore.scala:1159:48]
wire [4:0] _unpause_T = _csr_io_time[4:0]; // @[RocketCore.scala:341:19, :1164:28]
wire _unpause_T_1 = _unpause_T == 5'h0; // @[RocketCore.scala:1164:{28,62}]
wire _unpause_T_2 = _unpause_T_1 | _csr_io_inhibit_cycle; // @[RocketCore.scala:341:19, :1164:{62,70}]
wire _unpause_T_3 = _unpause_T_2 | io_dmem_perf_release_0; // @[RocketCore.scala:153:7, :1164:{70,94}]
wire unpause = _unpause_T_3 | take_pc_mem_wb; // @[RocketCore.scala:307:35, :1164:{94,118}]
reg icache_blocked_REG; // @[RocketCore.scala:1183:55]
wire _icache_blocked_T = io_imem_resp_valid_0 | icache_blocked_REG; // @[RocketCore.scala:153:7, :1183:{45,55}]
wire icache_blocked = ~_icache_blocked_T; // @[RocketCore.scala:1183:{24,45}]
wire _coreMonitorBundle_valid_T_1; // @[RocketCore.scala:1192:52]
wire [63:0] _coreMonitorBundle_pc_T_3; // @[package.scala:132:15]
wire _coreMonitorBundle_wrenx_T_1; // @[RocketCore.scala:1194:37]
wire [4:0] _coreMonitorBundle_rd0src_T; // @[RocketCore.scala:1198:42]
wire [4:0] _coreMonitorBundle_rd1src_T; // @[RocketCore.scala:1200:42]
wire coreMonitorBundle_excpt; // @[RocketCore.scala:1186:31]
wire [2:0] coreMonitorBundle_priv_mode; // @[RocketCore.scala:1186:31]
wire [63:0] coreMonitorBundle_hartid; // @[RocketCore.scala:1186:31]
wire [31:0] coreMonitorBundle_timer; // @[RocketCore.scala:1186:31]
wire coreMonitorBundle_valid; // @[RocketCore.scala:1186:31]
wire [63:0] coreMonitorBundle_pc; // @[RocketCore.scala:1186:31]
wire coreMonitorBundle_wrenx; // @[RocketCore.scala:1186:31]
wire [4:0] coreMonitorBundle_rd0src; // @[RocketCore.scala:1186:31]
wire [63:0] coreMonitorBundle_rd0val; // @[RocketCore.scala:1186:31]
wire [4:0] coreMonitorBundle_rd1src; // @[RocketCore.scala:1186:31]
wire [63:0] coreMonitorBundle_rd1val; // @[RocketCore.scala:1186:31]
wire [31:0] coreMonitorBundle_inst; // @[RocketCore.scala:1186:31]
wire [63:0] _GEN_71 = {63'h0, io_hartid_0}; // @[RocketCore.scala:153:7, :1190:28]
assign coreMonitorBundle_hartid = _GEN_71; // @[RocketCore.scala:1186:31, :1190:28]
wire [63:0] xrfWriteBundle_hartid; // @[RocketCore.scala:1249:28]
assign xrfWriteBundle_hartid = _GEN_71; // @[RocketCore.scala:1190:28, :1249:28]
assign coreMonitorBundle_timer = _coreMonitorBundle_timer_T; // @[RocketCore.scala:1186:31, :1191:41]
wire _coreMonitorBundle_valid_T = ~_csr_io_trace_0_exception; // @[RocketCore.scala:341:19, :1192:55]
assign _coreMonitorBundle_valid_T_1 = _csr_io_trace_0_valid & _coreMonitorBundle_valid_T; // @[RocketCore.scala:341:19, :1192:{52,55}]
assign coreMonitorBundle_valid = _coreMonitorBundle_valid_T_1; // @[RocketCore.scala:1186:31, :1192:52]
wire [39:0] _coreMonitorBundle_pc_T; // @[RocketCore.scala:1193:48]
wire _coreMonitorBundle_pc_T_1 = _coreMonitorBundle_pc_T[39]; // @[package.scala:132:38]
wire [23:0] _coreMonitorBundle_pc_T_2 = {24{_coreMonitorBundle_pc_T_1}}; // @[package.scala:132:{20,38}]
assign _coreMonitorBundle_pc_T_3 = {_coreMonitorBundle_pc_T_2, _coreMonitorBundle_pc_T}; // @[package.scala:132:{15,20}]
assign coreMonitorBundle_pc = _coreMonitorBundle_pc_T_3; // @[package.scala:132:15]
wire _coreMonitorBundle_wrenx_T = ~wb_set_sboard; // @[RocketCore.scala:756:69, :1194:40]
assign _coreMonitorBundle_wrenx_T_1 = wb_wen & _coreMonitorBundle_wrenx_T; // @[RocketCore.scala:816:25, :1194:{37,40}]
assign coreMonitorBundle_wrenx = _coreMonitorBundle_wrenx_T_1; // @[RocketCore.scala:1186:31, :1194:37]
assign _coreMonitorBundle_rd0src_T = wb_reg_inst[19:15]; // @[RocketCore.scala:300:24, :1198:42]
assign coreMonitorBundle_rd0src = _coreMonitorBundle_rd0src_T; // @[RocketCore.scala:1186:31, :1198:42]
reg [63:0] coreMonitorBundle_rd0val_REG; // @[RocketCore.scala:1199:46]
reg [63:0] coreMonitorBundle_rd0val_REG_1; // @[RocketCore.scala:1199:38]
assign coreMonitorBundle_rd0val = coreMonitorBundle_rd0val_REG_1; // @[RocketCore.scala:1186:31, :1199:38]
assign _coreMonitorBundle_rd1src_T = wb_reg_inst[24:20]; // @[RocketCore.scala:300:24, :1200:42]
assign coreMonitorBundle_rd1src = _coreMonitorBundle_rd1src_T; // @[RocketCore.scala:1186:31, :1200:42]
reg [63:0] coreMonitorBundle_rd1val_REG; // @[RocketCore.scala:1201:46]
reg [63:0] coreMonitorBundle_rd1val_REG_1; // @[RocketCore.scala:1201:38]
assign coreMonitorBundle_rd1val = coreMonitorBundle_rd1val_REG_1; // @[RocketCore.scala:1186:31, :1201:38] |
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_49 :
input clock : Clock
input reset : Reset
output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, request_hp : UInt<1>, flip grant : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip kill : UInt<1>, flip clear : UInt<1>, flip ldspec_miss : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<7>, poisoned : UInt<1>}}[7], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<7>}[1], flip in_uop : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}, out_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, debug : { p1 : UInt<1>, p2 : UInt<1>, p3 : UInt<1>, ppred : UInt<1>, state : UInt<2>}}
wire next_state : UInt
wire next_uopc : UInt
wire next_lrs1_rtype : UInt
wire next_lrs2_rtype : UInt
regreset state : UInt<2>, clock, reset, UInt<2>(0h0)
regreset p1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset p2 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset p3 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset ppred : UInt<1>, clock, reset, UInt<1>(0h0)
regreset p1_poisoned : UInt<1>, clock, reset, UInt<1>(0h0)
regreset p2_poisoned : UInt<1>, clock, reset, UInt<1>(0h0)
connect p1_poisoned, UInt<1>(0h0)
connect p2_poisoned, UInt<1>(0h0)
node next_p1_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned)
node next_p2_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned)
wire slot_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
invalidate slot_uop_uop.debug_tsrc
invalidate slot_uop_uop.debug_fsrc
invalidate slot_uop_uop.bp_xcpt_if
invalidate slot_uop_uop.bp_debug_if
invalidate slot_uop_uop.xcpt_ma_if
invalidate slot_uop_uop.xcpt_ae_if
invalidate slot_uop_uop.xcpt_pf_if
invalidate slot_uop_uop.fp_single
invalidate slot_uop_uop.fp_val
invalidate slot_uop_uop.frs3_en
invalidate slot_uop_uop.lrs2_rtype
invalidate slot_uop_uop.lrs1_rtype
invalidate slot_uop_uop.dst_rtype
invalidate slot_uop_uop.ldst_val
invalidate slot_uop_uop.lrs3
invalidate slot_uop_uop.lrs2
invalidate slot_uop_uop.lrs1
invalidate slot_uop_uop.ldst
invalidate slot_uop_uop.ldst_is_rs1
invalidate slot_uop_uop.flush_on_commit
invalidate slot_uop_uop.is_unique
invalidate slot_uop_uop.is_sys_pc2epc
invalidate slot_uop_uop.uses_stq
invalidate slot_uop_uop.uses_ldq
invalidate slot_uop_uop.is_amo
invalidate slot_uop_uop.is_fencei
invalidate slot_uop_uop.is_fence
invalidate slot_uop_uop.mem_signed
invalidate slot_uop_uop.mem_size
invalidate slot_uop_uop.mem_cmd
invalidate slot_uop_uop.bypassable
invalidate slot_uop_uop.exc_cause
invalidate slot_uop_uop.exception
invalidate slot_uop_uop.stale_pdst
invalidate slot_uop_uop.ppred_busy
invalidate slot_uop_uop.prs3_busy
invalidate slot_uop_uop.prs2_busy
invalidate slot_uop_uop.prs1_busy
invalidate slot_uop_uop.ppred
invalidate slot_uop_uop.prs3
invalidate slot_uop_uop.prs2
invalidate slot_uop_uop.prs1
invalidate slot_uop_uop.pdst
invalidate slot_uop_uop.rxq_idx
invalidate slot_uop_uop.stq_idx
invalidate slot_uop_uop.ldq_idx
invalidate slot_uop_uop.rob_idx
invalidate slot_uop_uop.csr_addr
invalidate slot_uop_uop.imm_packed
invalidate slot_uop_uop.taken
invalidate slot_uop_uop.pc_lob
invalidate slot_uop_uop.edge_inst
invalidate slot_uop_uop.ftq_idx
invalidate slot_uop_uop.br_tag
invalidate slot_uop_uop.br_mask
invalidate slot_uop_uop.is_sfb
invalidate slot_uop_uop.is_jal
invalidate slot_uop_uop.is_jalr
invalidate slot_uop_uop.is_br
invalidate slot_uop_uop.iw_p2_poisoned
invalidate slot_uop_uop.iw_p1_poisoned
invalidate slot_uop_uop.iw_state
invalidate slot_uop_uop.ctrl.is_std
invalidate slot_uop_uop.ctrl.is_sta
invalidate slot_uop_uop.ctrl.is_load
invalidate slot_uop_uop.ctrl.csr_cmd
invalidate slot_uop_uop.ctrl.fcn_dw
invalidate slot_uop_uop.ctrl.op_fcn
invalidate slot_uop_uop.ctrl.imm_sel
invalidate slot_uop_uop.ctrl.op2_sel
invalidate slot_uop_uop.ctrl.op1_sel
invalidate slot_uop_uop.ctrl.br_type
invalidate slot_uop_uop.fu_code
invalidate slot_uop_uop.iq_type
invalidate slot_uop_uop.debug_pc
invalidate slot_uop_uop.is_rvc
invalidate slot_uop_uop.debug_inst
invalidate slot_uop_uop.inst
invalidate slot_uop_uop.uopc
connect slot_uop_uop.uopc, UInt<7>(0h0)
connect slot_uop_uop.bypassable, UInt<1>(0h0)
connect slot_uop_uop.fp_val, UInt<1>(0h0)
connect slot_uop_uop.uses_stq, UInt<1>(0h0)
connect slot_uop_uop.uses_ldq, UInt<1>(0h0)
connect slot_uop_uop.pdst, UInt<1>(0h0)
connect slot_uop_uop.dst_rtype, UInt<2>(0h2)
wire slot_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}
invalidate slot_uop_cs.is_std
invalidate slot_uop_cs.is_sta
invalidate slot_uop_cs.is_load
invalidate slot_uop_cs.csr_cmd
invalidate slot_uop_cs.fcn_dw
invalidate slot_uop_cs.op_fcn
invalidate slot_uop_cs.imm_sel
invalidate slot_uop_cs.op2_sel
invalidate slot_uop_cs.op1_sel
invalidate slot_uop_cs.br_type
connect slot_uop_cs.br_type, UInt<4>(0h0)
connect slot_uop_cs.csr_cmd, UInt<3>(0h0)
connect slot_uop_cs.is_load, UInt<1>(0h0)
connect slot_uop_cs.is_sta, UInt<1>(0h0)
connect slot_uop_cs.is_std, UInt<1>(0h0)
connect slot_uop_uop.ctrl, slot_uop_cs
regreset slot_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock, reset, slot_uop_uop
node next_uop = mux(io.in_uop.valid, io.in_uop.bits, slot_uop)
when io.kill :
connect state, UInt<2>(0h0)
else :
when io.in_uop.valid :
connect state, io.in_uop.bits.iw_state
else :
when io.clear :
connect state, UInt<2>(0h0)
else :
connect state, next_state
connect next_state, state
connect next_uopc, slot_uop.uopc
connect next_lrs1_rtype, slot_uop.lrs1_rtype
connect next_lrs2_rtype, slot_uop.lrs2_rtype
when io.kill :
connect next_state, UInt<2>(0h0)
else :
node _T = eq(state, UInt<2>(0h1))
node _T_1 = and(io.grant, _T)
node _T_2 = eq(state, UInt<2>(0h2))
node _T_3 = and(io.grant, _T_2)
node _T_4 = and(_T_3, p1)
node _T_5 = and(_T_4, p2)
node _T_6 = and(_T_5, ppred)
node _T_7 = or(_T_1, _T_6)
when _T_7 :
node _T_8 = or(p1_poisoned, p2_poisoned)
node _T_9 = and(io.ldspec_miss, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
when _T_10 :
connect next_state, UInt<2>(0h0)
else :
node _T_11 = eq(state, UInt<2>(0h2))
node _T_12 = and(io.grant, _T_11)
when _T_12 :
node _T_13 = or(p1_poisoned, p2_poisoned)
node _T_14 = and(io.ldspec_miss, _T_13)
node _T_15 = eq(_T_14, UInt<1>(0h0))
when _T_15 :
connect next_state, UInt<2>(0h1)
when p1 :
connect slot_uop.uopc, UInt<7>(0h3)
connect next_uopc, UInt<7>(0h3)
connect slot_uop.lrs1_rtype, UInt<2>(0h2)
connect next_lrs1_rtype, UInt<2>(0h2)
else :
connect slot_uop.lrs2_rtype, UInt<2>(0h2)
connect next_lrs2_rtype, UInt<2>(0h2)
when io.in_uop.valid :
connect slot_uop, io.in_uop.bits
node _T_16 = eq(state, UInt<2>(0h0))
node _T_17 = or(_T_16, io.clear)
node _T_18 = or(_T_17, io.kill)
node _T_19 = asUInt(reset)
node _T_20 = eq(_T_19, UInt<1>(0h0))
when _T_20 :
node _T_21 = eq(_T_18, UInt<1>(0h0))
when _T_21 :
printf(clock, UInt<1>(0h1), "Assertion failed: trying to overwrite a valid issue slot.\n at issue-slot.scala:156 assert (is_invalid || io.clear || io.kill, \"trying to overwrite a valid issue slot.\")\n") : printf
assert(clock, _T_18, UInt<1>(0h1), "") : assert
wire next_p1 : UInt<1>
connect next_p1, p1
wire next_p2 : UInt<1>
connect next_p2, p2
wire next_p3 : UInt<1>
connect next_p3, p3
wire next_ppred : UInt<1>
connect next_ppred, ppred
when io.in_uop.valid :
node _p1_T = eq(io.in_uop.bits.prs1_busy, UInt<1>(0h0))
connect p1, _p1_T
node _p2_T = eq(io.in_uop.bits.prs2_busy, UInt<1>(0h0))
connect p2, _p2_T
node _p3_T = eq(io.in_uop.bits.prs3_busy, UInt<1>(0h0))
connect p3, _p3_T
node _ppred_T = eq(io.in_uop.bits.ppred_busy, UInt<1>(0h0))
connect ppred, _ppred_T
node _T_22 = and(io.ldspec_miss, next_p1_poisoned)
when _T_22 :
node _T_23 = neq(next_uop.prs1, UInt<1>(0h0))
node _T_24 = asUInt(reset)
node _T_25 = eq(_T_24, UInt<1>(0h0))
when _T_25 :
node _T_26 = eq(_T_23, UInt<1>(0h0))
when _T_26 :
printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs1=x0!\n at issue-slot.scala:176 assert(next_uop.prs1 =/= 0.U, \"Poison bit can't be set for prs1=x0!\")\n") : printf_1
assert(clock, _T_23, UInt<1>(0h1), "") : assert_1
connect p1, UInt<1>(0h0)
node _T_27 = and(io.ldspec_miss, next_p2_poisoned)
when _T_27 :
node _T_28 = neq(next_uop.prs2, UInt<1>(0h0))
node _T_29 = asUInt(reset)
node _T_30 = eq(_T_29, UInt<1>(0h0))
when _T_30 :
node _T_31 = eq(_T_28, UInt<1>(0h0))
when _T_31 :
printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs2=x0!\n at issue-slot.scala:180 assert(next_uop.prs2 =/= 0.U, \"Poison bit can't be set for prs2=x0!\")\n") : printf_2
assert(clock, _T_28, UInt<1>(0h1), "") : assert_2
connect p2, UInt<1>(0h0)
node _T_32 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs1)
node _T_33 = and(io.wakeup_ports[0].valid, _T_32)
when _T_33 :
connect p1, UInt<1>(0h1)
node _T_34 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs2)
node _T_35 = and(io.wakeup_ports[0].valid, _T_34)
when _T_35 :
connect p2, UInt<1>(0h1)
node _T_36 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs3)
node _T_37 = and(io.wakeup_ports[0].valid, _T_36)
when _T_37 :
connect p3, UInt<1>(0h1)
node _T_38 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs1)
node _T_39 = and(io.wakeup_ports[1].valid, _T_38)
when _T_39 :
connect p1, UInt<1>(0h1)
node _T_40 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs2)
node _T_41 = and(io.wakeup_ports[1].valid, _T_40)
when _T_41 :
connect p2, UInt<1>(0h1)
node _T_42 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs3)
node _T_43 = and(io.wakeup_ports[1].valid, _T_42)
when _T_43 :
connect p3, UInt<1>(0h1)
node _T_44 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs1)
node _T_45 = and(io.wakeup_ports[2].valid, _T_44)
when _T_45 :
connect p1, UInt<1>(0h1)
node _T_46 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs2)
node _T_47 = and(io.wakeup_ports[2].valid, _T_46)
when _T_47 :
connect p2, UInt<1>(0h1)
node _T_48 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs3)
node _T_49 = and(io.wakeup_ports[2].valid, _T_48)
when _T_49 :
connect p3, UInt<1>(0h1)
node _T_50 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs1)
node _T_51 = and(io.wakeup_ports[3].valid, _T_50)
when _T_51 :
connect p1, UInt<1>(0h1)
node _T_52 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs2)
node _T_53 = and(io.wakeup_ports[3].valid, _T_52)
when _T_53 :
connect p2, UInt<1>(0h1)
node _T_54 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs3)
node _T_55 = and(io.wakeup_ports[3].valid, _T_54)
when _T_55 :
connect p3, UInt<1>(0h1)
node _T_56 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs1)
node _T_57 = and(io.wakeup_ports[4].valid, _T_56)
when _T_57 :
connect p1, UInt<1>(0h1)
node _T_58 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs2)
node _T_59 = and(io.wakeup_ports[4].valid, _T_58)
when _T_59 :
connect p2, UInt<1>(0h1)
node _T_60 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs3)
node _T_61 = and(io.wakeup_ports[4].valid, _T_60)
when _T_61 :
connect p3, UInt<1>(0h1)
node _T_62 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs1)
node _T_63 = and(io.wakeup_ports[5].valid, _T_62)
when _T_63 :
connect p1, UInt<1>(0h1)
node _T_64 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs2)
node _T_65 = and(io.wakeup_ports[5].valid, _T_64)
when _T_65 :
connect p2, UInt<1>(0h1)
node _T_66 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs3)
node _T_67 = and(io.wakeup_ports[5].valid, _T_66)
when _T_67 :
connect p3, UInt<1>(0h1)
node _T_68 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs1)
node _T_69 = and(io.wakeup_ports[6].valid, _T_68)
when _T_69 :
connect p1, UInt<1>(0h1)
node _T_70 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs2)
node _T_71 = and(io.wakeup_ports[6].valid, _T_70)
when _T_71 :
connect p2, UInt<1>(0h1)
node _T_72 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs3)
node _T_73 = and(io.wakeup_ports[6].valid, _T_72)
when _T_73 :
connect p3, UInt<1>(0h1)
node _T_74 = eq(io.pred_wakeup_port.bits, next_uop.ppred)
node _T_75 = and(io.pred_wakeup_port.valid, _T_74)
when _T_75 :
connect ppred, UInt<1>(0h1)
node _T_76 = eq(io.spec_ld_wakeup[0].bits, UInt<1>(0h0))
node _T_77 = and(io.spec_ld_wakeup[0].valid, _T_76)
node _T_78 = eq(_T_77, UInt<1>(0h0))
node _T_79 = asUInt(reset)
node _T_80 = eq(_T_79, UInt<1>(0h0))
when _T_80 :
node _T_81 = eq(_T_78, UInt<1>(0h0))
when _T_81 :
printf(clock, UInt<1>(0h1), "Assertion failed: Loads to x0 should never speculatively wakeup other instructions\n at issue-slot.scala:203 assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),\n") : printf_3
assert(clock, _T_78, UInt<1>(0h1), "") : assert_3
node _T_82 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs1)
node _T_83 = and(io.spec_ld_wakeup[0].valid, _T_82)
node _T_84 = eq(next_uop.lrs1_rtype, UInt<2>(0h0))
node _T_85 = and(_T_83, _T_84)
when _T_85 :
connect p1, UInt<1>(0h1)
connect p1_poisoned, UInt<1>(0h1)
node _T_86 = eq(next_p1_poisoned, UInt<1>(0h0))
node _T_87 = asUInt(reset)
node _T_88 = eq(_T_87, UInt<1>(0h0))
when _T_88 :
node _T_89 = eq(_T_86, UInt<1>(0h0))
when _T_89 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:214 assert (!next_p1_poisoned)\n") : printf_4
assert(clock, _T_86, UInt<1>(0h1), "") : assert_4
node _T_90 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs2)
node _T_91 = and(io.spec_ld_wakeup[0].valid, _T_90)
node _T_92 = eq(next_uop.lrs2_rtype, UInt<2>(0h0))
node _T_93 = and(_T_91, _T_92)
when _T_93 :
connect p2, UInt<1>(0h1)
connect p2_poisoned, UInt<1>(0h1)
node _T_94 = eq(next_p2_poisoned, UInt<1>(0h0))
node _T_95 = asUInt(reset)
node _T_96 = eq(_T_95, UInt<1>(0h0))
when _T_96 :
node _T_97 = eq(_T_94, UInt<1>(0h0))
when _T_97 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:221 assert (!next_p2_poisoned)\n") : printf_5
assert(clock, _T_94, UInt<1>(0h1), "") : assert_5
node _next_br_mask_T = not(io.brupdate.b1.resolve_mask)
node next_br_mask = and(slot_uop.br_mask, _next_br_mask_T)
node _T_98 = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask)
node _T_99 = neq(_T_98, UInt<1>(0h0))
when _T_99 :
connect next_state, UInt<2>(0h0)
node _T_100 = eq(io.in_uop.valid, UInt<1>(0h0))
when _T_100 :
connect slot_uop.br_mask, next_br_mask
node _io_request_T = neq(state, UInt<2>(0h0))
node _io_request_T_1 = and(_io_request_T, p1)
node _io_request_T_2 = and(_io_request_T_1, p2)
node _io_request_T_3 = and(_io_request_T_2, p3)
node _io_request_T_4 = and(_io_request_T_3, ppred)
node _io_request_T_5 = eq(io.kill, UInt<1>(0h0))
node _io_request_T_6 = and(_io_request_T_4, _io_request_T_5)
connect io.request, _io_request_T_6
node _high_priority_T = or(slot_uop.is_br, slot_uop.is_jal)
node high_priority = or(_high_priority_T, slot_uop.is_jalr)
node _io_request_hp_T = and(io.request, high_priority)
connect io.request_hp, _io_request_hp_T
node _T_101 = eq(state, UInt<2>(0h1))
when _T_101 :
node _io_request_T_7 = and(p1, p2)
node _io_request_T_8 = and(_io_request_T_7, p3)
node _io_request_T_9 = and(_io_request_T_8, ppred)
node _io_request_T_10 = eq(io.kill, UInt<1>(0h0))
node _io_request_T_11 = and(_io_request_T_9, _io_request_T_10)
connect io.request, _io_request_T_11
else :
node _T_102 = eq(state, UInt<2>(0h2))
when _T_102 :
node _io_request_T_12 = or(p1, p2)
node _io_request_T_13 = and(_io_request_T_12, ppred)
node _io_request_T_14 = eq(io.kill, UInt<1>(0h0))
node _io_request_T_15 = and(_io_request_T_13, _io_request_T_14)
connect io.request, _io_request_T_15
else :
connect io.request, UInt<1>(0h0)
node _io_valid_T = neq(state, UInt<2>(0h0))
connect io.valid, _io_valid_T
connect io.uop, slot_uop
connect io.uop.iw_p1_poisoned, p1_poisoned
connect io.uop.iw_p2_poisoned, p2_poisoned
node _may_vacate_T = eq(state, UInt<2>(0h1))
node _may_vacate_T_1 = eq(state, UInt<2>(0h2))
node _may_vacate_T_2 = and(_may_vacate_T_1, p1)
node _may_vacate_T_3 = and(_may_vacate_T_2, p2)
node _may_vacate_T_4 = and(_may_vacate_T_3, ppred)
node _may_vacate_T_5 = or(_may_vacate_T, _may_vacate_T_4)
node may_vacate = and(io.grant, _may_vacate_T_5)
node _squash_grant_T = or(p1_poisoned, p2_poisoned)
node squash_grant = and(io.ldspec_miss, _squash_grant_T)
node _io_will_be_valid_T = neq(state, UInt<2>(0h0))
node _io_will_be_valid_T_1 = eq(squash_grant, UInt<1>(0h0))
node _io_will_be_valid_T_2 = and(may_vacate, _io_will_be_valid_T_1)
node _io_will_be_valid_T_3 = eq(_io_will_be_valid_T_2, UInt<1>(0h0))
node _io_will_be_valid_T_4 = and(_io_will_be_valid_T, _io_will_be_valid_T_3)
connect io.will_be_valid, _io_will_be_valid_T_4
connect io.out_uop, slot_uop
connect io.out_uop.iw_state, next_state
connect io.out_uop.uopc, next_uopc
connect io.out_uop.lrs1_rtype, next_lrs1_rtype
connect io.out_uop.lrs2_rtype, next_lrs2_rtype
connect io.out_uop.br_mask, next_br_mask
node _io_out_uop_prs1_busy_T = eq(p1, UInt<1>(0h0))
connect io.out_uop.prs1_busy, _io_out_uop_prs1_busy_T
node _io_out_uop_prs2_busy_T = eq(p2, UInt<1>(0h0))
connect io.out_uop.prs2_busy, _io_out_uop_prs2_busy_T
node _io_out_uop_prs3_busy_T = eq(p3, UInt<1>(0h0))
connect io.out_uop.prs3_busy, _io_out_uop_prs3_busy_T
node _io_out_uop_ppred_busy_T = eq(ppred, UInt<1>(0h0))
connect io.out_uop.ppred_busy, _io_out_uop_ppred_busy_T
connect io.out_uop.iw_p1_poisoned, p1_poisoned
connect io.out_uop.iw_p2_poisoned, p2_poisoned
node _T_103 = eq(state, UInt<2>(0h2))
when _T_103 :
node _T_104 = and(p1, p2)
node _T_105 = and(_T_104, ppred)
when _T_105 :
skip
else :
node _T_106 = and(p1, ppred)
when _T_106 :
connect io.uop.uopc, slot_uop.uopc
connect io.uop.lrs2_rtype, UInt<2>(0h2)
else :
node _T_107 = and(p2, ppred)
when _T_107 :
connect io.uop.uopc, UInt<7>(0h3)
connect io.uop.lrs1_rtype, UInt<2>(0h2)
connect io.debug.p1, p1
connect io.debug.p2, p2
connect io.debug.p3, p3
connect io.debug.ppred, ppred
connect io.debug.state, state | module IssueSlot_49( // @[issue-slot.scala:69:7]
input clock, // @[issue-slot.scala:69:7]
input reset, // @[issue-slot.scala:69:7]
output io_valid, // @[issue-slot.scala:73:14]
output io_will_be_valid, // @[issue-slot.scala:73:14]
output io_request, // @[issue-slot.scala:73:14]
output io_request_hp, // @[issue-slot.scala:73:14]
input io_grant, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14]
input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14]
input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14]
input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14]
input io_brupdate_b2_valid, // @[issue-slot.scala:73:14]
input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14]
input io_brupdate_b2_taken, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14]
input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14]
input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14]
input io_kill, // @[issue-slot.scala:73:14]
input io_clear, // @[issue-slot.scala:73:14]
input io_ldspec_miss, // @[issue-slot.scala:73:14]
input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_0_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_1_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_2_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_2_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_2_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_3_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_3_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_3_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_4_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_4_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_4_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_5_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_5_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_5_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_6_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_6_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_6_bits_poisoned, // @[issue-slot.scala:73:14]
input io_spec_ld_wakeup_0_valid, // @[issue-slot.scala:73:14]
input [6:0] io_spec_ld_wakeup_0_bits, // @[issue-slot.scala:73:14]
input io_in_uop_valid, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14]
input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14]
input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14]
input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14]
input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14]
input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14]
input io_in_uop_bits_iw_p1_poisoned, // @[issue-slot.scala:73:14]
input io_in_uop_bits_iw_p2_poisoned, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14]
input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14]
input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14]
input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14]
input io_in_uop_bits_taken, // @[issue-slot.scala:73:14]
input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14]
input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14]
input io_in_uop_bits_exception, // @[issue-slot.scala:73:14]
input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14]
input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14]
input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14]
input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14]
input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14]
input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14]
input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14]
input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14]
output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14]
output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14]
output io_out_uop_is_rvc, // @[issue-slot.scala:73:14]
output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14]
output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14]
output io_out_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
output io_out_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
output io_out_uop_is_br, // @[issue-slot.scala:73:14]
output io_out_uop_is_jalr, // @[issue-slot.scala:73:14]
output io_out_uop_is_jal, // @[issue-slot.scala:73:14]
output io_out_uop_is_sfb, // @[issue-slot.scala:73:14]
output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14]
output io_out_uop_edge_inst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14]
output io_out_uop_taken, // @[issue-slot.scala:73:14]
output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14]
output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14]
output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14]
output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14]
output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14]
output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14]
output io_out_uop_exception, // @[issue-slot.scala:73:14]
output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14]
output io_out_uop_bypassable, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14]
output io_out_uop_mem_signed, // @[issue-slot.scala:73:14]
output io_out_uop_is_fence, // @[issue-slot.scala:73:14]
output io_out_uop_is_fencei, // @[issue-slot.scala:73:14]
output io_out_uop_is_amo, // @[issue-slot.scala:73:14]
output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14]
output io_out_uop_uses_stq, // @[issue-slot.scala:73:14]
output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
output io_out_uop_is_unique, // @[issue-slot.scala:73:14]
output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14]
output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14]
output io_out_uop_ldst_val, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
output io_out_uop_frs3_en, // @[issue-slot.scala:73:14]
output io_out_uop_fp_val, // @[issue-slot.scala:73:14]
output io_out_uop_fp_single, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14]
output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14]
output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14]
output [31:0] io_uop_inst, // @[issue-slot.scala:73:14]
output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14]
output io_uop_is_rvc, // @[issue-slot.scala:73:14]
output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14]
output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14]
output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14]
output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14]
output io_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
output io_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
output io_uop_is_br, // @[issue-slot.scala:73:14]
output io_uop_is_jalr, // @[issue-slot.scala:73:14]
output io_uop_is_jal, // @[issue-slot.scala:73:14]
output io_uop_is_sfb, // @[issue-slot.scala:73:14]
output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14]
output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14]
output io_uop_edge_inst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14]
output io_uop_taken, // @[issue-slot.scala:73:14]
output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14]
output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14]
output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14]
output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14]
output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14]
output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14]
output io_uop_prs1_busy, // @[issue-slot.scala:73:14]
output io_uop_prs2_busy, // @[issue-slot.scala:73:14]
output io_uop_prs3_busy, // @[issue-slot.scala:73:14]
output io_uop_ppred_busy, // @[issue-slot.scala:73:14]
output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14]
output io_uop_exception, // @[issue-slot.scala:73:14]
output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14]
output io_uop_bypassable, // @[issue-slot.scala:73:14]
output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14]
output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14]
output io_uop_mem_signed, // @[issue-slot.scala:73:14]
output io_uop_is_fence, // @[issue-slot.scala:73:14]
output io_uop_is_fencei, // @[issue-slot.scala:73:14]
output io_uop_is_amo, // @[issue-slot.scala:73:14]
output io_uop_uses_ldq, // @[issue-slot.scala:73:14]
output io_uop_uses_stq, // @[issue-slot.scala:73:14]
output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
output io_uop_is_unique, // @[issue-slot.scala:73:14]
output io_uop_flush_on_commit, // @[issue-slot.scala:73:14]
output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14]
output io_uop_ldst_val, // @[issue-slot.scala:73:14]
output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
output io_uop_frs3_en, // @[issue-slot.scala:73:14]
output io_uop_fp_val, // @[issue-slot.scala:73:14]
output io_uop_fp_single, // @[issue-slot.scala:73:14]
output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
output io_uop_bp_debug_if, // @[issue-slot.scala:73:14]
output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14]
output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14]
output io_debug_p1, // @[issue-slot.scala:73:14]
output io_debug_p2, // @[issue-slot.scala:73:14]
output io_debug_p3, // @[issue-slot.scala:73:14]
output io_debug_ppred, // @[issue-slot.scala:73:14]
output [1:0] io_debug_state // @[issue-slot.scala:73:14]
);
wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7]
wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7]
wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7]
wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7]
wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7]
wire io_ldspec_miss_0 = io_ldspec_miss; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_3_bits_pdst_0 = io_wakeup_ports_3_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_3_bits_poisoned_0 = io_wakeup_ports_3_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_4_bits_pdst_0 = io_wakeup_ports_4_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_4_bits_poisoned_0 = io_wakeup_ports_4_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_5_valid_0 = io_wakeup_ports_5_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_5_bits_pdst_0 = io_wakeup_ports_5_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_5_bits_poisoned_0 = io_wakeup_ports_5_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_6_valid_0 = io_wakeup_ports_6_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_6_bits_pdst_0 = io_wakeup_ports_6_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_6_bits_poisoned_0 = io_wakeup_ports_6_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-slot.scala:69:7]
wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7]
wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7]
wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7]
wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7]
wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_iw_p1_poisoned_0 = io_in_uop_bits_iw_p1_poisoned; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_iw_p2_poisoned_0 = io_in_uop_bits_iw_p2_poisoned; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7]
wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7]
wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7]
wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7]
wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7]
wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7]
wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7]
wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19]
wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire _io_valid_T; // @[issue-slot.scala:79:24]
wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32]
wire _io_request_hp_T; // @[issue-slot.scala:243:31]
wire [6:0] next_uopc; // @[issue-slot.scala:82:29]
wire [1:0] next_state; // @[issue-slot.scala:81:29]
wire [15:0] next_br_mask; // @[util.scala:85:25]
wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28]
wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28]
wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28]
wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28]
wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29]
wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29]
wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7]
wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7]
wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7]
wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7]
wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7]
wire io_out_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7]
wire io_out_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7]
wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7]
wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7]
wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7]
wire io_out_uop_taken_0; // @[issue-slot.scala:69:7]
wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7]
wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7]
wire io_out_uop_exception_0; // @[issue-slot.scala:69:7]
wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7]
wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7]
wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7]
wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7]
wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7]
wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7]
wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7]
wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7]
wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7]
wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7]
wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7]
wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7]
wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7]
wire io_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7]
wire io_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7]
wire io_uop_is_br_0; // @[issue-slot.scala:69:7]
wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7]
wire io_uop_is_jal_0; // @[issue-slot.scala:69:7]
wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7]
wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7]
wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7]
wire io_uop_taken_0; // @[issue-slot.scala:69:7]
wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7]
wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7]
wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7]
wire io_uop_exception_0; // @[issue-slot.scala:69:7]
wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7]
wire io_uop_bypassable_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7]
wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7]
wire io_uop_is_fence_0; // @[issue-slot.scala:69:7]
wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7]
wire io_uop_is_amo_0; // @[issue-slot.scala:69:7]
wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7]
wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7]
wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7]
wire io_uop_is_unique_0; // @[issue-slot.scala:69:7]
wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7]
wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7]
wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7]
wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7]
wire io_uop_fp_val_0; // @[issue-slot.scala:69:7]
wire io_uop_fp_single_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7]
wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7]
wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7]
wire io_debug_p1_0; // @[issue-slot.scala:69:7]
wire io_debug_p2_0; // @[issue-slot.scala:69:7]
wire io_debug_p3_0; // @[issue-slot.scala:69:7]
wire io_debug_ppred_0; // @[issue-slot.scala:69:7]
wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7]
wire io_valid_0; // @[issue-slot.scala:69:7]
wire io_will_be_valid_0; // @[issue-slot.scala:69:7]
wire io_request_0; // @[issue-slot.scala:69:7]
wire io_request_hp_0; // @[issue-slot.scala:69:7]
assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29]
assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29]
assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29]
assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29]
reg [1:0] state; // @[issue-slot.scala:86:22]
assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22]
reg p1; // @[issue-slot.scala:87:22]
assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22]
wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25]
reg p2; // @[issue-slot.scala:88:22]
assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22]
wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25]
reg p3; // @[issue-slot.scala:89:22]
assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22]
wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25]
reg ppred; // @[issue-slot.scala:90:22]
assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22]
wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28]
reg p1_poisoned; // @[issue-slot.scala:95:28]
assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28]
assign io_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28]
reg p2_poisoned; // @[issue-slot.scala:96:28]
assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28]
assign io_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28]
wire next_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : p1_poisoned; // @[issue-slot.scala:69:7, :95:28, :99:29]
wire next_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : p2_poisoned; // @[issue-slot.scala:69:7, :96:28, :100:29]
reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25]
reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25]
reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_rvc; // @[issue-slot.scala:102:25]
assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25]
reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25]
assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25]
reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25]
assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25]
assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25]
reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25]
reg slot_uop_is_br; // @[issue-slot.scala:102:25]
assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_jalr; // @[issue-slot.scala:102:25]
assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_jal; // @[issue-slot.scala:102:25]
assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_sfb; // @[issue-slot.scala:102:25]
assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25]
reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25]
assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25]
assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_edge_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25]
assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_taken; // @[issue-slot.scala:102:25]
assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25]
reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25]
assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25]
reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25]
assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25]
assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25]
assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25]
assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25]
assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25]
assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25]
assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25]
assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_exception; // @[issue-slot.scala:102:25]
assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25]
reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25]
assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bypassable; // @[issue-slot.scala:102:25]
assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_mem_signed; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_fence; // @[issue-slot.scala:102:25]
assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_fencei; // @[issue-slot.scala:102:25]
assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_amo; // @[issue-slot.scala:102:25]
assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25]
assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_uses_stq; // @[issue-slot.scala:102:25]
assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25]
assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_unique; // @[issue-slot.scala:102:25]
assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25]
assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ldst_val; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25]
assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25]
reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25]
reg slot_uop_frs3_en; // @[issue-slot.scala:102:25]
assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_fp_val; // @[issue-slot.scala:102:25]
assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_fp_single; // @[issue-slot.scala:102:25]
assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25]
assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25]
assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25]
wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_iw_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_iw_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25]
wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}]
wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25]
wire _T_14 = io_ldspec_miss_0 & (p1_poisoned | p2_poisoned); // @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}]
wire _GEN = _T_12 & ~_T_14; // @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18]
wire _GEN_0 = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51]
wire _GEN_1 = _GEN_0 | ~(_T_12 & ~_T_14 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23]
assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51]
assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51]
wire _GEN_2 = _GEN_0 | ~_GEN | p1; // @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17]
assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17]
wire _p1_T = ~io_in_uop_bits_prs1_busy_0; // @[issue-slot.scala:69:7, :169:11]
wire _p2_T = ~io_in_uop_bits_prs2_busy_0; // @[issue-slot.scala:69:7, :170:11]
wire _p3_T = ~io_in_uop_bits_prs3_busy_0; // @[issue-slot.scala:69:7, :171:11]
wire _ppred_T = ~io_in_uop_bits_ppred_busy_0; // @[issue-slot.scala:69:7, :172:14]
wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned; // @[issue-slot.scala:69:7, :99:29, :175:24]
wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned; // @[issue-slot.scala:69:7, :100:29, :179:24]
wire _T_85 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27]
wire _T_93 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27] |
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_55 :
input clock : Clock
input reset : Reset
output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, flip grant : UInt<1>, iss_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip in_uop : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}, out_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip kill : UInt<1>, flip clear : UInt<1>, flip squash_grant : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}}[5], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip child_rebusys : UInt<3>}
regreset slot_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg slot_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, clock
wire next_valid : UInt<1>
connect next_valid, slot_valid
wire next_uop_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}
connect next_uop_out, slot_uop
node _next_uop_out_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _next_uop_out_br_mask_T_1 = and(slot_uop.br_mask, _next_uop_out_br_mask_T)
connect next_uop_out.br_mask, _next_uop_out_br_mask_T_1
wire next_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}
connect next_uop, next_uop_out
node _killed_T = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask)
node _killed_T_1 = neq(_killed_T, UInt<1>(0h0))
node killed = or(_killed_T_1, io.kill)
connect io.valid, slot_valid
connect io.out_uop, next_uop
node _io_will_be_valid_T = eq(killed, UInt<1>(0h0))
node _io_will_be_valid_T_1 = and(next_valid, _io_will_be_valid_T)
connect io.will_be_valid, _io_will_be_valid_T_1
when io.kill :
connect slot_valid, UInt<1>(0h0)
else :
when io.in_uop.valid :
connect slot_valid, UInt<1>(0h1)
else :
when io.clear :
connect slot_valid, UInt<1>(0h0)
else :
node _slot_valid_T = eq(killed, UInt<1>(0h0))
node _slot_valid_T_1 = and(next_valid, _slot_valid_T)
connect slot_valid, _slot_valid_T_1
when io.in_uop.valid :
connect slot_uop, io.in_uop.bits
node _T = eq(slot_valid, UInt<1>(0h0))
node _T_1 = or(_T, io.clear)
node _T_2 = or(_T_1, io.kill)
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:79 assert (!slot_valid || io.clear || io.kill)\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
else :
connect slot_uop, next_uop
connect next_uop.iw_p1_bypass_hint, UInt<1>(0h0)
connect next_uop.iw_p2_bypass_hint, UInt<1>(0h0)
connect next_uop.iw_p3_bypass_hint, UInt<1>(0h0)
connect next_uop.iw_p1_speculative_child, UInt<1>(0h0)
connect next_uop.iw_p2_speculative_child, UInt<1>(0h0)
wire rebusied_prs1 : UInt<1>
connect rebusied_prs1, UInt<1>(0h0)
wire rebusied_prs2 : UInt<1>
connect rebusied_prs2, UInt<1>(0h0)
node rebusied = or(rebusied_prs1, rebusied_prs2)
node prs1_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs1)
node prs1_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs1)
node prs1_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs1)
node prs1_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs1)
node prs1_matches_4 = eq(io.wakeup_ports[4].bits.uop.pdst, slot_uop.prs1)
node prs2_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs2)
node prs2_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs2)
node prs2_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs2)
node prs2_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs2)
node prs2_matches_4 = eq(io.wakeup_ports[4].bits.uop.pdst, slot_uop.prs2)
node prs3_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs3)
node prs3_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs3)
node prs3_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs3)
node prs3_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs3)
node prs3_matches_4 = eq(io.wakeup_ports[4].bits.uop.pdst, slot_uop.prs3)
node prs1_wakeups_0 = and(io.wakeup_ports[0].valid, prs1_matches_0)
node prs1_wakeups_1 = and(io.wakeup_ports[1].valid, prs1_matches_1)
node prs1_wakeups_2 = and(io.wakeup_ports[2].valid, prs1_matches_2)
node prs1_wakeups_3 = and(io.wakeup_ports[3].valid, prs1_matches_3)
node prs1_wakeups_4 = and(io.wakeup_ports[4].valid, prs1_matches_4)
node prs2_wakeups_0 = and(io.wakeup_ports[0].valid, prs2_matches_0)
node prs2_wakeups_1 = and(io.wakeup_ports[1].valid, prs2_matches_1)
node prs2_wakeups_2 = and(io.wakeup_ports[2].valid, prs2_matches_2)
node prs2_wakeups_3 = and(io.wakeup_ports[3].valid, prs2_matches_3)
node prs2_wakeups_4 = and(io.wakeup_ports[4].valid, prs2_matches_4)
node prs3_wakeups_0 = and(io.wakeup_ports[0].valid, prs3_matches_0)
node prs3_wakeups_1 = and(io.wakeup_ports[1].valid, prs3_matches_1)
node prs3_wakeups_2 = and(io.wakeup_ports[2].valid, prs3_matches_2)
node prs3_wakeups_3 = and(io.wakeup_ports[3].valid, prs3_matches_3)
node prs3_wakeups_4 = and(io.wakeup_ports[4].valid, prs3_matches_4)
node prs1_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs1_matches_0)
node prs1_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs1_matches_1)
node prs1_rebusys_2 = and(io.wakeup_ports[2].bits.rebusy, prs1_matches_2)
node prs1_rebusys_3 = and(io.wakeup_ports[3].bits.rebusy, prs1_matches_3)
node prs1_rebusys_4 = and(io.wakeup_ports[4].bits.rebusy, prs1_matches_4)
node prs2_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs2_matches_0)
node prs2_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs2_matches_1)
node prs2_rebusys_2 = and(io.wakeup_ports[2].bits.rebusy, prs2_matches_2)
node prs2_rebusys_3 = and(io.wakeup_ports[3].bits.rebusy, prs2_matches_3)
node prs2_rebusys_4 = and(io.wakeup_ports[4].bits.rebusy, prs2_matches_4)
node _T_6 = or(prs1_wakeups_0, prs1_wakeups_1)
node _T_7 = or(_T_6, prs1_wakeups_2)
node _T_8 = or(_T_7, prs1_wakeups_3)
node _T_9 = or(_T_8, prs1_wakeups_4)
when _T_9 :
connect next_uop.prs1_busy, UInt<1>(0h0)
node _next_uop_iw_p1_speculative_child_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_2 = mux(prs1_wakeups_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_3 = mux(prs1_wakeups_3, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_4 = mux(prs1_wakeups_4, io.wakeup_ports[4].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_5 = or(_next_uop_iw_p1_speculative_child_T, _next_uop_iw_p1_speculative_child_T_1)
node _next_uop_iw_p1_speculative_child_T_6 = or(_next_uop_iw_p1_speculative_child_T_5, _next_uop_iw_p1_speculative_child_T_2)
node _next_uop_iw_p1_speculative_child_T_7 = or(_next_uop_iw_p1_speculative_child_T_6, _next_uop_iw_p1_speculative_child_T_3)
node _next_uop_iw_p1_speculative_child_T_8 = or(_next_uop_iw_p1_speculative_child_T_7, _next_uop_iw_p1_speculative_child_T_4)
wire _next_uop_iw_p1_speculative_child_WIRE : UInt<3>
connect _next_uop_iw_p1_speculative_child_WIRE, _next_uop_iw_p1_speculative_child_T_8
connect next_uop.iw_p1_speculative_child, _next_uop_iw_p1_speculative_child_WIRE
node _next_uop_iw_p1_bypass_hint_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_2 = mux(prs1_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_3 = mux(prs1_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_4 = mux(prs1_wakeups_4, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_5 = or(_next_uop_iw_p1_bypass_hint_T, _next_uop_iw_p1_bypass_hint_T_1)
node _next_uop_iw_p1_bypass_hint_T_6 = or(_next_uop_iw_p1_bypass_hint_T_5, _next_uop_iw_p1_bypass_hint_T_2)
node _next_uop_iw_p1_bypass_hint_T_7 = or(_next_uop_iw_p1_bypass_hint_T_6, _next_uop_iw_p1_bypass_hint_T_3)
node _next_uop_iw_p1_bypass_hint_T_8 = or(_next_uop_iw_p1_bypass_hint_T_7, _next_uop_iw_p1_bypass_hint_T_4)
wire _next_uop_iw_p1_bypass_hint_WIRE : UInt<1>
connect _next_uop_iw_p1_bypass_hint_WIRE, _next_uop_iw_p1_bypass_hint_T_8
connect next_uop.iw_p1_bypass_hint, _next_uop_iw_p1_bypass_hint_WIRE
node _T_10 = or(prs1_rebusys_0, prs1_rebusys_1)
node _T_11 = or(_T_10, prs1_rebusys_2)
node _T_12 = or(_T_11, prs1_rebusys_3)
node _T_13 = or(_T_12, prs1_rebusys_4)
node _T_14 = and(io.child_rebusys, slot_uop.iw_p1_speculative_child)
node _T_15 = neq(_T_14, UInt<1>(0h0))
node _T_16 = or(_T_13, _T_15)
node _T_17 = eq(slot_uop.lrs1_rtype, UInt<2>(0h0))
node _T_18 = and(_T_16, _T_17)
when _T_18 :
connect next_uop.prs1_busy, UInt<1>(0h1)
connect rebusied_prs1, UInt<1>(0h1)
node _T_19 = or(prs2_wakeups_0, prs2_wakeups_1)
node _T_20 = or(_T_19, prs2_wakeups_2)
node _T_21 = or(_T_20, prs2_wakeups_3)
node _T_22 = or(_T_21, prs2_wakeups_4)
when _T_22 :
connect next_uop.prs2_busy, UInt<1>(0h0)
node _next_uop_iw_p2_speculative_child_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_2 = mux(prs2_wakeups_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_3 = mux(prs2_wakeups_3, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_4 = mux(prs2_wakeups_4, io.wakeup_ports[4].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_5 = or(_next_uop_iw_p2_speculative_child_T, _next_uop_iw_p2_speculative_child_T_1)
node _next_uop_iw_p2_speculative_child_T_6 = or(_next_uop_iw_p2_speculative_child_T_5, _next_uop_iw_p2_speculative_child_T_2)
node _next_uop_iw_p2_speculative_child_T_7 = or(_next_uop_iw_p2_speculative_child_T_6, _next_uop_iw_p2_speculative_child_T_3)
node _next_uop_iw_p2_speculative_child_T_8 = or(_next_uop_iw_p2_speculative_child_T_7, _next_uop_iw_p2_speculative_child_T_4)
wire _next_uop_iw_p2_speculative_child_WIRE : UInt<3>
connect _next_uop_iw_p2_speculative_child_WIRE, _next_uop_iw_p2_speculative_child_T_8
connect next_uop.iw_p2_speculative_child, _next_uop_iw_p2_speculative_child_WIRE
node _next_uop_iw_p2_bypass_hint_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_2 = mux(prs2_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_3 = mux(prs2_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_4 = mux(prs2_wakeups_4, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_5 = or(_next_uop_iw_p2_bypass_hint_T, _next_uop_iw_p2_bypass_hint_T_1)
node _next_uop_iw_p2_bypass_hint_T_6 = or(_next_uop_iw_p2_bypass_hint_T_5, _next_uop_iw_p2_bypass_hint_T_2)
node _next_uop_iw_p2_bypass_hint_T_7 = or(_next_uop_iw_p2_bypass_hint_T_6, _next_uop_iw_p2_bypass_hint_T_3)
node _next_uop_iw_p2_bypass_hint_T_8 = or(_next_uop_iw_p2_bypass_hint_T_7, _next_uop_iw_p2_bypass_hint_T_4)
wire _next_uop_iw_p2_bypass_hint_WIRE : UInt<1>
connect _next_uop_iw_p2_bypass_hint_WIRE, _next_uop_iw_p2_bypass_hint_T_8
connect next_uop.iw_p2_bypass_hint, _next_uop_iw_p2_bypass_hint_WIRE
node _T_23 = or(prs2_rebusys_0, prs2_rebusys_1)
node _T_24 = or(_T_23, prs2_rebusys_2)
node _T_25 = or(_T_24, prs2_rebusys_3)
node _T_26 = or(_T_25, prs2_rebusys_4)
node _T_27 = and(io.child_rebusys, slot_uop.iw_p2_speculative_child)
node _T_28 = neq(_T_27, UInt<1>(0h0))
node _T_29 = or(_T_26, _T_28)
node _T_30 = eq(slot_uop.lrs2_rtype, UInt<2>(0h0))
node _T_31 = and(_T_29, _T_30)
when _T_31 :
connect next_uop.prs2_busy, UInt<1>(0h1)
connect rebusied_prs2, UInt<1>(0h1)
node _T_32 = or(prs3_wakeups_0, prs3_wakeups_1)
node _T_33 = or(_T_32, prs3_wakeups_2)
node _T_34 = or(_T_33, prs3_wakeups_3)
node _T_35 = or(_T_34, prs3_wakeups_4)
when _T_35 :
connect next_uop.prs3_busy, UInt<1>(0h0)
node _next_uop_iw_p3_bypass_hint_T = mux(prs3_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_1 = mux(prs3_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_2 = mux(prs3_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_3 = mux(prs3_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_4 = mux(prs3_wakeups_4, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_5 = or(_next_uop_iw_p3_bypass_hint_T, _next_uop_iw_p3_bypass_hint_T_1)
node _next_uop_iw_p3_bypass_hint_T_6 = or(_next_uop_iw_p3_bypass_hint_T_5, _next_uop_iw_p3_bypass_hint_T_2)
node _next_uop_iw_p3_bypass_hint_T_7 = or(_next_uop_iw_p3_bypass_hint_T_6, _next_uop_iw_p3_bypass_hint_T_3)
node _next_uop_iw_p3_bypass_hint_T_8 = or(_next_uop_iw_p3_bypass_hint_T_7, _next_uop_iw_p3_bypass_hint_T_4)
wire _next_uop_iw_p3_bypass_hint_WIRE : UInt<1>
connect _next_uop_iw_p3_bypass_hint_WIRE, _next_uop_iw_p3_bypass_hint_T_8
connect next_uop.iw_p3_bypass_hint, _next_uop_iw_p3_bypass_hint_WIRE
node _T_36 = eq(io.pred_wakeup_port.bits, slot_uop.ppred)
node _T_37 = and(io.pred_wakeup_port.valid, _T_36)
when _T_37 :
connect next_uop.ppred_busy, UInt<1>(0h0)
node _iss_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0))
node _iss_ready_T_1 = eq(slot_uop.prs2_busy, UInt<1>(0h0))
node _iss_ready_T_2 = and(_iss_ready_T, _iss_ready_T_1)
node _iss_ready_T_3 = and(slot_uop.ppred_busy, UInt<1>(0h1))
node _iss_ready_T_4 = eq(_iss_ready_T_3, UInt<1>(0h0))
node _iss_ready_T_5 = and(_iss_ready_T_2, _iss_ready_T_4)
node _iss_ready_T_6 = and(slot_uop.prs3_busy, UInt<1>(0h0))
node _iss_ready_T_7 = eq(_iss_ready_T_6, UInt<1>(0h0))
node iss_ready = and(_iss_ready_T_5, _iss_ready_T_7)
node _agen_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0))
node _agen_ready_T_1 = and(slot_uop.fu_code[1], _agen_ready_T)
node _agen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1))
node _agen_ready_T_3 = eq(_agen_ready_T_2, UInt<1>(0h0))
node _agen_ready_T_4 = and(_agen_ready_T_1, _agen_ready_T_3)
node agen_ready = and(_agen_ready_T_4, UInt<1>(0h0))
node _dgen_ready_T = eq(slot_uop.prs2_busy, UInt<1>(0h0))
node _dgen_ready_T_1 = and(slot_uop.fu_code[2], _dgen_ready_T)
node _dgen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1))
node _dgen_ready_T_3 = eq(_dgen_ready_T_2, UInt<1>(0h0))
node _dgen_ready_T_4 = and(_dgen_ready_T_1, _dgen_ready_T_3)
node dgen_ready = and(_dgen_ready_T_4, UInt<1>(0h0))
node _io_request_T = eq(slot_uop.iw_issued, UInt<1>(0h0))
node _io_request_T_1 = and(slot_valid, _io_request_T)
node _io_request_T_2 = or(iss_ready, agen_ready)
node _io_request_T_3 = or(_io_request_T_2, dgen_ready)
node _io_request_T_4 = and(_io_request_T_1, _io_request_T_3)
connect io.request, _io_request_T_4
connect io.iss_uop, slot_uop
connect next_uop.iw_issued, UInt<1>(0h0)
connect next_uop.iw_issued_partial_agen, UInt<1>(0h0)
connect next_uop.iw_issued_partial_dgen, UInt<1>(0h0)
node _T_38 = eq(io.squash_grant, UInt<1>(0h0))
node _T_39 = and(io.grant, _T_38)
when _T_39 :
connect next_uop.iw_issued, UInt<1>(0h1)
node _T_40 = and(slot_valid, slot_uop.iw_issued)
when _T_40 :
connect next_valid, rebusied | module IssueSlot_55( // @[issue-slot.scala:49:7]
input clock, // @[issue-slot.scala:49:7]
input reset, // @[issue-slot.scala:49:7]
output io_valid, // @[issue-slot.scala:52:14]
output io_will_be_valid, // @[issue-slot.scala:52:14]
output io_request, // @[issue-slot.scala:52:14]
input io_grant, // @[issue-slot.scala:52:14]
output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14]
output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14]
output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14]
output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14]
output [15:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14]
output io_iss_uop_is_fence, // @[issue-slot.scala:52:14]
output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14]
output io_iss_uop_is_amo, // @[issue-slot.scala:52:14]
output io_iss_uop_is_eret, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14]
output io_iss_uop_is_mov, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14]
output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14]
output io_iss_uop_taken, // @[issue-slot.scala:52:14]
output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14]
output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14]
output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14]
output io_iss_uop_exception, // @[issue-slot.scala:52:14]
output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14]
output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14]
output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14]
output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14]
output io_iss_uop_is_unique, // @[issue-slot.scala:52:14]
output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14]
output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14]
output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_val, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14]
output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_in_uop_valid, // @[issue-slot.scala:52:14]
input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14]
input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14]
input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14]
input io_in_uop_bits_taken, // @[issue-slot.scala:52:14]
input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_exception, // @[issue-slot.scala:52:14]
input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14]
input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14]
input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14]
input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14]
input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14]
input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14]
output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14]
output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14]
output io_out_uop_is_rvc, // @[issue-slot.scala:52:14]
output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14]
output io_out_uop_iw_issued, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14]
output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14]
output io_out_uop_is_sfb, // @[issue-slot.scala:52:14]
output io_out_uop_is_fence, // @[issue-slot.scala:52:14]
output io_out_uop_is_fencei, // @[issue-slot.scala:52:14]
output io_out_uop_is_sfence, // @[issue-slot.scala:52:14]
output io_out_uop_is_amo, // @[issue-slot.scala:52:14]
output io_out_uop_is_eret, // @[issue-slot.scala:52:14]
output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
output io_out_uop_is_rocc, // @[issue-slot.scala:52:14]
output io_out_uop_is_mov, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14]
output io_out_uop_edge_inst, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14]
output io_out_uop_taken, // @[issue-slot.scala:52:14]
output io_out_uop_imm_rename, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14]
output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14]
output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14]
output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14]
output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14]
output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14]
output io_out_uop_exception, // @[issue-slot.scala:52:14]
output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14]
output io_out_uop_mem_signed, // @[issue-slot.scala:52:14]
output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14]
output io_out_uop_uses_stq, // @[issue-slot.scala:52:14]
output io_out_uop_is_unique, // @[issue-slot.scala:52:14]
output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14]
output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
output io_out_uop_frs3_en, // @[issue-slot.scala:52:14]
output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14]
output io_out_uop_fp_val, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14]
output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14]
input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14]
input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14]
input io_brupdate_b2_taken, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14]
input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14]
input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14]
input io_kill, // @[issue-slot.scala:52:14]
input io_clear, // @[issue-slot.scala:52:14]
input io_squash_grant, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_bypassable, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_speculative_mask, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_rebusy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_2_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_2_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_2_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_2_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_2_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_2_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_2_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_2_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_3_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_3_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_3_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_3_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_3_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_3_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_3_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_3_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_4_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_4_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_4_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_4_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_4_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_4_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_4_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_4_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input [2:0] io_child_rebusys // @[issue-slot.scala:52:14]
);
wire [15:0] next_uop_out_br_mask; // @[util.scala:104:23]
wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7]
wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_iw_p1_speculative_child_0 = io_in_uop_bits_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_iw_p2_speculative_child_0 = io_in_uop_bits_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7]
wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7]
wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7]
wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7]
wire io_clear_0 = io_clear; // @[issue-slot.scala:49:7]
wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_4_bits_uop_inst_0 = io_wakeup_ports_4_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_4_bits_uop_debug_inst_0 = io_wakeup_ports_4_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_rvc_0 = io_wakeup_ports_4_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_4_bits_uop_debug_pc_0 = io_wakeup_ports_4_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iq_type_0_0 = io_wakeup_ports_4_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iq_type_1_0 = io_wakeup_ports_4_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iq_type_2_0 = io_wakeup_ports_4_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iq_type_3_0 = io_wakeup_ports_4_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_0_0 = io_wakeup_ports_4_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_1_0 = io_wakeup_ports_4_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_2_0 = io_wakeup_ports_4_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_3_0 = io_wakeup_ports_4_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_4_0 = io_wakeup_ports_4_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_5_0 = io_wakeup_ports_4_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_6_0 = io_wakeup_ports_4_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_7_0 = io_wakeup_ports_4_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_8_0 = io_wakeup_ports_4_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_9_0 = io_wakeup_ports_4_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_issued_0 = io_wakeup_ports_4_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel_0 = io_wakeup_ports_4_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_4_bits_uop_br_mask_0 = io_wakeup_ports_4_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_4_bits_uop_br_tag_0 = io_wakeup_ports_4_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_4_bits_uop_br_type_0 = io_wakeup_ports_4_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_sfb_0 = io_wakeup_ports_4_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_fence_0 = io_wakeup_ports_4_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_fencei_0 = io_wakeup_ports_4_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_sfence_0 = io_wakeup_ports_4_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_amo_0 = io_wakeup_ports_4_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_eret_0 = io_wakeup_ports_4_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_4_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_rocc_0 = io_wakeup_ports_4_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_mov_0 = io_wakeup_ports_4_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_ftq_idx_0 = io_wakeup_ports_4_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_edge_inst_0 = io_wakeup_ports_4_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_pc_lob_0 = io_wakeup_ports_4_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_taken_0 = io_wakeup_ports_4_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_imm_rename_0 = io_wakeup_ports_4_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_imm_sel_0 = io_wakeup_ports_4_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_pimm_0 = io_wakeup_ports_4_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_4_bits_uop_imm_packed_0 = io_wakeup_ports_4_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_op1_sel_0 = io_wakeup_ports_4_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_op2_sel_0 = io_wakeup_ports_4_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_rob_idx_0 = io_wakeup_ports_4_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_ldq_idx_0 = io_wakeup_ports_4_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_stq_idx_0 = io_wakeup_ports_4_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_rxq_idx_0 = io_wakeup_ports_4_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_pdst_0 = io_wakeup_ports_4_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_prs1_0 = io_wakeup_ports_4_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_prs2_0 = io_wakeup_ports_4_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_prs3_0 = io_wakeup_ports_4_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_ppred_0 = io_wakeup_ports_4_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_prs1_busy_0 = io_wakeup_ports_4_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_prs2_busy_0 = io_wakeup_ports_4_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_prs3_busy_0 = io_wakeup_ports_4_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_ppred_busy_0 = io_wakeup_ports_4_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_stale_pdst_0 = io_wakeup_ports_4_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_exception_0 = io_wakeup_ports_4_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_4_bits_uop_exc_cause_0 = io_wakeup_ports_4_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_mem_cmd_0 = io_wakeup_ports_4_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_mem_size_0 = io_wakeup_ports_4_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_mem_signed_0 = io_wakeup_ports_4_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_uses_ldq_0 = io_wakeup_ports_4_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_uses_stq_0 = io_wakeup_ports_4_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_unique_0 = io_wakeup_ports_4_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_flush_on_commit_0 = io_wakeup_ports_4_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_csr_cmd_0 = io_wakeup_ports_4_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_4_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_ldst_0 = io_wakeup_ports_4_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_lrs1_0 = io_wakeup_ports_4_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_lrs2_0 = io_wakeup_ports_4_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_lrs3_0 = io_wakeup_ports_4_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_dst_rtype_0 = io_wakeup_ports_4_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype_0 = io_wakeup_ports_4_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype_0 = io_wakeup_ports_4_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_frs3_en_0 = io_wakeup_ports_4_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fcn_dw_0 = io_wakeup_ports_4_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_fcn_op_0 = io_wakeup_ports_4_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_val_0 = io_wakeup_ports_4_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_fp_rm_0 = io_wakeup_ports_4_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_fp_typ_0 = io_wakeup_ports_4_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_4_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_bp_debug_if_0 = io_wakeup_ports_4_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_4_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc_0 = io_wakeup_ports_4_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc_0 = io_wakeup_ports_4_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_child_rebusys_0 = io_child_rebusys; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued = 1'h0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_ppred_busy = 1'h0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:49:7]
wire next_uop_out_iw_issued_partial_agen = 1'h0; // @[util.scala:104:23]
wire next_uop_out_iw_issued_partial_dgen = 1'h0; // @[util.scala:104:23]
wire next_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:59:28]
wire next_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:59:28]
wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91]
wire prs1_rebusys_2 = 1'h0; // @[issue-slot.scala:102:91]
wire prs1_rebusys_3 = 1'h0; // @[issue-slot.scala:102:91]
wire prs1_rebusys_4 = 1'h0; // @[issue-slot.scala:102:91]
wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91]
wire prs2_rebusys_2 = 1'h0; // @[issue-slot.scala:103:91]
wire prs2_rebusys_3 = 1'h0; // @[issue-slot.scala:103:91]
wire prs2_rebusys_4 = 1'h0; // @[issue-slot.scala:103:91]
wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _iss_ready_T_6 = 1'h0; // @[issue-slot.scala:136:131]
wire agen_ready = 1'h0; // @[issue-slot.scala:137:114]
wire dgen_ready = 1'h0; // @[issue-slot.scala:138:114]
wire [2:0] io_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-slot.scala:49:7]
wire [2:0] _next_uop_iw_p1_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _next_uop_iw_p2_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73]
wire io_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7]
wire _iss_ready_T_7 = 1'h1; // @[issue-slot.scala:136:110]
wire [2:0] io_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-slot.scala:49:7]
wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:49:7]
wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34]
wire _io_request_T_4; // @[issue-slot.scala:140:51]
wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28]
wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28]
wire next_uop_is_rvc; // @[issue-slot.scala:59:28]
wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_0; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_1; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_2; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_3; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_0; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_1; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_2; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_3; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_4; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_5; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_6; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_7; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_8; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_9; // @[issue-slot.scala:59:28]
wire next_uop_iw_issued; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_iw_p1_speculative_child; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_iw_p2_speculative_child; // @[issue-slot.scala:59:28]
wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28]
wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28]
wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28]
wire [15:0] next_uop_br_mask; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28]
wire next_uop_is_sfb; // @[issue-slot.scala:59:28]
wire next_uop_is_fence; // @[issue-slot.scala:59:28]
wire next_uop_is_fencei; // @[issue-slot.scala:59:28]
wire next_uop_is_sfence; // @[issue-slot.scala:59:28]
wire next_uop_is_amo; // @[issue-slot.scala:59:28]
wire next_uop_is_eret; // @[issue-slot.scala:59:28]
wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28]
wire next_uop_is_rocc; // @[issue-slot.scala:59:28]
wire next_uop_is_mov; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28]
wire next_uop_edge_inst; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28]
wire next_uop_taken; // @[issue-slot.scala:59:28]
wire next_uop_imm_rename; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28]
wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_rob_idx; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_stq_idx; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28]
wire next_uop_prs1_busy; // @[issue-slot.scala:59:28]
wire next_uop_prs2_busy; // @[issue-slot.scala:59:28]
wire next_uop_prs3_busy; // @[issue-slot.scala:59:28]
wire next_uop_ppred_busy; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28]
wire next_uop_exception; // @[issue-slot.scala:59:28]
wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28]
wire next_uop_mem_signed; // @[issue-slot.scala:59:28]
wire next_uop_uses_ldq; // @[issue-slot.scala:59:28]
wire next_uop_uses_stq; // @[issue-slot.scala:59:28]
wire next_uop_is_unique; // @[issue-slot.scala:59:28]
wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28]
wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28]
wire next_uop_frs3_en; // @[issue-slot.scala:59:28]
wire next_uop_fcn_dw; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28]
wire next_uop_fp_val; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28]
wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28]
wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28]
wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7]
wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7]
wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7]
wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7]
wire [15:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7]
wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs2_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7]
wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7]
wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7]
wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7]
wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7]
wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7]
wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7]
wire io_out_uop_taken_0; // @[issue-slot.scala:49:7]
wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7]
wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_exception_0; // @[issue-slot.scala:49:7]
wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7]
wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7]
wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7]
wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7]
wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7]
wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7]
wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7]
wire io_valid_0; // @[issue-slot.scala:49:7]
wire io_will_be_valid_0; // @[issue-slot.scala:49:7]
wire io_request_0; // @[issue-slot.scala:49:7]
reg slot_valid; // @[issue-slot.scala:55:27]
assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27]
reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21]
wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23]
reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21]
wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23]
reg slot_uop_is_rvc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23]
reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21]
wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23]
reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23]
reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23]
reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23]
reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23]
reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23]
reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_1_0 = slot_uop_fu_code_1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23]
reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_2_0 = slot_uop_fu_code_2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23]
reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23]
reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23]
reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23]
reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23]
reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23]
reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23]
reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23]
reg slot_uop_iw_issued; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23]
reg [2:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23]
reg [2:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23]
reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p1_bypass_hint_0 = slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23]
reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23]
reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23]
reg [2:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23]
reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21]
reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23]
reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23]
reg slot_uop_is_sfb; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23]
reg slot_uop_is_fence; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23]
reg slot_uop_is_fencei; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23]
reg slot_uop_is_sfence; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23]
reg slot_uop_is_amo; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23]
reg slot_uop_is_eret; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23]
reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23]
reg slot_uop_is_rocc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23]
reg slot_uop_is_mov; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23]
reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23]
reg slot_uop_edge_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23]
reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21]
assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23]
reg slot_uop_taken; // @[issue-slot.scala:56:21]
assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23]
reg slot_uop_imm_rename; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23]
reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_sel_0 = slot_uop_imm_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23]
reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21]
assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23]
reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21]
wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23]
reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23]
reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23]
reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23]
reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23]
reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23]
reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23]
reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21]
assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23]
reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23]
reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23]
reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23]
reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21]
assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23]
reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23]
reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23]
reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23]
reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23]
wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88]
wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95]
wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95]
reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21]
assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23]
reg slot_uop_exception; // @[issue-slot.scala:56:21]
assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23]
reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21]
assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21]
wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23]
reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23]
reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23]
reg slot_uop_mem_signed; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23]
reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21]
assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23]
reg slot_uop_uses_stq; // @[issue-slot.scala:56:21]
assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23]
reg slot_uop_is_unique; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23]
reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21]
assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23]
reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21]
assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23]
reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23]
reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23]
reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23]
reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs1_rtype_0 = slot_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23]
reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs2_rtype_0 = slot_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23]
reg slot_uop_frs3_en; // @[issue-slot.scala:56:21]
assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23]
reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21]
assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23]
reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21]
assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23]
reg slot_uop_fp_val; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23]
reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23]
reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23]
reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23]
reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23]
reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23]
reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23]
reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23]
reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23]
wire next_valid; // @[issue-slot.scala:58:28]
assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23]
assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23]
assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23]
assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23]
assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23]
assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23]
assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23]
assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23]
assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23]
assign next_uop_fu_code_1 = next_uop_out_fu_code_1; // @[util.scala:104:23]
assign next_uop_fu_code_2 = next_uop_out_fu_code_2; // @[util.scala:104:23]
assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23]
assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23]
assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23]
assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23]
assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23]
assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23]
assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23]
wire [15:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25]
assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23]
assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23]
assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23]
assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23]
assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23]
assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23]
assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23]
assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23]
assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23]
assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23]
assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23]
assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23]
assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23]
assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23]
assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23]
assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23]
assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23]
assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23]
assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23]
assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23]
assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23]
assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23]
assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23]
assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23]
assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23]
assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23]
assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23]
assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23]
assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23]
assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23]
assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23]
assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23]
assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23]
assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23]
assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23]
assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23]
assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23]
assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23]
assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23]
assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23]
assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23]
assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23]
assign next_uop_ppred_busy = next_uop_out_ppred_busy; // @[util.scala:104:23]
assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23]
assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23]
assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23]
assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23]
assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23]
assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23]
assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23]
assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23]
assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23]
assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23]
assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23]
assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23]
assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23]
assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23]
assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23]
assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23]
assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23]
assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23]
assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23]
assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23]
assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23]
assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23]
assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23]
assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23]
assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23]
assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23]
assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23]
assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23]
assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23]
assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23]
assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23]
assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23]
wire [15:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27]
assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}]
assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23]
assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p1_speculative_child_0 = next_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p2_speculative_child_0 = next_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28]
wire [15:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51]
wire _killed_T_1 = |_killed_T; // @[util.scala:126:{51,59}]
wire killed = _killed_T_1 | io_kill_0; // @[util.scala:61:61, :126:59]
wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61]
assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}]
assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34]
wire _slot_valid_T = ~killed; // @[util.scala:61:61]
wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}] |
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFN_e8_s24_48 :
output io : { flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
inst mulAddRecFNToRaw_preMul of MulAddRecFNToRaw_preMul_e8_s24_48
inst mulAddRecFNToRaw_postMul of MulAddRecFNToRaw_postMul_e8_s24_48
connect mulAddRecFNToRaw_preMul.io.op, io.op
connect mulAddRecFNToRaw_preMul.io.a, io.a
connect mulAddRecFNToRaw_preMul.io.b, io.b
connect mulAddRecFNToRaw_preMul.io.c, io.c
node _mulAddResult_T = mul(mulAddRecFNToRaw_preMul.io.mulAddA, mulAddRecFNToRaw_preMul.io.mulAddB)
node mulAddResult = add(_mulAddResult_T, mulAddRecFNToRaw_preMul.io.mulAddC)
connect mulAddRecFNToRaw_postMul.io.fromPreMul.bit0AlignedSigC, mulAddRecFNToRaw_preMul.io.toPostMul.bit0AlignedSigC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.highAlignedSigC, mulAddRecFNToRaw_preMul.io.toPostMul.highAlignedSigC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.CDom_CAlignDist, mulAddRecFNToRaw_preMul.io.toPostMul.CDom_CAlignDist
connect mulAddRecFNToRaw_postMul.io.fromPreMul.CIsDominant, mulAddRecFNToRaw_preMul.io.toPostMul.CIsDominant
connect mulAddRecFNToRaw_postMul.io.fromPreMul.doSubMags, mulAddRecFNToRaw_preMul.io.toPostMul.doSubMags
connect mulAddRecFNToRaw_postMul.io.fromPreMul.sExpSum, mulAddRecFNToRaw_preMul.io.toPostMul.sExpSum
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroC, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfC, mulAddRecFNToRaw_preMul.io.toPostMul.isInfC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNC, mulAddRecFNToRaw_preMul.io.toPostMul.isNaNC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.signProd, mulAddRecFNToRaw_preMul.io.toPostMul.signProd
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroB, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroB
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfB, mulAddRecFNToRaw_preMul.io.toPostMul.isInfB
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroA, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroA
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfA, mulAddRecFNToRaw_preMul.io.toPostMul.isInfA
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNAOrB, mulAddRecFNToRaw_preMul.io.toPostMul.isNaNAOrB
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isSigNaNAny, mulAddRecFNToRaw_preMul.io.toPostMul.isSigNaNAny
connect mulAddRecFNToRaw_postMul.io.mulAddResult, mulAddResult
connect mulAddRecFNToRaw_postMul.io.roundingMode, io.roundingMode
inst roundRawFNToRecFN of RoundRawFNToRecFN_e8_s24_68
connect roundRawFNToRecFN.io.invalidExc, mulAddRecFNToRaw_postMul.io.invalidExc
connect roundRawFNToRecFN.io.infiniteExc, UInt<1>(0h0)
connect roundRawFNToRecFN.io.in.sig, mulAddRecFNToRaw_postMul.io.rawOut.sig
connect roundRawFNToRecFN.io.in.sExp, mulAddRecFNToRaw_postMul.io.rawOut.sExp
connect roundRawFNToRecFN.io.in.sign, mulAddRecFNToRaw_postMul.io.rawOut.sign
connect roundRawFNToRecFN.io.in.isZero, mulAddRecFNToRaw_postMul.io.rawOut.isZero
connect roundRawFNToRecFN.io.in.isInf, mulAddRecFNToRaw_postMul.io.rawOut.isInf
connect roundRawFNToRecFN.io.in.isNaN, mulAddRecFNToRaw_postMul.io.rawOut.isNaN
connect roundRawFNToRecFN.io.roundingMode, io.roundingMode
connect roundRawFNToRecFN.io.detectTininess, io.detectTininess
connect io.out, roundRawFNToRecFN.io.out
connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags | module MulAddRecFN_e8_s24_48( // @[MulAddRecFN.scala:300:7]
input [32:0] io_a, // @[MulAddRecFN.scala:303:16]
output [32:0] io_out // @[MulAddRecFN.scala:303:16]
);
wire _mulAddRecFNToRaw_postMul_io_invalidExc; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[MulAddRecFN.scala:319:15]
wire [9:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[MulAddRecFN.scala:319:15]
wire [26:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[MulAddRecFN.scala:319:15]
wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddA; // @[MulAddRecFN.scala:317:15]
wire [47:0] _mulAddRecFNToRaw_preMul_io_mulAddC; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[MulAddRecFN.scala:317:15]
wire [9:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[MulAddRecFN.scala:317:15]
wire [4:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[MulAddRecFN.scala:317:15]
wire [25:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[MulAddRecFN.scala:317:15]
wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:300:7]
wire io_detectTininess = 1'h1; // @[MulAddRecFN.scala:300:7, :303:16, :317:15, :319:15, :339:15]
wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:300:7, :303:16, :319:15, :339:15]
wire [32:0] io_c = 33'h15800000; // @[MulAddRecFN.scala:300:7, :303:16, :317:15]
wire [32:0] io_b = 33'h80000000; // @[MulAddRecFN.scala:300:7, :303:16, :317:15]
wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:300:7, :303:16, :317:15]
wire [32:0] io_out_0; // @[MulAddRecFN.scala:300:7]
wire [4:0] io_exceptionFlags; // @[MulAddRecFN.scala:300:7]
wire [47:0] _mulAddResult_T = {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddA, 23'h0}; // @[MulAddRecFN.scala:317:15, :327:45]
wire [48:0] mulAddResult = {1'h0, _mulAddResult_T} + {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC}; // @[MulAddRecFN.scala:317:15, :327:45, :328:50]
MulAddRecFNToRaw_preMul_e8_s24_48 mulAddRecFNToRaw_preMul ( // @[MulAddRecFN.scala:317:15]
.io_a (io_a_0), // @[MulAddRecFN.scala:300:7]
.io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA),
.io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC),
.io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny),
.io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB),
.io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA),
.io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA),
.io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd),
.io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum),
.io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags),
.io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist),
.io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC),
.io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC)
); // @[MulAddRecFN.scala:317:15]
MulAddRecFNToRaw_postMul_e8_s24_48 mulAddRecFNToRaw_postMul ( // @[MulAddRecFN.scala:319:15]
.io_fromPreMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC), // @[MulAddRecFN.scala:317:15]
.io_mulAddResult (mulAddResult), // @[MulAddRecFN.scala:328:50]
.io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc),
.io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN),
.io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf),
.io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero),
.io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign),
.io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp),
.io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig)
); // @[MulAddRecFN.scala:319:15]
RoundRawFNToRecFN_e8_s24_68 roundRawFNToRecFN ( // @[MulAddRecFN.scala:339:15]
.io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), // @[MulAddRecFN.scala:319:15]
.io_in_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), // @[MulAddRecFN.scala:319:15]
.io_in_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), // @[MulAddRecFN.scala:319:15]
.io_in_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), // @[MulAddRecFN.scala:319:15]
.io_in_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), // @[MulAddRecFN.scala:319:15]
.io_in_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), // @[MulAddRecFN.scala:319:15]
.io_in_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig), // @[MulAddRecFN.scala:319:15]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags)
); // @[MulAddRecFN.scala:339:15]
assign io_out = io_out_0; // @[MulAddRecFN.scala:300:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module IntSyncSyncCrossingSink_n1x1_1 :
output auto : { flip in : { sync : UInt<1>[1]}, out : UInt<1>[1]}
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
wire nodeIn : { sync : UInt<1>[1]}
invalidate nodeIn.sync[0]
wire nodeOut : UInt<1>[1]
invalidate nodeOut[0]
connect auto.out, nodeOut
connect nodeIn, auto.in
connect nodeOut, nodeIn.sync | module IntSyncSyncCrossingSink_n1x1_1(); // @[Crossing.scala:96:9]
wire auto_in_sync_0 = 1'h0; // @[Crossing.scala:96:9]
wire auto_out_0 = 1'h0; // @[Crossing.scala:96:9]
wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire nodeIn_sync_0 = 1'h0; // @[MixedNode.scala:551:17]
wire nodeOut_0 = 1'h0; // @[MixedNode.scala:542:17]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PE_269 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>}
inst mac_unit of MacUnit_13
connect mac_unit.clock, clock
connect mac_unit.reset, reset
reg c1 : SInt<32>, clock
reg c2 : SInt<32>, clock
connect io.out_a, io.in_a
connect io.out_control.dataflow, io.in_control.dataflow
connect io.out_control.propagate, io.in_control.propagate
connect io.out_control.shift, io.in_control.shift
connect io.out_id, io.in_id
connect io.out_last, io.in_last
connect io.out_valid, io.in_valid
connect mac_unit.io.in_a, io.in_a
reg last_s : UInt<1>, clock
when io.in_valid :
connect last_s, io.in_control.propagate
node flip = neq(last_s, io.in_control.propagate)
node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0))
connect io.bad_dataflow, UInt<1>(0h0)
node _T = eq(io.in_control.dataflow, UInt<1>(0h0))
node _T_1 = and(UInt<1>(0h1), _T)
node _T_2 = or(UInt<1>(0h0), _T_1)
when _T_2 :
node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_3 :
node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1)
node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2)
node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0)
node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4)
node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_1 = asUInt(c1)
node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1)
node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3)
node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1))
node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1)
node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6)
node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7)
node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0))
node _io_out_c_ones_digit_T = dshr(c1, shift_offset)
node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0)
node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit)
node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T)
node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0)
node _io_out_c_T = dshr(c1, shift_offset)
node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1)
node _io_out_c_T_3 = tail(_io_out_c_T_2, 1)
node _io_out_c_T_4 = asSInt(_io_out_c_T_3)
node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4)
node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7)
node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0)
node _io_out_c_T_10 = asSInt(_io_out_c_T_9)
connect io.out_c, _io_out_c_T_10
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE : SInt<8>
node _mac_unit_io_in_b_T = asUInt(io.in_b)
node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T)
connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE
connect mac_unit.io.in_c, c2
connect c2, mac_unit.io.out_d
node c1_sign = bits(io.in_d, 19, 19)
node c1_lo_lo_hi = cat(c1_sign, c1_sign)
node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign)
node c1_lo_hi_hi = cat(c1_sign, c1_sign)
node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign)
node c1_lo = cat(c1_lo_hi, c1_lo_lo)
node c1_hi_lo_hi = cat(c1_sign, c1_sign)
node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign)
node c1_hi_hi_hi = cat(c1_sign, c1_sign)
node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign)
node c1_hi = cat(c1_hi_hi, c1_hi_lo)
node _c1_T = cat(c1_hi, c1_lo)
node c1_lo_1 = asUInt(io.in_d)
node _c1_T_1 = cat(_c1_T, c1_lo_1)
wire _c1_WIRE : SInt<32>
node _c1_T_2 = asSInt(_c1_T_1)
connect _c1_WIRE, _c1_T_2
connect c1, _c1_WIRE
else :
node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1)
node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7)
node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0)
node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9)
node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_10 = asUInt(c2)
node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1)
node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12)
node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1))
node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1)
node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15)
node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16)
node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0))
node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset)
node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0)
node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1)
node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2)
node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0)
node _io_out_c_T_11 = dshr(c2, shift_offset)
node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12)
node _io_out_c_T_14 = tail(_io_out_c_T_13, 1)
node _io_out_c_T_15 = asSInt(_io_out_c_T_14)
node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15)
node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18)
node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0)
node _io_out_c_T_21 = asSInt(_io_out_c_T_20)
connect io.out_c, _io_out_c_T_21
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE_1 : SInt<8>
node _mac_unit_io_in_b_T_2 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2)
connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1
connect mac_unit.io.in_c, c1
connect c1, mac_unit.io.out_d
node c2_sign = bits(io.in_d, 19, 19)
node c2_lo_lo_hi = cat(c2_sign, c2_sign)
node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign)
node c2_lo_hi_hi = cat(c2_sign, c2_sign)
node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign)
node c2_lo = cat(c2_lo_hi, c2_lo_lo)
node c2_hi_lo_hi = cat(c2_sign, c2_sign)
node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign)
node c2_hi_hi_hi = cat(c2_sign, c2_sign)
node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign)
node c2_hi = cat(c2_hi_hi, c2_hi_lo)
node _c2_T = cat(c2_hi, c2_lo)
node c2_lo_1 = asUInt(io.in_d)
node _c2_T_1 = cat(_c2_T, c2_lo_1)
wire _c2_WIRE : SInt<32>
node _c2_T_2 = asSInt(_c2_T_1)
connect _c2_WIRE, _c2_T_2
connect c2, _c2_WIRE
else :
node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1))
node _T_5 = and(UInt<1>(0h1), _T_4)
node _T_6 = or(UInt<1>(0h0), _T_5)
when _T_6 :
node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_7 :
connect io.out_c, c1
wire _mac_unit_io_in_b_WIRE_2 : SInt<8>
node _mac_unit_io_in_b_T_4 = asUInt(c2)
node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4)
connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c1, io.in_d
else :
connect io.out_c, c2
wire _mac_unit_io_in_b_WIRE_3 : SInt<8>
node _mac_unit_io_in_b_T_6 = asUInt(c1)
node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6)
connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c2, io.in_d
else :
connect io.bad_dataflow, UInt<1>(0h1)
invalidate io.out_c
invalidate io.out_b
wire _mac_unit_io_in_b_WIRE_4 : SInt<8>
node _mac_unit_io_in_b_T_8 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8)
connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4
connect mac_unit.io.in_c, c2
node _T_8 = eq(io.in_valid, UInt<1>(0h0))
when _T_8 :
connect c1, c1
connect c2, c2
invalidate mac_unit.io.in_b
invalidate mac_unit.io.in_c | module PE_269( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid, // @[PE.scala:35:14]
output io_bad_dataflow // @[PE.scala:35:14]
);
wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24]
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [31:0] c1; // @[PE.scala:70:15]
wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [31:0] c2; // @[PE.scala:71:15]
wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25]
wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61]
wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38]
wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38]
assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16]
assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10]
wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10]
c1 <= _GEN_7; // @[PE.scala:70:15, :124:10]
if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30]
end
else // @[PE.scala:71:15, :118:101, :119:30]
c2 <= _GEN_7; // @[PE.scala:71:15, :124:10]
end
else begin // @[PE.scala:31:7]
c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10]
c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10]
end
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
end
always @(posedge)
MacUnit_13 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24]
.io_out_d (_mac_unit_io_out_d)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_197 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_357
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_197( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_357 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_51 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<13>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<13>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 12, 0)
node _source_ok_T = shr(io.in.a.bits.source, 13)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<13>(0h100f))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<13>(0h0))
node uncommonBits = bits(_uncommonBits_T, 12, 0)
node _T_4 = shr(io.in.a.bits.source, 13)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<13>(0h100f))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<13>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 12, 0)
node _T_24 = shr(io.in.a.bits.source, 13)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<13>(0h100f))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_33 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<27>(0h4000000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = and(_T_32, _T_37)
node _T_39 = or(UInt<1>(0h0), _T_38)
node _T_40 = and(_T_31, _T_39)
node _T_41 = asUInt(reset)
node _T_42 = eq(_T_41, UInt<1>(0h0))
when _T_42 :
node _T_43 = eq(_T_40, UInt<1>(0h0))
when _T_43 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_40, UInt<1>(0h1), "") : assert_2
node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_46 = and(_T_44, _T_45)
node _T_47 = or(UInt<1>(0h0), _T_46)
node _T_48 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_49 = cvt(_T_48)
node _T_50 = and(_T_49, asSInt(UInt<27>(0h4000000)))
node _T_51 = asSInt(_T_50)
node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = and(_T_47, _T_52)
node _T_54 = or(UInt<1>(0h0), _T_53)
node _T_55 = and(UInt<1>(0h0), _T_54)
node _T_56 = asUInt(reset)
node _T_57 = eq(_T_56, UInt<1>(0h0))
when _T_57 :
node _T_58 = eq(_T_55, UInt<1>(0h0))
when _T_58 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_55, UInt<1>(0h1), "") : assert_3
node _T_59 = asUInt(reset)
node _T_60 = eq(_T_59, UInt<1>(0h0))
when _T_60 :
node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_61 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_63 = asUInt(reset)
node _T_64 = eq(_T_63, UInt<1>(0h0))
when _T_64 :
node _T_65 = eq(_T_62, UInt<1>(0h0))
when _T_65 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_62, UInt<1>(0h1), "") : assert_5
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(is_aligned, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_70 = asUInt(reset)
node _T_71 = eq(_T_70, UInt<1>(0h0))
when _T_71 :
node _T_72 = eq(_T_69, UInt<1>(0h0))
when _T_72 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_69, UInt<1>(0h1), "") : assert_7
node _T_73 = not(io.in.a.bits.mask)
node _T_74 = eq(_T_73, UInt<1>(0h0))
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_T_74, UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_74, UInt<1>(0h1), "") : assert_8
node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_79 = asUInt(reset)
node _T_80 = eq(_T_79, UInt<1>(0h0))
when _T_80 :
node _T_81 = eq(_T_78, UInt<1>(0h0))
when _T_81 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_78, UInt<1>(0h1), "") : assert_9
node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_82 :
node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_85 = and(_T_83, _T_84)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<13>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 12, 0)
node _T_86 = shr(io.in.a.bits.source, 13)
node _T_87 = eq(_T_86, UInt<1>(0h0))
node _T_88 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_89 = and(_T_87, _T_88)
node _T_90 = leq(uncommonBits_2, UInt<13>(0h100f))
node _T_91 = and(_T_89, _T_90)
node _T_92 = and(_T_85, _T_91)
node _T_93 = or(UInt<1>(0h0), _T_92)
node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_95 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<27>(0h4000000)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = and(_T_94, _T_99)
node _T_101 = or(UInt<1>(0h0), _T_100)
node _T_102 = and(_T_93, _T_101)
node _T_103 = asUInt(reset)
node _T_104 = eq(_T_103, UInt<1>(0h0))
when _T_104 :
node _T_105 = eq(_T_102, UInt<1>(0h0))
when _T_105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_102, UInt<1>(0h1), "") : assert_10
node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_108 = and(_T_106, _T_107)
node _T_109 = or(UInt<1>(0h0), _T_108)
node _T_110 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_111 = cvt(_T_110)
node _T_112 = and(_T_111, asSInt(UInt<27>(0h4000000)))
node _T_113 = asSInt(_T_112)
node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0)))
node _T_115 = and(_T_109, _T_114)
node _T_116 = or(UInt<1>(0h0), _T_115)
node _T_117 = and(UInt<1>(0h0), _T_116)
node _T_118 = asUInt(reset)
node _T_119 = eq(_T_118, UInt<1>(0h0))
when _T_119 :
node _T_120 = eq(_T_117, UInt<1>(0h0))
when _T_120 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_117, UInt<1>(0h1), "") : assert_11
node _T_121 = asUInt(reset)
node _T_122 = eq(_T_121, UInt<1>(0h0))
when _T_122 :
node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_125 = asUInt(reset)
node _T_126 = eq(_T_125, UInt<1>(0h0))
when _T_126 :
node _T_127 = eq(_T_124, UInt<1>(0h0))
when _T_127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_124, UInt<1>(0h1), "") : assert_13
node _T_128 = asUInt(reset)
node _T_129 = eq(_T_128, UInt<1>(0h0))
when _T_129 :
node _T_130 = eq(is_aligned, UInt<1>(0h0))
when _T_130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_131, UInt<1>(0h1), "") : assert_15
node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_136 = asUInt(reset)
node _T_137 = eq(_T_136, UInt<1>(0h0))
when _T_137 :
node _T_138 = eq(_T_135, UInt<1>(0h0))
when _T_138 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_135, UInt<1>(0h1), "") : assert_16
node _T_139 = not(io.in.a.bits.mask)
node _T_140 = eq(_T_139, UInt<1>(0h0))
node _T_141 = asUInt(reset)
node _T_142 = eq(_T_141, UInt<1>(0h0))
when _T_142 :
node _T_143 = eq(_T_140, UInt<1>(0h0))
when _T_143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_140, UInt<1>(0h1), "") : assert_17
node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_145 = asUInt(reset)
node _T_146 = eq(_T_145, UInt<1>(0h0))
when _T_146 :
node _T_147 = eq(_T_144, UInt<1>(0h0))
when _T_147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_144, UInt<1>(0h1), "") : assert_18
node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_148 :
node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_151 = and(_T_149, _T_150)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<13>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 12, 0)
node _T_152 = shr(io.in.a.bits.source, 13)
node _T_153 = eq(_T_152, UInt<1>(0h0))
node _T_154 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_155 = and(_T_153, _T_154)
node _T_156 = leq(uncommonBits_3, UInt<13>(0h100f))
node _T_157 = and(_T_155, _T_156)
node _T_158 = and(_T_151, _T_157)
node _T_159 = or(UInt<1>(0h0), _T_158)
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_T_159, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_159, UInt<1>(0h1), "") : assert_19
node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_165 = and(_T_163, _T_164)
node _T_166 = or(UInt<1>(0h0), _T_165)
node _T_167 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_168 = cvt(_T_167)
node _T_169 = and(_T_168, asSInt(UInt<27>(0h4000000)))
node _T_170 = asSInt(_T_169)
node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0)))
node _T_172 = and(_T_166, _T_171)
node _T_173 = or(UInt<1>(0h0), _T_172)
node _T_174 = asUInt(reset)
node _T_175 = eq(_T_174, UInt<1>(0h0))
when _T_175 :
node _T_176 = eq(_T_173, UInt<1>(0h0))
when _T_176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_173, UInt<1>(0h1), "") : assert_20
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_180 = asUInt(reset)
node _T_181 = eq(_T_180, UInt<1>(0h0))
when _T_181 :
node _T_182 = eq(is_aligned, UInt<1>(0h0))
when _T_182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(io.in.a.bits.mask, mask)
node _T_188 = asUInt(reset)
node _T_189 = eq(_T_188, UInt<1>(0h0))
when _T_189 :
node _T_190 = eq(_T_187, UInt<1>(0h0))
when _T_190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_187, UInt<1>(0h1), "") : assert_24
node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_192 = asUInt(reset)
node _T_193 = eq(_T_192, UInt<1>(0h0))
when _T_193 :
node _T_194 = eq(_T_191, UInt<1>(0h0))
when _T_194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_191, UInt<1>(0h1), "") : assert_25
node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_195 :
node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_198 = and(_T_196, _T_197)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<13>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 12, 0)
node _T_199 = shr(io.in.a.bits.source, 13)
node _T_200 = eq(_T_199, UInt<1>(0h0))
node _T_201 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_202 = and(_T_200, _T_201)
node _T_203 = leq(uncommonBits_4, UInt<13>(0h100f))
node _T_204 = and(_T_202, _T_203)
node _T_205 = and(_T_198, _T_204)
node _T_206 = or(UInt<1>(0h0), _T_205)
node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_209 = and(_T_207, _T_208)
node _T_210 = or(UInt<1>(0h0), _T_209)
node _T_211 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_212 = cvt(_T_211)
node _T_213 = and(_T_212, asSInt(UInt<27>(0h4000000)))
node _T_214 = asSInt(_T_213)
node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0)))
node _T_216 = and(_T_210, _T_215)
node _T_217 = or(UInt<1>(0h0), _T_216)
node _T_218 = and(_T_206, _T_217)
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_218, UInt<1>(0h1), "") : assert_26
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_225 = asUInt(reset)
node _T_226 = eq(_T_225, UInt<1>(0h0))
when _T_226 :
node _T_227 = eq(is_aligned, UInt<1>(0h0))
when _T_227 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_229 = asUInt(reset)
node _T_230 = eq(_T_229, UInt<1>(0h0))
when _T_230 :
node _T_231 = eq(_T_228, UInt<1>(0h0))
when _T_231 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_228, UInt<1>(0h1), "") : assert_29
node _T_232 = eq(io.in.a.bits.mask, mask)
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_232, UInt<1>(0h1), "") : assert_30
node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_236 :
node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_239 = and(_T_237, _T_238)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<13>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 12, 0)
node _T_240 = shr(io.in.a.bits.source, 13)
node _T_241 = eq(_T_240, UInt<1>(0h0))
node _T_242 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_243 = and(_T_241, _T_242)
node _T_244 = leq(uncommonBits_5, UInt<13>(0h100f))
node _T_245 = and(_T_243, _T_244)
node _T_246 = and(_T_239, _T_245)
node _T_247 = or(UInt<1>(0h0), _T_246)
node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_250 = and(_T_248, _T_249)
node _T_251 = or(UInt<1>(0h0), _T_250)
node _T_252 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_253 = cvt(_T_252)
node _T_254 = and(_T_253, asSInt(UInt<27>(0h4000000)))
node _T_255 = asSInt(_T_254)
node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0)))
node _T_257 = and(_T_251, _T_256)
node _T_258 = or(UInt<1>(0h0), _T_257)
node _T_259 = and(_T_247, _T_258)
node _T_260 = asUInt(reset)
node _T_261 = eq(_T_260, UInt<1>(0h0))
when _T_261 :
node _T_262 = eq(_T_259, UInt<1>(0h0))
when _T_262 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_259, UInt<1>(0h1), "") : assert_31
node _T_263 = asUInt(reset)
node _T_264 = eq(_T_263, UInt<1>(0h0))
when _T_264 :
node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_265 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_266 = asUInt(reset)
node _T_267 = eq(_T_266, UInt<1>(0h0))
when _T_267 :
node _T_268 = eq(is_aligned, UInt<1>(0h0))
when _T_268 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_270 = asUInt(reset)
node _T_271 = eq(_T_270, UInt<1>(0h0))
when _T_271 :
node _T_272 = eq(_T_269, UInt<1>(0h0))
when _T_272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_269, UInt<1>(0h1), "") : assert_34
node _T_273 = not(mask)
node _T_274 = and(io.in.a.bits.mask, _T_273)
node _T_275 = eq(_T_274, UInt<1>(0h0))
node _T_276 = asUInt(reset)
node _T_277 = eq(_T_276, UInt<1>(0h0))
when _T_277 :
node _T_278 = eq(_T_275, UInt<1>(0h0))
when _T_278 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_275, UInt<1>(0h1), "") : assert_35
node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_279 :
node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_282 = and(_T_280, _T_281)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<13>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 12, 0)
node _T_283 = shr(io.in.a.bits.source, 13)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_286 = and(_T_284, _T_285)
node _T_287 = leq(uncommonBits_6, UInt<13>(0h100f))
node _T_288 = and(_T_286, _T_287)
node _T_289 = and(_T_282, _T_288)
node _T_290 = or(UInt<1>(0h0), _T_289)
node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_292 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_293 = cvt(_T_292)
node _T_294 = and(_T_293, asSInt(UInt<27>(0h4000000)))
node _T_295 = asSInt(_T_294)
node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0)))
node _T_297 = and(_T_291, _T_296)
node _T_298 = or(UInt<1>(0h0), _T_297)
node _T_299 = and(_T_290, _T_298)
node _T_300 = asUInt(reset)
node _T_301 = eq(_T_300, UInt<1>(0h0))
when _T_301 :
node _T_302 = eq(_T_299, UInt<1>(0h0))
when _T_302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_299, UInt<1>(0h1), "") : assert_36
node _T_303 = asUInt(reset)
node _T_304 = eq(_T_303, UInt<1>(0h0))
when _T_304 :
node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_305 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_306 = asUInt(reset)
node _T_307 = eq(_T_306, UInt<1>(0h0))
when _T_307 :
node _T_308 = eq(is_aligned, UInt<1>(0h0))
when _T_308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_310 = asUInt(reset)
node _T_311 = eq(_T_310, UInt<1>(0h0))
when _T_311 :
node _T_312 = eq(_T_309, UInt<1>(0h0))
when _T_312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_309, UInt<1>(0h1), "") : assert_39
node _T_313 = eq(io.in.a.bits.mask, mask)
node _T_314 = asUInt(reset)
node _T_315 = eq(_T_314, UInt<1>(0h0))
when _T_315 :
node _T_316 = eq(_T_313, UInt<1>(0h0))
when _T_316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_313, UInt<1>(0h1), "") : assert_40
node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_317 :
node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_320 = and(_T_318, _T_319)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<13>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 12, 0)
node _T_321 = shr(io.in.a.bits.source, 13)
node _T_322 = eq(_T_321, UInt<1>(0h0))
node _T_323 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_324 = and(_T_322, _T_323)
node _T_325 = leq(uncommonBits_7, UInt<13>(0h100f))
node _T_326 = and(_T_324, _T_325)
node _T_327 = and(_T_320, _T_326)
node _T_328 = or(UInt<1>(0h0), _T_327)
node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_330 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_331 = cvt(_T_330)
node _T_332 = and(_T_331, asSInt(UInt<27>(0h4000000)))
node _T_333 = asSInt(_T_332)
node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0)))
node _T_335 = and(_T_329, _T_334)
node _T_336 = or(UInt<1>(0h0), _T_335)
node _T_337 = and(_T_328, _T_336)
node _T_338 = asUInt(reset)
node _T_339 = eq(_T_338, UInt<1>(0h0))
when _T_339 :
node _T_340 = eq(_T_337, UInt<1>(0h0))
when _T_340 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_337, UInt<1>(0h1), "") : assert_41
node _T_341 = asUInt(reset)
node _T_342 = eq(_T_341, UInt<1>(0h0))
when _T_342 :
node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_343 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_344 = asUInt(reset)
node _T_345 = eq(_T_344, UInt<1>(0h0))
when _T_345 :
node _T_346 = eq(is_aligned, UInt<1>(0h0))
when _T_346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_347, UInt<1>(0h1), "") : assert_44
node _T_351 = eq(io.in.a.bits.mask, mask)
node _T_352 = asUInt(reset)
node _T_353 = eq(_T_352, UInt<1>(0h0))
when _T_353 :
node _T_354 = eq(_T_351, UInt<1>(0h0))
when _T_354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_351, UInt<1>(0h1), "") : assert_45
node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_355 :
node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_358 = and(_T_356, _T_357)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<13>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 12, 0)
node _T_359 = shr(io.in.a.bits.source, 13)
node _T_360 = eq(_T_359, UInt<1>(0h0))
node _T_361 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_362 = and(_T_360, _T_361)
node _T_363 = leq(uncommonBits_8, UInt<13>(0h100f))
node _T_364 = and(_T_362, _T_363)
node _T_365 = and(_T_358, _T_364)
node _T_366 = or(UInt<1>(0h0), _T_365)
node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_368 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_369 = cvt(_T_368)
node _T_370 = and(_T_369, asSInt(UInt<27>(0h4000000)))
node _T_371 = asSInt(_T_370)
node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0)))
node _T_373 = and(_T_367, _T_372)
node _T_374 = or(UInt<1>(0h0), _T_373)
node _T_375 = and(_T_366, _T_374)
node _T_376 = asUInt(reset)
node _T_377 = eq(_T_376, UInt<1>(0h0))
when _T_377 :
node _T_378 = eq(_T_375, UInt<1>(0h0))
when _T_378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_375, UInt<1>(0h1), "") : assert_46
node _T_379 = asUInt(reset)
node _T_380 = eq(_T_379, UInt<1>(0h0))
when _T_380 :
node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_382 = asUInt(reset)
node _T_383 = eq(_T_382, UInt<1>(0h0))
when _T_383 :
node _T_384 = eq(is_aligned, UInt<1>(0h0))
when _T_384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_386 = asUInt(reset)
node _T_387 = eq(_T_386, UInt<1>(0h0))
when _T_387 :
node _T_388 = eq(_T_385, UInt<1>(0h0))
when _T_388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_385, UInt<1>(0h1), "") : assert_49
node _T_389 = eq(io.in.a.bits.mask, mask)
node _T_390 = asUInt(reset)
node _T_391 = eq(_T_390, UInt<1>(0h0))
when _T_391 :
node _T_392 = eq(_T_389, UInt<1>(0h0))
when _T_392 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_389, UInt<1>(0h1), "") : assert_50
node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_394 = asUInt(reset)
node _T_395 = eq(_T_394, UInt<1>(0h0))
when _T_395 :
node _T_396 = eq(_T_393, UInt<1>(0h0))
when _T_396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_393, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_397, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<13>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 12, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 13)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<13>(0h100f))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_401 :
node _T_402 = asUInt(reset)
node _T_403 = eq(_T_402, UInt<1>(0h0))
when _T_403 :
node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_404 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_406 = asUInt(reset)
node _T_407 = eq(_T_406, UInt<1>(0h0))
when _T_407 :
node _T_408 = eq(_T_405, UInt<1>(0h0))
when _T_408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_405, UInt<1>(0h1), "") : assert_54
node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_410 = asUInt(reset)
node _T_411 = eq(_T_410, UInt<1>(0h0))
when _T_411 :
node _T_412 = eq(_T_409, UInt<1>(0h0))
when _T_412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_409, UInt<1>(0h1), "") : assert_55
node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_414 = asUInt(reset)
node _T_415 = eq(_T_414, UInt<1>(0h0))
when _T_415 :
node _T_416 = eq(_T_413, UInt<1>(0h0))
when _T_416 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_413, UInt<1>(0h1), "") : assert_56
node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_418 = asUInt(reset)
node _T_419 = eq(_T_418, UInt<1>(0h0))
when _T_419 :
node _T_420 = eq(_T_417, UInt<1>(0h0))
when _T_420 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_417, UInt<1>(0h1), "") : assert_57
node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_421 :
node _T_422 = asUInt(reset)
node _T_423 = eq(_T_422, UInt<1>(0h0))
when _T_423 :
node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_424 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_425 = asUInt(reset)
node _T_426 = eq(_T_425, UInt<1>(0h0))
when _T_426 :
node _T_427 = eq(sink_ok, UInt<1>(0h0))
when _T_427 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_429 = asUInt(reset)
node _T_430 = eq(_T_429, UInt<1>(0h0))
when _T_430 :
node _T_431 = eq(_T_428, UInt<1>(0h0))
when _T_431 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_428, UInt<1>(0h1), "") : assert_60
node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_433 = asUInt(reset)
node _T_434 = eq(_T_433, UInt<1>(0h0))
when _T_434 :
node _T_435 = eq(_T_432, UInt<1>(0h0))
when _T_435 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_432, UInt<1>(0h1), "") : assert_61
node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_437 = asUInt(reset)
node _T_438 = eq(_T_437, UInt<1>(0h0))
when _T_438 :
node _T_439 = eq(_T_436, UInt<1>(0h0))
when _T_439 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_436, UInt<1>(0h1), "") : assert_62
node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_441 = asUInt(reset)
node _T_442 = eq(_T_441, UInt<1>(0h0))
when _T_442 :
node _T_443 = eq(_T_440, UInt<1>(0h0))
when _T_443 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_440, UInt<1>(0h1), "") : assert_63
node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_445 = or(UInt<1>(0h0), _T_444)
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_445, UInt<1>(0h1), "") : assert_64
node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_449 :
node _T_450 = asUInt(reset)
node _T_451 = eq(_T_450, UInt<1>(0h0))
when _T_451 :
node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(sink_ok, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_457 = asUInt(reset)
node _T_458 = eq(_T_457, UInt<1>(0h0))
when _T_458 :
node _T_459 = eq(_T_456, UInt<1>(0h0))
when _T_459 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_456, UInt<1>(0h1), "") : assert_67
node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_461 = asUInt(reset)
node _T_462 = eq(_T_461, UInt<1>(0h0))
when _T_462 :
node _T_463 = eq(_T_460, UInt<1>(0h0))
when _T_463 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_460, UInt<1>(0h1), "") : assert_68
node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_465 = asUInt(reset)
node _T_466 = eq(_T_465, UInt<1>(0h0))
when _T_466 :
node _T_467 = eq(_T_464, UInt<1>(0h0))
when _T_467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_464, UInt<1>(0h1), "") : assert_69
node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_469 = or(_T_468, io.in.d.bits.corrupt)
node _T_470 = asUInt(reset)
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(_T_469, UInt<1>(0h0))
when _T_472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_469, UInt<1>(0h1), "") : assert_70
node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_474 = or(UInt<1>(0h0), _T_473)
node _T_475 = asUInt(reset)
node _T_476 = eq(_T_475, UInt<1>(0h0))
when _T_476 :
node _T_477 = eq(_T_474, UInt<1>(0h0))
when _T_477 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_474, UInt<1>(0h1), "") : assert_71
node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_478 :
node _T_479 = asUInt(reset)
node _T_480 = eq(_T_479, UInt<1>(0h0))
when _T_480 :
node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_481 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_483 = asUInt(reset)
node _T_484 = eq(_T_483, UInt<1>(0h0))
when _T_484 :
node _T_485 = eq(_T_482, UInt<1>(0h0))
when _T_485 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_482, UInt<1>(0h1), "") : assert_73
node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_487 = asUInt(reset)
node _T_488 = eq(_T_487, UInt<1>(0h0))
when _T_488 :
node _T_489 = eq(_T_486, UInt<1>(0h0))
when _T_489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_486, UInt<1>(0h1), "") : assert_74
node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_491 = or(UInt<1>(0h0), _T_490)
node _T_492 = asUInt(reset)
node _T_493 = eq(_T_492, UInt<1>(0h0))
when _T_493 :
node _T_494 = eq(_T_491, UInt<1>(0h0))
when _T_494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_491, UInt<1>(0h1), "") : assert_75
node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_495 :
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_500 = asUInt(reset)
node _T_501 = eq(_T_500, UInt<1>(0h0))
when _T_501 :
node _T_502 = eq(_T_499, UInt<1>(0h0))
when _T_502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_499, UInt<1>(0h1), "") : assert_77
node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_504 = or(_T_503, io.in.d.bits.corrupt)
node _T_505 = asUInt(reset)
node _T_506 = eq(_T_505, UInt<1>(0h0))
when _T_506 :
node _T_507 = eq(_T_504, UInt<1>(0h0))
when _T_507 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_504, UInt<1>(0h1), "") : assert_78
node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_509 = or(UInt<1>(0h0), _T_508)
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_509, UInt<1>(0h1), "") : assert_79
node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_513 :
node _T_514 = asUInt(reset)
node _T_515 = eq(_T_514, UInt<1>(0h0))
when _T_515 :
node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_516 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_518 = asUInt(reset)
node _T_519 = eq(_T_518, UInt<1>(0h0))
when _T_519 :
node _T_520 = eq(_T_517, UInt<1>(0h0))
when _T_520 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_517, UInt<1>(0h1), "") : assert_81
node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_522 = asUInt(reset)
node _T_523 = eq(_T_522, UInt<1>(0h0))
when _T_523 :
node _T_524 = eq(_T_521, UInt<1>(0h0))
when _T_524 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_521, UInt<1>(0h1), "") : assert_82
node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_526 = or(UInt<1>(0h0), _T_525)
node _T_527 = asUInt(reset)
node _T_528 = eq(_T_527, UInt<1>(0h0))
when _T_528 :
node _T_529 = eq(_T_526, UInt<1>(0h0))
when _T_529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_526, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<13>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<28>(0h0)
connect _WIRE.bits.source, UInt<13>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<13>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_531 = asUInt(reset)
node _T_532 = eq(_T_531, UInt<1>(0h0))
when _T_532 :
node _T_533 = eq(_T_530, UInt<1>(0h0))
when _T_533 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_530, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<28>(0h0)
connect _WIRE_2.bits.source, UInt<13>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_535 = asUInt(reset)
node _T_536 = eq(_T_535, UInt<1>(0h0))
when _T_536 :
node _T_537 = eq(_T_534, UInt<1>(0h0))
when _T_537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_534, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_T_538, UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_538, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_542 = eq(a_first, UInt<1>(0h0))
node _T_543 = and(io.in.a.valid, _T_542)
when _T_543 :
node _T_544 = eq(io.in.a.bits.opcode, opcode)
node _T_545 = asUInt(reset)
node _T_546 = eq(_T_545, UInt<1>(0h0))
when _T_546 :
node _T_547 = eq(_T_544, UInt<1>(0h0))
when _T_547 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_544, UInt<1>(0h1), "") : assert_87
node _T_548 = eq(io.in.a.bits.param, param)
node _T_549 = asUInt(reset)
node _T_550 = eq(_T_549, UInt<1>(0h0))
when _T_550 :
node _T_551 = eq(_T_548, UInt<1>(0h0))
when _T_551 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_548, UInt<1>(0h1), "") : assert_88
node _T_552 = eq(io.in.a.bits.size, size)
node _T_553 = asUInt(reset)
node _T_554 = eq(_T_553, UInt<1>(0h0))
when _T_554 :
node _T_555 = eq(_T_552, UInt<1>(0h0))
when _T_555 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_552, UInt<1>(0h1), "") : assert_89
node _T_556 = eq(io.in.a.bits.source, source)
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_556, UInt<1>(0h1), "") : assert_90
node _T_560 = eq(io.in.a.bits.address, address)
node _T_561 = asUInt(reset)
node _T_562 = eq(_T_561, UInt<1>(0h0))
when _T_562 :
node _T_563 = eq(_T_560, UInt<1>(0h0))
when _T_563 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_560, UInt<1>(0h1), "") : assert_91
node _T_564 = and(io.in.a.ready, io.in.a.valid)
node _T_565 = and(_T_564, a_first)
when _T_565 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_566 = eq(d_first, UInt<1>(0h0))
node _T_567 = and(io.in.d.valid, _T_566)
when _T_567 :
node _T_568 = eq(io.in.d.bits.opcode, opcode_1)
node _T_569 = asUInt(reset)
node _T_570 = eq(_T_569, UInt<1>(0h0))
when _T_570 :
node _T_571 = eq(_T_568, UInt<1>(0h0))
when _T_571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_568, UInt<1>(0h1), "") : assert_92
node _T_572 = eq(io.in.d.bits.param, param_1)
node _T_573 = asUInt(reset)
node _T_574 = eq(_T_573, UInt<1>(0h0))
when _T_574 :
node _T_575 = eq(_T_572, UInt<1>(0h0))
when _T_575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_572, UInt<1>(0h1), "") : assert_93
node _T_576 = eq(io.in.d.bits.size, size_1)
node _T_577 = asUInt(reset)
node _T_578 = eq(_T_577, UInt<1>(0h0))
when _T_578 :
node _T_579 = eq(_T_576, UInt<1>(0h0))
when _T_579 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_576, UInt<1>(0h1), "") : assert_94
node _T_580 = eq(io.in.d.bits.source, source_1)
node _T_581 = asUInt(reset)
node _T_582 = eq(_T_581, UInt<1>(0h0))
when _T_582 :
node _T_583 = eq(_T_580, UInt<1>(0h0))
when _T_583 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_580, UInt<1>(0h1), "") : assert_95
node _T_584 = eq(io.in.d.bits.sink, sink)
node _T_585 = asUInt(reset)
node _T_586 = eq(_T_585, UInt<1>(0h0))
when _T_586 :
node _T_587 = eq(_T_584, UInt<1>(0h0))
when _T_587 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_584, UInt<1>(0h1), "") : assert_96
node _T_588 = eq(io.in.d.bits.denied, denied)
node _T_589 = asUInt(reset)
node _T_590 = eq(_T_589, UInt<1>(0h0))
when _T_590 :
node _T_591 = eq(_T_588, UInt<1>(0h0))
when _T_591 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_588, UInt<1>(0h1), "") : assert_97
node _T_592 = and(io.in.d.ready, io.in.d.valid)
node _T_593 = and(_T_592, d_first)
when _T_593 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<4112>, clock, reset, UInt<4112>(0h0)
regreset inflight_opcodes : UInt<16448>, clock, reset, UInt<16448>(0h0)
regreset inflight_sizes : UInt<16448>, clock, reset, UInt<16448>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<4112>
connect a_set, UInt<4112>(0h0)
wire a_set_wo_ready : UInt<4112>
connect a_set_wo_ready, UInt<4112>(0h0)
wire a_opcodes_set : UInt<16448>
connect a_opcodes_set, UInt<16448>(0h0)
wire a_sizes_set : UInt<16448>
connect a_sizes_set, UInt<16448>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<3>
connect a_sizes_set_interm, UInt<3>(0h0)
node _T_594 = and(io.in.a.valid, a_first_1)
node _T_595 = and(_T_594, UInt<1>(0h1))
when _T_595 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_596 = and(io.in.a.ready, io.in.a.valid)
node _T_597 = and(_T_596, a_first_1)
node _T_598 = and(_T_597, UInt<1>(0h1))
when _T_598 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_599 = dshr(inflight, io.in.a.bits.source)
node _T_600 = bits(_T_599, 0, 0)
node _T_601 = eq(_T_600, UInt<1>(0h0))
node _T_602 = asUInt(reset)
node _T_603 = eq(_T_602, UInt<1>(0h0))
when _T_603 :
node _T_604 = eq(_T_601, UInt<1>(0h0))
when _T_604 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_601, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<4112>
connect d_clr, UInt<4112>(0h0)
wire d_clr_wo_ready : UInt<4112>
connect d_clr_wo_ready, UInt<4112>(0h0)
wire d_opcodes_clr : UInt<16448>
connect d_opcodes_clr, UInt<16448>(0h0)
wire d_sizes_clr : UInt<16448>
connect d_sizes_clr, UInt<16448>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_605 = and(io.in.d.valid, d_first_1)
node _T_606 = and(_T_605, UInt<1>(0h1))
node _T_607 = eq(d_release_ack, UInt<1>(0h0))
node _T_608 = and(_T_606, _T_607)
when _T_608 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_609 = and(io.in.d.ready, io.in.d.valid)
node _T_610 = and(_T_609, d_first_1)
node _T_611 = and(_T_610, UInt<1>(0h1))
node _T_612 = eq(d_release_ack, UInt<1>(0h0))
node _T_613 = and(_T_611, _T_612)
when _T_613 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_614 = and(io.in.d.valid, d_first_1)
node _T_615 = and(_T_614, UInt<1>(0h1))
node _T_616 = eq(d_release_ack, UInt<1>(0h0))
node _T_617 = and(_T_615, _T_616)
when _T_617 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_618 = dshr(inflight, io.in.d.bits.source)
node _T_619 = bits(_T_618, 0, 0)
node _T_620 = or(_T_619, same_cycle_resp)
node _T_621 = asUInt(reset)
node _T_622 = eq(_T_621, UInt<1>(0h0))
when _T_622 :
node _T_623 = eq(_T_620, UInt<1>(0h0))
when _T_623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_620, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_626 = or(_T_624, _T_625)
node _T_627 = asUInt(reset)
node _T_628 = eq(_T_627, UInt<1>(0h0))
when _T_628 :
node _T_629 = eq(_T_626, UInt<1>(0h0))
when _T_629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_626, UInt<1>(0h1), "") : assert_100
node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_630, UInt<1>(0h1), "") : assert_101
else :
node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_636 = or(_T_634, _T_635)
node _T_637 = asUInt(reset)
node _T_638 = eq(_T_637, UInt<1>(0h0))
when _T_638 :
node _T_639 = eq(_T_636, UInt<1>(0h0))
when _T_639 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_636, UInt<1>(0h1), "") : assert_102
node _T_640 = eq(io.in.d.bits.size, a_size_lookup)
node _T_641 = asUInt(reset)
node _T_642 = eq(_T_641, UInt<1>(0h0))
when _T_642 :
node _T_643 = eq(_T_640, UInt<1>(0h0))
when _T_643 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_640, UInt<1>(0h1), "") : assert_103
node _T_644 = and(io.in.d.valid, d_first_1)
node _T_645 = and(_T_644, a_first_1)
node _T_646 = and(_T_645, io.in.a.valid)
node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_648 = and(_T_646, _T_647)
node _T_649 = eq(d_release_ack, UInt<1>(0h0))
node _T_650 = and(_T_648, _T_649)
when _T_650 :
node _T_651 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_652 = or(_T_651, io.in.a.ready)
node _T_653 = asUInt(reset)
node _T_654 = eq(_T_653, UInt<1>(0h0))
when _T_654 :
node _T_655 = eq(_T_652, UInt<1>(0h0))
when _T_655 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_652, UInt<1>(0h1), "") : assert_104
node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_657 = orr(a_set_wo_ready)
node _T_658 = eq(_T_657, UInt<1>(0h0))
node _T_659 = or(_T_656, _T_658)
node _T_660 = asUInt(reset)
node _T_661 = eq(_T_660, UInt<1>(0h0))
when _T_661 :
node _T_662 = eq(_T_659, UInt<1>(0h0))
when _T_662 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_659, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_104
node _T_663 = orr(inflight)
node _T_664 = eq(_T_663, UInt<1>(0h0))
node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_666 = or(_T_664, _T_665)
node _T_667 = lt(watchdog, plusarg_reader.out)
node _T_668 = or(_T_666, _T_667)
node _T_669 = asUInt(reset)
node _T_670 = eq(_T_669, UInt<1>(0h0))
when _T_670 :
node _T_671 = eq(_T_668, UInt<1>(0h0))
when _T_671 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_668, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_672 = and(io.in.a.ready, io.in.a.valid)
node _T_673 = and(io.in.d.ready, io.in.d.valid)
node _T_674 = or(_T_672, _T_673)
when _T_674 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<4112>, clock, reset, UInt<4112>(0h0)
regreset inflight_opcodes_1 : UInt<16448>, clock, reset, UInt<16448>(0h0)
regreset inflight_sizes_1 : UInt<16448>, clock, reset, UInt<16448>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<28>(0h0)
connect _c_first_WIRE.bits.source, UInt<13>(0h0)
connect _c_first_WIRE.bits.size, UInt<2>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<28>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<13>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<4112>
connect c_set, UInt<4112>(0h0)
wire c_set_wo_ready : UInt<4112>
connect c_set_wo_ready, UInt<4112>(0h0)
wire c_opcodes_set : UInt<16448>
connect c_opcodes_set, UInt<16448>(0h0)
wire c_sizes_set : UInt<16448>
connect c_sizes_set, UInt<16448>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<3>
connect c_sizes_set_interm, UInt<3>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<28>(0h0)
connect _WIRE_6.bits.source, UInt<13>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_675 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<28>(0h0)
connect _WIRE_8.bits.source, UInt<13>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_678 = and(_T_676, _T_677)
node _T_679 = and(_T_675, _T_678)
when _T_679 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<13>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<28>(0h0)
connect _WIRE_10.bits.source, UInt<13>(0h0)
connect _WIRE_10.bits.size, UInt<2>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_681 = and(_T_680, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<28>(0h0)
connect _WIRE_12.bits.source, UInt<13>(0h0)
connect _WIRE_12.bits.size, UInt<2>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_684 = and(_T_682, _T_683)
node _T_685 = and(_T_681, _T_684)
when _T_685 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_set_WIRE.bits.source, UInt<13>(0h0)
connect _c_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<13>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<13>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<13>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<13>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<28>(0h0)
connect _WIRE_14.bits.source, UInt<13>(0h0)
connect _WIRE_14.bits.size, UInt<2>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_686 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_687 = bits(_T_686, 0, 0)
node _T_688 = eq(_T_687, UInt<1>(0h0))
node _T_689 = asUInt(reset)
node _T_690 = eq(_T_689, UInt<1>(0h0))
when _T_690 :
node _T_691 = eq(_T_688, UInt<1>(0h0))
when _T_691 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_688, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<13>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<13>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<4112>
connect d_clr_1, UInt<4112>(0h0)
wire d_clr_wo_ready_1 : UInt<4112>
connect d_clr_wo_ready_1, UInt<4112>(0h0)
wire d_opcodes_clr_1 : UInt<16448>
connect d_opcodes_clr_1, UInt<16448>(0h0)
wire d_sizes_clr_1 : UInt<16448>
connect d_sizes_clr_1, UInt<16448>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_692 = and(io.in.d.valid, d_first_2)
node _T_693 = and(_T_692, UInt<1>(0h1))
node _T_694 = and(_T_693, d_release_ack_1)
when _T_694 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_695 = and(io.in.d.ready, io.in.d.valid)
node _T_696 = and(_T_695, d_first_2)
node _T_697 = and(_T_696, UInt<1>(0h1))
node _T_698 = and(_T_697, d_release_ack_1)
when _T_698 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_699 = and(io.in.d.valid, d_first_2)
node _T_700 = and(_T_699, UInt<1>(0h1))
node _T_701 = and(_T_700, d_release_ack_1)
when _T_701 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<13>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<13>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<13>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_702 = dshr(inflight_1, io.in.d.bits.source)
node _T_703 = bits(_T_702, 0, 0)
node _T_704 = or(_T_703, same_cycle_resp_1)
node _T_705 = asUInt(reset)
node _T_706 = eq(_T_705, UInt<1>(0h0))
when _T_706 :
node _T_707 = eq(_T_704, UInt<1>(0h0))
when _T_707 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_704, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<28>(0h0)
connect _WIRE_16.bits.source, UInt<13>(0h0)
connect _WIRE_16.bits.size, UInt<2>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_709 = asUInt(reset)
node _T_710 = eq(_T_709, UInt<1>(0h0))
when _T_710 :
node _T_711 = eq(_T_708, UInt<1>(0h0))
when _T_711 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_708, UInt<1>(0h1), "") : assert_109
else :
node _T_712 = eq(io.in.d.bits.size, c_size_lookup)
node _T_713 = asUInt(reset)
node _T_714 = eq(_T_713, UInt<1>(0h0))
when _T_714 :
node _T_715 = eq(_T_712, UInt<1>(0h0))
when _T_715 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_712, UInt<1>(0h1), "") : assert_110
node _T_716 = and(io.in.d.valid, d_first_2)
node _T_717 = and(_T_716, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<28>(0h0)
connect _WIRE_18.bits.source, UInt<13>(0h0)
connect _WIRE_18.bits.size, UInt<2>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_718 = and(_T_717, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<28>(0h0)
connect _WIRE_20.bits.source, UInt<13>(0h0)
connect _WIRE_20.bits.size, UInt<2>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_720 = and(_T_718, _T_719)
node _T_721 = and(_T_720, d_release_ack_1)
node _T_722 = eq(c_probe_ack, UInt<1>(0h0))
node _T_723 = and(_T_721, _T_722)
when _T_723 :
node _T_724 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<28>(0h0)
connect _WIRE_22.bits.source, UInt<13>(0h0)
connect _WIRE_22.bits.size, UInt<2>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_725 = or(_T_724, _WIRE_23.ready)
node _T_726 = asUInt(reset)
node _T_727 = eq(_T_726, UInt<1>(0h0))
when _T_727 :
node _T_728 = eq(_T_725, UInt<1>(0h0))
when _T_728 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_725, UInt<1>(0h1), "") : assert_111
node _T_729 = orr(c_set_wo_ready)
when _T_729 :
node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_731 = asUInt(reset)
node _T_732 = eq(_T_731, UInt<1>(0h0))
when _T_732 :
node _T_733 = eq(_T_730, UInt<1>(0h0))
when _T_733 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_730, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_105
node _T_734 = orr(inflight_1)
node _T_735 = eq(_T_734, UInt<1>(0h0))
node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_737 = or(_T_735, _T_736)
node _T_738 = lt(watchdog_1, plusarg_reader_1.out)
node _T_739 = or(_T_737, _T_738)
node _T_740 = asUInt(reset)
node _T_741 = eq(_T_740, UInt<1>(0h0))
when _T_741 :
node _T_742 = eq(_T_739, UInt<1>(0h0))
when _T_742 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_739, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<28>(0h0)
connect _WIRE_24.bits.source, UInt<13>(0h0)
connect _WIRE_24.bits.size, UInt<2>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_744 = and(io.in.d.ready, io.in.d.valid)
node _T_745 = or(_T_743, _T_744)
when _T_745 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_51( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [12:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [12:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [12:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [12:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count = 1'h0; // @[Edges.scala:234:25]
wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27]
wire c_first_count = 1'h0; // @[Edges.scala:234:25]
wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21]
wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67]
wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last = 1'h1; // @[Edges.scala:232:33]
wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33]
wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_first_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_first_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_first_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_first_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_first_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_first_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_first_WIRE_2_bits_source = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_first_WIRE_3_bits_source = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_set_wo_ready_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_set_wo_ready_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_set_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_set_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_opcodes_set_interm_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_opcodes_set_interm_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_sizes_set_interm_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_sizes_set_interm_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_opcodes_set_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_opcodes_set_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_sizes_set_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_sizes_set_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_probe_ack_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_probe_ack_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_probe_ack_WIRE_2_bits_source = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_probe_ack_WIRE_3_bits_source = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _same_cycle_resp_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _same_cycle_resp_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _same_cycle_resp_WIRE_2_bits_source = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _same_cycle_resp_WIRE_3_bits_source = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _same_cycle_resp_WIRE_4_bits_source = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _same_cycle_resp_WIRE_5_bits_source = 13'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46]
wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [65537:0] _c_sizes_set_T_1 = 65538'h0; // @[Monitor.scala:768:52]
wire [15:0] _c_opcodes_set_T = 16'h0; // @[Monitor.scala:767:79]
wire [15:0] _c_sizes_set_T = 16'h0; // @[Monitor.scala:768:77]
wire [65538:0] _c_opcodes_set_T_1 = 65539'h0; // @[Monitor.scala:767:54]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [8191:0] _c_set_wo_ready_T = 8192'h1; // @[OneHot.scala:58:35]
wire [8191:0] _c_set_T = 8192'h1; // @[OneHot.scala:58:35]
wire [16447:0] c_opcodes_set = 16448'h0; // @[Monitor.scala:740:34]
wire [16447:0] c_sizes_set = 16448'h0; // @[Monitor.scala:741:34]
wire [4111:0] c_set = 4112'h0; // @[Monitor.scala:738:34]
wire [4111:0] c_set_wo_ready = 4112'h0; // @[Monitor.scala:739:34]
wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76]
wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [12:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [12:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [12:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [12:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [12:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [12:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [12:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [12:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [12:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [12:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [12:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [12:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_4 = source_ok_uncommonBits < 13'h1010; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [27:0] _is_aligned_T = {25'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala:21:{16,24}]
wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [12:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [12:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [12:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [12:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [12:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [12:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [12:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [12:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [12:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}]
wire [12:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_10 = source_ok_uncommonBits_1 < 13'h1010; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_672; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35]
wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
reg a_first_counter; // @[Edges.scala:229:27]
wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28]
wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [1:0] size; // @[Monitor.scala:389:22]
reg [12:0] source; // @[Monitor.scala:390:22]
reg [27:0] address; // @[Monitor.scala:391:22]
wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_745; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35]
wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35]
wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
reg d_first_counter; // @[Edges.scala:229:27]
wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28]
wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg [12:0] source_1; // @[Monitor.scala:541:22]
reg [4111:0] inflight; // @[Monitor.scala:614:27]
reg [16447:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [16447:0] inflight_sizes; // @[Monitor.scala:618:33]
wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
reg a_first_counter_1; // @[Edges.scala:229:27]
wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire [4111:0] a_set; // @[Monitor.scala:626:34]
wire [4111:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [16447:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [16447:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [15:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [15:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [15:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [15:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [15:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [15:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [15:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [15:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [15:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [16447:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [16447:0] _a_opcode_lookup_T_6 = {16444'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [16447:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[16447:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [16447:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [16447:0] _a_size_lookup_T_6 = {16444'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [16447:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[16447:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [8191:0] _GEN_2 = 8192'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [8191:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [8191:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[4111:0] : 4112'h0; // @[OneHot.scala:58:35]
wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_598 ? _a_set_T[4111:0] : 4112'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [15:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [15:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [15:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [65538:0] _a_opcodes_set_T_1 = {65535'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[16447:0] : 16448'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [65537:0] _a_sizes_set_T_1 = {65535'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[16447:0] : 16448'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [4111:0] d_clr; // @[Monitor.scala:664:34]
wire [4111:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [16447:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [16447:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [8191:0] _GEN_5 = 8192'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [8191:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [8191:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [8191:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [8191:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[4111:0] : 4112'h0; // @[OneHot.scala:58:35]
wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_613 ? _d_clr_T[4111:0] : 4112'h0; // @[OneHot.scala:58:35]
wire [65550:0] _d_opcodes_clr_T_5 = 65551'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[16447:0] : 16448'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [65550:0] _d_sizes_clr_T_5 = 65551'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[16447:0] : 16448'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [4111:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [4111:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [4111:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [16447:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [16447:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [16447:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [16447:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [16447:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [16447:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [4111:0] inflight_1; // @[Monitor.scala:726:35]
wire [4111:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [16447:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [16447:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [16447:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [16447:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
reg d_first_counter_2; // @[Edges.scala:229:27]
wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28]
wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [16447:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [16447:0] _c_opcode_lookup_T_6 = {16444'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [16447:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[16447:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [16447:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [16447:0] _c_size_lookup_T_6 = {16444'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [16447:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[16447:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [4111:0] d_clr_1; // @[Monitor.scala:774:34]
wire [4111:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [16447:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [16447:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[4111:0] : 4112'h0; // @[OneHot.scala:58:35]
wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_698 ? _d_clr_T_1[4111:0] : 4112'h0; // @[OneHot.scala:58:35]
wire [65550:0] _d_opcodes_clr_T_11 = 65551'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[16447:0] : 16448'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [65550:0] _d_sizes_clr_T_11 = 65551'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[16447:0] : 16448'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 13'h0; // @[Monitor.scala:36:7, :795:113]
wire [4111:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [4111:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [16447:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [16447:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [16447:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [16447:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_225 :
input clock : Clock
input reset : Reset
output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}}
regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff)
reg value_reg : { symbol : UInt<10>}, clock
connect io.output_prev.key, key_reg
connect io.output_prev.value, value_reg
connect io.output_nxt.key, key_reg
connect io.output_nxt.value, value_reg
connect io.cur_output_keyval.key, key_reg
connect io.cur_output_keyval.value, value_reg
when io.cmd.valid :
node _T = eq(UInt<1>(0h0), io.cmd.bits)
when _T :
connect key_reg, io.input_nxt.key
connect value_reg, io.input_nxt.value
else :
node _T_1 = eq(UInt<1>(0h1), io.cmd.bits)
when _T_1 :
when io.insert_here :
connect key_reg, io.cur_input_keyval.key
connect value_reg, io.cur_input_keyval.value
else :
node _T_2 = geq(key_reg, io.cur_input_keyval.key)
when _T_2 :
connect key_reg, io.input_prev.key
connect value_reg, io.input_prev.value
else :
skip | module PriorityQueueStage_225( // @[ShiftRegisterPriorityQueue.scala:21:7]
input clock, // @[ShiftRegisterPriorityQueue.scala:21:7]
input reset, // @[ShiftRegisterPriorityQueue.scala:21:7]
output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14]
);
wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24]
assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22]
assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30]
always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24]
else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
always @(posedge)
assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module IngressUnit_9 :
input clock : Clock
input reset : Reset
output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[6]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<0>, vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[6]}}}, flip vcalloc_resp : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[6]}}, flip out_credit_available : { `1` : UInt<1>[1], `0` : UInt<1>[6]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[6]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<0>, sa_stall : UInt<0>}, flip block : UInt<1>, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
inst route_buffer of Queue2_Flit_18
connect route_buffer.clock, clock
connect route_buffer.reset, reset
inst route_q of Queue2_RouteComputerResp_9
connect route_q.clock, clock
connect route_q.reset, reset
node _T = eq(UInt<4>(0hc), io.in.bits.egress_id)
node _T_1 = eq(UInt<4>(0he), io.in.bits.egress_id)
node _T_2 = eq(UInt<5>(0h10), io.in.bits.egress_id)
node _T_3 = eq(UInt<5>(0h12), io.in.bits.egress_id)
node _T_4 = or(_T, _T_1)
node _T_5 = or(_T_4, _T_2)
node _T_6 = or(_T_5, _T_3)
node _T_7 = eq(_T_6, UInt<1>(0h0))
node _T_8 = and(io.in.valid, _T_7)
node _T_9 = eq(_T_8, UInt<1>(0h0))
node _T_10 = asUInt(reset)
node _T_11 = eq(_T_10, UInt<1>(0h0))
when _T_11 :
node _T_12 = eq(_T_9, UInt<1>(0h0))
when _T_12 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:30 assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))\n") : printf
assert(clock, _T_9, UInt<1>(0h1), "") : assert
connect route_buffer.io.enq.bits.head, io.in.bits.head
connect route_buffer.io.enq.bits.tail, io.in.bits.tail
connect route_buffer.io.enq.bits.flow.ingress_node, UInt<3>(0h4)
connect route_buffer.io.enq.bits.flow.ingress_node_id, UInt<1>(0h1)
connect route_buffer.io.enq.bits.flow.vnet_id, UInt<1>(0h1)
node _route_buffer_io_enq_bits_flow_egress_node_T = eq(UInt<4>(0hc), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_1 = eq(UInt<4>(0he), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_2 = eq(UInt<5>(0h10), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_3 = eq(UInt<5>(0h12), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_4 = mux(_route_buffer_io_enq_bits_flow_egress_node_T, UInt<4>(0h9), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_1, UInt<4>(0ha), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_2, UInt<4>(0hb), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_3, UInt<4>(0hc), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_8 = or(_route_buffer_io_enq_bits_flow_egress_node_T_4, _route_buffer_io_enq_bits_flow_egress_node_T_5)
node _route_buffer_io_enq_bits_flow_egress_node_T_9 = or(_route_buffer_io_enq_bits_flow_egress_node_T_8, _route_buffer_io_enq_bits_flow_egress_node_T_6)
node _route_buffer_io_enq_bits_flow_egress_node_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_T_9, _route_buffer_io_enq_bits_flow_egress_node_T_7)
wire _route_buffer_io_enq_bits_flow_egress_node_WIRE : UInt<4>
connect _route_buffer_io_enq_bits_flow_egress_node_WIRE, _route_buffer_io_enq_bits_flow_egress_node_T_10
connect route_buffer.io.enq.bits.flow.egress_node, _route_buffer_io_enq_bits_flow_egress_node_WIRE
node _route_buffer_io_enq_bits_flow_egress_node_id_T = eq(UInt<4>(0hc), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = eq(UInt<4>(0he), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = eq(UInt<5>(0h10), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = eq(UInt<5>(0h12), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T, UInt<1>(0h1), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_1, UInt<1>(0h1), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_2, UInt<1>(0h1), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_3, UInt<1>(0h1), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_8 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_4, _route_buffer_io_enq_bits_flow_egress_node_id_T_5)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_9 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_8, _route_buffer_io_enq_bits_flow_egress_node_id_T_6)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_9, _route_buffer_io_enq_bits_flow_egress_node_id_T_7)
wire _route_buffer_io_enq_bits_flow_egress_node_id_WIRE : UInt<1>
connect _route_buffer_io_enq_bits_flow_egress_node_id_WIRE, _route_buffer_io_enq_bits_flow_egress_node_id_T_10
connect route_buffer.io.enq.bits.flow.egress_node_id, _route_buffer_io_enq_bits_flow_egress_node_id_WIRE
connect route_buffer.io.enq.bits.payload, io.in.bits.payload
invalidate route_buffer.io.enq.bits.virt_channel_id
connect io.router_req.bits.src_virt_id, UInt<1>(0h0)
connect io.router_req.bits.flow.egress_node_id, route_buffer.io.enq.bits.flow.egress_node_id
connect io.router_req.bits.flow.egress_node, route_buffer.io.enq.bits.flow.egress_node
connect io.router_req.bits.flow.ingress_node_id, route_buffer.io.enq.bits.flow.ingress_node_id
connect io.router_req.bits.flow.ingress_node, route_buffer.io.enq.bits.flow.ingress_node
connect io.router_req.bits.flow.vnet_id, route_buffer.io.enq.bits.flow.vnet_id
node at_dest = eq(route_buffer.io.enq.bits.flow.egress_node, UInt<3>(0h4))
node _route_buffer_io_enq_valid_T = eq(io.in.bits.head, UInt<1>(0h0))
node _route_buffer_io_enq_valid_T_1 = or(io.router_req.ready, _route_buffer_io_enq_valid_T)
node _route_buffer_io_enq_valid_T_2 = or(_route_buffer_io_enq_valid_T_1, at_dest)
node _route_buffer_io_enq_valid_T_3 = and(io.in.valid, _route_buffer_io_enq_valid_T_2)
connect route_buffer.io.enq.valid, _route_buffer_io_enq_valid_T_3
node _io_router_req_valid_T = and(io.in.valid, route_buffer.io.enq.ready)
node _io_router_req_valid_T_1 = and(_io_router_req_valid_T, io.in.bits.head)
node _io_router_req_valid_T_2 = eq(at_dest, UInt<1>(0h0))
node _io_router_req_valid_T_3 = and(_io_router_req_valid_T_1, _io_router_req_valid_T_2)
connect io.router_req.valid, _io_router_req_valid_T_3
node _io_in_ready_T = eq(io.in.bits.head, UInt<1>(0h0))
node _io_in_ready_T_1 = or(io.router_req.ready, _io_in_ready_T)
node _io_in_ready_T_2 = or(_io_in_ready_T_1, at_dest)
node _io_in_ready_T_3 = and(route_buffer.io.enq.ready, _io_in_ready_T_2)
connect io.in.ready, _io_in_ready_T_3
node _route_q_io_enq_valid_T = and(io.router_req.ready, io.router_req.valid)
connect route_q.io.enq.valid, _route_q_io_enq_valid_T
connect route_q.io.enq.bits.vc_sel.`0`[0], io.router_resp.vc_sel.`0`[0]
connect route_q.io.enq.bits.vc_sel.`0`[1], io.router_resp.vc_sel.`0`[1]
connect route_q.io.enq.bits.vc_sel.`0`[2], io.router_resp.vc_sel.`0`[2]
connect route_q.io.enq.bits.vc_sel.`0`[3], io.router_resp.vc_sel.`0`[3]
connect route_q.io.enq.bits.vc_sel.`0`[4], io.router_resp.vc_sel.`0`[4]
connect route_q.io.enq.bits.vc_sel.`0`[5], io.router_resp.vc_sel.`0`[5]
connect route_q.io.enq.bits.vc_sel.`1`[0], io.router_resp.vc_sel.`1`[0]
node _T_13 = and(io.in.ready, io.in.valid)
node _T_14 = and(_T_13, io.in.bits.head)
node _T_15 = and(_T_14, at_dest)
when _T_15 :
connect route_q.io.enq.valid, UInt<1>(0h1)
connect route_q.io.enq.bits.vc_sel.`0`[0], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[1], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[2], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[3], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[4], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[5], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h0)
node _T_16 = eq(UInt<3>(0h5), io.in.bits.egress_id)
when _T_16 :
connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h1)
node _T_17 = eq(route_q.io.enq.ready, UInt<1>(0h0))
node _T_18 = and(route_q.io.enq.valid, _T_17)
node _T_19 = eq(_T_18, UInt<1>(0h0))
node _T_20 = asUInt(reset)
node _T_21 = eq(_T_20, UInt<1>(0h0))
when _T_21 :
node _T_22 = eq(_T_19, UInt<1>(0h0))
when _T_22 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:73 assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))\n") : printf_1
assert(clock, _T_19, UInt<1>(0h1), "") : assert_1
inst vcalloc_buffer of Queue2_Flit_19
connect vcalloc_buffer.clock, clock
connect vcalloc_buffer.reset, reset
inst vcalloc_q of Queue1_VCAllocResp_9
connect vcalloc_q.clock, clock
connect vcalloc_q.reset, reset
connect vcalloc_buffer.io.enq.bits.virt_channel_id, route_buffer.io.deq.bits.virt_channel_id
connect vcalloc_buffer.io.enq.bits.flow.egress_node_id, route_buffer.io.deq.bits.flow.egress_node_id
connect vcalloc_buffer.io.enq.bits.flow.egress_node, route_buffer.io.deq.bits.flow.egress_node
connect vcalloc_buffer.io.enq.bits.flow.ingress_node_id, route_buffer.io.deq.bits.flow.ingress_node_id
connect vcalloc_buffer.io.enq.bits.flow.ingress_node, route_buffer.io.deq.bits.flow.ingress_node
connect vcalloc_buffer.io.enq.bits.flow.vnet_id, route_buffer.io.deq.bits.flow.vnet_id
connect vcalloc_buffer.io.enq.bits.payload, route_buffer.io.deq.bits.payload
connect vcalloc_buffer.io.enq.bits.tail, route_buffer.io.deq.bits.tail
connect vcalloc_buffer.io.enq.bits.head, route_buffer.io.deq.bits.head
connect io.vcalloc_req.bits.vc_sel.`0`, route_q.io.deq.bits.vc_sel.`0`
connect io.vcalloc_req.bits.vc_sel.`1`, route_q.io.deq.bits.vc_sel.`1`
connect io.vcalloc_req.bits.flow, route_buffer.io.deq.bits.flow
connect io.vcalloc_req.bits.in_vc, UInt<1>(0h0)
node _vcalloc_buffer_io_enq_valid_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _vcalloc_buffer_io_enq_valid_T_1 = or(route_q.io.deq.valid, _vcalloc_buffer_io_enq_valid_T)
node _vcalloc_buffer_io_enq_valid_T_2 = and(route_buffer.io.deq.valid, _vcalloc_buffer_io_enq_valid_T_1)
node _vcalloc_buffer_io_enq_valid_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _vcalloc_buffer_io_enq_valid_T_4 = or(io.vcalloc_req.ready, _vcalloc_buffer_io_enq_valid_T_3)
node _vcalloc_buffer_io_enq_valid_T_5 = and(_vcalloc_buffer_io_enq_valid_T_2, _vcalloc_buffer_io_enq_valid_T_4)
connect vcalloc_buffer.io.enq.valid, _vcalloc_buffer_io_enq_valid_T_5
node _io_vcalloc_req_valid_T = and(route_buffer.io.deq.valid, route_q.io.deq.valid)
node _io_vcalloc_req_valid_T_1 = and(_io_vcalloc_req_valid_T, route_buffer.io.deq.bits.head)
node _io_vcalloc_req_valid_T_2 = and(_io_vcalloc_req_valid_T_1, vcalloc_buffer.io.enq.ready)
node _io_vcalloc_req_valid_T_3 = and(_io_vcalloc_req_valid_T_2, vcalloc_q.io.enq.ready)
connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3
node _route_buffer_io_deq_ready_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _route_buffer_io_deq_ready_T_1 = or(route_q.io.deq.valid, _route_buffer_io_deq_ready_T)
node _route_buffer_io_deq_ready_T_2 = and(vcalloc_buffer.io.enq.ready, _route_buffer_io_deq_ready_T_1)
node _route_buffer_io_deq_ready_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _route_buffer_io_deq_ready_T_4 = or(io.vcalloc_req.ready, _route_buffer_io_deq_ready_T_3)
node _route_buffer_io_deq_ready_T_5 = and(_route_buffer_io_deq_ready_T_2, _route_buffer_io_deq_ready_T_4)
node _route_buffer_io_deq_ready_T_6 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _route_buffer_io_deq_ready_T_7 = or(vcalloc_q.io.enq.ready, _route_buffer_io_deq_ready_T_6)
node _route_buffer_io_deq_ready_T_8 = and(_route_buffer_io_deq_ready_T_5, _route_buffer_io_deq_ready_T_7)
connect route_buffer.io.deq.ready, _route_buffer_io_deq_ready_T_8
node _route_q_io_deq_ready_T = and(route_buffer.io.deq.ready, route_buffer.io.deq.valid)
node _route_q_io_deq_ready_T_1 = and(_route_q_io_deq_ready_T, route_buffer.io.deq.bits.tail)
connect route_q.io.deq.ready, _route_q_io_deq_ready_T_1
node _vcalloc_q_io_enq_valid_T = and(io.vcalloc_req.ready, io.vcalloc_req.valid)
connect vcalloc_q.io.enq.valid, _vcalloc_q_io_enq_valid_T
connect vcalloc_q.io.enq.bits.vc_sel.`0`[0], io.vcalloc_resp.vc_sel.`0`[0]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[1], io.vcalloc_resp.vc_sel.`0`[1]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[2], io.vcalloc_resp.vc_sel.`0`[2]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[3], io.vcalloc_resp.vc_sel.`0`[3]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[4], io.vcalloc_resp.vc_sel.`0`[4]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[5], io.vcalloc_resp.vc_sel.`0`[5]
connect vcalloc_q.io.enq.bits.vc_sel.`1`[0], io.vcalloc_resp.vc_sel.`1`[0]
node _T_23 = eq(vcalloc_q.io.enq.ready, UInt<1>(0h0))
node _T_24 = and(vcalloc_q.io.enq.valid, _T_23)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = asUInt(reset)
node _T_27 = eq(_T_26, UInt<1>(0h0))
when _T_27 :
node _T_28 = eq(_T_25, UInt<1>(0h0))
when _T_28 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:102 assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))\n") : printf_2
assert(clock, _T_25, UInt<1>(0h1), "") : assert_2
connect io.salloc_req[0].bits.vc_sel.`0`, vcalloc_q.io.deq.bits.vc_sel.`0`
connect io.salloc_req[0].bits.vc_sel.`1`, vcalloc_q.io.deq.bits.vc_sel.`1`
connect io.salloc_req[0].bits.tail, vcalloc_buffer.io.deq.bits.tail
node c_lo_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[2], vcalloc_q.io.deq.bits.vc_sel.`0`[1])
node c_lo = cat(c_lo_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[0])
node c_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[5], vcalloc_q.io.deq.bits.vc_sel.`0`[4])
node c_hi = cat(c_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[3])
node _c_T = cat(c_hi, c_lo)
node _c_T_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`1`[0], _c_T)
node c_lo_hi_1 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1])
node c_lo_1 = cat(c_lo_hi_1, io.out_credit_available.`0`[0])
node c_hi_hi_1 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node c_hi_1 = cat(c_hi_hi_1, io.out_credit_available.`0`[3])
node _c_T_2 = cat(c_hi_1, c_lo_1)
node _c_T_3 = cat(io.out_credit_available.`1`[0], _c_T_2)
node _c_T_4 = and(_c_T_1, _c_T_3)
node c = neq(_c_T_4, UInt<1>(0h0))
node _io_salloc_req_0_valid_T = and(vcalloc_buffer.io.deq.valid, vcalloc_q.io.deq.valid)
node _io_salloc_req_0_valid_T_1 = and(_io_salloc_req_0_valid_T, c)
node _io_salloc_req_0_valid_T_2 = eq(io.block, UInt<1>(0h0))
node _io_salloc_req_0_valid_T_3 = and(_io_salloc_req_0_valid_T_1, _io_salloc_req_0_valid_T_2)
connect io.salloc_req[0].valid, _io_salloc_req_0_valid_T_3
node _vcalloc_buffer_io_deq_ready_T = and(io.salloc_req[0].ready, vcalloc_q.io.deq.valid)
node _vcalloc_buffer_io_deq_ready_T_1 = and(_vcalloc_buffer_io_deq_ready_T, c)
node _vcalloc_buffer_io_deq_ready_T_2 = eq(io.block, UInt<1>(0h0))
node _vcalloc_buffer_io_deq_ready_T_3 = and(_vcalloc_buffer_io_deq_ready_T_1, _vcalloc_buffer_io_deq_ready_T_2)
connect vcalloc_buffer.io.deq.ready, _vcalloc_buffer_io_deq_ready_T_3
node _vcalloc_q_io_deq_ready_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid)
node _vcalloc_q_io_deq_ready_T_1 = and(vcalloc_buffer.io.deq.bits.tail, _vcalloc_q_io_deq_ready_T)
connect vcalloc_q.io.deq.ready, _vcalloc_q_io_deq_ready_T_1
reg out_bundle : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}, clock
connect io.out[0], out_bundle
node _out_bundle_valid_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid)
connect out_bundle.valid, _out_bundle_valid_T
connect out_bundle.bits.flit, vcalloc_buffer.io.deq.bits
connect out_bundle.bits.flit.virt_channel_id, UInt<1>(0h0)
node _out_channel_oh_T = or(vcalloc_q.io.deq.bits.vc_sel.`0`[0], vcalloc_q.io.deq.bits.vc_sel.`0`[1])
node _out_channel_oh_T_1 = or(_out_channel_oh_T, vcalloc_q.io.deq.bits.vc_sel.`0`[2])
node _out_channel_oh_T_2 = or(_out_channel_oh_T_1, vcalloc_q.io.deq.bits.vc_sel.`0`[3])
node _out_channel_oh_T_3 = or(_out_channel_oh_T_2, vcalloc_q.io.deq.bits.vc_sel.`0`[4])
node out_channel_oh_0 = or(_out_channel_oh_T_3, vcalloc_q.io.deq.bits.vc_sel.`0`[5])
node out_bundle_bits_out_virt_channel_lo_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[2], vcalloc_q.io.deq.bits.vc_sel.`0`[1])
node out_bundle_bits_out_virt_channel_lo = cat(out_bundle_bits_out_virt_channel_lo_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[0])
node out_bundle_bits_out_virt_channel_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[5], vcalloc_q.io.deq.bits.vc_sel.`0`[4])
node out_bundle_bits_out_virt_channel_hi = cat(out_bundle_bits_out_virt_channel_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[3])
node _out_bundle_bits_out_virt_channel_T = cat(out_bundle_bits_out_virt_channel_hi, out_bundle_bits_out_virt_channel_lo)
node out_bundle_bits_out_virt_channel_hi_1 = bits(_out_bundle_bits_out_virt_channel_T, 5, 4)
node out_bundle_bits_out_virt_channel_lo_1 = bits(_out_bundle_bits_out_virt_channel_T, 3, 0)
node _out_bundle_bits_out_virt_channel_T_1 = orr(out_bundle_bits_out_virt_channel_hi_1)
node _out_bundle_bits_out_virt_channel_T_2 = or(out_bundle_bits_out_virt_channel_hi_1, out_bundle_bits_out_virt_channel_lo_1)
node out_bundle_bits_out_virt_channel_hi_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 3, 2)
node out_bundle_bits_out_virt_channel_lo_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 1, 0)
node _out_bundle_bits_out_virt_channel_T_3 = orr(out_bundle_bits_out_virt_channel_hi_2)
node _out_bundle_bits_out_virt_channel_T_4 = or(out_bundle_bits_out_virt_channel_hi_2, out_bundle_bits_out_virt_channel_lo_2)
node _out_bundle_bits_out_virt_channel_T_5 = bits(_out_bundle_bits_out_virt_channel_T_4, 1, 1)
node _out_bundle_bits_out_virt_channel_T_6 = cat(_out_bundle_bits_out_virt_channel_T_3, _out_bundle_bits_out_virt_channel_T_5)
node _out_bundle_bits_out_virt_channel_T_7 = cat(_out_bundle_bits_out_virt_channel_T_1, _out_bundle_bits_out_virt_channel_T_6)
node _out_bundle_bits_out_virt_channel_T_8 = mux(out_channel_oh_0, _out_bundle_bits_out_virt_channel_T_7, UInt<1>(0h0))
node _out_bundle_bits_out_virt_channel_T_9 = mux(vcalloc_q.io.deq.bits.vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0))
node _out_bundle_bits_out_virt_channel_T_10 = or(_out_bundle_bits_out_virt_channel_T_8, _out_bundle_bits_out_virt_channel_T_9)
wire _out_bundle_bits_out_virt_channel_WIRE : UInt<3>
connect _out_bundle_bits_out_virt_channel_WIRE, _out_bundle_bits_out_virt_channel_T_10
connect out_bundle.bits.out_virt_channel, _out_bundle_bits_out_virt_channel_WIRE
node _io_debug_va_stall_T = eq(io.vcalloc_req.ready, UInt<1>(0h0))
node _io_debug_va_stall_T_1 = and(io.vcalloc_req.valid, _io_debug_va_stall_T)
connect io.debug.va_stall, _io_debug_va_stall_T_1
node _io_debug_sa_stall_T = eq(io.salloc_req[0].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_1 = and(io.salloc_req[0].valid, _io_debug_sa_stall_T)
connect io.debug.sa_stall, _io_debug_sa_stall_T_1 | module IngressUnit_9( // @[IngressUnit.scala:11:7]
input clock, // @[IngressUnit.scala:11:7]
input reset, // @[IngressUnit.scala:11:7]
input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_4, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_5, // @[IngressUnit.scala:24:14]
input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_1, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_2, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_3, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_4, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_5, // @[IngressUnit.scala:24:14]
input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14]
output io_out_0_valid, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14]
output [72:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14]
output [1:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14]
output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14]
output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14]
output [3:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14]
output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14]
output [2:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14]
output io_in_ready, // @[IngressUnit.scala:24:14]
input io_in_valid, // @[IngressUnit.scala:24:14]
input io_in_bits_head, // @[IngressUnit.scala:24:14]
input io_in_bits_tail, // @[IngressUnit.scala:24:14]
input [72:0] io_in_bits_payload, // @[IngressUnit.scala:24:14]
input [4:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14]
);
wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_3; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_4; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_5; // @[IngressUnit.scala:76:25]
wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_bits_head; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30]
wire [72:0] _vcalloc_buffer_io_deq_bits_payload; // @[IngressUnit.scala:75:30]
wire [1:0] _vcalloc_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:75:30]
wire [3:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:75:30]
wire [1:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:75:30]
wire [3:0] _vcalloc_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:75:30]
wire [1:0] _vcalloc_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:75:30]
wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23]
wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23]
wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28]
wire [72:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28]
wire [1:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28]
wire [3:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28]
wire [1:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28]
wire [3:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28]
wire [1:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28]
wire [2:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = io_in_bits_egress_id == 5'hC; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = io_in_bits_egress_id == 5'hE; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = io_in_bits_egress_id == 5'h10; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = io_in_bits_egress_id == 5'h12; // @[IngressUnit.scala:30:72]
wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_T_10 = (_route_buffer_io_enq_bits_flow_egress_node_id_T_4 ? 4'h9 : 4'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_5 ? 4'hA : 4'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_6 ? 4'hB : 4'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_7 ? 4'hC : 4'h0); // @[Mux.scala:30:73]
wire _GEN = _route_buffer_io_enq_ready & io_in_valid & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_10 == 4'h4; // @[Mux.scala:30:73]
wire route_q_io_enq_valid = _GEN | io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_10 != 4'h4; // @[Mux.scala:30:73]
wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}]
wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid | ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready | ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready | ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29]
wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_39 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<6>(0h20))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 2, 0)
node _source_ok_T_25 = shr(io.in.a.bits.source, 3)
node _source_ok_T_26 = eq(_source_ok_T_25, UInt<2>(0h3))
node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27)
node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<3>(0h7))
node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29)
node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 2, 0)
node _source_ok_T_31 = shr(io.in.a.bits.source, 3)
node _source_ok_T_32 = eq(_source_ok_T_31, UInt<2>(0h2))
node _source_ok_T_33 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_34 = and(_source_ok_T_32, _source_ok_T_33)
node _source_ok_T_35 = leq(source_ok_uncommonBits_5, UInt<3>(0h7))
node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35)
node _source_ok_uncommonBits_T_6 = or(io.in.a.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 2, 0)
node _source_ok_T_37 = shr(io.in.a.bits.source, 3)
node _source_ok_T_38 = eq(_source_ok_T_37, UInt<4>(0h8))
node _source_ok_T_39 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39)
node _source_ok_T_41 = leq(source_ok_uncommonBits_6, UInt<3>(0h4))
node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41)
node _source_ok_T_43 = eq(io.in.a.bits.source, UInt<7>(0h48))
wire _source_ok_WIRE : UInt<1>[9]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_30
connect _source_ok_WIRE[6], _source_ok_T_36
connect _source_ok_WIRE[7], _source_ok_T_42
connect _source_ok_WIRE[8], _source_ok_T_43
node _source_ok_T_44 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_45 = or(_source_ok_T_44, _source_ok_WIRE[2])
node _source_ok_T_46 = or(_source_ok_T_45, _source_ok_WIRE[3])
node _source_ok_T_47 = or(_source_ok_T_46, _source_ok_WIRE[4])
node _source_ok_T_48 = or(_source_ok_T_47, _source_ok_WIRE[5])
node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[6])
node _source_ok_T_50 = or(_source_ok_T_49, _source_ok_WIRE[7])
node source_ok = or(_source_ok_T_50, _source_ok_WIRE[8])
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<4>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 3, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<3>(0h4))
node mask_sub_sub_sub_size = bits(mask_sizeOH, 3, 3)
node mask_sub_sub_sub_bit = bits(io.in.a.bits.address, 3, 3)
node mask_sub_sub_sub_nbit = eq(mask_sub_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit)
node _mask_sub_sub_sub_acc_T = and(mask_sub_sub_sub_size, mask_sub_sub_sub_0_2)
node mask_sub_sub_sub_0_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T)
node mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_sub_bit)
node _mask_sub_sub_sub_acc_T_1 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_1_2)
node mask_sub_sub_sub_1_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T_1)
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_sub_2_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_nbit)
node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size, mask_sub_sub_2_2)
node mask_sub_sub_2_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_2)
node mask_sub_sub_3_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_bit)
node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size, mask_sub_sub_3_2)
node mask_sub_sub_3_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_3)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_sub_4_2 = and(mask_sub_sub_2_2, mask_sub_nbit)
node _mask_sub_acc_T_4 = and(mask_sub_size, mask_sub_4_2)
node mask_sub_4_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_4)
node mask_sub_5_2 = and(mask_sub_sub_2_2, mask_sub_bit)
node _mask_sub_acc_T_5 = and(mask_sub_size, mask_sub_5_2)
node mask_sub_5_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_5)
node mask_sub_6_2 = and(mask_sub_sub_3_2, mask_sub_nbit)
node _mask_sub_acc_T_6 = and(mask_sub_size, mask_sub_6_2)
node mask_sub_6_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_6)
node mask_sub_7_2 = and(mask_sub_sub_3_2, mask_sub_bit)
node _mask_sub_acc_T_7 = and(mask_sub_size, mask_sub_7_2)
node mask_sub_7_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_7)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_eq_8 = and(mask_sub_4_2, mask_nbit)
node _mask_acc_T_8 = and(mask_size, mask_eq_8)
node mask_acc_8 = or(mask_sub_4_1, _mask_acc_T_8)
node mask_eq_9 = and(mask_sub_4_2, mask_bit)
node _mask_acc_T_9 = and(mask_size, mask_eq_9)
node mask_acc_9 = or(mask_sub_4_1, _mask_acc_T_9)
node mask_eq_10 = and(mask_sub_5_2, mask_nbit)
node _mask_acc_T_10 = and(mask_size, mask_eq_10)
node mask_acc_10 = or(mask_sub_5_1, _mask_acc_T_10)
node mask_eq_11 = and(mask_sub_5_2, mask_bit)
node _mask_acc_T_11 = and(mask_size, mask_eq_11)
node mask_acc_11 = or(mask_sub_5_1, _mask_acc_T_11)
node mask_eq_12 = and(mask_sub_6_2, mask_nbit)
node _mask_acc_T_12 = and(mask_size, mask_eq_12)
node mask_acc_12 = or(mask_sub_6_1, _mask_acc_T_12)
node mask_eq_13 = and(mask_sub_6_2, mask_bit)
node _mask_acc_T_13 = and(mask_size, mask_eq_13)
node mask_acc_13 = or(mask_sub_6_1, _mask_acc_T_13)
node mask_eq_14 = and(mask_sub_7_2, mask_nbit)
node _mask_acc_T_14 = and(mask_size, mask_eq_14)
node mask_acc_14 = or(mask_sub_7_1, _mask_acc_T_14)
node mask_eq_15 = and(mask_sub_7_2, mask_bit)
node _mask_acc_T_15 = and(mask_size, mask_eq_15)
node mask_acc_15 = or(mask_sub_7_1, _mask_acc_T_15)
node mask_lo_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo_lo = cat(mask_lo_lo_hi, mask_lo_lo_lo)
node mask_lo_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_lo_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_lo_hi = cat(mask_lo_hi_hi, mask_lo_hi_lo)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo_lo = cat(mask_acc_9, mask_acc_8)
node mask_hi_lo_hi = cat(mask_acc_11, mask_acc_10)
node mask_hi_lo = cat(mask_hi_lo_hi, mask_hi_lo_lo)
node mask_hi_hi_lo = cat(mask_acc_13, mask_acc_12)
node mask_hi_hi_hi = cat(mask_acc_15, mask_acc_14)
node mask_hi_hi = cat(mask_hi_hi_hi, mask_hi_hi_lo)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<1>(0h1))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<2>(0h2))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<2>(0h3))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 2, 0)
node _T_64 = shr(io.in.a.bits.source, 3)
node _T_65 = eq(_T_64, UInt<2>(0h3))
node _T_66 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_67 = and(_T_65, _T_66)
node _T_68 = leq(uncommonBits_4, UInt<3>(0h7))
node _T_69 = and(_T_67, _T_68)
node _T_70 = eq(_T_69, UInt<1>(0h0))
node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_72 = cvt(_T_71)
node _T_73 = and(_T_72, asSInt(UInt<1>(0h0)))
node _T_74 = asSInt(_T_73)
node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0)))
node _T_76 = or(_T_70, _T_75)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 2, 0)
node _T_77 = shr(io.in.a.bits.source, 3)
node _T_78 = eq(_T_77, UInt<2>(0h2))
node _T_79 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_80 = and(_T_78, _T_79)
node _T_81 = leq(uncommonBits_5, UInt<3>(0h7))
node _T_82 = and(_T_80, _T_81)
node _T_83 = eq(_T_82, UInt<1>(0h0))
node _T_84 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_85 = cvt(_T_84)
node _T_86 = and(_T_85, asSInt(UInt<1>(0h0)))
node _T_87 = asSInt(_T_86)
node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0)))
node _T_89 = or(_T_83, _T_88)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 2, 0)
node _T_90 = shr(io.in.a.bits.source, 3)
node _T_91 = eq(_T_90, UInt<4>(0h8))
node _T_92 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_93 = and(_T_91, _T_92)
node _T_94 = leq(uncommonBits_6, UInt<3>(0h4))
node _T_95 = and(_T_93, _T_94)
node _T_96 = eq(_T_95, UInt<1>(0h0))
node _T_97 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_98 = cvt(_T_97)
node _T_99 = and(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = asSInt(_T_99)
node _T_101 = eq(_T_100, asSInt(UInt<1>(0h0)))
node _T_102 = or(_T_96, _T_101)
node _T_103 = eq(io.in.a.bits.source, UInt<7>(0h48))
node _T_104 = eq(_T_103, UInt<1>(0h0))
node _T_105 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_106 = cvt(_T_105)
node _T_107 = and(_T_106, asSInt(UInt<1>(0h0)))
node _T_108 = asSInt(_T_107)
node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0)))
node _T_110 = or(_T_104, _T_109)
node _T_111 = and(_T_11, _T_24)
node _T_112 = and(_T_111, _T_37)
node _T_113 = and(_T_112, _T_50)
node _T_114 = and(_T_113, _T_63)
node _T_115 = and(_T_114, _T_76)
node _T_116 = and(_T_115, _T_89)
node _T_117 = and(_T_116, _T_102)
node _T_118 = and(_T_117, _T_110)
node _T_119 = asUInt(reset)
node _T_120 = eq(_T_119, UInt<1>(0h0))
when _T_120 :
node _T_121 = eq(_T_118, UInt<1>(0h0))
when _T_121 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_118, UInt<1>(0h1), "") : assert_1
node _T_122 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_122 :
node _T_123 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_124 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_125 = and(_T_123, _T_124)
node _T_126 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_127 = shr(io.in.a.bits.source, 2)
node _T_128 = eq(_T_127, UInt<1>(0h0))
node _T_129 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_130 = and(_T_128, _T_129)
node _T_131 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_132 = and(_T_130, _T_131)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_133 = shr(io.in.a.bits.source, 2)
node _T_134 = eq(_T_133, UInt<1>(0h1))
node _T_135 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_136 = and(_T_134, _T_135)
node _T_137 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_138 = and(_T_136, _T_137)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_139 = shr(io.in.a.bits.source, 2)
node _T_140 = eq(_T_139, UInt<2>(0h2))
node _T_141 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_142 = and(_T_140, _T_141)
node _T_143 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_144 = and(_T_142, _T_143)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_145 = shr(io.in.a.bits.source, 2)
node _T_146 = eq(_T_145, UInt<2>(0h3))
node _T_147 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_148 = and(_T_146, _T_147)
node _T_149 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_150 = and(_T_148, _T_149)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 2, 0)
node _T_151 = shr(io.in.a.bits.source, 3)
node _T_152 = eq(_T_151, UInt<2>(0h3))
node _T_153 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_154 = and(_T_152, _T_153)
node _T_155 = leq(uncommonBits_11, UInt<3>(0h7))
node _T_156 = and(_T_154, _T_155)
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 2, 0)
node _T_157 = shr(io.in.a.bits.source, 3)
node _T_158 = eq(_T_157, UInt<2>(0h2))
node _T_159 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_160 = and(_T_158, _T_159)
node _T_161 = leq(uncommonBits_12, UInt<3>(0h7))
node _T_162 = and(_T_160, _T_161)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 2, 0)
node _T_163 = shr(io.in.a.bits.source, 3)
node _T_164 = eq(_T_163, UInt<4>(0h8))
node _T_165 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_166 = and(_T_164, _T_165)
node _T_167 = leq(uncommonBits_13, UInt<3>(0h4))
node _T_168 = and(_T_166, _T_167)
node _T_169 = eq(io.in.a.bits.source, UInt<7>(0h48))
node _T_170 = or(_T_126, _T_132)
node _T_171 = or(_T_170, _T_138)
node _T_172 = or(_T_171, _T_144)
node _T_173 = or(_T_172, _T_150)
node _T_174 = or(_T_173, _T_156)
node _T_175 = or(_T_174, _T_162)
node _T_176 = or(_T_175, _T_168)
node _T_177 = or(_T_176, _T_169)
node _T_178 = and(_T_125, _T_177)
node _T_179 = or(UInt<1>(0h0), _T_178)
node _T_180 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_181 = or(UInt<1>(0h0), _T_180)
node _T_182 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_183 = cvt(_T_182)
node _T_184 = and(_T_183, asSInt(UInt<17>(0h10000)))
node _T_185 = asSInt(_T_184)
node _T_186 = eq(_T_185, asSInt(UInt<1>(0h0)))
node _T_187 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_188 = cvt(_T_187)
node _T_189 = and(_T_188, asSInt(UInt<29>(0h10000000)))
node _T_190 = asSInt(_T_189)
node _T_191 = eq(_T_190, asSInt(UInt<1>(0h0)))
node _T_192 = or(_T_186, _T_191)
node _T_193 = and(_T_181, _T_192)
node _T_194 = or(UInt<1>(0h0), _T_193)
node _T_195 = and(_T_179, _T_194)
node _T_196 = asUInt(reset)
node _T_197 = eq(_T_196, UInt<1>(0h0))
when _T_197 :
node _T_198 = eq(_T_195, UInt<1>(0h0))
when _T_198 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_195, UInt<1>(0h1), "") : assert_2
node _T_199 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_200 = shr(io.in.a.bits.source, 2)
node _T_201 = eq(_T_200, UInt<1>(0h0))
node _T_202 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_203 = and(_T_201, _T_202)
node _T_204 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_205 = and(_T_203, _T_204)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_206 = shr(io.in.a.bits.source, 2)
node _T_207 = eq(_T_206, UInt<1>(0h1))
node _T_208 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_209 = and(_T_207, _T_208)
node _T_210 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_211 = and(_T_209, _T_210)
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_212 = shr(io.in.a.bits.source, 2)
node _T_213 = eq(_T_212, UInt<2>(0h2))
node _T_214 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_215 = and(_T_213, _T_214)
node _T_216 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_217 = and(_T_215, _T_216)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_218 = shr(io.in.a.bits.source, 2)
node _T_219 = eq(_T_218, UInt<2>(0h3))
node _T_220 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_221 = and(_T_219, _T_220)
node _T_222 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_223 = and(_T_221, _T_222)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 2, 0)
node _T_224 = shr(io.in.a.bits.source, 3)
node _T_225 = eq(_T_224, UInt<2>(0h3))
node _T_226 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_227 = and(_T_225, _T_226)
node _T_228 = leq(uncommonBits_18, UInt<3>(0h7))
node _T_229 = and(_T_227, _T_228)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 2, 0)
node _T_230 = shr(io.in.a.bits.source, 3)
node _T_231 = eq(_T_230, UInt<2>(0h2))
node _T_232 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_233 = and(_T_231, _T_232)
node _T_234 = leq(uncommonBits_19, UInt<3>(0h7))
node _T_235 = and(_T_233, _T_234)
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 2, 0)
node _T_236 = shr(io.in.a.bits.source, 3)
node _T_237 = eq(_T_236, UInt<4>(0h8))
node _T_238 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_239 = and(_T_237, _T_238)
node _T_240 = leq(uncommonBits_20, UInt<3>(0h4))
node _T_241 = and(_T_239, _T_240)
node _T_242 = eq(io.in.a.bits.source, UInt<7>(0h48))
wire _WIRE : UInt<1>[9]
connect _WIRE[0], _T_199
connect _WIRE[1], _T_205
connect _WIRE[2], _T_211
connect _WIRE[3], _T_217
connect _WIRE[4], _T_223
connect _WIRE[5], _T_229
connect _WIRE[6], _T_235
connect _WIRE[7], _T_241
connect _WIRE[8], _T_242
node _T_243 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_244 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_245 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_246 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_247 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_248 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_249 = mux(_WIRE[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_250 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_251 = mux(_WIRE[7], _T_243, UInt<1>(0h0))
node _T_252 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_253 = or(_T_244, _T_245)
node _T_254 = or(_T_253, _T_246)
node _T_255 = or(_T_254, _T_247)
node _T_256 = or(_T_255, _T_248)
node _T_257 = or(_T_256, _T_249)
node _T_258 = or(_T_257, _T_250)
node _T_259 = or(_T_258, _T_251)
node _T_260 = or(_T_259, _T_252)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_260
node _T_261 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_262 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_263 = and(_T_261, _T_262)
node _T_264 = or(UInt<1>(0h0), _T_263)
node _T_265 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_266 = cvt(_T_265)
node _T_267 = and(_T_266, asSInt(UInt<17>(0h10000)))
node _T_268 = asSInt(_T_267)
node _T_269 = eq(_T_268, asSInt(UInt<1>(0h0)))
node _T_270 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_271 = cvt(_T_270)
node _T_272 = and(_T_271, asSInt(UInt<29>(0h10000000)))
node _T_273 = asSInt(_T_272)
node _T_274 = eq(_T_273, asSInt(UInt<1>(0h0)))
node _T_275 = or(_T_269, _T_274)
node _T_276 = and(_T_264, _T_275)
node _T_277 = or(UInt<1>(0h0), _T_276)
node _T_278 = and(_WIRE_1, _T_277)
node _T_279 = asUInt(reset)
node _T_280 = eq(_T_279, UInt<1>(0h0))
when _T_280 :
node _T_281 = eq(_T_278, UInt<1>(0h0))
when _T_281 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_278, UInt<1>(0h1), "") : assert_3
node _T_282 = asUInt(reset)
node _T_283 = eq(_T_282, UInt<1>(0h0))
when _T_283 :
node _T_284 = eq(source_ok, UInt<1>(0h0))
when _T_284 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_285 = geq(io.in.a.bits.size, UInt<3>(0h4))
node _T_286 = asUInt(reset)
node _T_287 = eq(_T_286, UInt<1>(0h0))
when _T_287 :
node _T_288 = eq(_T_285, UInt<1>(0h0))
when _T_288 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_285, UInt<1>(0h1), "") : assert_5
node _T_289 = asUInt(reset)
node _T_290 = eq(_T_289, UInt<1>(0h0))
when _T_290 :
node _T_291 = eq(is_aligned, UInt<1>(0h0))
when _T_291 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_292 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_293 = asUInt(reset)
node _T_294 = eq(_T_293, UInt<1>(0h0))
when _T_294 :
node _T_295 = eq(_T_292, UInt<1>(0h0))
when _T_295 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_292, UInt<1>(0h1), "") : assert_7
node _T_296 = not(io.in.a.bits.mask)
node _T_297 = eq(_T_296, UInt<1>(0h0))
node _T_298 = asUInt(reset)
node _T_299 = eq(_T_298, UInt<1>(0h0))
when _T_299 :
node _T_300 = eq(_T_297, UInt<1>(0h0))
when _T_300 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_297, UInt<1>(0h1), "") : assert_8
node _T_301 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_302 = asUInt(reset)
node _T_303 = eq(_T_302, UInt<1>(0h0))
when _T_303 :
node _T_304 = eq(_T_301, UInt<1>(0h0))
when _T_304 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_301, UInt<1>(0h1), "") : assert_9
node _T_305 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_305 :
node _T_306 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_307 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_308 = and(_T_306, _T_307)
node _T_309 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_310 = shr(io.in.a.bits.source, 2)
node _T_311 = eq(_T_310, UInt<1>(0h0))
node _T_312 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_313 = and(_T_311, _T_312)
node _T_314 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_315 = and(_T_313, _T_314)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_316 = shr(io.in.a.bits.source, 2)
node _T_317 = eq(_T_316, UInt<1>(0h1))
node _T_318 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_319 = and(_T_317, _T_318)
node _T_320 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_321 = and(_T_319, _T_320)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_322 = shr(io.in.a.bits.source, 2)
node _T_323 = eq(_T_322, UInt<2>(0h2))
node _T_324 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_325 = and(_T_323, _T_324)
node _T_326 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_327 = and(_T_325, _T_326)
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_328 = shr(io.in.a.bits.source, 2)
node _T_329 = eq(_T_328, UInt<2>(0h3))
node _T_330 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_331 = and(_T_329, _T_330)
node _T_332 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_333 = and(_T_331, _T_332)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 2, 0)
node _T_334 = shr(io.in.a.bits.source, 3)
node _T_335 = eq(_T_334, UInt<2>(0h3))
node _T_336 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_337 = and(_T_335, _T_336)
node _T_338 = leq(uncommonBits_25, UInt<3>(0h7))
node _T_339 = and(_T_337, _T_338)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 2, 0)
node _T_340 = shr(io.in.a.bits.source, 3)
node _T_341 = eq(_T_340, UInt<2>(0h2))
node _T_342 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_343 = and(_T_341, _T_342)
node _T_344 = leq(uncommonBits_26, UInt<3>(0h7))
node _T_345 = and(_T_343, _T_344)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 2, 0)
node _T_346 = shr(io.in.a.bits.source, 3)
node _T_347 = eq(_T_346, UInt<4>(0h8))
node _T_348 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_349 = and(_T_347, _T_348)
node _T_350 = leq(uncommonBits_27, UInt<3>(0h4))
node _T_351 = and(_T_349, _T_350)
node _T_352 = eq(io.in.a.bits.source, UInt<7>(0h48))
node _T_353 = or(_T_309, _T_315)
node _T_354 = or(_T_353, _T_321)
node _T_355 = or(_T_354, _T_327)
node _T_356 = or(_T_355, _T_333)
node _T_357 = or(_T_356, _T_339)
node _T_358 = or(_T_357, _T_345)
node _T_359 = or(_T_358, _T_351)
node _T_360 = or(_T_359, _T_352)
node _T_361 = and(_T_308, _T_360)
node _T_362 = or(UInt<1>(0h0), _T_361)
node _T_363 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_364 = or(UInt<1>(0h0), _T_363)
node _T_365 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_366 = cvt(_T_365)
node _T_367 = and(_T_366, asSInt(UInt<17>(0h10000)))
node _T_368 = asSInt(_T_367)
node _T_369 = eq(_T_368, asSInt(UInt<1>(0h0)))
node _T_370 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_371 = cvt(_T_370)
node _T_372 = and(_T_371, asSInt(UInt<29>(0h10000000)))
node _T_373 = asSInt(_T_372)
node _T_374 = eq(_T_373, asSInt(UInt<1>(0h0)))
node _T_375 = or(_T_369, _T_374)
node _T_376 = and(_T_364, _T_375)
node _T_377 = or(UInt<1>(0h0), _T_376)
node _T_378 = and(_T_362, _T_377)
node _T_379 = asUInt(reset)
node _T_380 = eq(_T_379, UInt<1>(0h0))
when _T_380 :
node _T_381 = eq(_T_378, UInt<1>(0h0))
when _T_381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_378, UInt<1>(0h1), "") : assert_10
node _T_382 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_383 = shr(io.in.a.bits.source, 2)
node _T_384 = eq(_T_383, UInt<1>(0h0))
node _T_385 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_386 = and(_T_384, _T_385)
node _T_387 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_388 = and(_T_386, _T_387)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0)
node _T_389 = shr(io.in.a.bits.source, 2)
node _T_390 = eq(_T_389, UInt<1>(0h1))
node _T_391 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_392 = and(_T_390, _T_391)
node _T_393 = leq(uncommonBits_29, UInt<2>(0h3))
node _T_394 = and(_T_392, _T_393)
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_395 = shr(io.in.a.bits.source, 2)
node _T_396 = eq(_T_395, UInt<2>(0h2))
node _T_397 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_398 = and(_T_396, _T_397)
node _T_399 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_400 = and(_T_398, _T_399)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_401 = shr(io.in.a.bits.source, 2)
node _T_402 = eq(_T_401, UInt<2>(0h3))
node _T_403 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_404 = and(_T_402, _T_403)
node _T_405 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_406 = and(_T_404, _T_405)
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 2, 0)
node _T_407 = shr(io.in.a.bits.source, 3)
node _T_408 = eq(_T_407, UInt<2>(0h3))
node _T_409 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_410 = and(_T_408, _T_409)
node _T_411 = leq(uncommonBits_32, UInt<3>(0h7))
node _T_412 = and(_T_410, _T_411)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 2, 0)
node _T_413 = shr(io.in.a.bits.source, 3)
node _T_414 = eq(_T_413, UInt<2>(0h2))
node _T_415 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_416 = and(_T_414, _T_415)
node _T_417 = leq(uncommonBits_33, UInt<3>(0h7))
node _T_418 = and(_T_416, _T_417)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 2, 0)
node _T_419 = shr(io.in.a.bits.source, 3)
node _T_420 = eq(_T_419, UInt<4>(0h8))
node _T_421 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_422 = and(_T_420, _T_421)
node _T_423 = leq(uncommonBits_34, UInt<3>(0h4))
node _T_424 = and(_T_422, _T_423)
node _T_425 = eq(io.in.a.bits.source, UInt<7>(0h48))
wire _WIRE_2 : UInt<1>[9]
connect _WIRE_2[0], _T_382
connect _WIRE_2[1], _T_388
connect _WIRE_2[2], _T_394
connect _WIRE_2[3], _T_400
connect _WIRE_2[4], _T_406
connect _WIRE_2[5], _T_412
connect _WIRE_2[6], _T_418
connect _WIRE_2[7], _T_424
connect _WIRE_2[8], _T_425
node _T_426 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_427 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_428 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_429 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_430 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_431 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_432 = mux(_WIRE_2[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_433 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_434 = mux(_WIRE_2[7], _T_426, UInt<1>(0h0))
node _T_435 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_436 = or(_T_427, _T_428)
node _T_437 = or(_T_436, _T_429)
node _T_438 = or(_T_437, _T_430)
node _T_439 = or(_T_438, _T_431)
node _T_440 = or(_T_439, _T_432)
node _T_441 = or(_T_440, _T_433)
node _T_442 = or(_T_441, _T_434)
node _T_443 = or(_T_442, _T_435)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_443
node _T_444 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_445 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_446 = and(_T_444, _T_445)
node _T_447 = or(UInt<1>(0h0), _T_446)
node _T_448 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_449 = cvt(_T_448)
node _T_450 = and(_T_449, asSInt(UInt<17>(0h10000)))
node _T_451 = asSInt(_T_450)
node _T_452 = eq(_T_451, asSInt(UInt<1>(0h0)))
node _T_453 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_454 = cvt(_T_453)
node _T_455 = and(_T_454, asSInt(UInt<29>(0h10000000)))
node _T_456 = asSInt(_T_455)
node _T_457 = eq(_T_456, asSInt(UInt<1>(0h0)))
node _T_458 = or(_T_452, _T_457)
node _T_459 = and(_T_447, _T_458)
node _T_460 = or(UInt<1>(0h0), _T_459)
node _T_461 = and(_WIRE_3, _T_460)
node _T_462 = asUInt(reset)
node _T_463 = eq(_T_462, UInt<1>(0h0))
when _T_463 :
node _T_464 = eq(_T_461, UInt<1>(0h0))
when _T_464 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_461, UInt<1>(0h1), "") : assert_11
node _T_465 = asUInt(reset)
node _T_466 = eq(_T_465, UInt<1>(0h0))
when _T_466 :
node _T_467 = eq(source_ok, UInt<1>(0h0))
when _T_467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_468 = geq(io.in.a.bits.size, UInt<3>(0h4))
node _T_469 = asUInt(reset)
node _T_470 = eq(_T_469, UInt<1>(0h0))
when _T_470 :
node _T_471 = eq(_T_468, UInt<1>(0h0))
when _T_471 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_468, UInt<1>(0h1), "") : assert_13
node _T_472 = asUInt(reset)
node _T_473 = eq(_T_472, UInt<1>(0h0))
when _T_473 :
node _T_474 = eq(is_aligned, UInt<1>(0h0))
when _T_474 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_475 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_476 = asUInt(reset)
node _T_477 = eq(_T_476, UInt<1>(0h0))
when _T_477 :
node _T_478 = eq(_T_475, UInt<1>(0h0))
when _T_478 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_475, UInt<1>(0h1), "") : assert_15
node _T_479 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_480 = asUInt(reset)
node _T_481 = eq(_T_480, UInt<1>(0h0))
when _T_481 :
node _T_482 = eq(_T_479, UInt<1>(0h0))
when _T_482 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_479, UInt<1>(0h1), "") : assert_16
node _T_483 = not(io.in.a.bits.mask)
node _T_484 = eq(_T_483, UInt<1>(0h0))
node _T_485 = asUInt(reset)
node _T_486 = eq(_T_485, UInt<1>(0h0))
when _T_486 :
node _T_487 = eq(_T_484, UInt<1>(0h0))
when _T_487 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_484, UInt<1>(0h1), "") : assert_17
node _T_488 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_489 = asUInt(reset)
node _T_490 = eq(_T_489, UInt<1>(0h0))
when _T_490 :
node _T_491 = eq(_T_488, UInt<1>(0h0))
when _T_491 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_488, UInt<1>(0h1), "") : assert_18
node _T_492 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_492 :
node _T_493 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_494 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_495 = and(_T_493, _T_494)
node _T_496 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_497 = shr(io.in.a.bits.source, 2)
node _T_498 = eq(_T_497, UInt<1>(0h0))
node _T_499 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_500 = and(_T_498, _T_499)
node _T_501 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_502 = and(_T_500, _T_501)
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_503 = shr(io.in.a.bits.source, 2)
node _T_504 = eq(_T_503, UInt<1>(0h1))
node _T_505 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_506 = and(_T_504, _T_505)
node _T_507 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_508 = and(_T_506, _T_507)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_509 = shr(io.in.a.bits.source, 2)
node _T_510 = eq(_T_509, UInt<2>(0h2))
node _T_511 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_512 = and(_T_510, _T_511)
node _T_513 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_514 = and(_T_512, _T_513)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_515 = shr(io.in.a.bits.source, 2)
node _T_516 = eq(_T_515, UInt<2>(0h3))
node _T_517 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_518 = and(_T_516, _T_517)
node _T_519 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_520 = and(_T_518, _T_519)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 2, 0)
node _T_521 = shr(io.in.a.bits.source, 3)
node _T_522 = eq(_T_521, UInt<2>(0h3))
node _T_523 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_524 = and(_T_522, _T_523)
node _T_525 = leq(uncommonBits_39, UInt<3>(0h7))
node _T_526 = and(_T_524, _T_525)
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 2, 0)
node _T_527 = shr(io.in.a.bits.source, 3)
node _T_528 = eq(_T_527, UInt<2>(0h2))
node _T_529 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_530 = and(_T_528, _T_529)
node _T_531 = leq(uncommonBits_40, UInt<3>(0h7))
node _T_532 = and(_T_530, _T_531)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 2, 0)
node _T_533 = shr(io.in.a.bits.source, 3)
node _T_534 = eq(_T_533, UInt<4>(0h8))
node _T_535 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_536 = and(_T_534, _T_535)
node _T_537 = leq(uncommonBits_41, UInt<3>(0h4))
node _T_538 = and(_T_536, _T_537)
node _T_539 = eq(io.in.a.bits.source, UInt<7>(0h48))
node _T_540 = or(_T_496, _T_502)
node _T_541 = or(_T_540, _T_508)
node _T_542 = or(_T_541, _T_514)
node _T_543 = or(_T_542, _T_520)
node _T_544 = or(_T_543, _T_526)
node _T_545 = or(_T_544, _T_532)
node _T_546 = or(_T_545, _T_538)
node _T_547 = or(_T_546, _T_539)
node _T_548 = and(_T_495, _T_547)
node _T_549 = or(UInt<1>(0h0), _T_548)
node _T_550 = asUInt(reset)
node _T_551 = eq(_T_550, UInt<1>(0h0))
when _T_551 :
node _T_552 = eq(_T_549, UInt<1>(0h0))
when _T_552 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_549, UInt<1>(0h1), "") : assert_19
node _T_553 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_554 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_555 = and(_T_553, _T_554)
node _T_556 = or(UInt<1>(0h0), _T_555)
node _T_557 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_558 = cvt(_T_557)
node _T_559 = and(_T_558, asSInt(UInt<17>(0h10000)))
node _T_560 = asSInt(_T_559)
node _T_561 = eq(_T_560, asSInt(UInt<1>(0h0)))
node _T_562 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_563 = cvt(_T_562)
node _T_564 = and(_T_563, asSInt(UInt<29>(0h10000000)))
node _T_565 = asSInt(_T_564)
node _T_566 = eq(_T_565, asSInt(UInt<1>(0h0)))
node _T_567 = or(_T_561, _T_566)
node _T_568 = and(_T_556, _T_567)
node _T_569 = or(UInt<1>(0h0), _T_568)
node _T_570 = asUInt(reset)
node _T_571 = eq(_T_570, UInt<1>(0h0))
when _T_571 :
node _T_572 = eq(_T_569, UInt<1>(0h0))
when _T_572 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_569, UInt<1>(0h1), "") : assert_20
node _T_573 = asUInt(reset)
node _T_574 = eq(_T_573, UInt<1>(0h0))
when _T_574 :
node _T_575 = eq(source_ok, UInt<1>(0h0))
when _T_575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_576 = asUInt(reset)
node _T_577 = eq(_T_576, UInt<1>(0h0))
when _T_577 :
node _T_578 = eq(is_aligned, UInt<1>(0h0))
when _T_578 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_579 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_580 = asUInt(reset)
node _T_581 = eq(_T_580, UInt<1>(0h0))
when _T_581 :
node _T_582 = eq(_T_579, UInt<1>(0h0))
when _T_582 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_579, UInt<1>(0h1), "") : assert_23
node _T_583 = eq(io.in.a.bits.mask, mask)
node _T_584 = asUInt(reset)
node _T_585 = eq(_T_584, UInt<1>(0h0))
when _T_585 :
node _T_586 = eq(_T_583, UInt<1>(0h0))
when _T_586 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_583, UInt<1>(0h1), "") : assert_24
node _T_587 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_588 = asUInt(reset)
node _T_589 = eq(_T_588, UInt<1>(0h0))
when _T_589 :
node _T_590 = eq(_T_587, UInt<1>(0h0))
when _T_590 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_587, UInt<1>(0h1), "") : assert_25
node _T_591 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_591 :
node _T_592 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_593 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_594 = and(_T_592, _T_593)
node _T_595 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0)
node _T_596 = shr(io.in.a.bits.source, 2)
node _T_597 = eq(_T_596, UInt<1>(0h0))
node _T_598 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_599 = and(_T_597, _T_598)
node _T_600 = leq(uncommonBits_42, UInt<2>(0h3))
node _T_601 = and(_T_599, _T_600)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0)
node _T_602 = shr(io.in.a.bits.source, 2)
node _T_603 = eq(_T_602, UInt<1>(0h1))
node _T_604 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_605 = and(_T_603, _T_604)
node _T_606 = leq(uncommonBits_43, UInt<2>(0h3))
node _T_607 = and(_T_605, _T_606)
node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0)
node _T_608 = shr(io.in.a.bits.source, 2)
node _T_609 = eq(_T_608, UInt<2>(0h2))
node _T_610 = leq(UInt<1>(0h0), uncommonBits_44)
node _T_611 = and(_T_609, _T_610)
node _T_612 = leq(uncommonBits_44, UInt<2>(0h3))
node _T_613 = and(_T_611, _T_612)
node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0)
node _T_614 = shr(io.in.a.bits.source, 2)
node _T_615 = eq(_T_614, UInt<2>(0h3))
node _T_616 = leq(UInt<1>(0h0), uncommonBits_45)
node _T_617 = and(_T_615, _T_616)
node _T_618 = leq(uncommonBits_45, UInt<2>(0h3))
node _T_619 = and(_T_617, _T_618)
node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_46 = bits(_uncommonBits_T_46, 2, 0)
node _T_620 = shr(io.in.a.bits.source, 3)
node _T_621 = eq(_T_620, UInt<2>(0h3))
node _T_622 = leq(UInt<1>(0h0), uncommonBits_46)
node _T_623 = and(_T_621, _T_622)
node _T_624 = leq(uncommonBits_46, UInt<3>(0h7))
node _T_625 = and(_T_623, _T_624)
node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_47 = bits(_uncommonBits_T_47, 2, 0)
node _T_626 = shr(io.in.a.bits.source, 3)
node _T_627 = eq(_T_626, UInt<2>(0h2))
node _T_628 = leq(UInt<1>(0h0), uncommonBits_47)
node _T_629 = and(_T_627, _T_628)
node _T_630 = leq(uncommonBits_47, UInt<3>(0h7))
node _T_631 = and(_T_629, _T_630)
node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_48 = bits(_uncommonBits_T_48, 2, 0)
node _T_632 = shr(io.in.a.bits.source, 3)
node _T_633 = eq(_T_632, UInt<4>(0h8))
node _T_634 = leq(UInt<1>(0h0), uncommonBits_48)
node _T_635 = and(_T_633, _T_634)
node _T_636 = leq(uncommonBits_48, UInt<3>(0h4))
node _T_637 = and(_T_635, _T_636)
node _T_638 = eq(io.in.a.bits.source, UInt<7>(0h48))
node _T_639 = or(_T_595, _T_601)
node _T_640 = or(_T_639, _T_607)
node _T_641 = or(_T_640, _T_613)
node _T_642 = or(_T_641, _T_619)
node _T_643 = or(_T_642, _T_625)
node _T_644 = or(_T_643, _T_631)
node _T_645 = or(_T_644, _T_637)
node _T_646 = or(_T_645, _T_638)
node _T_647 = and(_T_594, _T_646)
node _T_648 = or(UInt<1>(0h0), _T_647)
node _T_649 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_650 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_651 = and(_T_649, _T_650)
node _T_652 = or(UInt<1>(0h0), _T_651)
node _T_653 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_654 = cvt(_T_653)
node _T_655 = and(_T_654, asSInt(UInt<17>(0h10000)))
node _T_656 = asSInt(_T_655)
node _T_657 = eq(_T_656, asSInt(UInt<1>(0h0)))
node _T_658 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_659 = cvt(_T_658)
node _T_660 = and(_T_659, asSInt(UInt<29>(0h10000000)))
node _T_661 = asSInt(_T_660)
node _T_662 = eq(_T_661, asSInt(UInt<1>(0h0)))
node _T_663 = or(_T_657, _T_662)
node _T_664 = and(_T_652, _T_663)
node _T_665 = or(UInt<1>(0h0), _T_664)
node _T_666 = and(_T_648, _T_665)
node _T_667 = asUInt(reset)
node _T_668 = eq(_T_667, UInt<1>(0h0))
when _T_668 :
node _T_669 = eq(_T_666, UInt<1>(0h0))
when _T_669 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_666, UInt<1>(0h1), "") : assert_26
node _T_670 = asUInt(reset)
node _T_671 = eq(_T_670, UInt<1>(0h0))
when _T_671 :
node _T_672 = eq(source_ok, UInt<1>(0h0))
when _T_672 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_673 = asUInt(reset)
node _T_674 = eq(_T_673, UInt<1>(0h0))
when _T_674 :
node _T_675 = eq(is_aligned, UInt<1>(0h0))
when _T_675 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_676 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_677 = asUInt(reset)
node _T_678 = eq(_T_677, UInt<1>(0h0))
when _T_678 :
node _T_679 = eq(_T_676, UInt<1>(0h0))
when _T_679 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_676, UInt<1>(0h1), "") : assert_29
node _T_680 = eq(io.in.a.bits.mask, mask)
node _T_681 = asUInt(reset)
node _T_682 = eq(_T_681, UInt<1>(0h0))
when _T_682 :
node _T_683 = eq(_T_680, UInt<1>(0h0))
when _T_683 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_680, UInt<1>(0h1), "") : assert_30
node _T_684 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_684 :
node _T_685 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_686 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_687 = and(_T_685, _T_686)
node _T_688 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0)
node _T_689 = shr(io.in.a.bits.source, 2)
node _T_690 = eq(_T_689, UInt<1>(0h0))
node _T_691 = leq(UInt<1>(0h0), uncommonBits_49)
node _T_692 = and(_T_690, _T_691)
node _T_693 = leq(uncommonBits_49, UInt<2>(0h3))
node _T_694 = and(_T_692, _T_693)
node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0)
node _T_695 = shr(io.in.a.bits.source, 2)
node _T_696 = eq(_T_695, UInt<1>(0h1))
node _T_697 = leq(UInt<1>(0h0), uncommonBits_50)
node _T_698 = and(_T_696, _T_697)
node _T_699 = leq(uncommonBits_50, UInt<2>(0h3))
node _T_700 = and(_T_698, _T_699)
node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0)
node _T_701 = shr(io.in.a.bits.source, 2)
node _T_702 = eq(_T_701, UInt<2>(0h2))
node _T_703 = leq(UInt<1>(0h0), uncommonBits_51)
node _T_704 = and(_T_702, _T_703)
node _T_705 = leq(uncommonBits_51, UInt<2>(0h3))
node _T_706 = and(_T_704, _T_705)
node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0)
node _T_707 = shr(io.in.a.bits.source, 2)
node _T_708 = eq(_T_707, UInt<2>(0h3))
node _T_709 = leq(UInt<1>(0h0), uncommonBits_52)
node _T_710 = and(_T_708, _T_709)
node _T_711 = leq(uncommonBits_52, UInt<2>(0h3))
node _T_712 = and(_T_710, _T_711)
node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_53 = bits(_uncommonBits_T_53, 2, 0)
node _T_713 = shr(io.in.a.bits.source, 3)
node _T_714 = eq(_T_713, UInt<2>(0h3))
node _T_715 = leq(UInt<1>(0h0), uncommonBits_53)
node _T_716 = and(_T_714, _T_715)
node _T_717 = leq(uncommonBits_53, UInt<3>(0h7))
node _T_718 = and(_T_716, _T_717)
node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_54 = bits(_uncommonBits_T_54, 2, 0)
node _T_719 = shr(io.in.a.bits.source, 3)
node _T_720 = eq(_T_719, UInt<2>(0h2))
node _T_721 = leq(UInt<1>(0h0), uncommonBits_54)
node _T_722 = and(_T_720, _T_721)
node _T_723 = leq(uncommonBits_54, UInt<3>(0h7))
node _T_724 = and(_T_722, _T_723)
node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_55 = bits(_uncommonBits_T_55, 2, 0)
node _T_725 = shr(io.in.a.bits.source, 3)
node _T_726 = eq(_T_725, UInt<4>(0h8))
node _T_727 = leq(UInt<1>(0h0), uncommonBits_55)
node _T_728 = and(_T_726, _T_727)
node _T_729 = leq(uncommonBits_55, UInt<3>(0h4))
node _T_730 = and(_T_728, _T_729)
node _T_731 = eq(io.in.a.bits.source, UInt<7>(0h48))
node _T_732 = or(_T_688, _T_694)
node _T_733 = or(_T_732, _T_700)
node _T_734 = or(_T_733, _T_706)
node _T_735 = or(_T_734, _T_712)
node _T_736 = or(_T_735, _T_718)
node _T_737 = or(_T_736, _T_724)
node _T_738 = or(_T_737, _T_730)
node _T_739 = or(_T_738, _T_731)
node _T_740 = and(_T_687, _T_739)
node _T_741 = or(UInt<1>(0h0), _T_740)
node _T_742 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_743 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_744 = and(_T_742, _T_743)
node _T_745 = or(UInt<1>(0h0), _T_744)
node _T_746 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_747 = cvt(_T_746)
node _T_748 = and(_T_747, asSInt(UInt<17>(0h10000)))
node _T_749 = asSInt(_T_748)
node _T_750 = eq(_T_749, asSInt(UInt<1>(0h0)))
node _T_751 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_752 = cvt(_T_751)
node _T_753 = and(_T_752, asSInt(UInt<29>(0h10000000)))
node _T_754 = asSInt(_T_753)
node _T_755 = eq(_T_754, asSInt(UInt<1>(0h0)))
node _T_756 = or(_T_750, _T_755)
node _T_757 = and(_T_745, _T_756)
node _T_758 = or(UInt<1>(0h0), _T_757)
node _T_759 = and(_T_741, _T_758)
node _T_760 = asUInt(reset)
node _T_761 = eq(_T_760, UInt<1>(0h0))
when _T_761 :
node _T_762 = eq(_T_759, UInt<1>(0h0))
when _T_762 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_759, UInt<1>(0h1), "") : assert_31
node _T_763 = asUInt(reset)
node _T_764 = eq(_T_763, UInt<1>(0h0))
when _T_764 :
node _T_765 = eq(source_ok, UInt<1>(0h0))
when _T_765 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_766 = asUInt(reset)
node _T_767 = eq(_T_766, UInt<1>(0h0))
when _T_767 :
node _T_768 = eq(is_aligned, UInt<1>(0h0))
when _T_768 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_769 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_770 = asUInt(reset)
node _T_771 = eq(_T_770, UInt<1>(0h0))
when _T_771 :
node _T_772 = eq(_T_769, UInt<1>(0h0))
when _T_772 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_769, UInt<1>(0h1), "") : assert_34
node _T_773 = not(mask)
node _T_774 = and(io.in.a.bits.mask, _T_773)
node _T_775 = eq(_T_774, UInt<1>(0h0))
node _T_776 = asUInt(reset)
node _T_777 = eq(_T_776, UInt<1>(0h0))
when _T_777 :
node _T_778 = eq(_T_775, UInt<1>(0h0))
when _T_778 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_775, UInt<1>(0h1), "") : assert_35
node _T_779 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_779 :
node _T_780 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_781 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_782 = and(_T_780, _T_781)
node _T_783 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0)
node _T_784 = shr(io.in.a.bits.source, 2)
node _T_785 = eq(_T_784, UInt<1>(0h0))
node _T_786 = leq(UInt<1>(0h0), uncommonBits_56)
node _T_787 = and(_T_785, _T_786)
node _T_788 = leq(uncommonBits_56, UInt<2>(0h3))
node _T_789 = and(_T_787, _T_788)
node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0)
node _T_790 = shr(io.in.a.bits.source, 2)
node _T_791 = eq(_T_790, UInt<1>(0h1))
node _T_792 = leq(UInt<1>(0h0), uncommonBits_57)
node _T_793 = and(_T_791, _T_792)
node _T_794 = leq(uncommonBits_57, UInt<2>(0h3))
node _T_795 = and(_T_793, _T_794)
node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_58 = bits(_uncommonBits_T_58, 1, 0)
node _T_796 = shr(io.in.a.bits.source, 2)
node _T_797 = eq(_T_796, UInt<2>(0h2))
node _T_798 = leq(UInt<1>(0h0), uncommonBits_58)
node _T_799 = and(_T_797, _T_798)
node _T_800 = leq(uncommonBits_58, UInt<2>(0h3))
node _T_801 = and(_T_799, _T_800)
node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_59 = bits(_uncommonBits_T_59, 1, 0)
node _T_802 = shr(io.in.a.bits.source, 2)
node _T_803 = eq(_T_802, UInt<2>(0h3))
node _T_804 = leq(UInt<1>(0h0), uncommonBits_59)
node _T_805 = and(_T_803, _T_804)
node _T_806 = leq(uncommonBits_59, UInt<2>(0h3))
node _T_807 = and(_T_805, _T_806)
node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_60 = bits(_uncommonBits_T_60, 2, 0)
node _T_808 = shr(io.in.a.bits.source, 3)
node _T_809 = eq(_T_808, UInt<2>(0h3))
node _T_810 = leq(UInt<1>(0h0), uncommonBits_60)
node _T_811 = and(_T_809, _T_810)
node _T_812 = leq(uncommonBits_60, UInt<3>(0h7))
node _T_813 = and(_T_811, _T_812)
node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_61 = bits(_uncommonBits_T_61, 2, 0)
node _T_814 = shr(io.in.a.bits.source, 3)
node _T_815 = eq(_T_814, UInt<2>(0h2))
node _T_816 = leq(UInt<1>(0h0), uncommonBits_61)
node _T_817 = and(_T_815, _T_816)
node _T_818 = leq(uncommonBits_61, UInt<3>(0h7))
node _T_819 = and(_T_817, _T_818)
node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_62 = bits(_uncommonBits_T_62, 2, 0)
node _T_820 = shr(io.in.a.bits.source, 3)
node _T_821 = eq(_T_820, UInt<4>(0h8))
node _T_822 = leq(UInt<1>(0h0), uncommonBits_62)
node _T_823 = and(_T_821, _T_822)
node _T_824 = leq(uncommonBits_62, UInt<3>(0h4))
node _T_825 = and(_T_823, _T_824)
node _T_826 = eq(io.in.a.bits.source, UInt<7>(0h48))
node _T_827 = or(_T_783, _T_789)
node _T_828 = or(_T_827, _T_795)
node _T_829 = or(_T_828, _T_801)
node _T_830 = or(_T_829, _T_807)
node _T_831 = or(_T_830, _T_813)
node _T_832 = or(_T_831, _T_819)
node _T_833 = or(_T_832, _T_825)
node _T_834 = or(_T_833, _T_826)
node _T_835 = and(_T_782, _T_834)
node _T_836 = or(UInt<1>(0h0), _T_835)
node _T_837 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_838 = leq(io.in.a.bits.size, UInt<3>(0h4))
node _T_839 = and(_T_837, _T_838)
node _T_840 = or(UInt<1>(0h0), _T_839)
node _T_841 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_842 = cvt(_T_841)
node _T_843 = and(_T_842, asSInt(UInt<17>(0h10000)))
node _T_844 = asSInt(_T_843)
node _T_845 = eq(_T_844, asSInt(UInt<1>(0h0)))
node _T_846 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_847 = cvt(_T_846)
node _T_848 = and(_T_847, asSInt(UInt<29>(0h10000000)))
node _T_849 = asSInt(_T_848)
node _T_850 = eq(_T_849, asSInt(UInt<1>(0h0)))
node _T_851 = or(_T_845, _T_850)
node _T_852 = and(_T_840, _T_851)
node _T_853 = or(UInt<1>(0h0), _T_852)
node _T_854 = and(_T_836, _T_853)
node _T_855 = asUInt(reset)
node _T_856 = eq(_T_855, UInt<1>(0h0))
when _T_856 :
node _T_857 = eq(_T_854, UInt<1>(0h0))
when _T_857 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_854, UInt<1>(0h1), "") : assert_36
node _T_858 = asUInt(reset)
node _T_859 = eq(_T_858, UInt<1>(0h0))
when _T_859 :
node _T_860 = eq(source_ok, UInt<1>(0h0))
when _T_860 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_861 = asUInt(reset)
node _T_862 = eq(_T_861, UInt<1>(0h0))
when _T_862 :
node _T_863 = eq(is_aligned, UInt<1>(0h0))
when _T_863 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_864 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_865 = asUInt(reset)
node _T_866 = eq(_T_865, UInt<1>(0h0))
when _T_866 :
node _T_867 = eq(_T_864, UInt<1>(0h0))
when _T_867 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_864, UInt<1>(0h1), "") : assert_39
node _T_868 = eq(io.in.a.bits.mask, mask)
node _T_869 = asUInt(reset)
node _T_870 = eq(_T_869, UInt<1>(0h0))
when _T_870 :
node _T_871 = eq(_T_868, UInt<1>(0h0))
when _T_871 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_868, UInt<1>(0h1), "") : assert_40
node _T_872 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_872 :
node _T_873 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_874 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_875 = and(_T_873, _T_874)
node _T_876 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0)
node _T_877 = shr(io.in.a.bits.source, 2)
node _T_878 = eq(_T_877, UInt<1>(0h0))
node _T_879 = leq(UInt<1>(0h0), uncommonBits_63)
node _T_880 = and(_T_878, _T_879)
node _T_881 = leq(uncommonBits_63, UInt<2>(0h3))
node _T_882 = and(_T_880, _T_881)
node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_64 = bits(_uncommonBits_T_64, 1, 0)
node _T_883 = shr(io.in.a.bits.source, 2)
node _T_884 = eq(_T_883, UInt<1>(0h1))
node _T_885 = leq(UInt<1>(0h0), uncommonBits_64)
node _T_886 = and(_T_884, _T_885)
node _T_887 = leq(uncommonBits_64, UInt<2>(0h3))
node _T_888 = and(_T_886, _T_887)
node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_65 = bits(_uncommonBits_T_65, 1, 0)
node _T_889 = shr(io.in.a.bits.source, 2)
node _T_890 = eq(_T_889, UInt<2>(0h2))
node _T_891 = leq(UInt<1>(0h0), uncommonBits_65)
node _T_892 = and(_T_890, _T_891)
node _T_893 = leq(uncommonBits_65, UInt<2>(0h3))
node _T_894 = and(_T_892, _T_893)
node _uncommonBits_T_66 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_66 = bits(_uncommonBits_T_66, 1, 0)
node _T_895 = shr(io.in.a.bits.source, 2)
node _T_896 = eq(_T_895, UInt<2>(0h3))
node _T_897 = leq(UInt<1>(0h0), uncommonBits_66)
node _T_898 = and(_T_896, _T_897)
node _T_899 = leq(uncommonBits_66, UInt<2>(0h3))
node _T_900 = and(_T_898, _T_899)
node _uncommonBits_T_67 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_67 = bits(_uncommonBits_T_67, 2, 0)
node _T_901 = shr(io.in.a.bits.source, 3)
node _T_902 = eq(_T_901, UInt<2>(0h3))
node _T_903 = leq(UInt<1>(0h0), uncommonBits_67)
node _T_904 = and(_T_902, _T_903)
node _T_905 = leq(uncommonBits_67, UInt<3>(0h7))
node _T_906 = and(_T_904, _T_905)
node _uncommonBits_T_68 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_68 = bits(_uncommonBits_T_68, 2, 0)
node _T_907 = shr(io.in.a.bits.source, 3)
node _T_908 = eq(_T_907, UInt<2>(0h2))
node _T_909 = leq(UInt<1>(0h0), uncommonBits_68)
node _T_910 = and(_T_908, _T_909)
node _T_911 = leq(uncommonBits_68, UInt<3>(0h7))
node _T_912 = and(_T_910, _T_911)
node _uncommonBits_T_69 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_69 = bits(_uncommonBits_T_69, 2, 0)
node _T_913 = shr(io.in.a.bits.source, 3)
node _T_914 = eq(_T_913, UInt<4>(0h8))
node _T_915 = leq(UInt<1>(0h0), uncommonBits_69)
node _T_916 = and(_T_914, _T_915)
node _T_917 = leq(uncommonBits_69, UInt<3>(0h4))
node _T_918 = and(_T_916, _T_917)
node _T_919 = eq(io.in.a.bits.source, UInt<7>(0h48))
node _T_920 = or(_T_876, _T_882)
node _T_921 = or(_T_920, _T_888)
node _T_922 = or(_T_921, _T_894)
node _T_923 = or(_T_922, _T_900)
node _T_924 = or(_T_923, _T_906)
node _T_925 = or(_T_924, _T_912)
node _T_926 = or(_T_925, _T_918)
node _T_927 = or(_T_926, _T_919)
node _T_928 = and(_T_875, _T_927)
node _T_929 = or(UInt<1>(0h0), _T_928)
node _T_930 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_931 = leq(io.in.a.bits.size, UInt<3>(0h4))
node _T_932 = and(_T_930, _T_931)
node _T_933 = or(UInt<1>(0h0), _T_932)
node _T_934 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_935 = cvt(_T_934)
node _T_936 = and(_T_935, asSInt(UInt<17>(0h10000)))
node _T_937 = asSInt(_T_936)
node _T_938 = eq(_T_937, asSInt(UInt<1>(0h0)))
node _T_939 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_940 = cvt(_T_939)
node _T_941 = and(_T_940, asSInt(UInt<29>(0h10000000)))
node _T_942 = asSInt(_T_941)
node _T_943 = eq(_T_942, asSInt(UInt<1>(0h0)))
node _T_944 = or(_T_938, _T_943)
node _T_945 = and(_T_933, _T_944)
node _T_946 = or(UInt<1>(0h0), _T_945)
node _T_947 = and(_T_929, _T_946)
node _T_948 = asUInt(reset)
node _T_949 = eq(_T_948, UInt<1>(0h0))
when _T_949 :
node _T_950 = eq(_T_947, UInt<1>(0h0))
when _T_950 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_947, UInt<1>(0h1), "") : assert_41
node _T_951 = asUInt(reset)
node _T_952 = eq(_T_951, UInt<1>(0h0))
when _T_952 :
node _T_953 = eq(source_ok, UInt<1>(0h0))
when _T_953 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_954 = asUInt(reset)
node _T_955 = eq(_T_954, UInt<1>(0h0))
when _T_955 :
node _T_956 = eq(is_aligned, UInt<1>(0h0))
when _T_956 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_957 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_958 = asUInt(reset)
node _T_959 = eq(_T_958, UInt<1>(0h0))
when _T_959 :
node _T_960 = eq(_T_957, UInt<1>(0h0))
when _T_960 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_957, UInt<1>(0h1), "") : assert_44
node _T_961 = eq(io.in.a.bits.mask, mask)
node _T_962 = asUInt(reset)
node _T_963 = eq(_T_962, UInt<1>(0h0))
when _T_963 :
node _T_964 = eq(_T_961, UInt<1>(0h0))
when _T_964 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_961, UInt<1>(0h1), "") : assert_45
node _T_965 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_965 :
node _T_966 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_967 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_968 = and(_T_966, _T_967)
node _T_969 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_70 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_70 = bits(_uncommonBits_T_70, 1, 0)
node _T_970 = shr(io.in.a.bits.source, 2)
node _T_971 = eq(_T_970, UInt<1>(0h0))
node _T_972 = leq(UInt<1>(0h0), uncommonBits_70)
node _T_973 = and(_T_971, _T_972)
node _T_974 = leq(uncommonBits_70, UInt<2>(0h3))
node _T_975 = and(_T_973, _T_974)
node _uncommonBits_T_71 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_71 = bits(_uncommonBits_T_71, 1, 0)
node _T_976 = shr(io.in.a.bits.source, 2)
node _T_977 = eq(_T_976, UInt<1>(0h1))
node _T_978 = leq(UInt<1>(0h0), uncommonBits_71)
node _T_979 = and(_T_977, _T_978)
node _T_980 = leq(uncommonBits_71, UInt<2>(0h3))
node _T_981 = and(_T_979, _T_980)
node _uncommonBits_T_72 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_72 = bits(_uncommonBits_T_72, 1, 0)
node _T_982 = shr(io.in.a.bits.source, 2)
node _T_983 = eq(_T_982, UInt<2>(0h2))
node _T_984 = leq(UInt<1>(0h0), uncommonBits_72)
node _T_985 = and(_T_983, _T_984)
node _T_986 = leq(uncommonBits_72, UInt<2>(0h3))
node _T_987 = and(_T_985, _T_986)
node _uncommonBits_T_73 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_73 = bits(_uncommonBits_T_73, 1, 0)
node _T_988 = shr(io.in.a.bits.source, 2)
node _T_989 = eq(_T_988, UInt<2>(0h3))
node _T_990 = leq(UInt<1>(0h0), uncommonBits_73)
node _T_991 = and(_T_989, _T_990)
node _T_992 = leq(uncommonBits_73, UInt<2>(0h3))
node _T_993 = and(_T_991, _T_992)
node _uncommonBits_T_74 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_74 = bits(_uncommonBits_T_74, 2, 0)
node _T_994 = shr(io.in.a.bits.source, 3)
node _T_995 = eq(_T_994, UInt<2>(0h3))
node _T_996 = leq(UInt<1>(0h0), uncommonBits_74)
node _T_997 = and(_T_995, _T_996)
node _T_998 = leq(uncommonBits_74, UInt<3>(0h7))
node _T_999 = and(_T_997, _T_998)
node _uncommonBits_T_75 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_75 = bits(_uncommonBits_T_75, 2, 0)
node _T_1000 = shr(io.in.a.bits.source, 3)
node _T_1001 = eq(_T_1000, UInt<2>(0h2))
node _T_1002 = leq(UInt<1>(0h0), uncommonBits_75)
node _T_1003 = and(_T_1001, _T_1002)
node _T_1004 = leq(uncommonBits_75, UInt<3>(0h7))
node _T_1005 = and(_T_1003, _T_1004)
node _uncommonBits_T_76 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_76 = bits(_uncommonBits_T_76, 2, 0)
node _T_1006 = shr(io.in.a.bits.source, 3)
node _T_1007 = eq(_T_1006, UInt<4>(0h8))
node _T_1008 = leq(UInt<1>(0h0), uncommonBits_76)
node _T_1009 = and(_T_1007, _T_1008)
node _T_1010 = leq(uncommonBits_76, UInt<3>(0h4))
node _T_1011 = and(_T_1009, _T_1010)
node _T_1012 = eq(io.in.a.bits.source, UInt<7>(0h48))
node _T_1013 = or(_T_969, _T_975)
node _T_1014 = or(_T_1013, _T_981)
node _T_1015 = or(_T_1014, _T_987)
node _T_1016 = or(_T_1015, _T_993)
node _T_1017 = or(_T_1016, _T_999)
node _T_1018 = or(_T_1017, _T_1005)
node _T_1019 = or(_T_1018, _T_1011)
node _T_1020 = or(_T_1019, _T_1012)
node _T_1021 = and(_T_968, _T_1020)
node _T_1022 = or(UInt<1>(0h0), _T_1021)
node _T_1023 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1024 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_1025 = and(_T_1023, _T_1024)
node _T_1026 = or(UInt<1>(0h0), _T_1025)
node _T_1027 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_1028 = cvt(_T_1027)
node _T_1029 = and(_T_1028, asSInt(UInt<17>(0h10000)))
node _T_1030 = asSInt(_T_1029)
node _T_1031 = eq(_T_1030, asSInt(UInt<1>(0h0)))
node _T_1032 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_1033 = cvt(_T_1032)
node _T_1034 = and(_T_1033, asSInt(UInt<29>(0h10000000)))
node _T_1035 = asSInt(_T_1034)
node _T_1036 = eq(_T_1035, asSInt(UInt<1>(0h0)))
node _T_1037 = or(_T_1031, _T_1036)
node _T_1038 = and(_T_1026, _T_1037)
node _T_1039 = or(UInt<1>(0h0), _T_1038)
node _T_1040 = and(_T_1022, _T_1039)
node _T_1041 = asUInt(reset)
node _T_1042 = eq(_T_1041, UInt<1>(0h0))
when _T_1042 :
node _T_1043 = eq(_T_1040, UInt<1>(0h0))
when _T_1043 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_1040, UInt<1>(0h1), "") : assert_46
node _T_1044 = asUInt(reset)
node _T_1045 = eq(_T_1044, UInt<1>(0h0))
when _T_1045 :
node _T_1046 = eq(source_ok, UInt<1>(0h0))
when _T_1046 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_1047 = asUInt(reset)
node _T_1048 = eq(_T_1047, UInt<1>(0h0))
when _T_1048 :
node _T_1049 = eq(is_aligned, UInt<1>(0h0))
when _T_1049 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_1050 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_1051 = asUInt(reset)
node _T_1052 = eq(_T_1051, UInt<1>(0h0))
when _T_1052 :
node _T_1053 = eq(_T_1050, UInt<1>(0h0))
when _T_1053 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_1050, UInt<1>(0h1), "") : assert_49
node _T_1054 = eq(io.in.a.bits.mask, mask)
node _T_1055 = asUInt(reset)
node _T_1056 = eq(_T_1055, UInt<1>(0h0))
when _T_1056 :
node _T_1057 = eq(_T_1054, UInt<1>(0h0))
when _T_1057 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_1054, UInt<1>(0h1), "") : assert_50
node _T_1058 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1059 = asUInt(reset)
node _T_1060 = eq(_T_1059, UInt<1>(0h0))
when _T_1060 :
node _T_1061 = eq(_T_1058, UInt<1>(0h0))
when _T_1061 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1058, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1062 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1063 = asUInt(reset)
node _T_1064 = eq(_T_1063, UInt<1>(0h0))
when _T_1064 :
node _T_1065 = eq(_T_1062, UInt<1>(0h0))
when _T_1065 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1062, UInt<1>(0h1), "") : assert_52
node _source_ok_T_51 = eq(io.in.d.bits.source, UInt<6>(0h20))
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_52 = shr(io.in.d.bits.source, 2)
node _source_ok_T_53 = eq(_source_ok_T_52, UInt<1>(0h0))
node _source_ok_T_54 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_55 = and(_source_ok_T_53, _source_ok_T_54)
node _source_ok_T_56 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_57 = and(_source_ok_T_55, _source_ok_T_56)
node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0)
node _source_ok_T_58 = shr(io.in.d.bits.source, 2)
node _source_ok_T_59 = eq(_source_ok_T_58, UInt<1>(0h1))
node _source_ok_T_60 = leq(UInt<1>(0h0), source_ok_uncommonBits_8)
node _source_ok_T_61 = and(_source_ok_T_59, _source_ok_T_60)
node _source_ok_T_62 = leq(source_ok_uncommonBits_8, UInt<2>(0h3))
node _source_ok_T_63 = and(_source_ok_T_61, _source_ok_T_62)
node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0)
node _source_ok_T_64 = shr(io.in.d.bits.source, 2)
node _source_ok_T_65 = eq(_source_ok_T_64, UInt<2>(0h2))
node _source_ok_T_66 = leq(UInt<1>(0h0), source_ok_uncommonBits_9)
node _source_ok_T_67 = and(_source_ok_T_65, _source_ok_T_66)
node _source_ok_T_68 = leq(source_ok_uncommonBits_9, UInt<2>(0h3))
node _source_ok_T_69 = and(_source_ok_T_67, _source_ok_T_68)
node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 1, 0)
node _source_ok_T_70 = shr(io.in.d.bits.source, 2)
node _source_ok_T_71 = eq(_source_ok_T_70, UInt<2>(0h3))
node _source_ok_T_72 = leq(UInt<1>(0h0), source_ok_uncommonBits_10)
node _source_ok_T_73 = and(_source_ok_T_71, _source_ok_T_72)
node _source_ok_T_74 = leq(source_ok_uncommonBits_10, UInt<2>(0h3))
node _source_ok_T_75 = and(_source_ok_T_73, _source_ok_T_74)
node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 2, 0)
node _source_ok_T_76 = shr(io.in.d.bits.source, 3)
node _source_ok_T_77 = eq(_source_ok_T_76, UInt<2>(0h3))
node _source_ok_T_78 = leq(UInt<1>(0h0), source_ok_uncommonBits_11)
node _source_ok_T_79 = and(_source_ok_T_77, _source_ok_T_78)
node _source_ok_T_80 = leq(source_ok_uncommonBits_11, UInt<3>(0h7))
node _source_ok_T_81 = and(_source_ok_T_79, _source_ok_T_80)
node _source_ok_uncommonBits_T_12 = or(io.in.d.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_12 = bits(_source_ok_uncommonBits_T_12, 2, 0)
node _source_ok_T_82 = shr(io.in.d.bits.source, 3)
node _source_ok_T_83 = eq(_source_ok_T_82, UInt<2>(0h2))
node _source_ok_T_84 = leq(UInt<1>(0h0), source_ok_uncommonBits_12)
node _source_ok_T_85 = and(_source_ok_T_83, _source_ok_T_84)
node _source_ok_T_86 = leq(source_ok_uncommonBits_12, UInt<3>(0h7))
node _source_ok_T_87 = and(_source_ok_T_85, _source_ok_T_86)
node _source_ok_uncommonBits_T_13 = or(io.in.d.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_13 = bits(_source_ok_uncommonBits_T_13, 2, 0)
node _source_ok_T_88 = shr(io.in.d.bits.source, 3)
node _source_ok_T_89 = eq(_source_ok_T_88, UInt<4>(0h8))
node _source_ok_T_90 = leq(UInt<1>(0h0), source_ok_uncommonBits_13)
node _source_ok_T_91 = and(_source_ok_T_89, _source_ok_T_90)
node _source_ok_T_92 = leq(source_ok_uncommonBits_13, UInt<3>(0h4))
node _source_ok_T_93 = and(_source_ok_T_91, _source_ok_T_92)
node _source_ok_T_94 = eq(io.in.d.bits.source, UInt<7>(0h48))
wire _source_ok_WIRE_1 : UInt<1>[9]
connect _source_ok_WIRE_1[0], _source_ok_T_51
connect _source_ok_WIRE_1[1], _source_ok_T_57
connect _source_ok_WIRE_1[2], _source_ok_T_63
connect _source_ok_WIRE_1[3], _source_ok_T_69
connect _source_ok_WIRE_1[4], _source_ok_T_75
connect _source_ok_WIRE_1[5], _source_ok_T_81
connect _source_ok_WIRE_1[6], _source_ok_T_87
connect _source_ok_WIRE_1[7], _source_ok_T_93
connect _source_ok_WIRE_1[8], _source_ok_T_94
node _source_ok_T_95 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_96 = or(_source_ok_T_95, _source_ok_WIRE_1[2])
node _source_ok_T_97 = or(_source_ok_T_96, _source_ok_WIRE_1[3])
node _source_ok_T_98 = or(_source_ok_T_97, _source_ok_WIRE_1[4])
node _source_ok_T_99 = or(_source_ok_T_98, _source_ok_WIRE_1[5])
node _source_ok_T_100 = or(_source_ok_T_99, _source_ok_WIRE_1[6])
node _source_ok_T_101 = or(_source_ok_T_100, _source_ok_WIRE_1[7])
node source_ok_1 = or(_source_ok_T_101, _source_ok_WIRE_1[8])
node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0hc))
node _T_1066 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1066 :
node _T_1067 = asUInt(reset)
node _T_1068 = eq(_T_1067, UInt<1>(0h0))
when _T_1068 :
node _T_1069 = eq(source_ok_1, UInt<1>(0h0))
when _T_1069 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1070 = geq(io.in.d.bits.size, UInt<3>(0h4))
node _T_1071 = asUInt(reset)
node _T_1072 = eq(_T_1071, UInt<1>(0h0))
when _T_1072 :
node _T_1073 = eq(_T_1070, UInt<1>(0h0))
when _T_1073 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1070, UInt<1>(0h1), "") : assert_54
node _T_1074 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1075 = asUInt(reset)
node _T_1076 = eq(_T_1075, UInt<1>(0h0))
when _T_1076 :
node _T_1077 = eq(_T_1074, UInt<1>(0h0))
when _T_1077 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1074, UInt<1>(0h1), "") : assert_55
node _T_1078 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1079 = asUInt(reset)
node _T_1080 = eq(_T_1079, UInt<1>(0h0))
when _T_1080 :
node _T_1081 = eq(_T_1078, UInt<1>(0h0))
when _T_1081 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1078, UInt<1>(0h1), "") : assert_56
node _T_1082 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1083 = asUInt(reset)
node _T_1084 = eq(_T_1083, UInt<1>(0h0))
when _T_1084 :
node _T_1085 = eq(_T_1082, UInt<1>(0h0))
when _T_1085 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1082, UInt<1>(0h1), "") : assert_57
node _T_1086 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1086 :
node _T_1087 = asUInt(reset)
node _T_1088 = eq(_T_1087, UInt<1>(0h0))
when _T_1088 :
node _T_1089 = eq(source_ok_1, UInt<1>(0h0))
when _T_1089 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1090 = asUInt(reset)
node _T_1091 = eq(_T_1090, UInt<1>(0h0))
when _T_1091 :
node _T_1092 = eq(sink_ok, UInt<1>(0h0))
when _T_1092 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1093 = geq(io.in.d.bits.size, UInt<3>(0h4))
node _T_1094 = asUInt(reset)
node _T_1095 = eq(_T_1094, UInt<1>(0h0))
when _T_1095 :
node _T_1096 = eq(_T_1093, UInt<1>(0h0))
when _T_1096 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1093, UInt<1>(0h1), "") : assert_60
node _T_1097 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1098 = asUInt(reset)
node _T_1099 = eq(_T_1098, UInt<1>(0h0))
when _T_1099 :
node _T_1100 = eq(_T_1097, UInt<1>(0h0))
when _T_1100 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1097, UInt<1>(0h1), "") : assert_61
node _T_1101 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1102 = asUInt(reset)
node _T_1103 = eq(_T_1102, UInt<1>(0h0))
when _T_1103 :
node _T_1104 = eq(_T_1101, UInt<1>(0h0))
when _T_1104 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1101, UInt<1>(0h1), "") : assert_62
node _T_1105 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1106 = asUInt(reset)
node _T_1107 = eq(_T_1106, UInt<1>(0h0))
when _T_1107 :
node _T_1108 = eq(_T_1105, UInt<1>(0h0))
when _T_1108 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1105, UInt<1>(0h1), "") : assert_63
node _T_1109 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1110 = or(UInt<1>(0h1), _T_1109)
node _T_1111 = asUInt(reset)
node _T_1112 = eq(_T_1111, UInt<1>(0h0))
when _T_1112 :
node _T_1113 = eq(_T_1110, UInt<1>(0h0))
when _T_1113 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1110, UInt<1>(0h1), "") : assert_64
node _T_1114 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1114 :
node _T_1115 = asUInt(reset)
node _T_1116 = eq(_T_1115, UInt<1>(0h0))
when _T_1116 :
node _T_1117 = eq(source_ok_1, UInt<1>(0h0))
when _T_1117 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1118 = asUInt(reset)
node _T_1119 = eq(_T_1118, UInt<1>(0h0))
when _T_1119 :
node _T_1120 = eq(sink_ok, UInt<1>(0h0))
when _T_1120 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1121 = geq(io.in.d.bits.size, UInt<3>(0h4))
node _T_1122 = asUInt(reset)
node _T_1123 = eq(_T_1122, UInt<1>(0h0))
when _T_1123 :
node _T_1124 = eq(_T_1121, UInt<1>(0h0))
when _T_1124 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1121, UInt<1>(0h1), "") : assert_67
node _T_1125 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1126 = asUInt(reset)
node _T_1127 = eq(_T_1126, UInt<1>(0h0))
when _T_1127 :
node _T_1128 = eq(_T_1125, UInt<1>(0h0))
when _T_1128 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1125, UInt<1>(0h1), "") : assert_68
node _T_1129 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1130 = asUInt(reset)
node _T_1131 = eq(_T_1130, UInt<1>(0h0))
when _T_1131 :
node _T_1132 = eq(_T_1129, UInt<1>(0h0))
when _T_1132 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1129, UInt<1>(0h1), "") : assert_69
node _T_1133 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1134 = or(_T_1133, io.in.d.bits.corrupt)
node _T_1135 = asUInt(reset)
node _T_1136 = eq(_T_1135, UInt<1>(0h0))
when _T_1136 :
node _T_1137 = eq(_T_1134, UInt<1>(0h0))
when _T_1137 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1134, UInt<1>(0h1), "") : assert_70
node _T_1138 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1139 = or(UInt<1>(0h1), _T_1138)
node _T_1140 = asUInt(reset)
node _T_1141 = eq(_T_1140, UInt<1>(0h0))
when _T_1141 :
node _T_1142 = eq(_T_1139, UInt<1>(0h0))
when _T_1142 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1139, UInt<1>(0h1), "") : assert_71
node _T_1143 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1143 :
node _T_1144 = asUInt(reset)
node _T_1145 = eq(_T_1144, UInt<1>(0h0))
when _T_1145 :
node _T_1146 = eq(source_ok_1, UInt<1>(0h0))
when _T_1146 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1147 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1148 = asUInt(reset)
node _T_1149 = eq(_T_1148, UInt<1>(0h0))
when _T_1149 :
node _T_1150 = eq(_T_1147, UInt<1>(0h0))
when _T_1150 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1147, UInt<1>(0h1), "") : assert_73
node _T_1151 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1152 = asUInt(reset)
node _T_1153 = eq(_T_1152, UInt<1>(0h0))
when _T_1153 :
node _T_1154 = eq(_T_1151, UInt<1>(0h0))
when _T_1154 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1151, UInt<1>(0h1), "") : assert_74
node _T_1155 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1156 = or(UInt<1>(0h1), _T_1155)
node _T_1157 = asUInt(reset)
node _T_1158 = eq(_T_1157, UInt<1>(0h0))
when _T_1158 :
node _T_1159 = eq(_T_1156, UInt<1>(0h0))
when _T_1159 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1156, UInt<1>(0h1), "") : assert_75
node _T_1160 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1160 :
node _T_1161 = asUInt(reset)
node _T_1162 = eq(_T_1161, UInt<1>(0h0))
when _T_1162 :
node _T_1163 = eq(source_ok_1, UInt<1>(0h0))
when _T_1163 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1164 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1165 = asUInt(reset)
node _T_1166 = eq(_T_1165, UInt<1>(0h0))
when _T_1166 :
node _T_1167 = eq(_T_1164, UInt<1>(0h0))
when _T_1167 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1164, UInt<1>(0h1), "") : assert_77
node _T_1168 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1169 = or(_T_1168, io.in.d.bits.corrupt)
node _T_1170 = asUInt(reset)
node _T_1171 = eq(_T_1170, UInt<1>(0h0))
when _T_1171 :
node _T_1172 = eq(_T_1169, UInt<1>(0h0))
when _T_1172 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1169, UInt<1>(0h1), "") : assert_78
node _T_1173 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1174 = or(UInt<1>(0h1), _T_1173)
node _T_1175 = asUInt(reset)
node _T_1176 = eq(_T_1175, UInt<1>(0h0))
when _T_1176 :
node _T_1177 = eq(_T_1174, UInt<1>(0h0))
when _T_1177 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1174, UInt<1>(0h1), "") : assert_79
node _T_1178 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1178 :
node _T_1179 = asUInt(reset)
node _T_1180 = eq(_T_1179, UInt<1>(0h0))
when _T_1180 :
node _T_1181 = eq(source_ok_1, UInt<1>(0h0))
when _T_1181 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1182 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1183 = asUInt(reset)
node _T_1184 = eq(_T_1183, UInt<1>(0h0))
when _T_1184 :
node _T_1185 = eq(_T_1182, UInt<1>(0h0))
when _T_1185 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1182, UInt<1>(0h1), "") : assert_81
node _T_1186 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1187 = asUInt(reset)
node _T_1188 = eq(_T_1187, UInt<1>(0h0))
when _T_1188 :
node _T_1189 = eq(_T_1186, UInt<1>(0h0))
when _T_1189 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1186, UInt<1>(0h1), "") : assert_82
node _T_1190 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1191 = or(UInt<1>(0h1), _T_1190)
node _T_1192 = asUInt(reset)
node _T_1193 = eq(_T_1192, UInt<1>(0h0))
when _T_1193 :
node _T_1194 = eq(_T_1191, UInt<1>(0h0))
when _T_1194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1191, UInt<1>(0h1), "") : assert_83
when io.in.b.valid :
node _T_1195 = leq(io.in.b.bits.opcode, UInt<3>(0h6))
node _T_1196 = asUInt(reset)
node _T_1197 = eq(_T_1196, UInt<1>(0h0))
when _T_1197 :
node _T_1198 = eq(_T_1195, UInt<1>(0h0))
when _T_1198 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1195, UInt<1>(0h1), "") : assert_84
node _T_1199 = eq(io.in.b.bits.source, UInt<6>(0h20))
node _T_1200 = eq(_T_1199, UInt<1>(0h0))
node _T_1201 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1202 = cvt(_T_1201)
node _T_1203 = and(_T_1202, asSInt(UInt<1>(0h0)))
node _T_1204 = asSInt(_T_1203)
node _T_1205 = eq(_T_1204, asSInt(UInt<1>(0h0)))
node _T_1206 = or(_T_1200, _T_1205)
node _uncommonBits_T_77 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_77 = bits(_uncommonBits_T_77, 1, 0)
node _T_1207 = shr(io.in.b.bits.source, 2)
node _T_1208 = eq(_T_1207, UInt<1>(0h0))
node _T_1209 = leq(UInt<1>(0h0), uncommonBits_77)
node _T_1210 = and(_T_1208, _T_1209)
node _T_1211 = leq(uncommonBits_77, UInt<2>(0h3))
node _T_1212 = and(_T_1210, _T_1211)
node _T_1213 = eq(_T_1212, UInt<1>(0h0))
node _T_1214 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1215 = cvt(_T_1214)
node _T_1216 = and(_T_1215, asSInt(UInt<1>(0h0)))
node _T_1217 = asSInt(_T_1216)
node _T_1218 = eq(_T_1217, asSInt(UInt<1>(0h0)))
node _T_1219 = or(_T_1213, _T_1218)
node _uncommonBits_T_78 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_78 = bits(_uncommonBits_T_78, 1, 0)
node _T_1220 = shr(io.in.b.bits.source, 2)
node _T_1221 = eq(_T_1220, UInt<1>(0h1))
node _T_1222 = leq(UInt<1>(0h0), uncommonBits_78)
node _T_1223 = and(_T_1221, _T_1222)
node _T_1224 = leq(uncommonBits_78, UInt<2>(0h3))
node _T_1225 = and(_T_1223, _T_1224)
node _T_1226 = eq(_T_1225, UInt<1>(0h0))
node _T_1227 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1228 = cvt(_T_1227)
node _T_1229 = and(_T_1228, asSInt(UInt<1>(0h0)))
node _T_1230 = asSInt(_T_1229)
node _T_1231 = eq(_T_1230, asSInt(UInt<1>(0h0)))
node _T_1232 = or(_T_1226, _T_1231)
node _uncommonBits_T_79 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_79 = bits(_uncommonBits_T_79, 1, 0)
node _T_1233 = shr(io.in.b.bits.source, 2)
node _T_1234 = eq(_T_1233, UInt<2>(0h2))
node _T_1235 = leq(UInt<1>(0h0), uncommonBits_79)
node _T_1236 = and(_T_1234, _T_1235)
node _T_1237 = leq(uncommonBits_79, UInt<2>(0h3))
node _T_1238 = and(_T_1236, _T_1237)
node _T_1239 = eq(_T_1238, UInt<1>(0h0))
node _T_1240 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1241 = cvt(_T_1240)
node _T_1242 = and(_T_1241, asSInt(UInt<1>(0h0)))
node _T_1243 = asSInt(_T_1242)
node _T_1244 = eq(_T_1243, asSInt(UInt<1>(0h0)))
node _T_1245 = or(_T_1239, _T_1244)
node _uncommonBits_T_80 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_80 = bits(_uncommonBits_T_80, 1, 0)
node _T_1246 = shr(io.in.b.bits.source, 2)
node _T_1247 = eq(_T_1246, UInt<2>(0h3))
node _T_1248 = leq(UInt<1>(0h0), uncommonBits_80)
node _T_1249 = and(_T_1247, _T_1248)
node _T_1250 = leq(uncommonBits_80, UInt<2>(0h3))
node _T_1251 = and(_T_1249, _T_1250)
node _T_1252 = eq(_T_1251, UInt<1>(0h0))
node _T_1253 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1254 = cvt(_T_1253)
node _T_1255 = and(_T_1254, asSInt(UInt<1>(0h0)))
node _T_1256 = asSInt(_T_1255)
node _T_1257 = eq(_T_1256, asSInt(UInt<1>(0h0)))
node _T_1258 = or(_T_1252, _T_1257)
node _uncommonBits_T_81 = or(io.in.b.bits.source, UInt<3>(0h0))
node uncommonBits_81 = bits(_uncommonBits_T_81, 2, 0)
node _T_1259 = shr(io.in.b.bits.source, 3)
node _T_1260 = eq(_T_1259, UInt<2>(0h3))
node _T_1261 = leq(UInt<1>(0h0), uncommonBits_81)
node _T_1262 = and(_T_1260, _T_1261)
node _T_1263 = leq(uncommonBits_81, UInt<3>(0h7))
node _T_1264 = and(_T_1262, _T_1263)
node _T_1265 = eq(_T_1264, UInt<1>(0h0))
node _T_1266 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1267 = cvt(_T_1266)
node _T_1268 = and(_T_1267, asSInt(UInt<1>(0h0)))
node _T_1269 = asSInt(_T_1268)
node _T_1270 = eq(_T_1269, asSInt(UInt<1>(0h0)))
node _T_1271 = or(_T_1265, _T_1270)
node _uncommonBits_T_82 = or(io.in.b.bits.source, UInt<3>(0h0))
node uncommonBits_82 = bits(_uncommonBits_T_82, 2, 0)
node _T_1272 = shr(io.in.b.bits.source, 3)
node _T_1273 = eq(_T_1272, UInt<2>(0h2))
node _T_1274 = leq(UInt<1>(0h0), uncommonBits_82)
node _T_1275 = and(_T_1273, _T_1274)
node _T_1276 = leq(uncommonBits_82, UInt<3>(0h7))
node _T_1277 = and(_T_1275, _T_1276)
node _T_1278 = eq(_T_1277, UInt<1>(0h0))
node _T_1279 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1280 = cvt(_T_1279)
node _T_1281 = and(_T_1280, asSInt(UInt<1>(0h0)))
node _T_1282 = asSInt(_T_1281)
node _T_1283 = eq(_T_1282, asSInt(UInt<1>(0h0)))
node _T_1284 = or(_T_1278, _T_1283)
node _uncommonBits_T_83 = or(io.in.b.bits.source, UInt<3>(0h0))
node uncommonBits_83 = bits(_uncommonBits_T_83, 2, 0)
node _T_1285 = shr(io.in.b.bits.source, 3)
node _T_1286 = eq(_T_1285, UInt<4>(0h8))
node _T_1287 = leq(UInt<1>(0h0), uncommonBits_83)
node _T_1288 = and(_T_1286, _T_1287)
node _T_1289 = leq(uncommonBits_83, UInt<3>(0h4))
node _T_1290 = and(_T_1288, _T_1289)
node _T_1291 = eq(_T_1290, UInt<1>(0h0))
node _T_1292 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1293 = cvt(_T_1292)
node _T_1294 = and(_T_1293, asSInt(UInt<1>(0h0)))
node _T_1295 = asSInt(_T_1294)
node _T_1296 = eq(_T_1295, asSInt(UInt<1>(0h0)))
node _T_1297 = or(_T_1291, _T_1296)
node _T_1298 = eq(io.in.b.bits.source, UInt<7>(0h48))
node _T_1299 = eq(_T_1298, UInt<1>(0h0))
node _T_1300 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1301 = cvt(_T_1300)
node _T_1302 = and(_T_1301, asSInt(UInt<1>(0h0)))
node _T_1303 = asSInt(_T_1302)
node _T_1304 = eq(_T_1303, asSInt(UInt<1>(0h0)))
node _T_1305 = or(_T_1299, _T_1304)
node _T_1306 = and(_T_1206, _T_1219)
node _T_1307 = and(_T_1306, _T_1232)
node _T_1308 = and(_T_1307, _T_1245)
node _T_1309 = and(_T_1308, _T_1258)
node _T_1310 = and(_T_1309, _T_1271)
node _T_1311 = and(_T_1310, _T_1284)
node _T_1312 = and(_T_1311, _T_1297)
node _T_1313 = and(_T_1312, _T_1305)
node _T_1314 = asUInt(reset)
node _T_1315 = eq(_T_1314, UInt<1>(0h0))
when _T_1315 :
node _T_1316 = eq(_T_1313, UInt<1>(0h0))
when _T_1316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1313, UInt<1>(0h1), "") : assert_85
node _address_ok_T = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _address_ok_T_1 = cvt(_address_ok_T)
node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<17>(0h10000)))
node _address_ok_T_3 = asSInt(_address_ok_T_2)
node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0)))
node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _address_ok_T_6 = cvt(_address_ok_T_5)
node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<29>(0h10000000)))
node _address_ok_T_8 = asSInt(_address_ok_T_7)
node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0)))
wire _address_ok_WIRE : UInt<1>[2]
connect _address_ok_WIRE[0], _address_ok_T_4
connect _address_ok_WIRE[1], _address_ok_T_9
node address_ok = or(_address_ok_WIRE[0], _address_ok_WIRE[1])
node _is_aligned_mask_T_2 = dshl(UInt<6>(0h3f), io.in.b.bits.size)
node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 5, 0)
node is_aligned_mask_1 = not(_is_aligned_mask_T_3)
node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1)
node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0))
node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<4>(0h0))
node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0)
node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1)
node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 3, 0)
node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1))
node mask_sub_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<3>(0h4))
node mask_sub_sub_sub_size_1 = bits(mask_sizeOH_1, 3, 3)
node mask_sub_sub_sub_bit_1 = bits(io.in.b.bits.address, 3, 3)
node mask_sub_sub_sub_nbit_1 = eq(mask_sub_sub_sub_bit_1, UInt<1>(0h0))
node mask_sub_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit_1)
node _mask_sub_sub_sub_acc_T_2 = and(mask_sub_sub_sub_size_1, mask_sub_sub_sub_0_2_1)
node mask_sub_sub_sub_0_1_1 = or(mask_sub_sub_sub_sub_0_1_1, _mask_sub_sub_sub_acc_T_2)
node mask_sub_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_sub_bit_1)
node _mask_sub_sub_sub_acc_T_3 = and(mask_sub_sub_sub_size_1, mask_sub_sub_sub_1_2_1)
node mask_sub_sub_sub_1_1_1 = or(mask_sub_sub_sub_sub_0_1_1, _mask_sub_sub_sub_acc_T_3)
node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2)
node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2)
node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0))
node mask_sub_sub_0_2_1 = and(mask_sub_sub_sub_0_2_1, mask_sub_sub_nbit_1)
node _mask_sub_sub_acc_T_4 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1)
node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_4)
node mask_sub_sub_1_2_1 = and(mask_sub_sub_sub_0_2_1, mask_sub_sub_bit_1)
node _mask_sub_sub_acc_T_5 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1)
node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_5)
node mask_sub_sub_2_2_1 = and(mask_sub_sub_sub_1_2_1, mask_sub_sub_nbit_1)
node _mask_sub_sub_acc_T_6 = and(mask_sub_sub_size_1, mask_sub_sub_2_2_1)
node mask_sub_sub_2_1_1 = or(mask_sub_sub_sub_1_1_1, _mask_sub_sub_acc_T_6)
node mask_sub_sub_3_2_1 = and(mask_sub_sub_sub_1_2_1, mask_sub_sub_bit_1)
node _mask_sub_sub_acc_T_7 = and(mask_sub_sub_size_1, mask_sub_sub_3_2_1)
node mask_sub_sub_3_1_1 = or(mask_sub_sub_sub_1_1_1, _mask_sub_sub_acc_T_7)
node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1)
node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1)
node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0))
node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1)
node _mask_sub_acc_T_8 = and(mask_sub_size_1, mask_sub_0_2_1)
node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_8)
node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1)
node _mask_sub_acc_T_9 = and(mask_sub_size_1, mask_sub_1_2_1)
node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_9)
node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1)
node _mask_sub_acc_T_10 = and(mask_sub_size_1, mask_sub_2_2_1)
node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_10)
node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1)
node _mask_sub_acc_T_11 = and(mask_sub_size_1, mask_sub_3_2_1)
node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_11)
node mask_sub_4_2_1 = and(mask_sub_sub_2_2_1, mask_sub_nbit_1)
node _mask_sub_acc_T_12 = and(mask_sub_size_1, mask_sub_4_2_1)
node mask_sub_4_1_1 = or(mask_sub_sub_2_1_1, _mask_sub_acc_T_12)
node mask_sub_5_2_1 = and(mask_sub_sub_2_2_1, mask_sub_bit_1)
node _mask_sub_acc_T_13 = and(mask_sub_size_1, mask_sub_5_2_1)
node mask_sub_5_1_1 = or(mask_sub_sub_2_1_1, _mask_sub_acc_T_13)
node mask_sub_6_2_1 = and(mask_sub_sub_3_2_1, mask_sub_nbit_1)
node _mask_sub_acc_T_14 = and(mask_sub_size_1, mask_sub_6_2_1)
node mask_sub_6_1_1 = or(mask_sub_sub_3_1_1, _mask_sub_acc_T_14)
node mask_sub_7_2_1 = and(mask_sub_sub_3_2_1, mask_sub_bit_1)
node _mask_sub_acc_T_15 = and(mask_sub_size_1, mask_sub_7_2_1)
node mask_sub_7_1_1 = or(mask_sub_sub_3_1_1, _mask_sub_acc_T_15)
node mask_size_1 = bits(mask_sizeOH_1, 0, 0)
node mask_bit_1 = bits(io.in.b.bits.address, 0, 0)
node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0))
node mask_eq_16 = and(mask_sub_0_2_1, mask_nbit_1)
node _mask_acc_T_16 = and(mask_size_1, mask_eq_16)
node mask_acc_16 = or(mask_sub_0_1_1, _mask_acc_T_16)
node mask_eq_17 = and(mask_sub_0_2_1, mask_bit_1)
node _mask_acc_T_17 = and(mask_size_1, mask_eq_17)
node mask_acc_17 = or(mask_sub_0_1_1, _mask_acc_T_17)
node mask_eq_18 = and(mask_sub_1_2_1, mask_nbit_1)
node _mask_acc_T_18 = and(mask_size_1, mask_eq_18)
node mask_acc_18 = or(mask_sub_1_1_1, _mask_acc_T_18)
node mask_eq_19 = and(mask_sub_1_2_1, mask_bit_1)
node _mask_acc_T_19 = and(mask_size_1, mask_eq_19)
node mask_acc_19 = or(mask_sub_1_1_1, _mask_acc_T_19)
node mask_eq_20 = and(mask_sub_2_2_1, mask_nbit_1)
node _mask_acc_T_20 = and(mask_size_1, mask_eq_20)
node mask_acc_20 = or(mask_sub_2_1_1, _mask_acc_T_20)
node mask_eq_21 = and(mask_sub_2_2_1, mask_bit_1)
node _mask_acc_T_21 = and(mask_size_1, mask_eq_21)
node mask_acc_21 = or(mask_sub_2_1_1, _mask_acc_T_21)
node mask_eq_22 = and(mask_sub_3_2_1, mask_nbit_1)
node _mask_acc_T_22 = and(mask_size_1, mask_eq_22)
node mask_acc_22 = or(mask_sub_3_1_1, _mask_acc_T_22)
node mask_eq_23 = and(mask_sub_3_2_1, mask_bit_1)
node _mask_acc_T_23 = and(mask_size_1, mask_eq_23)
node mask_acc_23 = or(mask_sub_3_1_1, _mask_acc_T_23)
node mask_eq_24 = and(mask_sub_4_2_1, mask_nbit_1)
node _mask_acc_T_24 = and(mask_size_1, mask_eq_24)
node mask_acc_24 = or(mask_sub_4_1_1, _mask_acc_T_24)
node mask_eq_25 = and(mask_sub_4_2_1, mask_bit_1)
node _mask_acc_T_25 = and(mask_size_1, mask_eq_25)
node mask_acc_25 = or(mask_sub_4_1_1, _mask_acc_T_25)
node mask_eq_26 = and(mask_sub_5_2_1, mask_nbit_1)
node _mask_acc_T_26 = and(mask_size_1, mask_eq_26)
node mask_acc_26 = or(mask_sub_5_1_1, _mask_acc_T_26)
node mask_eq_27 = and(mask_sub_5_2_1, mask_bit_1)
node _mask_acc_T_27 = and(mask_size_1, mask_eq_27)
node mask_acc_27 = or(mask_sub_5_1_1, _mask_acc_T_27)
node mask_eq_28 = and(mask_sub_6_2_1, mask_nbit_1)
node _mask_acc_T_28 = and(mask_size_1, mask_eq_28)
node mask_acc_28 = or(mask_sub_6_1_1, _mask_acc_T_28)
node mask_eq_29 = and(mask_sub_6_2_1, mask_bit_1)
node _mask_acc_T_29 = and(mask_size_1, mask_eq_29)
node mask_acc_29 = or(mask_sub_6_1_1, _mask_acc_T_29)
node mask_eq_30 = and(mask_sub_7_2_1, mask_nbit_1)
node _mask_acc_T_30 = and(mask_size_1, mask_eq_30)
node mask_acc_30 = or(mask_sub_7_1_1, _mask_acc_T_30)
node mask_eq_31 = and(mask_sub_7_2_1, mask_bit_1)
node _mask_acc_T_31 = and(mask_size_1, mask_eq_31)
node mask_acc_31 = or(mask_sub_7_1_1, _mask_acc_T_31)
node mask_lo_lo_lo_1 = cat(mask_acc_17, mask_acc_16)
node mask_lo_lo_hi_1 = cat(mask_acc_19, mask_acc_18)
node mask_lo_lo_1 = cat(mask_lo_lo_hi_1, mask_lo_lo_lo_1)
node mask_lo_hi_lo_1 = cat(mask_acc_21, mask_acc_20)
node mask_lo_hi_hi_1 = cat(mask_acc_23, mask_acc_22)
node mask_lo_hi_1 = cat(mask_lo_hi_hi_1, mask_lo_hi_lo_1)
node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1)
node mask_hi_lo_lo_1 = cat(mask_acc_25, mask_acc_24)
node mask_hi_lo_hi_1 = cat(mask_acc_27, mask_acc_26)
node mask_hi_lo_1 = cat(mask_hi_lo_hi_1, mask_hi_lo_lo_1)
node mask_hi_hi_lo_1 = cat(mask_acc_29, mask_acc_28)
node mask_hi_hi_hi_1 = cat(mask_acc_31, mask_acc_30)
node mask_hi_hi_1 = cat(mask_hi_hi_hi_1, mask_hi_hi_lo_1)
node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1)
node mask_1 = cat(mask_hi_1, mask_lo_1)
node _legal_source_T = eq(io.in.b.bits.source, UInt<6>(0h20))
node _legal_source_uncommonBits_T = or(io.in.b.bits.source, UInt<2>(0h0))
node legal_source_uncommonBits = bits(_legal_source_uncommonBits_T, 1, 0)
node _legal_source_T_1 = shr(io.in.b.bits.source, 2)
node _legal_source_T_2 = eq(_legal_source_T_1, UInt<1>(0h0))
node _legal_source_T_3 = leq(UInt<1>(0h0), legal_source_uncommonBits)
node _legal_source_T_4 = and(_legal_source_T_2, _legal_source_T_3)
node _legal_source_T_5 = leq(legal_source_uncommonBits, UInt<2>(0h3))
node _legal_source_T_6 = and(_legal_source_T_4, _legal_source_T_5)
node _legal_source_uncommonBits_T_1 = or(io.in.b.bits.source, UInt<2>(0h0))
node legal_source_uncommonBits_1 = bits(_legal_source_uncommonBits_T_1, 1, 0)
node _legal_source_T_7 = shr(io.in.b.bits.source, 2)
node _legal_source_T_8 = eq(_legal_source_T_7, UInt<1>(0h1))
node _legal_source_T_9 = leq(UInt<1>(0h0), legal_source_uncommonBits_1)
node _legal_source_T_10 = and(_legal_source_T_8, _legal_source_T_9)
node _legal_source_T_11 = leq(legal_source_uncommonBits_1, UInt<2>(0h3))
node _legal_source_T_12 = and(_legal_source_T_10, _legal_source_T_11)
node _legal_source_uncommonBits_T_2 = or(io.in.b.bits.source, UInt<2>(0h0))
node legal_source_uncommonBits_2 = bits(_legal_source_uncommonBits_T_2, 1, 0)
node _legal_source_T_13 = shr(io.in.b.bits.source, 2)
node _legal_source_T_14 = eq(_legal_source_T_13, UInt<2>(0h2))
node _legal_source_T_15 = leq(UInt<1>(0h0), legal_source_uncommonBits_2)
node _legal_source_T_16 = and(_legal_source_T_14, _legal_source_T_15)
node _legal_source_T_17 = leq(legal_source_uncommonBits_2, UInt<2>(0h3))
node _legal_source_T_18 = and(_legal_source_T_16, _legal_source_T_17)
node _legal_source_uncommonBits_T_3 = or(io.in.b.bits.source, UInt<2>(0h0))
node legal_source_uncommonBits_3 = bits(_legal_source_uncommonBits_T_3, 1, 0)
node _legal_source_T_19 = shr(io.in.b.bits.source, 2)
node _legal_source_T_20 = eq(_legal_source_T_19, UInt<2>(0h3))
node _legal_source_T_21 = leq(UInt<1>(0h0), legal_source_uncommonBits_3)
node _legal_source_T_22 = and(_legal_source_T_20, _legal_source_T_21)
node _legal_source_T_23 = leq(legal_source_uncommonBits_3, UInt<2>(0h3))
node _legal_source_T_24 = and(_legal_source_T_22, _legal_source_T_23)
node _legal_source_uncommonBits_T_4 = or(io.in.b.bits.source, UInt<3>(0h0))
node legal_source_uncommonBits_4 = bits(_legal_source_uncommonBits_T_4, 2, 0)
node _legal_source_T_25 = shr(io.in.b.bits.source, 3)
node _legal_source_T_26 = eq(_legal_source_T_25, UInt<2>(0h3))
node _legal_source_T_27 = leq(UInt<1>(0h0), legal_source_uncommonBits_4)
node _legal_source_T_28 = and(_legal_source_T_26, _legal_source_T_27)
node _legal_source_T_29 = leq(legal_source_uncommonBits_4, UInt<3>(0h7))
node _legal_source_T_30 = and(_legal_source_T_28, _legal_source_T_29)
node _legal_source_uncommonBits_T_5 = or(io.in.b.bits.source, UInt<3>(0h0))
node legal_source_uncommonBits_5 = bits(_legal_source_uncommonBits_T_5, 2, 0)
node _legal_source_T_31 = shr(io.in.b.bits.source, 3)
node _legal_source_T_32 = eq(_legal_source_T_31, UInt<2>(0h2))
node _legal_source_T_33 = leq(UInt<1>(0h0), legal_source_uncommonBits_5)
node _legal_source_T_34 = and(_legal_source_T_32, _legal_source_T_33)
node _legal_source_T_35 = leq(legal_source_uncommonBits_5, UInt<3>(0h7))
node _legal_source_T_36 = and(_legal_source_T_34, _legal_source_T_35)
node _legal_source_uncommonBits_T_6 = or(io.in.b.bits.source, UInt<3>(0h0))
node legal_source_uncommonBits_6 = bits(_legal_source_uncommonBits_T_6, 2, 0)
node _legal_source_T_37 = shr(io.in.b.bits.source, 3)
node _legal_source_T_38 = eq(_legal_source_T_37, UInt<4>(0h8))
node _legal_source_T_39 = leq(UInt<1>(0h0), legal_source_uncommonBits_6)
node _legal_source_T_40 = and(_legal_source_T_38, _legal_source_T_39)
node _legal_source_T_41 = leq(legal_source_uncommonBits_6, UInt<3>(0h4))
node _legal_source_T_42 = and(_legal_source_T_40, _legal_source_T_41)
node _legal_source_T_43 = eq(io.in.b.bits.source, UInt<7>(0h48))
wire _legal_source_WIRE : UInt<1>[9]
connect _legal_source_WIRE[0], _legal_source_T
connect _legal_source_WIRE[1], _legal_source_T_6
connect _legal_source_WIRE[2], _legal_source_T_12
connect _legal_source_WIRE[3], _legal_source_T_18
connect _legal_source_WIRE[4], _legal_source_T_24
connect _legal_source_WIRE[5], _legal_source_T_30
connect _legal_source_WIRE[6], _legal_source_T_36
connect _legal_source_WIRE[7], _legal_source_T_42
connect _legal_source_WIRE[8], _legal_source_T_43
node _legal_source_T_44 = mux(_legal_source_WIRE[0], UInt<6>(0h20), UInt<1>(0h0))
node _legal_source_T_45 = mux(_legal_source_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _legal_source_T_46 = mux(_legal_source_WIRE[2], UInt<3>(0h4), UInt<1>(0h0))
node _legal_source_T_47 = mux(_legal_source_WIRE[3], UInt<4>(0h8), UInt<1>(0h0))
node _legal_source_T_48 = mux(_legal_source_WIRE[4], UInt<4>(0hc), UInt<1>(0h0))
node _legal_source_T_49 = mux(_legal_source_WIRE[5], UInt<5>(0h18), UInt<1>(0h0))
node _legal_source_T_50 = mux(_legal_source_WIRE[6], UInt<5>(0h10), UInt<1>(0h0))
node _legal_source_T_51 = mux(_legal_source_WIRE[7], UInt<7>(0h40), UInt<1>(0h0))
node _legal_source_T_52 = mux(_legal_source_WIRE[8], UInt<7>(0h48), UInt<1>(0h0))
node _legal_source_T_53 = or(_legal_source_T_44, _legal_source_T_45)
node _legal_source_T_54 = or(_legal_source_T_53, _legal_source_T_46)
node _legal_source_T_55 = or(_legal_source_T_54, _legal_source_T_47)
node _legal_source_T_56 = or(_legal_source_T_55, _legal_source_T_48)
node _legal_source_T_57 = or(_legal_source_T_56, _legal_source_T_49)
node _legal_source_T_58 = or(_legal_source_T_57, _legal_source_T_50)
node _legal_source_T_59 = or(_legal_source_T_58, _legal_source_T_51)
node _legal_source_T_60 = or(_legal_source_T_59, _legal_source_T_52)
wire _legal_source_WIRE_1 : UInt<7>
connect _legal_source_WIRE_1, _legal_source_T_60
node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source)
node _T_1317 = eq(io.in.b.bits.opcode, UInt<3>(0h6))
when _T_1317 :
node _T_1318 = eq(io.in.b.bits.source, UInt<6>(0h20))
node _uncommonBits_T_84 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_84 = bits(_uncommonBits_T_84, 1, 0)
node _T_1319 = shr(io.in.b.bits.source, 2)
node _T_1320 = eq(_T_1319, UInt<1>(0h0))
node _T_1321 = leq(UInt<1>(0h0), uncommonBits_84)
node _T_1322 = and(_T_1320, _T_1321)
node _T_1323 = leq(uncommonBits_84, UInt<2>(0h3))
node _T_1324 = and(_T_1322, _T_1323)
node _uncommonBits_T_85 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_85 = bits(_uncommonBits_T_85, 1, 0)
node _T_1325 = shr(io.in.b.bits.source, 2)
node _T_1326 = eq(_T_1325, UInt<1>(0h1))
node _T_1327 = leq(UInt<1>(0h0), uncommonBits_85)
node _T_1328 = and(_T_1326, _T_1327)
node _T_1329 = leq(uncommonBits_85, UInt<2>(0h3))
node _T_1330 = and(_T_1328, _T_1329)
node _uncommonBits_T_86 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_86 = bits(_uncommonBits_T_86, 1, 0)
node _T_1331 = shr(io.in.b.bits.source, 2)
node _T_1332 = eq(_T_1331, UInt<2>(0h2))
node _T_1333 = leq(UInt<1>(0h0), uncommonBits_86)
node _T_1334 = and(_T_1332, _T_1333)
node _T_1335 = leq(uncommonBits_86, UInt<2>(0h3))
node _T_1336 = and(_T_1334, _T_1335)
node _uncommonBits_T_87 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_87 = bits(_uncommonBits_T_87, 1, 0)
node _T_1337 = shr(io.in.b.bits.source, 2)
node _T_1338 = eq(_T_1337, UInt<2>(0h3))
node _T_1339 = leq(UInt<1>(0h0), uncommonBits_87)
node _T_1340 = and(_T_1338, _T_1339)
node _T_1341 = leq(uncommonBits_87, UInt<2>(0h3))
node _T_1342 = and(_T_1340, _T_1341)
node _uncommonBits_T_88 = or(io.in.b.bits.source, UInt<3>(0h0))
node uncommonBits_88 = bits(_uncommonBits_T_88, 2, 0)
node _T_1343 = shr(io.in.b.bits.source, 3)
node _T_1344 = eq(_T_1343, UInt<2>(0h3))
node _T_1345 = leq(UInt<1>(0h0), uncommonBits_88)
node _T_1346 = and(_T_1344, _T_1345)
node _T_1347 = leq(uncommonBits_88, UInt<3>(0h7))
node _T_1348 = and(_T_1346, _T_1347)
node _uncommonBits_T_89 = or(io.in.b.bits.source, UInt<3>(0h0))
node uncommonBits_89 = bits(_uncommonBits_T_89, 2, 0)
node _T_1349 = shr(io.in.b.bits.source, 3)
node _T_1350 = eq(_T_1349, UInt<2>(0h2))
node _T_1351 = leq(UInt<1>(0h0), uncommonBits_89)
node _T_1352 = and(_T_1350, _T_1351)
node _T_1353 = leq(uncommonBits_89, UInt<3>(0h7))
node _T_1354 = and(_T_1352, _T_1353)
node _uncommonBits_T_90 = or(io.in.b.bits.source, UInt<3>(0h0))
node uncommonBits_90 = bits(_uncommonBits_T_90, 2, 0)
node _T_1355 = shr(io.in.b.bits.source, 3)
node _T_1356 = eq(_T_1355, UInt<4>(0h8))
node _T_1357 = leq(UInt<1>(0h0), uncommonBits_90)
node _T_1358 = and(_T_1356, _T_1357)
node _T_1359 = leq(uncommonBits_90, UInt<3>(0h4))
node _T_1360 = and(_T_1358, _T_1359)
node _T_1361 = eq(io.in.b.bits.source, UInt<7>(0h48))
wire _WIRE_4 : UInt<1>[9]
connect _WIRE_4[0], _T_1318
connect _WIRE_4[1], _T_1324
connect _WIRE_4[2], _T_1330
connect _WIRE_4[3], _T_1336
connect _WIRE_4[4], _T_1342
connect _WIRE_4[5], _T_1348
connect _WIRE_4[6], _T_1354
connect _WIRE_4[7], _T_1360
connect _WIRE_4[8], _T_1361
node _T_1362 = eq(UInt<3>(0h6), io.in.b.bits.size)
node _T_1363 = mux(_WIRE_4[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_1364 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_1365 = mux(_WIRE_4[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_1366 = mux(_WIRE_4[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_1367 = mux(_WIRE_4[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_1368 = mux(_WIRE_4[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_1369 = mux(_WIRE_4[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_1370 = mux(_WIRE_4[7], _T_1362, UInt<1>(0h0))
node _T_1371 = mux(_WIRE_4[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_1372 = or(_T_1363, _T_1364)
node _T_1373 = or(_T_1372, _T_1365)
node _T_1374 = or(_T_1373, _T_1366)
node _T_1375 = or(_T_1374, _T_1367)
node _T_1376 = or(_T_1375, _T_1368)
node _T_1377 = or(_T_1376, _T_1369)
node _T_1378 = or(_T_1377, _T_1370)
node _T_1379 = or(_T_1378, _T_1371)
wire _WIRE_5 : UInt<1>
connect _WIRE_5, _T_1379
node _T_1380 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1381 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1382 = and(_T_1380, _T_1381)
node _T_1383 = or(UInt<1>(0h0), _T_1382)
node _T_1384 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1385 = cvt(_T_1384)
node _T_1386 = and(_T_1385, asSInt(UInt<17>(0h10000)))
node _T_1387 = asSInt(_T_1386)
node _T_1388 = eq(_T_1387, asSInt(UInt<1>(0h0)))
node _T_1389 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1390 = cvt(_T_1389)
node _T_1391 = and(_T_1390, asSInt(UInt<29>(0h10000000)))
node _T_1392 = asSInt(_T_1391)
node _T_1393 = eq(_T_1392, asSInt(UInt<1>(0h0)))
node _T_1394 = or(_T_1388, _T_1393)
node _T_1395 = and(_T_1383, _T_1394)
node _T_1396 = or(UInt<1>(0h0), _T_1395)
node _T_1397 = and(_WIRE_5, _T_1396)
node _T_1398 = asUInt(reset)
node _T_1399 = eq(_T_1398, UInt<1>(0h0))
when _T_1399 :
node _T_1400 = eq(_T_1397, UInt<1>(0h0))
when _T_1400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86
assert(clock, _T_1397, UInt<1>(0h1), "") : assert_86
node _T_1401 = asUInt(reset)
node _T_1402 = eq(_T_1401, UInt<1>(0h0))
when _T_1402 :
node _T_1403 = eq(address_ok, UInt<1>(0h0))
when _T_1403 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87
assert(clock, address_ok, UInt<1>(0h1), "") : assert_87
node _T_1404 = asUInt(reset)
node _T_1405 = eq(_T_1404, UInt<1>(0h0))
when _T_1405 :
node _T_1406 = eq(legal_source, UInt<1>(0h0))
when _T_1406 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88
assert(clock, legal_source, UInt<1>(0h1), "") : assert_88
node _T_1407 = asUInt(reset)
node _T_1408 = eq(_T_1407, UInt<1>(0h0))
when _T_1408 :
node _T_1409 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1409 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89
node _T_1410 = leq(io.in.b.bits.param, UInt<2>(0h2))
node _T_1411 = asUInt(reset)
node _T_1412 = eq(_T_1411, UInt<1>(0h0))
when _T_1412 :
node _T_1413 = eq(_T_1410, UInt<1>(0h0))
when _T_1413 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90
assert(clock, _T_1410, UInt<1>(0h1), "") : assert_90
node _T_1414 = eq(io.in.b.bits.mask, mask_1)
node _T_1415 = asUInt(reset)
node _T_1416 = eq(_T_1415, UInt<1>(0h0))
when _T_1416 :
node _T_1417 = eq(_T_1414, UInt<1>(0h0))
when _T_1417 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91
assert(clock, _T_1414, UInt<1>(0h1), "") : assert_91
node _T_1418 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_1419 = asUInt(reset)
node _T_1420 = eq(_T_1419, UInt<1>(0h0))
when _T_1420 :
node _T_1421 = eq(_T_1418, UInt<1>(0h0))
when _T_1421 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1418, UInt<1>(0h1), "") : assert_92
node _T_1422 = eq(io.in.b.bits.opcode, UInt<3>(0h4))
when _T_1422 :
node _T_1423 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1424 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1425 = and(_T_1423, _T_1424)
node _T_1426 = or(UInt<1>(0h0), _T_1425)
node _T_1427 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1428 = cvt(_T_1427)
node _T_1429 = and(_T_1428, asSInt(UInt<17>(0h10000)))
node _T_1430 = asSInt(_T_1429)
node _T_1431 = eq(_T_1430, asSInt(UInt<1>(0h0)))
node _T_1432 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1433 = cvt(_T_1432)
node _T_1434 = and(_T_1433, asSInt(UInt<29>(0h10000000)))
node _T_1435 = asSInt(_T_1434)
node _T_1436 = eq(_T_1435, asSInt(UInt<1>(0h0)))
node _T_1437 = or(_T_1431, _T_1436)
node _T_1438 = and(_T_1426, _T_1437)
node _T_1439 = or(UInt<1>(0h0), _T_1438)
node _T_1440 = and(UInt<1>(0h0), _T_1439)
node _T_1441 = asUInt(reset)
node _T_1442 = eq(_T_1441, UInt<1>(0h0))
when _T_1442 :
node _T_1443 = eq(_T_1440, UInt<1>(0h0))
when _T_1443 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93
assert(clock, _T_1440, UInt<1>(0h1), "") : assert_93
node _T_1444 = asUInt(reset)
node _T_1445 = eq(_T_1444, UInt<1>(0h0))
when _T_1445 :
node _T_1446 = eq(address_ok, UInt<1>(0h0))
when _T_1446 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94
assert(clock, address_ok, UInt<1>(0h1), "") : assert_94
node _T_1447 = asUInt(reset)
node _T_1448 = eq(_T_1447, UInt<1>(0h0))
when _T_1448 :
node _T_1449 = eq(legal_source, UInt<1>(0h0))
when _T_1449 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95
assert(clock, legal_source, UInt<1>(0h1), "") : assert_95
node _T_1450 = asUInt(reset)
node _T_1451 = eq(_T_1450, UInt<1>(0h0))
when _T_1451 :
node _T_1452 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96
node _T_1453 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_1454 = asUInt(reset)
node _T_1455 = eq(_T_1454, UInt<1>(0h0))
when _T_1455 :
node _T_1456 = eq(_T_1453, UInt<1>(0h0))
when _T_1456 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97
assert(clock, _T_1453, UInt<1>(0h1), "") : assert_97
node _T_1457 = eq(io.in.b.bits.mask, mask_1)
node _T_1458 = asUInt(reset)
node _T_1459 = eq(_T_1458, UInt<1>(0h0))
when _T_1459 :
node _T_1460 = eq(_T_1457, UInt<1>(0h0))
when _T_1460 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1457, UInt<1>(0h1), "") : assert_98
node _T_1461 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_1462 = asUInt(reset)
node _T_1463 = eq(_T_1462, UInt<1>(0h0))
when _T_1463 :
node _T_1464 = eq(_T_1461, UInt<1>(0h0))
when _T_1464 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99
assert(clock, _T_1461, UInt<1>(0h1), "") : assert_99
node _T_1465 = eq(io.in.b.bits.opcode, UInt<1>(0h0))
when _T_1465 :
node _T_1466 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1467 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1468 = and(_T_1466, _T_1467)
node _T_1469 = or(UInt<1>(0h0), _T_1468)
node _T_1470 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1471 = cvt(_T_1470)
node _T_1472 = and(_T_1471, asSInt(UInt<17>(0h10000)))
node _T_1473 = asSInt(_T_1472)
node _T_1474 = eq(_T_1473, asSInt(UInt<1>(0h0)))
node _T_1475 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1476 = cvt(_T_1475)
node _T_1477 = and(_T_1476, asSInt(UInt<29>(0h10000000)))
node _T_1478 = asSInt(_T_1477)
node _T_1479 = eq(_T_1478, asSInt(UInt<1>(0h0)))
node _T_1480 = or(_T_1474, _T_1479)
node _T_1481 = and(_T_1469, _T_1480)
node _T_1482 = or(UInt<1>(0h0), _T_1481)
node _T_1483 = and(UInt<1>(0h0), _T_1482)
node _T_1484 = asUInt(reset)
node _T_1485 = eq(_T_1484, UInt<1>(0h0))
when _T_1485 :
node _T_1486 = eq(_T_1483, UInt<1>(0h0))
when _T_1486 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100
assert(clock, _T_1483, UInt<1>(0h1), "") : assert_100
node _T_1487 = asUInt(reset)
node _T_1488 = eq(_T_1487, UInt<1>(0h0))
when _T_1488 :
node _T_1489 = eq(address_ok, UInt<1>(0h0))
when _T_1489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101
assert(clock, address_ok, UInt<1>(0h1), "") : assert_101
node _T_1490 = asUInt(reset)
node _T_1491 = eq(_T_1490, UInt<1>(0h0))
when _T_1491 :
node _T_1492 = eq(legal_source, UInt<1>(0h0))
when _T_1492 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102
assert(clock, legal_source, UInt<1>(0h1), "") : assert_102
node _T_1493 = asUInt(reset)
node _T_1494 = eq(_T_1493, UInt<1>(0h0))
when _T_1494 :
node _T_1495 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1495 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103
node _T_1496 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_1497 = asUInt(reset)
node _T_1498 = eq(_T_1497, UInt<1>(0h0))
when _T_1498 :
node _T_1499 = eq(_T_1496, UInt<1>(0h0))
when _T_1499 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104
assert(clock, _T_1496, UInt<1>(0h1), "") : assert_104
node _T_1500 = eq(io.in.b.bits.mask, mask_1)
node _T_1501 = asUInt(reset)
node _T_1502 = eq(_T_1501, UInt<1>(0h0))
when _T_1502 :
node _T_1503 = eq(_T_1500, UInt<1>(0h0))
when _T_1503 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_1500, UInt<1>(0h1), "") : assert_105
node _T_1504 = eq(io.in.b.bits.opcode, UInt<1>(0h1))
when _T_1504 :
node _T_1505 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1506 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1507 = and(_T_1505, _T_1506)
node _T_1508 = or(UInt<1>(0h0), _T_1507)
node _T_1509 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1510 = cvt(_T_1509)
node _T_1511 = and(_T_1510, asSInt(UInt<17>(0h10000)))
node _T_1512 = asSInt(_T_1511)
node _T_1513 = eq(_T_1512, asSInt(UInt<1>(0h0)))
node _T_1514 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1515 = cvt(_T_1514)
node _T_1516 = and(_T_1515, asSInt(UInt<29>(0h10000000)))
node _T_1517 = asSInt(_T_1516)
node _T_1518 = eq(_T_1517, asSInt(UInt<1>(0h0)))
node _T_1519 = or(_T_1513, _T_1518)
node _T_1520 = and(_T_1508, _T_1519)
node _T_1521 = or(UInt<1>(0h0), _T_1520)
node _T_1522 = and(UInt<1>(0h0), _T_1521)
node _T_1523 = asUInt(reset)
node _T_1524 = eq(_T_1523, UInt<1>(0h0))
when _T_1524 :
node _T_1525 = eq(_T_1522, UInt<1>(0h0))
when _T_1525 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1522, UInt<1>(0h1), "") : assert_106
node _T_1526 = asUInt(reset)
node _T_1527 = eq(_T_1526, UInt<1>(0h0))
when _T_1527 :
node _T_1528 = eq(address_ok, UInt<1>(0h0))
when _T_1528 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, address_ok, UInt<1>(0h1), "") : assert_107
node _T_1529 = asUInt(reset)
node _T_1530 = eq(_T_1529, UInt<1>(0h0))
when _T_1530 :
node _T_1531 = eq(legal_source, UInt<1>(0h0))
when _T_1531 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108
assert(clock, legal_source, UInt<1>(0h1), "") : assert_108
node _T_1532 = asUInt(reset)
node _T_1533 = eq(_T_1532, UInt<1>(0h0))
when _T_1533 :
node _T_1534 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1534 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109
node _T_1535 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_1536 = asUInt(reset)
node _T_1537 = eq(_T_1536, UInt<1>(0h0))
when _T_1537 :
node _T_1538 = eq(_T_1535, UInt<1>(0h0))
when _T_1538 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110
assert(clock, _T_1535, UInt<1>(0h1), "") : assert_110
node _T_1539 = not(mask_1)
node _T_1540 = and(io.in.b.bits.mask, _T_1539)
node _T_1541 = eq(_T_1540, UInt<1>(0h0))
node _T_1542 = asUInt(reset)
node _T_1543 = eq(_T_1542, UInt<1>(0h0))
when _T_1543 :
node _T_1544 = eq(_T_1541, UInt<1>(0h0))
when _T_1544 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_1541, UInt<1>(0h1), "") : assert_111
node _T_1545 = eq(io.in.b.bits.opcode, UInt<2>(0h2))
when _T_1545 :
node _T_1546 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1547 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1548 = and(_T_1546, _T_1547)
node _T_1549 = or(UInt<1>(0h0), _T_1548)
node _T_1550 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1551 = cvt(_T_1550)
node _T_1552 = and(_T_1551, asSInt(UInt<17>(0h10000)))
node _T_1553 = asSInt(_T_1552)
node _T_1554 = eq(_T_1553, asSInt(UInt<1>(0h0)))
node _T_1555 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1556 = cvt(_T_1555)
node _T_1557 = and(_T_1556, asSInt(UInt<29>(0h10000000)))
node _T_1558 = asSInt(_T_1557)
node _T_1559 = eq(_T_1558, asSInt(UInt<1>(0h0)))
node _T_1560 = or(_T_1554, _T_1559)
node _T_1561 = and(_T_1549, _T_1560)
node _T_1562 = or(UInt<1>(0h0), _T_1561)
node _T_1563 = and(UInt<1>(0h0), _T_1562)
node _T_1564 = asUInt(reset)
node _T_1565 = eq(_T_1564, UInt<1>(0h0))
when _T_1565 :
node _T_1566 = eq(_T_1563, UInt<1>(0h0))
when _T_1566 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112
assert(clock, _T_1563, UInt<1>(0h1), "") : assert_112
node _T_1567 = asUInt(reset)
node _T_1568 = eq(_T_1567, UInt<1>(0h0))
when _T_1568 :
node _T_1569 = eq(address_ok, UInt<1>(0h0))
when _T_1569 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, address_ok, UInt<1>(0h1), "") : assert_113
node _T_1570 = asUInt(reset)
node _T_1571 = eq(_T_1570, UInt<1>(0h0))
when _T_1571 :
node _T_1572 = eq(legal_source, UInt<1>(0h0))
when _T_1572 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114
assert(clock, legal_source, UInt<1>(0h1), "") : assert_114
node _T_1573 = asUInt(reset)
node _T_1574 = eq(_T_1573, UInt<1>(0h0))
when _T_1574 :
node _T_1575 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115
node _T_1576 = leq(io.in.b.bits.param, UInt<3>(0h4))
node _T_1577 = asUInt(reset)
node _T_1578 = eq(_T_1577, UInt<1>(0h0))
when _T_1578 :
node _T_1579 = eq(_T_1576, UInt<1>(0h0))
when _T_1579 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116
assert(clock, _T_1576, UInt<1>(0h1), "") : assert_116
node _T_1580 = eq(io.in.b.bits.mask, mask_1)
node _T_1581 = asUInt(reset)
node _T_1582 = eq(_T_1581, UInt<1>(0h0))
when _T_1582 :
node _T_1583 = eq(_T_1580, UInt<1>(0h0))
when _T_1583 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117
assert(clock, _T_1580, UInt<1>(0h1), "") : assert_117
node _T_1584 = eq(io.in.b.bits.opcode, UInt<2>(0h3))
when _T_1584 :
node _T_1585 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1586 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1587 = and(_T_1585, _T_1586)
node _T_1588 = or(UInt<1>(0h0), _T_1587)
node _T_1589 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1590 = cvt(_T_1589)
node _T_1591 = and(_T_1590, asSInt(UInt<17>(0h10000)))
node _T_1592 = asSInt(_T_1591)
node _T_1593 = eq(_T_1592, asSInt(UInt<1>(0h0)))
node _T_1594 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1595 = cvt(_T_1594)
node _T_1596 = and(_T_1595, asSInt(UInt<29>(0h10000000)))
node _T_1597 = asSInt(_T_1596)
node _T_1598 = eq(_T_1597, asSInt(UInt<1>(0h0)))
node _T_1599 = or(_T_1593, _T_1598)
node _T_1600 = and(_T_1588, _T_1599)
node _T_1601 = or(UInt<1>(0h0), _T_1600)
node _T_1602 = and(UInt<1>(0h0), _T_1601)
node _T_1603 = asUInt(reset)
node _T_1604 = eq(_T_1603, UInt<1>(0h0))
when _T_1604 :
node _T_1605 = eq(_T_1602, UInt<1>(0h0))
when _T_1605 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118
assert(clock, _T_1602, UInt<1>(0h1), "") : assert_118
node _T_1606 = asUInt(reset)
node _T_1607 = eq(_T_1606, UInt<1>(0h0))
when _T_1607 :
node _T_1608 = eq(address_ok, UInt<1>(0h0))
when _T_1608 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119
assert(clock, address_ok, UInt<1>(0h1), "") : assert_119
node _T_1609 = asUInt(reset)
node _T_1610 = eq(_T_1609, UInt<1>(0h0))
when _T_1610 :
node _T_1611 = eq(legal_source, UInt<1>(0h0))
when _T_1611 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120
assert(clock, legal_source, UInt<1>(0h1), "") : assert_120
node _T_1612 = asUInt(reset)
node _T_1613 = eq(_T_1612, UInt<1>(0h0))
when _T_1613 :
node _T_1614 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1614 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121
node _T_1615 = leq(io.in.b.bits.param, UInt<3>(0h3))
node _T_1616 = asUInt(reset)
node _T_1617 = eq(_T_1616, UInt<1>(0h0))
when _T_1617 :
node _T_1618 = eq(_T_1615, UInt<1>(0h0))
when _T_1618 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122
assert(clock, _T_1615, UInt<1>(0h1), "") : assert_122
node _T_1619 = eq(io.in.b.bits.mask, mask_1)
node _T_1620 = asUInt(reset)
node _T_1621 = eq(_T_1620, UInt<1>(0h0))
when _T_1621 :
node _T_1622 = eq(_T_1619, UInt<1>(0h0))
when _T_1622 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123
assert(clock, _T_1619, UInt<1>(0h1), "") : assert_123
node _T_1623 = eq(io.in.b.bits.opcode, UInt<3>(0h5))
when _T_1623 :
node _T_1624 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1625 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1626 = and(_T_1624, _T_1625)
node _T_1627 = or(UInt<1>(0h0), _T_1626)
node _T_1628 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1629 = cvt(_T_1628)
node _T_1630 = and(_T_1629, asSInt(UInt<17>(0h10000)))
node _T_1631 = asSInt(_T_1630)
node _T_1632 = eq(_T_1631, asSInt(UInt<1>(0h0)))
node _T_1633 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1634 = cvt(_T_1633)
node _T_1635 = and(_T_1634, asSInt(UInt<29>(0h10000000)))
node _T_1636 = asSInt(_T_1635)
node _T_1637 = eq(_T_1636, asSInt(UInt<1>(0h0)))
node _T_1638 = or(_T_1632, _T_1637)
node _T_1639 = and(_T_1627, _T_1638)
node _T_1640 = or(UInt<1>(0h0), _T_1639)
node _T_1641 = and(UInt<1>(0h0), _T_1640)
node _T_1642 = asUInt(reset)
node _T_1643 = eq(_T_1642, UInt<1>(0h0))
when _T_1643 :
node _T_1644 = eq(_T_1641, UInt<1>(0h0))
when _T_1644 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124
assert(clock, _T_1641, UInt<1>(0h1), "") : assert_124
node _T_1645 = asUInt(reset)
node _T_1646 = eq(_T_1645, UInt<1>(0h0))
when _T_1646 :
node _T_1647 = eq(address_ok, UInt<1>(0h0))
when _T_1647 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125
assert(clock, address_ok, UInt<1>(0h1), "") : assert_125
node _T_1648 = asUInt(reset)
node _T_1649 = eq(_T_1648, UInt<1>(0h0))
when _T_1649 :
node _T_1650 = eq(legal_source, UInt<1>(0h0))
when _T_1650 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126
assert(clock, legal_source, UInt<1>(0h1), "") : assert_126
node _T_1651 = asUInt(reset)
node _T_1652 = eq(_T_1651, UInt<1>(0h0))
when _T_1652 :
node _T_1653 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1653 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127
node _T_1654 = eq(io.in.b.bits.mask, mask_1)
node _T_1655 = asUInt(reset)
node _T_1656 = eq(_T_1655, UInt<1>(0h0))
when _T_1656 :
node _T_1657 = eq(_T_1654, UInt<1>(0h0))
when _T_1657 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128
assert(clock, _T_1654, UInt<1>(0h1), "") : assert_128
node _T_1658 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_1659 = asUInt(reset)
node _T_1660 = eq(_T_1659, UInt<1>(0h0))
when _T_1660 :
node _T_1661 = eq(_T_1658, UInt<1>(0h0))
when _T_1661 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129
assert(clock, _T_1658, UInt<1>(0h1), "") : assert_129
when io.in.c.valid :
node _T_1662 = leq(io.in.c.bits.opcode, UInt<3>(0h7))
node _T_1663 = asUInt(reset)
node _T_1664 = eq(_T_1663, UInt<1>(0h0))
when _T_1664 :
node _T_1665 = eq(_T_1662, UInt<1>(0h0))
when _T_1665 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130
assert(clock, _T_1662, UInt<1>(0h1), "") : assert_130
node _source_ok_T_102 = eq(io.in.c.bits.source, UInt<6>(0h20))
node _source_ok_uncommonBits_T_14 = or(io.in.c.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_14 = bits(_source_ok_uncommonBits_T_14, 1, 0)
node _source_ok_T_103 = shr(io.in.c.bits.source, 2)
node _source_ok_T_104 = eq(_source_ok_T_103, UInt<1>(0h0))
node _source_ok_T_105 = leq(UInt<1>(0h0), source_ok_uncommonBits_14)
node _source_ok_T_106 = and(_source_ok_T_104, _source_ok_T_105)
node _source_ok_T_107 = leq(source_ok_uncommonBits_14, UInt<2>(0h3))
node _source_ok_T_108 = and(_source_ok_T_106, _source_ok_T_107)
node _source_ok_uncommonBits_T_15 = or(io.in.c.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_15 = bits(_source_ok_uncommonBits_T_15, 1, 0)
node _source_ok_T_109 = shr(io.in.c.bits.source, 2)
node _source_ok_T_110 = eq(_source_ok_T_109, UInt<1>(0h1))
node _source_ok_T_111 = leq(UInt<1>(0h0), source_ok_uncommonBits_15)
node _source_ok_T_112 = and(_source_ok_T_110, _source_ok_T_111)
node _source_ok_T_113 = leq(source_ok_uncommonBits_15, UInt<2>(0h3))
node _source_ok_T_114 = and(_source_ok_T_112, _source_ok_T_113)
node _source_ok_uncommonBits_T_16 = or(io.in.c.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_16 = bits(_source_ok_uncommonBits_T_16, 1, 0)
node _source_ok_T_115 = shr(io.in.c.bits.source, 2)
node _source_ok_T_116 = eq(_source_ok_T_115, UInt<2>(0h2))
node _source_ok_T_117 = leq(UInt<1>(0h0), source_ok_uncommonBits_16)
node _source_ok_T_118 = and(_source_ok_T_116, _source_ok_T_117)
node _source_ok_T_119 = leq(source_ok_uncommonBits_16, UInt<2>(0h3))
node _source_ok_T_120 = and(_source_ok_T_118, _source_ok_T_119)
node _source_ok_uncommonBits_T_17 = or(io.in.c.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_17 = bits(_source_ok_uncommonBits_T_17, 1, 0)
node _source_ok_T_121 = shr(io.in.c.bits.source, 2)
node _source_ok_T_122 = eq(_source_ok_T_121, UInt<2>(0h3))
node _source_ok_T_123 = leq(UInt<1>(0h0), source_ok_uncommonBits_17)
node _source_ok_T_124 = and(_source_ok_T_122, _source_ok_T_123)
node _source_ok_T_125 = leq(source_ok_uncommonBits_17, UInt<2>(0h3))
node _source_ok_T_126 = and(_source_ok_T_124, _source_ok_T_125)
node _source_ok_uncommonBits_T_18 = or(io.in.c.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_18 = bits(_source_ok_uncommonBits_T_18, 2, 0)
node _source_ok_T_127 = shr(io.in.c.bits.source, 3)
node _source_ok_T_128 = eq(_source_ok_T_127, UInt<2>(0h3))
node _source_ok_T_129 = leq(UInt<1>(0h0), source_ok_uncommonBits_18)
node _source_ok_T_130 = and(_source_ok_T_128, _source_ok_T_129)
node _source_ok_T_131 = leq(source_ok_uncommonBits_18, UInt<3>(0h7))
node _source_ok_T_132 = and(_source_ok_T_130, _source_ok_T_131)
node _source_ok_uncommonBits_T_19 = or(io.in.c.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_19 = bits(_source_ok_uncommonBits_T_19, 2, 0)
node _source_ok_T_133 = shr(io.in.c.bits.source, 3)
node _source_ok_T_134 = eq(_source_ok_T_133, UInt<2>(0h2))
node _source_ok_T_135 = leq(UInt<1>(0h0), source_ok_uncommonBits_19)
node _source_ok_T_136 = and(_source_ok_T_134, _source_ok_T_135)
node _source_ok_T_137 = leq(source_ok_uncommonBits_19, UInt<3>(0h7))
node _source_ok_T_138 = and(_source_ok_T_136, _source_ok_T_137)
node _source_ok_uncommonBits_T_20 = or(io.in.c.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_20 = bits(_source_ok_uncommonBits_T_20, 2, 0)
node _source_ok_T_139 = shr(io.in.c.bits.source, 3)
node _source_ok_T_140 = eq(_source_ok_T_139, UInt<4>(0h8))
node _source_ok_T_141 = leq(UInt<1>(0h0), source_ok_uncommonBits_20)
node _source_ok_T_142 = and(_source_ok_T_140, _source_ok_T_141)
node _source_ok_T_143 = leq(source_ok_uncommonBits_20, UInt<3>(0h4))
node _source_ok_T_144 = and(_source_ok_T_142, _source_ok_T_143)
node _source_ok_T_145 = eq(io.in.c.bits.source, UInt<7>(0h48))
wire _source_ok_WIRE_2 : UInt<1>[9]
connect _source_ok_WIRE_2[0], _source_ok_T_102
connect _source_ok_WIRE_2[1], _source_ok_T_108
connect _source_ok_WIRE_2[2], _source_ok_T_114
connect _source_ok_WIRE_2[3], _source_ok_T_120
connect _source_ok_WIRE_2[4], _source_ok_T_126
connect _source_ok_WIRE_2[5], _source_ok_T_132
connect _source_ok_WIRE_2[6], _source_ok_T_138
connect _source_ok_WIRE_2[7], _source_ok_T_144
connect _source_ok_WIRE_2[8], _source_ok_T_145
node _source_ok_T_146 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1])
node _source_ok_T_147 = or(_source_ok_T_146, _source_ok_WIRE_2[2])
node _source_ok_T_148 = or(_source_ok_T_147, _source_ok_WIRE_2[3])
node _source_ok_T_149 = or(_source_ok_T_148, _source_ok_WIRE_2[4])
node _source_ok_T_150 = or(_source_ok_T_149, _source_ok_WIRE_2[5])
node _source_ok_T_151 = or(_source_ok_T_150, _source_ok_WIRE_2[6])
node _source_ok_T_152 = or(_source_ok_T_151, _source_ok_WIRE_2[7])
node source_ok_2 = or(_source_ok_T_152, _source_ok_WIRE_2[8])
node _is_aligned_mask_T_4 = dshl(UInt<6>(0h3f), io.in.c.bits.size)
node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 5, 0)
node is_aligned_mask_2 = not(_is_aligned_mask_T_5)
node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2)
node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0))
node _address_ok_T_10 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _address_ok_T_11 = cvt(_address_ok_T_10)
node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<17>(0h10000)))
node _address_ok_T_13 = asSInt(_address_ok_T_12)
node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0)))
node _address_ok_T_15 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _address_ok_T_16 = cvt(_address_ok_T_15)
node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<29>(0h10000000)))
node _address_ok_T_18 = asSInt(_address_ok_T_17)
node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0)))
wire _address_ok_WIRE_1 : UInt<1>[2]
connect _address_ok_WIRE_1[0], _address_ok_T_14
connect _address_ok_WIRE_1[1], _address_ok_T_19
node address_ok_1 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1])
node _T_1666 = eq(io.in.c.bits.source, UInt<6>(0h20))
node _T_1667 = eq(_T_1666, UInt<1>(0h0))
node _T_1668 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1669 = cvt(_T_1668)
node _T_1670 = and(_T_1669, asSInt(UInt<1>(0h0)))
node _T_1671 = asSInt(_T_1670)
node _T_1672 = eq(_T_1671, asSInt(UInt<1>(0h0)))
node _T_1673 = or(_T_1667, _T_1672)
node _uncommonBits_T_91 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_91 = bits(_uncommonBits_T_91, 1, 0)
node _T_1674 = shr(io.in.c.bits.source, 2)
node _T_1675 = eq(_T_1674, UInt<1>(0h0))
node _T_1676 = leq(UInt<1>(0h0), uncommonBits_91)
node _T_1677 = and(_T_1675, _T_1676)
node _T_1678 = leq(uncommonBits_91, UInt<2>(0h3))
node _T_1679 = and(_T_1677, _T_1678)
node _T_1680 = eq(_T_1679, UInt<1>(0h0))
node _T_1681 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1682 = cvt(_T_1681)
node _T_1683 = and(_T_1682, asSInt(UInt<1>(0h0)))
node _T_1684 = asSInt(_T_1683)
node _T_1685 = eq(_T_1684, asSInt(UInt<1>(0h0)))
node _T_1686 = or(_T_1680, _T_1685)
node _uncommonBits_T_92 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_92 = bits(_uncommonBits_T_92, 1, 0)
node _T_1687 = shr(io.in.c.bits.source, 2)
node _T_1688 = eq(_T_1687, UInt<1>(0h1))
node _T_1689 = leq(UInt<1>(0h0), uncommonBits_92)
node _T_1690 = and(_T_1688, _T_1689)
node _T_1691 = leq(uncommonBits_92, UInt<2>(0h3))
node _T_1692 = and(_T_1690, _T_1691)
node _T_1693 = eq(_T_1692, UInt<1>(0h0))
node _T_1694 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1695 = cvt(_T_1694)
node _T_1696 = and(_T_1695, asSInt(UInt<1>(0h0)))
node _T_1697 = asSInt(_T_1696)
node _T_1698 = eq(_T_1697, asSInt(UInt<1>(0h0)))
node _T_1699 = or(_T_1693, _T_1698)
node _uncommonBits_T_93 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_93 = bits(_uncommonBits_T_93, 1, 0)
node _T_1700 = shr(io.in.c.bits.source, 2)
node _T_1701 = eq(_T_1700, UInt<2>(0h2))
node _T_1702 = leq(UInt<1>(0h0), uncommonBits_93)
node _T_1703 = and(_T_1701, _T_1702)
node _T_1704 = leq(uncommonBits_93, UInt<2>(0h3))
node _T_1705 = and(_T_1703, _T_1704)
node _T_1706 = eq(_T_1705, UInt<1>(0h0))
node _T_1707 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1708 = cvt(_T_1707)
node _T_1709 = and(_T_1708, asSInt(UInt<1>(0h0)))
node _T_1710 = asSInt(_T_1709)
node _T_1711 = eq(_T_1710, asSInt(UInt<1>(0h0)))
node _T_1712 = or(_T_1706, _T_1711)
node _uncommonBits_T_94 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_94 = bits(_uncommonBits_T_94, 1, 0)
node _T_1713 = shr(io.in.c.bits.source, 2)
node _T_1714 = eq(_T_1713, UInt<2>(0h3))
node _T_1715 = leq(UInt<1>(0h0), uncommonBits_94)
node _T_1716 = and(_T_1714, _T_1715)
node _T_1717 = leq(uncommonBits_94, UInt<2>(0h3))
node _T_1718 = and(_T_1716, _T_1717)
node _T_1719 = eq(_T_1718, UInt<1>(0h0))
node _T_1720 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1721 = cvt(_T_1720)
node _T_1722 = and(_T_1721, asSInt(UInt<1>(0h0)))
node _T_1723 = asSInt(_T_1722)
node _T_1724 = eq(_T_1723, asSInt(UInt<1>(0h0)))
node _T_1725 = or(_T_1719, _T_1724)
node _uncommonBits_T_95 = or(io.in.c.bits.source, UInt<3>(0h0))
node uncommonBits_95 = bits(_uncommonBits_T_95, 2, 0)
node _T_1726 = shr(io.in.c.bits.source, 3)
node _T_1727 = eq(_T_1726, UInt<2>(0h3))
node _T_1728 = leq(UInt<1>(0h0), uncommonBits_95)
node _T_1729 = and(_T_1727, _T_1728)
node _T_1730 = leq(uncommonBits_95, UInt<3>(0h7))
node _T_1731 = and(_T_1729, _T_1730)
node _T_1732 = eq(_T_1731, UInt<1>(0h0))
node _T_1733 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1734 = cvt(_T_1733)
node _T_1735 = and(_T_1734, asSInt(UInt<1>(0h0)))
node _T_1736 = asSInt(_T_1735)
node _T_1737 = eq(_T_1736, asSInt(UInt<1>(0h0)))
node _T_1738 = or(_T_1732, _T_1737)
node _uncommonBits_T_96 = or(io.in.c.bits.source, UInt<3>(0h0))
node uncommonBits_96 = bits(_uncommonBits_T_96, 2, 0)
node _T_1739 = shr(io.in.c.bits.source, 3)
node _T_1740 = eq(_T_1739, UInt<2>(0h2))
node _T_1741 = leq(UInt<1>(0h0), uncommonBits_96)
node _T_1742 = and(_T_1740, _T_1741)
node _T_1743 = leq(uncommonBits_96, UInt<3>(0h7))
node _T_1744 = and(_T_1742, _T_1743)
node _T_1745 = eq(_T_1744, UInt<1>(0h0))
node _T_1746 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1747 = cvt(_T_1746)
node _T_1748 = and(_T_1747, asSInt(UInt<1>(0h0)))
node _T_1749 = asSInt(_T_1748)
node _T_1750 = eq(_T_1749, asSInt(UInt<1>(0h0)))
node _T_1751 = or(_T_1745, _T_1750)
node _uncommonBits_T_97 = or(io.in.c.bits.source, UInt<3>(0h0))
node uncommonBits_97 = bits(_uncommonBits_T_97, 2, 0)
node _T_1752 = shr(io.in.c.bits.source, 3)
node _T_1753 = eq(_T_1752, UInt<4>(0h8))
node _T_1754 = leq(UInt<1>(0h0), uncommonBits_97)
node _T_1755 = and(_T_1753, _T_1754)
node _T_1756 = leq(uncommonBits_97, UInt<3>(0h4))
node _T_1757 = and(_T_1755, _T_1756)
node _T_1758 = eq(_T_1757, UInt<1>(0h0))
node _T_1759 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1760 = cvt(_T_1759)
node _T_1761 = and(_T_1760, asSInt(UInt<1>(0h0)))
node _T_1762 = asSInt(_T_1761)
node _T_1763 = eq(_T_1762, asSInt(UInt<1>(0h0)))
node _T_1764 = or(_T_1758, _T_1763)
node _T_1765 = eq(io.in.c.bits.source, UInt<7>(0h48))
node _T_1766 = eq(_T_1765, UInt<1>(0h0))
node _T_1767 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1768 = cvt(_T_1767)
node _T_1769 = and(_T_1768, asSInt(UInt<1>(0h0)))
node _T_1770 = asSInt(_T_1769)
node _T_1771 = eq(_T_1770, asSInt(UInt<1>(0h0)))
node _T_1772 = or(_T_1766, _T_1771)
node _T_1773 = and(_T_1673, _T_1686)
node _T_1774 = and(_T_1773, _T_1699)
node _T_1775 = and(_T_1774, _T_1712)
node _T_1776 = and(_T_1775, _T_1725)
node _T_1777 = and(_T_1776, _T_1738)
node _T_1778 = and(_T_1777, _T_1751)
node _T_1779 = and(_T_1778, _T_1764)
node _T_1780 = and(_T_1779, _T_1772)
node _T_1781 = asUInt(reset)
node _T_1782 = eq(_T_1781, UInt<1>(0h0))
when _T_1782 :
node _T_1783 = eq(_T_1780, UInt<1>(0h0))
when _T_1783 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131
assert(clock, _T_1780, UInt<1>(0h1), "") : assert_131
node _T_1784 = eq(io.in.c.bits.opcode, UInt<3>(0h4))
when _T_1784 :
node _T_1785 = asUInt(reset)
node _T_1786 = eq(_T_1785, UInt<1>(0h0))
when _T_1786 :
node _T_1787 = eq(address_ok_1, UInt<1>(0h0))
when _T_1787 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132
node _T_1788 = asUInt(reset)
node _T_1789 = eq(_T_1788, UInt<1>(0h0))
when _T_1789 :
node _T_1790 = eq(source_ok_2, UInt<1>(0h0))
when _T_1790 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133
node _T_1791 = geq(io.in.c.bits.size, UInt<3>(0h4))
node _T_1792 = asUInt(reset)
node _T_1793 = eq(_T_1792, UInt<1>(0h0))
when _T_1793 :
node _T_1794 = eq(_T_1791, UInt<1>(0h0))
when _T_1794 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134
assert(clock, _T_1791, UInt<1>(0h1), "") : assert_134
node _T_1795 = asUInt(reset)
node _T_1796 = eq(_T_1795, UInt<1>(0h0))
when _T_1796 :
node _T_1797 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1797 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135
node _T_1798 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_1799 = asUInt(reset)
node _T_1800 = eq(_T_1799, UInt<1>(0h0))
when _T_1800 :
node _T_1801 = eq(_T_1798, UInt<1>(0h0))
when _T_1801 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136
assert(clock, _T_1798, UInt<1>(0h1), "") : assert_136
node _T_1802 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_1803 = asUInt(reset)
node _T_1804 = eq(_T_1803, UInt<1>(0h0))
when _T_1804 :
node _T_1805 = eq(_T_1802, UInt<1>(0h0))
when _T_1805 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137
assert(clock, _T_1802, UInt<1>(0h1), "") : assert_137
node _T_1806 = eq(io.in.c.bits.opcode, UInt<3>(0h5))
when _T_1806 :
node _T_1807 = asUInt(reset)
node _T_1808 = eq(_T_1807, UInt<1>(0h0))
when _T_1808 :
node _T_1809 = eq(address_ok_1, UInt<1>(0h0))
when _T_1809 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138
node _T_1810 = asUInt(reset)
node _T_1811 = eq(_T_1810, UInt<1>(0h0))
when _T_1811 :
node _T_1812 = eq(source_ok_2, UInt<1>(0h0))
when _T_1812 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139
node _T_1813 = geq(io.in.c.bits.size, UInt<3>(0h4))
node _T_1814 = asUInt(reset)
node _T_1815 = eq(_T_1814, UInt<1>(0h0))
when _T_1815 :
node _T_1816 = eq(_T_1813, UInt<1>(0h0))
when _T_1816 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140
assert(clock, _T_1813, UInt<1>(0h1), "") : assert_140
node _T_1817 = asUInt(reset)
node _T_1818 = eq(_T_1817, UInt<1>(0h0))
when _T_1818 :
node _T_1819 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1819 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141
node _T_1820 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_1821 = asUInt(reset)
node _T_1822 = eq(_T_1821, UInt<1>(0h0))
when _T_1822 :
node _T_1823 = eq(_T_1820, UInt<1>(0h0))
when _T_1823 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142
assert(clock, _T_1820, UInt<1>(0h1), "") : assert_142
node _T_1824 = eq(io.in.c.bits.opcode, UInt<3>(0h6))
when _T_1824 :
node _T_1825 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_1826 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_1827 = and(_T_1825, _T_1826)
node _T_1828 = eq(io.in.c.bits.source, UInt<6>(0h20))
node _uncommonBits_T_98 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_98 = bits(_uncommonBits_T_98, 1, 0)
node _T_1829 = shr(io.in.c.bits.source, 2)
node _T_1830 = eq(_T_1829, UInt<1>(0h0))
node _T_1831 = leq(UInt<1>(0h0), uncommonBits_98)
node _T_1832 = and(_T_1830, _T_1831)
node _T_1833 = leq(uncommonBits_98, UInt<2>(0h3))
node _T_1834 = and(_T_1832, _T_1833)
node _uncommonBits_T_99 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_99 = bits(_uncommonBits_T_99, 1, 0)
node _T_1835 = shr(io.in.c.bits.source, 2)
node _T_1836 = eq(_T_1835, UInt<1>(0h1))
node _T_1837 = leq(UInt<1>(0h0), uncommonBits_99)
node _T_1838 = and(_T_1836, _T_1837)
node _T_1839 = leq(uncommonBits_99, UInt<2>(0h3))
node _T_1840 = and(_T_1838, _T_1839)
node _uncommonBits_T_100 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_100 = bits(_uncommonBits_T_100, 1, 0)
node _T_1841 = shr(io.in.c.bits.source, 2)
node _T_1842 = eq(_T_1841, UInt<2>(0h2))
node _T_1843 = leq(UInt<1>(0h0), uncommonBits_100)
node _T_1844 = and(_T_1842, _T_1843)
node _T_1845 = leq(uncommonBits_100, UInt<2>(0h3))
node _T_1846 = and(_T_1844, _T_1845)
node _uncommonBits_T_101 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_101 = bits(_uncommonBits_T_101, 1, 0)
node _T_1847 = shr(io.in.c.bits.source, 2)
node _T_1848 = eq(_T_1847, UInt<2>(0h3))
node _T_1849 = leq(UInt<1>(0h0), uncommonBits_101)
node _T_1850 = and(_T_1848, _T_1849)
node _T_1851 = leq(uncommonBits_101, UInt<2>(0h3))
node _T_1852 = and(_T_1850, _T_1851)
node _uncommonBits_T_102 = or(io.in.c.bits.source, UInt<3>(0h0))
node uncommonBits_102 = bits(_uncommonBits_T_102, 2, 0)
node _T_1853 = shr(io.in.c.bits.source, 3)
node _T_1854 = eq(_T_1853, UInt<2>(0h3))
node _T_1855 = leq(UInt<1>(0h0), uncommonBits_102)
node _T_1856 = and(_T_1854, _T_1855)
node _T_1857 = leq(uncommonBits_102, UInt<3>(0h7))
node _T_1858 = and(_T_1856, _T_1857)
node _uncommonBits_T_103 = or(io.in.c.bits.source, UInt<3>(0h0))
node uncommonBits_103 = bits(_uncommonBits_T_103, 2, 0)
node _T_1859 = shr(io.in.c.bits.source, 3)
node _T_1860 = eq(_T_1859, UInt<2>(0h2))
node _T_1861 = leq(UInt<1>(0h0), uncommonBits_103)
node _T_1862 = and(_T_1860, _T_1861)
node _T_1863 = leq(uncommonBits_103, UInt<3>(0h7))
node _T_1864 = and(_T_1862, _T_1863)
node _uncommonBits_T_104 = or(io.in.c.bits.source, UInt<3>(0h0))
node uncommonBits_104 = bits(_uncommonBits_T_104, 2, 0)
node _T_1865 = shr(io.in.c.bits.source, 3)
node _T_1866 = eq(_T_1865, UInt<4>(0h8))
node _T_1867 = leq(UInt<1>(0h0), uncommonBits_104)
node _T_1868 = and(_T_1866, _T_1867)
node _T_1869 = leq(uncommonBits_104, UInt<3>(0h4))
node _T_1870 = and(_T_1868, _T_1869)
node _T_1871 = eq(io.in.c.bits.source, UInt<7>(0h48))
node _T_1872 = or(_T_1828, _T_1834)
node _T_1873 = or(_T_1872, _T_1840)
node _T_1874 = or(_T_1873, _T_1846)
node _T_1875 = or(_T_1874, _T_1852)
node _T_1876 = or(_T_1875, _T_1858)
node _T_1877 = or(_T_1876, _T_1864)
node _T_1878 = or(_T_1877, _T_1870)
node _T_1879 = or(_T_1878, _T_1871)
node _T_1880 = and(_T_1827, _T_1879)
node _T_1881 = or(UInt<1>(0h0), _T_1880)
node _T_1882 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_1883 = or(UInt<1>(0h0), _T_1882)
node _T_1884 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_1885 = cvt(_T_1884)
node _T_1886 = and(_T_1885, asSInt(UInt<17>(0h10000)))
node _T_1887 = asSInt(_T_1886)
node _T_1888 = eq(_T_1887, asSInt(UInt<1>(0h0)))
node _T_1889 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_1890 = cvt(_T_1889)
node _T_1891 = and(_T_1890, asSInt(UInt<29>(0h10000000)))
node _T_1892 = asSInt(_T_1891)
node _T_1893 = eq(_T_1892, asSInt(UInt<1>(0h0)))
node _T_1894 = or(_T_1888, _T_1893)
node _T_1895 = and(_T_1883, _T_1894)
node _T_1896 = or(UInt<1>(0h0), _T_1895)
node _T_1897 = and(_T_1881, _T_1896)
node _T_1898 = asUInt(reset)
node _T_1899 = eq(_T_1898, UInt<1>(0h0))
when _T_1899 :
node _T_1900 = eq(_T_1897, UInt<1>(0h0))
when _T_1900 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143
assert(clock, _T_1897, UInt<1>(0h1), "") : assert_143
node _T_1901 = eq(io.in.c.bits.source, UInt<6>(0h20))
node _uncommonBits_T_105 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_105 = bits(_uncommonBits_T_105, 1, 0)
node _T_1902 = shr(io.in.c.bits.source, 2)
node _T_1903 = eq(_T_1902, UInt<1>(0h0))
node _T_1904 = leq(UInt<1>(0h0), uncommonBits_105)
node _T_1905 = and(_T_1903, _T_1904)
node _T_1906 = leq(uncommonBits_105, UInt<2>(0h3))
node _T_1907 = and(_T_1905, _T_1906)
node _uncommonBits_T_106 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_106 = bits(_uncommonBits_T_106, 1, 0)
node _T_1908 = shr(io.in.c.bits.source, 2)
node _T_1909 = eq(_T_1908, UInt<1>(0h1))
node _T_1910 = leq(UInt<1>(0h0), uncommonBits_106)
node _T_1911 = and(_T_1909, _T_1910)
node _T_1912 = leq(uncommonBits_106, UInt<2>(0h3))
node _T_1913 = and(_T_1911, _T_1912)
node _uncommonBits_T_107 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_107 = bits(_uncommonBits_T_107, 1, 0)
node _T_1914 = shr(io.in.c.bits.source, 2)
node _T_1915 = eq(_T_1914, UInt<2>(0h2))
node _T_1916 = leq(UInt<1>(0h0), uncommonBits_107)
node _T_1917 = and(_T_1915, _T_1916)
node _T_1918 = leq(uncommonBits_107, UInt<2>(0h3))
node _T_1919 = and(_T_1917, _T_1918)
node _uncommonBits_T_108 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_108 = bits(_uncommonBits_T_108, 1, 0)
node _T_1920 = shr(io.in.c.bits.source, 2)
node _T_1921 = eq(_T_1920, UInt<2>(0h3))
node _T_1922 = leq(UInt<1>(0h0), uncommonBits_108)
node _T_1923 = and(_T_1921, _T_1922)
node _T_1924 = leq(uncommonBits_108, UInt<2>(0h3))
node _T_1925 = and(_T_1923, _T_1924)
node _uncommonBits_T_109 = or(io.in.c.bits.source, UInt<3>(0h0))
node uncommonBits_109 = bits(_uncommonBits_T_109, 2, 0)
node _T_1926 = shr(io.in.c.bits.source, 3)
node _T_1927 = eq(_T_1926, UInt<2>(0h3))
node _T_1928 = leq(UInt<1>(0h0), uncommonBits_109)
node _T_1929 = and(_T_1927, _T_1928)
node _T_1930 = leq(uncommonBits_109, UInt<3>(0h7))
node _T_1931 = and(_T_1929, _T_1930)
node _uncommonBits_T_110 = or(io.in.c.bits.source, UInt<3>(0h0))
node uncommonBits_110 = bits(_uncommonBits_T_110, 2, 0)
node _T_1932 = shr(io.in.c.bits.source, 3)
node _T_1933 = eq(_T_1932, UInt<2>(0h2))
node _T_1934 = leq(UInt<1>(0h0), uncommonBits_110)
node _T_1935 = and(_T_1933, _T_1934)
node _T_1936 = leq(uncommonBits_110, UInt<3>(0h7))
node _T_1937 = and(_T_1935, _T_1936)
node _uncommonBits_T_111 = or(io.in.c.bits.source, UInt<3>(0h0))
node uncommonBits_111 = bits(_uncommonBits_T_111, 2, 0)
node _T_1938 = shr(io.in.c.bits.source, 3)
node _T_1939 = eq(_T_1938, UInt<4>(0h8))
node _T_1940 = leq(UInt<1>(0h0), uncommonBits_111)
node _T_1941 = and(_T_1939, _T_1940)
node _T_1942 = leq(uncommonBits_111, UInt<3>(0h4))
node _T_1943 = and(_T_1941, _T_1942)
node _T_1944 = eq(io.in.c.bits.source, UInt<7>(0h48))
wire _WIRE_6 : UInt<1>[9]
connect _WIRE_6[0], _T_1901
connect _WIRE_6[1], _T_1907
connect _WIRE_6[2], _T_1913
connect _WIRE_6[3], _T_1919
connect _WIRE_6[4], _T_1925
connect _WIRE_6[5], _T_1931
connect _WIRE_6[6], _T_1937
connect _WIRE_6[7], _T_1943
connect _WIRE_6[8], _T_1944
node _T_1945 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_1946 = mux(_WIRE_6[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_1947 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_1948 = mux(_WIRE_6[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_1949 = mux(_WIRE_6[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_1950 = mux(_WIRE_6[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_1951 = mux(_WIRE_6[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_1952 = mux(_WIRE_6[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_1953 = mux(_WIRE_6[7], _T_1945, UInt<1>(0h0))
node _T_1954 = mux(_WIRE_6[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_1955 = or(_T_1946, _T_1947)
node _T_1956 = or(_T_1955, _T_1948)
node _T_1957 = or(_T_1956, _T_1949)
node _T_1958 = or(_T_1957, _T_1950)
node _T_1959 = or(_T_1958, _T_1951)
node _T_1960 = or(_T_1959, _T_1952)
node _T_1961 = or(_T_1960, _T_1953)
node _T_1962 = or(_T_1961, _T_1954)
wire _WIRE_7 : UInt<1>
connect _WIRE_7, _T_1962
node _T_1963 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_1964 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_1965 = and(_T_1963, _T_1964)
node _T_1966 = or(UInt<1>(0h0), _T_1965)
node _T_1967 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_1968 = cvt(_T_1967)
node _T_1969 = and(_T_1968, asSInt(UInt<17>(0h10000)))
node _T_1970 = asSInt(_T_1969)
node _T_1971 = eq(_T_1970, asSInt(UInt<1>(0h0)))
node _T_1972 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_1973 = cvt(_T_1972)
node _T_1974 = and(_T_1973, asSInt(UInt<29>(0h10000000)))
node _T_1975 = asSInt(_T_1974)
node _T_1976 = eq(_T_1975, asSInt(UInt<1>(0h0)))
node _T_1977 = or(_T_1971, _T_1976)
node _T_1978 = and(_T_1966, _T_1977)
node _T_1979 = or(UInt<1>(0h0), _T_1978)
node _T_1980 = and(_WIRE_7, _T_1979)
node _T_1981 = asUInt(reset)
node _T_1982 = eq(_T_1981, UInt<1>(0h0))
when _T_1982 :
node _T_1983 = eq(_T_1980, UInt<1>(0h0))
when _T_1983 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144
assert(clock, _T_1980, UInt<1>(0h1), "") : assert_144
node _T_1984 = asUInt(reset)
node _T_1985 = eq(_T_1984, UInt<1>(0h0))
when _T_1985 :
node _T_1986 = eq(source_ok_2, UInt<1>(0h0))
when _T_1986 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145
node _T_1987 = geq(io.in.c.bits.size, UInt<3>(0h4))
node _T_1988 = asUInt(reset)
node _T_1989 = eq(_T_1988, UInt<1>(0h0))
when _T_1989 :
node _T_1990 = eq(_T_1987, UInt<1>(0h0))
when _T_1990 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146
assert(clock, _T_1987, UInt<1>(0h1), "") : assert_146
node _T_1991 = asUInt(reset)
node _T_1992 = eq(_T_1991, UInt<1>(0h0))
when _T_1992 :
node _T_1993 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1993 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147
node _T_1994 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_1995 = asUInt(reset)
node _T_1996 = eq(_T_1995, UInt<1>(0h0))
when _T_1996 :
node _T_1997 = eq(_T_1994, UInt<1>(0h0))
when _T_1997 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148
assert(clock, _T_1994, UInt<1>(0h1), "") : assert_148
node _T_1998 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_1999 = asUInt(reset)
node _T_2000 = eq(_T_1999, UInt<1>(0h0))
when _T_2000 :
node _T_2001 = eq(_T_1998, UInt<1>(0h0))
when _T_2001 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149
assert(clock, _T_1998, UInt<1>(0h1), "") : assert_149
node _T_2002 = eq(io.in.c.bits.opcode, UInt<3>(0h7))
when _T_2002 :
node _T_2003 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_2004 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_2005 = and(_T_2003, _T_2004)
node _T_2006 = eq(io.in.c.bits.source, UInt<6>(0h20))
node _uncommonBits_T_112 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_112 = bits(_uncommonBits_T_112, 1, 0)
node _T_2007 = shr(io.in.c.bits.source, 2)
node _T_2008 = eq(_T_2007, UInt<1>(0h0))
node _T_2009 = leq(UInt<1>(0h0), uncommonBits_112)
node _T_2010 = and(_T_2008, _T_2009)
node _T_2011 = leq(uncommonBits_112, UInt<2>(0h3))
node _T_2012 = and(_T_2010, _T_2011)
node _uncommonBits_T_113 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_113 = bits(_uncommonBits_T_113, 1, 0)
node _T_2013 = shr(io.in.c.bits.source, 2)
node _T_2014 = eq(_T_2013, UInt<1>(0h1))
node _T_2015 = leq(UInt<1>(0h0), uncommonBits_113)
node _T_2016 = and(_T_2014, _T_2015)
node _T_2017 = leq(uncommonBits_113, UInt<2>(0h3))
node _T_2018 = and(_T_2016, _T_2017)
node _uncommonBits_T_114 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_114 = bits(_uncommonBits_T_114, 1, 0)
node _T_2019 = shr(io.in.c.bits.source, 2)
node _T_2020 = eq(_T_2019, UInt<2>(0h2))
node _T_2021 = leq(UInt<1>(0h0), uncommonBits_114)
node _T_2022 = and(_T_2020, _T_2021)
node _T_2023 = leq(uncommonBits_114, UInt<2>(0h3))
node _T_2024 = and(_T_2022, _T_2023)
node _uncommonBits_T_115 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_115 = bits(_uncommonBits_T_115, 1, 0)
node _T_2025 = shr(io.in.c.bits.source, 2)
node _T_2026 = eq(_T_2025, UInt<2>(0h3))
node _T_2027 = leq(UInt<1>(0h0), uncommonBits_115)
node _T_2028 = and(_T_2026, _T_2027)
node _T_2029 = leq(uncommonBits_115, UInt<2>(0h3))
node _T_2030 = and(_T_2028, _T_2029)
node _uncommonBits_T_116 = or(io.in.c.bits.source, UInt<3>(0h0))
node uncommonBits_116 = bits(_uncommonBits_T_116, 2, 0)
node _T_2031 = shr(io.in.c.bits.source, 3)
node _T_2032 = eq(_T_2031, UInt<2>(0h3))
node _T_2033 = leq(UInt<1>(0h0), uncommonBits_116)
node _T_2034 = and(_T_2032, _T_2033)
node _T_2035 = leq(uncommonBits_116, UInt<3>(0h7))
node _T_2036 = and(_T_2034, _T_2035)
node _uncommonBits_T_117 = or(io.in.c.bits.source, UInt<3>(0h0))
node uncommonBits_117 = bits(_uncommonBits_T_117, 2, 0)
node _T_2037 = shr(io.in.c.bits.source, 3)
node _T_2038 = eq(_T_2037, UInt<2>(0h2))
node _T_2039 = leq(UInt<1>(0h0), uncommonBits_117)
node _T_2040 = and(_T_2038, _T_2039)
node _T_2041 = leq(uncommonBits_117, UInt<3>(0h7))
node _T_2042 = and(_T_2040, _T_2041)
node _uncommonBits_T_118 = or(io.in.c.bits.source, UInt<3>(0h0))
node uncommonBits_118 = bits(_uncommonBits_T_118, 2, 0)
node _T_2043 = shr(io.in.c.bits.source, 3)
node _T_2044 = eq(_T_2043, UInt<4>(0h8))
node _T_2045 = leq(UInt<1>(0h0), uncommonBits_118)
node _T_2046 = and(_T_2044, _T_2045)
node _T_2047 = leq(uncommonBits_118, UInt<3>(0h4))
node _T_2048 = and(_T_2046, _T_2047)
node _T_2049 = eq(io.in.c.bits.source, UInt<7>(0h48))
node _T_2050 = or(_T_2006, _T_2012)
node _T_2051 = or(_T_2050, _T_2018)
node _T_2052 = or(_T_2051, _T_2024)
node _T_2053 = or(_T_2052, _T_2030)
node _T_2054 = or(_T_2053, _T_2036)
node _T_2055 = or(_T_2054, _T_2042)
node _T_2056 = or(_T_2055, _T_2048)
node _T_2057 = or(_T_2056, _T_2049)
node _T_2058 = and(_T_2005, _T_2057)
node _T_2059 = or(UInt<1>(0h0), _T_2058)
node _T_2060 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2061 = or(UInt<1>(0h0), _T_2060)
node _T_2062 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_2063 = cvt(_T_2062)
node _T_2064 = and(_T_2063, asSInt(UInt<17>(0h10000)))
node _T_2065 = asSInt(_T_2064)
node _T_2066 = eq(_T_2065, asSInt(UInt<1>(0h0)))
node _T_2067 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_2068 = cvt(_T_2067)
node _T_2069 = and(_T_2068, asSInt(UInt<29>(0h10000000)))
node _T_2070 = asSInt(_T_2069)
node _T_2071 = eq(_T_2070, asSInt(UInt<1>(0h0)))
node _T_2072 = or(_T_2066, _T_2071)
node _T_2073 = and(_T_2061, _T_2072)
node _T_2074 = or(UInt<1>(0h0), _T_2073)
node _T_2075 = and(_T_2059, _T_2074)
node _T_2076 = asUInt(reset)
node _T_2077 = eq(_T_2076, UInt<1>(0h0))
when _T_2077 :
node _T_2078 = eq(_T_2075, UInt<1>(0h0))
when _T_2078 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150
assert(clock, _T_2075, UInt<1>(0h1), "") : assert_150
node _T_2079 = eq(io.in.c.bits.source, UInt<6>(0h20))
node _uncommonBits_T_119 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_119 = bits(_uncommonBits_T_119, 1, 0)
node _T_2080 = shr(io.in.c.bits.source, 2)
node _T_2081 = eq(_T_2080, UInt<1>(0h0))
node _T_2082 = leq(UInt<1>(0h0), uncommonBits_119)
node _T_2083 = and(_T_2081, _T_2082)
node _T_2084 = leq(uncommonBits_119, UInt<2>(0h3))
node _T_2085 = and(_T_2083, _T_2084)
node _uncommonBits_T_120 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_120 = bits(_uncommonBits_T_120, 1, 0)
node _T_2086 = shr(io.in.c.bits.source, 2)
node _T_2087 = eq(_T_2086, UInt<1>(0h1))
node _T_2088 = leq(UInt<1>(0h0), uncommonBits_120)
node _T_2089 = and(_T_2087, _T_2088)
node _T_2090 = leq(uncommonBits_120, UInt<2>(0h3))
node _T_2091 = and(_T_2089, _T_2090)
node _uncommonBits_T_121 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_121 = bits(_uncommonBits_T_121, 1, 0)
node _T_2092 = shr(io.in.c.bits.source, 2)
node _T_2093 = eq(_T_2092, UInt<2>(0h2))
node _T_2094 = leq(UInt<1>(0h0), uncommonBits_121)
node _T_2095 = and(_T_2093, _T_2094)
node _T_2096 = leq(uncommonBits_121, UInt<2>(0h3))
node _T_2097 = and(_T_2095, _T_2096)
node _uncommonBits_T_122 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_122 = bits(_uncommonBits_T_122, 1, 0)
node _T_2098 = shr(io.in.c.bits.source, 2)
node _T_2099 = eq(_T_2098, UInt<2>(0h3))
node _T_2100 = leq(UInt<1>(0h0), uncommonBits_122)
node _T_2101 = and(_T_2099, _T_2100)
node _T_2102 = leq(uncommonBits_122, UInt<2>(0h3))
node _T_2103 = and(_T_2101, _T_2102)
node _uncommonBits_T_123 = or(io.in.c.bits.source, UInt<3>(0h0))
node uncommonBits_123 = bits(_uncommonBits_T_123, 2, 0)
node _T_2104 = shr(io.in.c.bits.source, 3)
node _T_2105 = eq(_T_2104, UInt<2>(0h3))
node _T_2106 = leq(UInt<1>(0h0), uncommonBits_123)
node _T_2107 = and(_T_2105, _T_2106)
node _T_2108 = leq(uncommonBits_123, UInt<3>(0h7))
node _T_2109 = and(_T_2107, _T_2108)
node _uncommonBits_T_124 = or(io.in.c.bits.source, UInt<3>(0h0))
node uncommonBits_124 = bits(_uncommonBits_T_124, 2, 0)
node _T_2110 = shr(io.in.c.bits.source, 3)
node _T_2111 = eq(_T_2110, UInt<2>(0h2))
node _T_2112 = leq(UInt<1>(0h0), uncommonBits_124)
node _T_2113 = and(_T_2111, _T_2112)
node _T_2114 = leq(uncommonBits_124, UInt<3>(0h7))
node _T_2115 = and(_T_2113, _T_2114)
node _uncommonBits_T_125 = or(io.in.c.bits.source, UInt<3>(0h0))
node uncommonBits_125 = bits(_uncommonBits_T_125, 2, 0)
node _T_2116 = shr(io.in.c.bits.source, 3)
node _T_2117 = eq(_T_2116, UInt<4>(0h8))
node _T_2118 = leq(UInt<1>(0h0), uncommonBits_125)
node _T_2119 = and(_T_2117, _T_2118)
node _T_2120 = leq(uncommonBits_125, UInt<3>(0h4))
node _T_2121 = and(_T_2119, _T_2120)
node _T_2122 = eq(io.in.c.bits.source, UInt<7>(0h48))
wire _WIRE_8 : UInt<1>[9]
connect _WIRE_8[0], _T_2079
connect _WIRE_8[1], _T_2085
connect _WIRE_8[2], _T_2091
connect _WIRE_8[3], _T_2097
connect _WIRE_8[4], _T_2103
connect _WIRE_8[5], _T_2109
connect _WIRE_8[6], _T_2115
connect _WIRE_8[7], _T_2121
connect _WIRE_8[8], _T_2122
node _T_2123 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2124 = mux(_WIRE_8[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_2125 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_2126 = mux(_WIRE_8[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_2127 = mux(_WIRE_8[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_2128 = mux(_WIRE_8[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_2129 = mux(_WIRE_8[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_2130 = mux(_WIRE_8[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_2131 = mux(_WIRE_8[7], _T_2123, UInt<1>(0h0))
node _T_2132 = mux(_WIRE_8[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_2133 = or(_T_2124, _T_2125)
node _T_2134 = or(_T_2133, _T_2126)
node _T_2135 = or(_T_2134, _T_2127)
node _T_2136 = or(_T_2135, _T_2128)
node _T_2137 = or(_T_2136, _T_2129)
node _T_2138 = or(_T_2137, _T_2130)
node _T_2139 = or(_T_2138, _T_2131)
node _T_2140 = or(_T_2139, _T_2132)
wire _WIRE_9 : UInt<1>
connect _WIRE_9, _T_2140
node _T_2141 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_2142 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_2143 = and(_T_2141, _T_2142)
node _T_2144 = or(UInt<1>(0h0), _T_2143)
node _T_2145 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_2146 = cvt(_T_2145)
node _T_2147 = and(_T_2146, asSInt(UInt<17>(0h10000)))
node _T_2148 = asSInt(_T_2147)
node _T_2149 = eq(_T_2148, asSInt(UInt<1>(0h0)))
node _T_2150 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_2151 = cvt(_T_2150)
node _T_2152 = and(_T_2151, asSInt(UInt<29>(0h10000000)))
node _T_2153 = asSInt(_T_2152)
node _T_2154 = eq(_T_2153, asSInt(UInt<1>(0h0)))
node _T_2155 = or(_T_2149, _T_2154)
node _T_2156 = and(_T_2144, _T_2155)
node _T_2157 = or(UInt<1>(0h0), _T_2156)
node _T_2158 = and(_WIRE_9, _T_2157)
node _T_2159 = asUInt(reset)
node _T_2160 = eq(_T_2159, UInt<1>(0h0))
when _T_2160 :
node _T_2161 = eq(_T_2158, UInt<1>(0h0))
when _T_2161 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151
assert(clock, _T_2158, UInt<1>(0h1), "") : assert_151
node _T_2162 = asUInt(reset)
node _T_2163 = eq(_T_2162, UInt<1>(0h0))
when _T_2163 :
node _T_2164 = eq(source_ok_2, UInt<1>(0h0))
when _T_2164 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152
node _T_2165 = geq(io.in.c.bits.size, UInt<3>(0h4))
node _T_2166 = asUInt(reset)
node _T_2167 = eq(_T_2166, UInt<1>(0h0))
when _T_2167 :
node _T_2168 = eq(_T_2165, UInt<1>(0h0))
when _T_2168 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153
assert(clock, _T_2165, UInt<1>(0h1), "") : assert_153
node _T_2169 = asUInt(reset)
node _T_2170 = eq(_T_2169, UInt<1>(0h0))
when _T_2170 :
node _T_2171 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2171 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154
node _T_2172 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_2173 = asUInt(reset)
node _T_2174 = eq(_T_2173, UInt<1>(0h0))
when _T_2174 :
node _T_2175 = eq(_T_2172, UInt<1>(0h0))
when _T_2175 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155
assert(clock, _T_2172, UInt<1>(0h1), "") : assert_155
node _T_2176 = eq(io.in.c.bits.opcode, UInt<1>(0h0))
when _T_2176 :
node _T_2177 = asUInt(reset)
node _T_2178 = eq(_T_2177, UInt<1>(0h0))
when _T_2178 :
node _T_2179 = eq(address_ok_1, UInt<1>(0h0))
when _T_2179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156
node _T_2180 = asUInt(reset)
node _T_2181 = eq(_T_2180, UInt<1>(0h0))
when _T_2181 :
node _T_2182 = eq(source_ok_2, UInt<1>(0h0))
when _T_2182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157
node _T_2183 = asUInt(reset)
node _T_2184 = eq(_T_2183, UInt<1>(0h0))
when _T_2184 :
node _T_2185 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2185 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158
node _T_2186 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_2187 = asUInt(reset)
node _T_2188 = eq(_T_2187, UInt<1>(0h0))
when _T_2188 :
node _T_2189 = eq(_T_2186, UInt<1>(0h0))
when _T_2189 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159
assert(clock, _T_2186, UInt<1>(0h1), "") : assert_159
node _T_2190 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_2191 = asUInt(reset)
node _T_2192 = eq(_T_2191, UInt<1>(0h0))
when _T_2192 :
node _T_2193 = eq(_T_2190, UInt<1>(0h0))
when _T_2193 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160
assert(clock, _T_2190, UInt<1>(0h1), "") : assert_160
node _T_2194 = eq(io.in.c.bits.opcode, UInt<1>(0h1))
when _T_2194 :
node _T_2195 = asUInt(reset)
node _T_2196 = eq(_T_2195, UInt<1>(0h0))
when _T_2196 :
node _T_2197 = eq(address_ok_1, UInt<1>(0h0))
when _T_2197 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161
node _T_2198 = asUInt(reset)
node _T_2199 = eq(_T_2198, UInt<1>(0h0))
when _T_2199 :
node _T_2200 = eq(source_ok_2, UInt<1>(0h0))
when _T_2200 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162
node _T_2201 = asUInt(reset)
node _T_2202 = eq(_T_2201, UInt<1>(0h0))
when _T_2202 :
node _T_2203 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2203 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163
node _T_2204 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_2205 = asUInt(reset)
node _T_2206 = eq(_T_2205, UInt<1>(0h0))
when _T_2206 :
node _T_2207 = eq(_T_2204, UInt<1>(0h0))
when _T_2207 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164
assert(clock, _T_2204, UInt<1>(0h1), "") : assert_164
node _T_2208 = eq(io.in.c.bits.opcode, UInt<2>(0h2))
when _T_2208 :
node _T_2209 = asUInt(reset)
node _T_2210 = eq(_T_2209, UInt<1>(0h0))
when _T_2210 :
node _T_2211 = eq(address_ok_1, UInt<1>(0h0))
when _T_2211 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165
node _T_2212 = asUInt(reset)
node _T_2213 = eq(_T_2212, UInt<1>(0h0))
when _T_2213 :
node _T_2214 = eq(source_ok_2, UInt<1>(0h0))
when _T_2214 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166
node _T_2215 = asUInt(reset)
node _T_2216 = eq(_T_2215, UInt<1>(0h0))
when _T_2216 :
node _T_2217 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2217 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167
node _T_2218 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_2219 = asUInt(reset)
node _T_2220 = eq(_T_2219, UInt<1>(0h0))
when _T_2220 :
node _T_2221 = eq(_T_2218, UInt<1>(0h0))
when _T_2221 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168
assert(clock, _T_2218, UInt<1>(0h1), "") : assert_168
node _T_2222 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_2223 = asUInt(reset)
node _T_2224 = eq(_T_2223, UInt<1>(0h0))
when _T_2224 :
node _T_2225 = eq(_T_2222, UInt<1>(0h0))
when _T_2225 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169
assert(clock, _T_2222, UInt<1>(0h1), "") : assert_169
when io.in.e.valid :
node sink_ok_1 = lt(io.in.e.bits.sink, UInt<4>(0hc))
node _T_2226 = asUInt(reset)
node _T_2227 = eq(_T_2226, UInt<1>(0h0))
when _T_2227 :
node _T_2228 = eq(sink_ok_1, UInt<1>(0h0))
when _T_2228 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170
assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 4)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<2>, clock, reset, UInt<2>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_2229 = eq(a_first, UInt<1>(0h0))
node _T_2230 = and(io.in.a.valid, _T_2229)
when _T_2230 :
node _T_2231 = eq(io.in.a.bits.opcode, opcode)
node _T_2232 = asUInt(reset)
node _T_2233 = eq(_T_2232, UInt<1>(0h0))
when _T_2233 :
node _T_2234 = eq(_T_2231, UInt<1>(0h0))
when _T_2234 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171
assert(clock, _T_2231, UInt<1>(0h1), "") : assert_171
node _T_2235 = eq(io.in.a.bits.param, param)
node _T_2236 = asUInt(reset)
node _T_2237 = eq(_T_2236, UInt<1>(0h0))
when _T_2237 :
node _T_2238 = eq(_T_2235, UInt<1>(0h0))
when _T_2238 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172
assert(clock, _T_2235, UInt<1>(0h1), "") : assert_172
node _T_2239 = eq(io.in.a.bits.size, size)
node _T_2240 = asUInt(reset)
node _T_2241 = eq(_T_2240, UInt<1>(0h0))
when _T_2241 :
node _T_2242 = eq(_T_2239, UInt<1>(0h0))
when _T_2242 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173
assert(clock, _T_2239, UInt<1>(0h1), "") : assert_173
node _T_2243 = eq(io.in.a.bits.source, source)
node _T_2244 = asUInt(reset)
node _T_2245 = eq(_T_2244, UInt<1>(0h0))
when _T_2245 :
node _T_2246 = eq(_T_2243, UInt<1>(0h0))
when _T_2246 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174
assert(clock, _T_2243, UInt<1>(0h1), "") : assert_174
node _T_2247 = eq(io.in.a.bits.address, address)
node _T_2248 = asUInt(reset)
node _T_2249 = eq(_T_2248, UInt<1>(0h0))
when _T_2249 :
node _T_2250 = eq(_T_2247, UInt<1>(0h0))
when _T_2250 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175
assert(clock, _T_2247, UInt<1>(0h1), "") : assert_175
node _T_2251 = and(io.in.a.ready, io.in.a.valid)
node _T_2252 = and(_T_2251, a_first)
when _T_2252 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 4)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<2>, clock, reset, UInt<2>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_2253 = eq(d_first, UInt<1>(0h0))
node _T_2254 = and(io.in.d.valid, _T_2253)
when _T_2254 :
node _T_2255 = eq(io.in.d.bits.opcode, opcode_1)
node _T_2256 = asUInt(reset)
node _T_2257 = eq(_T_2256, UInt<1>(0h0))
when _T_2257 :
node _T_2258 = eq(_T_2255, UInt<1>(0h0))
when _T_2258 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176
assert(clock, _T_2255, UInt<1>(0h1), "") : assert_176
node _T_2259 = eq(io.in.d.bits.param, param_1)
node _T_2260 = asUInt(reset)
node _T_2261 = eq(_T_2260, UInt<1>(0h0))
when _T_2261 :
node _T_2262 = eq(_T_2259, UInt<1>(0h0))
when _T_2262 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177
assert(clock, _T_2259, UInt<1>(0h1), "") : assert_177
node _T_2263 = eq(io.in.d.bits.size, size_1)
node _T_2264 = asUInt(reset)
node _T_2265 = eq(_T_2264, UInt<1>(0h0))
when _T_2265 :
node _T_2266 = eq(_T_2263, UInt<1>(0h0))
when _T_2266 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178
assert(clock, _T_2263, UInt<1>(0h1), "") : assert_178
node _T_2267 = eq(io.in.d.bits.source, source_1)
node _T_2268 = asUInt(reset)
node _T_2269 = eq(_T_2268, UInt<1>(0h0))
when _T_2269 :
node _T_2270 = eq(_T_2267, UInt<1>(0h0))
when _T_2270 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179
assert(clock, _T_2267, UInt<1>(0h1), "") : assert_179
node _T_2271 = eq(io.in.d.bits.sink, sink)
node _T_2272 = asUInt(reset)
node _T_2273 = eq(_T_2272, UInt<1>(0h0))
when _T_2273 :
node _T_2274 = eq(_T_2271, UInt<1>(0h0))
when _T_2274 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180
assert(clock, _T_2271, UInt<1>(0h1), "") : assert_180
node _T_2275 = eq(io.in.d.bits.denied, denied)
node _T_2276 = asUInt(reset)
node _T_2277 = eq(_T_2276, UInt<1>(0h0))
when _T_2277 :
node _T_2278 = eq(_T_2275, UInt<1>(0h0))
when _T_2278 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181
assert(clock, _T_2275, UInt<1>(0h1), "") : assert_181
node _T_2279 = and(io.in.d.ready, io.in.d.valid)
node _T_2280 = and(_T_2279, d_first)
when _T_2280 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
node _b_first_T = and(io.in.b.ready, io.in.b.valid)
node _b_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.b.bits.size)
node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 5, 0)
node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1)
node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 4)
node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2)
node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0))
node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0))
regreset b_first_counter : UInt<2>, clock, reset, UInt<2>(0h0)
node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1))
node b_first_counter1 = tail(_b_first_counter1_T, 1)
node b_first = eq(b_first_counter, UInt<1>(0h0))
node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1))
node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0))
node b_first_last = or(_b_first_last_T, _b_first_last_T_1)
node b_first_done = and(b_first_last, _b_first_T)
node _b_first_count_T = not(b_first_counter1)
node b_first_count = and(b_first_beats1, _b_first_count_T)
when _b_first_T :
node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1)
connect b_first_counter, _b_first_counter_T
reg opcode_2 : UInt, clock
reg param_2 : UInt, clock
reg size_2 : UInt, clock
reg source_2 : UInt, clock
reg address_1 : UInt, clock
node _T_2281 = eq(b_first, UInt<1>(0h0))
node _T_2282 = and(io.in.b.valid, _T_2281)
when _T_2282 :
node _T_2283 = eq(io.in.b.bits.opcode, opcode_2)
node _T_2284 = asUInt(reset)
node _T_2285 = eq(_T_2284, UInt<1>(0h0))
when _T_2285 :
node _T_2286 = eq(_T_2283, UInt<1>(0h0))
when _T_2286 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182
assert(clock, _T_2283, UInt<1>(0h1), "") : assert_182
node _T_2287 = eq(io.in.b.bits.param, param_2)
node _T_2288 = asUInt(reset)
node _T_2289 = eq(_T_2288, UInt<1>(0h0))
when _T_2289 :
node _T_2290 = eq(_T_2287, UInt<1>(0h0))
when _T_2290 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183
assert(clock, _T_2287, UInt<1>(0h1), "") : assert_183
node _T_2291 = eq(io.in.b.bits.size, size_2)
node _T_2292 = asUInt(reset)
node _T_2293 = eq(_T_2292, UInt<1>(0h0))
when _T_2293 :
node _T_2294 = eq(_T_2291, UInt<1>(0h0))
when _T_2294 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184
assert(clock, _T_2291, UInt<1>(0h1), "") : assert_184
node _T_2295 = eq(io.in.b.bits.source, source_2)
node _T_2296 = asUInt(reset)
node _T_2297 = eq(_T_2296, UInt<1>(0h0))
when _T_2297 :
node _T_2298 = eq(_T_2295, UInt<1>(0h0))
when _T_2298 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185
assert(clock, _T_2295, UInt<1>(0h1), "") : assert_185
node _T_2299 = eq(io.in.b.bits.address, address_1)
node _T_2300 = asUInt(reset)
node _T_2301 = eq(_T_2300, UInt<1>(0h0))
when _T_2301 :
node _T_2302 = eq(_T_2299, UInt<1>(0h0))
when _T_2302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186
assert(clock, _T_2299, UInt<1>(0h1), "") : assert_186
node _T_2303 = and(io.in.b.ready, io.in.b.valid)
node _T_2304 = and(_T_2303, b_first)
when _T_2304 :
connect opcode_2, io.in.b.bits.opcode
connect param_2, io.in.b.bits.param
connect size_2, io.in.b.bits.size
connect source_2, io.in.b.bits.source
connect address_1, io.in.b.bits.address
node _c_first_T = and(io.in.c.ready, io.in.c.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.c.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 4)
node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<2>, clock, reset, UInt<2>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
reg opcode_3 : UInt, clock
reg param_3 : UInt, clock
reg size_3 : UInt, clock
reg source_3 : UInt, clock
reg address_2 : UInt, clock
node _T_2305 = eq(c_first, UInt<1>(0h0))
node _T_2306 = and(io.in.c.valid, _T_2305)
when _T_2306 :
node _T_2307 = eq(io.in.c.bits.opcode, opcode_3)
node _T_2308 = asUInt(reset)
node _T_2309 = eq(_T_2308, UInt<1>(0h0))
when _T_2309 :
node _T_2310 = eq(_T_2307, UInt<1>(0h0))
when _T_2310 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187
assert(clock, _T_2307, UInt<1>(0h1), "") : assert_187
node _T_2311 = eq(io.in.c.bits.param, param_3)
node _T_2312 = asUInt(reset)
node _T_2313 = eq(_T_2312, UInt<1>(0h0))
when _T_2313 :
node _T_2314 = eq(_T_2311, UInt<1>(0h0))
when _T_2314 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188
assert(clock, _T_2311, UInt<1>(0h1), "") : assert_188
node _T_2315 = eq(io.in.c.bits.size, size_3)
node _T_2316 = asUInt(reset)
node _T_2317 = eq(_T_2316, UInt<1>(0h0))
when _T_2317 :
node _T_2318 = eq(_T_2315, UInt<1>(0h0))
when _T_2318 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189
assert(clock, _T_2315, UInt<1>(0h1), "") : assert_189
node _T_2319 = eq(io.in.c.bits.source, source_3)
node _T_2320 = asUInt(reset)
node _T_2321 = eq(_T_2320, UInt<1>(0h0))
when _T_2321 :
node _T_2322 = eq(_T_2319, UInt<1>(0h0))
when _T_2322 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190
assert(clock, _T_2319, UInt<1>(0h1), "") : assert_190
node _T_2323 = eq(io.in.c.bits.address, address_2)
node _T_2324 = asUInt(reset)
node _T_2325 = eq(_T_2324, UInt<1>(0h0))
when _T_2325 :
node _T_2326 = eq(_T_2323, UInt<1>(0h0))
when _T_2326 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191
assert(clock, _T_2323, UInt<1>(0h1), "") : assert_191
node _T_2327 = and(io.in.c.ready, io.in.c.valid)
node _T_2328 = and(_T_2327, c_first)
when _T_2328 :
connect opcode_3, io.in.c.bits.opcode
connect param_3, io.in.c.bits.param
connect size_3, io.in.c.bits.size
connect source_3, io.in.c.bits.source
connect address_2, io.in.c.bits.address
regreset inflight : UInt<73>, clock, reset, UInt<73>(0h0)
regreset inflight_opcodes : UInt<292>, clock, reset, UInt<292>(0h0)
regreset inflight_sizes : UInt<292>, clock, reset, UInt<292>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 4)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<2>, clock, reset, UInt<2>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 4)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<2>, clock, reset, UInt<2>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<73>
connect a_set, UInt<73>(0h0)
wire a_set_wo_ready : UInt<73>
connect a_set_wo_ready, UInt<73>(0h0)
wire a_opcodes_set : UInt<292>
connect a_opcodes_set, UInt<292>(0h0)
wire a_sizes_set : UInt<292>
connect a_sizes_set, UInt<292>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_2329 = and(io.in.a.valid, a_first_1)
node _T_2330 = and(_T_2329, UInt<1>(0h1))
when _T_2330 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_2331 = and(io.in.a.ready, io.in.a.valid)
node _T_2332 = and(_T_2331, a_first_1)
node _T_2333 = and(_T_2332, UInt<1>(0h1))
when _T_2333 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_2334 = dshr(inflight, io.in.a.bits.source)
node _T_2335 = bits(_T_2334, 0, 0)
node _T_2336 = eq(_T_2335, UInt<1>(0h0))
node _T_2337 = asUInt(reset)
node _T_2338 = eq(_T_2337, UInt<1>(0h0))
when _T_2338 :
node _T_2339 = eq(_T_2336, UInt<1>(0h0))
when _T_2339 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192
assert(clock, _T_2336, UInt<1>(0h1), "") : assert_192
wire d_clr : UInt<73>
connect d_clr, UInt<73>(0h0)
wire d_clr_wo_ready : UInt<73>
connect d_clr_wo_ready, UInt<73>(0h0)
wire d_opcodes_clr : UInt<292>
connect d_opcodes_clr, UInt<292>(0h0)
wire d_sizes_clr : UInt<292>
connect d_sizes_clr, UInt<292>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_2340 = and(io.in.d.valid, d_first_1)
node _T_2341 = and(_T_2340, UInt<1>(0h1))
node _T_2342 = eq(d_release_ack, UInt<1>(0h0))
node _T_2343 = and(_T_2341, _T_2342)
when _T_2343 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_2344 = and(io.in.d.ready, io.in.d.valid)
node _T_2345 = and(_T_2344, d_first_1)
node _T_2346 = and(_T_2345, UInt<1>(0h1))
node _T_2347 = eq(d_release_ack, UInt<1>(0h0))
node _T_2348 = and(_T_2346, _T_2347)
when _T_2348 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_2349 = and(io.in.d.valid, d_first_1)
node _T_2350 = and(_T_2349, UInt<1>(0h1))
node _T_2351 = eq(d_release_ack, UInt<1>(0h0))
node _T_2352 = and(_T_2350, _T_2351)
when _T_2352 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_2353 = dshr(inflight, io.in.d.bits.source)
node _T_2354 = bits(_T_2353, 0, 0)
node _T_2355 = or(_T_2354, same_cycle_resp)
node _T_2356 = asUInt(reset)
node _T_2357 = eq(_T_2356, UInt<1>(0h0))
when _T_2357 :
node _T_2358 = eq(_T_2355, UInt<1>(0h0))
when _T_2358 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193
assert(clock, _T_2355, UInt<1>(0h1), "") : assert_193
when same_cycle_resp :
node _T_2359 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_2360 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_2361 = or(_T_2359, _T_2360)
node _T_2362 = asUInt(reset)
node _T_2363 = eq(_T_2362, UInt<1>(0h0))
when _T_2363 :
node _T_2364 = eq(_T_2361, UInt<1>(0h0))
when _T_2364 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194
assert(clock, _T_2361, UInt<1>(0h1), "") : assert_194
node _T_2365 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_2366 = asUInt(reset)
node _T_2367 = eq(_T_2366, UInt<1>(0h0))
when _T_2367 :
node _T_2368 = eq(_T_2365, UInt<1>(0h0))
when _T_2368 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195
assert(clock, _T_2365, UInt<1>(0h1), "") : assert_195
else :
node _T_2369 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_2370 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_2371 = or(_T_2369, _T_2370)
node _T_2372 = asUInt(reset)
node _T_2373 = eq(_T_2372, UInt<1>(0h0))
when _T_2373 :
node _T_2374 = eq(_T_2371, UInt<1>(0h0))
when _T_2374 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196
assert(clock, _T_2371, UInt<1>(0h1), "") : assert_196
node _T_2375 = eq(io.in.d.bits.size, a_size_lookup)
node _T_2376 = asUInt(reset)
node _T_2377 = eq(_T_2376, UInt<1>(0h0))
when _T_2377 :
node _T_2378 = eq(_T_2375, UInt<1>(0h0))
when _T_2378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197
assert(clock, _T_2375, UInt<1>(0h1), "") : assert_197
node _T_2379 = and(io.in.d.valid, d_first_1)
node _T_2380 = and(_T_2379, a_first_1)
node _T_2381 = and(_T_2380, io.in.a.valid)
node _T_2382 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_2383 = and(_T_2381, _T_2382)
node _T_2384 = eq(d_release_ack, UInt<1>(0h0))
node _T_2385 = and(_T_2383, _T_2384)
when _T_2385 :
node _T_2386 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_2387 = or(_T_2386, io.in.a.ready)
node _T_2388 = asUInt(reset)
node _T_2389 = eq(_T_2388, UInt<1>(0h0))
when _T_2389 :
node _T_2390 = eq(_T_2387, UInt<1>(0h0))
when _T_2390 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198
assert(clock, _T_2387, UInt<1>(0h1), "") : assert_198
node _T_2391 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_2392 = orr(a_set_wo_ready)
node _T_2393 = eq(_T_2392, UInt<1>(0h0))
node _T_2394 = or(_T_2391, _T_2393)
node _T_2395 = asUInt(reset)
node _T_2396 = eq(_T_2395, UInt<1>(0h0))
when _T_2396 :
node _T_2397 = eq(_T_2394, UInt<1>(0h0))
when _T_2397 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199
assert(clock, _T_2394, UInt<1>(0h1), "") : assert_199
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_78
node _T_2398 = orr(inflight)
node _T_2399 = eq(_T_2398, UInt<1>(0h0))
node _T_2400 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_2401 = or(_T_2399, _T_2400)
node _T_2402 = lt(watchdog, plusarg_reader.out)
node _T_2403 = or(_T_2401, _T_2402)
node _T_2404 = asUInt(reset)
node _T_2405 = eq(_T_2404, UInt<1>(0h0))
when _T_2405 :
node _T_2406 = eq(_T_2403, UInt<1>(0h0))
when _T_2406 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200
assert(clock, _T_2403, UInt<1>(0h1), "") : assert_200
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_2407 = and(io.in.a.ready, io.in.a.valid)
node _T_2408 = and(io.in.d.ready, io.in.d.valid)
node _T_2409 = or(_T_2407, _T_2408)
when _T_2409 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<73>, clock, reset, UInt<73>(0h0)
regreset inflight_opcodes_1 : UInt<292>, clock, reset, UInt<292>(0h0)
regreset inflight_sizes_1 : UInt<292>, clock, reset, UInt<292>(0h0)
node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid)
node _c_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.c.bits.size)
node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 5, 0)
node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4)
node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 4)
node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0)
node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0))
regreset c_first_counter_1 : UInt<2>, clock, reset, UInt<2>(0h0)
node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1))
node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1)
node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0))
node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1))
node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0))
node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3)
node c_first_done_1 = and(c_first_last_1, _c_first_T_1)
node _c_first_count_T_1 = not(c_first_counter1_1)
node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1)
when _c_first_T_1 :
node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1)
connect c_first_counter_1, _c_first_counter_T_1
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 4)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<2>, clock, reset, UInt<2>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<73>
connect c_set, UInt<73>(0h0)
wire c_set_wo_ready : UInt<73>
connect c_set_wo_ready, UInt<73>(0h0)
wire c_opcodes_set : UInt<292>
connect c_opcodes_set, UInt<292>(0h0)
wire c_sizes_set : UInt<292>
connect c_sizes_set, UInt<292>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
node _T_2410 = and(io.in.c.valid, c_first_1)
node _T_2411 = bits(io.in.c.bits.opcode, 2, 2)
node _T_2412 = bits(io.in.c.bits.opcode, 1, 1)
node _T_2413 = and(_T_2411, _T_2412)
node _T_2414 = and(_T_2410, _T_2413)
when _T_2414 :
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
node _T_2415 = and(io.in.c.ready, io.in.c.valid)
node _T_2416 = and(_T_2415, c_first_1)
node _T_2417 = bits(io.in.c.bits.opcode, 2, 2)
node _T_2418 = bits(io.in.c.bits.opcode, 1, 1)
node _T_2419 = and(_T_2417, _T_2418)
node _T_2420 = and(_T_2416, _T_2419)
when _T_2420 :
node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source)
connect c_set, _c_set_T
node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
node _T_2421 = dshr(inflight_1, io.in.c.bits.source)
node _T_2422 = bits(_T_2421, 0, 0)
node _T_2423 = eq(_T_2422, UInt<1>(0h0))
node _T_2424 = asUInt(reset)
node _T_2425 = eq(_T_2424, UInt<1>(0h0))
when _T_2425 :
node _T_2426 = eq(_T_2423, UInt<1>(0h0))
when _T_2426 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201
assert(clock, _T_2423, UInt<1>(0h1), "") : assert_201
node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4))
node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<73>
connect d_clr_1, UInt<73>(0h0)
wire d_clr_wo_ready_1 : UInt<73>
connect d_clr_wo_ready_1, UInt<73>(0h0)
wire d_opcodes_clr_1 : UInt<292>
connect d_opcodes_clr_1, UInt<292>(0h0)
wire d_sizes_clr_1 : UInt<292>
connect d_sizes_clr_1, UInt<292>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_2427 = and(io.in.d.valid, d_first_2)
node _T_2428 = and(_T_2427, UInt<1>(0h1))
node _T_2429 = and(_T_2428, d_release_ack_1)
when _T_2429 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_2430 = and(io.in.d.ready, io.in.d.valid)
node _T_2431 = and(_T_2430, d_first_2)
node _T_2432 = and(_T_2431, UInt<1>(0h1))
node _T_2433 = and(_T_2432, d_release_ack_1)
when _T_2433 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_2434 = and(io.in.d.valid, d_first_2)
node _T_2435 = and(_T_2434, UInt<1>(0h1))
node _T_2436 = and(_T_2435, d_release_ack_1)
when _T_2436 :
node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1)
node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_2437 = dshr(inflight_1, io.in.d.bits.source)
node _T_2438 = bits(_T_2437, 0, 0)
node _T_2439 = or(_T_2438, same_cycle_resp_1)
node _T_2440 = asUInt(reset)
node _T_2441 = eq(_T_2440, UInt<1>(0h0))
when _T_2441 :
node _T_2442 = eq(_T_2439, UInt<1>(0h0))
when _T_2442 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202
assert(clock, _T_2439, UInt<1>(0h1), "") : assert_202
when same_cycle_resp_1 :
node _T_2443 = eq(io.in.d.bits.size, io.in.c.bits.size)
node _T_2444 = asUInt(reset)
node _T_2445 = eq(_T_2444, UInt<1>(0h0))
when _T_2445 :
node _T_2446 = eq(_T_2443, UInt<1>(0h0))
when _T_2446 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203
assert(clock, _T_2443, UInt<1>(0h1), "") : assert_203
else :
node _T_2447 = eq(io.in.d.bits.size, c_size_lookup)
node _T_2448 = asUInt(reset)
node _T_2449 = eq(_T_2448, UInt<1>(0h0))
when _T_2449 :
node _T_2450 = eq(_T_2447, UInt<1>(0h0))
when _T_2450 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204
assert(clock, _T_2447, UInt<1>(0h1), "") : assert_204
node _T_2451 = and(io.in.d.valid, d_first_2)
node _T_2452 = and(_T_2451, c_first_1)
node _T_2453 = and(_T_2452, io.in.c.valid)
node _T_2454 = eq(io.in.c.bits.source, io.in.d.bits.source)
node _T_2455 = and(_T_2453, _T_2454)
node _T_2456 = and(_T_2455, d_release_ack_1)
node _T_2457 = eq(c_probe_ack, UInt<1>(0h0))
node _T_2458 = and(_T_2456, _T_2457)
when _T_2458 :
node _T_2459 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_2460 = or(_T_2459, io.in.c.ready)
node _T_2461 = asUInt(reset)
node _T_2462 = eq(_T_2461, UInt<1>(0h0))
when _T_2462 :
node _T_2463 = eq(_T_2460, UInt<1>(0h0))
when _T_2463 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205
assert(clock, _T_2460, UInt<1>(0h1), "") : assert_205
node _T_2464 = orr(c_set_wo_ready)
when _T_2464 :
node _T_2465 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_2466 = asUInt(reset)
node _T_2467 = eq(_T_2466, UInt<1>(0h0))
when _T_2467 :
node _T_2468 = eq(_T_2465, UInt<1>(0h0))
when _T_2468 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206
assert(clock, _T_2465, UInt<1>(0h1), "") : assert_206
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_79
node _T_2469 = orr(inflight_1)
node _T_2470 = eq(_T_2469, UInt<1>(0h0))
node _T_2471 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_2472 = or(_T_2470, _T_2471)
node _T_2473 = lt(watchdog_1, plusarg_reader_1.out)
node _T_2474 = or(_T_2472, _T_2473)
node _T_2475 = asUInt(reset)
node _T_2476 = eq(_T_2475, UInt<1>(0h0))
when _T_2476 :
node _T_2477 = eq(_T_2474, UInt<1>(0h0))
when _T_2477 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207
assert(clock, _T_2474, UInt<1>(0h1), "") : assert_207
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
node _T_2478 = and(io.in.c.ready, io.in.c.valid)
node _T_2479 = and(io.in.d.ready, io.in.d.valid)
node _T_2480 = or(_T_2478, _T_2479)
when _T_2480 :
connect watchdog_1, UInt<1>(0h0)
regreset inflight_2 : UInt<12>, clock, reset, UInt<12>(0h0)
node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_9 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 5, 0)
node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10)
node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 4)
node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0))
regreset d_first_counter_3 : UInt<2>, clock, reset, UInt<2>(0h0)
node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1))
node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1)
node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0))
node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1))
node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0))
node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7)
node d_first_done_3 = and(d_first_last_3, _d_first_T_3)
node _d_first_count_T_3 = not(d_first_counter1_3)
node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3)
when _d_first_T_3 :
node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3)
connect d_first_counter_3, _d_first_counter_T_3
wire d_set : UInt<12>
connect d_set, UInt<12>(0h0)
node _T_2481 = and(io.in.d.ready, io.in.d.valid)
node _T_2482 = and(_T_2481, d_first_3)
node _T_2483 = bits(io.in.d.bits.opcode, 2, 2)
node _T_2484 = bits(io.in.d.bits.opcode, 1, 1)
node _T_2485 = eq(_T_2484, UInt<1>(0h0))
node _T_2486 = and(_T_2483, _T_2485)
node _T_2487 = and(_T_2482, _T_2486)
when _T_2487 :
node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink)
connect d_set, _d_set_T
node _T_2488 = dshr(inflight_2, io.in.d.bits.sink)
node _T_2489 = bits(_T_2488, 0, 0)
node _T_2490 = eq(_T_2489, UInt<1>(0h0))
node _T_2491 = asUInt(reset)
node _T_2492 = eq(_T_2491, UInt<1>(0h0))
when _T_2492 :
node _T_2493 = eq(_T_2490, UInt<1>(0h0))
when _T_2493 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208
assert(clock, _T_2490, UInt<1>(0h1), "") : assert_208
wire e_clr : UInt<12>
connect e_clr, UInt<12>(0h0)
node _T_2494 = and(io.in.e.ready, io.in.e.valid)
node _T_2495 = and(_T_2494, UInt<1>(0h1))
node _T_2496 = and(_T_2495, UInt<1>(0h1))
when _T_2496 :
node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink)
connect e_clr, _e_clr_T
node _T_2497 = or(d_set, inflight_2)
node _T_2498 = dshr(_T_2497, io.in.e.bits.sink)
node _T_2499 = bits(_T_2498, 0, 0)
node _T_2500 = asUInt(reset)
node _T_2501 = eq(_T_2500, UInt<1>(0h0))
when _T_2501 :
node _T_2502 = eq(_T_2499, UInt<1>(0h0))
when _T_2502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209
assert(clock, _T_2499, UInt<1>(0h1), "") : assert_209
node _inflight_T_6 = or(inflight_2, d_set)
node _inflight_T_7 = not(e_clr)
node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7)
connect inflight_2, _inflight_T_8 | module TLMonitor_39( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [127:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_b_ready, // @[Monitor.scala:20:14]
input io_in_b_valid, // @[Monitor.scala:20:14]
input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14]
input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14]
input io_in_c_ready, // @[Monitor.scala:20:14]
input io_in_c_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_c_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14]
input [127:0] io_in_c_bits_data, // @[Monitor.scala:20:14]
input io_in_c_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [127:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_e_valid, // @[Monitor.scala:20:14]
input [3:0] io_in_e_bits_sink // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [15:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [127:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7]
wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7]
wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7]
wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7]
wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7]
wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7]
wire [127:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7]
wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [127:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7]
wire [3:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7]
wire io_in_e_ready = 1'h1; // @[Monitor.scala:36:7]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_54 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_56 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_60 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_62 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_66 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_68 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_72 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_74 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_78 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_80 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_84 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_86 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_90 = 1'h1; // @[Parameters.scala:56:32]
wire mask_sub_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:206:21]
wire mask_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_sub_size_1 = 1'h1; // @[Misc.scala:209:26]
wire mask_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_4_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_5_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_6_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_7_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_size_1 = 1'h1; // @[Misc.scala:209:26]
wire mask_acc_16 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_17 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_18 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_19 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_20 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_21 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_22 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_23 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_24 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_25 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_26 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_27 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_28 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_29 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_30 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_31 = 1'h1; // @[Misc.scala:215:29]
wire _legal_source_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _legal_source_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _legal_source_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _legal_source_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _legal_source_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _legal_source_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _legal_source_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _legal_source_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _legal_source_T_27 = 1'h1; // @[Parameters.scala:56:32]
wire _legal_source_T_29 = 1'h1; // @[Parameters.scala:57:20]
wire _legal_source_T_33 = 1'h1; // @[Parameters.scala:56:32]
wire _legal_source_T_35 = 1'h1; // @[Parameters.scala:57:20]
wire _legal_source_T_38 = 1'h1; // @[Parameters.scala:54:32]
wire _legal_source_T_39 = 1'h1; // @[Parameters.scala:56:32]
wire _legal_source_T_40 = 1'h1; // @[Parameters.scala:54:67]
wire _legal_source_T_41 = 1'h1; // @[Parameters.scala:57:20]
wire _legal_source_T_42 = 1'h1; // @[Parameters.scala:56:48]
wire _legal_source_WIRE_7 = 1'h1; // @[Parameters.scala:1138:31]
wire legal_source = 1'h1; // @[Monitor.scala:168:113]
wire _source_ok_T_105 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_107 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_111 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_113 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_117 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_119 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_123 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_125 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_129 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_131 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_135 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_137 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_141 = 1'h1; // @[Parameters.scala:56:32]
wire _b_first_beats1_opdata_T = 1'h1; // @[Edges.scala:97:37]
wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire b_first_last = 1'h1; // @[Edges.scala:232:33]
wire [6:0] io_in_b_bits_source = 7'h40; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_77 = 7'h40; // @[Parameters.scala:52:29]
wire [6:0] _uncommonBits_T_78 = 7'h40; // @[Parameters.scala:52:29]
wire [6:0] _uncommonBits_T_79 = 7'h40; // @[Parameters.scala:52:29]
wire [6:0] _uncommonBits_T_80 = 7'h40; // @[Parameters.scala:52:29]
wire [6:0] _uncommonBits_T_81 = 7'h40; // @[Parameters.scala:52:29]
wire [6:0] _uncommonBits_T_82 = 7'h40; // @[Parameters.scala:52:29]
wire [6:0] _uncommonBits_T_83 = 7'h40; // @[Parameters.scala:52:29]
wire [6:0] _legal_source_uncommonBits_T = 7'h40; // @[Parameters.scala:52:29]
wire [6:0] _legal_source_uncommonBits_T_1 = 7'h40; // @[Parameters.scala:52:29]
wire [6:0] _legal_source_uncommonBits_T_2 = 7'h40; // @[Parameters.scala:52:29]
wire [6:0] _legal_source_uncommonBits_T_3 = 7'h40; // @[Parameters.scala:52:29]
wire [6:0] _legal_source_uncommonBits_T_4 = 7'h40; // @[Parameters.scala:52:29]
wire [6:0] _legal_source_uncommonBits_T_5 = 7'h40; // @[Parameters.scala:52:29]
wire [6:0] _legal_source_uncommonBits_T_6 = 7'h40; // @[Parameters.scala:52:29]
wire [6:0] _legal_source_T_51 = 7'h40; // @[Mux.scala:30:73]
wire [6:0] _legal_source_T_59 = 7'h40; // @[Mux.scala:30:73]
wire [6:0] _legal_source_T_60 = 7'h40; // @[Mux.scala:30:73]
wire [6:0] _legal_source_WIRE_1 = 7'h40; // @[Mux.scala:30:73]
wire [6:0] _uncommonBits_T_84 = 7'h40; // @[Parameters.scala:52:29]
wire [6:0] _uncommonBits_T_85 = 7'h40; // @[Parameters.scala:52:29]
wire [6:0] _uncommonBits_T_86 = 7'h40; // @[Parameters.scala:52:29]
wire [6:0] _uncommonBits_T_87 = 7'h40; // @[Parameters.scala:52:29]
wire [6:0] _uncommonBits_T_88 = 7'h40; // @[Parameters.scala:52:29]
wire [6:0] _uncommonBits_T_89 = 7'h40; // @[Parameters.scala:52:29]
wire [6:0] _uncommonBits_T_90 = 7'h40; // @[Parameters.scala:52:29]
wire [2:0] io_in_b_bits_opcode = 3'h6; // @[Monitor.scala:36:7]
wire [2:0] io_in_b_bits_size = 3'h6; // @[Monitor.scala:36:7]
wire [15:0] io_in_b_bits_mask = 16'hFFFF; // @[Monitor.scala:36:7]
wire [15:0] mask_1 = 16'hFFFF; // @[Misc.scala:222:10]
wire [127:0] io_in_b_bits_data = 128'h0; // @[Monitor.scala:36:7]
wire io_in_b_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire mask_sub_sub_sub_size_1 = 1'h0; // @[Misc.scala:209:26]
wire _mask_sub_sub_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_sub_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38]
wire mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26]
wire _mask_sub_acc_T_8 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_9 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_10 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_11 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_12 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_13 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_14 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_15 = 1'h0; // @[Misc.scala:215:38]
wire _legal_source_T = 1'h0; // @[Parameters.scala:46:9]
wire _legal_source_T_2 = 1'h0; // @[Parameters.scala:54:32]
wire _legal_source_T_4 = 1'h0; // @[Parameters.scala:54:67]
wire _legal_source_T_6 = 1'h0; // @[Parameters.scala:56:48]
wire _legal_source_T_8 = 1'h0; // @[Parameters.scala:54:32]
wire _legal_source_T_10 = 1'h0; // @[Parameters.scala:54:67]
wire _legal_source_T_12 = 1'h0; // @[Parameters.scala:56:48]
wire _legal_source_T_14 = 1'h0; // @[Parameters.scala:54:32]
wire _legal_source_T_16 = 1'h0; // @[Parameters.scala:54:67]
wire _legal_source_T_18 = 1'h0; // @[Parameters.scala:56:48]
wire _legal_source_T_20 = 1'h0; // @[Parameters.scala:54:32]
wire _legal_source_T_22 = 1'h0; // @[Parameters.scala:54:67]
wire _legal_source_T_24 = 1'h0; // @[Parameters.scala:56:48]
wire _legal_source_T_26 = 1'h0; // @[Parameters.scala:54:32]
wire _legal_source_T_28 = 1'h0; // @[Parameters.scala:54:67]
wire _legal_source_T_30 = 1'h0; // @[Parameters.scala:56:48]
wire _legal_source_T_32 = 1'h0; // @[Parameters.scala:54:32]
wire _legal_source_T_34 = 1'h0; // @[Parameters.scala:54:67]
wire _legal_source_T_36 = 1'h0; // @[Parameters.scala:56:48]
wire _legal_source_T_43 = 1'h0; // @[Parameters.scala:46:9]
wire _legal_source_WIRE_0 = 1'h0; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_1_0 = 1'h0; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_2 = 1'h0; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_3 = 1'h0; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_4 = 1'h0; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_5 = 1'h0; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_6 = 1'h0; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_8 = 1'h0; // @[Parameters.scala:1138:31]
wire _legal_source_T_45 = 1'h0; // @[Mux.scala:30:73]
wire b_first_beats1_opdata = 1'h0; // @[Edges.scala:97:28]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [3:0] _mask_sizeOH_T_4 = 4'h4; // @[OneHot.scala:65:12]
wire [3:0] _mask_sizeOH_T_5 = 4'h4; // @[OneHot.scala:65:27]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] uncommonBits_81 = 3'h0; // @[Parameters.scala:52:56]
wire [2:0] uncommonBits_82 = 3'h0; // @[Parameters.scala:52:56]
wire [2:0] uncommonBits_83 = 3'h0; // @[Parameters.scala:52:56]
wire [2:0] legal_source_uncommonBits_4 = 3'h0; // @[Parameters.scala:52:56]
wire [2:0] legal_source_uncommonBits_5 = 3'h0; // @[Parameters.scala:52:56]
wire [2:0] legal_source_uncommonBits_6 = 3'h0; // @[Parameters.scala:52:56]
wire [2:0] _legal_source_T_46 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] uncommonBits_88 = 3'h0; // @[Parameters.scala:52:56]
wire [2:0] uncommonBits_89 = 3'h0; // @[Parameters.scala:52:56]
wire [2:0] uncommonBits_90 = 3'h0; // @[Parameters.scala:52:56]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [1:0] uncommonBits_77 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] uncommonBits_78 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] uncommonBits_79 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] uncommonBits_80 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] legal_source_uncommonBits = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] legal_source_uncommonBits_1 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] legal_source_uncommonBits_2 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] legal_source_uncommonBits_3 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] uncommonBits_84 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] uncommonBits_85 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] uncommonBits_86 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] uncommonBits_87 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] b_first_beats1 = 2'h0; // @[Edges.scala:221:14]
wire [1:0] b_first_count = 2'h0; // @[Edges.scala:234:25]
wire [1:0] mask_lo_lo_lo_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_lo_lo_hi_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_lo_hi_lo_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_lo_hi_hi_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo_lo_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo_hi_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi_hi_lo_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi_hi_hi_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] b_first_beats1_decode = 2'h3; // @[Edges.scala:220:59]
wire [5:0] is_aligned_mask_1 = 6'h3F; // @[package.scala:243:46]
wire [5:0] _b_first_beats1_decode_T_2 = 6'h3F; // @[package.scala:243:46]
wire [5:0] _is_aligned_mask_T_3 = 6'h0; // @[package.scala:243:76]
wire [5:0] _legal_source_T_44 = 6'h0; // @[Mux.scala:30:73]
wire [5:0] _legal_source_T_53 = 6'h0; // @[Mux.scala:30:73]
wire [5:0] _legal_source_T_54 = 6'h0; // @[Mux.scala:30:73]
wire [5:0] _legal_source_T_55 = 6'h0; // @[Mux.scala:30:73]
wire [5:0] _legal_source_T_56 = 6'h0; // @[Mux.scala:30:73]
wire [5:0] _legal_source_T_57 = 6'h0; // @[Mux.scala:30:73]
wire [5:0] _legal_source_T_58 = 6'h0; // @[Mux.scala:30:73]
wire [5:0] _b_first_beats1_decode_T_1 = 6'h0; // @[package.scala:243:76]
wire [12:0] _is_aligned_mask_T_2 = 13'hFC0; // @[package.scala:243:71]
wire [12:0] _b_first_beats1_decode_T = 13'hFC0; // @[package.scala:243:71]
wire [6:0] _legal_source_T_52 = 7'h0; // @[Mux.scala:30:73]
wire [4:0] _legal_source_T_49 = 5'h0; // @[Mux.scala:30:73]
wire [4:0] _legal_source_T_50 = 5'h0; // @[Mux.scala:30:73]
wire [3:0] _legal_source_T_47 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _legal_source_T_48 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _legal_source_T_25 = 4'h8; // @[Parameters.scala:54:10]
wire [3:0] _legal_source_T_31 = 4'h8; // @[Parameters.scala:54:10]
wire [3:0] _legal_source_T_37 = 4'h8; // @[Parameters.scala:54:10]
wire [4:0] _legal_source_T_1 = 5'h10; // @[Parameters.scala:54:10]
wire [4:0] _legal_source_T_7 = 5'h10; // @[Parameters.scala:54:10]
wire [4:0] _legal_source_T_13 = 5'h10; // @[Parameters.scala:54:10]
wire [4:0] _legal_source_T_19 = 5'h10; // @[Parameters.scala:54:10]
wire [7:0] mask_lo_1 = 8'hFF; // @[Misc.scala:222:10]
wire [7:0] mask_hi_1 = 8'hFF; // @[Misc.scala:222:10]
wire [3:0] mask_lo_lo_1 = 4'hF; // @[Misc.scala:222:10]
wire [3:0] mask_lo_hi_1 = 4'hF; // @[Misc.scala:222:10]
wire [3:0] mask_hi_lo_1 = 4'hF; // @[Misc.scala:222:10]
wire [3:0] mask_hi_hi_1 = 4'hF; // @[Misc.scala:222:10]
wire [3:0] mask_sizeOH_1 = 4'h5; // @[Misc.scala:202:81]
wire [1:0] mask_sizeOH_shiftAmount_1 = 2'h2; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_3 = 4'h6; // @[Misc.scala:202:34]
wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_66 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_67 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_68 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_69 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_70 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_71 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_72 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_73 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_74 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_75 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_76 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_14 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_15 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_16 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_17 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_18 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_19 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_20 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_91 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_92 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_93 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_94 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_95 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_96 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_97 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_98 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_99 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_100 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_101 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_102 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_103 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_104 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_105 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_106 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_107 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_108 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_109 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_110 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_111 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_112 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_113 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_114 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_115 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_116 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_117 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_118 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_119 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_120 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_121 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_122 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_123 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_124 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_125 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_12 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_13 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_25 = io_in_a_bits_source_0[6:3]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_31 = io_in_a_bits_source_0[6:3]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_37 = io_in_a_bits_source_0[6:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_26 = _source_ok_T_25 == 4'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_32 = _source_ok_T_31 == 4'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_38 = _source_ok_T_37 == 4'h8; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_41 = source_ok_uncommonBits_6 < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_42 = _source_ok_T_40 & _source_ok_T_41; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_7 = _source_ok_T_42; // @[Parameters.scala:1138:31]
wire _source_ok_T_43 = io_in_a_bits_source_0 == 7'h48; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_43; // @[Parameters.scala:1138:31]
wire _source_ok_T_44 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_45 = _source_ok_T_44 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_46 = _source_ok_T_45 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_48 = _source_ok_T_47 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_50 = _source_ok_T_49 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_50 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [3:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [3:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}]
wire [3:0] mask_sizeOH = {_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_sub_0_1 = io_in_a_bits_size_0[2]; // @[Misc.scala:206:21]
wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26]
wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_4_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_5_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_6_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_7_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_8 = mask_sub_4_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}]
wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_9 = mask_sub_4_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}]
wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_10 = mask_sub_5_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}]
wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_11 = mask_sub_5_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}]
wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_12 = mask_sub_6_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}]
wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_13 = mask_sub_6_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}]
wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_14 = mask_sub_7_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}]
wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_15 = mask_sub_7_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [15:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_5 = _uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_6 = _uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_11 = _uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_12 = _uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_13 = _uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_18 = _uncommonBits_T_18[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_19 = _uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_20 = _uncommonBits_T_20[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_25 = _uncommonBits_T_25[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_26 = _uncommonBits_T_26[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_27 = _uncommonBits_T_27[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_32 = _uncommonBits_T_32[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_33 = _uncommonBits_T_33[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_39 = _uncommonBits_T_39[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_40 = _uncommonBits_T_40[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_41 = _uncommonBits_T_41[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_46 = _uncommonBits_T_46[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_47 = _uncommonBits_T_47[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_48 = _uncommonBits_T_48[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_53 = _uncommonBits_T_53[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_54 = _uncommonBits_T_54[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_55 = _uncommonBits_T_55[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_58 = _uncommonBits_T_58[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_59 = _uncommonBits_T_59[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_60 = _uncommonBits_T_60[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_61 = _uncommonBits_T_61[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_62 = _uncommonBits_T_62[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_64 = _uncommonBits_T_64[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_65 = _uncommonBits_T_65[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_66 = _uncommonBits_T_66[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_67 = _uncommonBits_T_67[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_68 = _uncommonBits_T_68[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_69 = _uncommonBits_T_69[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_70 = _uncommonBits_T_70[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_71 = _uncommonBits_T_71[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_72 = _uncommonBits_T_72[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_73 = _uncommonBits_T_73[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_74 = _uncommonBits_T_74[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_75 = _uncommonBits_T_75[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_76 = _uncommonBits_T_76[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_51 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_51; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_52 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_58 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_64 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_70 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_53 = _source_ok_T_52 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_55 = _source_ok_T_53; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_57 = _source_ok_T_55; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_57; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_59 = _source_ok_T_58 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_61 = _source_ok_T_59; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_63 = _source_ok_T_61; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_63; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_65 = _source_ok_T_64 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_67 = _source_ok_T_65; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_69 = _source_ok_T_67; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_69; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_71 = _source_ok_T_70 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_73 = _source_ok_T_71; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_75 = _source_ok_T_73; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_75; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_76 = io_in_d_bits_source_0[6:3]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_82 = io_in_d_bits_source_0[6:3]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_88 = io_in_d_bits_source_0[6:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_77 = _source_ok_T_76 == 4'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_79 = _source_ok_T_77; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_81 = _source_ok_T_79; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_5 = _source_ok_T_81; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_12 = _source_ok_uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_83 = _source_ok_T_82 == 4'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_85 = _source_ok_T_83; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_87 = _source_ok_T_85; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_6 = _source_ok_T_87; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_13 = _source_ok_uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_89 = _source_ok_T_88 == 4'h8; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_91 = _source_ok_T_89; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_92 = source_ok_uncommonBits_13 < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_93 = _source_ok_T_91 & _source_ok_T_92; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_1_7 = _source_ok_T_93; // @[Parameters.scala:1138:31]
wire _source_ok_T_94 = io_in_d_bits_source_0 == 7'h48; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_94; // @[Parameters.scala:1138:31]
wire _source_ok_T_95 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_96 = _source_ok_T_95 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_97 = _source_ok_T_96 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_98 = _source_ok_T_97 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_99 = _source_ok_T_98 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_100 = _source_ok_T_99 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_101 = _source_ok_T_100 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_101 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire sink_ok = io_in_d_bits_sink_0[3:2] != 2'h3; // @[Monitor.scala:36:7, :309:31]
wire [27:0] _GEN_0 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T = {io_in_b_bits_address_0[31:28], _GEN_0}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46]
wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_5 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46]
wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40]
wire address_ok = _address_ok_WIRE_0 | _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64]
wire [31:0] _is_aligned_T_1 = {26'h0, io_in_b_bits_address_0[5:0]}; // @[Monitor.scala:36:7]
wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}]
wire mask_sub_sub_sub_bit_1 = io_in_b_bits_address_0[3]; // @[Misc.scala:210:26]
wire mask_sub_sub_sub_1_2_1 = mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_sub_nbit_1 = ~mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_sub_0_2_1 = mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2_1 = mask_sub_sub_sub_0_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T_4 = mask_sub_sub_0_2_1; // @[Misc.scala:214:27, :215:38]
wire mask_sub_sub_1_2_1 = mask_sub_sub_sub_0_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_acc_T_5 = mask_sub_sub_1_2_1; // @[Misc.scala:214:27, :215:38]
wire mask_sub_sub_2_2_1 = mask_sub_sub_sub_1_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T_6 = mask_sub_sub_2_2_1; // @[Misc.scala:214:27, :215:38]
wire mask_sub_sub_3_2_1 = mask_sub_sub_sub_1_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_acc_T_7 = mask_sub_sub_3_2_1; // @[Misc.scala:214:27, :215:38]
wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire mask_sub_4_2_1 = mask_sub_sub_2_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire mask_sub_5_2_1 = mask_sub_sub_2_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire mask_sub_6_2_1 = mask_sub_sub_3_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire mask_sub_7_2_1 = mask_sub_sub_3_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20]
wire mask_eq_16 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_16 = mask_eq_16; // @[Misc.scala:214:27, :215:38]
wire mask_eq_17 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_17 = mask_eq_17; // @[Misc.scala:214:27, :215:38]
wire mask_eq_18 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_18 = mask_eq_18; // @[Misc.scala:214:27, :215:38]
wire mask_eq_19 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_19 = mask_eq_19; // @[Misc.scala:214:27, :215:38]
wire mask_eq_20 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_20 = mask_eq_20; // @[Misc.scala:214:27, :215:38]
wire mask_eq_21 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_21 = mask_eq_21; // @[Misc.scala:214:27, :215:38]
wire mask_eq_22 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_22 = mask_eq_22; // @[Misc.scala:214:27, :215:38]
wire mask_eq_23 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_23 = mask_eq_23; // @[Misc.scala:214:27, :215:38]
wire mask_eq_24 = mask_sub_4_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_24 = mask_eq_24; // @[Misc.scala:214:27, :215:38]
wire mask_eq_25 = mask_sub_4_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_25 = mask_eq_25; // @[Misc.scala:214:27, :215:38]
wire mask_eq_26 = mask_sub_5_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_26 = mask_eq_26; // @[Misc.scala:214:27, :215:38]
wire mask_eq_27 = mask_sub_5_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_27 = mask_eq_27; // @[Misc.scala:214:27, :215:38]
wire mask_eq_28 = mask_sub_6_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_28 = mask_eq_28; // @[Misc.scala:214:27, :215:38]
wire mask_eq_29 = mask_sub_6_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_29 = mask_eq_29; // @[Misc.scala:214:27, :215:38]
wire mask_eq_30 = mask_sub_7_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_30 = mask_eq_30; // @[Misc.scala:214:27, :215:38]
wire mask_eq_31 = mask_sub_7_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_31 = mask_eq_31; // @[Misc.scala:214:27, :215:38]
wire _source_ok_T_102 = io_in_c_bits_source_0 == 7'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_2_0 = _source_ok_T_102; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_14 = _source_ok_uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_103 = io_in_c_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_109 = io_in_c_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_115 = io_in_c_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_121 = io_in_c_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_104 = _source_ok_T_103 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_106 = _source_ok_T_104; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_108 = _source_ok_T_106; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2_1 = _source_ok_T_108; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_15 = _source_ok_uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_110 = _source_ok_T_109 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_112 = _source_ok_T_110; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_114 = _source_ok_T_112; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2_2 = _source_ok_T_114; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_16 = _source_ok_uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_116 = _source_ok_T_115 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_118 = _source_ok_T_116; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_120 = _source_ok_T_118; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2_3 = _source_ok_T_120; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_17 = _source_ok_uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_122 = _source_ok_T_121 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_124 = _source_ok_T_122; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_126 = _source_ok_T_124; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2_4 = _source_ok_T_126; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_18 = _source_ok_uncommonBits_T_18[2:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_127 = io_in_c_bits_source_0[6:3]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_133 = io_in_c_bits_source_0[6:3]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_139 = io_in_c_bits_source_0[6:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_128 = _source_ok_T_127 == 4'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_130 = _source_ok_T_128; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_132 = _source_ok_T_130; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2_5 = _source_ok_T_132; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_19 = _source_ok_uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_134 = _source_ok_T_133 == 4'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_136 = _source_ok_T_134; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_138 = _source_ok_T_136; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2_6 = _source_ok_T_138; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_20 = _source_ok_uncommonBits_T_20[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_140 = _source_ok_T_139 == 4'h8; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_142 = _source_ok_T_140; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_143 = source_ok_uncommonBits_20 < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_144 = _source_ok_T_142 & _source_ok_T_143; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_2_7 = _source_ok_T_144; // @[Parameters.scala:1138:31]
wire _source_ok_T_145 = io_in_c_bits_source_0 == 7'h48; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_2_8 = _source_ok_T_145; // @[Parameters.scala:1138:31]
wire _source_ok_T_146 = _source_ok_WIRE_2_0 | _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_147 = _source_ok_T_146 | _source_ok_WIRE_2_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_148 = _source_ok_T_147 | _source_ok_WIRE_2_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_149 = _source_ok_T_148 | _source_ok_WIRE_2_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_150 = _source_ok_T_149 | _source_ok_WIRE_2_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_151 = _source_ok_T_150 | _source_ok_WIRE_2_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_152 = _source_ok_T_151 | _source_ok_WIRE_2_7; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_2 = _source_ok_T_152 | _source_ok_WIRE_2_8; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN_1 = 13'h3F << io_in_c_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T_4; // @[package.scala:243:71]
assign _is_aligned_mask_T_4 = _GEN_1; // @[package.scala:243:71]
wire [12:0] _c_first_beats1_decode_T; // @[package.scala:243:71]
assign _c_first_beats1_decode_T = _GEN_1; // @[package.scala:243:71]
wire [12:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _c_first_beats1_decode_T_3 = _GEN_1; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T_2 = {26'h0, io_in_c_bits_address_0[5:0] & is_aligned_mask_2}; // @[package.scala:243:46]
wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}]
wire [27:0] _GEN_2 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_10 = {io_in_c_bits_address_0[31:28], _GEN_2}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46]
wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_0 = _address_ok_T_14; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_15 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46]
wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_1 = _address_ok_T_19; // @[Parameters.scala:612:40]
wire address_ok_1 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64]
wire [1:0] uncommonBits_91 = _uncommonBits_T_91[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_92 = _uncommonBits_T_92[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_93 = _uncommonBits_T_93[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_94 = _uncommonBits_T_94[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_95 = _uncommonBits_T_95[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_96 = _uncommonBits_T_96[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_97 = _uncommonBits_T_97[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_98 = _uncommonBits_T_98[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_99 = _uncommonBits_T_99[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_100 = _uncommonBits_T_100[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_101 = _uncommonBits_T_101[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_102 = _uncommonBits_T_102[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_103 = _uncommonBits_T_103[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_104 = _uncommonBits_T_104[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_105 = _uncommonBits_T_105[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_106 = _uncommonBits_T_106[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_107 = _uncommonBits_T_107[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_108 = _uncommonBits_T_108[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_109 = _uncommonBits_T_109[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_110 = _uncommonBits_T_110[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_111 = _uncommonBits_T_111[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_112 = _uncommonBits_T_112[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_113 = _uncommonBits_T_113[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_114 = _uncommonBits_T_114[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_115 = _uncommonBits_T_115[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_116 = _uncommonBits_T_116[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_117 = _uncommonBits_T_117[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_118 = _uncommonBits_T_118[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_119 = _uncommonBits_T_119[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_120 = _uncommonBits_T_120[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_121 = _uncommonBits_T_121[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_122 = _uncommonBits_T_122[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_123 = _uncommonBits_T_123[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_124 = _uncommonBits_T_124[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_125 = _uncommonBits_T_125[2:0]; // @[Parameters.scala:52:{29,56}]
wire sink_ok_1 = io_in_e_bits_sink_0[3:2] != 2'h3; // @[Monitor.scala:36:7, :367:31]
wire _T_2407 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_2407; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_2407; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [1:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:4]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [1:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 2'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [1:0] a_first_counter; // @[Edges.scala:229:27]
wire [2:0] _a_first_counter1_T = {1'h0, a_first_counter} - 3'h1; // @[Edges.scala:229:27, :230:28]
wire [1:0] a_first_counter1 = _a_first_counter1_T[1:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 2'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 2'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [1:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [1:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [1:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_2481 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_2481; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_2481; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_2481; // @[Decoupled.scala:51:35]
wire _d_first_T_3; // @[Decoupled.scala:51:35]
assign _d_first_T_3 = _T_2481; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_3 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_3; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_3; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_3; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_9 = _GEN_3; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [1:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:4]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [1:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 2'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [1:0] d_first_counter; // @[Edges.scala:229:27]
wire [2:0] _d_first_counter1_T = {1'h0, d_first_counter} - 3'h1; // @[Edges.scala:229:27, :230:28]
wire [1:0] d_first_counter1 = _d_first_counter1_T[1:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 2'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 2'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [1:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [1:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [1:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg [3:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35]
wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35]
reg [1:0] b_first_counter; // @[Edges.scala:229:27]
wire [2:0] _b_first_counter1_T = {1'h0, b_first_counter} - 3'h1; // @[Edges.scala:229:27, :230:28]
wire [1:0] b_first_counter1 = _b_first_counter1_T[1:0]; // @[Edges.scala:230:28]
wire b_first = b_first_counter == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _b_first_last_T = b_first_counter == 2'h1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [1:0] _b_first_counter_T = b_first ? 2'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [1:0] param_2; // @[Monitor.scala:411:22]
reg [31:0] address_1; // @[Monitor.scala:414:22]
wire _T_2478 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35]
wire _c_first_T; // @[Decoupled.scala:51:35]
assign _c_first_T = _T_2478; // @[Decoupled.scala:51:35]
wire _c_first_T_1; // @[Decoupled.scala:51:35]
assign _c_first_T_1 = _T_2478; // @[Decoupled.scala:51:35]
wire [5:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [1:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[5:4]; // @[package.scala:243:46]
wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [1:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 2'h0; // @[Edges.scala:102:36, :220:59, :221:14]
reg [1:0] c_first_counter; // @[Edges.scala:229:27]
wire [2:0] _c_first_counter1_T = {1'h0, c_first_counter} - 3'h1; // @[Edges.scala:229:27, :230:28]
wire [1:0] c_first_counter1 = _c_first_counter1_T[1:0]; // @[Edges.scala:230:28]
wire c_first = c_first_counter == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _c_first_last_T = c_first_counter == 2'h1; // @[Edges.scala:229:27, :232:25]
wire _c_first_last_T_1 = c_first_beats1 == 2'h0; // @[Edges.scala:221:14, :232:43]
wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35]
wire [1:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [1:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [1:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_3; // @[Monitor.scala:515:22]
reg [2:0] param_3; // @[Monitor.scala:516:22]
reg [2:0] size_3; // @[Monitor.scala:517:22]
reg [6:0] source_3; // @[Monitor.scala:518:22]
reg [31:0] address_2; // @[Monitor.scala:519:22]
reg [72:0] inflight; // @[Monitor.scala:614:27]
reg [291:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [291:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [1:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:4]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [1:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 2'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [1:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [2:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 3'h1; // @[Edges.scala:229:27, :230:28]
wire [1:0] a_first_counter1_1 = _a_first_counter1_T_1[1:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 2'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 2'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [1:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [1:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [1:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [1:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:4]; // @[package.scala:243:46]
wire [1:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 2'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [1:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [2:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 3'h1; // @[Edges.scala:229:27, :230:28]
wire [1:0] d_first_counter1_1 = _d_first_counter1_T_1[1:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 2'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 2'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [1:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [1:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [1:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [72:0] a_set; // @[Monitor.scala:626:34]
wire [72:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [291:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [291:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [9:0] _GEN_4 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_4; // @[Monitor.scala:637:69]
wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :641:65]
wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_4; // @[Monitor.scala:637:69, :680:101]
wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_4; // @[Monitor.scala:637:69, :681:99]
wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :749:69]
wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :750:67]
wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_4; // @[Monitor.scala:637:69, :790:101]
wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_4; // @[Monitor.scala:637:69, :791:99]
wire [291:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [291:0] _a_opcode_lookup_T_6 = {288'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [291:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[291:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [291:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [291:0] _a_size_lookup_T_6 = {288'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [291:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[291:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [127:0] _GEN_5 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_5; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[72:0] : 73'h0; // @[OneHot.scala:58:35]
wire _T_2333 = _T_2407 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_2333 ? _a_set_T[72:0] : 73'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_2333 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_2333 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [9:0] _GEN_6 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_6; // @[Monitor.scala:659:79]
wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_6; // @[Monitor.scala:659:79, :660:77]
wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_2333 ? _a_opcodes_set_T_1[291:0] : 292'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_2333 ? _a_sizes_set_T_1[291:0] : 292'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [72:0] d_clr; // @[Monitor.scala:664:34]
wire [72:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [291:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [291:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_7 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_7; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_7; // @[Monitor.scala:673:46, :783:46]
wire _T_2379 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [127:0] _GEN_8 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_8; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_8; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_8; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_8; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_2379 & ~d_release_ack ? _d_clr_wo_ready_T[72:0] : 73'h0; // @[OneHot.scala:58:35]
wire _T_2348 = _T_2481 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_2348 ? _d_clr_T[72:0] : 73'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_2348 ? _d_opcodes_clr_T_5[291:0] : 292'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_2348 ? _d_sizes_clr_T_5[291:0] : 292'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [72:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [72:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [72:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [291:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [291:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [291:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [291:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [291:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [291:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [72:0] inflight_1; // @[Monitor.scala:726:35]
reg [291:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
reg [291:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [5:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [1:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[5:4]; // @[package.scala:243:46]
wire [1:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 2'h0; // @[Edges.scala:102:36, :220:59, :221:14]
reg [1:0] c_first_counter_1; // @[Edges.scala:229:27]
wire [2:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 3'h1; // @[Edges.scala:229:27, :230:28]
wire [1:0] c_first_counter1_1 = _c_first_counter1_T_1[1:0]; // @[Edges.scala:230:28]
wire c_first_1 = c_first_counter_1 == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _c_first_last_T_2 = c_first_counter_1 == 2'h1; // @[Edges.scala:229:27, :232:25]
wire _c_first_last_T_3 = c_first_beats1_1 == 2'h0; // @[Edges.scala:221:14, :232:43]
wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35]
wire [1:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [1:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [1:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [1:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:4]; // @[package.scala:243:46]
wire [1:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 2'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [1:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [2:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 3'h1; // @[Edges.scala:229:27, :230:28]
wire [1:0] d_first_counter1_2 = _d_first_counter1_T_2[1:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 2'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 2'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [1:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [1:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [1:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [72:0] c_set; // @[Monitor.scala:738:34]
wire [72:0] c_set_wo_ready; // @[Monitor.scala:739:34]
wire [291:0] c_opcodes_set; // @[Monitor.scala:740:34]
wire [291:0] c_sizes_set; // @[Monitor.scala:741:34]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [291:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [291:0] _c_opcode_lookup_T_6 = {288'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [291:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[291:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [291:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [291:0] _c_size_lookup_T_6 = {288'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [291:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[291:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm; // @[Monitor.scala:755:40]
wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44]
wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7]
wire [127:0] _GEN_9 = 128'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _c_set_wo_ready_T = _GEN_9; // @[OneHot.scala:58:35]
wire [127:0] _c_set_T; // @[OneHot.scala:58:35]
assign _c_set_T = _GEN_9; // @[OneHot.scala:58:35]
assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[72:0] : 73'h0; // @[OneHot.scala:58:35]
wire _T_2420 = _T_2478 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35]
assign c_set = _T_2420 ? _c_set_T[72:0] : 73'h0; // @[OneHot.scala:58:35]
wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53]
wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}]
assign c_opcodes_set_interm = _T_2420 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}]
wire [3:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51]
wire [3:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:766:{51,59}]
assign c_sizes_set_interm = _T_2420 ? _c_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}]
wire [9:0] _GEN_10 = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79]
wire [9:0] _c_opcodes_set_T; // @[Monitor.scala:767:79]
assign _c_opcodes_set_T = _GEN_10; // @[Monitor.scala:767:79]
wire [9:0] _c_sizes_set_T; // @[Monitor.scala:768:77]
assign _c_sizes_set_T = _GEN_10; // @[Monitor.scala:767:79, :768:77]
wire [1026:0] _c_opcodes_set_T_1 = {1023'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}]
assign c_opcodes_set = _T_2420 ? _c_opcodes_set_T_1[291:0] : 292'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}]
wire [1026:0] _c_sizes_set_T_1 = {1023'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}]
assign c_sizes_set = _T_2420 ? _c_sizes_set_T_1[291:0] : 292'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}]
wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47]
wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95]
wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}]
wire [72:0] d_clr_1; // @[Monitor.scala:774:34]
wire [72:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [291:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [291:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_2451 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_2451 & d_release_ack_1 ? _d_clr_wo_ready_T_1[72:0] : 73'h0; // @[OneHot.scala:58:35]
wire _T_2433 = _T_2481 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_2433 ? _d_clr_T_1[72:0] : 73'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_2433 ? _d_opcodes_clr_T_11[291:0] : 292'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_2433 ? _d_sizes_clr_T_11[291:0] : 292'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}]
wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}]
wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113]
wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}]
wire [72:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35]
wire [72:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [72:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [291:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43]
wire [291:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [291:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [291:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41]
wire [291:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [291:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26]
wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26]
reg [11:0] inflight_2; // @[Monitor.scala:828:27]
wire [5:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}]
wire [1:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[5:4]; // @[package.scala:243:46]
wire [1:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 2'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [1:0] d_first_counter_3; // @[Edges.scala:229:27]
wire [2:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 3'h1; // @[Edges.scala:229:27, :230:28]
wire [1:0] d_first_counter1_3 = _d_first_counter1_T_3[1:0]; // @[Edges.scala:230:28]
wire d_first_3 = d_first_counter_3 == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_6 = d_first_counter_3 == 2'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_7 = d_first_beats1_3 == 2'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35]
wire [1:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27]
wire [1:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}]
wire [1:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] d_set; // @[Monitor.scala:833:25]
wire _T_2487 = _T_2481 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35]
wire [15:0] _d_set_T = 16'h1 << io_in_d_bits_sink_0; // @[OneHot.scala:58:35]
assign d_set = _T_2487 ? _d_set_T[11:0] : 12'h0; // @[OneHot.scala:58:35]
wire [11:0] e_clr; // @[Monitor.scala:839:25]
wire [15:0] _e_clr_T = 16'h1 << io_in_e_bits_sink_0; // @[OneHot.scala:58:35]
assign e_clr = io_in_e_valid_0 ? _e_clr_T[11:0] : 12'h0; // @[OneHot.scala:58:35] |
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a32d64s1k3z4c_2 :
input clock : Clock
input reset : Reset
output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate nodeIn.e.bits.sink
invalidate nodeIn.e.valid
invalidate nodeIn.e.ready
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.c.bits.corrupt
invalidate nodeIn.c.bits.data
invalidate nodeIn.c.bits.address
invalidate nodeIn.c.bits.source
invalidate nodeIn.c.bits.size
invalidate nodeIn.c.bits.param
invalidate nodeIn.c.bits.opcode
invalidate nodeIn.c.valid
invalidate nodeIn.c.ready
invalidate nodeIn.b.bits.corrupt
invalidate nodeIn.b.bits.data
invalidate nodeIn.b.bits.mask
invalidate nodeIn.b.bits.address
invalidate nodeIn.b.bits.source
invalidate nodeIn.b.bits.size
invalidate nodeIn.b.bits.param
invalidate nodeIn.b.bits.opcode
invalidate nodeIn.b.valid
invalidate nodeIn.b.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
inst monitor of TLMonitor_9
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.e.bits.sink, nodeIn.e.bits.sink
connect monitor.io.in.e.valid, nodeIn.e.valid
connect monitor.io.in.e.ready, nodeIn.e.ready
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.c.bits.corrupt, nodeIn.c.bits.corrupt
connect monitor.io.in.c.bits.data, nodeIn.c.bits.data
connect monitor.io.in.c.bits.address, nodeIn.c.bits.address
connect monitor.io.in.c.bits.source, nodeIn.c.bits.source
connect monitor.io.in.c.bits.size, nodeIn.c.bits.size
connect monitor.io.in.c.bits.param, nodeIn.c.bits.param
connect monitor.io.in.c.bits.opcode, nodeIn.c.bits.opcode
connect monitor.io.in.c.valid, nodeIn.c.valid
connect monitor.io.in.c.ready, nodeIn.c.ready
connect monitor.io.in.b.bits.corrupt, nodeIn.b.bits.corrupt
connect monitor.io.in.b.bits.data, nodeIn.b.bits.data
connect monitor.io.in.b.bits.mask, nodeIn.b.bits.mask
connect monitor.io.in.b.bits.address, nodeIn.b.bits.address
connect monitor.io.in.b.bits.source, nodeIn.b.bits.source
connect monitor.io.in.b.bits.size, nodeIn.b.bits.size
connect monitor.io.in.b.bits.param, nodeIn.b.bits.param
connect monitor.io.in.b.bits.opcode, nodeIn.b.bits.opcode
connect monitor.io.in.b.valid, nodeIn.b.valid
connect monitor.io.in.b.ready, nodeIn.b.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate nodeOut.e.bits.sink
invalidate nodeOut.e.valid
invalidate nodeOut.e.ready
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.c.bits.corrupt
invalidate nodeOut.c.bits.data
invalidate nodeOut.c.bits.address
invalidate nodeOut.c.bits.source
invalidate nodeOut.c.bits.size
invalidate nodeOut.c.bits.param
invalidate nodeOut.c.bits.opcode
invalidate nodeOut.c.valid
invalidate nodeOut.c.ready
invalidate nodeOut.b.bits.corrupt
invalidate nodeOut.b.bits.data
invalidate nodeOut.b.bits.mask
invalidate nodeOut.b.bits.address
invalidate nodeOut.b.bits.source
invalidate nodeOut.b.bits.size
invalidate nodeOut.b.bits.param
invalidate nodeOut.b.bits.opcode
invalidate nodeOut.b.valid
invalidate nodeOut.b.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
connect auto.out, nodeOut
connect nodeIn, auto.in
inst nodeOut_a_q of Queue2_TLBundleA_a32d64s1k3z4c_2
connect nodeOut_a_q.clock, clock
connect nodeOut_a_q.reset, reset
connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid
connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt
connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data
connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask
connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address
connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source
connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size
connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param
connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode
connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready
connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits
connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid
connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready
inst nodeIn_d_q of Queue2_TLBundleD_a32d64s1k3z4c_2
connect nodeIn_d_q.clock, clock
connect nodeIn_d_q.reset, reset
connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid
connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt
connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data
connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied
connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink
connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source
connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size
connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param
connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode
connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready
connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits
connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid
connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready
inst nodeIn_b_q of Queue2_TLBundleB_a32d64s1k3z4c_2
connect nodeIn_b_q.clock, clock
connect nodeIn_b_q.reset, reset
connect nodeIn_b_q.io.enq.valid, nodeOut.b.valid
connect nodeIn_b_q.io.enq.bits.corrupt, nodeOut.b.bits.corrupt
connect nodeIn_b_q.io.enq.bits.data, nodeOut.b.bits.data
connect nodeIn_b_q.io.enq.bits.mask, nodeOut.b.bits.mask
connect nodeIn_b_q.io.enq.bits.address, nodeOut.b.bits.address
connect nodeIn_b_q.io.enq.bits.source, nodeOut.b.bits.source
connect nodeIn_b_q.io.enq.bits.size, nodeOut.b.bits.size
connect nodeIn_b_q.io.enq.bits.param, nodeOut.b.bits.param
connect nodeIn_b_q.io.enq.bits.opcode, nodeOut.b.bits.opcode
connect nodeOut.b.ready, nodeIn_b_q.io.enq.ready
connect nodeIn.b.bits, nodeIn_b_q.io.deq.bits
connect nodeIn.b.valid, nodeIn_b_q.io.deq.valid
connect nodeIn_b_q.io.deq.ready, nodeIn.b.ready
inst nodeOut_c_q of Queue2_TLBundleC_a32d64s1k3z4c_2
connect nodeOut_c_q.clock, clock
connect nodeOut_c_q.reset, reset
connect nodeOut_c_q.io.enq.valid, nodeIn.c.valid
connect nodeOut_c_q.io.enq.bits.corrupt, nodeIn.c.bits.corrupt
connect nodeOut_c_q.io.enq.bits.data, nodeIn.c.bits.data
connect nodeOut_c_q.io.enq.bits.address, nodeIn.c.bits.address
connect nodeOut_c_q.io.enq.bits.source, nodeIn.c.bits.source
connect nodeOut_c_q.io.enq.bits.size, nodeIn.c.bits.size
connect nodeOut_c_q.io.enq.bits.param, nodeIn.c.bits.param
connect nodeOut_c_q.io.enq.bits.opcode, nodeIn.c.bits.opcode
connect nodeIn.c.ready, nodeOut_c_q.io.enq.ready
connect nodeOut.c.bits, nodeOut_c_q.io.deq.bits
connect nodeOut.c.valid, nodeOut_c_q.io.deq.valid
connect nodeOut_c_q.io.deq.ready, nodeOut.c.ready
inst nodeOut_e_q of Queue2_TLBundleE_a32d64s1k3z4c_2
connect nodeOut_e_q.clock, clock
connect nodeOut_e_q.reset, reset
connect nodeOut_e_q.io.enq.valid, nodeIn.e.valid
connect nodeOut_e_q.io.enq.bits.sink, nodeIn.e.bits.sink
connect nodeIn.e.ready, nodeOut_e_q.io.enq.ready
connect nodeOut.e.bits, nodeOut_e_q.io.deq.bits
connect nodeOut.e.valid, nodeOut_e_q.io.deq.valid
connect nodeOut_e_q.io.deq.ready, nodeOut.e.ready | module TLBuffer_a32d64s1k3z4c_2( // @[Buffer.scala:40:9]
input clock, // @[Buffer.scala:40:9]
input reset, // @[Buffer.scala:40:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_b_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_b_bits_size, // @[LazyModuleImp.scala:107:25]
output auto_in_b_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_in_b_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_in_b_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_b_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_c_bits_size, // @[LazyModuleImp.scala:107:25]
input auto_in_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_e_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_e_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_b_valid, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_b_bits_param, // @[LazyModuleImp.scala:107:25]
input auto_out_b_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_out_b_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_out_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25]
output auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_e_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_e_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_e_bits_sink // @[LazyModuleImp.scala:107:25]
);
wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9]
wire auto_in_b_ready_0 = auto_in_b_ready; // @[Buffer.scala:40:9]
wire auto_in_c_valid_0 = auto_in_c_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_c_bits_opcode_0 = auto_in_c_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] auto_in_c_bits_param_0 = auto_in_c_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_in_c_bits_size_0 = auto_in_c_bits_size; // @[Buffer.scala:40:9]
wire auto_in_c_bits_source_0 = auto_in_c_bits_source; // @[Buffer.scala:40:9]
wire [31:0] auto_in_c_bits_address_0 = auto_in_c_bits_address; // @[Buffer.scala:40:9]
wire [63:0] auto_in_c_bits_data_0 = auto_in_c_bits_data; // @[Buffer.scala:40:9]
wire auto_in_c_bits_corrupt_0 = auto_in_c_bits_corrupt; // @[Buffer.scala:40:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9]
wire auto_in_e_valid_0 = auto_in_e_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_e_bits_sink_0 = auto_in_e_bits_sink; // @[Buffer.scala:40:9]
wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9]
wire auto_out_b_valid_0 = auto_out_b_valid; // @[Buffer.scala:40:9]
wire [1:0] auto_out_b_bits_param_0 = auto_out_b_bits_param; // @[Buffer.scala:40:9]
wire auto_out_b_bits_source_0 = auto_out_b_bits_source; // @[Buffer.scala:40:9]
wire [31:0] auto_out_b_bits_address_0 = auto_out_b_bits_address; // @[Buffer.scala:40:9]
wire auto_out_c_ready_0 = auto_out_c_ready; // @[Buffer.scala:40:9]
wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9]
wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9]
wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9]
wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9]
wire auto_out_e_ready_0 = auto_out_e_ready; // @[Buffer.scala:40:9]
wire auto_out_b_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire nodeOut_b_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire [63:0] auto_out_b_bits_data = 64'h0; // @[Decoupled.scala:362:21]
wire [63:0] nodeOut_b_bits_data = 64'h0; // @[Decoupled.scala:362:21]
wire [7:0] auto_out_b_bits_mask = 8'hFF; // @[Decoupled.scala:362:21]
wire [7:0] nodeOut_b_bits_mask = 8'hFF; // @[Decoupled.scala:362:21]
wire [3:0] auto_out_b_bits_size = 4'h6; // @[Decoupled.scala:362:21]
wire [3:0] nodeOut_b_bits_size = 4'h6; // @[Decoupled.scala:362:21]
wire [2:0] auto_out_b_bits_opcode = 3'h6; // @[Decoupled.scala:362:21]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire [2:0] nodeOut_b_bits_opcode = 3'h6; // @[Decoupled.scala:362:21]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9]
wire nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9]
wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire nodeIn_b_ready = auto_in_b_ready_0; // @[Buffer.scala:40:9]
wire nodeIn_b_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_b_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_b_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_b_bits_size; // @[MixedNode.scala:551:17]
wire nodeIn_b_bits_source; // @[MixedNode.scala:551:17]
wire [31:0] nodeIn_b_bits_address; // @[MixedNode.scala:551:17]
wire [7:0] nodeIn_b_bits_mask; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_b_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_b_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeIn_c_ready; // @[MixedNode.scala:551:17]
wire nodeIn_c_valid = auto_in_c_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_c_bits_opcode = auto_in_c_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_c_bits_param = auto_in_c_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeIn_c_bits_size = auto_in_c_bits_size_0; // @[Buffer.scala:40:9]
wire nodeIn_c_bits_source = auto_in_c_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] nodeIn_c_bits_address = auto_in_c_bits_address_0; // @[Buffer.scala:40:9]
wire [63:0] nodeIn_c_bits_data = auto_in_c_bits_data_0; // @[Buffer.scala:40:9]
wire nodeIn_c_bits_corrupt = auto_in_c_bits_corrupt_0; // @[Buffer.scala:40:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeIn_e_ready; // @[MixedNode.scala:551:17]
wire nodeIn_e_valid = auto_in_e_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_e_bits_sink = auto_in_e_bits_sink_0; // @[Buffer.scala:40:9]
wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_b_ready; // @[MixedNode.scala:542:17]
wire nodeOut_b_valid = auto_out_b_valid_0; // @[Buffer.scala:40:9]
wire [1:0] nodeOut_b_bits_param = auto_out_b_bits_param_0; // @[Buffer.scala:40:9]
wire nodeOut_b_bits_source = auto_out_b_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] nodeOut_b_bits_address = auto_out_b_bits_address_0; // @[Buffer.scala:40:9]
wire nodeOut_c_ready = auto_out_c_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_c_bits_size; // @[MixedNode.scala:542:17]
wire nodeOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_c_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire nodeOut_e_ready = auto_out_e_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_e_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire auto_in_a_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_b_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_b_bits_size_0; // @[Buffer.scala:40:9]
wire auto_in_b_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] auto_in_b_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] auto_in_b_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] auto_in_b_bits_data_0; // @[Buffer.scala:40:9]
wire auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_b_valid_0; // @[Buffer.scala:40:9]
wire auto_in_c_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_d_valid_0; // @[Buffer.scala:40:9]
wire auto_in_e_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
wire auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_out_a_valid_0; // @[Buffer.scala:40:9]
wire auto_out_b_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_c_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_c_bits_size_0; // @[Buffer.scala:40:9]
wire auto_out_c_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] auto_out_c_bits_address_0; // @[Buffer.scala:40:9]
wire [63:0] auto_out_c_bits_data_0; // @[Buffer.scala:40:9]
wire auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_out_c_valid_0; // @[Buffer.scala:40:9]
wire auto_out_d_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_e_bits_sink_0; // @[Buffer.scala:40:9]
wire auto_out_e_valid_0; // @[Buffer.scala:40:9]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9]
assign auto_in_b_valid_0 = nodeIn_b_valid; // @[Buffer.scala:40:9]
assign auto_in_b_bits_opcode_0 = nodeIn_b_bits_opcode; // @[Buffer.scala:40:9]
assign auto_in_b_bits_param_0 = nodeIn_b_bits_param; // @[Buffer.scala:40:9]
assign auto_in_b_bits_size_0 = nodeIn_b_bits_size; // @[Buffer.scala:40:9]
assign auto_in_b_bits_source_0 = nodeIn_b_bits_source; // @[Buffer.scala:40:9]
assign auto_in_b_bits_address_0 = nodeIn_b_bits_address; // @[Buffer.scala:40:9]
assign auto_in_b_bits_mask_0 = nodeIn_b_bits_mask; // @[Buffer.scala:40:9]
assign auto_in_b_bits_data_0 = nodeIn_b_bits_data; // @[Buffer.scala:40:9]
assign auto_in_b_bits_corrupt_0 = nodeIn_b_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_in_c_ready_0 = nodeIn_c_ready; // @[Buffer.scala:40:9]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_in_e_ready_0 = nodeIn_e_ready; // @[Buffer.scala:40:9]
assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_b_ready_0 = nodeOut_b_ready; // @[Buffer.scala:40:9]
assign auto_out_c_valid_0 = nodeOut_c_valid; // @[Buffer.scala:40:9]
assign auto_out_c_bits_opcode_0 = nodeOut_c_bits_opcode; // @[Buffer.scala:40:9]
assign auto_out_c_bits_param_0 = nodeOut_c_bits_param; // @[Buffer.scala:40:9]
assign auto_out_c_bits_size_0 = nodeOut_c_bits_size; // @[Buffer.scala:40:9]
assign auto_out_c_bits_source_0 = nodeOut_c_bits_source; // @[Buffer.scala:40:9]
assign auto_out_c_bits_address_0 = nodeOut_c_bits_address; // @[Buffer.scala:40:9]
assign auto_out_c_bits_data_0 = nodeOut_c_bits_data; // @[Buffer.scala:40:9]
assign auto_out_c_bits_corrupt_0 = nodeOut_c_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9]
assign auto_out_e_valid_0 = nodeOut_e_valid; // @[Buffer.scala:40:9]
assign auto_out_e_bits_sink_0 = nodeOut_e_bits_sink; // @[Buffer.scala:40:9]
TLMonitor_9 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_b_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17]
.io_in_b_valid (nodeIn_b_valid), // @[MixedNode.scala:551:17]
.io_in_b_bits_opcode (nodeIn_b_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_b_bits_param (nodeIn_b_bits_param), // @[MixedNode.scala:551:17]
.io_in_b_bits_size (nodeIn_b_bits_size), // @[MixedNode.scala:551:17]
.io_in_b_bits_source (nodeIn_b_bits_source), // @[MixedNode.scala:551:17]
.io_in_b_bits_address (nodeIn_b_bits_address), // @[MixedNode.scala:551:17]
.io_in_b_bits_mask (nodeIn_b_bits_mask), // @[MixedNode.scala:551:17]
.io_in_b_bits_data (nodeIn_b_bits_data), // @[MixedNode.scala:551:17]
.io_in_b_bits_corrupt (nodeIn_b_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_c_ready (nodeIn_c_ready), // @[MixedNode.scala:551:17]
.io_in_c_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17]
.io_in_c_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_c_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17]
.io_in_c_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17]
.io_in_c_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17]
.io_in_c_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17]
.io_in_c_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17]
.io_in_c_bits_corrupt (nodeIn_c_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_e_ready (nodeIn_e_ready), // @[MixedNode.scala:551:17]
.io_in_e_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17]
.io_in_e_bits_sink (nodeIn_e_bits_sink) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
Queue2_TLBundleA_a32d64s1k3z4c_2 nodeOut_a_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_a_ready),
.io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_a_valid),
.io_deq_bits_opcode (nodeOut_a_bits_opcode),
.io_deq_bits_param (nodeOut_a_bits_param),
.io_deq_bits_size (nodeOut_a_bits_size),
.io_deq_bits_source (nodeOut_a_bits_source),
.io_deq_bits_address (nodeOut_a_bits_address),
.io_deq_bits_mask (nodeOut_a_bits_mask),
.io_deq_bits_data (nodeOut_a_bits_data),
.io_deq_bits_corrupt (nodeOut_a_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleD_a32d64s1k3z4c_2 nodeIn_d_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeOut_d_ready),
.io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17]
.io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17]
.io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17]
.io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17]
.io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17]
.io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17]
.io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17]
.io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17]
.io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_d_valid),
.io_deq_bits_opcode (nodeIn_d_bits_opcode),
.io_deq_bits_param (nodeIn_d_bits_param),
.io_deq_bits_size (nodeIn_d_bits_size),
.io_deq_bits_source (nodeIn_d_bits_source),
.io_deq_bits_sink (nodeIn_d_bits_sink),
.io_deq_bits_denied (nodeIn_d_bits_denied),
.io_deq_bits_data (nodeIn_d_bits_data),
.io_deq_bits_corrupt (nodeIn_d_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleB_a32d64s1k3z4c_2 nodeIn_b_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeOut_b_ready),
.io_enq_valid (nodeOut_b_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_param (nodeOut_b_bits_param), // @[MixedNode.scala:542:17]
.io_enq_bits_source (nodeOut_b_bits_source), // @[MixedNode.scala:542:17]
.io_enq_bits_address (nodeOut_b_bits_address), // @[MixedNode.scala:542:17]
.io_deq_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_b_valid),
.io_deq_bits_opcode (nodeIn_b_bits_opcode),
.io_deq_bits_param (nodeIn_b_bits_param),
.io_deq_bits_size (nodeIn_b_bits_size),
.io_deq_bits_source (nodeIn_b_bits_source),
.io_deq_bits_address (nodeIn_b_bits_address),
.io_deq_bits_mask (nodeIn_b_bits_mask),
.io_deq_bits_data (nodeIn_b_bits_data),
.io_deq_bits_corrupt (nodeIn_b_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleC_a32d64s1k3z4c_2 nodeOut_c_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_c_ready),
.io_enq_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17]
.io_enq_bits_corrupt (nodeIn_c_bits_corrupt), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_c_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_c_valid),
.io_deq_bits_opcode (nodeOut_c_bits_opcode),
.io_deq_bits_param (nodeOut_c_bits_param),
.io_deq_bits_size (nodeOut_c_bits_size),
.io_deq_bits_source (nodeOut_c_bits_source),
.io_deq_bits_address (nodeOut_c_bits_address),
.io_deq_bits_data (nodeOut_c_bits_data),
.io_deq_bits_corrupt (nodeOut_c_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleE_a32d64s1k3z4c_2 nodeOut_e_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_e_ready),
.io_enq_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_sink (nodeIn_e_bits_sink), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_e_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_e_valid),
.io_deq_bits_sink (nodeOut_e_bits_sink)
); // @[Decoupled.scala:362:21]
assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9]
assign auto_in_b_valid = auto_in_b_valid_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_opcode = auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_param = auto_in_b_bits_param_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_size = auto_in_b_bits_size_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_source = auto_in_b_bits_source_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_address = auto_in_b_bits_address_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_mask = auto_in_b_bits_mask_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_data = auto_in_b_bits_data_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_corrupt = auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_in_c_ready = auto_in_c_ready_0; // @[Buffer.scala:40:9]
assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_in_e_ready = auto_in_e_ready_0; // @[Buffer.scala:40:9]
assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_b_ready = auto_out_b_ready_0; // @[Buffer.scala:40:9]
assign auto_out_c_valid = auto_out_c_valid_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_opcode = auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_param = auto_out_c_bits_param_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_size = auto_out_c_bits_size_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_source = auto_out_c_bits_source_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_address = auto_out_c_bits_address_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_data = auto_out_c_bits_data_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_corrupt = auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9]
assign auto_out_e_valid = auto_out_e_valid_0; // @[Buffer.scala:40:9]
assign auto_out_e_bits_sink = auto_out_e_bits_sink_0; // @[Buffer.scala:40:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_108 :
output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node rawIn_exp = bits(io.in, 31, 23)
node _rawIn_isZero_T = bits(rawIn_exp, 8, 6)
node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0))
node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7)
node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3))
wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T)
connect rawIn.isNaN, _rawIn_out_isNaN_T_1
node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0))
node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1)
connect rawIn.isInf, _rawIn_out_isInf_T_2
connect rawIn.isZero, rawIn_isZero
node _rawIn_out_sign_T = bits(io.in, 32, 32)
connect rawIn.sign, _rawIn_out_sign_T
node _rawIn_out_sExp_T = cvt(rawIn_exp)
connect rawIn.sExp, _rawIn_out_sExp_T
node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0))
node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T)
node _rawIn_out_sig_T_2 = bits(io.in, 22, 0)
node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2)
connect rawIn.sig, _rawIn_out_sig_T_3
node _io_out_T = shl(io.in, 0)
connect io.out, _io_out_T
node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22)
node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0))
node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0))
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RecFNToRecFN_108( // @[RecFNToRecFN.scala:44:5]
input [32:0] io_in, // @[RecFNToRecFN.scala:48:16]
output [32:0] io_out // @[RecFNToRecFN.scala:48:16]
);
wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5]
wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35]
wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54]
wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5]
wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5]
wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35]
wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}]
wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46]
assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54]
assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_97 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_161
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_97( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_161 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_3 :
input clock : Clock
input reset : Reset
output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}}}, flip vcalloc_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}}, flip out_credit_available : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<3>, sa_stall : UInt<3>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}}
inst input_buffer of InputBuffer_3
connect input_buffer.clock, clock
connect input_buffer.reset, reset
connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id
connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id
connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node
connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id
connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node
connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id
connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload
connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail
connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head
connect input_buffer.io.enq[0].valid, io.in.flit[0].valid
connect input_buffer.io.deq[0].ready, UInt<1>(0h0)
connect input_buffer.io.deq[1].ready, UInt<1>(0h0)
connect input_buffer.io.deq[2].ready, UInt<1>(0h0)
connect input_buffer.io.deq[3].ready, UInt<1>(0h0)
connect input_buffer.io.deq[4].ready, UInt<1>(0h0)
connect input_buffer.io.deq[5].ready, UInt<1>(0h0)
connect input_buffer.io.deq[6].ready, UInt<1>(0h0)
connect input_buffer.io.deq[7].ready, UInt<1>(0h0)
inst route_arbiter of Arbiter8_RouteComputerReq_3
connect route_arbiter.clock, clock
connect route_arbiter.reset, reset
connect io.router_req.bits, route_arbiter.io.out.bits
connect io.router_req.valid, route_arbiter.io.out.valid
connect route_arbiter.io.out.ready, io.router_req.ready
reg states : { g : UInt<3>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, fifo_deps : UInt<8>}[8], clock
node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T :
node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<4>(0h8))
node _T_2 = asUInt(reset)
node _T_3 = eq(_T_2, UInt<1>(0h0))
when _T_3 :
node _T_4 = eq(_T_1, UInt<1>(0h0))
when _T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf
assert(clock, _T_1, UInt<1>(0h1), "") : assert
node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0))
node _T_6 = asUInt(reset)
node _T_7 = eq(_T_6, UInt<1>(0h0))
when _T_7 :
node _T_8 = eq(_T_5, UInt<1>(0h0))
when _T_8 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1
assert(clock, _T_5, UInt<1>(0h1), "") : assert_1
node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3))
node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1))
connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[3], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[4], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[5], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[6], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[7], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h0)
node _T_9 = eq(UInt<1>(0h0), io.in.flit[0].bits.flow.egress_node_id)
when _T_9 :
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h1)
node _T_10 = eq(UInt<1>(0h1), io.in.flit[0].bits.flow.egress_node_id)
when _T_10 :
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h1)
node _T_11 = eq(UInt<2>(0h2), io.in.flit[0].bits.flow.egress_node_id)
when _T_11 :
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h1)
connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow
connect route_arbiter.io.in[0].valid, UInt<1>(0h0)
invalidate route_arbiter.io.in[0].bits.flow.egress_node_id
invalidate route_arbiter.io.in[0].bits.flow.egress_node
invalidate route_arbiter.io.in[0].bits.flow.ingress_node_id
invalidate route_arbiter.io.in[0].bits.flow.ingress_node
invalidate route_arbiter.io.in[0].bits.flow.vnet_id
invalidate route_arbiter.io.in[0].bits.src_virt_id
connect route_arbiter.io.in[1].valid, UInt<1>(0h0)
invalidate route_arbiter.io.in[1].bits.flow.egress_node_id
invalidate route_arbiter.io.in[1].bits.flow.egress_node
invalidate route_arbiter.io.in[1].bits.flow.ingress_node_id
invalidate route_arbiter.io.in[1].bits.flow.ingress_node
invalidate route_arbiter.io.in[1].bits.flow.vnet_id
invalidate route_arbiter.io.in[1].bits.src_virt_id
connect route_arbiter.io.in[2].valid, UInt<1>(0h0)
invalidate route_arbiter.io.in[2].bits.flow.egress_node_id
invalidate route_arbiter.io.in[2].bits.flow.egress_node
invalidate route_arbiter.io.in[2].bits.flow.ingress_node_id
invalidate route_arbiter.io.in[2].bits.flow.ingress_node
invalidate route_arbiter.io.in[2].bits.flow.vnet_id
invalidate route_arbiter.io.in[2].bits.src_virt_id
connect route_arbiter.io.in[3].valid, UInt<1>(0h0)
invalidate route_arbiter.io.in[3].bits.flow.egress_node_id
invalidate route_arbiter.io.in[3].bits.flow.egress_node
invalidate route_arbiter.io.in[3].bits.flow.ingress_node_id
invalidate route_arbiter.io.in[3].bits.flow.ingress_node
invalidate route_arbiter.io.in[3].bits.flow.vnet_id
invalidate route_arbiter.io.in[3].bits.src_virt_id
node _route_arbiter_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h1))
connect route_arbiter.io.in[4].valid, _route_arbiter_io_in_4_valid_T
connect route_arbiter.io.in[4].bits.flow.egress_node_id, states[4].flow.egress_node_id
connect route_arbiter.io.in[4].bits.flow.egress_node, states[4].flow.egress_node
connect route_arbiter.io.in[4].bits.flow.ingress_node_id, states[4].flow.ingress_node_id
connect route_arbiter.io.in[4].bits.flow.ingress_node, states[4].flow.ingress_node
connect route_arbiter.io.in[4].bits.flow.vnet_id, states[4].flow.vnet_id
connect route_arbiter.io.in[4].bits.src_virt_id, UInt<3>(0h4)
node _T_12 = and(route_arbiter.io.in[4].ready, route_arbiter.io.in[4].valid)
when _T_12 :
connect states[4].g, UInt<3>(0h2)
node _route_arbiter_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h1))
connect route_arbiter.io.in[5].valid, _route_arbiter_io_in_5_valid_T
connect route_arbiter.io.in[5].bits.flow.egress_node_id, states[5].flow.egress_node_id
connect route_arbiter.io.in[5].bits.flow.egress_node, states[5].flow.egress_node
connect route_arbiter.io.in[5].bits.flow.ingress_node_id, states[5].flow.ingress_node_id
connect route_arbiter.io.in[5].bits.flow.ingress_node, states[5].flow.ingress_node
connect route_arbiter.io.in[5].bits.flow.vnet_id, states[5].flow.vnet_id
connect route_arbiter.io.in[5].bits.src_virt_id, UInt<3>(0h5)
node _T_13 = and(route_arbiter.io.in[5].ready, route_arbiter.io.in[5].valid)
when _T_13 :
connect states[5].g, UInt<3>(0h2)
node _route_arbiter_io_in_6_valid_T = eq(states[6].g, UInt<3>(0h1))
connect route_arbiter.io.in[6].valid, _route_arbiter_io_in_6_valid_T
connect route_arbiter.io.in[6].bits.flow.egress_node_id, states[6].flow.egress_node_id
connect route_arbiter.io.in[6].bits.flow.egress_node, states[6].flow.egress_node
connect route_arbiter.io.in[6].bits.flow.ingress_node_id, states[6].flow.ingress_node_id
connect route_arbiter.io.in[6].bits.flow.ingress_node, states[6].flow.ingress_node
connect route_arbiter.io.in[6].bits.flow.vnet_id, states[6].flow.vnet_id
connect route_arbiter.io.in[6].bits.src_virt_id, UInt<3>(0h6)
node _T_14 = and(route_arbiter.io.in[6].ready, route_arbiter.io.in[6].valid)
when _T_14 :
connect states[6].g, UInt<3>(0h2)
node _route_arbiter_io_in_7_valid_T = eq(states[7].g, UInt<3>(0h1))
connect route_arbiter.io.in[7].valid, _route_arbiter_io_in_7_valid_T
connect route_arbiter.io.in[7].bits.flow.egress_node_id, states[7].flow.egress_node_id
connect route_arbiter.io.in[7].bits.flow.egress_node, states[7].flow.egress_node
connect route_arbiter.io.in[7].bits.flow.ingress_node_id, states[7].flow.ingress_node_id
connect route_arbiter.io.in[7].bits.flow.ingress_node, states[7].flow.ingress_node
connect route_arbiter.io.in[7].bits.flow.vnet_id, states[7].flow.vnet_id
connect route_arbiter.io.in[7].bits.src_virt_id, UInt<3>(0h7)
node _T_15 = and(route_arbiter.io.in[7].ready, route_arbiter.io.in[7].valid)
when _T_15 :
connect states[7].g, UInt<3>(0h2)
node _T_16 = and(io.router_req.ready, io.router_req.valid)
when _T_16 :
node _T_17 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1))
node _T_18 = asUInt(reset)
node _T_19 = eq(_T_18, UInt<1>(0h0))
when _T_19 :
node _T_20 = eq(_T_17, UInt<1>(0h0))
when _T_20 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2
assert(clock, _T_17, UInt<1>(0h1), "") : assert_2
connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2)
node _T_21 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id)
when _T_21 :
connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[0].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_22 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id)
when _T_22 :
connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[1].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_23 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id)
when _T_23 :
connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[2].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[2].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_24 = eq(UInt<2>(0h3), io.router_req.bits.src_virt_id)
when _T_24 :
connect states[3].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[3].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[3].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[3].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_25 = eq(UInt<3>(0h4), io.router_req.bits.src_virt_id)
when _T_25 :
connect states[4].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[4].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[4].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[4].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_26 = eq(UInt<3>(0h5), io.router_req.bits.src_virt_id)
when _T_26 :
connect states[5].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[5].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[5].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[5].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_27 = eq(UInt<3>(0h6), io.router_req.bits.src_virt_id)
when _T_27 :
connect states[6].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[6].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[6].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[6].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_28 = eq(UInt<3>(0h7), io.router_req.bits.src_virt_id)
when _T_28 :
connect states[7].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[7].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[7].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[7].vc_sel.`3`, io.router_resp.vc_sel.`3`
regreset mask : UInt<8>, clock, reset, UInt<8>(0h0)
wire vcalloc_reqs : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}}[8]
wire vcalloc_vals : UInt<1>[8]
node vcalloc_filter_lo_lo = cat(vcalloc_vals[1], vcalloc_vals[0])
node vcalloc_filter_lo_hi = cat(vcalloc_vals[3], vcalloc_vals[2])
node vcalloc_filter_lo = cat(vcalloc_filter_lo_hi, vcalloc_filter_lo_lo)
node vcalloc_filter_hi_lo = cat(vcalloc_vals[5], vcalloc_vals[4])
node vcalloc_filter_hi_hi = cat(vcalloc_vals[7], vcalloc_vals[6])
node vcalloc_filter_hi = cat(vcalloc_filter_hi_hi, vcalloc_filter_hi_lo)
node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_filter_lo)
node vcalloc_filter_lo_lo_1 = cat(vcalloc_vals[1], vcalloc_vals[0])
node vcalloc_filter_lo_hi_1 = cat(vcalloc_vals[3], vcalloc_vals[2])
node vcalloc_filter_lo_1 = cat(vcalloc_filter_lo_hi_1, vcalloc_filter_lo_lo_1)
node vcalloc_filter_hi_lo_1 = cat(vcalloc_vals[5], vcalloc_vals[4])
node vcalloc_filter_hi_hi_1 = cat(vcalloc_vals[7], vcalloc_vals[6])
node vcalloc_filter_hi_1 = cat(vcalloc_filter_hi_hi_1, vcalloc_filter_hi_lo_1)
node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_filter_lo_1)
node _vcalloc_filter_T_2 = not(mask)
node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2)
node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3)
node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0)
node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1)
node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2)
node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3)
node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4)
node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5)
node _vcalloc_filter_T_11 = bits(_vcalloc_filter_T_4, 6, 6)
node _vcalloc_filter_T_12 = bits(_vcalloc_filter_T_4, 7, 7)
node _vcalloc_filter_T_13 = bits(_vcalloc_filter_T_4, 8, 8)
node _vcalloc_filter_T_14 = bits(_vcalloc_filter_T_4, 9, 9)
node _vcalloc_filter_T_15 = bits(_vcalloc_filter_T_4, 10, 10)
node _vcalloc_filter_T_16 = bits(_vcalloc_filter_T_4, 11, 11)
node _vcalloc_filter_T_17 = bits(_vcalloc_filter_T_4, 12, 12)
node _vcalloc_filter_T_18 = bits(_vcalloc_filter_T_4, 13, 13)
node _vcalloc_filter_T_19 = bits(_vcalloc_filter_T_4, 14, 14)
node _vcalloc_filter_T_20 = bits(_vcalloc_filter_T_4, 15, 15)
node _vcalloc_filter_T_21 = mux(_vcalloc_filter_T_20, UInt<16>(0h8000), UInt<16>(0h0))
node _vcalloc_filter_T_22 = mux(_vcalloc_filter_T_19, UInt<16>(0h4000), _vcalloc_filter_T_21)
node _vcalloc_filter_T_23 = mux(_vcalloc_filter_T_18, UInt<16>(0h2000), _vcalloc_filter_T_22)
node _vcalloc_filter_T_24 = mux(_vcalloc_filter_T_17, UInt<16>(0h1000), _vcalloc_filter_T_23)
node _vcalloc_filter_T_25 = mux(_vcalloc_filter_T_16, UInt<16>(0h800), _vcalloc_filter_T_24)
node _vcalloc_filter_T_26 = mux(_vcalloc_filter_T_15, UInt<16>(0h400), _vcalloc_filter_T_25)
node _vcalloc_filter_T_27 = mux(_vcalloc_filter_T_14, UInt<16>(0h200), _vcalloc_filter_T_26)
node _vcalloc_filter_T_28 = mux(_vcalloc_filter_T_13, UInt<16>(0h100), _vcalloc_filter_T_27)
node _vcalloc_filter_T_29 = mux(_vcalloc_filter_T_12, UInt<16>(0h80), _vcalloc_filter_T_28)
node _vcalloc_filter_T_30 = mux(_vcalloc_filter_T_11, UInt<16>(0h40), _vcalloc_filter_T_29)
node _vcalloc_filter_T_31 = mux(_vcalloc_filter_T_10, UInt<16>(0h20), _vcalloc_filter_T_30)
node _vcalloc_filter_T_32 = mux(_vcalloc_filter_T_9, UInt<16>(0h10), _vcalloc_filter_T_31)
node _vcalloc_filter_T_33 = mux(_vcalloc_filter_T_8, UInt<16>(0h8), _vcalloc_filter_T_32)
node _vcalloc_filter_T_34 = mux(_vcalloc_filter_T_7, UInt<16>(0h4), _vcalloc_filter_T_33)
node _vcalloc_filter_T_35 = mux(_vcalloc_filter_T_6, UInt<16>(0h2), _vcalloc_filter_T_34)
node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<16>(0h1), _vcalloc_filter_T_35)
node _vcalloc_sel_T = bits(vcalloc_filter, 7, 0)
node _vcalloc_sel_T_1 = shr(vcalloc_filter, 8)
node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1)
node _T_29 = and(io.router_req.ready, io.router_req.valid)
when _T_29 :
node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id)
node _mask_T_1 = sub(_mask_T, UInt<1>(0h1))
node _mask_T_2 = tail(_mask_T_1, 1)
connect mask, _mask_T_2
else :
node _T_30 = or(vcalloc_vals[0], vcalloc_vals[1])
node _T_31 = or(_T_30, vcalloc_vals[2])
node _T_32 = or(_T_31, vcalloc_vals[3])
node _T_33 = or(_T_32, vcalloc_vals[4])
node _T_34 = or(_T_33, vcalloc_vals[5])
node _T_35 = or(_T_34, vcalloc_vals[6])
node _T_36 = or(_T_35, vcalloc_vals[7])
when _T_36 :
node _mask_T_3 = not(UInt<1>(0h0))
node _mask_T_4 = not(UInt<2>(0h0))
node _mask_T_5 = not(UInt<3>(0h0))
node _mask_T_6 = not(UInt<4>(0h0))
node _mask_T_7 = not(UInt<5>(0h0))
node _mask_T_8 = not(UInt<6>(0h0))
node _mask_T_9 = not(UInt<7>(0h0))
node _mask_T_10 = not(UInt<8>(0h0))
node _mask_T_11 = bits(vcalloc_sel, 0, 0)
node _mask_T_12 = bits(vcalloc_sel, 1, 1)
node _mask_T_13 = bits(vcalloc_sel, 2, 2)
node _mask_T_14 = bits(vcalloc_sel, 3, 3)
node _mask_T_15 = bits(vcalloc_sel, 4, 4)
node _mask_T_16 = bits(vcalloc_sel, 5, 5)
node _mask_T_17 = bits(vcalloc_sel, 6, 6)
node _mask_T_18 = bits(vcalloc_sel, 7, 7)
node _mask_T_19 = mux(_mask_T_11, _mask_T_3, UInt<1>(0h0))
node _mask_T_20 = mux(_mask_T_12, _mask_T_4, UInt<1>(0h0))
node _mask_T_21 = mux(_mask_T_13, _mask_T_5, UInt<1>(0h0))
node _mask_T_22 = mux(_mask_T_14, _mask_T_6, UInt<1>(0h0))
node _mask_T_23 = mux(_mask_T_15, _mask_T_7, UInt<1>(0h0))
node _mask_T_24 = mux(_mask_T_16, _mask_T_8, UInt<1>(0h0))
node _mask_T_25 = mux(_mask_T_17, _mask_T_9, UInt<1>(0h0))
node _mask_T_26 = mux(_mask_T_18, _mask_T_10, UInt<1>(0h0))
node _mask_T_27 = or(_mask_T_19, _mask_T_20)
node _mask_T_28 = or(_mask_T_27, _mask_T_21)
node _mask_T_29 = or(_mask_T_28, _mask_T_22)
node _mask_T_30 = or(_mask_T_29, _mask_T_23)
node _mask_T_31 = or(_mask_T_30, _mask_T_24)
node _mask_T_32 = or(_mask_T_31, _mask_T_25)
node _mask_T_33 = or(_mask_T_32, _mask_T_26)
wire _mask_WIRE : UInt<8>
connect _mask_WIRE, _mask_T_33
connect mask, _mask_WIRE
node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1])
node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2])
node _io_vcalloc_req_valid_T_2 = or(_io_vcalloc_req_valid_T_1, vcalloc_vals[3])
node _io_vcalloc_req_valid_T_3 = or(_io_vcalloc_req_valid_T_2, vcalloc_vals[4])
node _io_vcalloc_req_valid_T_4 = or(_io_vcalloc_req_valid_T_3, vcalloc_vals[5])
node _io_vcalloc_req_valid_T_5 = or(_io_vcalloc_req_valid_T_4, vcalloc_vals[6])
node _io_vcalloc_req_valid_T_6 = or(_io_vcalloc_req_valid_T_5, vcalloc_vals[7])
connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_6
node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0)
node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1)
node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2)
node _io_vcalloc_req_bits_T_3 = bits(vcalloc_sel, 3, 3)
node _io_vcalloc_req_bits_T_4 = bits(vcalloc_sel, 4, 4)
node _io_vcalloc_req_bits_T_5 = bits(vcalloc_sel, 5, 5)
node _io_vcalloc_req_bits_T_6 = bits(vcalloc_sel, 6, 6)
node _io_vcalloc_req_bits_T_7 = bits(vcalloc_sel, 7, 7)
wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}}
wire _io_vcalloc_req_bits_WIRE_1 : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}
wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[8]
node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_10 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_11 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_12 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_13 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_16 = or(_io_vcalloc_req_bits_T_8, _io_vcalloc_req_bits_T_9)
node _io_vcalloc_req_bits_T_17 = or(_io_vcalloc_req_bits_T_16, _io_vcalloc_req_bits_T_10)
node _io_vcalloc_req_bits_T_18 = or(_io_vcalloc_req_bits_T_17, _io_vcalloc_req_bits_T_11)
node _io_vcalloc_req_bits_T_19 = or(_io_vcalloc_req_bits_T_18, _io_vcalloc_req_bits_T_12)
node _io_vcalloc_req_bits_T_20 = or(_io_vcalloc_req_bits_T_19, _io_vcalloc_req_bits_T_13)
node _io_vcalloc_req_bits_T_21 = or(_io_vcalloc_req_bits_T_20, _io_vcalloc_req_bits_T_14)
node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_21, _io_vcalloc_req_bits_T_15)
wire _io_vcalloc_req_bits_WIRE_3 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_22
connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3
node _io_vcalloc_req_bits_T_23 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_24 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_25 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_26 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_27 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_28 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_31 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_24)
node _io_vcalloc_req_bits_T_32 = or(_io_vcalloc_req_bits_T_31, _io_vcalloc_req_bits_T_25)
node _io_vcalloc_req_bits_T_33 = or(_io_vcalloc_req_bits_T_32, _io_vcalloc_req_bits_T_26)
node _io_vcalloc_req_bits_T_34 = or(_io_vcalloc_req_bits_T_33, _io_vcalloc_req_bits_T_27)
node _io_vcalloc_req_bits_T_35 = or(_io_vcalloc_req_bits_T_34, _io_vcalloc_req_bits_T_28)
node _io_vcalloc_req_bits_T_36 = or(_io_vcalloc_req_bits_T_35, _io_vcalloc_req_bits_T_29)
node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_36, _io_vcalloc_req_bits_T_30)
wire _io_vcalloc_req_bits_WIRE_4 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_37
connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4
node _io_vcalloc_req_bits_T_38 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_39 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_40 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_41 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_42 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_43 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_44 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_45 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_38, _io_vcalloc_req_bits_T_39)
node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_40)
node _io_vcalloc_req_bits_T_48 = or(_io_vcalloc_req_bits_T_47, _io_vcalloc_req_bits_T_41)
node _io_vcalloc_req_bits_T_49 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_42)
node _io_vcalloc_req_bits_T_50 = or(_io_vcalloc_req_bits_T_49, _io_vcalloc_req_bits_T_43)
node _io_vcalloc_req_bits_T_51 = or(_io_vcalloc_req_bits_T_50, _io_vcalloc_req_bits_T_44)
node _io_vcalloc_req_bits_T_52 = or(_io_vcalloc_req_bits_T_51, _io_vcalloc_req_bits_T_45)
wire _io_vcalloc_req_bits_WIRE_5 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_52
connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5
node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_55 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_56 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_57 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_58 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_59 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_60 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_61 = or(_io_vcalloc_req_bits_T_53, _io_vcalloc_req_bits_T_54)
node _io_vcalloc_req_bits_T_62 = or(_io_vcalloc_req_bits_T_61, _io_vcalloc_req_bits_T_55)
node _io_vcalloc_req_bits_T_63 = or(_io_vcalloc_req_bits_T_62, _io_vcalloc_req_bits_T_56)
node _io_vcalloc_req_bits_T_64 = or(_io_vcalloc_req_bits_T_63, _io_vcalloc_req_bits_T_57)
node _io_vcalloc_req_bits_T_65 = or(_io_vcalloc_req_bits_T_64, _io_vcalloc_req_bits_T_58)
node _io_vcalloc_req_bits_T_66 = or(_io_vcalloc_req_bits_T_65, _io_vcalloc_req_bits_T_59)
node _io_vcalloc_req_bits_T_67 = or(_io_vcalloc_req_bits_T_66, _io_vcalloc_req_bits_T_60)
wire _io_vcalloc_req_bits_WIRE_6 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_6, _io_vcalloc_req_bits_T_67
connect _io_vcalloc_req_bits_WIRE_2[3], _io_vcalloc_req_bits_WIRE_6
node _io_vcalloc_req_bits_T_68 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_69 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_70 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_71 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_72 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_73 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_74 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_75 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_76 = or(_io_vcalloc_req_bits_T_68, _io_vcalloc_req_bits_T_69)
node _io_vcalloc_req_bits_T_77 = or(_io_vcalloc_req_bits_T_76, _io_vcalloc_req_bits_T_70)
node _io_vcalloc_req_bits_T_78 = or(_io_vcalloc_req_bits_T_77, _io_vcalloc_req_bits_T_71)
node _io_vcalloc_req_bits_T_79 = or(_io_vcalloc_req_bits_T_78, _io_vcalloc_req_bits_T_72)
node _io_vcalloc_req_bits_T_80 = or(_io_vcalloc_req_bits_T_79, _io_vcalloc_req_bits_T_73)
node _io_vcalloc_req_bits_T_81 = or(_io_vcalloc_req_bits_T_80, _io_vcalloc_req_bits_T_74)
node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_81, _io_vcalloc_req_bits_T_75)
wire _io_vcalloc_req_bits_WIRE_7 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_82
connect _io_vcalloc_req_bits_WIRE_2[4], _io_vcalloc_req_bits_WIRE_7
node _io_vcalloc_req_bits_T_83 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_84 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_85 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_86 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_87 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_88 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_89 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_90 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_91 = or(_io_vcalloc_req_bits_T_83, _io_vcalloc_req_bits_T_84)
node _io_vcalloc_req_bits_T_92 = or(_io_vcalloc_req_bits_T_91, _io_vcalloc_req_bits_T_85)
node _io_vcalloc_req_bits_T_93 = or(_io_vcalloc_req_bits_T_92, _io_vcalloc_req_bits_T_86)
node _io_vcalloc_req_bits_T_94 = or(_io_vcalloc_req_bits_T_93, _io_vcalloc_req_bits_T_87)
node _io_vcalloc_req_bits_T_95 = or(_io_vcalloc_req_bits_T_94, _io_vcalloc_req_bits_T_88)
node _io_vcalloc_req_bits_T_96 = or(_io_vcalloc_req_bits_T_95, _io_vcalloc_req_bits_T_89)
node _io_vcalloc_req_bits_T_97 = or(_io_vcalloc_req_bits_T_96, _io_vcalloc_req_bits_T_90)
wire _io_vcalloc_req_bits_WIRE_8 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_8, _io_vcalloc_req_bits_T_97
connect _io_vcalloc_req_bits_WIRE_2[5], _io_vcalloc_req_bits_WIRE_8
node _io_vcalloc_req_bits_T_98 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_99 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_100 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_101 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_102 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_103 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_104 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_105 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_106 = or(_io_vcalloc_req_bits_T_98, _io_vcalloc_req_bits_T_99)
node _io_vcalloc_req_bits_T_107 = or(_io_vcalloc_req_bits_T_106, _io_vcalloc_req_bits_T_100)
node _io_vcalloc_req_bits_T_108 = or(_io_vcalloc_req_bits_T_107, _io_vcalloc_req_bits_T_101)
node _io_vcalloc_req_bits_T_109 = or(_io_vcalloc_req_bits_T_108, _io_vcalloc_req_bits_T_102)
node _io_vcalloc_req_bits_T_110 = or(_io_vcalloc_req_bits_T_109, _io_vcalloc_req_bits_T_103)
node _io_vcalloc_req_bits_T_111 = or(_io_vcalloc_req_bits_T_110, _io_vcalloc_req_bits_T_104)
node _io_vcalloc_req_bits_T_112 = or(_io_vcalloc_req_bits_T_111, _io_vcalloc_req_bits_T_105)
wire _io_vcalloc_req_bits_WIRE_9 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_112
connect _io_vcalloc_req_bits_WIRE_2[6], _io_vcalloc_req_bits_WIRE_9
node _io_vcalloc_req_bits_T_113 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_114 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_115 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_116 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_117 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_118 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_119 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_120 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_121 = or(_io_vcalloc_req_bits_T_113, _io_vcalloc_req_bits_T_114)
node _io_vcalloc_req_bits_T_122 = or(_io_vcalloc_req_bits_T_121, _io_vcalloc_req_bits_T_115)
node _io_vcalloc_req_bits_T_123 = or(_io_vcalloc_req_bits_T_122, _io_vcalloc_req_bits_T_116)
node _io_vcalloc_req_bits_T_124 = or(_io_vcalloc_req_bits_T_123, _io_vcalloc_req_bits_T_117)
node _io_vcalloc_req_bits_T_125 = or(_io_vcalloc_req_bits_T_124, _io_vcalloc_req_bits_T_118)
node _io_vcalloc_req_bits_T_126 = or(_io_vcalloc_req_bits_T_125, _io_vcalloc_req_bits_T_119)
node _io_vcalloc_req_bits_T_127 = or(_io_vcalloc_req_bits_T_126, _io_vcalloc_req_bits_T_120)
wire _io_vcalloc_req_bits_WIRE_10 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_10, _io_vcalloc_req_bits_T_127
connect _io_vcalloc_req_bits_WIRE_2[7], _io_vcalloc_req_bits_WIRE_10
connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2
wire _io_vcalloc_req_bits_WIRE_11 : UInt<1>[1]
node _io_vcalloc_req_bits_T_128 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_129 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_130 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_131 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_132 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_133 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_134 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_135 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_136 = or(_io_vcalloc_req_bits_T_128, _io_vcalloc_req_bits_T_129)
node _io_vcalloc_req_bits_T_137 = or(_io_vcalloc_req_bits_T_136, _io_vcalloc_req_bits_T_130)
node _io_vcalloc_req_bits_T_138 = or(_io_vcalloc_req_bits_T_137, _io_vcalloc_req_bits_T_131)
node _io_vcalloc_req_bits_T_139 = or(_io_vcalloc_req_bits_T_138, _io_vcalloc_req_bits_T_132)
node _io_vcalloc_req_bits_T_140 = or(_io_vcalloc_req_bits_T_139, _io_vcalloc_req_bits_T_133)
node _io_vcalloc_req_bits_T_141 = or(_io_vcalloc_req_bits_T_140, _io_vcalloc_req_bits_T_134)
node _io_vcalloc_req_bits_T_142 = or(_io_vcalloc_req_bits_T_141, _io_vcalloc_req_bits_T_135)
wire _io_vcalloc_req_bits_WIRE_12 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_142
connect _io_vcalloc_req_bits_WIRE_11[0], _io_vcalloc_req_bits_WIRE_12
connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_11
wire _io_vcalloc_req_bits_WIRE_13 : UInt<1>[1]
node _io_vcalloc_req_bits_T_143 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_144 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_145 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_146 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_147 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_148 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_149 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_150 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_151 = or(_io_vcalloc_req_bits_T_143, _io_vcalloc_req_bits_T_144)
node _io_vcalloc_req_bits_T_152 = or(_io_vcalloc_req_bits_T_151, _io_vcalloc_req_bits_T_145)
node _io_vcalloc_req_bits_T_153 = or(_io_vcalloc_req_bits_T_152, _io_vcalloc_req_bits_T_146)
node _io_vcalloc_req_bits_T_154 = or(_io_vcalloc_req_bits_T_153, _io_vcalloc_req_bits_T_147)
node _io_vcalloc_req_bits_T_155 = or(_io_vcalloc_req_bits_T_154, _io_vcalloc_req_bits_T_148)
node _io_vcalloc_req_bits_T_156 = or(_io_vcalloc_req_bits_T_155, _io_vcalloc_req_bits_T_149)
node _io_vcalloc_req_bits_T_157 = or(_io_vcalloc_req_bits_T_156, _io_vcalloc_req_bits_T_150)
wire _io_vcalloc_req_bits_WIRE_14 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_14, _io_vcalloc_req_bits_T_157
connect _io_vcalloc_req_bits_WIRE_13[0], _io_vcalloc_req_bits_WIRE_14
connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_13
wire _io_vcalloc_req_bits_WIRE_15 : UInt<1>[1]
node _io_vcalloc_req_bits_T_158 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_159 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_160 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_161 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_162 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_163 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_164 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_165 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_166 = or(_io_vcalloc_req_bits_T_158, _io_vcalloc_req_bits_T_159)
node _io_vcalloc_req_bits_T_167 = or(_io_vcalloc_req_bits_T_166, _io_vcalloc_req_bits_T_160)
node _io_vcalloc_req_bits_T_168 = or(_io_vcalloc_req_bits_T_167, _io_vcalloc_req_bits_T_161)
node _io_vcalloc_req_bits_T_169 = or(_io_vcalloc_req_bits_T_168, _io_vcalloc_req_bits_T_162)
node _io_vcalloc_req_bits_T_170 = or(_io_vcalloc_req_bits_T_169, _io_vcalloc_req_bits_T_163)
node _io_vcalloc_req_bits_T_171 = or(_io_vcalloc_req_bits_T_170, _io_vcalloc_req_bits_T_164)
node _io_vcalloc_req_bits_T_172 = or(_io_vcalloc_req_bits_T_171, _io_vcalloc_req_bits_T_165)
wire _io_vcalloc_req_bits_WIRE_16 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_172
connect _io_vcalloc_req_bits_WIRE_15[0], _io_vcalloc_req_bits_WIRE_16
connect _io_vcalloc_req_bits_WIRE_1.`3`, _io_vcalloc_req_bits_WIRE_15
connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1
node _io_vcalloc_req_bits_T_173 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_174 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_175 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_176 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_177 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_178 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_179 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_180 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_181 = or(_io_vcalloc_req_bits_T_173, _io_vcalloc_req_bits_T_174)
node _io_vcalloc_req_bits_T_182 = or(_io_vcalloc_req_bits_T_181, _io_vcalloc_req_bits_T_175)
node _io_vcalloc_req_bits_T_183 = or(_io_vcalloc_req_bits_T_182, _io_vcalloc_req_bits_T_176)
node _io_vcalloc_req_bits_T_184 = or(_io_vcalloc_req_bits_T_183, _io_vcalloc_req_bits_T_177)
node _io_vcalloc_req_bits_T_185 = or(_io_vcalloc_req_bits_T_184, _io_vcalloc_req_bits_T_178)
node _io_vcalloc_req_bits_T_186 = or(_io_vcalloc_req_bits_T_185, _io_vcalloc_req_bits_T_179)
node _io_vcalloc_req_bits_T_187 = or(_io_vcalloc_req_bits_T_186, _io_vcalloc_req_bits_T_180)
wire _io_vcalloc_req_bits_WIRE_17 : UInt<3>
connect _io_vcalloc_req_bits_WIRE_17, _io_vcalloc_req_bits_T_187
connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_17
wire _io_vcalloc_req_bits_WIRE_18 : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}
node _io_vcalloc_req_bits_T_188 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_189 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_190 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_191 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_192 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_193 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_194 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_195 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_196 = or(_io_vcalloc_req_bits_T_188, _io_vcalloc_req_bits_T_189)
node _io_vcalloc_req_bits_T_197 = or(_io_vcalloc_req_bits_T_196, _io_vcalloc_req_bits_T_190)
node _io_vcalloc_req_bits_T_198 = or(_io_vcalloc_req_bits_T_197, _io_vcalloc_req_bits_T_191)
node _io_vcalloc_req_bits_T_199 = or(_io_vcalloc_req_bits_T_198, _io_vcalloc_req_bits_T_192)
node _io_vcalloc_req_bits_T_200 = or(_io_vcalloc_req_bits_T_199, _io_vcalloc_req_bits_T_193)
node _io_vcalloc_req_bits_T_201 = or(_io_vcalloc_req_bits_T_200, _io_vcalloc_req_bits_T_194)
node _io_vcalloc_req_bits_T_202 = or(_io_vcalloc_req_bits_T_201, _io_vcalloc_req_bits_T_195)
wire _io_vcalloc_req_bits_WIRE_19 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_202
connect _io_vcalloc_req_bits_WIRE_18.egress_node_id, _io_vcalloc_req_bits_WIRE_19
node _io_vcalloc_req_bits_T_203 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_204 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_205 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_206 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_207 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_208 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_209 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_210 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_211 = or(_io_vcalloc_req_bits_T_203, _io_vcalloc_req_bits_T_204)
node _io_vcalloc_req_bits_T_212 = or(_io_vcalloc_req_bits_T_211, _io_vcalloc_req_bits_T_205)
node _io_vcalloc_req_bits_T_213 = or(_io_vcalloc_req_bits_T_212, _io_vcalloc_req_bits_T_206)
node _io_vcalloc_req_bits_T_214 = or(_io_vcalloc_req_bits_T_213, _io_vcalloc_req_bits_T_207)
node _io_vcalloc_req_bits_T_215 = or(_io_vcalloc_req_bits_T_214, _io_vcalloc_req_bits_T_208)
node _io_vcalloc_req_bits_T_216 = or(_io_vcalloc_req_bits_T_215, _io_vcalloc_req_bits_T_209)
node _io_vcalloc_req_bits_T_217 = or(_io_vcalloc_req_bits_T_216, _io_vcalloc_req_bits_T_210)
wire _io_vcalloc_req_bits_WIRE_20 : UInt<5>
connect _io_vcalloc_req_bits_WIRE_20, _io_vcalloc_req_bits_T_217
connect _io_vcalloc_req_bits_WIRE_18.egress_node, _io_vcalloc_req_bits_WIRE_20
node _io_vcalloc_req_bits_T_218 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_219 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_220 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_221 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_222 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_223 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_224 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_225 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_226 = or(_io_vcalloc_req_bits_T_218, _io_vcalloc_req_bits_T_219)
node _io_vcalloc_req_bits_T_227 = or(_io_vcalloc_req_bits_T_226, _io_vcalloc_req_bits_T_220)
node _io_vcalloc_req_bits_T_228 = or(_io_vcalloc_req_bits_T_227, _io_vcalloc_req_bits_T_221)
node _io_vcalloc_req_bits_T_229 = or(_io_vcalloc_req_bits_T_228, _io_vcalloc_req_bits_T_222)
node _io_vcalloc_req_bits_T_230 = or(_io_vcalloc_req_bits_T_229, _io_vcalloc_req_bits_T_223)
node _io_vcalloc_req_bits_T_231 = or(_io_vcalloc_req_bits_T_230, _io_vcalloc_req_bits_T_224)
node _io_vcalloc_req_bits_T_232 = or(_io_vcalloc_req_bits_T_231, _io_vcalloc_req_bits_T_225)
wire _io_vcalloc_req_bits_WIRE_21 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_21, _io_vcalloc_req_bits_T_232
connect _io_vcalloc_req_bits_WIRE_18.ingress_node_id, _io_vcalloc_req_bits_WIRE_21
node _io_vcalloc_req_bits_T_233 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_234 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_235 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_236 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_237 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_238 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_239 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_240 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_241 = or(_io_vcalloc_req_bits_T_233, _io_vcalloc_req_bits_T_234)
node _io_vcalloc_req_bits_T_242 = or(_io_vcalloc_req_bits_T_241, _io_vcalloc_req_bits_T_235)
node _io_vcalloc_req_bits_T_243 = or(_io_vcalloc_req_bits_T_242, _io_vcalloc_req_bits_T_236)
node _io_vcalloc_req_bits_T_244 = or(_io_vcalloc_req_bits_T_243, _io_vcalloc_req_bits_T_237)
node _io_vcalloc_req_bits_T_245 = or(_io_vcalloc_req_bits_T_244, _io_vcalloc_req_bits_T_238)
node _io_vcalloc_req_bits_T_246 = or(_io_vcalloc_req_bits_T_245, _io_vcalloc_req_bits_T_239)
node _io_vcalloc_req_bits_T_247 = or(_io_vcalloc_req_bits_T_246, _io_vcalloc_req_bits_T_240)
wire _io_vcalloc_req_bits_WIRE_22 : UInt<5>
connect _io_vcalloc_req_bits_WIRE_22, _io_vcalloc_req_bits_T_247
connect _io_vcalloc_req_bits_WIRE_18.ingress_node, _io_vcalloc_req_bits_WIRE_22
node _io_vcalloc_req_bits_T_248 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_249 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_250 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_251 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_252 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_253 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_254 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_255 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_256 = or(_io_vcalloc_req_bits_T_248, _io_vcalloc_req_bits_T_249)
node _io_vcalloc_req_bits_T_257 = or(_io_vcalloc_req_bits_T_256, _io_vcalloc_req_bits_T_250)
node _io_vcalloc_req_bits_T_258 = or(_io_vcalloc_req_bits_T_257, _io_vcalloc_req_bits_T_251)
node _io_vcalloc_req_bits_T_259 = or(_io_vcalloc_req_bits_T_258, _io_vcalloc_req_bits_T_252)
node _io_vcalloc_req_bits_T_260 = or(_io_vcalloc_req_bits_T_259, _io_vcalloc_req_bits_T_253)
node _io_vcalloc_req_bits_T_261 = or(_io_vcalloc_req_bits_T_260, _io_vcalloc_req_bits_T_254)
node _io_vcalloc_req_bits_T_262 = or(_io_vcalloc_req_bits_T_261, _io_vcalloc_req_bits_T_255)
wire _io_vcalloc_req_bits_WIRE_23 : UInt<3>
connect _io_vcalloc_req_bits_WIRE_23, _io_vcalloc_req_bits_T_262
connect _io_vcalloc_req_bits_WIRE_18.vnet_id, _io_vcalloc_req_bits_WIRE_23
connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_18
connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE
connect vcalloc_vals[0], UInt<1>(0h0)
invalidate vcalloc_reqs[0].vc_sel.`0`[0]
invalidate vcalloc_reqs[0].vc_sel.`0`[1]
invalidate vcalloc_reqs[0].vc_sel.`0`[2]
invalidate vcalloc_reqs[0].vc_sel.`0`[3]
invalidate vcalloc_reqs[0].vc_sel.`0`[4]
invalidate vcalloc_reqs[0].vc_sel.`0`[5]
invalidate vcalloc_reqs[0].vc_sel.`0`[6]
invalidate vcalloc_reqs[0].vc_sel.`0`[7]
invalidate vcalloc_reqs[0].vc_sel.`1`[0]
invalidate vcalloc_reqs[0].vc_sel.`2`[0]
invalidate vcalloc_reqs[0].vc_sel.`3`[0]
invalidate vcalloc_reqs[0].in_vc
invalidate vcalloc_reqs[0].flow.egress_node_id
invalidate vcalloc_reqs[0].flow.egress_node
invalidate vcalloc_reqs[0].flow.ingress_node_id
invalidate vcalloc_reqs[0].flow.ingress_node
invalidate vcalloc_reqs[0].flow.vnet_id
connect vcalloc_vals[1], UInt<1>(0h0)
invalidate vcalloc_reqs[1].vc_sel.`0`[0]
invalidate vcalloc_reqs[1].vc_sel.`0`[1]
invalidate vcalloc_reqs[1].vc_sel.`0`[2]
invalidate vcalloc_reqs[1].vc_sel.`0`[3]
invalidate vcalloc_reqs[1].vc_sel.`0`[4]
invalidate vcalloc_reqs[1].vc_sel.`0`[5]
invalidate vcalloc_reqs[1].vc_sel.`0`[6]
invalidate vcalloc_reqs[1].vc_sel.`0`[7]
invalidate vcalloc_reqs[1].vc_sel.`1`[0]
invalidate vcalloc_reqs[1].vc_sel.`2`[0]
invalidate vcalloc_reqs[1].vc_sel.`3`[0]
invalidate vcalloc_reqs[1].in_vc
invalidate vcalloc_reqs[1].flow.egress_node_id
invalidate vcalloc_reqs[1].flow.egress_node
invalidate vcalloc_reqs[1].flow.ingress_node_id
invalidate vcalloc_reqs[1].flow.ingress_node
invalidate vcalloc_reqs[1].flow.vnet_id
connect vcalloc_vals[2], UInt<1>(0h0)
invalidate vcalloc_reqs[2].vc_sel.`0`[0]
invalidate vcalloc_reqs[2].vc_sel.`0`[1]
invalidate vcalloc_reqs[2].vc_sel.`0`[2]
invalidate vcalloc_reqs[2].vc_sel.`0`[3]
invalidate vcalloc_reqs[2].vc_sel.`0`[4]
invalidate vcalloc_reqs[2].vc_sel.`0`[5]
invalidate vcalloc_reqs[2].vc_sel.`0`[6]
invalidate vcalloc_reqs[2].vc_sel.`0`[7]
invalidate vcalloc_reqs[2].vc_sel.`1`[0]
invalidate vcalloc_reqs[2].vc_sel.`2`[0]
invalidate vcalloc_reqs[2].vc_sel.`3`[0]
invalidate vcalloc_reqs[2].in_vc
invalidate vcalloc_reqs[2].flow.egress_node_id
invalidate vcalloc_reqs[2].flow.egress_node
invalidate vcalloc_reqs[2].flow.ingress_node_id
invalidate vcalloc_reqs[2].flow.ingress_node
invalidate vcalloc_reqs[2].flow.vnet_id
connect vcalloc_vals[3], UInt<1>(0h0)
invalidate vcalloc_reqs[3].vc_sel.`0`[0]
invalidate vcalloc_reqs[3].vc_sel.`0`[1]
invalidate vcalloc_reqs[3].vc_sel.`0`[2]
invalidate vcalloc_reqs[3].vc_sel.`0`[3]
invalidate vcalloc_reqs[3].vc_sel.`0`[4]
invalidate vcalloc_reqs[3].vc_sel.`0`[5]
invalidate vcalloc_reqs[3].vc_sel.`0`[6]
invalidate vcalloc_reqs[3].vc_sel.`0`[7]
invalidate vcalloc_reqs[3].vc_sel.`1`[0]
invalidate vcalloc_reqs[3].vc_sel.`2`[0]
invalidate vcalloc_reqs[3].vc_sel.`3`[0]
invalidate vcalloc_reqs[3].in_vc
invalidate vcalloc_reqs[3].flow.egress_node_id
invalidate vcalloc_reqs[3].flow.egress_node
invalidate vcalloc_reqs[3].flow.ingress_node_id
invalidate vcalloc_reqs[3].flow.ingress_node
invalidate vcalloc_reqs[3].flow.vnet_id
node _vcalloc_vals_4_T = eq(states[4].g, UInt<3>(0h2))
node _vcalloc_vals_4_T_1 = eq(states[4].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_4_T_2 = and(_vcalloc_vals_4_T, _vcalloc_vals_4_T_1)
connect vcalloc_vals[4], _vcalloc_vals_4_T_2
connect vcalloc_reqs[4].in_vc, UInt<3>(0h4)
connect vcalloc_reqs[4].vc_sel.`0`, states[4].vc_sel.`0`
connect vcalloc_reqs[4].vc_sel.`1`, states[4].vc_sel.`1`
connect vcalloc_reqs[4].vc_sel.`2`, states[4].vc_sel.`2`
connect vcalloc_reqs[4].vc_sel.`3`, states[4].vc_sel.`3`
connect vcalloc_reqs[4].flow, states[4].flow
node _T_37 = bits(vcalloc_sel, 4, 4)
node _T_38 = and(vcalloc_vals[4], _T_37)
node _T_39 = and(_T_38, io.vcalloc_req.ready)
when _T_39 :
connect states[4].g, UInt<3>(0h3)
node _vcalloc_vals_5_T = eq(states[5].g, UInt<3>(0h2))
node _vcalloc_vals_5_T_1 = eq(states[5].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_5_T_2 = and(_vcalloc_vals_5_T, _vcalloc_vals_5_T_1)
connect vcalloc_vals[5], _vcalloc_vals_5_T_2
connect vcalloc_reqs[5].in_vc, UInt<3>(0h5)
connect vcalloc_reqs[5].vc_sel.`0`, states[5].vc_sel.`0`
connect vcalloc_reqs[5].vc_sel.`1`, states[5].vc_sel.`1`
connect vcalloc_reqs[5].vc_sel.`2`, states[5].vc_sel.`2`
connect vcalloc_reqs[5].vc_sel.`3`, states[5].vc_sel.`3`
connect vcalloc_reqs[5].flow, states[5].flow
node _T_40 = bits(vcalloc_sel, 5, 5)
node _T_41 = and(vcalloc_vals[5], _T_40)
node _T_42 = and(_T_41, io.vcalloc_req.ready)
when _T_42 :
connect states[5].g, UInt<3>(0h3)
node _vcalloc_vals_6_T = eq(states[6].g, UInt<3>(0h2))
node _vcalloc_vals_6_T_1 = eq(states[6].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_6_T_2 = and(_vcalloc_vals_6_T, _vcalloc_vals_6_T_1)
connect vcalloc_vals[6], _vcalloc_vals_6_T_2
connect vcalloc_reqs[6].in_vc, UInt<3>(0h6)
connect vcalloc_reqs[6].vc_sel.`0`, states[6].vc_sel.`0`
connect vcalloc_reqs[6].vc_sel.`1`, states[6].vc_sel.`1`
connect vcalloc_reqs[6].vc_sel.`2`, states[6].vc_sel.`2`
connect vcalloc_reqs[6].vc_sel.`3`, states[6].vc_sel.`3`
connect vcalloc_reqs[6].flow, states[6].flow
node _T_43 = bits(vcalloc_sel, 6, 6)
node _T_44 = and(vcalloc_vals[6], _T_43)
node _T_45 = and(_T_44, io.vcalloc_req.ready)
when _T_45 :
connect states[6].g, UInt<3>(0h3)
node _vcalloc_vals_7_T = eq(states[7].g, UInt<3>(0h2))
node _vcalloc_vals_7_T_1 = eq(states[7].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_7_T_2 = and(_vcalloc_vals_7_T, _vcalloc_vals_7_T_1)
connect vcalloc_vals[7], _vcalloc_vals_7_T_2
connect vcalloc_reqs[7].in_vc, UInt<3>(0h7)
connect vcalloc_reqs[7].vc_sel.`0`, states[7].vc_sel.`0`
connect vcalloc_reqs[7].vc_sel.`1`, states[7].vc_sel.`1`
connect vcalloc_reqs[7].vc_sel.`2`, states[7].vc_sel.`2`
connect vcalloc_reqs[7].vc_sel.`3`, states[7].vc_sel.`3`
connect vcalloc_reqs[7].flow, states[7].flow
node _T_46 = bits(vcalloc_sel, 7, 7)
node _T_47 = and(vcalloc_vals[7], _T_46)
node _T_48 = and(_T_47, io.vcalloc_req.ready)
when _T_48 :
connect states[7].g, UInt<3>(0h3)
node _io_debug_va_stall_T = add(vcalloc_vals[0], vcalloc_vals[1])
node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0)
node _io_debug_va_stall_T_2 = add(vcalloc_vals[2], vcalloc_vals[3])
node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0)
node _io_debug_va_stall_T_4 = add(_io_debug_va_stall_T_1, _io_debug_va_stall_T_3)
node _io_debug_va_stall_T_5 = bits(_io_debug_va_stall_T_4, 2, 0)
node _io_debug_va_stall_T_6 = add(vcalloc_vals[4], vcalloc_vals[5])
node _io_debug_va_stall_T_7 = bits(_io_debug_va_stall_T_6, 1, 0)
node _io_debug_va_stall_T_8 = add(vcalloc_vals[6], vcalloc_vals[7])
node _io_debug_va_stall_T_9 = bits(_io_debug_va_stall_T_8, 1, 0)
node _io_debug_va_stall_T_10 = add(_io_debug_va_stall_T_7, _io_debug_va_stall_T_9)
node _io_debug_va_stall_T_11 = bits(_io_debug_va_stall_T_10, 2, 0)
node _io_debug_va_stall_T_12 = add(_io_debug_va_stall_T_5, _io_debug_va_stall_T_11)
node _io_debug_va_stall_T_13 = bits(_io_debug_va_stall_T_12, 3, 0)
node _io_debug_va_stall_T_14 = sub(_io_debug_va_stall_T_13, io.vcalloc_req.ready)
node _io_debug_va_stall_T_15 = tail(_io_debug_va_stall_T_14, 1)
connect io.debug.va_stall, _io_debug_va_stall_T_15
node _T_49 = and(io.vcalloc_req.ready, io.vcalloc_req.valid)
when _T_49 :
node _T_50 = bits(vcalloc_sel, 0, 0)
when _T_50 :
connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[0].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[0].g, UInt<3>(0h3)
node _T_51 = eq(states[0].g, UInt<3>(0h2))
node _T_52 = asUInt(reset)
node _T_53 = eq(_T_52, UInt<1>(0h0))
when _T_53 :
node _T_54 = eq(_T_51, UInt<1>(0h0))
when _T_54 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_3
assert(clock, _T_51, UInt<1>(0h1), "") : assert_3
node _T_55 = bits(vcalloc_sel, 1, 1)
when _T_55 :
connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[1].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[1].g, UInt<3>(0h3)
node _T_56 = eq(states[1].g, UInt<3>(0h2))
node _T_57 = asUInt(reset)
node _T_58 = eq(_T_57, UInt<1>(0h0))
when _T_58 :
node _T_59 = eq(_T_56, UInt<1>(0h0))
when _T_59 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_4
assert(clock, _T_56, UInt<1>(0h1), "") : assert_4
node _T_60 = bits(vcalloc_sel, 2, 2)
when _T_60 :
connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[2].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[2].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[2].g, UInt<3>(0h3)
node _T_61 = eq(states[2].g, UInt<3>(0h2))
node _T_62 = asUInt(reset)
node _T_63 = eq(_T_62, UInt<1>(0h0))
when _T_63 :
node _T_64 = eq(_T_61, UInt<1>(0h0))
when _T_64 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_5
assert(clock, _T_61, UInt<1>(0h1), "") : assert_5
node _T_65 = bits(vcalloc_sel, 3, 3)
when _T_65 :
connect states[3].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[3].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[3].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[3].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[3].g, UInt<3>(0h3)
node _T_66 = eq(states[3].g, UInt<3>(0h2))
node _T_67 = asUInt(reset)
node _T_68 = eq(_T_67, UInt<1>(0h0))
when _T_68 :
node _T_69 = eq(_T_66, UInt<1>(0h0))
when _T_69 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_6
assert(clock, _T_66, UInt<1>(0h1), "") : assert_6
node _T_70 = bits(vcalloc_sel, 4, 4)
when _T_70 :
connect states[4].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[4].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[4].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[4].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[4].g, UInt<3>(0h3)
node _T_71 = eq(states[4].g, UInt<3>(0h2))
node _T_72 = asUInt(reset)
node _T_73 = eq(_T_72, UInt<1>(0h0))
when _T_73 :
node _T_74 = eq(_T_71, UInt<1>(0h0))
when _T_74 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_7
assert(clock, _T_71, UInt<1>(0h1), "") : assert_7
node _T_75 = bits(vcalloc_sel, 5, 5)
when _T_75 :
connect states[5].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[5].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[5].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[5].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[5].g, UInt<3>(0h3)
node _T_76 = eq(states[5].g, UInt<3>(0h2))
node _T_77 = asUInt(reset)
node _T_78 = eq(_T_77, UInt<1>(0h0))
when _T_78 :
node _T_79 = eq(_T_76, UInt<1>(0h0))
when _T_79 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_8
assert(clock, _T_76, UInt<1>(0h1), "") : assert_8
node _T_80 = bits(vcalloc_sel, 6, 6)
when _T_80 :
connect states[6].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[6].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[6].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[6].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[6].g, UInt<3>(0h3)
node _T_81 = eq(states[6].g, UInt<3>(0h2))
node _T_82 = asUInt(reset)
node _T_83 = eq(_T_82, UInt<1>(0h0))
when _T_83 :
node _T_84 = eq(_T_81, UInt<1>(0h0))
when _T_84 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_9
assert(clock, _T_81, UInt<1>(0h1), "") : assert_9
node _T_85 = bits(vcalloc_sel, 7, 7)
when _T_85 :
connect states[7].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[7].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[7].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[7].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[7].g, UInt<3>(0h3)
node _T_86 = eq(states[7].g, UInt<3>(0h2))
node _T_87 = asUInt(reset)
node _T_88 = eq(_T_87, UInt<1>(0h0))
when _T_88 :
node _T_89 = eq(_T_86, UInt<1>(0h0))
when _T_89 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_10
assert(clock, _T_86, UInt<1>(0h1), "") : assert_10
inst salloc_arb of SwitchArbiter_12
connect salloc_arb.clock, clock
connect salloc_arb.reset, reset
connect salloc_arb.io.in[0].valid, UInt<1>(0h0)
invalidate salloc_arb.io.in[0].bits.tail
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[0]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[1]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[2]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[3]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[4]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[5]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[6]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[7]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[0]
invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[0]
invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[0]
connect salloc_arb.io.in[1].valid, UInt<1>(0h0)
invalidate salloc_arb.io.in[1].bits.tail
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[0]
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[1]
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[2]
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[3]
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[4]
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[5]
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[6]
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[7]
invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[0]
invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[0]
invalidate salloc_arb.io.in[1].bits.vc_sel.`3`[0]
connect salloc_arb.io.in[2].valid, UInt<1>(0h0)
invalidate salloc_arb.io.in[2].bits.tail
invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[0]
invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[1]
invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[2]
invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[3]
invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[4]
invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[5]
invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[6]
invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[7]
invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[0]
invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[0]
invalidate salloc_arb.io.in[2].bits.vc_sel.`3`[0]
connect salloc_arb.io.in[3].valid, UInt<1>(0h0)
invalidate salloc_arb.io.in[3].bits.tail
invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[0]
invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[1]
invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[2]
invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[3]
invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[4]
invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[5]
invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[6]
invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[7]
invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[0]
invalidate salloc_arb.io.in[3].bits.vc_sel.`2`[0]
invalidate salloc_arb.io.in[3].bits.vc_sel.`3`[0]
node credit_available_lo_lo = cat(states[4].vc_sel.`0`[1], states[4].vc_sel.`0`[0])
node credit_available_lo_hi = cat(states[4].vc_sel.`0`[3], states[4].vc_sel.`0`[2])
node credit_available_lo = cat(credit_available_lo_hi, credit_available_lo_lo)
node credit_available_hi_lo = cat(states[4].vc_sel.`0`[5], states[4].vc_sel.`0`[4])
node credit_available_hi_hi = cat(states[4].vc_sel.`0`[7], states[4].vc_sel.`0`[6])
node credit_available_hi = cat(credit_available_hi_hi, credit_available_hi_lo)
node _credit_available_T = cat(credit_available_hi, credit_available_lo)
node credit_available_lo_1 = cat(states[4].vc_sel.`1`[0], _credit_available_T)
node credit_available_hi_1 = cat(states[4].vc_sel.`3`[0], states[4].vc_sel.`2`[0])
node _credit_available_T_1 = cat(credit_available_hi_1, credit_available_lo_1)
node credit_available_lo_lo_1 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_1 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_2 = cat(credit_available_lo_hi_1, credit_available_lo_lo_1)
node credit_available_hi_lo_1 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_1 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_2 = cat(credit_available_hi_hi_1, credit_available_hi_lo_1)
node _credit_available_T_2 = cat(credit_available_hi_2, credit_available_lo_2)
node credit_available_lo_3 = cat(io.out_credit_available.`1`[0], _credit_available_T_2)
node credit_available_hi_3 = cat(io.out_credit_available.`3`[0], io.out_credit_available.`2`[0])
node _credit_available_T_3 = cat(credit_available_hi_3, credit_available_lo_3)
node _credit_available_T_4 = and(_credit_available_T_1, _credit_available_T_3)
node credit_available = neq(_credit_available_T_4, UInt<1>(0h0))
node _salloc_arb_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h3))
node _salloc_arb_io_in_4_valid_T_1 = and(_salloc_arb_io_in_4_valid_T, credit_available)
node _salloc_arb_io_in_4_valid_T_2 = and(_salloc_arb_io_in_4_valid_T_1, input_buffer.io.deq[4].valid)
connect salloc_arb.io.in[4].valid, _salloc_arb_io_in_4_valid_T_2
connect salloc_arb.io.in[4].bits.vc_sel.`0`[0], states[4].vc_sel.`0`[0]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[1], states[4].vc_sel.`0`[1]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[2], states[4].vc_sel.`0`[2]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[3], states[4].vc_sel.`0`[3]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[4], states[4].vc_sel.`0`[4]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[5], states[4].vc_sel.`0`[5]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[6], states[4].vc_sel.`0`[6]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[7], states[4].vc_sel.`0`[7]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[0], states[4].vc_sel.`1`[0]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[0], states[4].vc_sel.`2`[0]
connect salloc_arb.io.in[4].bits.vc_sel.`3`[0], states[4].vc_sel.`3`[0]
connect salloc_arb.io.in[4].bits.tail, input_buffer.io.deq[4].bits.tail
node _T_90 = and(salloc_arb.io.in[4].ready, salloc_arb.io.in[4].valid)
node _T_91 = and(_T_90, input_buffer.io.deq[4].bits.tail)
when _T_91 :
connect states[4].g, UInt<3>(0h0)
connect input_buffer.io.deq[4].ready, salloc_arb.io.in[4].ready
node credit_available_lo_lo_2 = cat(states[5].vc_sel.`0`[1], states[5].vc_sel.`0`[0])
node credit_available_lo_hi_2 = cat(states[5].vc_sel.`0`[3], states[5].vc_sel.`0`[2])
node credit_available_lo_4 = cat(credit_available_lo_hi_2, credit_available_lo_lo_2)
node credit_available_hi_lo_2 = cat(states[5].vc_sel.`0`[5], states[5].vc_sel.`0`[4])
node credit_available_hi_hi_2 = cat(states[5].vc_sel.`0`[7], states[5].vc_sel.`0`[6])
node credit_available_hi_4 = cat(credit_available_hi_hi_2, credit_available_hi_lo_2)
node _credit_available_T_5 = cat(credit_available_hi_4, credit_available_lo_4)
node credit_available_lo_5 = cat(states[5].vc_sel.`1`[0], _credit_available_T_5)
node credit_available_hi_5 = cat(states[5].vc_sel.`3`[0], states[5].vc_sel.`2`[0])
node _credit_available_T_6 = cat(credit_available_hi_5, credit_available_lo_5)
node credit_available_lo_lo_3 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_3 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_6 = cat(credit_available_lo_hi_3, credit_available_lo_lo_3)
node credit_available_hi_lo_3 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_3 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_6 = cat(credit_available_hi_hi_3, credit_available_hi_lo_3)
node _credit_available_T_7 = cat(credit_available_hi_6, credit_available_lo_6)
node credit_available_lo_7 = cat(io.out_credit_available.`1`[0], _credit_available_T_7)
node credit_available_hi_7 = cat(io.out_credit_available.`3`[0], io.out_credit_available.`2`[0])
node _credit_available_T_8 = cat(credit_available_hi_7, credit_available_lo_7)
node _credit_available_T_9 = and(_credit_available_T_6, _credit_available_T_8)
node credit_available_1 = neq(_credit_available_T_9, UInt<1>(0h0))
node _salloc_arb_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h3))
node _salloc_arb_io_in_5_valid_T_1 = and(_salloc_arb_io_in_5_valid_T, credit_available_1)
node _salloc_arb_io_in_5_valid_T_2 = and(_salloc_arb_io_in_5_valid_T_1, input_buffer.io.deq[5].valid)
connect salloc_arb.io.in[5].valid, _salloc_arb_io_in_5_valid_T_2
connect salloc_arb.io.in[5].bits.vc_sel.`0`[0], states[5].vc_sel.`0`[0]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[1], states[5].vc_sel.`0`[1]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[2], states[5].vc_sel.`0`[2]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[3], states[5].vc_sel.`0`[3]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[4], states[5].vc_sel.`0`[4]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[5], states[5].vc_sel.`0`[5]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[6], states[5].vc_sel.`0`[6]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[7], states[5].vc_sel.`0`[7]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[0], states[5].vc_sel.`1`[0]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[0], states[5].vc_sel.`2`[0]
connect salloc_arb.io.in[5].bits.vc_sel.`3`[0], states[5].vc_sel.`3`[0]
connect salloc_arb.io.in[5].bits.tail, input_buffer.io.deq[5].bits.tail
node _T_92 = and(salloc_arb.io.in[5].ready, salloc_arb.io.in[5].valid)
node _T_93 = and(_T_92, input_buffer.io.deq[5].bits.tail)
when _T_93 :
connect states[5].g, UInt<3>(0h0)
connect input_buffer.io.deq[5].ready, salloc_arb.io.in[5].ready
node credit_available_lo_lo_4 = cat(states[6].vc_sel.`0`[1], states[6].vc_sel.`0`[0])
node credit_available_lo_hi_4 = cat(states[6].vc_sel.`0`[3], states[6].vc_sel.`0`[2])
node credit_available_lo_8 = cat(credit_available_lo_hi_4, credit_available_lo_lo_4)
node credit_available_hi_lo_4 = cat(states[6].vc_sel.`0`[5], states[6].vc_sel.`0`[4])
node credit_available_hi_hi_4 = cat(states[6].vc_sel.`0`[7], states[6].vc_sel.`0`[6])
node credit_available_hi_8 = cat(credit_available_hi_hi_4, credit_available_hi_lo_4)
node _credit_available_T_10 = cat(credit_available_hi_8, credit_available_lo_8)
node credit_available_lo_9 = cat(states[6].vc_sel.`1`[0], _credit_available_T_10)
node credit_available_hi_9 = cat(states[6].vc_sel.`3`[0], states[6].vc_sel.`2`[0])
node _credit_available_T_11 = cat(credit_available_hi_9, credit_available_lo_9)
node credit_available_lo_lo_5 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_5 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_10 = cat(credit_available_lo_hi_5, credit_available_lo_lo_5)
node credit_available_hi_lo_5 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_5 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_10 = cat(credit_available_hi_hi_5, credit_available_hi_lo_5)
node _credit_available_T_12 = cat(credit_available_hi_10, credit_available_lo_10)
node credit_available_lo_11 = cat(io.out_credit_available.`1`[0], _credit_available_T_12)
node credit_available_hi_11 = cat(io.out_credit_available.`3`[0], io.out_credit_available.`2`[0])
node _credit_available_T_13 = cat(credit_available_hi_11, credit_available_lo_11)
node _credit_available_T_14 = and(_credit_available_T_11, _credit_available_T_13)
node credit_available_2 = neq(_credit_available_T_14, UInt<1>(0h0))
node _salloc_arb_io_in_6_valid_T = eq(states[6].g, UInt<3>(0h3))
node _salloc_arb_io_in_6_valid_T_1 = and(_salloc_arb_io_in_6_valid_T, credit_available_2)
node _salloc_arb_io_in_6_valid_T_2 = and(_salloc_arb_io_in_6_valid_T_1, input_buffer.io.deq[6].valid)
connect salloc_arb.io.in[6].valid, _salloc_arb_io_in_6_valid_T_2
connect salloc_arb.io.in[6].bits.vc_sel.`0`[0], states[6].vc_sel.`0`[0]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[1], states[6].vc_sel.`0`[1]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[2], states[6].vc_sel.`0`[2]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[3], states[6].vc_sel.`0`[3]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[4], states[6].vc_sel.`0`[4]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[5], states[6].vc_sel.`0`[5]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[6], states[6].vc_sel.`0`[6]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[7], states[6].vc_sel.`0`[7]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[0], states[6].vc_sel.`1`[0]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[0], states[6].vc_sel.`2`[0]
connect salloc_arb.io.in[6].bits.vc_sel.`3`[0], states[6].vc_sel.`3`[0]
connect salloc_arb.io.in[6].bits.tail, input_buffer.io.deq[6].bits.tail
node _T_94 = and(salloc_arb.io.in[6].ready, salloc_arb.io.in[6].valid)
node _T_95 = and(_T_94, input_buffer.io.deq[6].bits.tail)
when _T_95 :
connect states[6].g, UInt<3>(0h0)
connect input_buffer.io.deq[6].ready, salloc_arb.io.in[6].ready
node credit_available_lo_lo_6 = cat(states[7].vc_sel.`0`[1], states[7].vc_sel.`0`[0])
node credit_available_lo_hi_6 = cat(states[7].vc_sel.`0`[3], states[7].vc_sel.`0`[2])
node credit_available_lo_12 = cat(credit_available_lo_hi_6, credit_available_lo_lo_6)
node credit_available_hi_lo_6 = cat(states[7].vc_sel.`0`[5], states[7].vc_sel.`0`[4])
node credit_available_hi_hi_6 = cat(states[7].vc_sel.`0`[7], states[7].vc_sel.`0`[6])
node credit_available_hi_12 = cat(credit_available_hi_hi_6, credit_available_hi_lo_6)
node _credit_available_T_15 = cat(credit_available_hi_12, credit_available_lo_12)
node credit_available_lo_13 = cat(states[7].vc_sel.`1`[0], _credit_available_T_15)
node credit_available_hi_13 = cat(states[7].vc_sel.`3`[0], states[7].vc_sel.`2`[0])
node _credit_available_T_16 = cat(credit_available_hi_13, credit_available_lo_13)
node credit_available_lo_lo_7 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_7 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_14 = cat(credit_available_lo_hi_7, credit_available_lo_lo_7)
node credit_available_hi_lo_7 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_7 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_14 = cat(credit_available_hi_hi_7, credit_available_hi_lo_7)
node _credit_available_T_17 = cat(credit_available_hi_14, credit_available_lo_14)
node credit_available_lo_15 = cat(io.out_credit_available.`1`[0], _credit_available_T_17)
node credit_available_hi_15 = cat(io.out_credit_available.`3`[0], io.out_credit_available.`2`[0])
node _credit_available_T_18 = cat(credit_available_hi_15, credit_available_lo_15)
node _credit_available_T_19 = and(_credit_available_T_16, _credit_available_T_18)
node credit_available_3 = neq(_credit_available_T_19, UInt<1>(0h0))
node _salloc_arb_io_in_7_valid_T = eq(states[7].g, UInt<3>(0h3))
node _salloc_arb_io_in_7_valid_T_1 = and(_salloc_arb_io_in_7_valid_T, credit_available_3)
node _salloc_arb_io_in_7_valid_T_2 = and(_salloc_arb_io_in_7_valid_T_1, input_buffer.io.deq[7].valid)
connect salloc_arb.io.in[7].valid, _salloc_arb_io_in_7_valid_T_2
connect salloc_arb.io.in[7].bits.vc_sel.`0`[0], states[7].vc_sel.`0`[0]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[1], states[7].vc_sel.`0`[1]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[2], states[7].vc_sel.`0`[2]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[3], states[7].vc_sel.`0`[3]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[4], states[7].vc_sel.`0`[4]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[5], states[7].vc_sel.`0`[5]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[6], states[7].vc_sel.`0`[6]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[7], states[7].vc_sel.`0`[7]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[0], states[7].vc_sel.`1`[0]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[0], states[7].vc_sel.`2`[0]
connect salloc_arb.io.in[7].bits.vc_sel.`3`[0], states[7].vc_sel.`3`[0]
connect salloc_arb.io.in[7].bits.tail, input_buffer.io.deq[7].bits.tail
node _T_96 = and(salloc_arb.io.in[7].ready, salloc_arb.io.in[7].valid)
node _T_97 = and(_T_96, input_buffer.io.deq[7].bits.tail)
when _T_97 :
connect states[7].g, UInt<3>(0h0)
connect input_buffer.io.deq[7].ready, salloc_arb.io.in[7].ready
node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T)
node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2)
node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4)
node _io_debug_sa_stall_T_6 = eq(salloc_arb.io.in[3].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_7 = and(salloc_arb.io.in[3].valid, _io_debug_sa_stall_T_6)
node _io_debug_sa_stall_T_8 = eq(salloc_arb.io.in[4].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_9 = and(salloc_arb.io.in[4].valid, _io_debug_sa_stall_T_8)
node _io_debug_sa_stall_T_10 = eq(salloc_arb.io.in[5].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_11 = and(salloc_arb.io.in[5].valid, _io_debug_sa_stall_T_10)
node _io_debug_sa_stall_T_12 = eq(salloc_arb.io.in[6].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_13 = and(salloc_arb.io.in[6].valid, _io_debug_sa_stall_T_12)
node _io_debug_sa_stall_T_14 = eq(salloc_arb.io.in[7].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_15 = and(salloc_arb.io.in[7].valid, _io_debug_sa_stall_T_14)
node _io_debug_sa_stall_T_16 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_3)
node _io_debug_sa_stall_T_17 = bits(_io_debug_sa_stall_T_16, 1, 0)
node _io_debug_sa_stall_T_18 = add(_io_debug_sa_stall_T_5, _io_debug_sa_stall_T_7)
node _io_debug_sa_stall_T_19 = bits(_io_debug_sa_stall_T_18, 1, 0)
node _io_debug_sa_stall_T_20 = add(_io_debug_sa_stall_T_17, _io_debug_sa_stall_T_19)
node _io_debug_sa_stall_T_21 = bits(_io_debug_sa_stall_T_20, 2, 0)
node _io_debug_sa_stall_T_22 = add(_io_debug_sa_stall_T_9, _io_debug_sa_stall_T_11)
node _io_debug_sa_stall_T_23 = bits(_io_debug_sa_stall_T_22, 1, 0)
node _io_debug_sa_stall_T_24 = add(_io_debug_sa_stall_T_13, _io_debug_sa_stall_T_15)
node _io_debug_sa_stall_T_25 = bits(_io_debug_sa_stall_T_24, 1, 0)
node _io_debug_sa_stall_T_26 = add(_io_debug_sa_stall_T_23, _io_debug_sa_stall_T_25)
node _io_debug_sa_stall_T_27 = bits(_io_debug_sa_stall_T_26, 2, 0)
node _io_debug_sa_stall_T_28 = add(_io_debug_sa_stall_T_21, _io_debug_sa_stall_T_27)
node _io_debug_sa_stall_T_29 = bits(_io_debug_sa_stall_T_28, 3, 0)
connect io.debug.sa_stall, _io_debug_sa_stall_T_29
connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits
connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid
connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready
when io.block :
connect salloc_arb.io.out[0].ready, UInt<1>(0h0)
connect io.salloc_req[0].valid, UInt<1>(0h0)
reg salloc_outs : { valid : UInt<1>, vid : UInt<3>, out_vid : UInt<3>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], clock
node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0))
connect io.in.credit_return, _io_in_credit_return_T_1
node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _io_in_vc_free_T_4 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _io_in_vc_free_T_5 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _io_in_vc_free_T_6 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _io_in_vc_free_T_7 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _io_in_vc_free_T_8 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
node _io_in_vc_free_T_9 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_10 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_11 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_12 = mux(_io_in_vc_free_T_4, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_13 = mux(_io_in_vc_free_T_5, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_14 = mux(_io_in_vc_free_T_6, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_15 = mux(_io_in_vc_free_T_7, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_16 = mux(_io_in_vc_free_T_8, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_17 = or(_io_in_vc_free_T_9, _io_in_vc_free_T_10)
node _io_in_vc_free_T_18 = or(_io_in_vc_free_T_17, _io_in_vc_free_T_11)
node _io_in_vc_free_T_19 = or(_io_in_vc_free_T_18, _io_in_vc_free_T_12)
node _io_in_vc_free_T_20 = or(_io_in_vc_free_T_19, _io_in_vc_free_T_13)
node _io_in_vc_free_T_21 = or(_io_in_vc_free_T_20, _io_in_vc_free_T_14)
node _io_in_vc_free_T_22 = or(_io_in_vc_free_T_21, _io_in_vc_free_T_15)
node _io_in_vc_free_T_23 = or(_io_in_vc_free_T_22, _io_in_vc_free_T_16)
wire _io_in_vc_free_WIRE : UInt<1>
connect _io_in_vc_free_WIRE, _io_in_vc_free_T_23
node _io_in_vc_free_T_24 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE)
node _io_in_vc_free_T_25 = mux(_io_in_vc_free_T_24, salloc_arb.io.chosen_oh[0], UInt<1>(0h0))
connect io.in.vc_free, _io_in_vc_free_T_25
node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
connect salloc_outs[0].valid, _salloc_outs_0_valid_T
node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 7, 4)
node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 3, 0)
node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi)
node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo)
node salloc_outs_0_vid_hi_1 = bits(_salloc_outs_0_vid_T_1, 3, 2)
node salloc_outs_0_vid_lo_1 = bits(_salloc_outs_0_vid_T_1, 1, 0)
node _salloc_outs_0_vid_T_2 = orr(salloc_outs_0_vid_hi_1)
node _salloc_outs_0_vid_T_3 = or(salloc_outs_0_vid_hi_1, salloc_outs_0_vid_lo_1)
node _salloc_outs_0_vid_T_4 = bits(_salloc_outs_0_vid_T_3, 1, 1)
node _salloc_outs_0_vid_T_5 = cat(_salloc_outs_0_vid_T_2, _salloc_outs_0_vid_T_4)
node _salloc_outs_0_vid_T_6 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_5)
connect salloc_outs[0].vid, _salloc_outs_0_vid_T_6
node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _vc_sel_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _vc_sel_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _vc_sel_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _vc_sel_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _vc_sel_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
wire vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}
wire _vc_sel_WIRE : UInt<1>[8]
node _vc_sel_T_8 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_9 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_10 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_11 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_12 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_13 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_14 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_15 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_16 = or(_vc_sel_T_8, _vc_sel_T_9)
node _vc_sel_T_17 = or(_vc_sel_T_16, _vc_sel_T_10)
node _vc_sel_T_18 = or(_vc_sel_T_17, _vc_sel_T_11)
node _vc_sel_T_19 = or(_vc_sel_T_18, _vc_sel_T_12)
node _vc_sel_T_20 = or(_vc_sel_T_19, _vc_sel_T_13)
node _vc_sel_T_21 = or(_vc_sel_T_20, _vc_sel_T_14)
node _vc_sel_T_22 = or(_vc_sel_T_21, _vc_sel_T_15)
wire _vc_sel_WIRE_1 : UInt<1>
connect _vc_sel_WIRE_1, _vc_sel_T_22
connect _vc_sel_WIRE[0], _vc_sel_WIRE_1
node _vc_sel_T_23 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_24 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_25 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_26 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_27 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_28 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_29 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_30 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_31 = or(_vc_sel_T_23, _vc_sel_T_24)
node _vc_sel_T_32 = or(_vc_sel_T_31, _vc_sel_T_25)
node _vc_sel_T_33 = or(_vc_sel_T_32, _vc_sel_T_26)
node _vc_sel_T_34 = or(_vc_sel_T_33, _vc_sel_T_27)
node _vc_sel_T_35 = or(_vc_sel_T_34, _vc_sel_T_28)
node _vc_sel_T_36 = or(_vc_sel_T_35, _vc_sel_T_29)
node _vc_sel_T_37 = or(_vc_sel_T_36, _vc_sel_T_30)
wire _vc_sel_WIRE_2 : UInt<1>
connect _vc_sel_WIRE_2, _vc_sel_T_37
connect _vc_sel_WIRE[1], _vc_sel_WIRE_2
node _vc_sel_T_38 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_39 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_40 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_41 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_42 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_43 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_44 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_45 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_46 = or(_vc_sel_T_38, _vc_sel_T_39)
node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_40)
node _vc_sel_T_48 = or(_vc_sel_T_47, _vc_sel_T_41)
node _vc_sel_T_49 = or(_vc_sel_T_48, _vc_sel_T_42)
node _vc_sel_T_50 = or(_vc_sel_T_49, _vc_sel_T_43)
node _vc_sel_T_51 = or(_vc_sel_T_50, _vc_sel_T_44)
node _vc_sel_T_52 = or(_vc_sel_T_51, _vc_sel_T_45)
wire _vc_sel_WIRE_3 : UInt<1>
connect _vc_sel_WIRE_3, _vc_sel_T_52
connect _vc_sel_WIRE[2], _vc_sel_WIRE_3
node _vc_sel_T_53 = mux(_vc_sel_T, states[0].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_54 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_55 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_56 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_57 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_58 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_59 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_60 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_61 = or(_vc_sel_T_53, _vc_sel_T_54)
node _vc_sel_T_62 = or(_vc_sel_T_61, _vc_sel_T_55)
node _vc_sel_T_63 = or(_vc_sel_T_62, _vc_sel_T_56)
node _vc_sel_T_64 = or(_vc_sel_T_63, _vc_sel_T_57)
node _vc_sel_T_65 = or(_vc_sel_T_64, _vc_sel_T_58)
node _vc_sel_T_66 = or(_vc_sel_T_65, _vc_sel_T_59)
node _vc_sel_T_67 = or(_vc_sel_T_66, _vc_sel_T_60)
wire _vc_sel_WIRE_4 : UInt<1>
connect _vc_sel_WIRE_4, _vc_sel_T_67
connect _vc_sel_WIRE[3], _vc_sel_WIRE_4
node _vc_sel_T_68 = mux(_vc_sel_T, states[0].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_69 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_70 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_71 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_72 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_73 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_74 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_75 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_76 = or(_vc_sel_T_68, _vc_sel_T_69)
node _vc_sel_T_77 = or(_vc_sel_T_76, _vc_sel_T_70)
node _vc_sel_T_78 = or(_vc_sel_T_77, _vc_sel_T_71)
node _vc_sel_T_79 = or(_vc_sel_T_78, _vc_sel_T_72)
node _vc_sel_T_80 = or(_vc_sel_T_79, _vc_sel_T_73)
node _vc_sel_T_81 = or(_vc_sel_T_80, _vc_sel_T_74)
node _vc_sel_T_82 = or(_vc_sel_T_81, _vc_sel_T_75)
wire _vc_sel_WIRE_5 : UInt<1>
connect _vc_sel_WIRE_5, _vc_sel_T_82
connect _vc_sel_WIRE[4], _vc_sel_WIRE_5
node _vc_sel_T_83 = mux(_vc_sel_T, states[0].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_84 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_85 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_86 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_87 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_88 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_89 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_90 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_91 = or(_vc_sel_T_83, _vc_sel_T_84)
node _vc_sel_T_92 = or(_vc_sel_T_91, _vc_sel_T_85)
node _vc_sel_T_93 = or(_vc_sel_T_92, _vc_sel_T_86)
node _vc_sel_T_94 = or(_vc_sel_T_93, _vc_sel_T_87)
node _vc_sel_T_95 = or(_vc_sel_T_94, _vc_sel_T_88)
node _vc_sel_T_96 = or(_vc_sel_T_95, _vc_sel_T_89)
node _vc_sel_T_97 = or(_vc_sel_T_96, _vc_sel_T_90)
wire _vc_sel_WIRE_6 : UInt<1>
connect _vc_sel_WIRE_6, _vc_sel_T_97
connect _vc_sel_WIRE[5], _vc_sel_WIRE_6
node _vc_sel_T_98 = mux(_vc_sel_T, states[0].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_99 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_100 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_101 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_102 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_103 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_104 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_105 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_106 = or(_vc_sel_T_98, _vc_sel_T_99)
node _vc_sel_T_107 = or(_vc_sel_T_106, _vc_sel_T_100)
node _vc_sel_T_108 = or(_vc_sel_T_107, _vc_sel_T_101)
node _vc_sel_T_109 = or(_vc_sel_T_108, _vc_sel_T_102)
node _vc_sel_T_110 = or(_vc_sel_T_109, _vc_sel_T_103)
node _vc_sel_T_111 = or(_vc_sel_T_110, _vc_sel_T_104)
node _vc_sel_T_112 = or(_vc_sel_T_111, _vc_sel_T_105)
wire _vc_sel_WIRE_7 : UInt<1>
connect _vc_sel_WIRE_7, _vc_sel_T_112
connect _vc_sel_WIRE[6], _vc_sel_WIRE_7
node _vc_sel_T_113 = mux(_vc_sel_T, states[0].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_114 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_115 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_116 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_117 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_118 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_119 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_120 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_121 = or(_vc_sel_T_113, _vc_sel_T_114)
node _vc_sel_T_122 = or(_vc_sel_T_121, _vc_sel_T_115)
node _vc_sel_T_123 = or(_vc_sel_T_122, _vc_sel_T_116)
node _vc_sel_T_124 = or(_vc_sel_T_123, _vc_sel_T_117)
node _vc_sel_T_125 = or(_vc_sel_T_124, _vc_sel_T_118)
node _vc_sel_T_126 = or(_vc_sel_T_125, _vc_sel_T_119)
node _vc_sel_T_127 = or(_vc_sel_T_126, _vc_sel_T_120)
wire _vc_sel_WIRE_8 : UInt<1>
connect _vc_sel_WIRE_8, _vc_sel_T_127
connect _vc_sel_WIRE[7], _vc_sel_WIRE_8
connect vc_sel.`0`, _vc_sel_WIRE
wire _vc_sel_WIRE_9 : UInt<1>[1]
node _vc_sel_T_128 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_129 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_130 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_131 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_132 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_133 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_134 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_135 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_136 = or(_vc_sel_T_128, _vc_sel_T_129)
node _vc_sel_T_137 = or(_vc_sel_T_136, _vc_sel_T_130)
node _vc_sel_T_138 = or(_vc_sel_T_137, _vc_sel_T_131)
node _vc_sel_T_139 = or(_vc_sel_T_138, _vc_sel_T_132)
node _vc_sel_T_140 = or(_vc_sel_T_139, _vc_sel_T_133)
node _vc_sel_T_141 = or(_vc_sel_T_140, _vc_sel_T_134)
node _vc_sel_T_142 = or(_vc_sel_T_141, _vc_sel_T_135)
wire _vc_sel_WIRE_10 : UInt<1>
connect _vc_sel_WIRE_10, _vc_sel_T_142
connect _vc_sel_WIRE_9[0], _vc_sel_WIRE_10
connect vc_sel.`1`, _vc_sel_WIRE_9
wire _vc_sel_WIRE_11 : UInt<1>[1]
node _vc_sel_T_143 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_144 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_145 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_146 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_147 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_148 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_149 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_150 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_151 = or(_vc_sel_T_143, _vc_sel_T_144)
node _vc_sel_T_152 = or(_vc_sel_T_151, _vc_sel_T_145)
node _vc_sel_T_153 = or(_vc_sel_T_152, _vc_sel_T_146)
node _vc_sel_T_154 = or(_vc_sel_T_153, _vc_sel_T_147)
node _vc_sel_T_155 = or(_vc_sel_T_154, _vc_sel_T_148)
node _vc_sel_T_156 = or(_vc_sel_T_155, _vc_sel_T_149)
node _vc_sel_T_157 = or(_vc_sel_T_156, _vc_sel_T_150)
wire _vc_sel_WIRE_12 : UInt<1>
connect _vc_sel_WIRE_12, _vc_sel_T_157
connect _vc_sel_WIRE_11[0], _vc_sel_WIRE_12
connect vc_sel.`2`, _vc_sel_WIRE_11
wire _vc_sel_WIRE_13 : UInt<1>[1]
node _vc_sel_T_158 = mux(_vc_sel_T, states[0].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_159 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_160 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_161 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_162 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_163 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_164 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_165 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_166 = or(_vc_sel_T_158, _vc_sel_T_159)
node _vc_sel_T_167 = or(_vc_sel_T_166, _vc_sel_T_160)
node _vc_sel_T_168 = or(_vc_sel_T_167, _vc_sel_T_161)
node _vc_sel_T_169 = or(_vc_sel_T_168, _vc_sel_T_162)
node _vc_sel_T_170 = or(_vc_sel_T_169, _vc_sel_T_163)
node _vc_sel_T_171 = or(_vc_sel_T_170, _vc_sel_T_164)
node _vc_sel_T_172 = or(_vc_sel_T_171, _vc_sel_T_165)
wire _vc_sel_WIRE_14 : UInt<1>
connect _vc_sel_WIRE_14, _vc_sel_T_172
connect _vc_sel_WIRE_13[0], _vc_sel_WIRE_14
connect vc_sel.`3`, _vc_sel_WIRE_13
node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1])
node _channel_oh_T_1 = or(_channel_oh_T, vc_sel.`0`[2])
node _channel_oh_T_2 = or(_channel_oh_T_1, vc_sel.`0`[3])
node _channel_oh_T_3 = or(_channel_oh_T_2, vc_sel.`0`[4])
node _channel_oh_T_4 = or(_channel_oh_T_3, vc_sel.`0`[5])
node _channel_oh_T_5 = or(_channel_oh_T_4, vc_sel.`0`[6])
node channel_oh_0 = or(_channel_oh_T_5, vc_sel.`0`[7])
node virt_channel_lo_lo = cat(vc_sel.`0`[1], vc_sel.`0`[0])
node virt_channel_lo_hi = cat(vc_sel.`0`[3], vc_sel.`0`[2])
node virt_channel_lo = cat(virt_channel_lo_hi, virt_channel_lo_lo)
node virt_channel_hi_lo = cat(vc_sel.`0`[5], vc_sel.`0`[4])
node virt_channel_hi_hi = cat(vc_sel.`0`[7], vc_sel.`0`[6])
node virt_channel_hi = cat(virt_channel_hi_hi, virt_channel_hi_lo)
node _virt_channel_T = cat(virt_channel_hi, virt_channel_lo)
node virt_channel_hi_1 = bits(_virt_channel_T, 7, 4)
node virt_channel_lo_1 = bits(_virt_channel_T, 3, 0)
node _virt_channel_T_1 = orr(virt_channel_hi_1)
node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo_1)
node virt_channel_hi_2 = bits(_virt_channel_T_2, 3, 2)
node virt_channel_lo_2 = bits(_virt_channel_T_2, 1, 0)
node _virt_channel_T_3 = orr(virt_channel_hi_2)
node _virt_channel_T_4 = or(virt_channel_hi_2, virt_channel_lo_2)
node _virt_channel_T_5 = bits(_virt_channel_T_4, 1, 1)
node _virt_channel_T_6 = cat(_virt_channel_T_3, _virt_channel_T_5)
node _virt_channel_T_7 = cat(_virt_channel_T_1, _virt_channel_T_6)
node _virt_channel_T_8 = mux(channel_oh_0, _virt_channel_T_7, UInt<1>(0h0))
node _virt_channel_T_9 = mux(vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0))
node _virt_channel_T_10 = mux(vc_sel.`2`[0], UInt<1>(0h0), UInt<1>(0h0))
node _virt_channel_T_11 = mux(vc_sel.`3`[0], UInt<1>(0h0), UInt<1>(0h0))
node _virt_channel_T_12 = or(_virt_channel_T_8, _virt_channel_T_9)
node _virt_channel_T_13 = or(_virt_channel_T_12, _virt_channel_T_10)
node _virt_channel_T_14 = or(_virt_channel_T_13, _virt_channel_T_11)
wire virt_channel : UInt<3>
connect virt_channel, _virt_channel_T_14
node _T_98 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
when _T_98 :
connect salloc_outs[0].out_vid, virt_channel
node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_payload_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_payload_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_payload_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _salloc_outs_0_flit_payload_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _salloc_outs_0_flit_payload_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
node _salloc_outs_0_flit_payload_T_8 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_9 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_10 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_11 = mux(_salloc_outs_0_flit_payload_T_3, input_buffer.io.deq[3].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_12 = mux(_salloc_outs_0_flit_payload_T_4, input_buffer.io.deq[4].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_13 = mux(_salloc_outs_0_flit_payload_T_5, input_buffer.io.deq[5].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_14 = mux(_salloc_outs_0_flit_payload_T_6, input_buffer.io.deq[6].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_15 = mux(_salloc_outs_0_flit_payload_T_7, input_buffer.io.deq[7].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_16 = or(_salloc_outs_0_flit_payload_T_8, _salloc_outs_0_flit_payload_T_9)
node _salloc_outs_0_flit_payload_T_17 = or(_salloc_outs_0_flit_payload_T_16, _salloc_outs_0_flit_payload_T_10)
node _salloc_outs_0_flit_payload_T_18 = or(_salloc_outs_0_flit_payload_T_17, _salloc_outs_0_flit_payload_T_11)
node _salloc_outs_0_flit_payload_T_19 = or(_salloc_outs_0_flit_payload_T_18, _salloc_outs_0_flit_payload_T_12)
node _salloc_outs_0_flit_payload_T_20 = or(_salloc_outs_0_flit_payload_T_19, _salloc_outs_0_flit_payload_T_13)
node _salloc_outs_0_flit_payload_T_21 = or(_salloc_outs_0_flit_payload_T_20, _salloc_outs_0_flit_payload_T_14)
node _salloc_outs_0_flit_payload_T_22 = or(_salloc_outs_0_flit_payload_T_21, _salloc_outs_0_flit_payload_T_15)
wire _salloc_outs_0_flit_payload_WIRE : UInt<73>
connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_22
connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE
node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_head_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_head_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_head_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _salloc_outs_0_flit_head_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _salloc_outs_0_flit_head_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
node _salloc_outs_0_flit_head_T_8 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_9 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_10 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_11 = mux(_salloc_outs_0_flit_head_T_3, input_buffer.io.deq[3].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_12 = mux(_salloc_outs_0_flit_head_T_4, input_buffer.io.deq[4].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_13 = mux(_salloc_outs_0_flit_head_T_5, input_buffer.io.deq[5].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_14 = mux(_salloc_outs_0_flit_head_T_6, input_buffer.io.deq[6].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_15 = mux(_salloc_outs_0_flit_head_T_7, input_buffer.io.deq[7].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_16 = or(_salloc_outs_0_flit_head_T_8, _salloc_outs_0_flit_head_T_9)
node _salloc_outs_0_flit_head_T_17 = or(_salloc_outs_0_flit_head_T_16, _salloc_outs_0_flit_head_T_10)
node _salloc_outs_0_flit_head_T_18 = or(_salloc_outs_0_flit_head_T_17, _salloc_outs_0_flit_head_T_11)
node _salloc_outs_0_flit_head_T_19 = or(_salloc_outs_0_flit_head_T_18, _salloc_outs_0_flit_head_T_12)
node _salloc_outs_0_flit_head_T_20 = or(_salloc_outs_0_flit_head_T_19, _salloc_outs_0_flit_head_T_13)
node _salloc_outs_0_flit_head_T_21 = or(_salloc_outs_0_flit_head_T_20, _salloc_outs_0_flit_head_T_14)
node _salloc_outs_0_flit_head_T_22 = or(_salloc_outs_0_flit_head_T_21, _salloc_outs_0_flit_head_T_15)
wire _salloc_outs_0_flit_head_WIRE : UInt<1>
connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_22
connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE
node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_tail_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_tail_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_tail_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _salloc_outs_0_flit_tail_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _salloc_outs_0_flit_tail_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
node _salloc_outs_0_flit_tail_T_8 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_9 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_10 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_11 = mux(_salloc_outs_0_flit_tail_T_3, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_12 = mux(_salloc_outs_0_flit_tail_T_4, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_13 = mux(_salloc_outs_0_flit_tail_T_5, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_14 = mux(_salloc_outs_0_flit_tail_T_6, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_15 = mux(_salloc_outs_0_flit_tail_T_7, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_16 = or(_salloc_outs_0_flit_tail_T_8, _salloc_outs_0_flit_tail_T_9)
node _salloc_outs_0_flit_tail_T_17 = or(_salloc_outs_0_flit_tail_T_16, _salloc_outs_0_flit_tail_T_10)
node _salloc_outs_0_flit_tail_T_18 = or(_salloc_outs_0_flit_tail_T_17, _salloc_outs_0_flit_tail_T_11)
node _salloc_outs_0_flit_tail_T_19 = or(_salloc_outs_0_flit_tail_T_18, _salloc_outs_0_flit_tail_T_12)
node _salloc_outs_0_flit_tail_T_20 = or(_salloc_outs_0_flit_tail_T_19, _salloc_outs_0_flit_tail_T_13)
node _salloc_outs_0_flit_tail_T_21 = or(_salloc_outs_0_flit_tail_T_20, _salloc_outs_0_flit_tail_T_14)
node _salloc_outs_0_flit_tail_T_22 = or(_salloc_outs_0_flit_tail_T_21, _salloc_outs_0_flit_tail_T_15)
wire _salloc_outs_0_flit_tail_WIRE : UInt<1>
connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_22
connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE
node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_flow_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_flow_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_flow_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _salloc_outs_0_flit_flow_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _salloc_outs_0_flit_flow_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}
node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_10 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_11 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_12 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_13 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_16 = or(_salloc_outs_0_flit_flow_T_8, _salloc_outs_0_flit_flow_T_9)
node _salloc_outs_0_flit_flow_T_17 = or(_salloc_outs_0_flit_flow_T_16, _salloc_outs_0_flit_flow_T_10)
node _salloc_outs_0_flit_flow_T_18 = or(_salloc_outs_0_flit_flow_T_17, _salloc_outs_0_flit_flow_T_11)
node _salloc_outs_0_flit_flow_T_19 = or(_salloc_outs_0_flit_flow_T_18, _salloc_outs_0_flit_flow_T_12)
node _salloc_outs_0_flit_flow_T_20 = or(_salloc_outs_0_flit_flow_T_19, _salloc_outs_0_flit_flow_T_13)
node _salloc_outs_0_flit_flow_T_21 = or(_salloc_outs_0_flit_flow_T_20, _salloc_outs_0_flit_flow_T_14)
node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_21, _salloc_outs_0_flit_flow_T_15)
wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2>
connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_22
connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1
node _salloc_outs_0_flit_flow_T_23 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_24 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_25 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_26 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_27 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_28 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_29 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_30 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_31 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_24)
node _salloc_outs_0_flit_flow_T_32 = or(_salloc_outs_0_flit_flow_T_31, _salloc_outs_0_flit_flow_T_25)
node _salloc_outs_0_flit_flow_T_33 = or(_salloc_outs_0_flit_flow_T_32, _salloc_outs_0_flit_flow_T_26)
node _salloc_outs_0_flit_flow_T_34 = or(_salloc_outs_0_flit_flow_T_33, _salloc_outs_0_flit_flow_T_27)
node _salloc_outs_0_flit_flow_T_35 = or(_salloc_outs_0_flit_flow_T_34, _salloc_outs_0_flit_flow_T_28)
node _salloc_outs_0_flit_flow_T_36 = or(_salloc_outs_0_flit_flow_T_35, _salloc_outs_0_flit_flow_T_29)
node _salloc_outs_0_flit_flow_T_37 = or(_salloc_outs_0_flit_flow_T_36, _salloc_outs_0_flit_flow_T_30)
wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<5>
connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_37
connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2
node _salloc_outs_0_flit_flow_T_38 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_39 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_40 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_41 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_42 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_43 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_44 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_45 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_46 = or(_salloc_outs_0_flit_flow_T_38, _salloc_outs_0_flit_flow_T_39)
node _salloc_outs_0_flit_flow_T_47 = or(_salloc_outs_0_flit_flow_T_46, _salloc_outs_0_flit_flow_T_40)
node _salloc_outs_0_flit_flow_T_48 = or(_salloc_outs_0_flit_flow_T_47, _salloc_outs_0_flit_flow_T_41)
node _salloc_outs_0_flit_flow_T_49 = or(_salloc_outs_0_flit_flow_T_48, _salloc_outs_0_flit_flow_T_42)
node _salloc_outs_0_flit_flow_T_50 = or(_salloc_outs_0_flit_flow_T_49, _salloc_outs_0_flit_flow_T_43)
node _salloc_outs_0_flit_flow_T_51 = or(_salloc_outs_0_flit_flow_T_50, _salloc_outs_0_flit_flow_T_44)
node _salloc_outs_0_flit_flow_T_52 = or(_salloc_outs_0_flit_flow_T_51, _salloc_outs_0_flit_flow_T_45)
wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<2>
connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_52
connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3
node _salloc_outs_0_flit_flow_T_53 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_54 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_55 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_56 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_57 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_58 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_59 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_60 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_61 = or(_salloc_outs_0_flit_flow_T_53, _salloc_outs_0_flit_flow_T_54)
node _salloc_outs_0_flit_flow_T_62 = or(_salloc_outs_0_flit_flow_T_61, _salloc_outs_0_flit_flow_T_55)
node _salloc_outs_0_flit_flow_T_63 = or(_salloc_outs_0_flit_flow_T_62, _salloc_outs_0_flit_flow_T_56)
node _salloc_outs_0_flit_flow_T_64 = or(_salloc_outs_0_flit_flow_T_63, _salloc_outs_0_flit_flow_T_57)
node _salloc_outs_0_flit_flow_T_65 = or(_salloc_outs_0_flit_flow_T_64, _salloc_outs_0_flit_flow_T_58)
node _salloc_outs_0_flit_flow_T_66 = or(_salloc_outs_0_flit_flow_T_65, _salloc_outs_0_flit_flow_T_59)
node _salloc_outs_0_flit_flow_T_67 = or(_salloc_outs_0_flit_flow_T_66, _salloc_outs_0_flit_flow_T_60)
wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<5>
connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_67
connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4
node _salloc_outs_0_flit_flow_T_68 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_69 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_70 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_71 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_72 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_73 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_74 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_75 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_76 = or(_salloc_outs_0_flit_flow_T_68, _salloc_outs_0_flit_flow_T_69)
node _salloc_outs_0_flit_flow_T_77 = or(_salloc_outs_0_flit_flow_T_76, _salloc_outs_0_flit_flow_T_70)
node _salloc_outs_0_flit_flow_T_78 = or(_salloc_outs_0_flit_flow_T_77, _salloc_outs_0_flit_flow_T_71)
node _salloc_outs_0_flit_flow_T_79 = or(_salloc_outs_0_flit_flow_T_78, _salloc_outs_0_flit_flow_T_72)
node _salloc_outs_0_flit_flow_T_80 = or(_salloc_outs_0_flit_flow_T_79, _salloc_outs_0_flit_flow_T_73)
node _salloc_outs_0_flit_flow_T_81 = or(_salloc_outs_0_flit_flow_T_80, _salloc_outs_0_flit_flow_T_74)
node _salloc_outs_0_flit_flow_T_82 = or(_salloc_outs_0_flit_flow_T_81, _salloc_outs_0_flit_flow_T_75)
wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<3>
connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_82
connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5
connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE
else :
invalidate salloc_outs[0].out_vid
invalidate salloc_outs[0].flit.virt_channel_id
invalidate salloc_outs[0].flit.flow.egress_node_id
invalidate salloc_outs[0].flit.flow.egress_node
invalidate salloc_outs[0].flit.flow.ingress_node_id
invalidate salloc_outs[0].flit.flow.ingress_node
invalidate salloc_outs[0].flit.flow.vnet_id
invalidate salloc_outs[0].flit.payload
invalidate salloc_outs[0].flit.tail
invalidate salloc_outs[0].flit.head
invalidate salloc_outs[0].flit.virt_channel_id
connect io.out[0].valid, salloc_outs[0].valid
connect io.out[0].bits.flit, salloc_outs[0].flit
connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid
invalidate states[0].fifo_deps
invalidate states[0].flow.egress_node_id
invalidate states[0].flow.egress_node
invalidate states[0].flow.ingress_node_id
invalidate states[0].flow.ingress_node
invalidate states[0].flow.vnet_id
invalidate states[0].vc_sel.`0`[0]
invalidate states[0].vc_sel.`0`[1]
invalidate states[0].vc_sel.`0`[2]
invalidate states[0].vc_sel.`0`[3]
invalidate states[0].vc_sel.`0`[4]
invalidate states[0].vc_sel.`0`[5]
invalidate states[0].vc_sel.`0`[6]
invalidate states[0].vc_sel.`0`[7]
invalidate states[0].vc_sel.`1`[0]
invalidate states[0].vc_sel.`2`[0]
invalidate states[0].vc_sel.`3`[0]
invalidate states[0].g
invalidate states[1].fifo_deps
invalidate states[1].flow.egress_node_id
invalidate states[1].flow.egress_node
invalidate states[1].flow.ingress_node_id
invalidate states[1].flow.ingress_node
invalidate states[1].flow.vnet_id
invalidate states[1].vc_sel.`0`[0]
invalidate states[1].vc_sel.`0`[1]
invalidate states[1].vc_sel.`0`[2]
invalidate states[1].vc_sel.`0`[3]
invalidate states[1].vc_sel.`0`[4]
invalidate states[1].vc_sel.`0`[5]
invalidate states[1].vc_sel.`0`[6]
invalidate states[1].vc_sel.`0`[7]
invalidate states[1].vc_sel.`1`[0]
invalidate states[1].vc_sel.`2`[0]
invalidate states[1].vc_sel.`3`[0]
invalidate states[1].g
invalidate states[2].fifo_deps
invalidate states[2].flow.egress_node_id
invalidate states[2].flow.egress_node
invalidate states[2].flow.ingress_node_id
invalidate states[2].flow.ingress_node
invalidate states[2].flow.vnet_id
invalidate states[2].vc_sel.`0`[0]
invalidate states[2].vc_sel.`0`[1]
invalidate states[2].vc_sel.`0`[2]
invalidate states[2].vc_sel.`0`[3]
invalidate states[2].vc_sel.`0`[4]
invalidate states[2].vc_sel.`0`[5]
invalidate states[2].vc_sel.`0`[6]
invalidate states[2].vc_sel.`0`[7]
invalidate states[2].vc_sel.`1`[0]
invalidate states[2].vc_sel.`2`[0]
invalidate states[2].vc_sel.`3`[0]
invalidate states[2].g
invalidate states[3].fifo_deps
invalidate states[3].flow.egress_node_id
invalidate states[3].flow.egress_node
invalidate states[3].flow.ingress_node_id
invalidate states[3].flow.ingress_node
invalidate states[3].flow.vnet_id
invalidate states[3].vc_sel.`0`[0]
invalidate states[3].vc_sel.`0`[1]
invalidate states[3].vc_sel.`0`[2]
invalidate states[3].vc_sel.`0`[3]
invalidate states[3].vc_sel.`0`[4]
invalidate states[3].vc_sel.`0`[5]
invalidate states[3].vc_sel.`0`[6]
invalidate states[3].vc_sel.`0`[7]
invalidate states[3].vc_sel.`1`[0]
invalidate states[3].vc_sel.`2`[0]
invalidate states[3].vc_sel.`3`[0]
invalidate states[3].g
connect states[4].vc_sel.`0`[0], UInt<1>(0h0)
connect states[4].vc_sel.`0`[1], UInt<1>(0h0)
connect states[4].vc_sel.`0`[2], UInt<1>(0h0)
connect states[4].vc_sel.`0`[3], UInt<1>(0h0)
connect states[4].vc_sel.`0`[4], UInt<1>(0h0)
connect states[4].vc_sel.`0`[5], UInt<1>(0h0)
connect states[4].vc_sel.`0`[6], UInt<1>(0h0)
connect states[4].vc_sel.`0`[7], UInt<1>(0h0)
connect states[5].vc_sel.`0`[0], UInt<1>(0h0)
connect states[5].vc_sel.`0`[1], UInt<1>(0h0)
connect states[5].vc_sel.`0`[2], UInt<1>(0h0)
connect states[5].vc_sel.`0`[3], UInt<1>(0h0)
connect states[5].vc_sel.`0`[4], UInt<1>(0h0)
connect states[5].vc_sel.`0`[5], UInt<1>(0h0)
connect states[5].vc_sel.`0`[6], UInt<1>(0h0)
connect states[5].vc_sel.`0`[7], UInt<1>(0h0)
connect states[6].vc_sel.`0`[0], UInt<1>(0h0)
connect states[6].vc_sel.`0`[1], UInt<1>(0h0)
connect states[6].vc_sel.`0`[2], UInt<1>(0h0)
connect states[6].vc_sel.`0`[3], UInt<1>(0h0)
connect states[6].vc_sel.`0`[4], UInt<1>(0h0)
connect states[6].vc_sel.`0`[5], UInt<1>(0h0)
connect states[6].vc_sel.`0`[6], UInt<1>(0h0)
connect states[6].vc_sel.`0`[7], UInt<1>(0h0)
connect states[7].vc_sel.`0`[0], UInt<1>(0h0)
connect states[7].vc_sel.`0`[1], UInt<1>(0h0)
connect states[7].vc_sel.`0`[2], UInt<1>(0h0)
connect states[7].vc_sel.`0`[3], UInt<1>(0h0)
connect states[7].vc_sel.`0`[4], UInt<1>(0h0)
connect states[7].vc_sel.`0`[5], UInt<1>(0h0)
connect states[7].vc_sel.`0`[6], UInt<1>(0h0)
connect states[7].vc_sel.`0`[7], UInt<1>(0h0)
node _T_99 = asUInt(reset)
when _T_99 :
connect states[0].g, UInt<3>(0h0)
connect states[1].g, UInt<3>(0h0)
connect states[2].g, UInt<3>(0h0)
connect states[3].g, UInt<3>(0h0)
connect states[4].g, UInt<3>(0h0)
connect states[5].g, UInt<3>(0h0)
connect states[6].g, UInt<3>(0h0)
connect states[7].g, UInt<3>(0h0) | module InputUnit_3( // @[InputUnit.scala:158:7]
input clock, // @[InputUnit.scala:158:7]
input reset, // @[InputUnit.scala:158:7]
input io_vcalloc_req_ready, // @[InputUnit.scala:170:14]
output io_vcalloc_req_valid, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_0, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_0, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_0, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_3, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_5, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_6, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_7, // @[InputUnit.scala:170:14]
input io_salloc_req_0_ready, // @[InputUnit.scala:170:14]
output io_salloc_req_0_valid, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14]
output io_out_0_valid, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14]
output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14]
output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14]
output [4:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [4:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14]
output [2:0] io_debug_va_stall, // @[InputUnit.scala:170:14]
output [2:0] io_debug_sa_stall, // @[InputUnit.scala:170:14]
input io_in_flit_0_valid, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14]
input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14]
input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
input [4:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input [2:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14]
output [7:0] io_in_credit_return, // @[InputUnit.scala:170:14]
output [7:0] io_in_vc_free // @[InputUnit.scala:170:14]
);
wire vcalloc_vals_7; // @[InputUnit.scala:266:32]
wire vcalloc_vals_6; // @[InputUnit.scala:266:32]
wire vcalloc_vals_5; // @[InputUnit.scala:266:32]
wire vcalloc_vals_4; // @[InputUnit.scala:266:32]
wire _salloc_arb_io_in_4_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_5_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_6_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_7_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26]
wire [7:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26]
wire _route_arbiter_io_in_4_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_5_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_6_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_7_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29]
wire [2:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29]
wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_5_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_6_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_6_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_6_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_6_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_7_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_7_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_7_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_7_bits_payload; // @[InputUnit.scala:181:28]
reg [2:0] states_4_g; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_3_0; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_0; // @[InputUnit.scala:192:19]
reg [2:0] states_4_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_4_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_4_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_4_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_4_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_5_g; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_3_0; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_0; // @[InputUnit.scala:192:19]
reg [2:0] states_5_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_5_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_5_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_5_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_5_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_6_g; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_3_0; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_0; // @[InputUnit.scala:192:19]
reg [2:0] states_6_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_6_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_6_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_6_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_6_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_7_g; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_3_0; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_0; // @[InputUnit.scala:192:19]
reg [2:0] states_7_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_7_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_7_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_7_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_7_flow_egress_node_id; // @[InputUnit.scala:192:19]
wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30]
wire route_arbiter_io_in_4_valid = states_4_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_5_valid = states_5_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_6_valid = states_6_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_7_valid = states_7_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
reg [7:0] mask; // @[InputUnit.scala:250:21]
wire [7:0] _vcalloc_filter_T_3 = {vcalloc_vals_7, vcalloc_vals_6, vcalloc_vals_5, vcalloc_vals_4, 4'h0} & ~mask; // @[InputUnit.scala:158:7, :250:21, :253:{80,87,89}, :266:32]
wire [15:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 16'h1 : _vcalloc_filter_T_3[1] ? 16'h2 : _vcalloc_filter_T_3[2] ? 16'h4 : _vcalloc_filter_T_3[3] ? 16'h8 : _vcalloc_filter_T_3[4] ? 16'h10 : _vcalloc_filter_T_3[5] ? 16'h20 : _vcalloc_filter_T_3[6] ? 16'h40 : _vcalloc_filter_T_3[7] ? 16'h80 : vcalloc_vals_4 ? 16'h1000 : vcalloc_vals_5 ? 16'h2000 : vcalloc_vals_6 ? 16'h4000 : {vcalloc_vals_7, 15'h0}; // @[OneHot.scala:85:71]
wire [7:0] vcalloc_sel = vcalloc_filter[7:0] | vcalloc_filter[15:8]; // @[Mux.scala:50:70]
wire io_vcalloc_req_valid_0 = vcalloc_vals_4 | vcalloc_vals_5 | vcalloc_vals_6 | vcalloc_vals_7; // @[package.scala:81:59]
assign vcalloc_vals_4 = states_4_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_5 = states_5_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_6 = states_6_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_7 = states_7_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
wire _GEN_0 = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]
wire _GEN_1 = _GEN_0 & vcalloc_sel[4]; // @[Mux.scala:32:36]
wire _GEN_2 = _GEN_0 & vcalloc_sel[5]; // @[Mux.scala:32:36]
wire _GEN_3 = _GEN_0 & vcalloc_sel[6]; // @[Mux.scala:32:36]
wire _GEN_4 = _GEN_0 & vcalloc_sel[7]; // @[Mux.scala:32:36] |
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_88 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>}
node _io_out_d_T = mul(io.in_a, io.in_b)
node _io_out_d_T_1 = add(_io_out_d_T, io.in_c)
node _io_out_d_T_2 = tail(_io_out_d_T_1, 1)
node _io_out_d_T_3 = asSInt(_io_out_d_T_2)
connect io.out_d, _io_out_d_T_3 | module MacUnit_88( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [31:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7]
wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54]
wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PredRenameStage :
input clock : Clock
input reset : Reset
output io : { ren_stalls : UInt<1>[1], flip kill : UInt<1>, flip dec_fire : UInt<1>[1], flip dec_uops : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[1], ren2_mask : UInt<1>[1], ren2_uops : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[1], flip brupdate : { b1 : { resolve_mask : UInt<8>, mispredict_mask : UInt<8>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip dis_fire : UInt<1>[1], flip dis_ready : UInt<1>, flip wakeups : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<64>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}[1], flip com_valids : UInt<1>[1], flip com_uops : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[1], flip rbk_valids : UInt<1>[1], flip rollback : UInt<1>, flip debug_rob_empty : UInt<1>, debug : { freelist : UInt<16>, isprlist : UInt<16>, busytable : UInt<16>}}
connect io.ren_stalls[0], UInt<1>(0h0)
invalidate io.debug.busytable
invalidate io.debug.isprlist
invalidate io.debug.freelist
wire ren1_fire : UInt<1>[1]
wire ren1_uops : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[1]
wire ren2_valids : UInt<1>[1]
wire ren2_uops : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[1]
wire ren2_alloc_reqs : UInt<1>[1]
connect ren1_fire[0], io.dec_fire[0]
connect ren1_uops[0], io.dec_uops[0]
regreset r_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg r_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock
wire next_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
connect next_uop, r_uop
when io.kill :
connect r_valid, UInt<1>(0h0)
else :
when io.dis_ready :
connect r_valid, ren1_fire[0]
connect next_uop, ren1_uops[0]
else :
node _r_valid_T = eq(io.dis_fire[0], UInt<1>(0h0))
node _r_valid_T_1 = and(r_valid, _r_valid_T)
connect r_valid, _r_valid_T_1
connect next_uop, r_uop
wire r_uop_newuop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
connect r_uop_newuop, next_uop
node _r_uop_newuop_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _r_uop_newuop_br_mask_T_1 = and(next_uop.br_mask, _r_uop_newuop_br_mask_T)
connect r_uop_newuop.br_mask, _r_uop_newuop_br_mask_T_1
connect r_uop, r_uop_newuop
connect ren2_valids[0], r_valid
connect ren2_uops[0], r_uop
connect io.ren2_mask, ren2_valids
invalidate ren2_alloc_reqs[0]
wire _busy_table_WIRE : UInt<1>[16]
connect _busy_table_WIRE[0], UInt<1>(0h0)
connect _busy_table_WIRE[1], UInt<1>(0h0)
connect _busy_table_WIRE[2], UInt<1>(0h0)
connect _busy_table_WIRE[3], UInt<1>(0h0)
connect _busy_table_WIRE[4], UInt<1>(0h0)
connect _busy_table_WIRE[5], UInt<1>(0h0)
connect _busy_table_WIRE[6], UInt<1>(0h0)
connect _busy_table_WIRE[7], UInt<1>(0h0)
connect _busy_table_WIRE[8], UInt<1>(0h0)
connect _busy_table_WIRE[9], UInt<1>(0h0)
connect _busy_table_WIRE[10], UInt<1>(0h0)
connect _busy_table_WIRE[11], UInt<1>(0h0)
connect _busy_table_WIRE[12], UInt<1>(0h0)
connect _busy_table_WIRE[13], UInt<1>(0h0)
connect _busy_table_WIRE[14], UInt<1>(0h0)
connect _busy_table_WIRE[15], UInt<1>(0h0)
regreset busy_table : UInt<1>[16], clock, reset, _busy_table_WIRE
wire _to_busy_WIRE : UInt<1>[16]
connect _to_busy_WIRE[0], UInt<1>(0h0)
connect _to_busy_WIRE[1], UInt<1>(0h0)
connect _to_busy_WIRE[2], UInt<1>(0h0)
connect _to_busy_WIRE[3], UInt<1>(0h0)
connect _to_busy_WIRE[4], UInt<1>(0h0)
connect _to_busy_WIRE[5], UInt<1>(0h0)
connect _to_busy_WIRE[6], UInt<1>(0h0)
connect _to_busy_WIRE[7], UInt<1>(0h0)
connect _to_busy_WIRE[8], UInt<1>(0h0)
connect _to_busy_WIRE[9], UInt<1>(0h0)
connect _to_busy_WIRE[10], UInt<1>(0h0)
connect _to_busy_WIRE[11], UInt<1>(0h0)
connect _to_busy_WIRE[12], UInt<1>(0h0)
connect _to_busy_WIRE[13], UInt<1>(0h0)
connect _to_busy_WIRE[14], UInt<1>(0h0)
connect _to_busy_WIRE[15], UInt<1>(0h0)
wire to_busy : UInt<1>[16]
connect to_busy, _to_busy_WIRE
wire _unbusy_WIRE : UInt<1>[16]
connect _unbusy_WIRE[0], UInt<1>(0h0)
connect _unbusy_WIRE[1], UInt<1>(0h0)
connect _unbusy_WIRE[2], UInt<1>(0h0)
connect _unbusy_WIRE[3], UInt<1>(0h0)
connect _unbusy_WIRE[4], UInt<1>(0h0)
connect _unbusy_WIRE[5], UInt<1>(0h0)
connect _unbusy_WIRE[6], UInt<1>(0h0)
connect _unbusy_WIRE[7], UInt<1>(0h0)
connect _unbusy_WIRE[8], UInt<1>(0h0)
connect _unbusy_WIRE[9], UInt<1>(0h0)
connect _unbusy_WIRE[10], UInt<1>(0h0)
connect _unbusy_WIRE[11], UInt<1>(0h0)
connect _unbusy_WIRE[12], UInt<1>(0h0)
connect _unbusy_WIRE[13], UInt<1>(0h0)
connect _unbusy_WIRE[14], UInt<1>(0h0)
connect _unbusy_WIRE[15], UInt<1>(0h0)
wire unbusy : UInt<1>[16]
connect unbusy, _unbusy_WIRE
reg current_ftq_idx : UInt<4>, clock
connect io.ren2_uops[0], ren2_uops[0]
node _is_sfb_br_T = and(ren2_uops[0].is_br, ren2_uops[0].is_sfb)
node _is_sfb_br_T_1 = and(_is_sfb_br_T, UInt<1>(0h0))
node is_sfb_br = and(_is_sfb_br_T_1, io.dis_fire[0])
node _is_sfb_shadow_T = eq(ren2_uops[0].is_br, UInt<1>(0h0))
node _is_sfb_shadow_T_1 = and(_is_sfb_shadow_T, ren2_uops[0].is_sfb)
node _is_sfb_shadow_T_2 = and(_is_sfb_shadow_T_1, UInt<1>(0h0))
node is_sfb_shadow = and(_is_sfb_shadow_T_2, io.dis_fire[0])
when is_sfb_br :
connect io.ren2_uops[0].pdst, ren2_uops[0].ftq_idx
connect to_busy[ren2_uops[0].ftq_idx], UInt<1>(0h1)
node _T = mux(is_sfb_br, ren2_uops[0].ftq_idx, current_ftq_idx)
when is_sfb_shadow :
connect io.ren2_uops[0].ppred, _T
node _io_ren2_uops_0_ppred_busy_T = or(busy_table[_T], to_busy[_T])
node _io_ren2_uops_0_ppred_busy_T_1 = eq(unbusy[_T], UInt<1>(0h0))
node _io_ren2_uops_0_ppred_busy_T_2 = and(_io_ren2_uops_0_ppred_busy_T, _io_ren2_uops_0_ppred_busy_T_1)
connect io.ren2_uops[0].ppred_busy, _io_ren2_uops_0_ppred_busy_T_2
when io.wakeups[0].valid :
node _T_1 = bits(io.wakeups[0].bits.uop.pdst, 3, 0)
connect unbusy[_T_1], UInt<1>(0h1)
connect current_ftq_idx, _T
node lo_lo_lo = cat(busy_table[1], busy_table[0])
node lo_lo_hi = cat(busy_table[3], busy_table[2])
node lo_lo = cat(lo_lo_hi, lo_lo_lo)
node lo_hi_lo = cat(busy_table[5], busy_table[4])
node lo_hi_hi = cat(busy_table[7], busy_table[6])
node lo_hi = cat(lo_hi_hi, lo_hi_lo)
node lo = cat(lo_hi, lo_lo)
node hi_lo_lo = cat(busy_table[9], busy_table[8])
node hi_lo_hi = cat(busy_table[11], busy_table[10])
node hi_lo = cat(hi_lo_hi, hi_lo_lo)
node hi_hi_lo = cat(busy_table[13], busy_table[12])
node hi_hi_hi = cat(busy_table[15], busy_table[14])
node hi_hi = cat(hi_hi_hi, hi_hi_lo)
node hi = cat(hi_hi, hi_lo)
node _T_2 = cat(hi, lo)
node lo_lo_lo_1 = cat(to_busy[1], to_busy[0])
node lo_lo_hi_1 = cat(to_busy[3], to_busy[2])
node lo_lo_1 = cat(lo_lo_hi_1, lo_lo_lo_1)
node lo_hi_lo_1 = cat(to_busy[5], to_busy[4])
node lo_hi_hi_1 = cat(to_busy[7], to_busy[6])
node lo_hi_1 = cat(lo_hi_hi_1, lo_hi_lo_1)
node lo_1 = cat(lo_hi_1, lo_lo_1)
node hi_lo_lo_1 = cat(to_busy[9], to_busy[8])
node hi_lo_hi_1 = cat(to_busy[11], to_busy[10])
node hi_lo_1 = cat(hi_lo_hi_1, hi_lo_lo_1)
node hi_hi_lo_1 = cat(to_busy[13], to_busy[12])
node hi_hi_hi_1 = cat(to_busy[15], to_busy[14])
node hi_hi_1 = cat(hi_hi_hi_1, hi_hi_lo_1)
node hi_1 = cat(hi_hi_1, hi_lo_1)
node _T_3 = cat(hi_1, lo_1)
node _T_4 = or(_T_2, _T_3)
node lo_lo_lo_2 = cat(unbusy[1], unbusy[0])
node lo_lo_hi_2 = cat(unbusy[3], unbusy[2])
node lo_lo_2 = cat(lo_lo_hi_2, lo_lo_lo_2)
node lo_hi_lo_2 = cat(unbusy[5], unbusy[4])
node lo_hi_hi_2 = cat(unbusy[7], unbusy[6])
node lo_hi_2 = cat(lo_hi_hi_2, lo_hi_lo_2)
node lo_2 = cat(lo_hi_2, lo_lo_2)
node hi_lo_lo_2 = cat(unbusy[9], unbusy[8])
node hi_lo_hi_2 = cat(unbusy[11], unbusy[10])
node hi_lo_2 = cat(hi_lo_hi_2, hi_lo_lo_2)
node hi_hi_lo_2 = cat(unbusy[13], unbusy[12])
node hi_hi_hi_2 = cat(unbusy[15], unbusy[14])
node hi_hi_2 = cat(hi_hi_hi_2, hi_hi_lo_2)
node hi_2 = cat(hi_hi_2, hi_lo_2)
node _T_5 = cat(hi_2, lo_2)
node _T_6 = not(_T_5)
node _T_7 = and(_T_4, _T_6)
node _T_8 = bits(_T_7, 0, 0)
node _T_9 = bits(_T_7, 1, 1)
node _T_10 = bits(_T_7, 2, 2)
node _T_11 = bits(_T_7, 3, 3)
node _T_12 = bits(_T_7, 4, 4)
node _T_13 = bits(_T_7, 5, 5)
node _T_14 = bits(_T_7, 6, 6)
node _T_15 = bits(_T_7, 7, 7)
node _T_16 = bits(_T_7, 8, 8)
node _T_17 = bits(_T_7, 9, 9)
node _T_18 = bits(_T_7, 10, 10)
node _T_19 = bits(_T_7, 11, 11)
node _T_20 = bits(_T_7, 12, 12)
node _T_21 = bits(_T_7, 13, 13)
node _T_22 = bits(_T_7, 14, 14)
node _T_23 = bits(_T_7, 15, 15)
connect busy_table[0], _T_8
connect busy_table[1], _T_9
connect busy_table[2], _T_10
connect busy_table[3], _T_11
connect busy_table[4], _T_12
connect busy_table[5], _T_13
connect busy_table[6], _T_14
connect busy_table[7], _T_15
connect busy_table[8], _T_16
connect busy_table[9], _T_17
connect busy_table[10], _T_18
connect busy_table[11], _T_19
connect busy_table[12], _T_20
connect busy_table[13], _T_21
connect busy_table[14], _T_22
connect busy_table[15], _T_23 | module PredRenameStage( // @[rename-stage.scala:356:7]
input clock, // @[rename-stage.scala:356:7]
input reset, // @[rename-stage.scala:356:7]
input io_kill, // @[rename-stage.scala:60:14]
input io_dec_fire_0, // @[rename-stage.scala:60:14]
input [6:0] io_dec_uops_0_uopc, // @[rename-stage.scala:60:14]
input [31:0] io_dec_uops_0_inst, // @[rename-stage.scala:60:14]
input [31:0] io_dec_uops_0_debug_inst, // @[rename-stage.scala:60:14]
input io_dec_uops_0_is_rvc, // @[rename-stage.scala:60:14]
input [39:0] io_dec_uops_0_debug_pc, // @[rename-stage.scala:60:14]
input [2:0] io_dec_uops_0_iq_type, // @[rename-stage.scala:60:14]
input [9:0] io_dec_uops_0_fu_code, // @[rename-stage.scala:60:14]
input io_dec_uops_0_is_br, // @[rename-stage.scala:60:14]
input io_dec_uops_0_is_jalr, // @[rename-stage.scala:60:14]
input io_dec_uops_0_is_jal, // @[rename-stage.scala:60:14]
input io_dec_uops_0_is_sfb, // @[rename-stage.scala:60:14]
input [7:0] io_dec_uops_0_br_mask, // @[rename-stage.scala:60:14]
input [2:0] io_dec_uops_0_br_tag, // @[rename-stage.scala:60:14]
input [3:0] io_dec_uops_0_ftq_idx, // @[rename-stage.scala:60:14]
input io_dec_uops_0_edge_inst, // @[rename-stage.scala:60:14]
input [5:0] io_dec_uops_0_pc_lob, // @[rename-stage.scala:60:14]
input io_dec_uops_0_taken, // @[rename-stage.scala:60:14]
input [19:0] io_dec_uops_0_imm_packed, // @[rename-stage.scala:60:14]
input io_dec_uops_0_exception, // @[rename-stage.scala:60:14]
input [63:0] io_dec_uops_0_exc_cause, // @[rename-stage.scala:60:14]
input io_dec_uops_0_bypassable, // @[rename-stage.scala:60:14]
input [4:0] io_dec_uops_0_mem_cmd, // @[rename-stage.scala:60:14]
input [1:0] io_dec_uops_0_mem_size, // @[rename-stage.scala:60:14]
input io_dec_uops_0_mem_signed, // @[rename-stage.scala:60:14]
input io_dec_uops_0_is_fence, // @[rename-stage.scala:60:14]
input io_dec_uops_0_is_fencei, // @[rename-stage.scala:60:14]
input io_dec_uops_0_is_amo, // @[rename-stage.scala:60:14]
input io_dec_uops_0_uses_ldq, // @[rename-stage.scala:60:14]
input io_dec_uops_0_uses_stq, // @[rename-stage.scala:60:14]
input io_dec_uops_0_is_sys_pc2epc, // @[rename-stage.scala:60:14]
input io_dec_uops_0_is_unique, // @[rename-stage.scala:60:14]
input io_dec_uops_0_flush_on_commit, // @[rename-stage.scala:60:14]
input [5:0] io_dec_uops_0_ldst, // @[rename-stage.scala:60:14]
input [5:0] io_dec_uops_0_lrs1, // @[rename-stage.scala:60:14]
input [5:0] io_dec_uops_0_lrs2, // @[rename-stage.scala:60:14]
input [5:0] io_dec_uops_0_lrs3, // @[rename-stage.scala:60:14]
input io_dec_uops_0_ldst_val, // @[rename-stage.scala:60:14]
input [1:0] io_dec_uops_0_dst_rtype, // @[rename-stage.scala:60:14]
input [1:0] io_dec_uops_0_lrs1_rtype, // @[rename-stage.scala:60:14]
input [1:0] io_dec_uops_0_lrs2_rtype, // @[rename-stage.scala:60:14]
input io_dec_uops_0_frs3_en, // @[rename-stage.scala:60:14]
input io_dec_uops_0_fp_val, // @[rename-stage.scala:60:14]
input io_dec_uops_0_fp_single, // @[rename-stage.scala:60:14]
input io_dec_uops_0_xcpt_pf_if, // @[rename-stage.scala:60:14]
input io_dec_uops_0_xcpt_ae_if, // @[rename-stage.scala:60:14]
input io_dec_uops_0_bp_debug_if, // @[rename-stage.scala:60:14]
input io_dec_uops_0_bp_xcpt_if, // @[rename-stage.scala:60:14]
input [1:0] io_dec_uops_0_debug_fsrc, // @[rename-stage.scala:60:14]
input [7:0] io_brupdate_b1_resolve_mask, // @[rename-stage.scala:60:14]
input [7:0] io_brupdate_b1_mispredict_mask, // @[rename-stage.scala:60:14]
input [6:0] io_brupdate_b2_uop_uopc, // @[rename-stage.scala:60:14]
input [31:0] io_brupdate_b2_uop_inst, // @[rename-stage.scala:60:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_is_rvc, // @[rename-stage.scala:60:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[rename-stage.scala:60:14]
input [2:0] io_brupdate_b2_uop_iq_type, // @[rename-stage.scala:60:14]
input [9:0] io_brupdate_b2_uop_fu_code, // @[rename-stage.scala:60:14]
input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[rename-stage.scala:60:14]
input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[rename-stage.scala:60:14]
input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[rename-stage.scala:60:14]
input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[rename-stage.scala:60:14]
input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_ctrl_fcn_dw, // @[rename-stage.scala:60:14]
input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_ctrl_is_load, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_ctrl_is_sta, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_ctrl_is_std, // @[rename-stage.scala:60:14]
input [1:0] io_brupdate_b2_uop_iw_state, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_iw_p1_poisoned, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_iw_p2_poisoned, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_is_br, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_is_jalr, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_is_jal, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_is_sfb, // @[rename-stage.scala:60:14]
input [7:0] io_brupdate_b2_uop_br_mask, // @[rename-stage.scala:60:14]
input [2:0] io_brupdate_b2_uop_br_tag, // @[rename-stage.scala:60:14]
input [3:0] io_brupdate_b2_uop_ftq_idx, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_edge_inst, // @[rename-stage.scala:60:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_taken, // @[rename-stage.scala:60:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[rename-stage.scala:60:14]
input [11:0] io_brupdate_b2_uop_csr_addr, // @[rename-stage.scala:60:14]
input [4:0] io_brupdate_b2_uop_rob_idx, // @[rename-stage.scala:60:14]
input [2:0] io_brupdate_b2_uop_ldq_idx, // @[rename-stage.scala:60:14]
input [2:0] io_brupdate_b2_uop_stq_idx, // @[rename-stage.scala:60:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[rename-stage.scala:60:14]
input [5:0] io_brupdate_b2_uop_pdst, // @[rename-stage.scala:60:14]
input [5:0] io_brupdate_b2_uop_prs1, // @[rename-stage.scala:60:14]
input [5:0] io_brupdate_b2_uop_prs2, // @[rename-stage.scala:60:14]
input [5:0] io_brupdate_b2_uop_prs3, // @[rename-stage.scala:60:14]
input [3:0] io_brupdate_b2_uop_ppred, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_prs1_busy, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_prs2_busy, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_prs3_busy, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_ppred_busy, // @[rename-stage.scala:60:14]
input [5:0] io_brupdate_b2_uop_stale_pdst, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_exception, // @[rename-stage.scala:60:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_bypassable, // @[rename-stage.scala:60:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[rename-stage.scala:60:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_mem_signed, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_is_fence, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_is_fencei, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_is_amo, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_uses_ldq, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_uses_stq, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_is_unique, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_flush_on_commit, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[rename-stage.scala:60:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[rename-stage.scala:60:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[rename-stage.scala:60:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[rename-stage.scala:60:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_ldst_val, // @[rename-stage.scala:60:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[rename-stage.scala:60:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[rename-stage.scala:60:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_frs3_en, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_fp_val, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_fp_single, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_bp_debug_if, // @[rename-stage.scala:60:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[rename-stage.scala:60:14]
input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[rename-stage.scala:60:14]
input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[rename-stage.scala:60:14]
input io_brupdate_b2_valid, // @[rename-stage.scala:60:14]
input io_brupdate_b2_mispredict, // @[rename-stage.scala:60:14]
input io_brupdate_b2_taken, // @[rename-stage.scala:60:14]
input [2:0] io_brupdate_b2_cfi_type, // @[rename-stage.scala:60:14]
input [1:0] io_brupdate_b2_pc_sel, // @[rename-stage.scala:60:14]
input [39:0] io_brupdate_b2_jalr_target, // @[rename-stage.scala:60:14]
input [20:0] io_brupdate_b2_target_offset, // @[rename-stage.scala:60:14]
input io_dis_fire_0, // @[rename-stage.scala:60:14]
input io_dis_ready, // @[rename-stage.scala:60:14]
input io_com_valids_0, // @[rename-stage.scala:60:14]
input [6:0] io_com_uops_0_uopc, // @[rename-stage.scala:60:14]
input [31:0] io_com_uops_0_inst, // @[rename-stage.scala:60:14]
input [31:0] io_com_uops_0_debug_inst, // @[rename-stage.scala:60:14]
input io_com_uops_0_is_rvc, // @[rename-stage.scala:60:14]
input [39:0] io_com_uops_0_debug_pc, // @[rename-stage.scala:60:14]
input [2:0] io_com_uops_0_iq_type, // @[rename-stage.scala:60:14]
input [9:0] io_com_uops_0_fu_code, // @[rename-stage.scala:60:14]
input [3:0] io_com_uops_0_ctrl_br_type, // @[rename-stage.scala:60:14]
input [1:0] io_com_uops_0_ctrl_op1_sel, // @[rename-stage.scala:60:14]
input [2:0] io_com_uops_0_ctrl_op2_sel, // @[rename-stage.scala:60:14]
input [2:0] io_com_uops_0_ctrl_imm_sel, // @[rename-stage.scala:60:14]
input [4:0] io_com_uops_0_ctrl_op_fcn, // @[rename-stage.scala:60:14]
input io_com_uops_0_ctrl_fcn_dw, // @[rename-stage.scala:60:14]
input [2:0] io_com_uops_0_ctrl_csr_cmd, // @[rename-stage.scala:60:14]
input io_com_uops_0_ctrl_is_load, // @[rename-stage.scala:60:14]
input io_com_uops_0_ctrl_is_sta, // @[rename-stage.scala:60:14]
input io_com_uops_0_ctrl_is_std, // @[rename-stage.scala:60:14]
input [1:0] io_com_uops_0_iw_state, // @[rename-stage.scala:60:14]
input io_com_uops_0_iw_p1_poisoned, // @[rename-stage.scala:60:14]
input io_com_uops_0_iw_p2_poisoned, // @[rename-stage.scala:60:14]
input io_com_uops_0_is_br, // @[rename-stage.scala:60:14]
input io_com_uops_0_is_jalr, // @[rename-stage.scala:60:14]
input io_com_uops_0_is_jal, // @[rename-stage.scala:60:14]
input io_com_uops_0_is_sfb, // @[rename-stage.scala:60:14]
input [7:0] io_com_uops_0_br_mask, // @[rename-stage.scala:60:14]
input [2:0] io_com_uops_0_br_tag, // @[rename-stage.scala:60:14]
input [3:0] io_com_uops_0_ftq_idx, // @[rename-stage.scala:60:14]
input io_com_uops_0_edge_inst, // @[rename-stage.scala:60:14]
input [5:0] io_com_uops_0_pc_lob, // @[rename-stage.scala:60:14]
input io_com_uops_0_taken, // @[rename-stage.scala:60:14]
input [19:0] io_com_uops_0_imm_packed, // @[rename-stage.scala:60:14]
input [11:0] io_com_uops_0_csr_addr, // @[rename-stage.scala:60:14]
input [4:0] io_com_uops_0_rob_idx, // @[rename-stage.scala:60:14]
input [2:0] io_com_uops_0_ldq_idx, // @[rename-stage.scala:60:14]
input [2:0] io_com_uops_0_stq_idx, // @[rename-stage.scala:60:14]
input [1:0] io_com_uops_0_rxq_idx, // @[rename-stage.scala:60:14]
input [5:0] io_com_uops_0_pdst, // @[rename-stage.scala:60:14]
input [5:0] io_com_uops_0_prs1, // @[rename-stage.scala:60:14]
input [5:0] io_com_uops_0_prs2, // @[rename-stage.scala:60:14]
input [5:0] io_com_uops_0_prs3, // @[rename-stage.scala:60:14]
input [3:0] io_com_uops_0_ppred, // @[rename-stage.scala:60:14]
input io_com_uops_0_prs1_busy, // @[rename-stage.scala:60:14]
input io_com_uops_0_prs2_busy, // @[rename-stage.scala:60:14]
input io_com_uops_0_prs3_busy, // @[rename-stage.scala:60:14]
input io_com_uops_0_ppred_busy, // @[rename-stage.scala:60:14]
input [5:0] io_com_uops_0_stale_pdst, // @[rename-stage.scala:60:14]
input io_com_uops_0_exception, // @[rename-stage.scala:60:14]
input [63:0] io_com_uops_0_exc_cause, // @[rename-stage.scala:60:14]
input io_com_uops_0_bypassable, // @[rename-stage.scala:60:14]
input [4:0] io_com_uops_0_mem_cmd, // @[rename-stage.scala:60:14]
input [1:0] io_com_uops_0_mem_size, // @[rename-stage.scala:60:14]
input io_com_uops_0_mem_signed, // @[rename-stage.scala:60:14]
input io_com_uops_0_is_fence, // @[rename-stage.scala:60:14]
input io_com_uops_0_is_fencei, // @[rename-stage.scala:60:14]
input io_com_uops_0_is_amo, // @[rename-stage.scala:60:14]
input io_com_uops_0_uses_ldq, // @[rename-stage.scala:60:14]
input io_com_uops_0_uses_stq, // @[rename-stage.scala:60:14]
input io_com_uops_0_is_sys_pc2epc, // @[rename-stage.scala:60:14]
input io_com_uops_0_is_unique, // @[rename-stage.scala:60:14]
input io_com_uops_0_flush_on_commit, // @[rename-stage.scala:60:14]
input io_com_uops_0_ldst_is_rs1, // @[rename-stage.scala:60:14]
input [5:0] io_com_uops_0_ldst, // @[rename-stage.scala:60:14]
input [5:0] io_com_uops_0_lrs1, // @[rename-stage.scala:60:14]
input [5:0] io_com_uops_0_lrs2, // @[rename-stage.scala:60:14]
input [5:0] io_com_uops_0_lrs3, // @[rename-stage.scala:60:14]
input io_com_uops_0_ldst_val, // @[rename-stage.scala:60:14]
input [1:0] io_com_uops_0_dst_rtype, // @[rename-stage.scala:60:14]
input [1:0] io_com_uops_0_lrs1_rtype, // @[rename-stage.scala:60:14]
input [1:0] io_com_uops_0_lrs2_rtype, // @[rename-stage.scala:60:14]
input io_com_uops_0_frs3_en, // @[rename-stage.scala:60:14]
input io_com_uops_0_fp_val, // @[rename-stage.scala:60:14]
input io_com_uops_0_fp_single, // @[rename-stage.scala:60:14]
input io_com_uops_0_xcpt_pf_if, // @[rename-stage.scala:60:14]
input io_com_uops_0_xcpt_ae_if, // @[rename-stage.scala:60:14]
input io_com_uops_0_xcpt_ma_if, // @[rename-stage.scala:60:14]
input io_com_uops_0_bp_debug_if, // @[rename-stage.scala:60:14]
input io_com_uops_0_bp_xcpt_if, // @[rename-stage.scala:60:14]
input [1:0] io_com_uops_0_debug_fsrc, // @[rename-stage.scala:60:14]
input [1:0] io_com_uops_0_debug_tsrc, // @[rename-stage.scala:60:14]
input io_rbk_valids_0, // @[rename-stage.scala:60:14]
input io_rollback, // @[rename-stage.scala:60:14]
input io_debug_rob_empty // @[rename-stage.scala:60:14]
);
wire [1:0] next_uop_debug_tsrc; // @[rename-stage.scala:123:24]
wire [1:0] next_uop_debug_fsrc; // @[rename-stage.scala:123:24]
wire next_uop_bp_xcpt_if; // @[rename-stage.scala:123:24]
wire next_uop_bp_debug_if; // @[rename-stage.scala:123:24]
wire next_uop_xcpt_ma_if; // @[rename-stage.scala:123:24]
wire next_uop_xcpt_ae_if; // @[rename-stage.scala:123:24]
wire next_uop_xcpt_pf_if; // @[rename-stage.scala:123:24]
wire next_uop_fp_single; // @[rename-stage.scala:123:24]
wire next_uop_fp_val; // @[rename-stage.scala:123:24]
wire next_uop_frs3_en; // @[rename-stage.scala:123:24]
wire [1:0] next_uop_lrs2_rtype; // @[rename-stage.scala:123:24]
wire [1:0] next_uop_lrs1_rtype; // @[rename-stage.scala:123:24]
wire [1:0] next_uop_dst_rtype; // @[rename-stage.scala:123:24]
wire next_uop_ldst_val; // @[rename-stage.scala:123:24]
wire [5:0] next_uop_lrs3; // @[rename-stage.scala:123:24]
wire [5:0] next_uop_lrs2; // @[rename-stage.scala:123:24]
wire [5:0] next_uop_lrs1; // @[rename-stage.scala:123:24]
wire [5:0] next_uop_ldst; // @[rename-stage.scala:123:24]
wire next_uop_ldst_is_rs1; // @[rename-stage.scala:123:24]
wire next_uop_flush_on_commit; // @[rename-stage.scala:123:24]
wire next_uop_is_unique; // @[rename-stage.scala:123:24]
wire next_uop_is_sys_pc2epc; // @[rename-stage.scala:123:24]
wire next_uop_uses_stq; // @[rename-stage.scala:123:24]
wire next_uop_uses_ldq; // @[rename-stage.scala:123:24]
wire next_uop_is_amo; // @[rename-stage.scala:123:24]
wire next_uop_is_fencei; // @[rename-stage.scala:123:24]
wire next_uop_is_fence; // @[rename-stage.scala:123:24]
wire next_uop_mem_signed; // @[rename-stage.scala:123:24]
wire [1:0] next_uop_mem_size; // @[rename-stage.scala:123:24]
wire [4:0] next_uop_mem_cmd; // @[rename-stage.scala:123:24]
wire next_uop_bypassable; // @[rename-stage.scala:123:24]
wire [63:0] next_uop_exc_cause; // @[rename-stage.scala:123:24]
wire next_uop_exception; // @[rename-stage.scala:123:24]
wire [5:0] next_uop_stale_pdst; // @[rename-stage.scala:123:24]
wire next_uop_ppred_busy; // @[rename-stage.scala:123:24]
wire next_uop_prs3_busy; // @[rename-stage.scala:123:24]
wire next_uop_prs2_busy; // @[rename-stage.scala:123:24]
wire next_uop_prs1_busy; // @[rename-stage.scala:123:24]
wire [3:0] next_uop_ppred; // @[rename-stage.scala:123:24]
wire [5:0] next_uop_prs3; // @[rename-stage.scala:123:24]
wire [5:0] next_uop_prs2; // @[rename-stage.scala:123:24]
wire [5:0] next_uop_prs1; // @[rename-stage.scala:123:24]
wire [5:0] next_uop_pdst; // @[rename-stage.scala:123:24]
wire [1:0] next_uop_rxq_idx; // @[rename-stage.scala:123:24]
wire [2:0] next_uop_stq_idx; // @[rename-stage.scala:123:24]
wire [2:0] next_uop_ldq_idx; // @[rename-stage.scala:123:24]
wire [4:0] next_uop_rob_idx; // @[rename-stage.scala:123:24]
wire [11:0] next_uop_csr_addr; // @[rename-stage.scala:123:24]
wire [19:0] next_uop_imm_packed; // @[rename-stage.scala:123:24]
wire next_uop_taken; // @[rename-stage.scala:123:24]
wire [5:0] next_uop_pc_lob; // @[rename-stage.scala:123:24]
wire next_uop_edge_inst; // @[rename-stage.scala:123:24]
wire [3:0] next_uop_ftq_idx; // @[rename-stage.scala:123:24]
wire [2:0] next_uop_br_tag; // @[rename-stage.scala:123:24]
wire next_uop_is_sfb; // @[rename-stage.scala:123:24]
wire next_uop_is_jal; // @[rename-stage.scala:123:24]
wire next_uop_is_jalr; // @[rename-stage.scala:123:24]
wire next_uop_is_br; // @[rename-stage.scala:123:24]
wire next_uop_iw_p2_poisoned; // @[rename-stage.scala:123:24]
wire next_uop_iw_p1_poisoned; // @[rename-stage.scala:123:24]
wire [1:0] next_uop_iw_state; // @[rename-stage.scala:123:24]
wire [9:0] next_uop_fu_code; // @[rename-stage.scala:123:24]
wire [2:0] next_uop_iq_type; // @[rename-stage.scala:123:24]
wire [39:0] next_uop_debug_pc; // @[rename-stage.scala:123:24]
wire next_uop_is_rvc; // @[rename-stage.scala:123:24]
wire [31:0] next_uop_debug_inst; // @[rename-stage.scala:123:24]
wire [31:0] next_uop_inst; // @[rename-stage.scala:123:24]
wire [6:0] next_uop_uopc; // @[rename-stage.scala:123:24]
wire next_uop_ctrl_is_std; // @[rename-stage.scala:123:24]
wire next_uop_ctrl_is_sta; // @[rename-stage.scala:123:24]
wire next_uop_ctrl_is_load; // @[rename-stage.scala:123:24]
wire [2:0] next_uop_ctrl_csr_cmd; // @[rename-stage.scala:123:24]
wire next_uop_ctrl_fcn_dw; // @[rename-stage.scala:123:24]
wire [4:0] next_uop_ctrl_op_fcn; // @[rename-stage.scala:123:24]
wire [2:0] next_uop_ctrl_imm_sel; // @[rename-stage.scala:123:24]
wire [2:0] next_uop_ctrl_op2_sel; // @[rename-stage.scala:123:24]
wire [1:0] next_uop_ctrl_op1_sel; // @[rename-stage.scala:123:24]
wire [3:0] next_uop_ctrl_br_type; // @[rename-stage.scala:123:24]
wire io_kill_0 = io_kill; // @[rename-stage.scala:356:7]
wire io_dec_fire_0_0 = io_dec_fire_0; // @[rename-stage.scala:356:7]
wire [6:0] io_dec_uops_0_uopc_0 = io_dec_uops_0_uopc; // @[rename-stage.scala:356:7]
wire [31:0] io_dec_uops_0_inst_0 = io_dec_uops_0_inst; // @[rename-stage.scala:356:7]
wire [31:0] io_dec_uops_0_debug_inst_0 = io_dec_uops_0_debug_inst; // @[rename-stage.scala:356:7]
wire io_dec_uops_0_is_rvc_0 = io_dec_uops_0_is_rvc; // @[rename-stage.scala:356:7]
wire [39:0] io_dec_uops_0_debug_pc_0 = io_dec_uops_0_debug_pc; // @[rename-stage.scala:356:7]
wire [2:0] io_dec_uops_0_iq_type_0 = io_dec_uops_0_iq_type; // @[rename-stage.scala:356:7]
wire [9:0] io_dec_uops_0_fu_code_0 = io_dec_uops_0_fu_code; // @[rename-stage.scala:356:7]
wire io_dec_uops_0_is_br_0 = io_dec_uops_0_is_br; // @[rename-stage.scala:356:7]
wire io_dec_uops_0_is_jalr_0 = io_dec_uops_0_is_jalr; // @[rename-stage.scala:356:7]
wire io_dec_uops_0_is_jal_0 = io_dec_uops_0_is_jal; // @[rename-stage.scala:356:7]
wire io_dec_uops_0_is_sfb_0 = io_dec_uops_0_is_sfb; // @[rename-stage.scala:356:7]
wire [7:0] io_dec_uops_0_br_mask_0 = io_dec_uops_0_br_mask; // @[rename-stage.scala:356:7]
wire [2:0] io_dec_uops_0_br_tag_0 = io_dec_uops_0_br_tag; // @[rename-stage.scala:356:7]
wire [3:0] io_dec_uops_0_ftq_idx_0 = io_dec_uops_0_ftq_idx; // @[rename-stage.scala:356:7]
wire io_dec_uops_0_edge_inst_0 = io_dec_uops_0_edge_inst; // @[rename-stage.scala:356:7]
wire [5:0] io_dec_uops_0_pc_lob_0 = io_dec_uops_0_pc_lob; // @[rename-stage.scala:356:7]
wire io_dec_uops_0_taken_0 = io_dec_uops_0_taken; // @[rename-stage.scala:356:7]
wire [19:0] io_dec_uops_0_imm_packed_0 = io_dec_uops_0_imm_packed; // @[rename-stage.scala:356:7]
wire io_dec_uops_0_exception_0 = io_dec_uops_0_exception; // @[rename-stage.scala:356:7]
wire [63:0] io_dec_uops_0_exc_cause_0 = io_dec_uops_0_exc_cause; // @[rename-stage.scala:356:7]
wire io_dec_uops_0_bypassable_0 = io_dec_uops_0_bypassable; // @[rename-stage.scala:356:7]
wire [4:0] io_dec_uops_0_mem_cmd_0 = io_dec_uops_0_mem_cmd; // @[rename-stage.scala:356:7]
wire [1:0] io_dec_uops_0_mem_size_0 = io_dec_uops_0_mem_size; // @[rename-stage.scala:356:7]
wire io_dec_uops_0_mem_signed_0 = io_dec_uops_0_mem_signed; // @[rename-stage.scala:356:7]
wire io_dec_uops_0_is_fence_0 = io_dec_uops_0_is_fence; // @[rename-stage.scala:356:7]
wire io_dec_uops_0_is_fencei_0 = io_dec_uops_0_is_fencei; // @[rename-stage.scala:356:7]
wire io_dec_uops_0_is_amo_0 = io_dec_uops_0_is_amo; // @[rename-stage.scala:356:7]
wire io_dec_uops_0_uses_ldq_0 = io_dec_uops_0_uses_ldq; // @[rename-stage.scala:356:7]
wire io_dec_uops_0_uses_stq_0 = io_dec_uops_0_uses_stq; // @[rename-stage.scala:356:7]
wire io_dec_uops_0_is_sys_pc2epc_0 = io_dec_uops_0_is_sys_pc2epc; // @[rename-stage.scala:356:7]
wire io_dec_uops_0_is_unique_0 = io_dec_uops_0_is_unique; // @[rename-stage.scala:356:7]
wire io_dec_uops_0_flush_on_commit_0 = io_dec_uops_0_flush_on_commit; // @[rename-stage.scala:356:7]
wire [5:0] io_dec_uops_0_ldst_0 = io_dec_uops_0_ldst; // @[rename-stage.scala:356:7]
wire [5:0] io_dec_uops_0_lrs1_0 = io_dec_uops_0_lrs1; // @[rename-stage.scala:356:7]
wire [5:0] io_dec_uops_0_lrs2_0 = io_dec_uops_0_lrs2; // @[rename-stage.scala:356:7]
wire [5:0] io_dec_uops_0_lrs3_0 = io_dec_uops_0_lrs3; // @[rename-stage.scala:356:7]
wire io_dec_uops_0_ldst_val_0 = io_dec_uops_0_ldst_val; // @[rename-stage.scala:356:7]
wire [1:0] io_dec_uops_0_dst_rtype_0 = io_dec_uops_0_dst_rtype; // @[rename-stage.scala:356:7]
wire [1:0] io_dec_uops_0_lrs1_rtype_0 = io_dec_uops_0_lrs1_rtype; // @[rename-stage.scala:356:7]
wire [1:0] io_dec_uops_0_lrs2_rtype_0 = io_dec_uops_0_lrs2_rtype; // @[rename-stage.scala:356:7]
wire io_dec_uops_0_frs3_en_0 = io_dec_uops_0_frs3_en; // @[rename-stage.scala:356:7]
wire io_dec_uops_0_fp_val_0 = io_dec_uops_0_fp_val; // @[rename-stage.scala:356:7]
wire io_dec_uops_0_fp_single_0 = io_dec_uops_0_fp_single; // @[rename-stage.scala:356:7]
wire io_dec_uops_0_xcpt_pf_if_0 = io_dec_uops_0_xcpt_pf_if; // @[rename-stage.scala:356:7]
wire io_dec_uops_0_xcpt_ae_if_0 = io_dec_uops_0_xcpt_ae_if; // @[rename-stage.scala:356:7]
wire io_dec_uops_0_bp_debug_if_0 = io_dec_uops_0_bp_debug_if; // @[rename-stage.scala:356:7]
wire io_dec_uops_0_bp_xcpt_if_0 = io_dec_uops_0_bp_xcpt_if; // @[rename-stage.scala:356:7]
wire [1:0] io_dec_uops_0_debug_fsrc_0 = io_dec_uops_0_debug_fsrc; // @[rename-stage.scala:356:7]
wire [7:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[rename-stage.scala:356:7]
wire [7:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[rename-stage.scala:356:7]
wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[rename-stage.scala:356:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[rename-stage.scala:356:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[rename-stage.scala:356:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[rename-stage.scala:356:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[rename-stage.scala:356:7]
wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[rename-stage.scala:356:7]
wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[rename-stage.scala:356:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[rename-stage.scala:356:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[rename-stage.scala:356:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[rename-stage.scala:356:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[rename-stage.scala:356:7]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[rename-stage.scala:356:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[rename-stage.scala:356:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[rename-stage.scala:356:7]
wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[rename-stage.scala:356:7]
wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[rename-stage.scala:356:7]
wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[rename-stage.scala:356:7]
wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[rename-stage.scala:356:7]
wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[rename-stage.scala:356:7]
wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[rename-stage.scala:356:7]
wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[rename-stage.scala:356:7]
wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[rename-stage.scala:356:7]
wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[rename-stage.scala:356:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[rename-stage.scala:356:7]
wire [7:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[rename-stage.scala:356:7]
wire [2:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[rename-stage.scala:356:7]
wire [3:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[rename-stage.scala:356:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[rename-stage.scala:356:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[rename-stage.scala:356:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[rename-stage.scala:356:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[rename-stage.scala:356:7]
wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[rename-stage.scala:356:7]
wire [4:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[rename-stage.scala:356:7]
wire [2:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[rename-stage.scala:356:7]
wire [2:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[rename-stage.scala:356:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[rename-stage.scala:356:7]
wire [5:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[rename-stage.scala:356:7]
wire [5:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[rename-stage.scala:356:7]
wire [5:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[rename-stage.scala:356:7]
wire [5:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[rename-stage.scala:356:7]
wire [3:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[rename-stage.scala:356:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[rename-stage.scala:356:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[rename-stage.scala:356:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[rename-stage.scala:356:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[rename-stage.scala:356:7]
wire [5:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[rename-stage.scala:356:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[rename-stage.scala:356:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[rename-stage.scala:356:7]
wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[rename-stage.scala:356:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[rename-stage.scala:356:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[rename-stage.scala:356:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[rename-stage.scala:356:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[rename-stage.scala:356:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[rename-stage.scala:356:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[rename-stage.scala:356:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[rename-stage.scala:356:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[rename-stage.scala:356:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[rename-stage.scala:356:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[rename-stage.scala:356:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[rename-stage.scala:356:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[rename-stage.scala:356:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[rename-stage.scala:356:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[rename-stage.scala:356:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[rename-stage.scala:356:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[rename-stage.scala:356:7]
wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[rename-stage.scala:356:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[rename-stage.scala:356:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[rename-stage.scala:356:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[rename-stage.scala:356:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[rename-stage.scala:356:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[rename-stage.scala:356:7]
wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[rename-stage.scala:356:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[rename-stage.scala:356:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[rename-stage.scala:356:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[rename-stage.scala:356:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[rename-stage.scala:356:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[rename-stage.scala:356:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[rename-stage.scala:356:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[rename-stage.scala:356:7]
wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[rename-stage.scala:356:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[rename-stage.scala:356:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[rename-stage.scala:356:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[rename-stage.scala:356:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[rename-stage.scala:356:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[rename-stage.scala:356:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[rename-stage.scala:356:7]
wire io_dis_fire_0_0 = io_dis_fire_0; // @[rename-stage.scala:356:7]
wire io_dis_ready_0 = io_dis_ready; // @[rename-stage.scala:356:7]
wire io_com_valids_0_0 = io_com_valids_0; // @[rename-stage.scala:356:7]
wire [6:0] io_com_uops_0_uopc_0 = io_com_uops_0_uopc; // @[rename-stage.scala:356:7]
wire [31:0] io_com_uops_0_inst_0 = io_com_uops_0_inst; // @[rename-stage.scala:356:7]
wire [31:0] io_com_uops_0_debug_inst_0 = io_com_uops_0_debug_inst; // @[rename-stage.scala:356:7]
wire io_com_uops_0_is_rvc_0 = io_com_uops_0_is_rvc; // @[rename-stage.scala:356:7]
wire [39:0] io_com_uops_0_debug_pc_0 = io_com_uops_0_debug_pc; // @[rename-stage.scala:356:7]
wire [2:0] io_com_uops_0_iq_type_0 = io_com_uops_0_iq_type; // @[rename-stage.scala:356:7]
wire [9:0] io_com_uops_0_fu_code_0 = io_com_uops_0_fu_code; // @[rename-stage.scala:356:7]
wire [3:0] io_com_uops_0_ctrl_br_type_0 = io_com_uops_0_ctrl_br_type; // @[rename-stage.scala:356:7]
wire [1:0] io_com_uops_0_ctrl_op1_sel_0 = io_com_uops_0_ctrl_op1_sel; // @[rename-stage.scala:356:7]
wire [2:0] io_com_uops_0_ctrl_op2_sel_0 = io_com_uops_0_ctrl_op2_sel; // @[rename-stage.scala:356:7]
wire [2:0] io_com_uops_0_ctrl_imm_sel_0 = io_com_uops_0_ctrl_imm_sel; // @[rename-stage.scala:356:7]
wire [4:0] io_com_uops_0_ctrl_op_fcn_0 = io_com_uops_0_ctrl_op_fcn; // @[rename-stage.scala:356:7]
wire io_com_uops_0_ctrl_fcn_dw_0 = io_com_uops_0_ctrl_fcn_dw; // @[rename-stage.scala:356:7]
wire [2:0] io_com_uops_0_ctrl_csr_cmd_0 = io_com_uops_0_ctrl_csr_cmd; // @[rename-stage.scala:356:7]
wire io_com_uops_0_ctrl_is_load_0 = io_com_uops_0_ctrl_is_load; // @[rename-stage.scala:356:7]
wire io_com_uops_0_ctrl_is_sta_0 = io_com_uops_0_ctrl_is_sta; // @[rename-stage.scala:356:7]
wire io_com_uops_0_ctrl_is_std_0 = io_com_uops_0_ctrl_is_std; // @[rename-stage.scala:356:7]
wire [1:0] io_com_uops_0_iw_state_0 = io_com_uops_0_iw_state; // @[rename-stage.scala:356:7]
wire io_com_uops_0_iw_p1_poisoned_0 = io_com_uops_0_iw_p1_poisoned; // @[rename-stage.scala:356:7]
wire io_com_uops_0_iw_p2_poisoned_0 = io_com_uops_0_iw_p2_poisoned; // @[rename-stage.scala:356:7]
wire io_com_uops_0_is_br_0 = io_com_uops_0_is_br; // @[rename-stage.scala:356:7]
wire io_com_uops_0_is_jalr_0 = io_com_uops_0_is_jalr; // @[rename-stage.scala:356:7]
wire io_com_uops_0_is_jal_0 = io_com_uops_0_is_jal; // @[rename-stage.scala:356:7]
wire io_com_uops_0_is_sfb_0 = io_com_uops_0_is_sfb; // @[rename-stage.scala:356:7]
wire [7:0] io_com_uops_0_br_mask_0 = io_com_uops_0_br_mask; // @[rename-stage.scala:356:7]
wire [2:0] io_com_uops_0_br_tag_0 = io_com_uops_0_br_tag; // @[rename-stage.scala:356:7]
wire [3:0] io_com_uops_0_ftq_idx_0 = io_com_uops_0_ftq_idx; // @[rename-stage.scala:356:7]
wire io_com_uops_0_edge_inst_0 = io_com_uops_0_edge_inst; // @[rename-stage.scala:356:7]
wire [5:0] io_com_uops_0_pc_lob_0 = io_com_uops_0_pc_lob; // @[rename-stage.scala:356:7]
wire io_com_uops_0_taken_0 = io_com_uops_0_taken; // @[rename-stage.scala:356:7]
wire [19:0] io_com_uops_0_imm_packed_0 = io_com_uops_0_imm_packed; // @[rename-stage.scala:356:7]
wire [11:0] io_com_uops_0_csr_addr_0 = io_com_uops_0_csr_addr; // @[rename-stage.scala:356:7]
wire [4:0] io_com_uops_0_rob_idx_0 = io_com_uops_0_rob_idx; // @[rename-stage.scala:356:7]
wire [2:0] io_com_uops_0_ldq_idx_0 = io_com_uops_0_ldq_idx; // @[rename-stage.scala:356:7]
wire [2:0] io_com_uops_0_stq_idx_0 = io_com_uops_0_stq_idx; // @[rename-stage.scala:356:7]
wire [1:0] io_com_uops_0_rxq_idx_0 = io_com_uops_0_rxq_idx; // @[rename-stage.scala:356:7]
wire [5:0] io_com_uops_0_pdst_0 = io_com_uops_0_pdst; // @[rename-stage.scala:356:7]
wire [5:0] io_com_uops_0_prs1_0 = io_com_uops_0_prs1; // @[rename-stage.scala:356:7]
wire [5:0] io_com_uops_0_prs2_0 = io_com_uops_0_prs2; // @[rename-stage.scala:356:7]
wire [5:0] io_com_uops_0_prs3_0 = io_com_uops_0_prs3; // @[rename-stage.scala:356:7]
wire [3:0] io_com_uops_0_ppred_0 = io_com_uops_0_ppred; // @[rename-stage.scala:356:7]
wire io_com_uops_0_prs1_busy_0 = io_com_uops_0_prs1_busy; // @[rename-stage.scala:356:7]
wire io_com_uops_0_prs2_busy_0 = io_com_uops_0_prs2_busy; // @[rename-stage.scala:356:7]
wire io_com_uops_0_prs3_busy_0 = io_com_uops_0_prs3_busy; // @[rename-stage.scala:356:7]
wire io_com_uops_0_ppred_busy_0 = io_com_uops_0_ppred_busy; // @[rename-stage.scala:356:7]
wire [5:0] io_com_uops_0_stale_pdst_0 = io_com_uops_0_stale_pdst; // @[rename-stage.scala:356:7]
wire io_com_uops_0_exception_0 = io_com_uops_0_exception; // @[rename-stage.scala:356:7]
wire [63:0] io_com_uops_0_exc_cause_0 = io_com_uops_0_exc_cause; // @[rename-stage.scala:356:7]
wire io_com_uops_0_bypassable_0 = io_com_uops_0_bypassable; // @[rename-stage.scala:356:7]
wire [4:0] io_com_uops_0_mem_cmd_0 = io_com_uops_0_mem_cmd; // @[rename-stage.scala:356:7]
wire [1:0] io_com_uops_0_mem_size_0 = io_com_uops_0_mem_size; // @[rename-stage.scala:356:7]
wire io_com_uops_0_mem_signed_0 = io_com_uops_0_mem_signed; // @[rename-stage.scala:356:7]
wire io_com_uops_0_is_fence_0 = io_com_uops_0_is_fence; // @[rename-stage.scala:356:7]
wire io_com_uops_0_is_fencei_0 = io_com_uops_0_is_fencei; // @[rename-stage.scala:356:7]
wire io_com_uops_0_is_amo_0 = io_com_uops_0_is_amo; // @[rename-stage.scala:356:7]
wire io_com_uops_0_uses_ldq_0 = io_com_uops_0_uses_ldq; // @[rename-stage.scala:356:7]
wire io_com_uops_0_uses_stq_0 = io_com_uops_0_uses_stq; // @[rename-stage.scala:356:7]
wire io_com_uops_0_is_sys_pc2epc_0 = io_com_uops_0_is_sys_pc2epc; // @[rename-stage.scala:356:7]
wire io_com_uops_0_is_unique_0 = io_com_uops_0_is_unique; // @[rename-stage.scala:356:7]
wire io_com_uops_0_flush_on_commit_0 = io_com_uops_0_flush_on_commit; // @[rename-stage.scala:356:7]
wire io_com_uops_0_ldst_is_rs1_0 = io_com_uops_0_ldst_is_rs1; // @[rename-stage.scala:356:7]
wire [5:0] io_com_uops_0_ldst_0 = io_com_uops_0_ldst; // @[rename-stage.scala:356:7]
wire [5:0] io_com_uops_0_lrs1_0 = io_com_uops_0_lrs1; // @[rename-stage.scala:356:7]
wire [5:0] io_com_uops_0_lrs2_0 = io_com_uops_0_lrs2; // @[rename-stage.scala:356:7]
wire [5:0] io_com_uops_0_lrs3_0 = io_com_uops_0_lrs3; // @[rename-stage.scala:356:7]
wire io_com_uops_0_ldst_val_0 = io_com_uops_0_ldst_val; // @[rename-stage.scala:356:7]
wire [1:0] io_com_uops_0_dst_rtype_0 = io_com_uops_0_dst_rtype; // @[rename-stage.scala:356:7]
wire [1:0] io_com_uops_0_lrs1_rtype_0 = io_com_uops_0_lrs1_rtype; // @[rename-stage.scala:356:7]
wire [1:0] io_com_uops_0_lrs2_rtype_0 = io_com_uops_0_lrs2_rtype; // @[rename-stage.scala:356:7]
wire io_com_uops_0_frs3_en_0 = io_com_uops_0_frs3_en; // @[rename-stage.scala:356:7]
wire io_com_uops_0_fp_val_0 = io_com_uops_0_fp_val; // @[rename-stage.scala:356:7]
wire io_com_uops_0_fp_single_0 = io_com_uops_0_fp_single; // @[rename-stage.scala:356:7]
wire io_com_uops_0_xcpt_pf_if_0 = io_com_uops_0_xcpt_pf_if; // @[rename-stage.scala:356:7]
wire io_com_uops_0_xcpt_ae_if_0 = io_com_uops_0_xcpt_ae_if; // @[rename-stage.scala:356:7]
wire io_com_uops_0_xcpt_ma_if_0 = io_com_uops_0_xcpt_ma_if; // @[rename-stage.scala:356:7]
wire io_com_uops_0_bp_debug_if_0 = io_com_uops_0_bp_debug_if; // @[rename-stage.scala:356:7]
wire io_com_uops_0_bp_xcpt_if_0 = io_com_uops_0_bp_xcpt_if; // @[rename-stage.scala:356:7]
wire [1:0] io_com_uops_0_debug_fsrc_0 = io_com_uops_0_debug_fsrc; // @[rename-stage.scala:356:7]
wire [1:0] io_com_uops_0_debug_tsrc_0 = io_com_uops_0_debug_tsrc; // @[rename-stage.scala:356:7]
wire io_rbk_valids_0_0 = io_rbk_valids_0; // @[rename-stage.scala:356:7]
wire io_rollback_0 = io_rollback; // @[rename-stage.scala:356:7]
wire io_debug_rob_empty_0 = io_debug_rob_empty; // @[rename-stage.scala:356:7]
wire [15:0] io_debug_freelist = 16'h0; // @[rename-stage.scala:356:7]
wire [15:0] io_debug_isprlist = 16'h0; // @[rename-stage.scala:356:7]
wire [15:0] io_debug_busytable = 16'h0; // @[rename-stage.scala:356:7]
wire [63:0] io_wakeups_0_bits_uop_exc_cause = 64'h0; // @[rename-stage.scala:60:14, :356:7]
wire [63:0] io_wakeups_0_bits_data = 64'h0; // @[rename-stage.scala:60:14, :356:7]
wire [63:0] io_wakeups_0_bits_fflags_bits_uop_exc_cause = 64'h0; // @[rename-stage.scala:60:14, :356:7]
wire [19:0] io_wakeups_0_bits_uop_imm_packed = 20'h0; // @[rename-stage.scala:60:14, :356:7]
wire [19:0] io_wakeups_0_bits_fflags_bits_uop_imm_packed = 20'h0; // @[rename-stage.scala:60:14, :356:7]
wire [7:0] io_wakeups_0_bits_uop_br_mask = 8'h0; // @[rename-stage.scala:60:14, :356:7, :402:{47,65}]
wire [7:0] io_wakeups_0_bits_fflags_bits_uop_br_mask = 8'h0; // @[rename-stage.scala:60:14, :356:7, :402:{47,65}]
wire [7:0] lo_1 = 8'h0; // @[rename-stage.scala:60:14, :356:7, :402:{47,65}]
wire [7:0] hi_1 = 8'h0; // @[rename-stage.scala:60:14, :356:7, :402:{47,65}]
wire [7:0] lo_2 = 8'h0; // @[rename-stage.scala:60:14, :356:7, :402:{47,65}]
wire [7:0] hi_2 = 8'h0; // @[rename-stage.scala:60:14, :356:7, :402:{47,65}]
wire [9:0] io_wakeups_0_bits_uop_fu_code = 10'h0; // @[rename-stage.scala:60:14, :356:7]
wire [9:0] io_wakeups_0_bits_fflags_bits_uop_fu_code = 10'h0; // @[rename-stage.scala:60:14, :356:7]
wire [39:0] io_wakeups_0_bits_uop_debug_pc = 40'h0; // @[rename-stage.scala:60:14, :356:7]
wire [39:0] io_wakeups_0_bits_fflags_bits_uop_debug_pc = 40'h0; // @[rename-stage.scala:60:14, :356:7]
wire [31:0] io_wakeups_0_bits_uop_inst = 32'h0; // @[rename-stage.scala:60:14, :356:7]
wire [31:0] io_wakeups_0_bits_uop_debug_inst = 32'h0; // @[rename-stage.scala:60:14, :356:7]
wire [31:0] io_wakeups_0_bits_fflags_bits_uop_inst = 32'h0; // @[rename-stage.scala:60:14, :356:7]
wire [31:0] io_wakeups_0_bits_fflags_bits_uop_debug_inst = 32'h0; // @[rename-stage.scala:60:14, :356:7]
wire [6:0] io_wakeups_0_bits_uop_uopc = 7'h0; // @[rename-stage.scala:60:14, :356:7]
wire [6:0] io_wakeups_0_bits_fflags_bits_uop_uopc = 7'h0; // @[rename-stage.scala:60:14, :356:7]
wire _io_ren2_uops_0_ppred_busy_T_1 = 1'h1; // @[rename-stage.scala:390:92]
wire [5:0] io_dec_uops_0_pdst = 6'h0; // @[rename-stage.scala:356:7]
wire [5:0] io_dec_uops_0_prs1 = 6'h0; // @[rename-stage.scala:356:7]
wire [5:0] io_dec_uops_0_prs2 = 6'h0; // @[rename-stage.scala:356:7]
wire [5:0] io_dec_uops_0_prs3 = 6'h0; // @[rename-stage.scala:356:7]
wire [5:0] io_dec_uops_0_stale_pdst = 6'h0; // @[rename-stage.scala:356:7]
wire [5:0] io_wakeups_0_bits_uop_pc_lob = 6'h0; // @[rename-stage.scala:356:7]
wire [5:0] io_wakeups_0_bits_uop_pdst = 6'h0; // @[rename-stage.scala:356:7]
wire [5:0] io_wakeups_0_bits_uop_prs1 = 6'h0; // @[rename-stage.scala:356:7]
wire [5:0] io_wakeups_0_bits_uop_prs2 = 6'h0; // @[rename-stage.scala:356:7]
wire [5:0] io_wakeups_0_bits_uop_prs3 = 6'h0; // @[rename-stage.scala:356:7]
wire [5:0] io_wakeups_0_bits_uop_stale_pdst = 6'h0; // @[rename-stage.scala:356:7]
wire [5:0] io_wakeups_0_bits_uop_ldst = 6'h0; // @[rename-stage.scala:356:7]
wire [5:0] io_wakeups_0_bits_uop_lrs1 = 6'h0; // @[rename-stage.scala:356:7]
wire [5:0] io_wakeups_0_bits_uop_lrs2 = 6'h0; // @[rename-stage.scala:356:7]
wire [5:0] io_wakeups_0_bits_uop_lrs3 = 6'h0; // @[rename-stage.scala:356:7]
wire [5:0] io_wakeups_0_bits_fflags_bits_uop_pc_lob = 6'h0; // @[rename-stage.scala:356:7]
wire [5:0] io_wakeups_0_bits_fflags_bits_uop_pdst = 6'h0; // @[rename-stage.scala:356:7]
wire [5:0] io_wakeups_0_bits_fflags_bits_uop_prs1 = 6'h0; // @[rename-stage.scala:356:7]
wire [5:0] io_wakeups_0_bits_fflags_bits_uop_prs2 = 6'h0; // @[rename-stage.scala:356:7]
wire [5:0] io_wakeups_0_bits_fflags_bits_uop_prs3 = 6'h0; // @[rename-stage.scala:356:7]
wire [5:0] io_wakeups_0_bits_fflags_bits_uop_stale_pdst = 6'h0; // @[rename-stage.scala:356:7]
wire [5:0] io_wakeups_0_bits_fflags_bits_uop_ldst = 6'h0; // @[rename-stage.scala:356:7]
wire [5:0] io_wakeups_0_bits_fflags_bits_uop_lrs1 = 6'h0; // @[rename-stage.scala:356:7]
wire [5:0] io_wakeups_0_bits_fflags_bits_uop_lrs2 = 6'h0; // @[rename-stage.scala:356:7]
wire [5:0] io_wakeups_0_bits_fflags_bits_uop_lrs3 = 6'h0; // @[rename-stage.scala:356:7]
wire [5:0] ren1_uops_0_pdst = 6'h0; // @[rename-stage.scala:101:29]
wire [5:0] ren1_uops_0_prs1 = 6'h0; // @[rename-stage.scala:101:29]
wire [5:0] ren1_uops_0_prs2 = 6'h0; // @[rename-stage.scala:101:29]
wire [5:0] ren1_uops_0_prs3 = 6'h0; // @[rename-stage.scala:101:29]
wire [5:0] ren1_uops_0_stale_pdst = 6'h0; // @[rename-stage.scala:101:29]
wire [11:0] io_dec_uops_0_csr_addr = 12'h0; // @[rename-stage.scala:356:7]
wire [11:0] io_wakeups_0_bits_uop_csr_addr = 12'h0; // @[rename-stage.scala:356:7]
wire [11:0] io_wakeups_0_bits_fflags_bits_uop_csr_addr = 12'h0; // @[rename-stage.scala:356:7]
wire [11:0] ren1_uops_0_csr_addr = 12'h0; // @[rename-stage.scala:101:29]
wire io_ren_stalls_0 = 1'h0; // @[rename-stage.scala:356:7]
wire io_dec_uops_0_ctrl_fcn_dw = 1'h0; // @[rename-stage.scala:356:7]
wire io_dec_uops_0_ctrl_is_load = 1'h0; // @[rename-stage.scala:356:7]
wire io_dec_uops_0_ctrl_is_sta = 1'h0; // @[rename-stage.scala:356:7]
wire io_dec_uops_0_ctrl_is_std = 1'h0; // @[rename-stage.scala:356:7]
wire io_dec_uops_0_iw_p1_poisoned = 1'h0; // @[rename-stage.scala:356:7]
wire io_dec_uops_0_iw_p2_poisoned = 1'h0; // @[rename-stage.scala:356:7]
wire io_dec_uops_0_prs1_busy = 1'h0; // @[rename-stage.scala:356:7]
wire io_dec_uops_0_prs2_busy = 1'h0; // @[rename-stage.scala:356:7]
wire io_dec_uops_0_prs3_busy = 1'h0; // @[rename-stage.scala:356:7]
wire io_dec_uops_0_ppred_busy = 1'h0; // @[rename-stage.scala:356:7]
wire io_dec_uops_0_ldst_is_rs1 = 1'h0; // @[rename-stage.scala:356:7]
wire io_dec_uops_0_xcpt_ma_if = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_valid = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_uop_is_rvc = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_uop_ctrl_fcn_dw = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_uop_ctrl_is_load = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_uop_ctrl_is_sta = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_uop_ctrl_is_std = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_uop_iw_p1_poisoned = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_uop_iw_p2_poisoned = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_uop_is_br = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_uop_is_jalr = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_uop_is_jal = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_uop_is_sfb = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_uop_edge_inst = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_uop_taken = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_uop_prs1_busy = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_uop_prs2_busy = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_uop_prs3_busy = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_uop_ppred_busy = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_uop_exception = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_uop_bypassable = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_uop_mem_signed = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_uop_is_fence = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_uop_is_fencei = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_uop_is_amo = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_uop_uses_ldq = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_uop_uses_stq = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_uop_is_sys_pc2epc = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_uop_is_unique = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_uop_flush_on_commit = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_uop_ldst_is_rs1 = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_uop_ldst_val = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_uop_frs3_en = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_uop_fp_val = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_uop_fp_single = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_uop_xcpt_pf_if = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_uop_xcpt_ae_if = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_uop_xcpt_ma_if = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_uop_bp_debug_if = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_uop_bp_xcpt_if = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_predicated = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_fflags_valid = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_fflags_bits_uop_is_rvc = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_fflags_bits_uop_is_br = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_fflags_bits_uop_is_jalr = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_fflags_bits_uop_is_jal = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_fflags_bits_uop_is_sfb = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_fflags_bits_uop_edge_inst = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_fflags_bits_uop_taken = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_fflags_bits_uop_exception = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_fflags_bits_uop_bypassable = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_fflags_bits_uop_mem_signed = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_fflags_bits_uop_is_fence = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_fflags_bits_uop_is_fencei = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_fflags_bits_uop_is_amo = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_fflags_bits_uop_uses_stq = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_fflags_bits_uop_is_unique = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_fflags_bits_uop_ldst_val = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_fflags_bits_uop_frs3_en = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_fflags_bits_uop_fp_val = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_fflags_bits_uop_fp_single = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[rename-stage.scala:356:7]
wire io_wakeups_0_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[rename-stage.scala:356:7]
wire ren1_uops_0_ctrl_fcn_dw = 1'h0; // @[rename-stage.scala:101:29]
wire ren1_uops_0_ctrl_is_load = 1'h0; // @[rename-stage.scala:101:29]
wire ren1_uops_0_ctrl_is_sta = 1'h0; // @[rename-stage.scala:101:29]
wire ren1_uops_0_ctrl_is_std = 1'h0; // @[rename-stage.scala:101:29]
wire ren1_uops_0_iw_p1_poisoned = 1'h0; // @[rename-stage.scala:101:29]
wire ren1_uops_0_iw_p2_poisoned = 1'h0; // @[rename-stage.scala:101:29]
wire ren1_uops_0_prs1_busy = 1'h0; // @[rename-stage.scala:101:29]
wire ren1_uops_0_prs2_busy = 1'h0; // @[rename-stage.scala:101:29]
wire ren1_uops_0_prs3_busy = 1'h0; // @[rename-stage.scala:101:29]
wire ren1_uops_0_ppred_busy = 1'h0; // @[rename-stage.scala:101:29]
wire ren1_uops_0_ldst_is_rs1 = 1'h0; // @[rename-stage.scala:101:29]
wire ren1_uops_0_xcpt_ma_if = 1'h0; // @[rename-stage.scala:101:29]
wire ren2_alloc_reqs_0 = 1'h0; // @[rename-stage.scala:109:29]
wire _busy_table_WIRE_0 = 1'h0; // @[rename-stage.scala:368:35]
wire _busy_table_WIRE_1 = 1'h0; // @[rename-stage.scala:368:35]
wire _busy_table_WIRE_2 = 1'h0; // @[rename-stage.scala:368:35]
wire _busy_table_WIRE_3 = 1'h0; // @[rename-stage.scala:368:35]
wire _busy_table_WIRE_4 = 1'h0; // @[rename-stage.scala:368:35]
wire _busy_table_WIRE_5 = 1'h0; // @[rename-stage.scala:368:35]
wire _busy_table_WIRE_6 = 1'h0; // @[rename-stage.scala:368:35]
wire _busy_table_WIRE_7 = 1'h0; // @[rename-stage.scala:368:35]
wire _busy_table_WIRE_8 = 1'h0; // @[rename-stage.scala:368:35]
wire _busy_table_WIRE_9 = 1'h0; // @[rename-stage.scala:368:35]
wire _busy_table_WIRE_10 = 1'h0; // @[rename-stage.scala:368:35]
wire _busy_table_WIRE_11 = 1'h0; // @[rename-stage.scala:368:35]
wire _busy_table_WIRE_12 = 1'h0; // @[rename-stage.scala:368:35]
wire _busy_table_WIRE_13 = 1'h0; // @[rename-stage.scala:368:35]
wire _busy_table_WIRE_14 = 1'h0; // @[rename-stage.scala:368:35]
wire _busy_table_WIRE_15 = 1'h0; // @[rename-stage.scala:368:35]
wire _to_busy_WIRE_0 = 1'h0; // @[rename-stage.scala:369:33]
wire _to_busy_WIRE_1 = 1'h0; // @[rename-stage.scala:369:33]
wire _to_busy_WIRE_2 = 1'h0; // @[rename-stage.scala:369:33]
wire _to_busy_WIRE_3 = 1'h0; // @[rename-stage.scala:369:33]
wire _to_busy_WIRE_4 = 1'h0; // @[rename-stage.scala:369:33]
wire _to_busy_WIRE_5 = 1'h0; // @[rename-stage.scala:369:33]
wire _to_busy_WIRE_6 = 1'h0; // @[rename-stage.scala:369:33]
wire _to_busy_WIRE_7 = 1'h0; // @[rename-stage.scala:369:33]
wire _to_busy_WIRE_8 = 1'h0; // @[rename-stage.scala:369:33]
wire _to_busy_WIRE_9 = 1'h0; // @[rename-stage.scala:369:33]
wire _to_busy_WIRE_10 = 1'h0; // @[rename-stage.scala:369:33]
wire _to_busy_WIRE_11 = 1'h0; // @[rename-stage.scala:369:33]
wire _to_busy_WIRE_12 = 1'h0; // @[rename-stage.scala:369:33]
wire _to_busy_WIRE_13 = 1'h0; // @[rename-stage.scala:369:33]
wire _to_busy_WIRE_14 = 1'h0; // @[rename-stage.scala:369:33]
wire _to_busy_WIRE_15 = 1'h0; // @[rename-stage.scala:369:33]
wire to_busy_0 = 1'h0; // @[rename-stage.scala:369:25]
wire to_busy_1 = 1'h0; // @[rename-stage.scala:369:25]
wire to_busy_2 = 1'h0; // @[rename-stage.scala:369:25]
wire to_busy_3 = 1'h0; // @[rename-stage.scala:369:25]
wire to_busy_4 = 1'h0; // @[rename-stage.scala:369:25]
wire to_busy_5 = 1'h0; // @[rename-stage.scala:369:25]
wire to_busy_6 = 1'h0; // @[rename-stage.scala:369:25]
wire to_busy_7 = 1'h0; // @[rename-stage.scala:369:25]
wire to_busy_8 = 1'h0; // @[rename-stage.scala:369:25]
wire to_busy_9 = 1'h0; // @[rename-stage.scala:369:25]
wire to_busy_10 = 1'h0; // @[rename-stage.scala:369:25]
wire to_busy_11 = 1'h0; // @[rename-stage.scala:369:25]
wire to_busy_12 = 1'h0; // @[rename-stage.scala:369:25]
wire to_busy_13 = 1'h0; // @[rename-stage.scala:369:25]
wire to_busy_14 = 1'h0; // @[rename-stage.scala:369:25]
wire to_busy_15 = 1'h0; // @[rename-stage.scala:369:25]
wire _unbusy_WIRE_0 = 1'h0; // @[rename-stage.scala:370:32]
wire _unbusy_WIRE_1 = 1'h0; // @[rename-stage.scala:370:32]
wire _unbusy_WIRE_2 = 1'h0; // @[rename-stage.scala:370:32]
wire _unbusy_WIRE_3 = 1'h0; // @[rename-stage.scala:370:32]
wire _unbusy_WIRE_4 = 1'h0; // @[rename-stage.scala:370:32]
wire _unbusy_WIRE_5 = 1'h0; // @[rename-stage.scala:370:32]
wire _unbusy_WIRE_6 = 1'h0; // @[rename-stage.scala:370:32]
wire _unbusy_WIRE_7 = 1'h0; // @[rename-stage.scala:370:32]
wire _unbusy_WIRE_8 = 1'h0; // @[rename-stage.scala:370:32]
wire _unbusy_WIRE_9 = 1'h0; // @[rename-stage.scala:370:32]
wire _unbusy_WIRE_10 = 1'h0; // @[rename-stage.scala:370:32]
wire _unbusy_WIRE_11 = 1'h0; // @[rename-stage.scala:370:32]
wire _unbusy_WIRE_12 = 1'h0; // @[rename-stage.scala:370:32]
wire _unbusy_WIRE_13 = 1'h0; // @[rename-stage.scala:370:32]
wire _unbusy_WIRE_14 = 1'h0; // @[rename-stage.scala:370:32]
wire _unbusy_WIRE_15 = 1'h0; // @[rename-stage.scala:370:32]
wire unbusy_0 = 1'h0; // @[rename-stage.scala:370:24]
wire unbusy_1 = 1'h0; // @[rename-stage.scala:370:24]
wire unbusy_2 = 1'h0; // @[rename-stage.scala:370:24]
wire unbusy_3 = 1'h0; // @[rename-stage.scala:370:24]
wire unbusy_4 = 1'h0; // @[rename-stage.scala:370:24]
wire unbusy_5 = 1'h0; // @[rename-stage.scala:370:24]
wire unbusy_6 = 1'h0; // @[rename-stage.scala:370:24]
wire unbusy_7 = 1'h0; // @[rename-stage.scala:370:24]
wire unbusy_8 = 1'h0; // @[rename-stage.scala:370:24]
wire unbusy_9 = 1'h0; // @[rename-stage.scala:370:24]
wire unbusy_10 = 1'h0; // @[rename-stage.scala:370:24]
wire unbusy_11 = 1'h0; // @[rename-stage.scala:370:24]
wire unbusy_12 = 1'h0; // @[rename-stage.scala:370:24]
wire unbusy_13 = 1'h0; // @[rename-stage.scala:370:24]
wire unbusy_14 = 1'h0; // @[rename-stage.scala:370:24]
wire unbusy_15 = 1'h0; // @[rename-stage.scala:370:24]
wire _is_sfb_br_T_1 = 1'h0; // @[micro-op.scala:109:42]
wire is_sfb_br = 1'h0; // @[rename-stage.scala:378:44]
wire _is_sfb_shadow_T_2 = 1'h0; // @[micro-op.scala:110:43]
wire is_sfb_shadow = 1'h0; // @[rename-stage.scala:379:52]
wire [4:0] io_dec_uops_0_ctrl_op_fcn = 5'h0; // @[rename-stage.scala:356:7]
wire [4:0] io_dec_uops_0_rob_idx = 5'h0; // @[rename-stage.scala:356:7]
wire [4:0] io_wakeups_0_bits_uop_ctrl_op_fcn = 5'h0; // @[rename-stage.scala:356:7]
wire [4:0] io_wakeups_0_bits_uop_rob_idx = 5'h0; // @[rename-stage.scala:356:7]
wire [4:0] io_wakeups_0_bits_uop_mem_cmd = 5'h0; // @[rename-stage.scala:356:7]
wire [4:0] io_wakeups_0_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[rename-stage.scala:356:7]
wire [4:0] io_wakeups_0_bits_fflags_bits_uop_rob_idx = 5'h0; // @[rename-stage.scala:356:7]
wire [4:0] io_wakeups_0_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[rename-stage.scala:356:7]
wire [4:0] io_wakeups_0_bits_fflags_bits_flags = 5'h0; // @[rename-stage.scala:356:7]
wire [4:0] ren1_uops_0_ctrl_op_fcn = 5'h0; // @[rename-stage.scala:101:29]
wire [4:0] ren1_uops_0_rob_idx = 5'h0; // @[rename-stage.scala:101:29]
wire [2:0] io_dec_uops_0_ctrl_op2_sel = 3'h0; // @[rename-stage.scala:356:7]
wire [2:0] io_dec_uops_0_ctrl_imm_sel = 3'h0; // @[rename-stage.scala:356:7]
wire [2:0] io_dec_uops_0_ctrl_csr_cmd = 3'h0; // @[rename-stage.scala:356:7]
wire [2:0] io_dec_uops_0_ldq_idx = 3'h0; // @[rename-stage.scala:356:7]
wire [2:0] io_dec_uops_0_stq_idx = 3'h0; // @[rename-stage.scala:356:7]
wire [2:0] io_wakeups_0_bits_uop_iq_type = 3'h0; // @[rename-stage.scala:356:7]
wire [2:0] io_wakeups_0_bits_uop_ctrl_op2_sel = 3'h0; // @[rename-stage.scala:356:7]
wire [2:0] io_wakeups_0_bits_uop_ctrl_imm_sel = 3'h0; // @[rename-stage.scala:356:7]
wire [2:0] io_wakeups_0_bits_uop_ctrl_csr_cmd = 3'h0; // @[rename-stage.scala:356:7]
wire [2:0] io_wakeups_0_bits_uop_br_tag = 3'h0; // @[rename-stage.scala:356:7]
wire [2:0] io_wakeups_0_bits_uop_ldq_idx = 3'h0; // @[rename-stage.scala:356:7]
wire [2:0] io_wakeups_0_bits_uop_stq_idx = 3'h0; // @[rename-stage.scala:356:7]
wire [2:0] io_wakeups_0_bits_fflags_bits_uop_iq_type = 3'h0; // @[rename-stage.scala:356:7]
wire [2:0] io_wakeups_0_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[rename-stage.scala:356:7]
wire [2:0] io_wakeups_0_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[rename-stage.scala:356:7]
wire [2:0] io_wakeups_0_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[rename-stage.scala:356:7]
wire [2:0] io_wakeups_0_bits_fflags_bits_uop_br_tag = 3'h0; // @[rename-stage.scala:356:7]
wire [2:0] io_wakeups_0_bits_fflags_bits_uop_ldq_idx = 3'h0; // @[rename-stage.scala:356:7]
wire [2:0] io_wakeups_0_bits_fflags_bits_uop_stq_idx = 3'h0; // @[rename-stage.scala:356:7]
wire [2:0] ren1_uops_0_ctrl_op2_sel = 3'h0; // @[rename-stage.scala:101:29]
wire [2:0] ren1_uops_0_ctrl_imm_sel = 3'h0; // @[rename-stage.scala:101:29]
wire [2:0] ren1_uops_0_ctrl_csr_cmd = 3'h0; // @[rename-stage.scala:101:29]
wire [2:0] ren1_uops_0_ldq_idx = 3'h0; // @[rename-stage.scala:101:29]
wire [2:0] ren1_uops_0_stq_idx = 3'h0; // @[rename-stage.scala:101:29]
wire [1:0] io_dec_uops_0_ctrl_op1_sel = 2'h0; // @[rename-stage.scala:356:7]
wire [1:0] io_dec_uops_0_iw_state = 2'h0; // @[rename-stage.scala:356:7]
wire [1:0] io_dec_uops_0_rxq_idx = 2'h0; // @[rename-stage.scala:356:7]
wire [1:0] io_dec_uops_0_debug_tsrc = 2'h0; // @[rename-stage.scala:356:7]
wire [1:0] io_wakeups_0_bits_uop_ctrl_op1_sel = 2'h0; // @[rename-stage.scala:356:7]
wire [1:0] io_wakeups_0_bits_uop_iw_state = 2'h0; // @[rename-stage.scala:356:7]
wire [1:0] io_wakeups_0_bits_uop_rxq_idx = 2'h0; // @[rename-stage.scala:356:7]
wire [1:0] io_wakeups_0_bits_uop_mem_size = 2'h0; // @[rename-stage.scala:356:7]
wire [1:0] io_wakeups_0_bits_uop_dst_rtype = 2'h0; // @[rename-stage.scala:356:7]
wire [1:0] io_wakeups_0_bits_uop_lrs1_rtype = 2'h0; // @[rename-stage.scala:356:7]
wire [1:0] io_wakeups_0_bits_uop_lrs2_rtype = 2'h0; // @[rename-stage.scala:356:7]
wire [1:0] io_wakeups_0_bits_uop_debug_fsrc = 2'h0; // @[rename-stage.scala:356:7]
wire [1:0] io_wakeups_0_bits_uop_debug_tsrc = 2'h0; // @[rename-stage.scala:356:7]
wire [1:0] io_wakeups_0_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[rename-stage.scala:356:7]
wire [1:0] io_wakeups_0_bits_fflags_bits_uop_iw_state = 2'h0; // @[rename-stage.scala:356:7]
wire [1:0] io_wakeups_0_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[rename-stage.scala:356:7]
wire [1:0] io_wakeups_0_bits_fflags_bits_uop_mem_size = 2'h0; // @[rename-stage.scala:356:7]
wire [1:0] io_wakeups_0_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[rename-stage.scala:356:7]
wire [1:0] io_wakeups_0_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[rename-stage.scala:356:7]
wire [1:0] io_wakeups_0_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[rename-stage.scala:356:7]
wire [1:0] io_wakeups_0_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[rename-stage.scala:356:7]
wire [1:0] io_wakeups_0_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[rename-stage.scala:356:7]
wire [1:0] ren1_uops_0_ctrl_op1_sel = 2'h0; // @[rename-stage.scala:101:29]
wire [1:0] ren1_uops_0_iw_state = 2'h0; // @[rename-stage.scala:101:29]
wire [1:0] ren1_uops_0_rxq_idx = 2'h0; // @[rename-stage.scala:101:29]
wire [1:0] ren1_uops_0_debug_tsrc = 2'h0; // @[rename-stage.scala:101:29]
wire [1:0] lo_lo_lo_1 = 2'h0; // @[rename-stage.scala:402:47]
wire [1:0] lo_lo_hi_1 = 2'h0; // @[rename-stage.scala:402:47]
wire [1:0] lo_hi_lo_1 = 2'h0; // @[rename-stage.scala:402:47]
wire [1:0] lo_hi_hi_1 = 2'h0; // @[rename-stage.scala:402:47]
wire [1:0] hi_lo_lo_1 = 2'h0; // @[rename-stage.scala:402:47]
wire [1:0] hi_lo_hi_1 = 2'h0; // @[rename-stage.scala:402:47]
wire [1:0] hi_hi_lo_1 = 2'h0; // @[rename-stage.scala:402:47]
wire [1:0] hi_hi_hi_1 = 2'h0; // @[rename-stage.scala:402:47]
wire [1:0] lo_lo_lo_2 = 2'h0; // @[rename-stage.scala:402:65]
wire [1:0] lo_lo_hi_2 = 2'h0; // @[rename-stage.scala:402:65]
wire [1:0] lo_hi_lo_2 = 2'h0; // @[rename-stage.scala:402:65]
wire [1:0] lo_hi_hi_2 = 2'h0; // @[rename-stage.scala:402:65]
wire [1:0] hi_lo_lo_2 = 2'h0; // @[rename-stage.scala:402:65]
wire [1:0] hi_lo_hi_2 = 2'h0; // @[rename-stage.scala:402:65]
wire [1:0] hi_hi_lo_2 = 2'h0; // @[rename-stage.scala:402:65]
wire [1:0] hi_hi_hi_2 = 2'h0; // @[rename-stage.scala:402:65]
wire [3:0] io_dec_uops_0_ctrl_br_type = 4'h0; // @[rename-stage.scala:356:7]
wire [3:0] io_dec_uops_0_ppred = 4'h0; // @[rename-stage.scala:356:7]
wire [3:0] io_wakeups_0_bits_uop_ctrl_br_type = 4'h0; // @[rename-stage.scala:356:7]
wire [3:0] io_wakeups_0_bits_uop_ftq_idx = 4'h0; // @[rename-stage.scala:356:7]
wire [3:0] io_wakeups_0_bits_uop_ppred = 4'h0; // @[rename-stage.scala:356:7]
wire [3:0] io_wakeups_0_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[rename-stage.scala:356:7]
wire [3:0] io_wakeups_0_bits_fflags_bits_uop_ftq_idx = 4'h0; // @[rename-stage.scala:356:7]
wire [3:0] io_wakeups_0_bits_fflags_bits_uop_ppred = 4'h0; // @[rename-stage.scala:356:7]
wire [3:0] ren1_uops_0_ctrl_br_type = 4'h0; // @[rename-stage.scala:101:29]
wire [3:0] ren1_uops_0_ppred = 4'h0; // @[rename-stage.scala:101:29]
wire [3:0] lo_lo_1 = 4'h0; // @[rename-stage.scala:402:47]
wire [3:0] lo_hi_1 = 4'h0; // @[rename-stage.scala:402:47]
wire [3:0] hi_lo_1 = 4'h0; // @[rename-stage.scala:402:47]
wire [3:0] hi_hi_1 = 4'h0; // @[rename-stage.scala:402:47]
wire [3:0] lo_lo_2 = 4'h0; // @[rename-stage.scala:402:65]
wire [3:0] lo_hi_2 = 4'h0; // @[rename-stage.scala:402:65]
wire [3:0] hi_lo_2 = 4'h0; // @[rename-stage.scala:402:65]
wire [3:0] hi_hi_2 = 4'h0; // @[rename-stage.scala:402:65]
wire ren1_fire_0 = io_dec_fire_0_0; // @[rename-stage.scala:100:29, :356:7]
wire [6:0] ren1_uops_0_uopc = io_dec_uops_0_uopc_0; // @[rename-stage.scala:101:29, :356:7]
wire [31:0] ren1_uops_0_inst = io_dec_uops_0_inst_0; // @[rename-stage.scala:101:29, :356:7]
wire [31:0] ren1_uops_0_debug_inst = io_dec_uops_0_debug_inst_0; // @[rename-stage.scala:101:29, :356:7]
wire ren1_uops_0_is_rvc = io_dec_uops_0_is_rvc_0; // @[rename-stage.scala:101:29, :356:7]
wire [39:0] ren1_uops_0_debug_pc = io_dec_uops_0_debug_pc_0; // @[rename-stage.scala:101:29, :356:7]
wire [2:0] ren1_uops_0_iq_type = io_dec_uops_0_iq_type_0; // @[rename-stage.scala:101:29, :356:7]
wire [9:0] ren1_uops_0_fu_code = io_dec_uops_0_fu_code_0; // @[rename-stage.scala:101:29, :356:7]
wire ren1_uops_0_is_br = io_dec_uops_0_is_br_0; // @[rename-stage.scala:101:29, :356:7]
wire ren1_uops_0_is_jalr = io_dec_uops_0_is_jalr_0; // @[rename-stage.scala:101:29, :356:7]
wire ren1_uops_0_is_jal = io_dec_uops_0_is_jal_0; // @[rename-stage.scala:101:29, :356:7]
wire ren1_uops_0_is_sfb = io_dec_uops_0_is_sfb_0; // @[rename-stage.scala:101:29, :356:7]
wire [7:0] ren1_uops_0_br_mask = io_dec_uops_0_br_mask_0; // @[rename-stage.scala:101:29, :356:7]
wire [2:0] ren1_uops_0_br_tag = io_dec_uops_0_br_tag_0; // @[rename-stage.scala:101:29, :356:7]
wire [3:0] ren1_uops_0_ftq_idx = io_dec_uops_0_ftq_idx_0; // @[rename-stage.scala:101:29, :356:7]
wire ren1_uops_0_edge_inst = io_dec_uops_0_edge_inst_0; // @[rename-stage.scala:101:29, :356:7]
wire [5:0] ren1_uops_0_pc_lob = io_dec_uops_0_pc_lob_0; // @[rename-stage.scala:101:29, :356:7]
wire ren1_uops_0_taken = io_dec_uops_0_taken_0; // @[rename-stage.scala:101:29, :356:7]
wire [19:0] ren1_uops_0_imm_packed = io_dec_uops_0_imm_packed_0; // @[rename-stage.scala:101:29, :356:7]
wire ren1_uops_0_exception = io_dec_uops_0_exception_0; // @[rename-stage.scala:101:29, :356:7]
wire [63:0] ren1_uops_0_exc_cause = io_dec_uops_0_exc_cause_0; // @[rename-stage.scala:101:29, :356:7]
wire ren1_uops_0_bypassable = io_dec_uops_0_bypassable_0; // @[rename-stage.scala:101:29, :356:7]
wire [4:0] ren1_uops_0_mem_cmd = io_dec_uops_0_mem_cmd_0; // @[rename-stage.scala:101:29, :356:7]
wire [1:0] ren1_uops_0_mem_size = io_dec_uops_0_mem_size_0; // @[rename-stage.scala:101:29, :356:7]
wire ren1_uops_0_mem_signed = io_dec_uops_0_mem_signed_0; // @[rename-stage.scala:101:29, :356:7]
wire ren1_uops_0_is_fence = io_dec_uops_0_is_fence_0; // @[rename-stage.scala:101:29, :356:7]
wire ren1_uops_0_is_fencei = io_dec_uops_0_is_fencei_0; // @[rename-stage.scala:101:29, :356:7]
wire ren1_uops_0_is_amo = io_dec_uops_0_is_amo_0; // @[rename-stage.scala:101:29, :356:7]
wire ren1_uops_0_uses_ldq = io_dec_uops_0_uses_ldq_0; // @[rename-stage.scala:101:29, :356:7]
wire ren1_uops_0_uses_stq = io_dec_uops_0_uses_stq_0; // @[rename-stage.scala:101:29, :356:7]
wire ren1_uops_0_is_sys_pc2epc = io_dec_uops_0_is_sys_pc2epc_0; // @[rename-stage.scala:101:29, :356:7]
wire ren1_uops_0_is_unique = io_dec_uops_0_is_unique_0; // @[rename-stage.scala:101:29, :356:7]
wire ren1_uops_0_flush_on_commit = io_dec_uops_0_flush_on_commit_0; // @[rename-stage.scala:101:29, :356:7]
wire [5:0] ren1_uops_0_ldst = io_dec_uops_0_ldst_0; // @[rename-stage.scala:101:29, :356:7]
wire [5:0] ren1_uops_0_lrs1 = io_dec_uops_0_lrs1_0; // @[rename-stage.scala:101:29, :356:7]
wire [5:0] ren1_uops_0_lrs2 = io_dec_uops_0_lrs2_0; // @[rename-stage.scala:101:29, :356:7]
wire [5:0] ren1_uops_0_lrs3 = io_dec_uops_0_lrs3_0; // @[rename-stage.scala:101:29, :356:7]
wire ren1_uops_0_ldst_val = io_dec_uops_0_ldst_val_0; // @[rename-stage.scala:101:29, :356:7]
wire [1:0] ren1_uops_0_dst_rtype = io_dec_uops_0_dst_rtype_0; // @[rename-stage.scala:101:29, :356:7]
wire [1:0] ren1_uops_0_lrs1_rtype = io_dec_uops_0_lrs1_rtype_0; // @[rename-stage.scala:101:29, :356:7]
wire [1:0] ren1_uops_0_lrs2_rtype = io_dec_uops_0_lrs2_rtype_0; // @[rename-stage.scala:101:29, :356:7]
wire ren1_uops_0_frs3_en = io_dec_uops_0_frs3_en_0; // @[rename-stage.scala:101:29, :356:7]
wire ren1_uops_0_fp_val = io_dec_uops_0_fp_val_0; // @[rename-stage.scala:101:29, :356:7]
wire ren1_uops_0_fp_single = io_dec_uops_0_fp_single_0; // @[rename-stage.scala:101:29, :356:7]
wire ren1_uops_0_xcpt_pf_if = io_dec_uops_0_xcpt_pf_if_0; // @[rename-stage.scala:101:29, :356:7]
wire ren1_uops_0_xcpt_ae_if = io_dec_uops_0_xcpt_ae_if_0; // @[rename-stage.scala:101:29, :356:7]
wire ren1_uops_0_bp_debug_if = io_dec_uops_0_bp_debug_if_0; // @[rename-stage.scala:101:29, :356:7]
wire ren1_uops_0_bp_xcpt_if = io_dec_uops_0_bp_xcpt_if_0; // @[rename-stage.scala:101:29, :356:7]
wire [1:0] ren1_uops_0_debug_fsrc = io_dec_uops_0_debug_fsrc_0; // @[rename-stage.scala:101:29, :356:7]
wire ren2_valids_0; // @[rename-stage.scala:107:29]
wire [6:0] ren2_uops_0_uopc; // @[rename-stage.scala:108:29]
wire [31:0] ren2_uops_0_inst; // @[rename-stage.scala:108:29]
wire [31:0] ren2_uops_0_debug_inst; // @[rename-stage.scala:108:29]
wire ren2_uops_0_is_rvc; // @[rename-stage.scala:108:29]
wire [39:0] ren2_uops_0_debug_pc; // @[rename-stage.scala:108:29]
wire [2:0] ren2_uops_0_iq_type; // @[rename-stage.scala:108:29]
wire [9:0] ren2_uops_0_fu_code; // @[rename-stage.scala:108:29]
wire [3:0] ren2_uops_0_ctrl_br_type; // @[rename-stage.scala:108:29]
wire [1:0] ren2_uops_0_ctrl_op1_sel; // @[rename-stage.scala:108:29]
wire [2:0] ren2_uops_0_ctrl_op2_sel; // @[rename-stage.scala:108:29]
wire [2:0] ren2_uops_0_ctrl_imm_sel; // @[rename-stage.scala:108:29]
wire [4:0] ren2_uops_0_ctrl_op_fcn; // @[rename-stage.scala:108:29]
wire ren2_uops_0_ctrl_fcn_dw; // @[rename-stage.scala:108:29]
wire [2:0] ren2_uops_0_ctrl_csr_cmd; // @[rename-stage.scala:108:29]
wire ren2_uops_0_ctrl_is_load; // @[rename-stage.scala:108:29]
wire ren2_uops_0_ctrl_is_sta; // @[rename-stage.scala:108:29]
wire ren2_uops_0_ctrl_is_std; // @[rename-stage.scala:108:29]
wire [1:0] ren2_uops_0_iw_state; // @[rename-stage.scala:108:29]
wire ren2_uops_0_iw_p1_poisoned; // @[rename-stage.scala:108:29]
wire ren2_uops_0_iw_p2_poisoned; // @[rename-stage.scala:108:29]
wire ren2_uops_0_is_br; // @[rename-stage.scala:108:29]
wire ren2_uops_0_is_jalr; // @[rename-stage.scala:108:29]
wire ren2_uops_0_is_jal; // @[rename-stage.scala:108:29]
wire ren2_uops_0_is_sfb; // @[rename-stage.scala:108:29]
wire [7:0] ren2_uops_0_br_mask; // @[rename-stage.scala:108:29]
wire [2:0] ren2_uops_0_br_tag; // @[rename-stage.scala:108:29]
wire [3:0] ren2_uops_0_ftq_idx; // @[rename-stage.scala:108:29]
wire ren2_uops_0_edge_inst; // @[rename-stage.scala:108:29]
wire [5:0] ren2_uops_0_pc_lob; // @[rename-stage.scala:108:29]
wire ren2_uops_0_taken; // @[rename-stage.scala:108:29]
wire [19:0] ren2_uops_0_imm_packed; // @[rename-stage.scala:108:29]
wire [11:0] ren2_uops_0_csr_addr; // @[rename-stage.scala:108:29]
wire [4:0] ren2_uops_0_rob_idx; // @[rename-stage.scala:108:29]
wire [2:0] ren2_uops_0_ldq_idx; // @[rename-stage.scala:108:29]
wire [2:0] ren2_uops_0_stq_idx; // @[rename-stage.scala:108:29]
wire [1:0] ren2_uops_0_rxq_idx; // @[rename-stage.scala:108:29]
wire [5:0] ren2_uops_0_pdst; // @[rename-stage.scala:108:29]
wire [5:0] ren2_uops_0_prs1; // @[rename-stage.scala:108:29]
wire [5:0] ren2_uops_0_prs2; // @[rename-stage.scala:108:29]
wire [5:0] ren2_uops_0_prs3; // @[rename-stage.scala:108:29]
wire [3:0] ren2_uops_0_ppred; // @[rename-stage.scala:108:29]
wire ren2_uops_0_prs1_busy; // @[rename-stage.scala:108:29]
wire ren2_uops_0_prs2_busy; // @[rename-stage.scala:108:29]
wire ren2_uops_0_prs3_busy; // @[rename-stage.scala:108:29]
wire ren2_uops_0_ppred_busy; // @[rename-stage.scala:108:29]
wire [5:0] ren2_uops_0_stale_pdst; // @[rename-stage.scala:108:29]
wire ren2_uops_0_exception; // @[rename-stage.scala:108:29]
wire [63:0] ren2_uops_0_exc_cause; // @[rename-stage.scala:108:29]
wire ren2_uops_0_bypassable; // @[rename-stage.scala:108:29]
wire [4:0] ren2_uops_0_mem_cmd; // @[rename-stage.scala:108:29]
wire [1:0] ren2_uops_0_mem_size; // @[rename-stage.scala:108:29]
wire ren2_uops_0_mem_signed; // @[rename-stage.scala:108:29]
wire ren2_uops_0_is_fence; // @[rename-stage.scala:108:29]
wire ren2_uops_0_is_fencei; // @[rename-stage.scala:108:29]
wire ren2_uops_0_is_amo; // @[rename-stage.scala:108:29]
wire ren2_uops_0_uses_ldq; // @[rename-stage.scala:108:29]
wire ren2_uops_0_uses_stq; // @[rename-stage.scala:108:29]
wire ren2_uops_0_is_sys_pc2epc; // @[rename-stage.scala:108:29]
wire ren2_uops_0_is_unique; // @[rename-stage.scala:108:29]
wire ren2_uops_0_flush_on_commit; // @[rename-stage.scala:108:29]
wire ren2_uops_0_ldst_is_rs1; // @[rename-stage.scala:108:29]
wire [5:0] ren2_uops_0_ldst; // @[rename-stage.scala:108:29]
wire [5:0] ren2_uops_0_lrs1; // @[rename-stage.scala:108:29]
wire [5:0] ren2_uops_0_lrs2; // @[rename-stage.scala:108:29]
wire [5:0] ren2_uops_0_lrs3; // @[rename-stage.scala:108:29]
wire ren2_uops_0_ldst_val; // @[rename-stage.scala:108:29]
wire [1:0] ren2_uops_0_dst_rtype; // @[rename-stage.scala:108:29]
wire [1:0] ren2_uops_0_lrs1_rtype; // @[rename-stage.scala:108:29]
wire [1:0] ren2_uops_0_lrs2_rtype; // @[rename-stage.scala:108:29]
wire ren2_uops_0_frs3_en; // @[rename-stage.scala:108:29]
wire ren2_uops_0_fp_val; // @[rename-stage.scala:108:29]
wire ren2_uops_0_fp_single; // @[rename-stage.scala:108:29]
wire ren2_uops_0_xcpt_pf_if; // @[rename-stage.scala:108:29]
wire ren2_uops_0_xcpt_ae_if; // @[rename-stage.scala:108:29]
wire ren2_uops_0_xcpt_ma_if; // @[rename-stage.scala:108:29]
wire ren2_uops_0_bp_debug_if; // @[rename-stage.scala:108:29]
wire ren2_uops_0_bp_xcpt_if; // @[rename-stage.scala:108:29]
wire [1:0] ren2_uops_0_debug_fsrc; // @[rename-stage.scala:108:29]
wire [1:0] ren2_uops_0_debug_tsrc; // @[rename-stage.scala:108:29]
wire io_ren2_mask_0; // @[rename-stage.scala:356:7]
wire [3:0] io_ren2_uops_0_ctrl_br_type; // @[rename-stage.scala:356:7]
wire [1:0] io_ren2_uops_0_ctrl_op1_sel; // @[rename-stage.scala:356:7]
wire [2:0] io_ren2_uops_0_ctrl_op2_sel; // @[rename-stage.scala:356:7]
wire [2:0] io_ren2_uops_0_ctrl_imm_sel; // @[rename-stage.scala:356:7]
wire [4:0] io_ren2_uops_0_ctrl_op_fcn; // @[rename-stage.scala:356:7]
wire io_ren2_uops_0_ctrl_fcn_dw; // @[rename-stage.scala:356:7]
wire [2:0] io_ren2_uops_0_ctrl_csr_cmd; // @[rename-stage.scala:356:7]
wire io_ren2_uops_0_ctrl_is_load; // @[rename-stage.scala:356:7]
wire io_ren2_uops_0_ctrl_is_sta; // @[rename-stage.scala:356:7]
wire io_ren2_uops_0_ctrl_is_std; // @[rename-stage.scala:356:7]
wire [6:0] io_ren2_uops_0_uopc; // @[rename-stage.scala:356:7]
wire [31:0] io_ren2_uops_0_inst; // @[rename-stage.scala:356:7]
wire [31:0] io_ren2_uops_0_debug_inst; // @[rename-stage.scala:356:7]
wire io_ren2_uops_0_is_rvc; // @[rename-stage.scala:356:7]
wire [39:0] io_ren2_uops_0_debug_pc; // @[rename-stage.scala:356:7]
wire [2:0] io_ren2_uops_0_iq_type; // @[rename-stage.scala:356:7]
wire [9:0] io_ren2_uops_0_fu_code; // @[rename-stage.scala:356:7]
wire [1:0] io_ren2_uops_0_iw_state; // @[rename-stage.scala:356:7]
wire io_ren2_uops_0_iw_p1_poisoned; // @[rename-stage.scala:356:7]
wire io_ren2_uops_0_iw_p2_poisoned; // @[rename-stage.scala:356:7]
wire io_ren2_uops_0_is_br; // @[rename-stage.scala:356:7]
wire io_ren2_uops_0_is_jalr; // @[rename-stage.scala:356:7]
wire io_ren2_uops_0_is_jal; // @[rename-stage.scala:356:7]
wire io_ren2_uops_0_is_sfb; // @[rename-stage.scala:356:7]
wire [7:0] io_ren2_uops_0_br_mask; // @[rename-stage.scala:356:7]
wire [2:0] io_ren2_uops_0_br_tag; // @[rename-stage.scala:356:7]
wire [3:0] io_ren2_uops_0_ftq_idx; // @[rename-stage.scala:356:7]
wire io_ren2_uops_0_edge_inst; // @[rename-stage.scala:356:7]
wire [5:0] io_ren2_uops_0_pc_lob; // @[rename-stage.scala:356:7]
wire io_ren2_uops_0_taken; // @[rename-stage.scala:356:7]
wire [19:0] io_ren2_uops_0_imm_packed; // @[rename-stage.scala:356:7]
wire [11:0] io_ren2_uops_0_csr_addr; // @[rename-stage.scala:356:7]
wire [4:0] io_ren2_uops_0_rob_idx; // @[rename-stage.scala:356:7]
wire [2:0] io_ren2_uops_0_ldq_idx; // @[rename-stage.scala:356:7]
wire [2:0] io_ren2_uops_0_stq_idx; // @[rename-stage.scala:356:7]
wire [1:0] io_ren2_uops_0_rxq_idx; // @[rename-stage.scala:356:7]
wire [5:0] io_ren2_uops_0_pdst; // @[rename-stage.scala:356:7]
wire [5:0] io_ren2_uops_0_prs1; // @[rename-stage.scala:356:7]
wire [5:0] io_ren2_uops_0_prs2; // @[rename-stage.scala:356:7]
wire [5:0] io_ren2_uops_0_prs3; // @[rename-stage.scala:356:7]
wire [3:0] io_ren2_uops_0_ppred; // @[rename-stage.scala:356:7]
wire io_ren2_uops_0_prs1_busy; // @[rename-stage.scala:356:7]
wire io_ren2_uops_0_prs2_busy; // @[rename-stage.scala:356:7]
wire io_ren2_uops_0_prs3_busy; // @[rename-stage.scala:356:7]
wire io_ren2_uops_0_ppred_busy; // @[rename-stage.scala:356:7]
wire [5:0] io_ren2_uops_0_stale_pdst; // @[rename-stage.scala:356:7]
wire io_ren2_uops_0_exception; // @[rename-stage.scala:356:7]
wire [63:0] io_ren2_uops_0_exc_cause; // @[rename-stage.scala:356:7]
wire io_ren2_uops_0_bypassable; // @[rename-stage.scala:356:7]
wire [4:0] io_ren2_uops_0_mem_cmd; // @[rename-stage.scala:356:7]
wire [1:0] io_ren2_uops_0_mem_size; // @[rename-stage.scala:356:7]
wire io_ren2_uops_0_mem_signed; // @[rename-stage.scala:356:7]
wire io_ren2_uops_0_is_fence; // @[rename-stage.scala:356:7]
wire io_ren2_uops_0_is_fencei; // @[rename-stage.scala:356:7]
wire io_ren2_uops_0_is_amo; // @[rename-stage.scala:356:7]
wire io_ren2_uops_0_uses_ldq; // @[rename-stage.scala:356:7]
wire io_ren2_uops_0_uses_stq; // @[rename-stage.scala:356:7]
wire io_ren2_uops_0_is_sys_pc2epc; // @[rename-stage.scala:356:7]
wire io_ren2_uops_0_is_unique; // @[rename-stage.scala:356:7]
wire io_ren2_uops_0_flush_on_commit; // @[rename-stage.scala:356:7]
wire io_ren2_uops_0_ldst_is_rs1; // @[rename-stage.scala:356:7]
wire [5:0] io_ren2_uops_0_ldst; // @[rename-stage.scala:356:7]
wire [5:0] io_ren2_uops_0_lrs1; // @[rename-stage.scala:356:7]
wire [5:0] io_ren2_uops_0_lrs2; // @[rename-stage.scala:356:7]
wire [5:0] io_ren2_uops_0_lrs3; // @[rename-stage.scala:356:7]
wire io_ren2_uops_0_ldst_val; // @[rename-stage.scala:356:7]
wire [1:0] io_ren2_uops_0_dst_rtype; // @[rename-stage.scala:356:7]
wire [1:0] io_ren2_uops_0_lrs1_rtype; // @[rename-stage.scala:356:7]
wire [1:0] io_ren2_uops_0_lrs2_rtype; // @[rename-stage.scala:356:7]
wire io_ren2_uops_0_frs3_en; // @[rename-stage.scala:356:7]
wire io_ren2_uops_0_fp_val; // @[rename-stage.scala:356:7]
wire io_ren2_uops_0_fp_single; // @[rename-stage.scala:356:7]
wire io_ren2_uops_0_xcpt_pf_if; // @[rename-stage.scala:356:7]
wire io_ren2_uops_0_xcpt_ae_if; // @[rename-stage.scala:356:7]
wire io_ren2_uops_0_xcpt_ma_if; // @[rename-stage.scala:356:7]
wire io_ren2_uops_0_bp_debug_if; // @[rename-stage.scala:356:7]
wire io_ren2_uops_0_bp_xcpt_if; // @[rename-stage.scala:356:7]
wire [1:0] io_ren2_uops_0_debug_fsrc; // @[rename-stage.scala:356:7]
wire [1:0] io_ren2_uops_0_debug_tsrc; // @[rename-stage.scala:356:7]
assign io_ren2_mask_0 = ren2_valids_0; // @[rename-stage.scala:107:29, :356:7]
assign io_ren2_uops_0_uopc = ren2_uops_0_uopc; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_inst = ren2_uops_0_inst; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_debug_inst = ren2_uops_0_debug_inst; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_is_rvc = ren2_uops_0_is_rvc; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_debug_pc = ren2_uops_0_debug_pc; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_iq_type = ren2_uops_0_iq_type; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_fu_code = ren2_uops_0_fu_code; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_ctrl_br_type = ren2_uops_0_ctrl_br_type; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_ctrl_op1_sel = ren2_uops_0_ctrl_op1_sel; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_ctrl_op2_sel = ren2_uops_0_ctrl_op2_sel; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_ctrl_imm_sel = ren2_uops_0_ctrl_imm_sel; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_ctrl_op_fcn = ren2_uops_0_ctrl_op_fcn; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_ctrl_fcn_dw = ren2_uops_0_ctrl_fcn_dw; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_ctrl_csr_cmd = ren2_uops_0_ctrl_csr_cmd; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_ctrl_is_load = ren2_uops_0_ctrl_is_load; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_ctrl_is_sta = ren2_uops_0_ctrl_is_sta; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_ctrl_is_std = ren2_uops_0_ctrl_is_std; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_iw_state = ren2_uops_0_iw_state; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_iw_p1_poisoned = ren2_uops_0_iw_p1_poisoned; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_iw_p2_poisoned = ren2_uops_0_iw_p2_poisoned; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_is_br = ren2_uops_0_is_br; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_is_jalr = ren2_uops_0_is_jalr; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_is_jal = ren2_uops_0_is_jal; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_is_sfb = ren2_uops_0_is_sfb; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_br_mask = ren2_uops_0_br_mask; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_br_tag = ren2_uops_0_br_tag; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_ftq_idx = ren2_uops_0_ftq_idx; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_edge_inst = ren2_uops_0_edge_inst; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_pc_lob = ren2_uops_0_pc_lob; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_taken = ren2_uops_0_taken; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_imm_packed = ren2_uops_0_imm_packed; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_csr_addr = ren2_uops_0_csr_addr; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_rob_idx = ren2_uops_0_rob_idx; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_ldq_idx = ren2_uops_0_ldq_idx; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_stq_idx = ren2_uops_0_stq_idx; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_rxq_idx = ren2_uops_0_rxq_idx; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_pdst = ren2_uops_0_pdst; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_prs1 = ren2_uops_0_prs1; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_prs2 = ren2_uops_0_prs2; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_prs3 = ren2_uops_0_prs3; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_ppred = ren2_uops_0_ppred; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_prs1_busy = ren2_uops_0_prs1_busy; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_prs2_busy = ren2_uops_0_prs2_busy; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_prs3_busy = ren2_uops_0_prs3_busy; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_ppred_busy = ren2_uops_0_ppred_busy; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_stale_pdst = ren2_uops_0_stale_pdst; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_exception = ren2_uops_0_exception; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_exc_cause = ren2_uops_0_exc_cause; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_bypassable = ren2_uops_0_bypassable; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_mem_cmd = ren2_uops_0_mem_cmd; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_mem_size = ren2_uops_0_mem_size; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_mem_signed = ren2_uops_0_mem_signed; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_is_fence = ren2_uops_0_is_fence; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_is_fencei = ren2_uops_0_is_fencei; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_is_amo = ren2_uops_0_is_amo; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_uses_ldq = ren2_uops_0_uses_ldq; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_uses_stq = ren2_uops_0_uses_stq; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_is_sys_pc2epc = ren2_uops_0_is_sys_pc2epc; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_is_unique = ren2_uops_0_is_unique; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_flush_on_commit = ren2_uops_0_flush_on_commit; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_ldst_is_rs1 = ren2_uops_0_ldst_is_rs1; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_ldst = ren2_uops_0_ldst; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_lrs1 = ren2_uops_0_lrs1; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_lrs2 = ren2_uops_0_lrs2; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_lrs3 = ren2_uops_0_lrs3; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_ldst_val = ren2_uops_0_ldst_val; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_dst_rtype = ren2_uops_0_dst_rtype; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_lrs1_rtype = ren2_uops_0_lrs1_rtype; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_lrs2_rtype = ren2_uops_0_lrs2_rtype; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_frs3_en = ren2_uops_0_frs3_en; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_fp_val = ren2_uops_0_fp_val; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_fp_single = ren2_uops_0_fp_single; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_xcpt_pf_if = ren2_uops_0_xcpt_pf_if; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_xcpt_ae_if = ren2_uops_0_xcpt_ae_if; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_xcpt_ma_if = ren2_uops_0_xcpt_ma_if; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_bp_debug_if = ren2_uops_0_bp_debug_if; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_bp_xcpt_if = ren2_uops_0_bp_xcpt_if; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_debug_fsrc = ren2_uops_0_debug_fsrc; // @[rename-stage.scala:108:29, :356:7]
assign io_ren2_uops_0_debug_tsrc = ren2_uops_0_debug_tsrc; // @[rename-stage.scala:108:29, :356:7]
reg r_valid; // @[rename-stage.scala:121:27]
assign ren2_valids_0 = r_valid; // @[rename-stage.scala:107:29, :121:27]
reg [6:0] r_uop_uopc; // @[rename-stage.scala:122:23]
assign ren2_uops_0_uopc = r_uop_uopc; // @[rename-stage.scala:108:29, :122:23]
reg [31:0] r_uop_inst; // @[rename-stage.scala:122:23]
assign ren2_uops_0_inst = r_uop_inst; // @[rename-stage.scala:108:29, :122:23]
reg [31:0] r_uop_debug_inst; // @[rename-stage.scala:122:23]
assign ren2_uops_0_debug_inst = r_uop_debug_inst; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_is_rvc; // @[rename-stage.scala:122:23]
assign ren2_uops_0_is_rvc = r_uop_is_rvc; // @[rename-stage.scala:108:29, :122:23]
reg [39:0] r_uop_debug_pc; // @[rename-stage.scala:122:23]
assign ren2_uops_0_debug_pc = r_uop_debug_pc; // @[rename-stage.scala:108:29, :122:23]
reg [2:0] r_uop_iq_type; // @[rename-stage.scala:122:23]
assign ren2_uops_0_iq_type = r_uop_iq_type; // @[rename-stage.scala:108:29, :122:23]
reg [9:0] r_uop_fu_code; // @[rename-stage.scala:122:23]
assign ren2_uops_0_fu_code = r_uop_fu_code; // @[rename-stage.scala:108:29, :122:23]
reg [3:0] r_uop_ctrl_br_type; // @[rename-stage.scala:122:23]
assign ren2_uops_0_ctrl_br_type = r_uop_ctrl_br_type; // @[rename-stage.scala:108:29, :122:23]
reg [1:0] r_uop_ctrl_op1_sel; // @[rename-stage.scala:122:23]
assign ren2_uops_0_ctrl_op1_sel = r_uop_ctrl_op1_sel; // @[rename-stage.scala:108:29, :122:23]
reg [2:0] r_uop_ctrl_op2_sel; // @[rename-stage.scala:122:23]
assign ren2_uops_0_ctrl_op2_sel = r_uop_ctrl_op2_sel; // @[rename-stage.scala:108:29, :122:23]
reg [2:0] r_uop_ctrl_imm_sel; // @[rename-stage.scala:122:23]
assign ren2_uops_0_ctrl_imm_sel = r_uop_ctrl_imm_sel; // @[rename-stage.scala:108:29, :122:23]
reg [4:0] r_uop_ctrl_op_fcn; // @[rename-stage.scala:122:23]
assign ren2_uops_0_ctrl_op_fcn = r_uop_ctrl_op_fcn; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_ctrl_fcn_dw; // @[rename-stage.scala:122:23]
assign ren2_uops_0_ctrl_fcn_dw = r_uop_ctrl_fcn_dw; // @[rename-stage.scala:108:29, :122:23]
reg [2:0] r_uop_ctrl_csr_cmd; // @[rename-stage.scala:122:23]
assign ren2_uops_0_ctrl_csr_cmd = r_uop_ctrl_csr_cmd; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_ctrl_is_load; // @[rename-stage.scala:122:23]
assign ren2_uops_0_ctrl_is_load = r_uop_ctrl_is_load; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_ctrl_is_sta; // @[rename-stage.scala:122:23]
assign ren2_uops_0_ctrl_is_sta = r_uop_ctrl_is_sta; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_ctrl_is_std; // @[rename-stage.scala:122:23]
assign ren2_uops_0_ctrl_is_std = r_uop_ctrl_is_std; // @[rename-stage.scala:108:29, :122:23]
reg [1:0] r_uop_iw_state; // @[rename-stage.scala:122:23]
assign ren2_uops_0_iw_state = r_uop_iw_state; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_iw_p1_poisoned; // @[rename-stage.scala:122:23]
assign ren2_uops_0_iw_p1_poisoned = r_uop_iw_p1_poisoned; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_iw_p2_poisoned; // @[rename-stage.scala:122:23]
assign ren2_uops_0_iw_p2_poisoned = r_uop_iw_p2_poisoned; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_is_br; // @[rename-stage.scala:122:23]
assign ren2_uops_0_is_br = r_uop_is_br; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_is_jalr; // @[rename-stage.scala:122:23]
assign ren2_uops_0_is_jalr = r_uop_is_jalr; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_is_jal; // @[rename-stage.scala:122:23]
assign ren2_uops_0_is_jal = r_uop_is_jal; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_is_sfb; // @[rename-stage.scala:122:23]
assign ren2_uops_0_is_sfb = r_uop_is_sfb; // @[rename-stage.scala:108:29, :122:23]
reg [7:0] r_uop_br_mask; // @[rename-stage.scala:122:23]
assign ren2_uops_0_br_mask = r_uop_br_mask; // @[rename-stage.scala:108:29, :122:23]
reg [2:0] r_uop_br_tag; // @[rename-stage.scala:122:23]
assign ren2_uops_0_br_tag = r_uop_br_tag; // @[rename-stage.scala:108:29, :122:23]
reg [3:0] r_uop_ftq_idx; // @[rename-stage.scala:122:23]
assign ren2_uops_0_ftq_idx = r_uop_ftq_idx; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_edge_inst; // @[rename-stage.scala:122:23]
assign ren2_uops_0_edge_inst = r_uop_edge_inst; // @[rename-stage.scala:108:29, :122:23]
reg [5:0] r_uop_pc_lob; // @[rename-stage.scala:122:23]
assign ren2_uops_0_pc_lob = r_uop_pc_lob; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_taken; // @[rename-stage.scala:122:23]
assign ren2_uops_0_taken = r_uop_taken; // @[rename-stage.scala:108:29, :122:23]
reg [19:0] r_uop_imm_packed; // @[rename-stage.scala:122:23]
assign ren2_uops_0_imm_packed = r_uop_imm_packed; // @[rename-stage.scala:108:29, :122:23]
reg [11:0] r_uop_csr_addr; // @[rename-stage.scala:122:23]
assign ren2_uops_0_csr_addr = r_uop_csr_addr; // @[rename-stage.scala:108:29, :122:23]
reg [4:0] r_uop_rob_idx; // @[rename-stage.scala:122:23]
assign ren2_uops_0_rob_idx = r_uop_rob_idx; // @[rename-stage.scala:108:29, :122:23]
reg [2:0] r_uop_ldq_idx; // @[rename-stage.scala:122:23]
assign ren2_uops_0_ldq_idx = r_uop_ldq_idx; // @[rename-stage.scala:108:29, :122:23]
reg [2:0] r_uop_stq_idx; // @[rename-stage.scala:122:23]
assign ren2_uops_0_stq_idx = r_uop_stq_idx; // @[rename-stage.scala:108:29, :122:23]
reg [1:0] r_uop_rxq_idx; // @[rename-stage.scala:122:23]
assign ren2_uops_0_rxq_idx = r_uop_rxq_idx; // @[rename-stage.scala:108:29, :122:23]
reg [5:0] r_uop_pdst; // @[rename-stage.scala:122:23]
assign ren2_uops_0_pdst = r_uop_pdst; // @[rename-stage.scala:108:29, :122:23]
reg [5:0] r_uop_prs1; // @[rename-stage.scala:122:23]
assign ren2_uops_0_prs1 = r_uop_prs1; // @[rename-stage.scala:108:29, :122:23]
reg [5:0] r_uop_prs2; // @[rename-stage.scala:122:23]
assign ren2_uops_0_prs2 = r_uop_prs2; // @[rename-stage.scala:108:29, :122:23]
reg [5:0] r_uop_prs3; // @[rename-stage.scala:122:23]
assign ren2_uops_0_prs3 = r_uop_prs3; // @[rename-stage.scala:108:29, :122:23]
reg [3:0] r_uop_ppred; // @[rename-stage.scala:122:23]
assign ren2_uops_0_ppred = r_uop_ppred; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_prs1_busy; // @[rename-stage.scala:122:23]
assign ren2_uops_0_prs1_busy = r_uop_prs1_busy; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_prs2_busy; // @[rename-stage.scala:122:23]
assign ren2_uops_0_prs2_busy = r_uop_prs2_busy; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_prs3_busy; // @[rename-stage.scala:122:23]
assign ren2_uops_0_prs3_busy = r_uop_prs3_busy; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_ppred_busy; // @[rename-stage.scala:122:23]
assign ren2_uops_0_ppred_busy = r_uop_ppred_busy; // @[rename-stage.scala:108:29, :122:23]
reg [5:0] r_uop_stale_pdst; // @[rename-stage.scala:122:23]
assign ren2_uops_0_stale_pdst = r_uop_stale_pdst; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_exception; // @[rename-stage.scala:122:23]
assign ren2_uops_0_exception = r_uop_exception; // @[rename-stage.scala:108:29, :122:23]
reg [63:0] r_uop_exc_cause; // @[rename-stage.scala:122:23]
assign ren2_uops_0_exc_cause = r_uop_exc_cause; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_bypassable; // @[rename-stage.scala:122:23]
assign ren2_uops_0_bypassable = r_uop_bypassable; // @[rename-stage.scala:108:29, :122:23]
reg [4:0] r_uop_mem_cmd; // @[rename-stage.scala:122:23]
assign ren2_uops_0_mem_cmd = r_uop_mem_cmd; // @[rename-stage.scala:108:29, :122:23]
reg [1:0] r_uop_mem_size; // @[rename-stage.scala:122:23]
assign ren2_uops_0_mem_size = r_uop_mem_size; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_mem_signed; // @[rename-stage.scala:122:23]
assign ren2_uops_0_mem_signed = r_uop_mem_signed; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_is_fence; // @[rename-stage.scala:122:23]
assign ren2_uops_0_is_fence = r_uop_is_fence; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_is_fencei; // @[rename-stage.scala:122:23]
assign ren2_uops_0_is_fencei = r_uop_is_fencei; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_is_amo; // @[rename-stage.scala:122:23]
assign ren2_uops_0_is_amo = r_uop_is_amo; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_uses_ldq; // @[rename-stage.scala:122:23]
assign ren2_uops_0_uses_ldq = r_uop_uses_ldq; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_uses_stq; // @[rename-stage.scala:122:23]
assign ren2_uops_0_uses_stq = r_uop_uses_stq; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_is_sys_pc2epc; // @[rename-stage.scala:122:23]
assign ren2_uops_0_is_sys_pc2epc = r_uop_is_sys_pc2epc; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_is_unique; // @[rename-stage.scala:122:23]
assign ren2_uops_0_is_unique = r_uop_is_unique; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_flush_on_commit; // @[rename-stage.scala:122:23]
assign ren2_uops_0_flush_on_commit = r_uop_flush_on_commit; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_ldst_is_rs1; // @[rename-stage.scala:122:23]
assign ren2_uops_0_ldst_is_rs1 = r_uop_ldst_is_rs1; // @[rename-stage.scala:108:29, :122:23]
reg [5:0] r_uop_ldst; // @[rename-stage.scala:122:23]
assign ren2_uops_0_ldst = r_uop_ldst; // @[rename-stage.scala:108:29, :122:23]
reg [5:0] r_uop_lrs1; // @[rename-stage.scala:122:23]
assign ren2_uops_0_lrs1 = r_uop_lrs1; // @[rename-stage.scala:108:29, :122:23]
reg [5:0] r_uop_lrs2; // @[rename-stage.scala:122:23]
assign ren2_uops_0_lrs2 = r_uop_lrs2; // @[rename-stage.scala:108:29, :122:23]
reg [5:0] r_uop_lrs3; // @[rename-stage.scala:122:23]
assign ren2_uops_0_lrs3 = r_uop_lrs3; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_ldst_val; // @[rename-stage.scala:122:23]
assign ren2_uops_0_ldst_val = r_uop_ldst_val; // @[rename-stage.scala:108:29, :122:23]
reg [1:0] r_uop_dst_rtype; // @[rename-stage.scala:122:23]
assign ren2_uops_0_dst_rtype = r_uop_dst_rtype; // @[rename-stage.scala:108:29, :122:23]
reg [1:0] r_uop_lrs1_rtype; // @[rename-stage.scala:122:23]
assign ren2_uops_0_lrs1_rtype = r_uop_lrs1_rtype; // @[rename-stage.scala:108:29, :122:23]
reg [1:0] r_uop_lrs2_rtype; // @[rename-stage.scala:122:23]
assign ren2_uops_0_lrs2_rtype = r_uop_lrs2_rtype; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_frs3_en; // @[rename-stage.scala:122:23]
assign ren2_uops_0_frs3_en = r_uop_frs3_en; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_fp_val; // @[rename-stage.scala:122:23]
assign ren2_uops_0_fp_val = r_uop_fp_val; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_fp_single; // @[rename-stage.scala:122:23]
assign ren2_uops_0_fp_single = r_uop_fp_single; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_xcpt_pf_if; // @[rename-stage.scala:122:23]
assign ren2_uops_0_xcpt_pf_if = r_uop_xcpt_pf_if; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_xcpt_ae_if; // @[rename-stage.scala:122:23]
assign ren2_uops_0_xcpt_ae_if = r_uop_xcpt_ae_if; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_xcpt_ma_if; // @[rename-stage.scala:122:23]
assign ren2_uops_0_xcpt_ma_if = r_uop_xcpt_ma_if; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_bp_debug_if; // @[rename-stage.scala:122:23]
assign ren2_uops_0_bp_debug_if = r_uop_bp_debug_if; // @[rename-stage.scala:108:29, :122:23]
reg r_uop_bp_xcpt_if; // @[rename-stage.scala:122:23]
assign ren2_uops_0_bp_xcpt_if = r_uop_bp_xcpt_if; // @[rename-stage.scala:108:29, :122:23]
reg [1:0] r_uop_debug_fsrc; // @[rename-stage.scala:122:23]
assign ren2_uops_0_debug_fsrc = r_uop_debug_fsrc; // @[rename-stage.scala:108:29, :122:23]
reg [1:0] r_uop_debug_tsrc; // @[rename-stage.scala:122:23]
assign ren2_uops_0_debug_tsrc = r_uop_debug_tsrc; // @[rename-stage.scala:108:29, :122:23]
wire [6:0] r_uop_newuop_uopc = next_uop_uopc; // @[util.scala:73:26]
wire [31:0] r_uop_newuop_inst = next_uop_inst; // @[util.scala:73:26]
wire [31:0] r_uop_newuop_debug_inst = next_uop_debug_inst; // @[util.scala:73:26]
wire r_uop_newuop_is_rvc = next_uop_is_rvc; // @[util.scala:73:26]
wire [39:0] r_uop_newuop_debug_pc = next_uop_debug_pc; // @[util.scala:73:26]
wire [2:0] r_uop_newuop_iq_type = next_uop_iq_type; // @[util.scala:73:26]
wire [9:0] r_uop_newuop_fu_code = next_uop_fu_code; // @[util.scala:73:26]
wire [3:0] r_uop_newuop_ctrl_br_type = next_uop_ctrl_br_type; // @[util.scala:73:26]
wire [1:0] r_uop_newuop_ctrl_op1_sel = next_uop_ctrl_op1_sel; // @[util.scala:73:26]
wire [2:0] r_uop_newuop_ctrl_op2_sel = next_uop_ctrl_op2_sel; // @[util.scala:73:26]
wire [2:0] r_uop_newuop_ctrl_imm_sel = next_uop_ctrl_imm_sel; // @[util.scala:73:26]
wire [4:0] r_uop_newuop_ctrl_op_fcn = next_uop_ctrl_op_fcn; // @[util.scala:73:26]
wire r_uop_newuop_ctrl_fcn_dw = next_uop_ctrl_fcn_dw; // @[util.scala:73:26]
wire [2:0] r_uop_newuop_ctrl_csr_cmd = next_uop_ctrl_csr_cmd; // @[util.scala:73:26]
wire r_uop_newuop_ctrl_is_load = next_uop_ctrl_is_load; // @[util.scala:73:26]
wire r_uop_newuop_ctrl_is_sta = next_uop_ctrl_is_sta; // @[util.scala:73:26]
wire r_uop_newuop_ctrl_is_std = next_uop_ctrl_is_std; // @[util.scala:73:26]
wire [1:0] r_uop_newuop_iw_state = next_uop_iw_state; // @[util.scala:73:26]
wire r_uop_newuop_iw_p1_poisoned = next_uop_iw_p1_poisoned; // @[util.scala:73:26]
wire r_uop_newuop_iw_p2_poisoned = next_uop_iw_p2_poisoned; // @[util.scala:73:26]
wire r_uop_newuop_is_br = next_uop_is_br; // @[util.scala:73:26]
wire r_uop_newuop_is_jalr = next_uop_is_jalr; // @[util.scala:73:26]
wire r_uop_newuop_is_jal = next_uop_is_jal; // @[util.scala:73:26]
wire r_uop_newuop_is_sfb = next_uop_is_sfb; // @[util.scala:73:26]
wire [2:0] r_uop_newuop_br_tag = next_uop_br_tag; // @[util.scala:73:26]
wire [3:0] r_uop_newuop_ftq_idx = next_uop_ftq_idx; // @[util.scala:73:26]
wire r_uop_newuop_edge_inst = next_uop_edge_inst; // @[util.scala:73:26]
wire [5:0] r_uop_newuop_pc_lob = next_uop_pc_lob; // @[util.scala:73:26]
wire r_uop_newuop_taken = next_uop_taken; // @[util.scala:73:26]
wire [19:0] r_uop_newuop_imm_packed = next_uop_imm_packed; // @[util.scala:73:26]
wire [11:0] r_uop_newuop_csr_addr = next_uop_csr_addr; // @[util.scala:73:26]
wire [4:0] r_uop_newuop_rob_idx = next_uop_rob_idx; // @[util.scala:73:26]
wire [2:0] r_uop_newuop_ldq_idx = next_uop_ldq_idx; // @[util.scala:73:26]
wire [2:0] r_uop_newuop_stq_idx = next_uop_stq_idx; // @[util.scala:73:26]
wire [1:0] r_uop_newuop_rxq_idx = next_uop_rxq_idx; // @[util.scala:73:26]
wire [5:0] r_uop_newuop_pdst = next_uop_pdst; // @[util.scala:73:26]
wire [5:0] r_uop_newuop_prs1 = next_uop_prs1; // @[util.scala:73:26]
wire [5:0] r_uop_newuop_prs2 = next_uop_prs2; // @[util.scala:73:26]
wire [5:0] r_uop_newuop_prs3 = next_uop_prs3; // @[util.scala:73:26]
wire [3:0] r_uop_newuop_ppred = next_uop_ppred; // @[util.scala:73:26]
wire r_uop_newuop_prs1_busy = next_uop_prs1_busy; // @[util.scala:73:26]
wire r_uop_newuop_prs2_busy = next_uop_prs2_busy; // @[util.scala:73:26]
wire r_uop_newuop_prs3_busy = next_uop_prs3_busy; // @[util.scala:73:26]
wire r_uop_newuop_ppred_busy = next_uop_ppred_busy; // @[util.scala:73:26]
wire [5:0] r_uop_newuop_stale_pdst = next_uop_stale_pdst; // @[util.scala:73:26]
wire r_uop_newuop_exception = next_uop_exception; // @[util.scala:73:26]
wire [63:0] r_uop_newuop_exc_cause = next_uop_exc_cause; // @[util.scala:73:26]
wire r_uop_newuop_bypassable = next_uop_bypassable; // @[util.scala:73:26]
wire [4:0] r_uop_newuop_mem_cmd = next_uop_mem_cmd; // @[util.scala:73:26]
wire [1:0] r_uop_newuop_mem_size = next_uop_mem_size; // @[util.scala:73:26]
wire r_uop_newuop_mem_signed = next_uop_mem_signed; // @[util.scala:73:26]
wire r_uop_newuop_is_fence = next_uop_is_fence; // @[util.scala:73:26]
wire r_uop_newuop_is_fencei = next_uop_is_fencei; // @[util.scala:73:26]
wire r_uop_newuop_is_amo = next_uop_is_amo; // @[util.scala:73:26]
wire r_uop_newuop_uses_ldq = next_uop_uses_ldq; // @[util.scala:73:26]
wire r_uop_newuop_uses_stq = next_uop_uses_stq; // @[util.scala:73:26]
wire r_uop_newuop_is_sys_pc2epc = next_uop_is_sys_pc2epc; // @[util.scala:73:26]
wire r_uop_newuop_is_unique = next_uop_is_unique; // @[util.scala:73:26]
wire r_uop_newuop_flush_on_commit = next_uop_flush_on_commit; // @[util.scala:73:26]
wire r_uop_newuop_ldst_is_rs1 = next_uop_ldst_is_rs1; // @[util.scala:73:26]
wire [5:0] r_uop_newuop_ldst = next_uop_ldst; // @[util.scala:73:26]
wire [5:0] r_uop_newuop_lrs1 = next_uop_lrs1; // @[util.scala:73:26]
wire [5:0] r_uop_newuop_lrs2 = next_uop_lrs2; // @[util.scala:73:26]
wire [5:0] r_uop_newuop_lrs3 = next_uop_lrs3; // @[util.scala:73:26]
wire r_uop_newuop_ldst_val = next_uop_ldst_val; // @[util.scala:73:26]
wire [1:0] r_uop_newuop_dst_rtype = next_uop_dst_rtype; // @[util.scala:73:26]
wire [1:0] r_uop_newuop_lrs1_rtype = next_uop_lrs1_rtype; // @[util.scala:73:26]
wire [1:0] r_uop_newuop_lrs2_rtype = next_uop_lrs2_rtype; // @[util.scala:73:26]
wire r_uop_newuop_frs3_en = next_uop_frs3_en; // @[util.scala:73:26]
wire r_uop_newuop_fp_val = next_uop_fp_val; // @[util.scala:73:26]
wire r_uop_newuop_fp_single = next_uop_fp_single; // @[util.scala:73:26]
wire r_uop_newuop_xcpt_pf_if = next_uop_xcpt_pf_if; // @[util.scala:73:26]
wire r_uop_newuop_xcpt_ae_if = next_uop_xcpt_ae_if; // @[util.scala:73:26]
wire r_uop_newuop_xcpt_ma_if = next_uop_xcpt_ma_if; // @[util.scala:73:26]
wire r_uop_newuop_bp_debug_if = next_uop_bp_debug_if; // @[util.scala:73:26]
wire r_uop_newuop_bp_xcpt_if = next_uop_bp_xcpt_if; // @[util.scala:73:26]
wire [1:0] r_uop_newuop_debug_fsrc = next_uop_debug_fsrc; // @[util.scala:73:26]
wire [1:0] r_uop_newuop_debug_tsrc = next_uop_debug_tsrc; // @[util.scala:73:26]
wire [7:0] next_uop_br_mask; // @[rename-stage.scala:123:24]
wire _r_valid_T = ~io_dis_fire_0_0; // @[rename-stage.scala:133:29, :356:7]
wire _r_valid_T_1 = r_valid & _r_valid_T; // @[rename-stage.scala:121:27, :133:{26,29}]
wire _GEN = io_kill_0 | ~io_dis_ready_0; // @[rename-stage.scala:125:14, :127:20, :129:30, :356:7]
assign next_uop_uopc = _GEN ? r_uop_uopc : ren1_uops_0_uopc; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_inst = _GEN ? r_uop_inst : ren1_uops_0_inst; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_debug_inst = _GEN ? r_uop_debug_inst : ren1_uops_0_debug_inst; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_is_rvc = _GEN ? r_uop_is_rvc : ren1_uops_0_is_rvc; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_debug_pc = _GEN ? r_uop_debug_pc : ren1_uops_0_debug_pc; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_iq_type = _GEN ? r_uop_iq_type : ren1_uops_0_iq_type; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_fu_code = _GEN ? r_uop_fu_code : ren1_uops_0_fu_code; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_ctrl_br_type = _GEN ? r_uop_ctrl_br_type : 4'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_ctrl_op1_sel = _GEN ? r_uop_ctrl_op1_sel : 2'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_ctrl_op2_sel = _GEN ? r_uop_ctrl_op2_sel : 3'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_ctrl_imm_sel = _GEN ? r_uop_ctrl_imm_sel : 3'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_ctrl_op_fcn = _GEN ? r_uop_ctrl_op_fcn : 5'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_ctrl_fcn_dw = _GEN & r_uop_ctrl_fcn_dw; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_ctrl_csr_cmd = _GEN ? r_uop_ctrl_csr_cmd : 3'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_ctrl_is_load = _GEN & r_uop_ctrl_is_load; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_ctrl_is_sta = _GEN & r_uop_ctrl_is_sta; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_ctrl_is_std = _GEN & r_uop_ctrl_is_std; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_iw_state = _GEN ? r_uop_iw_state : 2'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_iw_p1_poisoned = _GEN & r_uop_iw_p1_poisoned; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_iw_p2_poisoned = _GEN & r_uop_iw_p2_poisoned; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_is_br = _GEN ? r_uop_is_br : ren1_uops_0_is_br; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_is_jalr = _GEN ? r_uop_is_jalr : ren1_uops_0_is_jalr; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_is_jal = _GEN ? r_uop_is_jal : ren1_uops_0_is_jal; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_is_sfb = _GEN ? r_uop_is_sfb : ren1_uops_0_is_sfb; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_br_mask = _GEN ? r_uop_br_mask : ren1_uops_0_br_mask; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_br_tag = _GEN ? r_uop_br_tag : ren1_uops_0_br_tag; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_ftq_idx = _GEN ? r_uop_ftq_idx : ren1_uops_0_ftq_idx; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_edge_inst = _GEN ? r_uop_edge_inst : ren1_uops_0_edge_inst; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_pc_lob = _GEN ? r_uop_pc_lob : ren1_uops_0_pc_lob; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_taken = _GEN ? r_uop_taken : ren1_uops_0_taken; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_imm_packed = _GEN ? r_uop_imm_packed : ren1_uops_0_imm_packed; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_csr_addr = _GEN ? r_uop_csr_addr : 12'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_rob_idx = _GEN ? r_uop_rob_idx : 5'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_ldq_idx = _GEN ? r_uop_ldq_idx : 3'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_stq_idx = _GEN ? r_uop_stq_idx : 3'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_rxq_idx = _GEN ? r_uop_rxq_idx : 2'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_pdst = _GEN ? r_uop_pdst : 6'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_prs1 = _GEN ? r_uop_prs1 : 6'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_prs2 = _GEN ? r_uop_prs2 : 6'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_prs3 = _GEN ? r_uop_prs3 : 6'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_ppred = _GEN ? r_uop_ppred : 4'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_prs1_busy = _GEN & r_uop_prs1_busy; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_prs2_busy = _GEN & r_uop_prs2_busy; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_prs3_busy = _GEN & r_uop_prs3_busy; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_ppred_busy = _GEN & r_uop_ppred_busy; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_stale_pdst = _GEN ? r_uop_stale_pdst : 6'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_exception = _GEN ? r_uop_exception : ren1_uops_0_exception; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_exc_cause = _GEN ? r_uop_exc_cause : ren1_uops_0_exc_cause; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_bypassable = _GEN ? r_uop_bypassable : ren1_uops_0_bypassable; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_mem_cmd = _GEN ? r_uop_mem_cmd : ren1_uops_0_mem_cmd; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_mem_size = _GEN ? r_uop_mem_size : ren1_uops_0_mem_size; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_mem_signed = _GEN ? r_uop_mem_signed : ren1_uops_0_mem_signed; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_is_fence = _GEN ? r_uop_is_fence : ren1_uops_0_is_fence; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_is_fencei = _GEN ? r_uop_is_fencei : ren1_uops_0_is_fencei; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_is_amo = _GEN ? r_uop_is_amo : ren1_uops_0_is_amo; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_uses_ldq = _GEN ? r_uop_uses_ldq : ren1_uops_0_uses_ldq; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_uses_stq = _GEN ? r_uop_uses_stq : ren1_uops_0_uses_stq; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_is_sys_pc2epc = _GEN ? r_uop_is_sys_pc2epc : ren1_uops_0_is_sys_pc2epc; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_is_unique = _GEN ? r_uop_is_unique : ren1_uops_0_is_unique; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_flush_on_commit = _GEN ? r_uop_flush_on_commit : ren1_uops_0_flush_on_commit; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_ldst_is_rs1 = _GEN & r_uop_ldst_is_rs1; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_ldst = _GEN ? r_uop_ldst : ren1_uops_0_ldst; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_lrs1 = _GEN ? r_uop_lrs1 : ren1_uops_0_lrs1; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_lrs2 = _GEN ? r_uop_lrs2 : ren1_uops_0_lrs2; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_lrs3 = _GEN ? r_uop_lrs3 : ren1_uops_0_lrs3; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_ldst_val = _GEN ? r_uop_ldst_val : ren1_uops_0_ldst_val; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_dst_rtype = _GEN ? r_uop_dst_rtype : ren1_uops_0_dst_rtype; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_lrs1_rtype = _GEN ? r_uop_lrs1_rtype : ren1_uops_0_lrs1_rtype; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_lrs2_rtype = _GEN ? r_uop_lrs2_rtype : ren1_uops_0_lrs2_rtype; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_frs3_en = _GEN ? r_uop_frs3_en : ren1_uops_0_frs3_en; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_fp_val = _GEN ? r_uop_fp_val : ren1_uops_0_fp_val; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_fp_single = _GEN ? r_uop_fp_single : ren1_uops_0_fp_single; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_xcpt_pf_if = _GEN ? r_uop_xcpt_pf_if : ren1_uops_0_xcpt_pf_if; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_xcpt_ae_if = _GEN ? r_uop_xcpt_ae_if : ren1_uops_0_xcpt_ae_if; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_xcpt_ma_if = _GEN & r_uop_xcpt_ma_if; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_bp_debug_if = _GEN ? r_uop_bp_debug_if : ren1_uops_0_bp_debug_if; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_bp_xcpt_if = _GEN ? r_uop_bp_xcpt_if : ren1_uops_0_bp_xcpt_if; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_debug_fsrc = _GEN ? r_uop_debug_fsrc : ren1_uops_0_debug_fsrc; // @[rename-stage.scala:101:29, :122:23, :123:24, :125:14, :127:20, :129:30]
assign next_uop_debug_tsrc = _GEN ? r_uop_debug_tsrc : 2'h0; // @[rename-stage.scala:122:23, :123:24, :125:14, :127:20, :129:30]
wire [7:0] _r_uop_newuop_br_mask_T_1; // @[util.scala:74:35]
wire [7:0] r_uop_newuop_br_mask; // @[util.scala:73:26]
wire [7:0] _r_uop_newuop_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:74:37]
assign _r_uop_newuop_br_mask_T_1 = next_uop_br_mask & _r_uop_newuop_br_mask_T; // @[util.scala:74:{35,37}]
assign r_uop_newuop_br_mask = _r_uop_newuop_br_mask_T_1; // @[util.scala:73:26, :74:35]
reg busy_table_0; // @[rename-stage.scala:368:27]
wire _io_ren2_uops_0_ppred_busy_T = busy_table_0; // @[rename-stage.scala:368:27, :390:63]
reg busy_table_1; // @[rename-stage.scala:368:27]
reg busy_table_2; // @[rename-stage.scala:368:27]
reg busy_table_3; // @[rename-stage.scala:368:27]
reg busy_table_4; // @[rename-stage.scala:368:27]
reg busy_table_5; // @[rename-stage.scala:368:27]
reg busy_table_6; // @[rename-stage.scala:368:27]
reg busy_table_7; // @[rename-stage.scala:368:27]
reg busy_table_8; // @[rename-stage.scala:368:27]
reg busy_table_9; // @[rename-stage.scala:368:27]
reg busy_table_10; // @[rename-stage.scala:368:27]
reg busy_table_11; // @[rename-stage.scala:368:27]
reg busy_table_12; // @[rename-stage.scala:368:27]
reg busy_table_13; // @[rename-stage.scala:368:27]
reg busy_table_14; // @[rename-stage.scala:368:27]
reg busy_table_15; // @[rename-stage.scala:368:27]
wire _is_sfb_br_T = ren2_uops_0_is_br & ren2_uops_0_is_sfb; // @[rename-stage.scala:108:29]
wire _is_sfb_shadow_T = ~ren2_uops_0_is_br; // @[rename-stage.scala:108:29]
wire _is_sfb_shadow_T_1 = _is_sfb_shadow_T & ren2_uops_0_is_sfb; // @[rename-stage.scala:108:29]
wire _io_ren2_uops_0_ppred_busy_T_2 = _io_ren2_uops_0_ppred_busy_T; // @[rename-stage.scala:390:{63,89}]
wire [1:0] lo_lo_lo = {busy_table_1, busy_table_0}; // @[rename-stage.scala:368:27, :402:30]
wire [1:0] lo_lo_hi = {busy_table_3, busy_table_2}; // @[rename-stage.scala:368:27, :402:30]
wire [3:0] lo_lo = {lo_lo_hi, lo_lo_lo}; // @[rename-stage.scala:402:30]
wire [1:0] lo_hi_lo = {busy_table_5, busy_table_4}; // @[rename-stage.scala:368:27, :402:30]
wire [1:0] lo_hi_hi = {busy_table_7, busy_table_6}; // @[rename-stage.scala:368:27, :402:30]
wire [3:0] lo_hi = {lo_hi_hi, lo_hi_lo}; // @[rename-stage.scala:402:30]
wire [7:0] lo = {lo_hi, lo_lo}; // @[rename-stage.scala:402:30]
wire [1:0] hi_lo_lo = {busy_table_9, busy_table_8}; // @[rename-stage.scala:368:27, :402:30]
wire [1:0] hi_lo_hi = {busy_table_11, busy_table_10}; // @[rename-stage.scala:368:27, :402:30]
wire [3:0] hi_lo = {hi_lo_hi, hi_lo_lo}; // @[rename-stage.scala:402:30]
wire [1:0] hi_hi_lo = {busy_table_13, busy_table_12}; // @[rename-stage.scala:368:27, :402:30]
wire [1:0] hi_hi_hi = {busy_table_15, busy_table_14}; // @[rename-stage.scala:368:27, :402:30]
wire [3:0] hi_hi = {hi_hi_hi, hi_hi_lo}; // @[rename-stage.scala:402:30]
wire [7:0] hi = {hi_hi, hi_lo}; // @[rename-stage.scala:402:30]
always @(posedge clock) begin // @[rename-stage.scala:356:7]
if (reset) begin // @[rename-stage.scala:356:7]
r_valid <= 1'h0; // @[rename-stage.scala:121:27]
busy_table_0 <= 1'h0; // @[rename-stage.scala:368:27]
busy_table_1 <= 1'h0; // @[rename-stage.scala:368:27]
busy_table_2 <= 1'h0; // @[rename-stage.scala:368:27]
busy_table_3 <= 1'h0; // @[rename-stage.scala:368:27]
busy_table_4 <= 1'h0; // @[rename-stage.scala:368:27]
busy_table_5 <= 1'h0; // @[rename-stage.scala:368:27]
busy_table_6 <= 1'h0; // @[rename-stage.scala:368:27]
busy_table_7 <= 1'h0; // @[rename-stage.scala:368:27]
busy_table_8 <= 1'h0; // @[rename-stage.scala:368:27]
busy_table_9 <= 1'h0; // @[rename-stage.scala:368:27]
busy_table_10 <= 1'h0; // @[rename-stage.scala:368:27]
busy_table_11 <= 1'h0; // @[rename-stage.scala:368:27]
busy_table_12 <= 1'h0; // @[rename-stage.scala:368:27]
busy_table_13 <= 1'h0; // @[rename-stage.scala:368:27]
busy_table_14 <= 1'h0; // @[rename-stage.scala:368:27]
busy_table_15 <= 1'h0; // @[rename-stage.scala:368:27]
end
else begin // @[rename-stage.scala:356:7]
r_valid <= ~io_kill_0 & (io_dis_ready_0 ? ren1_fire_0 : _r_valid_T_1); // @[rename-stage.scala:100:29, :121:27, :127:20, :128:15, :129:30, :130:15, :133:{15,26}, :356:7]
busy_table_0 <= lo[0]; // @[rename-stage.scala:368:27, :402:{30,55,73}]
busy_table_1 <= lo[1]; // @[rename-stage.scala:368:27, :402:{30,55,73}]
busy_table_2 <= lo[2]; // @[rename-stage.scala:368:27, :402:{30,55,73}]
busy_table_3 <= lo[3]; // @[rename-stage.scala:368:27, :402:{30,55,73}]
busy_table_4 <= lo[4]; // @[rename-stage.scala:368:27, :402:{30,55,73}]
busy_table_5 <= lo[5]; // @[rename-stage.scala:368:27, :402:{30,55,73}]
busy_table_6 <= lo[6]; // @[rename-stage.scala:368:27, :402:{30,55,73}]
busy_table_7 <= lo[7]; // @[rename-stage.scala:368:27, :402:{30,55,73}]
busy_table_8 <= hi[0]; // @[rename-stage.scala:368:27, :402:{30,55,73}]
busy_table_9 <= hi[1]; // @[rename-stage.scala:368:27, :402:{30,55,73}]
busy_table_10 <= hi[2]; // @[rename-stage.scala:368:27, :402:{30,55,73}]
busy_table_11 <= hi[3]; // @[rename-stage.scala:368:27, :402:{30,55,73}]
busy_table_12 <= hi[4]; // @[rename-stage.scala:368:27, :402:{30,55,73}]
busy_table_13 <= hi[5]; // @[rename-stage.scala:368:27, :402:{30,55,73}]
busy_table_14 <= hi[6]; // @[rename-stage.scala:368:27, :402:{30,55,73}]
busy_table_15 <= hi[7]; // @[rename-stage.scala:368:27, :402:{30,55,73}]
end
r_uop_uopc <= r_uop_newuop_uopc; // @[util.scala:73:26]
r_uop_inst <= r_uop_newuop_inst; // @[util.scala:73:26]
r_uop_debug_inst <= r_uop_newuop_debug_inst; // @[util.scala:73:26]
r_uop_is_rvc <= r_uop_newuop_is_rvc; // @[util.scala:73:26]
r_uop_debug_pc <= r_uop_newuop_debug_pc; // @[util.scala:73:26]
r_uop_iq_type <= r_uop_newuop_iq_type; // @[util.scala:73:26]
r_uop_fu_code <= r_uop_newuop_fu_code; // @[util.scala:73:26]
r_uop_ctrl_br_type <= r_uop_newuop_ctrl_br_type; // @[util.scala:73:26]
r_uop_ctrl_op1_sel <= r_uop_newuop_ctrl_op1_sel; // @[util.scala:73:26]
r_uop_ctrl_op2_sel <= r_uop_newuop_ctrl_op2_sel; // @[util.scala:73:26]
r_uop_ctrl_imm_sel <= r_uop_newuop_ctrl_imm_sel; // @[util.scala:73:26]
r_uop_ctrl_op_fcn <= r_uop_newuop_ctrl_op_fcn; // @[util.scala:73:26]
r_uop_ctrl_fcn_dw <= r_uop_newuop_ctrl_fcn_dw; // @[util.scala:73:26]
r_uop_ctrl_csr_cmd <= r_uop_newuop_ctrl_csr_cmd; // @[util.scala:73:26]
r_uop_ctrl_is_load <= r_uop_newuop_ctrl_is_load; // @[util.scala:73:26]
r_uop_ctrl_is_sta <= r_uop_newuop_ctrl_is_sta; // @[util.scala:73:26]
r_uop_ctrl_is_std <= r_uop_newuop_ctrl_is_std; // @[util.scala:73:26]
r_uop_iw_state <= r_uop_newuop_iw_state; // @[util.scala:73:26]
r_uop_iw_p1_poisoned <= r_uop_newuop_iw_p1_poisoned; // @[util.scala:73:26]
r_uop_iw_p2_poisoned <= r_uop_newuop_iw_p2_poisoned; // @[util.scala:73:26]
r_uop_is_br <= r_uop_newuop_is_br; // @[util.scala:73:26]
r_uop_is_jalr <= r_uop_newuop_is_jalr; // @[util.scala:73:26]
r_uop_is_jal <= r_uop_newuop_is_jal; // @[util.scala:73:26]
r_uop_is_sfb <= r_uop_newuop_is_sfb; // @[util.scala:73:26]
r_uop_br_mask <= r_uop_newuop_br_mask; // @[util.scala:73:26]
r_uop_br_tag <= r_uop_newuop_br_tag; // @[util.scala:73:26]
r_uop_ftq_idx <= r_uop_newuop_ftq_idx; // @[util.scala:73:26]
r_uop_edge_inst <= r_uop_newuop_edge_inst; // @[util.scala:73:26]
r_uop_pc_lob <= r_uop_newuop_pc_lob; // @[util.scala:73:26]
r_uop_taken <= r_uop_newuop_taken; // @[util.scala:73:26]
r_uop_imm_packed <= r_uop_newuop_imm_packed; // @[util.scala:73:26]
r_uop_csr_addr <= r_uop_newuop_csr_addr; // @[util.scala:73:26]
r_uop_rob_idx <= r_uop_newuop_rob_idx; // @[util.scala:73:26]
r_uop_ldq_idx <= r_uop_newuop_ldq_idx; // @[util.scala:73:26]
r_uop_stq_idx <= r_uop_newuop_stq_idx; // @[util.scala:73:26]
r_uop_rxq_idx <= r_uop_newuop_rxq_idx; // @[util.scala:73:26]
r_uop_pdst <= r_uop_newuop_pdst; // @[util.scala:73:26]
r_uop_prs1 <= r_uop_newuop_prs1; // @[util.scala:73:26]
r_uop_prs2 <= r_uop_newuop_prs2; // @[util.scala:73:26]
r_uop_prs3 <= r_uop_newuop_prs3; // @[util.scala:73:26]
r_uop_ppred <= r_uop_newuop_ppred; // @[util.scala:73:26]
r_uop_prs1_busy <= r_uop_newuop_prs1_busy; // @[util.scala:73:26]
r_uop_prs2_busy <= r_uop_newuop_prs2_busy; // @[util.scala:73:26]
r_uop_prs3_busy <= r_uop_newuop_prs3_busy; // @[util.scala:73:26]
r_uop_ppred_busy <= r_uop_newuop_ppred_busy; // @[util.scala:73:26]
r_uop_stale_pdst <= r_uop_newuop_stale_pdst; // @[util.scala:73:26]
r_uop_exception <= r_uop_newuop_exception; // @[util.scala:73:26]
r_uop_exc_cause <= r_uop_newuop_exc_cause; // @[util.scala:73:26]
r_uop_bypassable <= r_uop_newuop_bypassable; // @[util.scala:73:26]
r_uop_mem_cmd <= r_uop_newuop_mem_cmd; // @[util.scala:73:26]
r_uop_mem_size <= r_uop_newuop_mem_size; // @[util.scala:73:26]
r_uop_mem_signed <= r_uop_newuop_mem_signed; // @[util.scala:73:26]
r_uop_is_fence <= r_uop_newuop_is_fence; // @[util.scala:73:26]
r_uop_is_fencei <= r_uop_newuop_is_fencei; // @[util.scala:73:26]
r_uop_is_amo <= r_uop_newuop_is_amo; // @[util.scala:73:26]
r_uop_uses_ldq <= r_uop_newuop_uses_ldq; // @[util.scala:73:26]
r_uop_uses_stq <= r_uop_newuop_uses_stq; // @[util.scala:73:26]
r_uop_is_sys_pc2epc <= r_uop_newuop_is_sys_pc2epc; // @[util.scala:73:26]
r_uop_is_unique <= r_uop_newuop_is_unique; // @[util.scala:73:26]
r_uop_flush_on_commit <= r_uop_newuop_flush_on_commit; // @[util.scala:73:26]
r_uop_ldst_is_rs1 <= r_uop_newuop_ldst_is_rs1; // @[util.scala:73:26]
r_uop_ldst <= r_uop_newuop_ldst; // @[util.scala:73:26]
r_uop_lrs1 <= r_uop_newuop_lrs1; // @[util.scala:73:26]
r_uop_lrs2 <= r_uop_newuop_lrs2; // @[util.scala:73:26]
r_uop_lrs3 <= r_uop_newuop_lrs3; // @[util.scala:73:26]
r_uop_ldst_val <= r_uop_newuop_ldst_val; // @[util.scala:73:26]
r_uop_dst_rtype <= r_uop_newuop_dst_rtype; // @[util.scala:73:26]
r_uop_lrs1_rtype <= r_uop_newuop_lrs1_rtype; // @[util.scala:73:26]
r_uop_lrs2_rtype <= r_uop_newuop_lrs2_rtype; // @[util.scala:73:26]
r_uop_frs3_en <= r_uop_newuop_frs3_en; // @[util.scala:73:26]
r_uop_fp_val <= r_uop_newuop_fp_val; // @[util.scala:73:26]
r_uop_fp_single <= r_uop_newuop_fp_single; // @[util.scala:73:26]
r_uop_xcpt_pf_if <= r_uop_newuop_xcpt_pf_if; // @[util.scala:73:26]
r_uop_xcpt_ae_if <= r_uop_newuop_xcpt_ae_if; // @[util.scala:73:26]
r_uop_xcpt_ma_if <= r_uop_newuop_xcpt_ma_if; // @[util.scala:73:26]
r_uop_bp_debug_if <= r_uop_newuop_bp_debug_if; // @[util.scala:73:26]
r_uop_bp_xcpt_if <= r_uop_newuop_bp_xcpt_if; // @[util.scala:73:26]
r_uop_debug_fsrc <= r_uop_newuop_debug_fsrc; // @[util.scala:73:26]
r_uop_debug_tsrc <= r_uop_newuop_debug_tsrc; // @[util.scala:73:26]
always @(posedge)
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_36 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<12>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 11, 0)
node _source_ok_T = shr(io.in.a.bits.source, 12)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<12>(0h80f))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<12>(0h0))
node uncommonBits = bits(_uncommonBits_T, 11, 0)
node _T_4 = shr(io.in.a.bits.source, 12)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<12>(0h80f))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<12>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 11, 0)
node _T_24 = shr(io.in.a.bits.source, 12)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<12>(0h80f))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_33 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = and(_T_32, _T_37)
node _T_39 = or(UInt<1>(0h0), _T_38)
node _T_40 = and(_T_31, _T_39)
node _T_41 = asUInt(reset)
node _T_42 = eq(_T_41, UInt<1>(0h0))
when _T_42 :
node _T_43 = eq(_T_40, UInt<1>(0h0))
when _T_43 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_40, UInt<1>(0h1), "") : assert_2
node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_46 = and(_T_44, _T_45)
node _T_47 = or(UInt<1>(0h0), _T_46)
node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_49 = cvt(_T_48)
node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000)))
node _T_51 = asSInt(_T_50)
node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = and(_T_47, _T_52)
node _T_54 = or(UInt<1>(0h0), _T_53)
node _T_55 = and(UInt<1>(0h0), _T_54)
node _T_56 = asUInt(reset)
node _T_57 = eq(_T_56, UInt<1>(0h0))
when _T_57 :
node _T_58 = eq(_T_55, UInt<1>(0h0))
when _T_58 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_55, UInt<1>(0h1), "") : assert_3
node _T_59 = asUInt(reset)
node _T_60 = eq(_T_59, UInt<1>(0h0))
when _T_60 :
node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_61 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_63 = asUInt(reset)
node _T_64 = eq(_T_63, UInt<1>(0h0))
when _T_64 :
node _T_65 = eq(_T_62, UInt<1>(0h0))
when _T_65 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_62, UInt<1>(0h1), "") : assert_5
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(is_aligned, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_70 = asUInt(reset)
node _T_71 = eq(_T_70, UInt<1>(0h0))
when _T_71 :
node _T_72 = eq(_T_69, UInt<1>(0h0))
when _T_72 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_69, UInt<1>(0h1), "") : assert_7
node _T_73 = not(io.in.a.bits.mask)
node _T_74 = eq(_T_73, UInt<1>(0h0))
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_T_74, UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_74, UInt<1>(0h1), "") : assert_8
node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_79 = asUInt(reset)
node _T_80 = eq(_T_79, UInt<1>(0h0))
when _T_80 :
node _T_81 = eq(_T_78, UInt<1>(0h0))
when _T_81 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_78, UInt<1>(0h1), "") : assert_9
node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_82 :
node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_85 = and(_T_83, _T_84)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<12>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 11, 0)
node _T_86 = shr(io.in.a.bits.source, 12)
node _T_87 = eq(_T_86, UInt<1>(0h0))
node _T_88 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_89 = and(_T_87, _T_88)
node _T_90 = leq(uncommonBits_2, UInt<12>(0h80f))
node _T_91 = and(_T_89, _T_90)
node _T_92 = and(_T_85, _T_91)
node _T_93 = or(UInt<1>(0h0), _T_92)
node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_95 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = and(_T_94, _T_99)
node _T_101 = or(UInt<1>(0h0), _T_100)
node _T_102 = and(_T_93, _T_101)
node _T_103 = asUInt(reset)
node _T_104 = eq(_T_103, UInt<1>(0h0))
when _T_104 :
node _T_105 = eq(_T_102, UInt<1>(0h0))
when _T_105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_102, UInt<1>(0h1), "") : assert_10
node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_108 = and(_T_106, _T_107)
node _T_109 = or(UInt<1>(0h0), _T_108)
node _T_110 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_111 = cvt(_T_110)
node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000)))
node _T_113 = asSInt(_T_112)
node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0)))
node _T_115 = and(_T_109, _T_114)
node _T_116 = or(UInt<1>(0h0), _T_115)
node _T_117 = and(UInt<1>(0h0), _T_116)
node _T_118 = asUInt(reset)
node _T_119 = eq(_T_118, UInt<1>(0h0))
when _T_119 :
node _T_120 = eq(_T_117, UInt<1>(0h0))
when _T_120 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_117, UInt<1>(0h1), "") : assert_11
node _T_121 = asUInt(reset)
node _T_122 = eq(_T_121, UInt<1>(0h0))
when _T_122 :
node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_125 = asUInt(reset)
node _T_126 = eq(_T_125, UInt<1>(0h0))
when _T_126 :
node _T_127 = eq(_T_124, UInt<1>(0h0))
when _T_127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_124, UInt<1>(0h1), "") : assert_13
node _T_128 = asUInt(reset)
node _T_129 = eq(_T_128, UInt<1>(0h0))
when _T_129 :
node _T_130 = eq(is_aligned, UInt<1>(0h0))
when _T_130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_131, UInt<1>(0h1), "") : assert_15
node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_136 = asUInt(reset)
node _T_137 = eq(_T_136, UInt<1>(0h0))
when _T_137 :
node _T_138 = eq(_T_135, UInt<1>(0h0))
when _T_138 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_135, UInt<1>(0h1), "") : assert_16
node _T_139 = not(io.in.a.bits.mask)
node _T_140 = eq(_T_139, UInt<1>(0h0))
node _T_141 = asUInt(reset)
node _T_142 = eq(_T_141, UInt<1>(0h0))
when _T_142 :
node _T_143 = eq(_T_140, UInt<1>(0h0))
when _T_143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_140, UInt<1>(0h1), "") : assert_17
node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_145 = asUInt(reset)
node _T_146 = eq(_T_145, UInt<1>(0h0))
when _T_146 :
node _T_147 = eq(_T_144, UInt<1>(0h0))
when _T_147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_144, UInt<1>(0h1), "") : assert_18
node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_148 :
node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_151 = and(_T_149, _T_150)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<12>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 11, 0)
node _T_152 = shr(io.in.a.bits.source, 12)
node _T_153 = eq(_T_152, UInt<1>(0h0))
node _T_154 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_155 = and(_T_153, _T_154)
node _T_156 = leq(uncommonBits_3, UInt<12>(0h80f))
node _T_157 = and(_T_155, _T_156)
node _T_158 = and(_T_151, _T_157)
node _T_159 = or(UInt<1>(0h0), _T_158)
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_T_159, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_159, UInt<1>(0h1), "") : assert_19
node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_165 = and(_T_163, _T_164)
node _T_166 = or(UInt<1>(0h0), _T_165)
node _T_167 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_168 = cvt(_T_167)
node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000)))
node _T_170 = asSInt(_T_169)
node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0)))
node _T_172 = and(_T_166, _T_171)
node _T_173 = or(UInt<1>(0h0), _T_172)
node _T_174 = asUInt(reset)
node _T_175 = eq(_T_174, UInt<1>(0h0))
when _T_175 :
node _T_176 = eq(_T_173, UInt<1>(0h0))
when _T_176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_173, UInt<1>(0h1), "") : assert_20
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_180 = asUInt(reset)
node _T_181 = eq(_T_180, UInt<1>(0h0))
when _T_181 :
node _T_182 = eq(is_aligned, UInt<1>(0h0))
when _T_182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(io.in.a.bits.mask, mask)
node _T_188 = asUInt(reset)
node _T_189 = eq(_T_188, UInt<1>(0h0))
when _T_189 :
node _T_190 = eq(_T_187, UInt<1>(0h0))
when _T_190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_187, UInt<1>(0h1), "") : assert_24
node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_192 = asUInt(reset)
node _T_193 = eq(_T_192, UInt<1>(0h0))
when _T_193 :
node _T_194 = eq(_T_191, UInt<1>(0h0))
when _T_194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_191, UInt<1>(0h1), "") : assert_25
node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_195 :
node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_198 = and(_T_196, _T_197)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<12>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 11, 0)
node _T_199 = shr(io.in.a.bits.source, 12)
node _T_200 = eq(_T_199, UInt<1>(0h0))
node _T_201 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_202 = and(_T_200, _T_201)
node _T_203 = leq(uncommonBits_4, UInt<12>(0h80f))
node _T_204 = and(_T_202, _T_203)
node _T_205 = and(_T_198, _T_204)
node _T_206 = or(UInt<1>(0h0), _T_205)
node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_209 = and(_T_207, _T_208)
node _T_210 = or(UInt<1>(0h0), _T_209)
node _T_211 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_212 = cvt(_T_211)
node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000)))
node _T_214 = asSInt(_T_213)
node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0)))
node _T_216 = and(_T_210, _T_215)
node _T_217 = or(UInt<1>(0h0), _T_216)
node _T_218 = and(_T_206, _T_217)
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_218, UInt<1>(0h1), "") : assert_26
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_225 = asUInt(reset)
node _T_226 = eq(_T_225, UInt<1>(0h0))
when _T_226 :
node _T_227 = eq(is_aligned, UInt<1>(0h0))
when _T_227 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_229 = asUInt(reset)
node _T_230 = eq(_T_229, UInt<1>(0h0))
when _T_230 :
node _T_231 = eq(_T_228, UInt<1>(0h0))
when _T_231 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_228, UInt<1>(0h1), "") : assert_29
node _T_232 = eq(io.in.a.bits.mask, mask)
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_232, UInt<1>(0h1), "") : assert_30
node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_236 :
node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_239 = and(_T_237, _T_238)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<12>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 11, 0)
node _T_240 = shr(io.in.a.bits.source, 12)
node _T_241 = eq(_T_240, UInt<1>(0h0))
node _T_242 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_243 = and(_T_241, _T_242)
node _T_244 = leq(uncommonBits_5, UInt<12>(0h80f))
node _T_245 = and(_T_243, _T_244)
node _T_246 = and(_T_239, _T_245)
node _T_247 = or(UInt<1>(0h0), _T_246)
node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_250 = and(_T_248, _T_249)
node _T_251 = or(UInt<1>(0h0), _T_250)
node _T_252 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_253 = cvt(_T_252)
node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000)))
node _T_255 = asSInt(_T_254)
node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0)))
node _T_257 = and(_T_251, _T_256)
node _T_258 = or(UInt<1>(0h0), _T_257)
node _T_259 = and(_T_247, _T_258)
node _T_260 = asUInt(reset)
node _T_261 = eq(_T_260, UInt<1>(0h0))
when _T_261 :
node _T_262 = eq(_T_259, UInt<1>(0h0))
when _T_262 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_259, UInt<1>(0h1), "") : assert_31
node _T_263 = asUInt(reset)
node _T_264 = eq(_T_263, UInt<1>(0h0))
when _T_264 :
node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_265 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_266 = asUInt(reset)
node _T_267 = eq(_T_266, UInt<1>(0h0))
when _T_267 :
node _T_268 = eq(is_aligned, UInt<1>(0h0))
when _T_268 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_270 = asUInt(reset)
node _T_271 = eq(_T_270, UInt<1>(0h0))
when _T_271 :
node _T_272 = eq(_T_269, UInt<1>(0h0))
when _T_272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_269, UInt<1>(0h1), "") : assert_34
node _T_273 = not(mask)
node _T_274 = and(io.in.a.bits.mask, _T_273)
node _T_275 = eq(_T_274, UInt<1>(0h0))
node _T_276 = asUInt(reset)
node _T_277 = eq(_T_276, UInt<1>(0h0))
when _T_277 :
node _T_278 = eq(_T_275, UInt<1>(0h0))
when _T_278 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_275, UInt<1>(0h1), "") : assert_35
node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_279 :
node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_282 = and(_T_280, _T_281)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<12>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 11, 0)
node _T_283 = shr(io.in.a.bits.source, 12)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_286 = and(_T_284, _T_285)
node _T_287 = leq(uncommonBits_6, UInt<12>(0h80f))
node _T_288 = and(_T_286, _T_287)
node _T_289 = and(_T_282, _T_288)
node _T_290 = or(UInt<1>(0h0), _T_289)
node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_292 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_293 = cvt(_T_292)
node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000)))
node _T_295 = asSInt(_T_294)
node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0)))
node _T_297 = and(_T_291, _T_296)
node _T_298 = or(UInt<1>(0h0), _T_297)
node _T_299 = and(_T_290, _T_298)
node _T_300 = asUInt(reset)
node _T_301 = eq(_T_300, UInt<1>(0h0))
when _T_301 :
node _T_302 = eq(_T_299, UInt<1>(0h0))
when _T_302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_299, UInt<1>(0h1), "") : assert_36
node _T_303 = asUInt(reset)
node _T_304 = eq(_T_303, UInt<1>(0h0))
when _T_304 :
node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_305 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_306 = asUInt(reset)
node _T_307 = eq(_T_306, UInt<1>(0h0))
when _T_307 :
node _T_308 = eq(is_aligned, UInt<1>(0h0))
when _T_308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_310 = asUInt(reset)
node _T_311 = eq(_T_310, UInt<1>(0h0))
when _T_311 :
node _T_312 = eq(_T_309, UInt<1>(0h0))
when _T_312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_309, UInt<1>(0h1), "") : assert_39
node _T_313 = eq(io.in.a.bits.mask, mask)
node _T_314 = asUInt(reset)
node _T_315 = eq(_T_314, UInt<1>(0h0))
when _T_315 :
node _T_316 = eq(_T_313, UInt<1>(0h0))
when _T_316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_313, UInt<1>(0h1), "") : assert_40
node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_317 :
node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_320 = and(_T_318, _T_319)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<12>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 11, 0)
node _T_321 = shr(io.in.a.bits.source, 12)
node _T_322 = eq(_T_321, UInt<1>(0h0))
node _T_323 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_324 = and(_T_322, _T_323)
node _T_325 = leq(uncommonBits_7, UInt<12>(0h80f))
node _T_326 = and(_T_324, _T_325)
node _T_327 = and(_T_320, _T_326)
node _T_328 = or(UInt<1>(0h0), _T_327)
node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_330 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_331 = cvt(_T_330)
node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000)))
node _T_333 = asSInt(_T_332)
node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0)))
node _T_335 = and(_T_329, _T_334)
node _T_336 = or(UInt<1>(0h0), _T_335)
node _T_337 = and(_T_328, _T_336)
node _T_338 = asUInt(reset)
node _T_339 = eq(_T_338, UInt<1>(0h0))
when _T_339 :
node _T_340 = eq(_T_337, UInt<1>(0h0))
when _T_340 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_337, UInt<1>(0h1), "") : assert_41
node _T_341 = asUInt(reset)
node _T_342 = eq(_T_341, UInt<1>(0h0))
when _T_342 :
node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_343 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_344 = asUInt(reset)
node _T_345 = eq(_T_344, UInt<1>(0h0))
when _T_345 :
node _T_346 = eq(is_aligned, UInt<1>(0h0))
when _T_346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_347, UInt<1>(0h1), "") : assert_44
node _T_351 = eq(io.in.a.bits.mask, mask)
node _T_352 = asUInt(reset)
node _T_353 = eq(_T_352, UInt<1>(0h0))
when _T_353 :
node _T_354 = eq(_T_351, UInt<1>(0h0))
when _T_354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_351, UInt<1>(0h1), "") : assert_45
node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_355 :
node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_358 = and(_T_356, _T_357)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<12>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 11, 0)
node _T_359 = shr(io.in.a.bits.source, 12)
node _T_360 = eq(_T_359, UInt<1>(0h0))
node _T_361 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_362 = and(_T_360, _T_361)
node _T_363 = leq(uncommonBits_8, UInt<12>(0h80f))
node _T_364 = and(_T_362, _T_363)
node _T_365 = and(_T_358, _T_364)
node _T_366 = or(UInt<1>(0h0), _T_365)
node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_368 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_369 = cvt(_T_368)
node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000)))
node _T_371 = asSInt(_T_370)
node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0)))
node _T_373 = and(_T_367, _T_372)
node _T_374 = or(UInt<1>(0h0), _T_373)
node _T_375 = and(_T_366, _T_374)
node _T_376 = asUInt(reset)
node _T_377 = eq(_T_376, UInt<1>(0h0))
when _T_377 :
node _T_378 = eq(_T_375, UInt<1>(0h0))
when _T_378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_375, UInt<1>(0h1), "") : assert_46
node _T_379 = asUInt(reset)
node _T_380 = eq(_T_379, UInt<1>(0h0))
when _T_380 :
node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_382 = asUInt(reset)
node _T_383 = eq(_T_382, UInt<1>(0h0))
when _T_383 :
node _T_384 = eq(is_aligned, UInt<1>(0h0))
when _T_384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_386 = asUInt(reset)
node _T_387 = eq(_T_386, UInt<1>(0h0))
when _T_387 :
node _T_388 = eq(_T_385, UInt<1>(0h0))
when _T_388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_385, UInt<1>(0h1), "") : assert_49
node _T_389 = eq(io.in.a.bits.mask, mask)
node _T_390 = asUInt(reset)
node _T_391 = eq(_T_390, UInt<1>(0h0))
when _T_391 :
node _T_392 = eq(_T_389, UInt<1>(0h0))
when _T_392 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_389, UInt<1>(0h1), "") : assert_50
node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_394 = asUInt(reset)
node _T_395 = eq(_T_394, UInt<1>(0h0))
when _T_395 :
node _T_396 = eq(_T_393, UInt<1>(0h0))
when _T_396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_393, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_397, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<12>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 11, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 12)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<12>(0h80f))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_401 :
node _T_402 = asUInt(reset)
node _T_403 = eq(_T_402, UInt<1>(0h0))
when _T_403 :
node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_404 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_406 = asUInt(reset)
node _T_407 = eq(_T_406, UInt<1>(0h0))
when _T_407 :
node _T_408 = eq(_T_405, UInt<1>(0h0))
when _T_408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_405, UInt<1>(0h1), "") : assert_54
node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_410 = asUInt(reset)
node _T_411 = eq(_T_410, UInt<1>(0h0))
when _T_411 :
node _T_412 = eq(_T_409, UInt<1>(0h0))
when _T_412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_409, UInt<1>(0h1), "") : assert_55
node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_414 = asUInt(reset)
node _T_415 = eq(_T_414, UInt<1>(0h0))
when _T_415 :
node _T_416 = eq(_T_413, UInt<1>(0h0))
when _T_416 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_413, UInt<1>(0h1), "") : assert_56
node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_418 = asUInt(reset)
node _T_419 = eq(_T_418, UInt<1>(0h0))
when _T_419 :
node _T_420 = eq(_T_417, UInt<1>(0h0))
when _T_420 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_417, UInt<1>(0h1), "") : assert_57
node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_421 :
node _T_422 = asUInt(reset)
node _T_423 = eq(_T_422, UInt<1>(0h0))
when _T_423 :
node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_424 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_425 = asUInt(reset)
node _T_426 = eq(_T_425, UInt<1>(0h0))
when _T_426 :
node _T_427 = eq(sink_ok, UInt<1>(0h0))
when _T_427 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_429 = asUInt(reset)
node _T_430 = eq(_T_429, UInt<1>(0h0))
when _T_430 :
node _T_431 = eq(_T_428, UInt<1>(0h0))
when _T_431 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_428, UInt<1>(0h1), "") : assert_60
node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_433 = asUInt(reset)
node _T_434 = eq(_T_433, UInt<1>(0h0))
when _T_434 :
node _T_435 = eq(_T_432, UInt<1>(0h0))
when _T_435 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_432, UInt<1>(0h1), "") : assert_61
node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_437 = asUInt(reset)
node _T_438 = eq(_T_437, UInt<1>(0h0))
when _T_438 :
node _T_439 = eq(_T_436, UInt<1>(0h0))
when _T_439 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_436, UInt<1>(0h1), "") : assert_62
node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_441 = asUInt(reset)
node _T_442 = eq(_T_441, UInt<1>(0h0))
when _T_442 :
node _T_443 = eq(_T_440, UInt<1>(0h0))
when _T_443 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_440, UInt<1>(0h1), "") : assert_63
node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_445 = or(UInt<1>(0h0), _T_444)
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_445, UInt<1>(0h1), "") : assert_64
node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_449 :
node _T_450 = asUInt(reset)
node _T_451 = eq(_T_450, UInt<1>(0h0))
when _T_451 :
node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(sink_ok, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_457 = asUInt(reset)
node _T_458 = eq(_T_457, UInt<1>(0h0))
when _T_458 :
node _T_459 = eq(_T_456, UInt<1>(0h0))
when _T_459 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_456, UInt<1>(0h1), "") : assert_67
node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_461 = asUInt(reset)
node _T_462 = eq(_T_461, UInt<1>(0h0))
when _T_462 :
node _T_463 = eq(_T_460, UInt<1>(0h0))
when _T_463 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_460, UInt<1>(0h1), "") : assert_68
node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_465 = asUInt(reset)
node _T_466 = eq(_T_465, UInt<1>(0h0))
when _T_466 :
node _T_467 = eq(_T_464, UInt<1>(0h0))
when _T_467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_464, UInt<1>(0h1), "") : assert_69
node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_469 = or(_T_468, io.in.d.bits.corrupt)
node _T_470 = asUInt(reset)
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(_T_469, UInt<1>(0h0))
when _T_472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_469, UInt<1>(0h1), "") : assert_70
node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_474 = or(UInt<1>(0h0), _T_473)
node _T_475 = asUInt(reset)
node _T_476 = eq(_T_475, UInt<1>(0h0))
when _T_476 :
node _T_477 = eq(_T_474, UInt<1>(0h0))
when _T_477 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_474, UInt<1>(0h1), "") : assert_71
node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_478 :
node _T_479 = asUInt(reset)
node _T_480 = eq(_T_479, UInt<1>(0h0))
when _T_480 :
node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_481 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_483 = asUInt(reset)
node _T_484 = eq(_T_483, UInt<1>(0h0))
when _T_484 :
node _T_485 = eq(_T_482, UInt<1>(0h0))
when _T_485 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_482, UInt<1>(0h1), "") : assert_73
node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_487 = asUInt(reset)
node _T_488 = eq(_T_487, UInt<1>(0h0))
when _T_488 :
node _T_489 = eq(_T_486, UInt<1>(0h0))
when _T_489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_486, UInt<1>(0h1), "") : assert_74
node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_491 = or(UInt<1>(0h0), _T_490)
node _T_492 = asUInt(reset)
node _T_493 = eq(_T_492, UInt<1>(0h0))
when _T_493 :
node _T_494 = eq(_T_491, UInt<1>(0h0))
when _T_494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_491, UInt<1>(0h1), "") : assert_75
node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_495 :
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_500 = asUInt(reset)
node _T_501 = eq(_T_500, UInt<1>(0h0))
when _T_501 :
node _T_502 = eq(_T_499, UInt<1>(0h0))
when _T_502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_499, UInt<1>(0h1), "") : assert_77
node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_504 = or(_T_503, io.in.d.bits.corrupt)
node _T_505 = asUInt(reset)
node _T_506 = eq(_T_505, UInt<1>(0h0))
when _T_506 :
node _T_507 = eq(_T_504, UInt<1>(0h0))
when _T_507 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_504, UInt<1>(0h1), "") : assert_78
node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_509 = or(UInt<1>(0h0), _T_508)
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_509, UInt<1>(0h1), "") : assert_79
node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_513 :
node _T_514 = asUInt(reset)
node _T_515 = eq(_T_514, UInt<1>(0h0))
when _T_515 :
node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_516 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_518 = asUInt(reset)
node _T_519 = eq(_T_518, UInt<1>(0h0))
when _T_519 :
node _T_520 = eq(_T_517, UInt<1>(0h0))
when _T_520 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_517, UInt<1>(0h1), "") : assert_81
node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_522 = asUInt(reset)
node _T_523 = eq(_T_522, UInt<1>(0h0))
when _T_523 :
node _T_524 = eq(_T_521, UInt<1>(0h0))
when _T_524 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_521, UInt<1>(0h1), "") : assert_82
node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_526 = or(UInt<1>(0h0), _T_525)
node _T_527 = asUInt(reset)
node _T_528 = eq(_T_527, UInt<1>(0h0))
when _T_528 :
node _T_529 = eq(_T_526, UInt<1>(0h0))
when _T_529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_526, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<26>(0h0)
connect _WIRE.bits.source, UInt<12>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_531 = asUInt(reset)
node _T_532 = eq(_T_531, UInt<1>(0h0))
when _T_532 :
node _T_533 = eq(_T_530, UInt<1>(0h0))
when _T_533 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_530, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<26>(0h0)
connect _WIRE_2.bits.source, UInt<12>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_535 = asUInt(reset)
node _T_536 = eq(_T_535, UInt<1>(0h0))
when _T_536 :
node _T_537 = eq(_T_534, UInt<1>(0h0))
when _T_537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_534, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_T_538, UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_538, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_542 = eq(a_first, UInt<1>(0h0))
node _T_543 = and(io.in.a.valid, _T_542)
when _T_543 :
node _T_544 = eq(io.in.a.bits.opcode, opcode)
node _T_545 = asUInt(reset)
node _T_546 = eq(_T_545, UInt<1>(0h0))
when _T_546 :
node _T_547 = eq(_T_544, UInt<1>(0h0))
when _T_547 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_544, UInt<1>(0h1), "") : assert_87
node _T_548 = eq(io.in.a.bits.param, param)
node _T_549 = asUInt(reset)
node _T_550 = eq(_T_549, UInt<1>(0h0))
when _T_550 :
node _T_551 = eq(_T_548, UInt<1>(0h0))
when _T_551 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_548, UInt<1>(0h1), "") : assert_88
node _T_552 = eq(io.in.a.bits.size, size)
node _T_553 = asUInt(reset)
node _T_554 = eq(_T_553, UInt<1>(0h0))
when _T_554 :
node _T_555 = eq(_T_552, UInt<1>(0h0))
when _T_555 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_552, UInt<1>(0h1), "") : assert_89
node _T_556 = eq(io.in.a.bits.source, source)
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_556, UInt<1>(0h1), "") : assert_90
node _T_560 = eq(io.in.a.bits.address, address)
node _T_561 = asUInt(reset)
node _T_562 = eq(_T_561, UInt<1>(0h0))
when _T_562 :
node _T_563 = eq(_T_560, UInt<1>(0h0))
when _T_563 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_560, UInt<1>(0h1), "") : assert_91
node _T_564 = and(io.in.a.ready, io.in.a.valid)
node _T_565 = and(_T_564, a_first)
when _T_565 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_566 = eq(d_first, UInt<1>(0h0))
node _T_567 = and(io.in.d.valid, _T_566)
when _T_567 :
node _T_568 = eq(io.in.d.bits.opcode, opcode_1)
node _T_569 = asUInt(reset)
node _T_570 = eq(_T_569, UInt<1>(0h0))
when _T_570 :
node _T_571 = eq(_T_568, UInt<1>(0h0))
when _T_571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_568, UInt<1>(0h1), "") : assert_92
node _T_572 = eq(io.in.d.bits.param, param_1)
node _T_573 = asUInt(reset)
node _T_574 = eq(_T_573, UInt<1>(0h0))
when _T_574 :
node _T_575 = eq(_T_572, UInt<1>(0h0))
when _T_575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_572, UInt<1>(0h1), "") : assert_93
node _T_576 = eq(io.in.d.bits.size, size_1)
node _T_577 = asUInt(reset)
node _T_578 = eq(_T_577, UInt<1>(0h0))
when _T_578 :
node _T_579 = eq(_T_576, UInt<1>(0h0))
when _T_579 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_576, UInt<1>(0h1), "") : assert_94
node _T_580 = eq(io.in.d.bits.source, source_1)
node _T_581 = asUInt(reset)
node _T_582 = eq(_T_581, UInt<1>(0h0))
when _T_582 :
node _T_583 = eq(_T_580, UInt<1>(0h0))
when _T_583 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_580, UInt<1>(0h1), "") : assert_95
node _T_584 = eq(io.in.d.bits.sink, sink)
node _T_585 = asUInt(reset)
node _T_586 = eq(_T_585, UInt<1>(0h0))
when _T_586 :
node _T_587 = eq(_T_584, UInt<1>(0h0))
when _T_587 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_584, UInt<1>(0h1), "") : assert_96
node _T_588 = eq(io.in.d.bits.denied, denied)
node _T_589 = asUInt(reset)
node _T_590 = eq(_T_589, UInt<1>(0h0))
when _T_590 :
node _T_591 = eq(_T_588, UInt<1>(0h0))
when _T_591 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_588, UInt<1>(0h1), "") : assert_97
node _T_592 = and(io.in.d.ready, io.in.d.valid)
node _T_593 = and(_T_592, d_first)
when _T_593 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<2064>, clock, reset, UInt<2064>(0h0)
regreset inflight_opcodes : UInt<8256>, clock, reset, UInt<8256>(0h0)
regreset inflight_sizes : UInt<8256>, clock, reset, UInt<8256>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<2064>
connect a_set, UInt<2064>(0h0)
wire a_set_wo_ready : UInt<2064>
connect a_set_wo_ready, UInt<2064>(0h0)
wire a_opcodes_set : UInt<8256>
connect a_opcodes_set, UInt<8256>(0h0)
wire a_sizes_set : UInt<8256>
connect a_sizes_set, UInt<8256>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<3>
connect a_sizes_set_interm, UInt<3>(0h0)
node _T_594 = and(io.in.a.valid, a_first_1)
node _T_595 = and(_T_594, UInt<1>(0h1))
when _T_595 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_596 = and(io.in.a.ready, io.in.a.valid)
node _T_597 = and(_T_596, a_first_1)
node _T_598 = and(_T_597, UInt<1>(0h1))
when _T_598 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_599 = dshr(inflight, io.in.a.bits.source)
node _T_600 = bits(_T_599, 0, 0)
node _T_601 = eq(_T_600, UInt<1>(0h0))
node _T_602 = asUInt(reset)
node _T_603 = eq(_T_602, UInt<1>(0h0))
when _T_603 :
node _T_604 = eq(_T_601, UInt<1>(0h0))
when _T_604 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_601, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<2064>
connect d_clr, UInt<2064>(0h0)
wire d_clr_wo_ready : UInt<2064>
connect d_clr_wo_ready, UInt<2064>(0h0)
wire d_opcodes_clr : UInt<8256>
connect d_opcodes_clr, UInt<8256>(0h0)
wire d_sizes_clr : UInt<8256>
connect d_sizes_clr, UInt<8256>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_605 = and(io.in.d.valid, d_first_1)
node _T_606 = and(_T_605, UInt<1>(0h1))
node _T_607 = eq(d_release_ack, UInt<1>(0h0))
node _T_608 = and(_T_606, _T_607)
when _T_608 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_609 = and(io.in.d.ready, io.in.d.valid)
node _T_610 = and(_T_609, d_first_1)
node _T_611 = and(_T_610, UInt<1>(0h1))
node _T_612 = eq(d_release_ack, UInt<1>(0h0))
node _T_613 = and(_T_611, _T_612)
when _T_613 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_614 = and(io.in.d.valid, d_first_1)
node _T_615 = and(_T_614, UInt<1>(0h1))
node _T_616 = eq(d_release_ack, UInt<1>(0h0))
node _T_617 = and(_T_615, _T_616)
when _T_617 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_618 = dshr(inflight, io.in.d.bits.source)
node _T_619 = bits(_T_618, 0, 0)
node _T_620 = or(_T_619, same_cycle_resp)
node _T_621 = asUInt(reset)
node _T_622 = eq(_T_621, UInt<1>(0h0))
when _T_622 :
node _T_623 = eq(_T_620, UInt<1>(0h0))
when _T_623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_620, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_626 = or(_T_624, _T_625)
node _T_627 = asUInt(reset)
node _T_628 = eq(_T_627, UInt<1>(0h0))
when _T_628 :
node _T_629 = eq(_T_626, UInt<1>(0h0))
when _T_629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_626, UInt<1>(0h1), "") : assert_100
node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_630, UInt<1>(0h1), "") : assert_101
else :
node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_636 = or(_T_634, _T_635)
node _T_637 = asUInt(reset)
node _T_638 = eq(_T_637, UInt<1>(0h0))
when _T_638 :
node _T_639 = eq(_T_636, UInt<1>(0h0))
when _T_639 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_636, UInt<1>(0h1), "") : assert_102
node _T_640 = eq(io.in.d.bits.size, a_size_lookup)
node _T_641 = asUInt(reset)
node _T_642 = eq(_T_641, UInt<1>(0h0))
when _T_642 :
node _T_643 = eq(_T_640, UInt<1>(0h0))
when _T_643 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_640, UInt<1>(0h1), "") : assert_103
node _T_644 = and(io.in.d.valid, d_first_1)
node _T_645 = and(_T_644, a_first_1)
node _T_646 = and(_T_645, io.in.a.valid)
node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_648 = and(_T_646, _T_647)
node _T_649 = eq(d_release_ack, UInt<1>(0h0))
node _T_650 = and(_T_648, _T_649)
when _T_650 :
node _T_651 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_652 = or(_T_651, io.in.a.ready)
node _T_653 = asUInt(reset)
node _T_654 = eq(_T_653, UInt<1>(0h0))
when _T_654 :
node _T_655 = eq(_T_652, UInt<1>(0h0))
when _T_655 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_652, UInt<1>(0h1), "") : assert_104
node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_657 = orr(a_set_wo_ready)
node _T_658 = eq(_T_657, UInt<1>(0h0))
node _T_659 = or(_T_656, _T_658)
node _T_660 = asUInt(reset)
node _T_661 = eq(_T_660, UInt<1>(0h0))
when _T_661 :
node _T_662 = eq(_T_659, UInt<1>(0h0))
when _T_662 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_659, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_72
node _T_663 = orr(inflight)
node _T_664 = eq(_T_663, UInt<1>(0h0))
node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_666 = or(_T_664, _T_665)
node _T_667 = lt(watchdog, plusarg_reader.out)
node _T_668 = or(_T_666, _T_667)
node _T_669 = asUInt(reset)
node _T_670 = eq(_T_669, UInt<1>(0h0))
when _T_670 :
node _T_671 = eq(_T_668, UInt<1>(0h0))
when _T_671 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_668, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_672 = and(io.in.a.ready, io.in.a.valid)
node _T_673 = and(io.in.d.ready, io.in.d.valid)
node _T_674 = or(_T_672, _T_673)
when _T_674 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<2064>, clock, reset, UInt<2064>(0h0)
regreset inflight_opcodes_1 : UInt<8256>, clock, reset, UInt<8256>(0h0)
regreset inflight_sizes_1 : UInt<8256>, clock, reset, UInt<8256>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<26>(0h0)
connect _c_first_WIRE.bits.source, UInt<12>(0h0)
connect _c_first_WIRE.bits.size, UInt<2>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<26>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<12>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<2064>
connect c_set, UInt<2064>(0h0)
wire c_set_wo_ready : UInt<2064>
connect c_set_wo_ready, UInt<2064>(0h0)
wire c_opcodes_set : UInt<8256>
connect c_opcodes_set, UInt<8256>(0h0)
wire c_sizes_set : UInt<8256>
connect c_sizes_set, UInt<8256>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<3>
connect c_sizes_set_interm, UInt<3>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<26>(0h0)
connect _WIRE_6.bits.source, UInt<12>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_675 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<26>(0h0)
connect _WIRE_8.bits.source, UInt<12>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_678 = and(_T_676, _T_677)
node _T_679 = and(_T_675, _T_678)
when _T_679 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<26>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<12>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<26>(0h0)
connect _WIRE_10.bits.source, UInt<12>(0h0)
connect _WIRE_10.bits.size, UInt<2>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_681 = and(_T_680, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<26>(0h0)
connect _WIRE_12.bits.source, UInt<12>(0h0)
connect _WIRE_12.bits.size, UInt<2>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_684 = and(_T_682, _T_683)
node _T_685 = and(_T_681, _T_684)
when _T_685 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<26>(0h0)
connect _c_set_WIRE.bits.source, UInt<12>(0h0)
connect _c_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<26>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<12>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<26>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<12>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<26>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<12>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<26>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<12>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<26>(0h0)
connect _WIRE_14.bits.source, UInt<12>(0h0)
connect _WIRE_14.bits.size, UInt<2>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_686 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_687 = bits(_T_686, 0, 0)
node _T_688 = eq(_T_687, UInt<1>(0h0))
node _T_689 = asUInt(reset)
node _T_690 = eq(_T_689, UInt<1>(0h0))
when _T_690 :
node _T_691 = eq(_T_688, UInt<1>(0h0))
when _T_691 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_688, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<26>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<12>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<26>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<12>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<2064>
connect d_clr_1, UInt<2064>(0h0)
wire d_clr_wo_ready_1 : UInt<2064>
connect d_clr_wo_ready_1, UInt<2064>(0h0)
wire d_opcodes_clr_1 : UInt<8256>
connect d_opcodes_clr_1, UInt<8256>(0h0)
wire d_sizes_clr_1 : UInt<8256>
connect d_sizes_clr_1, UInt<8256>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_692 = and(io.in.d.valid, d_first_2)
node _T_693 = and(_T_692, UInt<1>(0h1))
node _T_694 = and(_T_693, d_release_ack_1)
when _T_694 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_695 = and(io.in.d.ready, io.in.d.valid)
node _T_696 = and(_T_695, d_first_2)
node _T_697 = and(_T_696, UInt<1>(0h1))
node _T_698 = and(_T_697, d_release_ack_1)
when _T_698 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_699 = and(io.in.d.valid, d_first_2)
node _T_700 = and(_T_699, UInt<1>(0h1))
node _T_701 = and(_T_700, d_release_ack_1)
when _T_701 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<26>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<12>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<26>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<12>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<26>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<12>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_702 = dshr(inflight_1, io.in.d.bits.source)
node _T_703 = bits(_T_702, 0, 0)
node _T_704 = or(_T_703, same_cycle_resp_1)
node _T_705 = asUInt(reset)
node _T_706 = eq(_T_705, UInt<1>(0h0))
when _T_706 :
node _T_707 = eq(_T_704, UInt<1>(0h0))
when _T_707 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_704, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<26>(0h0)
connect _WIRE_16.bits.source, UInt<12>(0h0)
connect _WIRE_16.bits.size, UInt<2>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_709 = asUInt(reset)
node _T_710 = eq(_T_709, UInt<1>(0h0))
when _T_710 :
node _T_711 = eq(_T_708, UInt<1>(0h0))
when _T_711 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_708, UInt<1>(0h1), "") : assert_109
else :
node _T_712 = eq(io.in.d.bits.size, c_size_lookup)
node _T_713 = asUInt(reset)
node _T_714 = eq(_T_713, UInt<1>(0h0))
when _T_714 :
node _T_715 = eq(_T_712, UInt<1>(0h0))
when _T_715 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_712, UInt<1>(0h1), "") : assert_110
node _T_716 = and(io.in.d.valid, d_first_2)
node _T_717 = and(_T_716, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<26>(0h0)
connect _WIRE_18.bits.source, UInt<12>(0h0)
connect _WIRE_18.bits.size, UInt<2>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_718 = and(_T_717, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<26>(0h0)
connect _WIRE_20.bits.source, UInt<12>(0h0)
connect _WIRE_20.bits.size, UInt<2>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_720 = and(_T_718, _T_719)
node _T_721 = and(_T_720, d_release_ack_1)
node _T_722 = eq(c_probe_ack, UInt<1>(0h0))
node _T_723 = and(_T_721, _T_722)
when _T_723 :
node _T_724 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<26>(0h0)
connect _WIRE_22.bits.source, UInt<12>(0h0)
connect _WIRE_22.bits.size, UInt<2>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_725 = or(_T_724, _WIRE_23.ready)
node _T_726 = asUInt(reset)
node _T_727 = eq(_T_726, UInt<1>(0h0))
when _T_727 :
node _T_728 = eq(_T_725, UInt<1>(0h0))
when _T_728 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_725, UInt<1>(0h1), "") : assert_111
node _T_729 = orr(c_set_wo_ready)
when _T_729 :
node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_731 = asUInt(reset)
node _T_732 = eq(_T_731, UInt<1>(0h0))
when _T_732 :
node _T_733 = eq(_T_730, UInt<1>(0h0))
when _T_733 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_730, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_73
node _T_734 = orr(inflight_1)
node _T_735 = eq(_T_734, UInt<1>(0h0))
node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_737 = or(_T_735, _T_736)
node _T_738 = lt(watchdog_1, plusarg_reader_1.out)
node _T_739 = or(_T_737, _T_738)
node _T_740 = asUInt(reset)
node _T_741 = eq(_T_740, UInt<1>(0h0))
when _T_741 :
node _T_742 = eq(_T_739, UInt<1>(0h0))
when _T_742 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_739, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<26>(0h0)
connect _WIRE_24.bits.source, UInt<12>(0h0)
connect _WIRE_24.bits.size, UInt<2>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_744 = and(io.in.d.ready, io.in.d.valid)
node _T_745 = or(_T_743, _T_744)
when _T_745 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_36( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [11:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [25:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [11:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [11:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [25:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [11:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count = 1'h0; // @[Edges.scala:234:25]
wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27]
wire c_first_count = 1'h0; // @[Edges.scala:234:25]
wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21]
wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67]
wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last = 1'h1; // @[Edges.scala:232:33]
wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33]
wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_first_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_first_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_first_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_first_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_set_wo_ready_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_set_wo_ready_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_opcodes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_opcodes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_sizes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_sizes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_opcodes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_opcodes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_sizes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_sizes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_probe_ack_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_probe_ack_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_probe_ack_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_probe_ack_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _same_cycle_resp_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _same_cycle_resp_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _same_cycle_resp_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _same_cycle_resp_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _same_cycle_resp_WIRE_4_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _same_cycle_resp_WIRE_5_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_first_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_first_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_first_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_first_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_set_wo_ready_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_set_wo_ready_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_opcodes_set_interm_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_opcodes_set_interm_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_sizes_set_interm_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_sizes_set_interm_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_opcodes_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_opcodes_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_sizes_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_sizes_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_probe_ack_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_probe_ack_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_probe_ack_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_probe_ack_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _same_cycle_resp_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _same_cycle_resp_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _same_cycle_resp_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _same_cycle_resp_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _same_cycle_resp_WIRE_4_bits_source = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _same_cycle_resp_WIRE_5_bits_source = 12'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46]
wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [32769:0] _c_sizes_set_T_1 = 32770'h0; // @[Monitor.scala:768:52]
wire [14:0] _c_opcodes_set_T = 15'h0; // @[Monitor.scala:767:79]
wire [14:0] _c_sizes_set_T = 15'h0; // @[Monitor.scala:768:77]
wire [32770:0] _c_opcodes_set_T_1 = 32771'h0; // @[Monitor.scala:767:54]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [4095:0] _c_set_wo_ready_T = 4096'h1; // @[OneHot.scala:58:35]
wire [4095:0] _c_set_T = 4096'h1; // @[OneHot.scala:58:35]
wire [8255:0] c_opcodes_set = 8256'h0; // @[Monitor.scala:740:34]
wire [8255:0] c_sizes_set = 8256'h0; // @[Monitor.scala:741:34]
wire [2063:0] c_set = 2064'h0; // @[Monitor.scala:738:34]
wire [2063:0] c_set_wo_ready = 2064'h0; // @[Monitor.scala:739:34]
wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76]
wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [11:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [11:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [11:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [11:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [11:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [11:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [11:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [11:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [11:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [11:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [11:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [11:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_4 = source_ok_uncommonBits < 12'h810; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [25:0] _is_aligned_T = {23'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 26'h0; // @[Edges.scala:21:{16,24}]
wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [11:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [11:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [11:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [11:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [11:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [11:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [11:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [11:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [11:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}]
wire [11:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_10 = source_ok_uncommonBits_1 < 12'h810; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_672; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35]
wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
reg a_first_counter; // @[Edges.scala:229:27]
wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28]
wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [1:0] size; // @[Monitor.scala:389:22]
reg [11:0] source; // @[Monitor.scala:390:22]
reg [25:0] address; // @[Monitor.scala:391:22]
wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_745; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35]
wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35]
wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
reg d_first_counter; // @[Edges.scala:229:27]
wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28]
wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg [11:0] source_1; // @[Monitor.scala:541:22]
reg [2063:0] inflight; // @[Monitor.scala:614:27]
reg [8255:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [8255:0] inflight_sizes; // @[Monitor.scala:618:33]
wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
reg a_first_counter_1; // @[Edges.scala:229:27]
wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire [2063:0] a_set; // @[Monitor.scala:626:34]
wire [2063:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [8255:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [8255:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [14:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [14:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [14:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [14:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [14:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [14:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [14:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [14:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [14:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [8255:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [8255:0] _a_opcode_lookup_T_6 = {8252'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [8255:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[8255:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [8255:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [8255:0] _a_size_lookup_T_6 = {8252'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [8255:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[8255:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [4095:0] _GEN_2 = 4096'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [4095:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [4095:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35]
wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_598 ? _a_set_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [14:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [14:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [14:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [32770:0] _a_opcodes_set_T_1 = {32767'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[8255:0] : 8256'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [32769:0] _a_sizes_set_T_1 = {32767'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[8255:0] : 8256'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [2063:0] d_clr; // @[Monitor.scala:664:34]
wire [2063:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [8255:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [8255:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [4095:0] _GEN_5 = 4096'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [4095:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [4095:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [4095:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [4095:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35]
wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_613 ? _d_clr_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35]
wire [32782:0] _d_opcodes_clr_T_5 = 32783'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[8255:0] : 8256'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [32782:0] _d_sizes_clr_T_5 = 32783'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[8255:0] : 8256'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [2063:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [2063:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [2063:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [8255:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [8255:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [8255:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [8255:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [8255:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [8255:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [2063:0] inflight_1; // @[Monitor.scala:726:35]
wire [2063:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [8255:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [8255:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [8255:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [8255:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
reg d_first_counter_2; // @[Edges.scala:229:27]
wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28]
wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [8255:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [8255:0] _c_opcode_lookup_T_6 = {8252'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [8255:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[8255:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [8255:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [8255:0] _c_size_lookup_T_6 = {8252'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [8255:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[8255:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [2063:0] d_clr_1; // @[Monitor.scala:774:34]
wire [2063:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [8255:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [8255:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[2063:0] : 2064'h0; // @[OneHot.scala:58:35]
wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_698 ? _d_clr_T_1[2063:0] : 2064'h0; // @[OneHot.scala:58:35]
wire [32782:0] _d_opcodes_clr_T_11 = 32783'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[8255:0] : 8256'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [32782:0] _d_sizes_clr_T_11 = 32783'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[8255:0] : 8256'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 12'h0; // @[Monitor.scala:36:7, :795:113]
wire [2063:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [2063:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [8255:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [8255:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [8255:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [8255:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_350 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_350( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_175 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_source_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_185
connect io_out_source_valid.clock, clock
connect io_out_source_valid.reset, reset
connect io_out_source_valid.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_source_valid.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_175( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_185 io_out_source_valid ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_180 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_sink_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_194
connect io_out_sink_valid_0.clock, clock
connect io_out_sink_valid_0.reset, reset
connect io_out_sink_valid_0.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_sink_valid_0.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_180( // @[AsyncQueue.scala:58:7]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in = 1'h1; // @[ShiftReg.scala:45:23]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_194 io_out_sink_valid_0 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PMAChecker_2 :
input clock : Clock
input reset : Reset
output io : { flip paddr : UInt, resp : { cacheable : UInt<1>, r : UInt<1>, w : UInt<1>, pp : UInt<1>, al : UInt<1>, aa : UInt<1>, x : UInt<1>, eff : UInt<1>}}
node _legal_address_T = xor(io.paddr, UInt<1>(0h0))
node _legal_address_T_1 = cvt(_legal_address_T)
node _legal_address_T_2 = and(_legal_address_T_1, asSInt(UInt<13>(0h1000)))
node _legal_address_T_3 = asSInt(_legal_address_T_2)
node _legal_address_T_4 = eq(_legal_address_T_3, asSInt(UInt<1>(0h0)))
node _legal_address_T_5 = xor(io.paddr, UInt<13>(0h1000))
node _legal_address_T_6 = cvt(_legal_address_T_5)
node _legal_address_T_7 = and(_legal_address_T_6, asSInt(UInt<13>(0h1000)))
node _legal_address_T_8 = asSInt(_legal_address_T_7)
node _legal_address_T_9 = eq(_legal_address_T_8, asSInt(UInt<1>(0h0)))
node _legal_address_T_10 = xor(io.paddr, UInt<14>(0h3000))
node _legal_address_T_11 = cvt(_legal_address_T_10)
node _legal_address_T_12 = and(_legal_address_T_11, asSInt(UInt<13>(0h1000)))
node _legal_address_T_13 = asSInt(_legal_address_T_12)
node _legal_address_T_14 = eq(_legal_address_T_13, asSInt(UInt<1>(0h0)))
node _legal_address_T_15 = xor(io.paddr, UInt<17>(0h10000))
node _legal_address_T_16 = cvt(_legal_address_T_15)
node _legal_address_T_17 = and(_legal_address_T_16, asSInt(UInt<17>(0h10000)))
node _legal_address_T_18 = asSInt(_legal_address_T_17)
node _legal_address_T_19 = eq(_legal_address_T_18, asSInt(UInt<1>(0h0)))
node _legal_address_T_20 = xor(io.paddr, UInt<21>(0h100000))
node _legal_address_T_21 = cvt(_legal_address_T_20)
node _legal_address_T_22 = and(_legal_address_T_21, asSInt(UInt<13>(0h1000)))
node _legal_address_T_23 = asSInt(_legal_address_T_22)
node _legal_address_T_24 = eq(_legal_address_T_23, asSInt(UInt<1>(0h0)))
node _legal_address_T_25 = xor(io.paddr, UInt<21>(0h110000))
node _legal_address_T_26 = cvt(_legal_address_T_25)
node _legal_address_T_27 = and(_legal_address_T_26, asSInt(UInt<13>(0h1000)))
node _legal_address_T_28 = asSInt(_legal_address_T_27)
node _legal_address_T_29 = eq(_legal_address_T_28, asSInt(UInt<1>(0h0)))
node _legal_address_T_30 = xor(io.paddr, UInt<26>(0h2000000))
node _legal_address_T_31 = cvt(_legal_address_T_30)
node _legal_address_T_32 = and(_legal_address_T_31, asSInt(UInt<17>(0h10000)))
node _legal_address_T_33 = asSInt(_legal_address_T_32)
node _legal_address_T_34 = eq(_legal_address_T_33, asSInt(UInt<1>(0h0)))
node _legal_address_T_35 = xor(io.paddr, UInt<26>(0h2010000))
node _legal_address_T_36 = cvt(_legal_address_T_35)
node _legal_address_T_37 = and(_legal_address_T_36, asSInt(UInt<13>(0h1000)))
node _legal_address_T_38 = asSInt(_legal_address_T_37)
node _legal_address_T_39 = eq(_legal_address_T_38, asSInt(UInt<1>(0h0)))
node _legal_address_T_40 = xor(io.paddr, UInt<28>(0h8000000))
node _legal_address_T_41 = cvt(_legal_address_T_40)
node _legal_address_T_42 = and(_legal_address_T_41, asSInt(UInt<17>(0h10000)))
node _legal_address_T_43 = asSInt(_legal_address_T_42)
node _legal_address_T_44 = eq(_legal_address_T_43, asSInt(UInt<1>(0h0)))
node _legal_address_T_45 = xor(io.paddr, UInt<28>(0hc000000))
node _legal_address_T_46 = cvt(_legal_address_T_45)
node _legal_address_T_47 = and(_legal_address_T_46, asSInt(UInt<27>(0h4000000)))
node _legal_address_T_48 = asSInt(_legal_address_T_47)
node _legal_address_T_49 = eq(_legal_address_T_48, asSInt(UInt<1>(0h0)))
node _legal_address_T_50 = xor(io.paddr, UInt<29>(0h10020000))
node _legal_address_T_51 = cvt(_legal_address_T_50)
node _legal_address_T_52 = and(_legal_address_T_51, asSInt(UInt<13>(0h1000)))
node _legal_address_T_53 = asSInt(_legal_address_T_52)
node _legal_address_T_54 = eq(_legal_address_T_53, asSInt(UInt<1>(0h0)))
node _legal_address_T_55 = xor(io.paddr, UInt<32>(0h80000000))
node _legal_address_T_56 = cvt(_legal_address_T_55)
node _legal_address_T_57 = and(_legal_address_T_56, asSInt(UInt<29>(0h10000000)))
node _legal_address_T_58 = asSInt(_legal_address_T_57)
node _legal_address_T_59 = eq(_legal_address_T_58, asSInt(UInt<1>(0h0)))
wire _legal_address_WIRE : UInt<1>[12]
connect _legal_address_WIRE[0], _legal_address_T_4
connect _legal_address_WIRE[1], _legal_address_T_9
connect _legal_address_WIRE[2], _legal_address_T_14
connect _legal_address_WIRE[3], _legal_address_T_19
connect _legal_address_WIRE[4], _legal_address_T_24
connect _legal_address_WIRE[5], _legal_address_T_29
connect _legal_address_WIRE[6], _legal_address_T_34
connect _legal_address_WIRE[7], _legal_address_T_39
connect _legal_address_WIRE[8], _legal_address_T_44
connect _legal_address_WIRE[9], _legal_address_T_49
connect _legal_address_WIRE[10], _legal_address_T_54
connect _legal_address_WIRE[11], _legal_address_T_59
node _legal_address_T_60 = or(_legal_address_WIRE[0], _legal_address_WIRE[1])
node _legal_address_T_61 = or(_legal_address_T_60, _legal_address_WIRE[2])
node _legal_address_T_62 = or(_legal_address_T_61, _legal_address_WIRE[3])
node _legal_address_T_63 = or(_legal_address_T_62, _legal_address_WIRE[4])
node _legal_address_T_64 = or(_legal_address_T_63, _legal_address_WIRE[5])
node _legal_address_T_65 = or(_legal_address_T_64, _legal_address_WIRE[6])
node _legal_address_T_66 = or(_legal_address_T_65, _legal_address_WIRE[7])
node _legal_address_T_67 = or(_legal_address_T_66, _legal_address_WIRE[8])
node _legal_address_T_68 = or(_legal_address_T_67, _legal_address_WIRE[9])
node _legal_address_T_69 = or(_legal_address_T_68, _legal_address_WIRE[10])
node legal_address = or(_legal_address_T_69, _legal_address_WIRE[11])
node _io_resp_cacheable_T = xor(io.paddr, UInt<1>(0h0))
node _io_resp_cacheable_T_1 = cvt(_io_resp_cacheable_T)
node _io_resp_cacheable_T_2 = and(_io_resp_cacheable_T_1, asSInt(UInt<33>(0h8c000000)))
node _io_resp_cacheable_T_3 = asSInt(_io_resp_cacheable_T_2)
node _io_resp_cacheable_T_4 = eq(_io_resp_cacheable_T_3, asSInt(UInt<1>(0h0)))
node _io_resp_cacheable_T_5 = xor(io.paddr, UInt<17>(0h10000))
node _io_resp_cacheable_T_6 = cvt(_io_resp_cacheable_T_5)
node _io_resp_cacheable_T_7 = and(_io_resp_cacheable_T_6, asSInt(UInt<33>(0h8c011000)))
node _io_resp_cacheable_T_8 = asSInt(_io_resp_cacheable_T_7)
node _io_resp_cacheable_T_9 = eq(_io_resp_cacheable_T_8, asSInt(UInt<1>(0h0)))
node _io_resp_cacheable_T_10 = xor(io.paddr, UInt<28>(0hc000000))
node _io_resp_cacheable_T_11 = cvt(_io_resp_cacheable_T_10)
node _io_resp_cacheable_T_12 = and(_io_resp_cacheable_T_11, asSInt(UInt<33>(0h8c000000)))
node _io_resp_cacheable_T_13 = asSInt(_io_resp_cacheable_T_12)
node _io_resp_cacheable_T_14 = eq(_io_resp_cacheable_T_13, asSInt(UInt<1>(0h0)))
node _io_resp_cacheable_T_15 = or(_io_resp_cacheable_T_4, _io_resp_cacheable_T_9)
node _io_resp_cacheable_T_16 = or(_io_resp_cacheable_T_15, _io_resp_cacheable_T_14)
node _io_resp_cacheable_T_17 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_cacheable_T_18 = cvt(_io_resp_cacheable_T_17)
node _io_resp_cacheable_T_19 = and(_io_resp_cacheable_T_18, asSInt(UInt<33>(0h8c010000)))
node _io_resp_cacheable_T_20 = asSInt(_io_resp_cacheable_T_19)
node _io_resp_cacheable_T_21 = eq(_io_resp_cacheable_T_20, asSInt(UInt<1>(0h0)))
node _io_resp_cacheable_T_22 = xor(io.paddr, UInt<32>(0h80000000))
node _io_resp_cacheable_T_23 = cvt(_io_resp_cacheable_T_22)
node _io_resp_cacheable_T_24 = and(_io_resp_cacheable_T_23, asSInt(UInt<33>(0h80000000)))
node _io_resp_cacheable_T_25 = asSInt(_io_resp_cacheable_T_24)
node _io_resp_cacheable_T_26 = eq(_io_resp_cacheable_T_25, asSInt(UInt<1>(0h0)))
node _io_resp_cacheable_T_27 = or(_io_resp_cacheable_T_21, _io_resp_cacheable_T_26)
node _io_resp_cacheable_T_28 = mux(_io_resp_cacheable_T_16, UInt<1>(0h0), UInt<1>(0h0))
node _io_resp_cacheable_T_29 = mux(_io_resp_cacheable_T_27, UInt<1>(0h1), UInt<1>(0h0))
node _io_resp_cacheable_T_30 = or(_io_resp_cacheable_T_28, _io_resp_cacheable_T_29)
wire _io_resp_cacheable_WIRE : UInt<1>
connect _io_resp_cacheable_WIRE, _io_resp_cacheable_T_30
node _io_resp_cacheable_T_31 = and(legal_address, _io_resp_cacheable_WIRE)
connect io.resp.cacheable, _io_resp_cacheable_T_31
node _io_resp_r_T = xor(io.paddr, UInt<1>(0h0))
node _io_resp_r_T_1 = cvt(_io_resp_r_T)
node _io_resp_r_T_2 = and(_io_resp_r_T_1, asSInt(UInt<1>(0h0)))
node _io_resp_r_T_3 = asSInt(_io_resp_r_T_2)
node _io_resp_r_T_4 = eq(_io_resp_r_T_3, asSInt(UInt<1>(0h0)))
node _io_resp_r_T_5 = and(legal_address, UInt<1>(0h1))
connect io.resp.r, _io_resp_r_T_5
node _io_resp_w_T = xor(io.paddr, UInt<1>(0h0))
node _io_resp_w_T_1 = cvt(_io_resp_w_T)
node _io_resp_w_T_2 = and(_io_resp_w_T_1, asSInt(UInt<33>(0h98110000)))
node _io_resp_w_T_3 = asSInt(_io_resp_w_T_2)
node _io_resp_w_T_4 = eq(_io_resp_w_T_3, asSInt(UInt<1>(0h0)))
node _io_resp_w_T_5 = xor(io.paddr, UInt<21>(0h100000))
node _io_resp_w_T_6 = cvt(_io_resp_w_T_5)
node _io_resp_w_T_7 = and(_io_resp_w_T_6, asSInt(UInt<33>(0h9a101000)))
node _io_resp_w_T_8 = asSInt(_io_resp_w_T_7)
node _io_resp_w_T_9 = eq(_io_resp_w_T_8, asSInt(UInt<1>(0h0)))
node _io_resp_w_T_10 = xor(io.paddr, UInt<26>(0h2010000))
node _io_resp_w_T_11 = cvt(_io_resp_w_T_10)
node _io_resp_w_T_12 = and(_io_resp_w_T_11, asSInt(UInt<33>(0h9a111000)))
node _io_resp_w_T_13 = asSInt(_io_resp_w_T_12)
node _io_resp_w_T_14 = eq(_io_resp_w_T_13, asSInt(UInt<1>(0h0)))
node _io_resp_w_T_15 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_w_T_16 = cvt(_io_resp_w_T_15)
node _io_resp_w_T_17 = and(_io_resp_w_T_16, asSInt(UInt<33>(0h98000000)))
node _io_resp_w_T_18 = asSInt(_io_resp_w_T_17)
node _io_resp_w_T_19 = eq(_io_resp_w_T_18, asSInt(UInt<1>(0h0)))
node _io_resp_w_T_20 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_w_T_21 = cvt(_io_resp_w_T_20)
node _io_resp_w_T_22 = and(_io_resp_w_T_21, asSInt(UInt<33>(0h9a110000)))
node _io_resp_w_T_23 = asSInt(_io_resp_w_T_22)
node _io_resp_w_T_24 = eq(_io_resp_w_T_23, asSInt(UInt<1>(0h0)))
node _io_resp_w_T_25 = xor(io.paddr, UInt<29>(0h10000000))
node _io_resp_w_T_26 = cvt(_io_resp_w_T_25)
node _io_resp_w_T_27 = and(_io_resp_w_T_26, asSInt(UInt<33>(0h9a111000)))
node _io_resp_w_T_28 = asSInt(_io_resp_w_T_27)
node _io_resp_w_T_29 = eq(_io_resp_w_T_28, asSInt(UInt<1>(0h0)))
node _io_resp_w_T_30 = xor(io.paddr, UInt<32>(0h80000000))
node _io_resp_w_T_31 = cvt(_io_resp_w_T_30)
node _io_resp_w_T_32 = and(_io_resp_w_T_31, asSInt(UInt<33>(0h90000000)))
node _io_resp_w_T_33 = asSInt(_io_resp_w_T_32)
node _io_resp_w_T_34 = eq(_io_resp_w_T_33, asSInt(UInt<1>(0h0)))
node _io_resp_w_T_35 = or(_io_resp_w_T_4, _io_resp_w_T_9)
node _io_resp_w_T_36 = or(_io_resp_w_T_35, _io_resp_w_T_14)
node _io_resp_w_T_37 = or(_io_resp_w_T_36, _io_resp_w_T_19)
node _io_resp_w_T_38 = or(_io_resp_w_T_37, _io_resp_w_T_24)
node _io_resp_w_T_39 = or(_io_resp_w_T_38, _io_resp_w_T_29)
node _io_resp_w_T_40 = or(_io_resp_w_T_39, _io_resp_w_T_34)
node _io_resp_w_T_41 = xor(io.paddr, UInt<17>(0h10000))
node _io_resp_w_T_42 = cvt(_io_resp_w_T_41)
node _io_resp_w_T_43 = and(_io_resp_w_T_42, asSInt(UInt<33>(0h9a110000)))
node _io_resp_w_T_44 = asSInt(_io_resp_w_T_43)
node _io_resp_w_T_45 = eq(_io_resp_w_T_44, asSInt(UInt<1>(0h0)))
node _io_resp_w_T_46 = mux(_io_resp_w_T_40, UInt<1>(0h1), UInt<1>(0h0))
node _io_resp_w_T_47 = mux(_io_resp_w_T_45, UInt<1>(0h0), UInt<1>(0h0))
node _io_resp_w_T_48 = or(_io_resp_w_T_46, _io_resp_w_T_47)
wire _io_resp_w_WIRE : UInt<1>
connect _io_resp_w_WIRE, _io_resp_w_T_48
node _io_resp_w_T_49 = and(legal_address, _io_resp_w_WIRE)
connect io.resp.w, _io_resp_w_T_49
node _io_resp_pp_T = xor(io.paddr, UInt<1>(0h0))
node _io_resp_pp_T_1 = cvt(_io_resp_pp_T)
node _io_resp_pp_T_2 = and(_io_resp_pp_T_1, asSInt(UInt<33>(0h98110000)))
node _io_resp_pp_T_3 = asSInt(_io_resp_pp_T_2)
node _io_resp_pp_T_4 = eq(_io_resp_pp_T_3, asSInt(UInt<1>(0h0)))
node _io_resp_pp_T_5 = xor(io.paddr, UInt<21>(0h100000))
node _io_resp_pp_T_6 = cvt(_io_resp_pp_T_5)
node _io_resp_pp_T_7 = and(_io_resp_pp_T_6, asSInt(UInt<33>(0h9a101000)))
node _io_resp_pp_T_8 = asSInt(_io_resp_pp_T_7)
node _io_resp_pp_T_9 = eq(_io_resp_pp_T_8, asSInt(UInt<1>(0h0)))
node _io_resp_pp_T_10 = xor(io.paddr, UInt<26>(0h2010000))
node _io_resp_pp_T_11 = cvt(_io_resp_pp_T_10)
node _io_resp_pp_T_12 = and(_io_resp_pp_T_11, asSInt(UInt<33>(0h9a111000)))
node _io_resp_pp_T_13 = asSInt(_io_resp_pp_T_12)
node _io_resp_pp_T_14 = eq(_io_resp_pp_T_13, asSInt(UInt<1>(0h0)))
node _io_resp_pp_T_15 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_pp_T_16 = cvt(_io_resp_pp_T_15)
node _io_resp_pp_T_17 = and(_io_resp_pp_T_16, asSInt(UInt<33>(0h98000000)))
node _io_resp_pp_T_18 = asSInt(_io_resp_pp_T_17)
node _io_resp_pp_T_19 = eq(_io_resp_pp_T_18, asSInt(UInt<1>(0h0)))
node _io_resp_pp_T_20 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_pp_T_21 = cvt(_io_resp_pp_T_20)
node _io_resp_pp_T_22 = and(_io_resp_pp_T_21, asSInt(UInt<33>(0h9a110000)))
node _io_resp_pp_T_23 = asSInt(_io_resp_pp_T_22)
node _io_resp_pp_T_24 = eq(_io_resp_pp_T_23, asSInt(UInt<1>(0h0)))
node _io_resp_pp_T_25 = xor(io.paddr, UInt<29>(0h10000000))
node _io_resp_pp_T_26 = cvt(_io_resp_pp_T_25)
node _io_resp_pp_T_27 = and(_io_resp_pp_T_26, asSInt(UInt<33>(0h9a111000)))
node _io_resp_pp_T_28 = asSInt(_io_resp_pp_T_27)
node _io_resp_pp_T_29 = eq(_io_resp_pp_T_28, asSInt(UInt<1>(0h0)))
node _io_resp_pp_T_30 = xor(io.paddr, UInt<32>(0h80000000))
node _io_resp_pp_T_31 = cvt(_io_resp_pp_T_30)
node _io_resp_pp_T_32 = and(_io_resp_pp_T_31, asSInt(UInt<33>(0h90000000)))
node _io_resp_pp_T_33 = asSInt(_io_resp_pp_T_32)
node _io_resp_pp_T_34 = eq(_io_resp_pp_T_33, asSInt(UInt<1>(0h0)))
node _io_resp_pp_T_35 = or(_io_resp_pp_T_4, _io_resp_pp_T_9)
node _io_resp_pp_T_36 = or(_io_resp_pp_T_35, _io_resp_pp_T_14)
node _io_resp_pp_T_37 = or(_io_resp_pp_T_36, _io_resp_pp_T_19)
node _io_resp_pp_T_38 = or(_io_resp_pp_T_37, _io_resp_pp_T_24)
node _io_resp_pp_T_39 = or(_io_resp_pp_T_38, _io_resp_pp_T_29)
node _io_resp_pp_T_40 = or(_io_resp_pp_T_39, _io_resp_pp_T_34)
node _io_resp_pp_T_41 = xor(io.paddr, UInt<17>(0h10000))
node _io_resp_pp_T_42 = cvt(_io_resp_pp_T_41)
node _io_resp_pp_T_43 = and(_io_resp_pp_T_42, asSInt(UInt<33>(0h9a110000)))
node _io_resp_pp_T_44 = asSInt(_io_resp_pp_T_43)
node _io_resp_pp_T_45 = eq(_io_resp_pp_T_44, asSInt(UInt<1>(0h0)))
node _io_resp_pp_T_46 = mux(_io_resp_pp_T_40, UInt<1>(0h1), UInt<1>(0h0))
node _io_resp_pp_T_47 = mux(_io_resp_pp_T_45, UInt<1>(0h0), UInt<1>(0h0))
node _io_resp_pp_T_48 = or(_io_resp_pp_T_46, _io_resp_pp_T_47)
wire _io_resp_pp_WIRE : UInt<1>
connect _io_resp_pp_WIRE, _io_resp_pp_T_48
node _io_resp_pp_T_49 = and(legal_address, _io_resp_pp_WIRE)
connect io.resp.pp, _io_resp_pp_T_49
node _io_resp_al_T = xor(io.paddr, UInt<1>(0h0))
node _io_resp_al_T_1 = cvt(_io_resp_al_T)
node _io_resp_al_T_2 = and(_io_resp_al_T_1, asSInt(UInt<33>(0h98110000)))
node _io_resp_al_T_3 = asSInt(_io_resp_al_T_2)
node _io_resp_al_T_4 = eq(_io_resp_al_T_3, asSInt(UInt<1>(0h0)))
node _io_resp_al_T_5 = xor(io.paddr, UInt<21>(0h100000))
node _io_resp_al_T_6 = cvt(_io_resp_al_T_5)
node _io_resp_al_T_7 = and(_io_resp_al_T_6, asSInt(UInt<33>(0h9a101000)))
node _io_resp_al_T_8 = asSInt(_io_resp_al_T_7)
node _io_resp_al_T_9 = eq(_io_resp_al_T_8, asSInt(UInt<1>(0h0)))
node _io_resp_al_T_10 = xor(io.paddr, UInt<26>(0h2010000))
node _io_resp_al_T_11 = cvt(_io_resp_al_T_10)
node _io_resp_al_T_12 = and(_io_resp_al_T_11, asSInt(UInt<33>(0h9a111000)))
node _io_resp_al_T_13 = asSInt(_io_resp_al_T_12)
node _io_resp_al_T_14 = eq(_io_resp_al_T_13, asSInt(UInt<1>(0h0)))
node _io_resp_al_T_15 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_al_T_16 = cvt(_io_resp_al_T_15)
node _io_resp_al_T_17 = and(_io_resp_al_T_16, asSInt(UInt<33>(0h98000000)))
node _io_resp_al_T_18 = asSInt(_io_resp_al_T_17)
node _io_resp_al_T_19 = eq(_io_resp_al_T_18, asSInt(UInt<1>(0h0)))
node _io_resp_al_T_20 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_al_T_21 = cvt(_io_resp_al_T_20)
node _io_resp_al_T_22 = and(_io_resp_al_T_21, asSInt(UInt<33>(0h9a110000)))
node _io_resp_al_T_23 = asSInt(_io_resp_al_T_22)
node _io_resp_al_T_24 = eq(_io_resp_al_T_23, asSInt(UInt<1>(0h0)))
node _io_resp_al_T_25 = xor(io.paddr, UInt<29>(0h10000000))
node _io_resp_al_T_26 = cvt(_io_resp_al_T_25)
node _io_resp_al_T_27 = and(_io_resp_al_T_26, asSInt(UInt<33>(0h9a111000)))
node _io_resp_al_T_28 = asSInt(_io_resp_al_T_27)
node _io_resp_al_T_29 = eq(_io_resp_al_T_28, asSInt(UInt<1>(0h0)))
node _io_resp_al_T_30 = xor(io.paddr, UInt<32>(0h80000000))
node _io_resp_al_T_31 = cvt(_io_resp_al_T_30)
node _io_resp_al_T_32 = and(_io_resp_al_T_31, asSInt(UInt<33>(0h90000000)))
node _io_resp_al_T_33 = asSInt(_io_resp_al_T_32)
node _io_resp_al_T_34 = eq(_io_resp_al_T_33, asSInt(UInt<1>(0h0)))
node _io_resp_al_T_35 = or(_io_resp_al_T_4, _io_resp_al_T_9)
node _io_resp_al_T_36 = or(_io_resp_al_T_35, _io_resp_al_T_14)
node _io_resp_al_T_37 = or(_io_resp_al_T_36, _io_resp_al_T_19)
node _io_resp_al_T_38 = or(_io_resp_al_T_37, _io_resp_al_T_24)
node _io_resp_al_T_39 = or(_io_resp_al_T_38, _io_resp_al_T_29)
node _io_resp_al_T_40 = or(_io_resp_al_T_39, _io_resp_al_T_34)
node _io_resp_al_T_41 = xor(io.paddr, UInt<17>(0h10000))
node _io_resp_al_T_42 = cvt(_io_resp_al_T_41)
node _io_resp_al_T_43 = and(_io_resp_al_T_42, asSInt(UInt<33>(0h9a110000)))
node _io_resp_al_T_44 = asSInt(_io_resp_al_T_43)
node _io_resp_al_T_45 = eq(_io_resp_al_T_44, asSInt(UInt<1>(0h0)))
node _io_resp_al_T_46 = mux(_io_resp_al_T_40, UInt<1>(0h1), UInt<1>(0h0))
node _io_resp_al_T_47 = mux(_io_resp_al_T_45, UInt<1>(0h0), UInt<1>(0h0))
node _io_resp_al_T_48 = or(_io_resp_al_T_46, _io_resp_al_T_47)
wire _io_resp_al_WIRE : UInt<1>
connect _io_resp_al_WIRE, _io_resp_al_T_48
node _io_resp_al_T_49 = and(legal_address, _io_resp_al_WIRE)
connect io.resp.al, _io_resp_al_T_49
node _io_resp_aa_T = xor(io.paddr, UInt<1>(0h0))
node _io_resp_aa_T_1 = cvt(_io_resp_aa_T)
node _io_resp_aa_T_2 = and(_io_resp_aa_T_1, asSInt(UInt<33>(0h98110000)))
node _io_resp_aa_T_3 = asSInt(_io_resp_aa_T_2)
node _io_resp_aa_T_4 = eq(_io_resp_aa_T_3, asSInt(UInt<1>(0h0)))
node _io_resp_aa_T_5 = xor(io.paddr, UInt<21>(0h100000))
node _io_resp_aa_T_6 = cvt(_io_resp_aa_T_5)
node _io_resp_aa_T_7 = and(_io_resp_aa_T_6, asSInt(UInt<33>(0h9a101000)))
node _io_resp_aa_T_8 = asSInt(_io_resp_aa_T_7)
node _io_resp_aa_T_9 = eq(_io_resp_aa_T_8, asSInt(UInt<1>(0h0)))
node _io_resp_aa_T_10 = xor(io.paddr, UInt<26>(0h2010000))
node _io_resp_aa_T_11 = cvt(_io_resp_aa_T_10)
node _io_resp_aa_T_12 = and(_io_resp_aa_T_11, asSInt(UInt<33>(0h9a111000)))
node _io_resp_aa_T_13 = asSInt(_io_resp_aa_T_12)
node _io_resp_aa_T_14 = eq(_io_resp_aa_T_13, asSInt(UInt<1>(0h0)))
node _io_resp_aa_T_15 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_aa_T_16 = cvt(_io_resp_aa_T_15)
node _io_resp_aa_T_17 = and(_io_resp_aa_T_16, asSInt(UInt<33>(0h98000000)))
node _io_resp_aa_T_18 = asSInt(_io_resp_aa_T_17)
node _io_resp_aa_T_19 = eq(_io_resp_aa_T_18, asSInt(UInt<1>(0h0)))
node _io_resp_aa_T_20 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_aa_T_21 = cvt(_io_resp_aa_T_20)
node _io_resp_aa_T_22 = and(_io_resp_aa_T_21, asSInt(UInt<33>(0h9a110000)))
node _io_resp_aa_T_23 = asSInt(_io_resp_aa_T_22)
node _io_resp_aa_T_24 = eq(_io_resp_aa_T_23, asSInt(UInt<1>(0h0)))
node _io_resp_aa_T_25 = xor(io.paddr, UInt<29>(0h10000000))
node _io_resp_aa_T_26 = cvt(_io_resp_aa_T_25)
node _io_resp_aa_T_27 = and(_io_resp_aa_T_26, asSInt(UInt<33>(0h9a111000)))
node _io_resp_aa_T_28 = asSInt(_io_resp_aa_T_27)
node _io_resp_aa_T_29 = eq(_io_resp_aa_T_28, asSInt(UInt<1>(0h0)))
node _io_resp_aa_T_30 = xor(io.paddr, UInt<32>(0h80000000))
node _io_resp_aa_T_31 = cvt(_io_resp_aa_T_30)
node _io_resp_aa_T_32 = and(_io_resp_aa_T_31, asSInt(UInt<33>(0h90000000)))
node _io_resp_aa_T_33 = asSInt(_io_resp_aa_T_32)
node _io_resp_aa_T_34 = eq(_io_resp_aa_T_33, asSInt(UInt<1>(0h0)))
node _io_resp_aa_T_35 = or(_io_resp_aa_T_4, _io_resp_aa_T_9)
node _io_resp_aa_T_36 = or(_io_resp_aa_T_35, _io_resp_aa_T_14)
node _io_resp_aa_T_37 = or(_io_resp_aa_T_36, _io_resp_aa_T_19)
node _io_resp_aa_T_38 = or(_io_resp_aa_T_37, _io_resp_aa_T_24)
node _io_resp_aa_T_39 = or(_io_resp_aa_T_38, _io_resp_aa_T_29)
node _io_resp_aa_T_40 = or(_io_resp_aa_T_39, _io_resp_aa_T_34)
node _io_resp_aa_T_41 = xor(io.paddr, UInt<17>(0h10000))
node _io_resp_aa_T_42 = cvt(_io_resp_aa_T_41)
node _io_resp_aa_T_43 = and(_io_resp_aa_T_42, asSInt(UInt<33>(0h9a110000)))
node _io_resp_aa_T_44 = asSInt(_io_resp_aa_T_43)
node _io_resp_aa_T_45 = eq(_io_resp_aa_T_44, asSInt(UInt<1>(0h0)))
node _io_resp_aa_T_46 = mux(_io_resp_aa_T_40, UInt<1>(0h1), UInt<1>(0h0))
node _io_resp_aa_T_47 = mux(_io_resp_aa_T_45, UInt<1>(0h0), UInt<1>(0h0))
node _io_resp_aa_T_48 = or(_io_resp_aa_T_46, _io_resp_aa_T_47)
wire _io_resp_aa_WIRE : UInt<1>
connect _io_resp_aa_WIRE, _io_resp_aa_T_48
node _io_resp_aa_T_49 = and(legal_address, _io_resp_aa_WIRE)
connect io.resp.aa, _io_resp_aa_T_49
node _io_resp_x_T = xor(io.paddr, UInt<1>(0h0))
node _io_resp_x_T_1 = cvt(_io_resp_x_T)
node _io_resp_x_T_2 = and(_io_resp_x_T_1, asSInt(UInt<33>(0h9e113000)))
node _io_resp_x_T_3 = asSInt(_io_resp_x_T_2)
node _io_resp_x_T_4 = eq(_io_resp_x_T_3, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_5 = xor(io.paddr, UInt<14>(0h3000))
node _io_resp_x_T_6 = cvt(_io_resp_x_T_5)
node _io_resp_x_T_7 = and(_io_resp_x_T_6, asSInt(UInt<33>(0h9e113000)))
node _io_resp_x_T_8 = asSInt(_io_resp_x_T_7)
node _io_resp_x_T_9 = eq(_io_resp_x_T_8, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_10 = xor(io.paddr, UInt<17>(0h10000))
node _io_resp_x_T_11 = cvt(_io_resp_x_T_10)
node _io_resp_x_T_12 = and(_io_resp_x_T_11, asSInt(UInt<33>(0h9e110000)))
node _io_resp_x_T_13 = asSInt(_io_resp_x_T_12)
node _io_resp_x_T_14 = eq(_io_resp_x_T_13, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_15 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_x_T_16 = cvt(_io_resp_x_T_15)
node _io_resp_x_T_17 = and(_io_resp_x_T_16, asSInt(UInt<33>(0h9e110000)))
node _io_resp_x_T_18 = asSInt(_io_resp_x_T_17)
node _io_resp_x_T_19 = eq(_io_resp_x_T_18, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_20 = xor(io.paddr, UInt<32>(0h80000000))
node _io_resp_x_T_21 = cvt(_io_resp_x_T_20)
node _io_resp_x_T_22 = and(_io_resp_x_T_21, asSInt(UInt<33>(0h90000000)))
node _io_resp_x_T_23 = asSInt(_io_resp_x_T_22)
node _io_resp_x_T_24 = eq(_io_resp_x_T_23, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_25 = or(_io_resp_x_T_4, _io_resp_x_T_9)
node _io_resp_x_T_26 = or(_io_resp_x_T_25, _io_resp_x_T_14)
node _io_resp_x_T_27 = or(_io_resp_x_T_26, _io_resp_x_T_19)
node _io_resp_x_T_28 = or(_io_resp_x_T_27, _io_resp_x_T_24)
node _io_resp_x_T_29 = xor(io.paddr, UInt<13>(0h1000))
node _io_resp_x_T_30 = cvt(_io_resp_x_T_29)
node _io_resp_x_T_31 = and(_io_resp_x_T_30, asSInt(UInt<33>(0h9e113000)))
node _io_resp_x_T_32 = asSInt(_io_resp_x_T_31)
node _io_resp_x_T_33 = eq(_io_resp_x_T_32, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_34 = xor(io.paddr, UInt<21>(0h100000))
node _io_resp_x_T_35 = cvt(_io_resp_x_T_34)
node _io_resp_x_T_36 = and(_io_resp_x_T_35, asSInt(UInt<33>(0h9e103000)))
node _io_resp_x_T_37 = asSInt(_io_resp_x_T_36)
node _io_resp_x_T_38 = eq(_io_resp_x_T_37, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_39 = xor(io.paddr, UInt<26>(0h2000000))
node _io_resp_x_T_40 = cvt(_io_resp_x_T_39)
node _io_resp_x_T_41 = and(_io_resp_x_T_40, asSInt(UInt<33>(0h9e110000)))
node _io_resp_x_T_42 = asSInt(_io_resp_x_T_41)
node _io_resp_x_T_43 = eq(_io_resp_x_T_42, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_44 = xor(io.paddr, UInt<26>(0h2010000))
node _io_resp_x_T_45 = cvt(_io_resp_x_T_44)
node _io_resp_x_T_46 = and(_io_resp_x_T_45, asSInt(UInt<33>(0h9e113000)))
node _io_resp_x_T_47 = asSInt(_io_resp_x_T_46)
node _io_resp_x_T_48 = eq(_io_resp_x_T_47, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_49 = xor(io.paddr, UInt<28>(0hc000000))
node _io_resp_x_T_50 = cvt(_io_resp_x_T_49)
node _io_resp_x_T_51 = and(_io_resp_x_T_50, asSInt(UInt<33>(0h9c000000)))
node _io_resp_x_T_52 = asSInt(_io_resp_x_T_51)
node _io_resp_x_T_53 = eq(_io_resp_x_T_52, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_54 = xor(io.paddr, UInt<29>(0h10000000))
node _io_resp_x_T_55 = cvt(_io_resp_x_T_54)
node _io_resp_x_T_56 = and(_io_resp_x_T_55, asSInt(UInt<33>(0h9e113000)))
node _io_resp_x_T_57 = asSInt(_io_resp_x_T_56)
node _io_resp_x_T_58 = eq(_io_resp_x_T_57, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_59 = or(_io_resp_x_T_33, _io_resp_x_T_38)
node _io_resp_x_T_60 = or(_io_resp_x_T_59, _io_resp_x_T_43)
node _io_resp_x_T_61 = or(_io_resp_x_T_60, _io_resp_x_T_48)
node _io_resp_x_T_62 = or(_io_resp_x_T_61, _io_resp_x_T_53)
node _io_resp_x_T_63 = or(_io_resp_x_T_62, _io_resp_x_T_58)
node _io_resp_x_T_64 = mux(_io_resp_x_T_28, UInt<1>(0h1), UInt<1>(0h0))
node _io_resp_x_T_65 = mux(_io_resp_x_T_63, UInt<1>(0h0), UInt<1>(0h0))
node _io_resp_x_T_66 = or(_io_resp_x_T_64, _io_resp_x_T_65)
wire _io_resp_x_WIRE : UInt<1>
connect _io_resp_x_WIRE, _io_resp_x_T_66
node _io_resp_x_T_67 = and(legal_address, _io_resp_x_WIRE)
connect io.resp.x, _io_resp_x_T_67
node _io_resp_eff_T = xor(io.paddr, UInt<1>(0h0))
node _io_resp_eff_T_1 = cvt(_io_resp_eff_T)
node _io_resp_eff_T_2 = and(_io_resp_eff_T_1, asSInt(UInt<33>(0h9e112000)))
node _io_resp_eff_T_3 = asSInt(_io_resp_eff_T_2)
node _io_resp_eff_T_4 = eq(_io_resp_eff_T_3, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_5 = xor(io.paddr, UInt<21>(0h100000))
node _io_resp_eff_T_6 = cvt(_io_resp_eff_T_5)
node _io_resp_eff_T_7 = and(_io_resp_eff_T_6, asSInt(UInt<33>(0h9e103000)))
node _io_resp_eff_T_8 = asSInt(_io_resp_eff_T_7)
node _io_resp_eff_T_9 = eq(_io_resp_eff_T_8, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_10 = xor(io.paddr, UInt<26>(0h2000000))
node _io_resp_eff_T_11 = cvt(_io_resp_eff_T_10)
node _io_resp_eff_T_12 = and(_io_resp_eff_T_11, asSInt(UInt<33>(0h9e110000)))
node _io_resp_eff_T_13 = asSInt(_io_resp_eff_T_12)
node _io_resp_eff_T_14 = eq(_io_resp_eff_T_13, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_15 = xor(io.paddr, UInt<26>(0h2010000))
node _io_resp_eff_T_16 = cvt(_io_resp_eff_T_15)
node _io_resp_eff_T_17 = and(_io_resp_eff_T_16, asSInt(UInt<33>(0h9e113000)))
node _io_resp_eff_T_18 = asSInt(_io_resp_eff_T_17)
node _io_resp_eff_T_19 = eq(_io_resp_eff_T_18, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_20 = xor(io.paddr, UInt<28>(0hc000000))
node _io_resp_eff_T_21 = cvt(_io_resp_eff_T_20)
node _io_resp_eff_T_22 = and(_io_resp_eff_T_21, asSInt(UInt<33>(0h9c000000)))
node _io_resp_eff_T_23 = asSInt(_io_resp_eff_T_22)
node _io_resp_eff_T_24 = eq(_io_resp_eff_T_23, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_25 = xor(io.paddr, UInt<29>(0h10000000))
node _io_resp_eff_T_26 = cvt(_io_resp_eff_T_25)
node _io_resp_eff_T_27 = and(_io_resp_eff_T_26, asSInt(UInt<33>(0h9e113000)))
node _io_resp_eff_T_28 = asSInt(_io_resp_eff_T_27)
node _io_resp_eff_T_29 = eq(_io_resp_eff_T_28, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_30 = or(_io_resp_eff_T_4, _io_resp_eff_T_9)
node _io_resp_eff_T_31 = or(_io_resp_eff_T_30, _io_resp_eff_T_14)
node _io_resp_eff_T_32 = or(_io_resp_eff_T_31, _io_resp_eff_T_19)
node _io_resp_eff_T_33 = or(_io_resp_eff_T_32, _io_resp_eff_T_24)
node _io_resp_eff_T_34 = or(_io_resp_eff_T_33, _io_resp_eff_T_29)
node _io_resp_eff_T_35 = xor(io.paddr, UInt<14>(0h3000))
node _io_resp_eff_T_36 = cvt(_io_resp_eff_T_35)
node _io_resp_eff_T_37 = and(_io_resp_eff_T_36, asSInt(UInt<33>(0h9e113000)))
node _io_resp_eff_T_38 = asSInt(_io_resp_eff_T_37)
node _io_resp_eff_T_39 = eq(_io_resp_eff_T_38, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_40 = xor(io.paddr, UInt<17>(0h10000))
node _io_resp_eff_T_41 = cvt(_io_resp_eff_T_40)
node _io_resp_eff_T_42 = and(_io_resp_eff_T_41, asSInt(UInt<33>(0h9e110000)))
node _io_resp_eff_T_43 = asSInt(_io_resp_eff_T_42)
node _io_resp_eff_T_44 = eq(_io_resp_eff_T_43, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_45 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_eff_T_46 = cvt(_io_resp_eff_T_45)
node _io_resp_eff_T_47 = and(_io_resp_eff_T_46, asSInt(UInt<33>(0h9e110000)))
node _io_resp_eff_T_48 = asSInt(_io_resp_eff_T_47)
node _io_resp_eff_T_49 = eq(_io_resp_eff_T_48, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_50 = xor(io.paddr, UInt<32>(0h80000000))
node _io_resp_eff_T_51 = cvt(_io_resp_eff_T_50)
node _io_resp_eff_T_52 = and(_io_resp_eff_T_51, asSInt(UInt<33>(0h90000000)))
node _io_resp_eff_T_53 = asSInt(_io_resp_eff_T_52)
node _io_resp_eff_T_54 = eq(_io_resp_eff_T_53, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_55 = or(_io_resp_eff_T_39, _io_resp_eff_T_44)
node _io_resp_eff_T_56 = or(_io_resp_eff_T_55, _io_resp_eff_T_49)
node _io_resp_eff_T_57 = or(_io_resp_eff_T_56, _io_resp_eff_T_54)
node _io_resp_eff_T_58 = mux(_io_resp_eff_T_34, UInt<1>(0h1), UInt<1>(0h0))
node _io_resp_eff_T_59 = mux(_io_resp_eff_T_57, UInt<1>(0h0), UInt<1>(0h0))
node _io_resp_eff_T_60 = or(_io_resp_eff_T_58, _io_resp_eff_T_59)
wire _io_resp_eff_WIRE : UInt<1>
connect _io_resp_eff_WIRE, _io_resp_eff_T_60
node _io_resp_eff_T_61 = and(legal_address, _io_resp_eff_WIRE)
connect io.resp.eff, _io_resp_eff_T_61 | module PMAChecker_2( // @[PMA.scala:18:7]
input clock, // @[PMA.scala:18:7]
input reset, // @[PMA.scala:18:7]
input [39:0] io_paddr, // @[PMA.scala:19:14]
output io_resp_cacheable, // @[PMA.scala:19:14]
output io_resp_r, // @[PMA.scala:19:14]
output io_resp_w, // @[PMA.scala:19:14]
output io_resp_pp, // @[PMA.scala:19:14]
output io_resp_al, // @[PMA.scala:19:14]
output io_resp_aa, // @[PMA.scala:19:14]
output io_resp_x, // @[PMA.scala:19:14]
output io_resp_eff // @[PMA.scala:19:14]
);
wire [39:0] io_paddr_0 = io_paddr; // @[PMA.scala:18:7]
wire [40:0] _io_resp_r_T_2 = 41'h0; // @[Parameters.scala:137:46]
wire [40:0] _io_resp_r_T_3 = 41'h0; // @[Parameters.scala:137:46]
wire _io_resp_r_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire _io_resp_cacheable_T_28 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_w_T_47 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_pp_T_47 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_al_T_47 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_aa_T_47 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_x_T_65 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_eff_T_59 = 1'h0; // @[Mux.scala:30:73]
wire [39:0] _legal_address_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_cacheable_T = io_paddr_0; // @[PMA.scala:18:7]
wire _io_resp_cacheable_T_31; // @[PMA.scala:39:19]
wire [39:0] _io_resp_r_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_w_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_pp_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_al_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_aa_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_x_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_eff_T = io_paddr_0; // @[PMA.scala:18:7]
wire _io_resp_r_T_5; // @[PMA.scala:39:19]
wire _io_resp_w_T_49; // @[PMA.scala:39:19]
wire _io_resp_pp_T_49; // @[PMA.scala:39:19]
wire _io_resp_al_T_49; // @[PMA.scala:39:19]
wire _io_resp_aa_T_49; // @[PMA.scala:39:19]
wire _io_resp_x_T_67; // @[PMA.scala:39:19]
wire _io_resp_eff_T_61; // @[PMA.scala:39:19]
wire io_resp_cacheable_0; // @[PMA.scala:18:7]
wire io_resp_r_0; // @[PMA.scala:18:7]
wire io_resp_w_0; // @[PMA.scala:18:7]
wire io_resp_pp_0; // @[PMA.scala:18:7]
wire io_resp_al_0; // @[PMA.scala:18:7]
wire io_resp_aa_0; // @[PMA.scala:18:7]
wire io_resp_x_0; // @[PMA.scala:18:7]
wire io_resp_eff_0; // @[PMA.scala:18:7]
wire [40:0] _legal_address_T_1 = {1'h0, _legal_address_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_2 = _legal_address_T_1 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_3 = _legal_address_T_2; // @[Parameters.scala:137:46]
wire _legal_address_T_4 = _legal_address_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_0 = _legal_address_T_4; // @[Parameters.scala:612:40]
wire [39:0] _GEN = {io_paddr_0[39:13], io_paddr_0[12:0] ^ 13'h1000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_5; // @[Parameters.scala:137:31]
assign _legal_address_T_5 = _GEN; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_29; // @[Parameters.scala:137:31]
assign _io_resp_x_T_29 = _GEN; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_6 = {1'h0, _legal_address_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_7 = _legal_address_T_6 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_8 = _legal_address_T_7; // @[Parameters.scala:137:46]
wire _legal_address_T_9 = _legal_address_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_1 = _legal_address_T_9; // @[Parameters.scala:612:40]
wire [39:0] _GEN_0 = {io_paddr_0[39:14], io_paddr_0[13:0] ^ 14'h3000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_10; // @[Parameters.scala:137:31]
assign _legal_address_T_10 = _GEN_0; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_5; // @[Parameters.scala:137:31]
assign _io_resp_x_T_5 = _GEN_0; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_35; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_35 = _GEN_0; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_11 = {1'h0, _legal_address_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_12 = _legal_address_T_11 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_13 = _legal_address_T_12; // @[Parameters.scala:137:46]
wire _legal_address_T_14 = _legal_address_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_2 = _legal_address_T_14; // @[Parameters.scala:612:40]
wire [39:0] _GEN_1 = {io_paddr_0[39:17], io_paddr_0[16:0] ^ 17'h10000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_15; // @[Parameters.scala:137:31]
assign _legal_address_T_15 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_cacheable_T_5; // @[Parameters.scala:137:31]
assign _io_resp_cacheable_T_5 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_41; // @[Parameters.scala:137:31]
assign _io_resp_w_T_41 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_41; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_41 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_41; // @[Parameters.scala:137:31]
assign _io_resp_al_T_41 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_41; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_41 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_10; // @[Parameters.scala:137:31]
assign _io_resp_x_T_10 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_40; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_40 = _GEN_1; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_16 = {1'h0, _legal_address_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_17 = _legal_address_T_16 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_18 = _legal_address_T_17; // @[Parameters.scala:137:46]
wire _legal_address_T_19 = _legal_address_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_3 = _legal_address_T_19; // @[Parameters.scala:612:40]
wire [39:0] _GEN_2 = {io_paddr_0[39:21], io_paddr_0[20:0] ^ 21'h100000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_20; // @[Parameters.scala:137:31]
assign _legal_address_T_20 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_5; // @[Parameters.scala:137:31]
assign _io_resp_w_T_5 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_5; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_5 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_5; // @[Parameters.scala:137:31]
assign _io_resp_al_T_5 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_5; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_5 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_34; // @[Parameters.scala:137:31]
assign _io_resp_x_T_34 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_5; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_5 = _GEN_2; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_21 = {1'h0, _legal_address_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_22 = _legal_address_T_21 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_23 = _legal_address_T_22; // @[Parameters.scala:137:46]
wire _legal_address_T_24 = _legal_address_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_4 = _legal_address_T_24; // @[Parameters.scala:612:40]
wire [39:0] _legal_address_T_25 = {io_paddr_0[39:21], io_paddr_0[20:0] ^ 21'h110000}; // @[PMA.scala:18:7]
wire [40:0] _legal_address_T_26 = {1'h0, _legal_address_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_27 = _legal_address_T_26 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_28 = _legal_address_T_27; // @[Parameters.scala:137:46]
wire _legal_address_T_29 = _legal_address_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_5 = _legal_address_T_29; // @[Parameters.scala:612:40]
wire [39:0] _GEN_3 = {io_paddr_0[39:26], io_paddr_0[25:0] ^ 26'h2000000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_30; // @[Parameters.scala:137:31]
assign _legal_address_T_30 = _GEN_3; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_39; // @[Parameters.scala:137:31]
assign _io_resp_x_T_39 = _GEN_3; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_10; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_10 = _GEN_3; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_31 = {1'h0, _legal_address_T_30}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_32 = _legal_address_T_31 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_33 = _legal_address_T_32; // @[Parameters.scala:137:46]
wire _legal_address_T_34 = _legal_address_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_6 = _legal_address_T_34; // @[Parameters.scala:612:40]
wire [39:0] _GEN_4 = {io_paddr_0[39:26], io_paddr_0[25:0] ^ 26'h2010000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_35; // @[Parameters.scala:137:31]
assign _legal_address_T_35 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_10; // @[Parameters.scala:137:31]
assign _io_resp_w_T_10 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_10; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_10 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_10; // @[Parameters.scala:137:31]
assign _io_resp_al_T_10 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_10; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_10 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_44; // @[Parameters.scala:137:31]
assign _io_resp_x_T_44 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_15; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_15 = _GEN_4; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_36 = {1'h0, _legal_address_T_35}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_37 = _legal_address_T_36 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_38 = _legal_address_T_37; // @[Parameters.scala:137:46]
wire _legal_address_T_39 = _legal_address_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_7 = _legal_address_T_39; // @[Parameters.scala:612:40]
wire [39:0] _GEN_5 = {io_paddr_0[39:28], io_paddr_0[27:0] ^ 28'h8000000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_40; // @[Parameters.scala:137:31]
assign _legal_address_T_40 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_cacheable_T_17; // @[Parameters.scala:137:31]
assign _io_resp_cacheable_T_17 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_15; // @[Parameters.scala:137:31]
assign _io_resp_w_T_15 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_20; // @[Parameters.scala:137:31]
assign _io_resp_w_T_20 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_15; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_15 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_20; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_20 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_15; // @[Parameters.scala:137:31]
assign _io_resp_al_T_15 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_20; // @[Parameters.scala:137:31]
assign _io_resp_al_T_20 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_15; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_15 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_20; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_20 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_15; // @[Parameters.scala:137:31]
assign _io_resp_x_T_15 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_45; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_45 = _GEN_5; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_41 = {1'h0, _legal_address_T_40}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_42 = _legal_address_T_41 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_43 = _legal_address_T_42; // @[Parameters.scala:137:46]
wire _legal_address_T_44 = _legal_address_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_8 = _legal_address_T_44; // @[Parameters.scala:612:40]
wire [39:0] _GEN_6 = {io_paddr_0[39:28], io_paddr_0[27:0] ^ 28'hC000000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_45; // @[Parameters.scala:137:31]
assign _legal_address_T_45 = _GEN_6; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_cacheable_T_10; // @[Parameters.scala:137:31]
assign _io_resp_cacheable_T_10 = _GEN_6; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_49; // @[Parameters.scala:137:31]
assign _io_resp_x_T_49 = _GEN_6; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_20; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_20 = _GEN_6; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_46 = {1'h0, _legal_address_T_45}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_47 = _legal_address_T_46 & 41'h1FFFC000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_48 = _legal_address_T_47; // @[Parameters.scala:137:46]
wire _legal_address_T_49 = _legal_address_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_9 = _legal_address_T_49; // @[Parameters.scala:612:40]
wire [39:0] _legal_address_T_50 = {io_paddr_0[39:29], io_paddr_0[28:0] ^ 29'h10020000}; // @[PMA.scala:18:7]
wire [40:0] _legal_address_T_51 = {1'h0, _legal_address_T_50}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_52 = _legal_address_T_51 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_53 = _legal_address_T_52; // @[Parameters.scala:137:46]
wire _legal_address_T_54 = _legal_address_T_53 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_10 = _legal_address_T_54; // @[Parameters.scala:612:40]
wire [39:0] _GEN_7 = {io_paddr_0[39:32], io_paddr_0[31:0] ^ 32'h80000000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_55; // @[Parameters.scala:137:31]
assign _legal_address_T_55 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_cacheable_T_22; // @[Parameters.scala:137:31]
assign _io_resp_cacheable_T_22 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_30; // @[Parameters.scala:137:31]
assign _io_resp_w_T_30 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_30; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_30 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_30; // @[Parameters.scala:137:31]
assign _io_resp_al_T_30 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_30; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_30 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_20; // @[Parameters.scala:137:31]
assign _io_resp_x_T_20 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_50; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_50 = _GEN_7; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_56 = {1'h0, _legal_address_T_55}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_57 = _legal_address_T_56 & 41'h1FFF0000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_58 = _legal_address_T_57; // @[Parameters.scala:137:46]
wire _legal_address_T_59 = _legal_address_T_58 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_11 = _legal_address_T_59; // @[Parameters.scala:612:40]
wire _legal_address_T_60 = _legal_address_WIRE_0 | _legal_address_WIRE_1; // @[Parameters.scala:612:40]
wire _legal_address_T_61 = _legal_address_T_60 | _legal_address_WIRE_2; // @[Parameters.scala:612:40]
wire _legal_address_T_62 = _legal_address_T_61 | _legal_address_WIRE_3; // @[Parameters.scala:612:40]
wire _legal_address_T_63 = _legal_address_T_62 | _legal_address_WIRE_4; // @[Parameters.scala:612:40]
wire _legal_address_T_64 = _legal_address_T_63 | _legal_address_WIRE_5; // @[Parameters.scala:612:40]
wire _legal_address_T_65 = _legal_address_T_64 | _legal_address_WIRE_6; // @[Parameters.scala:612:40]
wire _legal_address_T_66 = _legal_address_T_65 | _legal_address_WIRE_7; // @[Parameters.scala:612:40]
wire _legal_address_T_67 = _legal_address_T_66 | _legal_address_WIRE_8; // @[Parameters.scala:612:40]
wire _legal_address_T_68 = _legal_address_T_67 | _legal_address_WIRE_9; // @[Parameters.scala:612:40]
wire _legal_address_T_69 = _legal_address_T_68 | _legal_address_WIRE_10; // @[Parameters.scala:612:40]
wire legal_address = _legal_address_T_69 | _legal_address_WIRE_11; // @[Parameters.scala:612:40]
assign _io_resp_r_T_5 = legal_address; // @[PMA.scala:36:58, :39:19]
wire [40:0] _io_resp_cacheable_T_1 = {1'h0, _io_resp_cacheable_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_cacheable_T_2 = _io_resp_cacheable_T_1 & 41'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_cacheable_T_3 = _io_resp_cacheable_T_2; // @[Parameters.scala:137:46]
wire _io_resp_cacheable_T_4 = _io_resp_cacheable_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_cacheable_T_6 = {1'h0, _io_resp_cacheable_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_cacheable_T_7 = _io_resp_cacheable_T_6 & 41'h8C011000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_cacheable_T_8 = _io_resp_cacheable_T_7; // @[Parameters.scala:137:46]
wire _io_resp_cacheable_T_9 = _io_resp_cacheable_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_cacheable_T_11 = {1'h0, _io_resp_cacheable_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_cacheable_T_12 = _io_resp_cacheable_T_11 & 41'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_cacheable_T_13 = _io_resp_cacheable_T_12; // @[Parameters.scala:137:46]
wire _io_resp_cacheable_T_14 = _io_resp_cacheable_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_cacheable_T_15 = _io_resp_cacheable_T_4 | _io_resp_cacheable_T_9; // @[Parameters.scala:629:89]
wire _io_resp_cacheable_T_16 = _io_resp_cacheable_T_15 | _io_resp_cacheable_T_14; // @[Parameters.scala:629:89]
wire [40:0] _io_resp_cacheable_T_18 = {1'h0, _io_resp_cacheable_T_17}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_cacheable_T_19 = _io_resp_cacheable_T_18 & 41'h8C010000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_cacheable_T_20 = _io_resp_cacheable_T_19; // @[Parameters.scala:137:46]
wire _io_resp_cacheable_T_21 = _io_resp_cacheable_T_20 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_cacheable_T_23 = {1'h0, _io_resp_cacheable_T_22}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_cacheable_T_24 = _io_resp_cacheable_T_23 & 41'h80000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_cacheable_T_25 = _io_resp_cacheable_T_24; // @[Parameters.scala:137:46]
wire _io_resp_cacheable_T_26 = _io_resp_cacheable_T_25 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_cacheable_T_27 = _io_resp_cacheable_T_21 | _io_resp_cacheable_T_26; // @[Parameters.scala:629:89]
wire _io_resp_cacheable_T_29 = _io_resp_cacheable_T_27; // @[Mux.scala:30:73]
wire _io_resp_cacheable_T_30 = _io_resp_cacheable_T_29; // @[Mux.scala:30:73]
wire _io_resp_cacheable_WIRE = _io_resp_cacheable_T_30; // @[Mux.scala:30:73]
assign _io_resp_cacheable_T_31 = legal_address & _io_resp_cacheable_WIRE; // @[Mux.scala:30:73]
assign io_resp_cacheable_0 = _io_resp_cacheable_T_31; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_r_T_1 = {1'h0, _io_resp_r_T}; // @[Parameters.scala:137:{31,41}]
assign io_resp_r_0 = _io_resp_r_T_5; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_w_T_1 = {1'h0, _io_resp_w_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_2 = _io_resp_w_T_1 & 41'h98110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_3 = _io_resp_w_T_2; // @[Parameters.scala:137:46]
wire _io_resp_w_T_4 = _io_resp_w_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_w_T_6 = {1'h0, _io_resp_w_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_7 = _io_resp_w_T_6 & 41'h9A101000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_8 = _io_resp_w_T_7; // @[Parameters.scala:137:46]
wire _io_resp_w_T_9 = _io_resp_w_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_w_T_11 = {1'h0, _io_resp_w_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_12 = _io_resp_w_T_11 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_13 = _io_resp_w_T_12; // @[Parameters.scala:137:46]
wire _io_resp_w_T_14 = _io_resp_w_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_w_T_16 = {1'h0, _io_resp_w_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_17 = _io_resp_w_T_16 & 41'h98000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_18 = _io_resp_w_T_17; // @[Parameters.scala:137:46]
wire _io_resp_w_T_19 = _io_resp_w_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_w_T_21 = {1'h0, _io_resp_w_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_22 = _io_resp_w_T_21 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_23 = _io_resp_w_T_22; // @[Parameters.scala:137:46]
wire _io_resp_w_T_24 = _io_resp_w_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_8 = {io_paddr_0[39:29], io_paddr_0[28:0] ^ 29'h10000000}; // @[PMA.scala:18:7]
wire [39:0] _io_resp_w_T_25; // @[Parameters.scala:137:31]
assign _io_resp_w_T_25 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_25; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_25 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_25; // @[Parameters.scala:137:31]
assign _io_resp_al_T_25 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_25; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_25 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_54; // @[Parameters.scala:137:31]
assign _io_resp_x_T_54 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_25; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_25 = _GEN_8; // @[Parameters.scala:137:31]
wire [40:0] _io_resp_w_T_26 = {1'h0, _io_resp_w_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_27 = _io_resp_w_T_26 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_28 = _io_resp_w_T_27; // @[Parameters.scala:137:46]
wire _io_resp_w_T_29 = _io_resp_w_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_w_T_31 = {1'h0, _io_resp_w_T_30}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_32 = _io_resp_w_T_31 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_33 = _io_resp_w_T_32; // @[Parameters.scala:137:46]
wire _io_resp_w_T_34 = _io_resp_w_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_w_T_35 = _io_resp_w_T_4 | _io_resp_w_T_9; // @[Parameters.scala:629:89]
wire _io_resp_w_T_36 = _io_resp_w_T_35 | _io_resp_w_T_14; // @[Parameters.scala:629:89]
wire _io_resp_w_T_37 = _io_resp_w_T_36 | _io_resp_w_T_19; // @[Parameters.scala:629:89]
wire _io_resp_w_T_38 = _io_resp_w_T_37 | _io_resp_w_T_24; // @[Parameters.scala:629:89]
wire _io_resp_w_T_39 = _io_resp_w_T_38 | _io_resp_w_T_29; // @[Parameters.scala:629:89]
wire _io_resp_w_T_40 = _io_resp_w_T_39 | _io_resp_w_T_34; // @[Parameters.scala:629:89]
wire _io_resp_w_T_46 = _io_resp_w_T_40; // @[Mux.scala:30:73]
wire [40:0] _io_resp_w_T_42 = {1'h0, _io_resp_w_T_41}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_43 = _io_resp_w_T_42 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_44 = _io_resp_w_T_43; // @[Parameters.scala:137:46]
wire _io_resp_w_T_45 = _io_resp_w_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_w_T_48 = _io_resp_w_T_46; // @[Mux.scala:30:73]
wire _io_resp_w_WIRE = _io_resp_w_T_48; // @[Mux.scala:30:73]
assign _io_resp_w_T_49 = legal_address & _io_resp_w_WIRE; // @[Mux.scala:30:73]
assign io_resp_w_0 = _io_resp_w_T_49; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_pp_T_1 = {1'h0, _io_resp_pp_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_2 = _io_resp_pp_T_1 & 41'h98110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_3 = _io_resp_pp_T_2; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_4 = _io_resp_pp_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_6 = {1'h0, _io_resp_pp_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_7 = _io_resp_pp_T_6 & 41'h9A101000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_8 = _io_resp_pp_T_7; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_9 = _io_resp_pp_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_11 = {1'h0, _io_resp_pp_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_12 = _io_resp_pp_T_11 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_13 = _io_resp_pp_T_12; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_14 = _io_resp_pp_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_16 = {1'h0, _io_resp_pp_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_17 = _io_resp_pp_T_16 & 41'h98000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_18 = _io_resp_pp_T_17; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_19 = _io_resp_pp_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_21 = {1'h0, _io_resp_pp_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_22 = _io_resp_pp_T_21 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_23 = _io_resp_pp_T_22; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_24 = _io_resp_pp_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_26 = {1'h0, _io_resp_pp_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_27 = _io_resp_pp_T_26 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_28 = _io_resp_pp_T_27; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_29 = _io_resp_pp_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_31 = {1'h0, _io_resp_pp_T_30}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_32 = _io_resp_pp_T_31 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_33 = _io_resp_pp_T_32; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_34 = _io_resp_pp_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_pp_T_35 = _io_resp_pp_T_4 | _io_resp_pp_T_9; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_36 = _io_resp_pp_T_35 | _io_resp_pp_T_14; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_37 = _io_resp_pp_T_36 | _io_resp_pp_T_19; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_38 = _io_resp_pp_T_37 | _io_resp_pp_T_24; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_39 = _io_resp_pp_T_38 | _io_resp_pp_T_29; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_40 = _io_resp_pp_T_39 | _io_resp_pp_T_34; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_46 = _io_resp_pp_T_40; // @[Mux.scala:30:73]
wire [40:0] _io_resp_pp_T_42 = {1'h0, _io_resp_pp_T_41}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_43 = _io_resp_pp_T_42 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_44 = _io_resp_pp_T_43; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_45 = _io_resp_pp_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_pp_T_48 = _io_resp_pp_T_46; // @[Mux.scala:30:73]
wire _io_resp_pp_WIRE = _io_resp_pp_T_48; // @[Mux.scala:30:73]
assign _io_resp_pp_T_49 = legal_address & _io_resp_pp_WIRE; // @[Mux.scala:30:73]
assign io_resp_pp_0 = _io_resp_pp_T_49; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_al_T_1 = {1'h0, _io_resp_al_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_2 = _io_resp_al_T_1 & 41'h98110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_3 = _io_resp_al_T_2; // @[Parameters.scala:137:46]
wire _io_resp_al_T_4 = _io_resp_al_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_6 = {1'h0, _io_resp_al_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_7 = _io_resp_al_T_6 & 41'h9A101000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_8 = _io_resp_al_T_7; // @[Parameters.scala:137:46]
wire _io_resp_al_T_9 = _io_resp_al_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_11 = {1'h0, _io_resp_al_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_12 = _io_resp_al_T_11 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_13 = _io_resp_al_T_12; // @[Parameters.scala:137:46]
wire _io_resp_al_T_14 = _io_resp_al_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_16 = {1'h0, _io_resp_al_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_17 = _io_resp_al_T_16 & 41'h98000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_18 = _io_resp_al_T_17; // @[Parameters.scala:137:46]
wire _io_resp_al_T_19 = _io_resp_al_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_21 = {1'h0, _io_resp_al_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_22 = _io_resp_al_T_21 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_23 = _io_resp_al_T_22; // @[Parameters.scala:137:46]
wire _io_resp_al_T_24 = _io_resp_al_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_26 = {1'h0, _io_resp_al_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_27 = _io_resp_al_T_26 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_28 = _io_resp_al_T_27; // @[Parameters.scala:137:46]
wire _io_resp_al_T_29 = _io_resp_al_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_31 = {1'h0, _io_resp_al_T_30}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_32 = _io_resp_al_T_31 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_33 = _io_resp_al_T_32; // @[Parameters.scala:137:46]
wire _io_resp_al_T_34 = _io_resp_al_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_al_T_35 = _io_resp_al_T_4 | _io_resp_al_T_9; // @[Parameters.scala:629:89]
wire _io_resp_al_T_36 = _io_resp_al_T_35 | _io_resp_al_T_14; // @[Parameters.scala:629:89]
wire _io_resp_al_T_37 = _io_resp_al_T_36 | _io_resp_al_T_19; // @[Parameters.scala:629:89]
wire _io_resp_al_T_38 = _io_resp_al_T_37 | _io_resp_al_T_24; // @[Parameters.scala:629:89]
wire _io_resp_al_T_39 = _io_resp_al_T_38 | _io_resp_al_T_29; // @[Parameters.scala:629:89]
wire _io_resp_al_T_40 = _io_resp_al_T_39 | _io_resp_al_T_34; // @[Parameters.scala:629:89]
wire _io_resp_al_T_46 = _io_resp_al_T_40; // @[Mux.scala:30:73]
wire [40:0] _io_resp_al_T_42 = {1'h0, _io_resp_al_T_41}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_43 = _io_resp_al_T_42 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_44 = _io_resp_al_T_43; // @[Parameters.scala:137:46]
wire _io_resp_al_T_45 = _io_resp_al_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_al_T_48 = _io_resp_al_T_46; // @[Mux.scala:30:73]
wire _io_resp_al_WIRE = _io_resp_al_T_48; // @[Mux.scala:30:73]
assign _io_resp_al_T_49 = legal_address & _io_resp_al_WIRE; // @[Mux.scala:30:73]
assign io_resp_al_0 = _io_resp_al_T_49; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_aa_T_1 = {1'h0, _io_resp_aa_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_2 = _io_resp_aa_T_1 & 41'h98110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_3 = _io_resp_aa_T_2; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_4 = _io_resp_aa_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_6 = {1'h0, _io_resp_aa_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_7 = _io_resp_aa_T_6 & 41'h9A101000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_8 = _io_resp_aa_T_7; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_9 = _io_resp_aa_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_11 = {1'h0, _io_resp_aa_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_12 = _io_resp_aa_T_11 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_13 = _io_resp_aa_T_12; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_14 = _io_resp_aa_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_16 = {1'h0, _io_resp_aa_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_17 = _io_resp_aa_T_16 & 41'h98000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_18 = _io_resp_aa_T_17; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_19 = _io_resp_aa_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_21 = {1'h0, _io_resp_aa_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_22 = _io_resp_aa_T_21 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_23 = _io_resp_aa_T_22; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_24 = _io_resp_aa_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_26 = {1'h0, _io_resp_aa_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_27 = _io_resp_aa_T_26 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_28 = _io_resp_aa_T_27; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_29 = _io_resp_aa_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_31 = {1'h0, _io_resp_aa_T_30}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_32 = _io_resp_aa_T_31 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_33 = _io_resp_aa_T_32; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_34 = _io_resp_aa_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_aa_T_35 = _io_resp_aa_T_4 | _io_resp_aa_T_9; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_36 = _io_resp_aa_T_35 | _io_resp_aa_T_14; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_37 = _io_resp_aa_T_36 | _io_resp_aa_T_19; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_38 = _io_resp_aa_T_37 | _io_resp_aa_T_24; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_39 = _io_resp_aa_T_38 | _io_resp_aa_T_29; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_40 = _io_resp_aa_T_39 | _io_resp_aa_T_34; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_46 = _io_resp_aa_T_40; // @[Mux.scala:30:73]
wire [40:0] _io_resp_aa_T_42 = {1'h0, _io_resp_aa_T_41}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_43 = _io_resp_aa_T_42 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_44 = _io_resp_aa_T_43; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_45 = _io_resp_aa_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_aa_T_48 = _io_resp_aa_T_46; // @[Mux.scala:30:73]
wire _io_resp_aa_WIRE = _io_resp_aa_T_48; // @[Mux.scala:30:73]
assign _io_resp_aa_T_49 = legal_address & _io_resp_aa_WIRE; // @[Mux.scala:30:73]
assign io_resp_aa_0 = _io_resp_aa_T_49; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_x_T_1 = {1'h0, _io_resp_x_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_2 = _io_resp_x_T_1 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_3 = _io_resp_x_T_2; // @[Parameters.scala:137:46]
wire _io_resp_x_T_4 = _io_resp_x_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_6 = {1'h0, _io_resp_x_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_7 = _io_resp_x_T_6 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_8 = _io_resp_x_T_7; // @[Parameters.scala:137:46]
wire _io_resp_x_T_9 = _io_resp_x_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_11 = {1'h0, _io_resp_x_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_12 = _io_resp_x_T_11 & 41'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_13 = _io_resp_x_T_12; // @[Parameters.scala:137:46]
wire _io_resp_x_T_14 = _io_resp_x_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_16 = {1'h0, _io_resp_x_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_17 = _io_resp_x_T_16 & 41'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_18 = _io_resp_x_T_17; // @[Parameters.scala:137:46]
wire _io_resp_x_T_19 = _io_resp_x_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_21 = {1'h0, _io_resp_x_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_22 = _io_resp_x_T_21 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_23 = _io_resp_x_T_22; // @[Parameters.scala:137:46]
wire _io_resp_x_T_24 = _io_resp_x_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_x_T_25 = _io_resp_x_T_4 | _io_resp_x_T_9; // @[Parameters.scala:629:89]
wire _io_resp_x_T_26 = _io_resp_x_T_25 | _io_resp_x_T_14; // @[Parameters.scala:629:89]
wire _io_resp_x_T_27 = _io_resp_x_T_26 | _io_resp_x_T_19; // @[Parameters.scala:629:89]
wire _io_resp_x_T_28 = _io_resp_x_T_27 | _io_resp_x_T_24; // @[Parameters.scala:629:89]
wire _io_resp_x_T_64 = _io_resp_x_T_28; // @[Mux.scala:30:73]
wire [40:0] _io_resp_x_T_30 = {1'h0, _io_resp_x_T_29}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_31 = _io_resp_x_T_30 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_32 = _io_resp_x_T_31; // @[Parameters.scala:137:46]
wire _io_resp_x_T_33 = _io_resp_x_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_35 = {1'h0, _io_resp_x_T_34}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_36 = _io_resp_x_T_35 & 41'h9E103000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_37 = _io_resp_x_T_36; // @[Parameters.scala:137:46]
wire _io_resp_x_T_38 = _io_resp_x_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_40 = {1'h0, _io_resp_x_T_39}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_41 = _io_resp_x_T_40 & 41'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_42 = _io_resp_x_T_41; // @[Parameters.scala:137:46]
wire _io_resp_x_T_43 = _io_resp_x_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_45 = {1'h0, _io_resp_x_T_44}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_46 = _io_resp_x_T_45 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_47 = _io_resp_x_T_46; // @[Parameters.scala:137:46]
wire _io_resp_x_T_48 = _io_resp_x_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_50 = {1'h0, _io_resp_x_T_49}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_51 = _io_resp_x_T_50 & 41'h9C000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_52 = _io_resp_x_T_51; // @[Parameters.scala:137:46]
wire _io_resp_x_T_53 = _io_resp_x_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_55 = {1'h0, _io_resp_x_T_54}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_56 = _io_resp_x_T_55 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_57 = _io_resp_x_T_56; // @[Parameters.scala:137:46]
wire _io_resp_x_T_58 = _io_resp_x_T_57 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_x_T_59 = _io_resp_x_T_33 | _io_resp_x_T_38; // @[Parameters.scala:629:89]
wire _io_resp_x_T_60 = _io_resp_x_T_59 | _io_resp_x_T_43; // @[Parameters.scala:629:89]
wire _io_resp_x_T_61 = _io_resp_x_T_60 | _io_resp_x_T_48; // @[Parameters.scala:629:89]
wire _io_resp_x_T_62 = _io_resp_x_T_61 | _io_resp_x_T_53; // @[Parameters.scala:629:89]
wire _io_resp_x_T_63 = _io_resp_x_T_62 | _io_resp_x_T_58; // @[Parameters.scala:629:89]
wire _io_resp_x_T_66 = _io_resp_x_T_64; // @[Mux.scala:30:73]
wire _io_resp_x_WIRE = _io_resp_x_T_66; // @[Mux.scala:30:73]
assign _io_resp_x_T_67 = legal_address & _io_resp_x_WIRE; // @[Mux.scala:30:73]
assign io_resp_x_0 = _io_resp_x_T_67; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_eff_T_1 = {1'h0, _io_resp_eff_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_2 = _io_resp_eff_T_1 & 41'h9E112000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_3 = _io_resp_eff_T_2; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_4 = _io_resp_eff_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_6 = {1'h0, _io_resp_eff_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_7 = _io_resp_eff_T_6 & 41'h9E103000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_8 = _io_resp_eff_T_7; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_9 = _io_resp_eff_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_11 = {1'h0, _io_resp_eff_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_12 = _io_resp_eff_T_11 & 41'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_13 = _io_resp_eff_T_12; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_14 = _io_resp_eff_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_16 = {1'h0, _io_resp_eff_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_17 = _io_resp_eff_T_16 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_18 = _io_resp_eff_T_17; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_19 = _io_resp_eff_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_21 = {1'h0, _io_resp_eff_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_22 = _io_resp_eff_T_21 & 41'h9C000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_23 = _io_resp_eff_T_22; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_24 = _io_resp_eff_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_26 = {1'h0, _io_resp_eff_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_27 = _io_resp_eff_T_26 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_28 = _io_resp_eff_T_27; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_29 = _io_resp_eff_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_eff_T_30 = _io_resp_eff_T_4 | _io_resp_eff_T_9; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_31 = _io_resp_eff_T_30 | _io_resp_eff_T_14; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_32 = _io_resp_eff_T_31 | _io_resp_eff_T_19; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_33 = _io_resp_eff_T_32 | _io_resp_eff_T_24; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_34 = _io_resp_eff_T_33 | _io_resp_eff_T_29; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_58 = _io_resp_eff_T_34; // @[Mux.scala:30:73]
wire [40:0] _io_resp_eff_T_36 = {1'h0, _io_resp_eff_T_35}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_37 = _io_resp_eff_T_36 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_38 = _io_resp_eff_T_37; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_39 = _io_resp_eff_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_41 = {1'h0, _io_resp_eff_T_40}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_42 = _io_resp_eff_T_41 & 41'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_43 = _io_resp_eff_T_42; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_44 = _io_resp_eff_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_46 = {1'h0, _io_resp_eff_T_45}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_47 = _io_resp_eff_T_46 & 41'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_48 = _io_resp_eff_T_47; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_49 = _io_resp_eff_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_51 = {1'h0, _io_resp_eff_T_50}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_52 = _io_resp_eff_T_51 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_53 = _io_resp_eff_T_52; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_54 = _io_resp_eff_T_53 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_eff_T_55 = _io_resp_eff_T_39 | _io_resp_eff_T_44; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_56 = _io_resp_eff_T_55 | _io_resp_eff_T_49; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_57 = _io_resp_eff_T_56 | _io_resp_eff_T_54; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_60 = _io_resp_eff_T_58; // @[Mux.scala:30:73]
wire _io_resp_eff_WIRE = _io_resp_eff_T_60; // @[Mux.scala:30:73]
assign _io_resp_eff_T_61 = legal_address & _io_resp_eff_WIRE; // @[Mux.scala:30:73]
assign io_resp_eff_0 = _io_resp_eff_T_61; // @[PMA.scala:18:7, :39:19]
assign io_resp_cacheable = io_resp_cacheable_0; // @[PMA.scala:18:7]
assign io_resp_r = io_resp_r_0; // @[PMA.scala:18:7]
assign io_resp_w = io_resp_w_0; // @[PMA.scala:18:7]
assign io_resp_pp = io_resp_pp_0; // @[PMA.scala:18:7]
assign io_resp_al = io_resp_al_0; // @[PMA.scala:18:7]
assign io_resp_aa = io_resp_aa_0; // @[PMA.scala:18:7]
assign io_resp_x = io_resp_x_0; // @[PMA.scala:18:7]
assign io_resp_eff = io_resp_eff_0; // @[PMA.scala:18:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLInterconnectCoupler_sbus_to_sport_named_rerocc_2 :
input clock : Clock
input reset : Reset
output auto : { }
inst buffer of TLBuffer_4
connect buffer.clock, clock
connect buffer.reset, reset
inst widget of TLWidthWidget8_5
connect widget.clock, clock
connect widget.reset, reset
inst buffer_1 of TLBuffer_5
connect buffer_1.clock, clock
connect buffer_1.reset, reset
extmodule plusarg_reader_20 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_21 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLInterconnectCoupler_sbus_to_sport_named_rerocc_2( // @[LazyModuleImp.scala:138:7]
input clock, // @[LazyModuleImp.scala:138:7]
input reset // @[LazyModuleImp.scala:138:7]
);
TLBuffer_4 buffer ( // @[Buffer.scala:75:28]
.clock (clock),
.reset (reset)
); // @[Buffer.scala:75:28]
TLBuffer_5 buffer_1 ( // @[Buffer.scala:75:28]
.clock (clock),
.reset (reset)
); // @[Buffer.scala:75:28]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLAsyncCrossingSource_a9d32s1k1z2u :
input clock : Clock
input reset : Reset
output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, out : { a : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip b : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, c : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip d : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, e : { mem : { sink : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}}}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
inst monitor of TLMonitor_92
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
wire nodeOut : { a : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip b : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, c : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip d : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, e : { mem : { sink : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}}
invalidate nodeOut.e.safe.sink_reset_n
invalidate nodeOut.e.safe.source_reset_n
invalidate nodeOut.e.safe.widx_valid
invalidate nodeOut.e.safe.ridx_valid
invalidate nodeOut.e.widx
invalidate nodeOut.e.ridx
invalidate nodeOut.e.mem[0].sink
invalidate nodeOut.d.safe.sink_reset_n
invalidate nodeOut.d.safe.source_reset_n
invalidate nodeOut.d.safe.widx_valid
invalidate nodeOut.d.safe.ridx_valid
invalidate nodeOut.d.widx
invalidate nodeOut.d.ridx
invalidate nodeOut.d.mem[0].corrupt
invalidate nodeOut.d.mem[0].data
invalidate nodeOut.d.mem[0].denied
invalidate nodeOut.d.mem[0].sink
invalidate nodeOut.d.mem[0].source
invalidate nodeOut.d.mem[0].size
invalidate nodeOut.d.mem[0].param
invalidate nodeOut.d.mem[0].opcode
invalidate nodeOut.c.safe.sink_reset_n
invalidate nodeOut.c.safe.source_reset_n
invalidate nodeOut.c.safe.widx_valid
invalidate nodeOut.c.safe.ridx_valid
invalidate nodeOut.c.widx
invalidate nodeOut.c.ridx
invalidate nodeOut.c.mem[0].corrupt
invalidate nodeOut.c.mem[0].data
invalidate nodeOut.c.mem[0].address
invalidate nodeOut.c.mem[0].source
invalidate nodeOut.c.mem[0].size
invalidate nodeOut.c.mem[0].param
invalidate nodeOut.c.mem[0].opcode
invalidate nodeOut.b.safe.sink_reset_n
invalidate nodeOut.b.safe.source_reset_n
invalidate nodeOut.b.safe.widx_valid
invalidate nodeOut.b.safe.ridx_valid
invalidate nodeOut.b.widx
invalidate nodeOut.b.ridx
invalidate nodeOut.b.mem[0].corrupt
invalidate nodeOut.b.mem[0].data
invalidate nodeOut.b.mem[0].mask
invalidate nodeOut.b.mem[0].address
invalidate nodeOut.b.mem[0].source
invalidate nodeOut.b.mem[0].size
invalidate nodeOut.b.mem[0].param
invalidate nodeOut.b.mem[0].opcode
invalidate nodeOut.a.safe.sink_reset_n
invalidate nodeOut.a.safe.source_reset_n
invalidate nodeOut.a.safe.widx_valid
invalidate nodeOut.a.safe.ridx_valid
invalidate nodeOut.a.widx
invalidate nodeOut.a.ridx
invalidate nodeOut.a.mem[0].corrupt
invalidate nodeOut.a.mem[0].data
invalidate nodeOut.a.mem[0].mask
invalidate nodeOut.a.mem[0].address
invalidate nodeOut.a.mem[0].source
invalidate nodeOut.a.mem[0].size
invalidate nodeOut.a.mem[0].param
invalidate nodeOut.a.mem[0].opcode
connect auto.out, nodeOut
connect nodeIn, auto.in
inst nodeOut_a_source of AsyncQueueSource_TLBundleA_a9d32s1k1z2u
connect nodeOut_a_source.clock, clock
connect nodeOut_a_source.reset, reset
connect nodeOut_a_source.io.enq, nodeIn.a
connect nodeOut_a_source.io.async.safe.sink_reset_n, nodeOut.a.safe.sink_reset_n
connect nodeOut.a.safe.source_reset_n, nodeOut_a_source.io.async.safe.source_reset_n
connect nodeOut.a.safe.widx_valid, nodeOut_a_source.io.async.safe.widx_valid
connect nodeOut_a_source.io.async.safe.ridx_valid, nodeOut.a.safe.ridx_valid
connect nodeOut.a.widx, nodeOut_a_source.io.async.widx
connect nodeOut_a_source.io.async.ridx, nodeOut.a.ridx
connect nodeOut.a.mem, nodeOut_a_source.io.async.mem
inst nodeIn_d_sink of AsyncQueueSink_TLBundleD_a9d32s1k1z2u
connect nodeIn_d_sink.clock, clock
connect nodeIn_d_sink.reset, reset
connect nodeIn_d_sink.io.async, nodeOut.d
connect nodeIn.d.bits, nodeIn_d_sink.io.deq.bits
connect nodeIn.d.valid, nodeIn_d_sink.io.deq.valid
connect nodeIn_d_sink.io.deq.ready, nodeIn.d.ready
node _T = and(nodeIn.a.valid, nodeIn.a.ready)
node _T_1 = eq(nodeIn.a.ready, UInt<1>(0h0))
node _T_2 = and(nodeIn.a.valid, _T_1)
node _T_3 = eq(nodeIn.a.valid, UInt<1>(0h0))
node _T_4 = and(_T_3, nodeIn.a.ready)
node _T_5 = eq(nodeIn.a.valid, UInt<1>(0h0))
node _T_6 = eq(nodeIn.a.ready, UInt<1>(0h0))
node _T_7 = and(_T_5, _T_6)
node _T_8 = and(nodeIn.d.valid, nodeIn.d.ready)
node _T_9 = eq(nodeIn.d.ready, UInt<1>(0h0))
node _T_10 = and(nodeIn.d.valid, _T_9)
node _T_11 = eq(nodeIn.d.valid, UInt<1>(0h0))
node _T_12 = and(_T_11, nodeIn.d.ready)
node _T_13 = eq(nodeIn.d.valid, UInt<1>(0h0))
node _T_14 = eq(nodeIn.d.ready, UInt<1>(0h0))
node _T_15 = and(_T_13, _T_14)
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<32>(0h0)
connect _WIRE.bits.mask, UInt<4>(0h0)
connect _WIRE.bits.address, UInt<9>(0h0)
connect _WIRE.bits.source, UInt<1>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.valid, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<32>(0h0)
connect _WIRE_2.bits.address, UInt<9>(0h0)
connect _WIRE_2.bits.source, UInt<1>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.ready, UInt<1>(0h1)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1)
connect nodeOut.b.ridx, UInt<1>(0h0)
connect nodeOut.c.widx, UInt<1>(0h0)
connect nodeOut.e.widx, UInt<1>(0h0) | module TLAsyncCrossingSource_a9d32s1k1z2u( // @[AsyncCrossing.scala:23:9]
input clock, // @[AsyncCrossing.scala:23:9]
input reset, // @[AsyncCrossing.scala:23:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [8:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_mem_0_opcode, // @[LazyModuleImp.scala:107:25]
output [8:0] auto_out_a_mem_0_address, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_mem_0_data, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ridx, // @[LazyModuleImp.scala:107:25]
output auto_out_a_widx, // @[LazyModuleImp.scala:107:25]
input auto_out_a_safe_ridx_valid, // @[LazyModuleImp.scala:107:25]
output auto_out_a_safe_widx_valid, // @[LazyModuleImp.scala:107:25]
output auto_out_a_safe_source_reset_n, // @[LazyModuleImp.scala:107:25]
input auto_out_a_safe_sink_reset_n, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_mem_0_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_mem_0_size, // @[LazyModuleImp.scala:107:25]
input auto_out_d_mem_0_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_out_d_mem_0_data, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ridx, // @[LazyModuleImp.scala:107:25]
input auto_out_d_widx, // @[LazyModuleImp.scala:107:25]
output auto_out_d_safe_ridx_valid, // @[LazyModuleImp.scala:107:25]
input auto_out_d_safe_widx_valid, // @[LazyModuleImp.scala:107:25]
input auto_out_d_safe_source_reset_n, // @[LazyModuleImp.scala:107:25]
output auto_out_d_safe_sink_reset_n // @[LazyModuleImp.scala:107:25]
);
wire auto_in_a_valid_0 = auto_in_a_valid; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[AsyncCrossing.scala:23:9]
wire [8:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[AsyncCrossing.scala:23:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[AsyncCrossing.scala:23:9]
wire auto_out_a_ridx_0 = auto_out_a_ridx; // @[AsyncCrossing.scala:23:9]
wire auto_out_a_safe_ridx_valid_0 = auto_out_a_safe_ridx_valid; // @[AsyncCrossing.scala:23:9]
wire auto_out_a_safe_sink_reset_n_0 = auto_out_a_safe_sink_reset_n; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_d_mem_0_opcode_0 = auto_out_d_mem_0_opcode; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_d_mem_0_size_0 = auto_out_d_mem_0_size; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_mem_0_source_0 = auto_out_d_mem_0_source; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_out_d_mem_0_data_0 = auto_out_d_mem_0_data; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_widx_0 = auto_out_d_widx; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_safe_widx_valid_0 = auto_out_d_safe_widx_valid; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_safe_source_reset_n_0 = auto_out_d_safe_source_reset_n; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_out_b_mem_0_data = 32'h0; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_out_c_mem_0_data = 32'h0; // @[AsyncCrossing.scala:23:9]
wire [31:0] nodeOut_b_mem_0_data = 32'h0; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_c_mem_0_data = 32'h0; // @[MixedNode.scala:542:17]
wire [3:0] auto_out_b_mem_0_mask = 4'h0; // @[AsyncCrossing.scala:23:9]
wire [3:0] nodeOut_b_mem_0_mask = 4'h0; // @[AsyncCrossing.scala:23:9]
wire [8:0] auto_out_b_mem_0_address = 9'h0; // @[AsyncCrossing.scala:23:9]
wire [8:0] auto_out_c_mem_0_address = 9'h0; // @[AsyncCrossing.scala:23:9]
wire [8:0] nodeOut_b_mem_0_address = 9'h0; // @[MixedNode.scala:542:17]
wire [8:0] nodeOut_c_mem_0_address = 9'h0; // @[MixedNode.scala:542:17]
wire [1:0] auto_out_b_mem_0_param = 2'h0; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_b_mem_0_size = 2'h0; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_c_mem_0_size = 2'h0; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_d_mem_0_param = 2'h0; // @[AsyncCrossing.scala:23:9]
wire [1:0] nodeOut_b_mem_0_param = 2'h0; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_b_mem_0_size = 2'h0; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_c_mem_0_size = 2'h0; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_d_mem_0_param = 2'h0; // @[MixedNode.scala:542:17]
wire [3:0] auto_in_a_bits_mask = 4'hF; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_a_mem_0_mask = 4'hF; // @[AsyncCrossing.scala:23:9]
wire [3:0] nodeIn_a_bits_mask = 4'hF; // @[MixedNode.scala:551:17]
wire [3:0] nodeOut_a_mem_0_mask = 4'hF; // @[MixedNode.scala:542:17]
wire auto_in_a_bits_source = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_in_a_bits_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_a_mem_0_source = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_a_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_b_mem_0_source = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_b_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_b_ridx = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_b_widx = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_b_safe_ridx_valid = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_b_safe_widx_valid = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_b_safe_source_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_b_safe_sink_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_c_mem_0_source = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_c_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_c_ridx = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_c_widx = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_c_safe_ridx_valid = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_c_safe_widx_valid = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_c_safe_source_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_c_safe_sink_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_mem_0_sink = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_mem_0_denied = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_e_mem_0_sink = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_e_ridx = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_e_widx = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_e_safe_ridx_valid = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_e_safe_widx_valid = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_e_safe_source_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_e_safe_sink_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9]
wire nodeIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire nodeOut_a_mem_0_source = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_a_mem_0_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_b_mem_0_source = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_b_mem_0_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_b_ridx = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_b_widx = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_b_safe_ridx_valid = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_b_safe_widx_valid = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_b_safe_source_reset_n = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_b_safe_sink_reset_n = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_c_mem_0_source = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_c_mem_0_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_c_ridx = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_c_widx = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_c_safe_ridx_valid = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_c_safe_widx_valid = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_c_safe_source_reset_n = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_c_safe_sink_reset_n = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_d_mem_0_sink = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_d_mem_0_denied = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_d_mem_0_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_e_mem_0_sink = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_e_ridx = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_e_widx = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_e_safe_ridx_valid = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_e_safe_widx_valid = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_e_safe_source_reset_n = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_e_safe_sink_reset_n = 1'h0; // @[MixedNode.scala:542:17]
wire [1:0] auto_in_a_bits_size = 2'h2; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_a_mem_0_size = 2'h2; // @[AsyncCrossing.scala:23:9]
wire [1:0] nodeIn_a_bits_size = 2'h2; // @[MixedNode.scala:551:17]
wire [1:0] nodeOut_a_mem_0_size = 2'h2; // @[MixedNode.scala:542:17]
wire [2:0] auto_in_a_bits_param = 3'h0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_a_mem_0_param = 3'h0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_b_mem_0_opcode = 3'h0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_c_mem_0_opcode = 3'h0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_c_mem_0_param = 3'h0; // @[AsyncCrossing.scala:23:9]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_a_bits_param = 3'h0; // @[MixedNode.scala:551:17]
wire [2:0] nodeOut_a_mem_0_param = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_b_mem_0_opcode = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_mem_0_opcode = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_mem_0_param = 3'h0; // @[MixedNode.scala:542:17]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[AsyncCrossing.scala:23:9]
wire [8:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[AsyncCrossing.scala:23:9]
wire [31:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[AsyncCrossing.scala:23:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[AsyncCrossing.scala:23:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [31:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire [2:0] nodeOut_a_mem_0_opcode; // @[MixedNode.scala:542:17]
wire [8:0] nodeOut_a_mem_0_address; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_mem_0_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_ridx = auto_out_a_ridx_0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_a_widx; // @[MixedNode.scala:542:17]
wire nodeOut_a_safe_ridx_valid = auto_out_a_safe_ridx_valid_0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_a_safe_widx_valid; // @[MixedNode.scala:542:17]
wire nodeOut_a_safe_source_reset_n; // @[MixedNode.scala:542:17]
wire nodeOut_a_safe_sink_reset_n = auto_out_a_safe_sink_reset_n_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] nodeOut_d_mem_0_opcode = auto_out_d_mem_0_opcode_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] nodeOut_d_mem_0_size = auto_out_d_mem_0_size_0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_d_mem_0_source = auto_out_d_mem_0_source_0; // @[AsyncCrossing.scala:23:9]
wire [31:0] nodeOut_d_mem_0_data = auto_out_d_mem_0_data_0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_d_ridx; // @[MixedNode.scala:542:17]
wire nodeOut_d_widx = auto_out_d_widx_0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_d_safe_ridx_valid; // @[MixedNode.scala:542:17]
wire nodeOut_d_safe_widx_valid = auto_out_d_safe_widx_valid_0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_d_safe_source_reset_n = auto_out_d_safe_source_reset_n_0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_d_safe_sink_reset_n; // @[MixedNode.scala:542:17]
wire auto_in_a_ready_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_in_d_bits_param_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_in_d_bits_size_0; // @[AsyncCrossing.scala:23:9]
wire auto_in_d_bits_source_0; // @[AsyncCrossing.scala:23:9]
wire auto_in_d_bits_sink_0; // @[AsyncCrossing.scala:23:9]
wire auto_in_d_bits_denied_0; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_in_d_bits_data_0; // @[AsyncCrossing.scala:23:9]
wire auto_in_d_bits_corrupt_0; // @[AsyncCrossing.scala:23:9]
wire auto_in_d_valid_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_a_mem_0_opcode_0; // @[AsyncCrossing.scala:23:9]
wire [8:0] auto_out_a_mem_0_address_0; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_out_a_mem_0_data_0; // @[AsyncCrossing.scala:23:9]
wire auto_out_a_safe_widx_valid_0; // @[AsyncCrossing.scala:23:9]
wire auto_out_a_safe_source_reset_n_0; // @[AsyncCrossing.scala:23:9]
wire auto_out_a_widx_0; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_safe_ridx_valid_0; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_safe_sink_reset_n_0; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_ridx_0; // @[AsyncCrossing.scala:23:9]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_0_opcode_0 = nodeOut_a_mem_0_opcode; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_0_address_0 = nodeOut_a_mem_0_address; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_0_data_0 = nodeOut_a_mem_0_data; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_widx_0 = nodeOut_a_widx; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_safe_widx_valid_0 = nodeOut_a_safe_widx_valid; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_safe_source_reset_n_0 = nodeOut_a_safe_source_reset_n; // @[AsyncCrossing.scala:23:9]
assign auto_out_d_ridx_0 = nodeOut_d_ridx; // @[AsyncCrossing.scala:23:9]
assign auto_out_d_safe_ridx_valid_0 = nodeOut_d_safe_ridx_valid; // @[AsyncCrossing.scala:23:9]
assign auto_out_d_safe_sink_reset_n_0 = nodeOut_d_safe_sink_reset_n; // @[AsyncCrossing.scala:23:9]
TLMonitor_92 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
AsyncQueueSource_TLBundleA_a9d32s1k1z2u nodeOut_a_source ( // @[AsyncQueue.scala:220:24]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_a_ready),
.io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_async_mem_0_opcode (nodeOut_a_mem_0_opcode),
.io_async_mem_0_address (nodeOut_a_mem_0_address),
.io_async_mem_0_data (nodeOut_a_mem_0_data),
.io_async_ridx (nodeOut_a_ridx), // @[MixedNode.scala:542:17]
.io_async_widx (nodeOut_a_widx),
.io_async_safe_ridx_valid (nodeOut_a_safe_ridx_valid), // @[MixedNode.scala:542:17]
.io_async_safe_widx_valid (nodeOut_a_safe_widx_valid),
.io_async_safe_source_reset_n (nodeOut_a_safe_source_reset_n),
.io_async_safe_sink_reset_n (nodeOut_a_safe_sink_reset_n) // @[MixedNode.scala:542:17]
); // @[AsyncQueue.scala:220:24]
AsyncQueueSink_TLBundleD_a9d32s1k1z2u nodeIn_d_sink ( // @[AsyncQueue.scala:211:22]
.clock (clock),
.reset (reset),
.io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_d_valid),
.io_deq_bits_opcode (nodeIn_d_bits_opcode),
.io_deq_bits_param (nodeIn_d_bits_param),
.io_deq_bits_size (nodeIn_d_bits_size),
.io_deq_bits_source (nodeIn_d_bits_source),
.io_deq_bits_sink (nodeIn_d_bits_sink),
.io_deq_bits_denied (nodeIn_d_bits_denied),
.io_deq_bits_data (nodeIn_d_bits_data),
.io_deq_bits_corrupt (nodeIn_d_bits_corrupt),
.io_async_mem_0_opcode (nodeOut_d_mem_0_opcode), // @[MixedNode.scala:542:17]
.io_async_mem_0_size (nodeOut_d_mem_0_size), // @[MixedNode.scala:542:17]
.io_async_mem_0_source (nodeOut_d_mem_0_source), // @[MixedNode.scala:542:17]
.io_async_mem_0_data (nodeOut_d_mem_0_data), // @[MixedNode.scala:542:17]
.io_async_ridx (nodeOut_d_ridx),
.io_async_widx (nodeOut_d_widx), // @[MixedNode.scala:542:17]
.io_async_safe_ridx_valid (nodeOut_d_safe_ridx_valid),
.io_async_safe_widx_valid (nodeOut_d_safe_widx_valid), // @[MixedNode.scala:542:17]
.io_async_safe_source_reset_n (nodeOut_d_safe_source_reset_n), // @[MixedNode.scala:542:17]
.io_async_safe_sink_reset_n (nodeOut_d_safe_sink_reset_n)
); // @[AsyncQueue.scala:211:22]
assign auto_in_a_ready = auto_in_a_ready_0; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_valid = auto_in_d_valid_0; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_0_opcode = auto_out_a_mem_0_opcode_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_0_address = auto_out_a_mem_0_address_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_0_data = auto_out_a_mem_0_data_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_widx = auto_out_a_widx_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_safe_widx_valid = auto_out_a_safe_widx_valid_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_safe_source_reset_n = auto_out_a_safe_source_reset_n_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_d_ridx = auto_out_d_ridx_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_d_safe_ridx_valid = auto_out_d_safe_ridx_valid_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_d_safe_sink_reset_n = auto_out_d_safe_sink_reset_n_0; // @[AsyncCrossing.scala:23:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_78 :
input clock : Clock
input reset : Reset
output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, request_hp : UInt<1>, flip grant : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip kill : UInt<1>, flip clear : UInt<1>, flip ldspec_miss : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<7>, poisoned : UInt<1>}}[2], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<7>}[1], flip in_uop : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}, out_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, debug : { p1 : UInt<1>, p2 : UInt<1>, p3 : UInt<1>, ppred : UInt<1>, state : UInt<2>}}
wire next_state : UInt
wire next_uopc : UInt
wire next_lrs1_rtype : UInt
wire next_lrs2_rtype : UInt
regreset state : UInt<2>, clock, reset, UInt<2>(0h0)
regreset p1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset p2 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset p3 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset ppred : UInt<1>, clock, reset, UInt<1>(0h0)
regreset p1_poisoned : UInt<1>, clock, reset, UInt<1>(0h0)
regreset p2_poisoned : UInt<1>, clock, reset, UInt<1>(0h0)
connect p1_poisoned, UInt<1>(0h0)
connect p2_poisoned, UInt<1>(0h0)
node next_p1_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned)
node next_p2_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned)
wire slot_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
invalidate slot_uop_uop.debug_tsrc
invalidate slot_uop_uop.debug_fsrc
invalidate slot_uop_uop.bp_xcpt_if
invalidate slot_uop_uop.bp_debug_if
invalidate slot_uop_uop.xcpt_ma_if
invalidate slot_uop_uop.xcpt_ae_if
invalidate slot_uop_uop.xcpt_pf_if
invalidate slot_uop_uop.fp_single
invalidate slot_uop_uop.fp_val
invalidate slot_uop_uop.frs3_en
invalidate slot_uop_uop.lrs2_rtype
invalidate slot_uop_uop.lrs1_rtype
invalidate slot_uop_uop.dst_rtype
invalidate slot_uop_uop.ldst_val
invalidate slot_uop_uop.lrs3
invalidate slot_uop_uop.lrs2
invalidate slot_uop_uop.lrs1
invalidate slot_uop_uop.ldst
invalidate slot_uop_uop.ldst_is_rs1
invalidate slot_uop_uop.flush_on_commit
invalidate slot_uop_uop.is_unique
invalidate slot_uop_uop.is_sys_pc2epc
invalidate slot_uop_uop.uses_stq
invalidate slot_uop_uop.uses_ldq
invalidate slot_uop_uop.is_amo
invalidate slot_uop_uop.is_fencei
invalidate slot_uop_uop.is_fence
invalidate slot_uop_uop.mem_signed
invalidate slot_uop_uop.mem_size
invalidate slot_uop_uop.mem_cmd
invalidate slot_uop_uop.bypassable
invalidate slot_uop_uop.exc_cause
invalidate slot_uop_uop.exception
invalidate slot_uop_uop.stale_pdst
invalidate slot_uop_uop.ppred_busy
invalidate slot_uop_uop.prs3_busy
invalidate slot_uop_uop.prs2_busy
invalidate slot_uop_uop.prs1_busy
invalidate slot_uop_uop.ppred
invalidate slot_uop_uop.prs3
invalidate slot_uop_uop.prs2
invalidate slot_uop_uop.prs1
invalidate slot_uop_uop.pdst
invalidate slot_uop_uop.rxq_idx
invalidate slot_uop_uop.stq_idx
invalidate slot_uop_uop.ldq_idx
invalidate slot_uop_uop.rob_idx
invalidate slot_uop_uop.csr_addr
invalidate slot_uop_uop.imm_packed
invalidate slot_uop_uop.taken
invalidate slot_uop_uop.pc_lob
invalidate slot_uop_uop.edge_inst
invalidate slot_uop_uop.ftq_idx
invalidate slot_uop_uop.br_tag
invalidate slot_uop_uop.br_mask
invalidate slot_uop_uop.is_sfb
invalidate slot_uop_uop.is_jal
invalidate slot_uop_uop.is_jalr
invalidate slot_uop_uop.is_br
invalidate slot_uop_uop.iw_p2_poisoned
invalidate slot_uop_uop.iw_p1_poisoned
invalidate slot_uop_uop.iw_state
invalidate slot_uop_uop.ctrl.is_std
invalidate slot_uop_uop.ctrl.is_sta
invalidate slot_uop_uop.ctrl.is_load
invalidate slot_uop_uop.ctrl.csr_cmd
invalidate slot_uop_uop.ctrl.fcn_dw
invalidate slot_uop_uop.ctrl.op_fcn
invalidate slot_uop_uop.ctrl.imm_sel
invalidate slot_uop_uop.ctrl.op2_sel
invalidate slot_uop_uop.ctrl.op1_sel
invalidate slot_uop_uop.ctrl.br_type
invalidate slot_uop_uop.fu_code
invalidate slot_uop_uop.iq_type
invalidate slot_uop_uop.debug_pc
invalidate slot_uop_uop.is_rvc
invalidate slot_uop_uop.debug_inst
invalidate slot_uop_uop.inst
invalidate slot_uop_uop.uopc
connect slot_uop_uop.uopc, UInt<7>(0h0)
connect slot_uop_uop.bypassable, UInt<1>(0h0)
connect slot_uop_uop.fp_val, UInt<1>(0h0)
connect slot_uop_uop.uses_stq, UInt<1>(0h0)
connect slot_uop_uop.uses_ldq, UInt<1>(0h0)
connect slot_uop_uop.pdst, UInt<1>(0h0)
connect slot_uop_uop.dst_rtype, UInt<2>(0h2)
wire slot_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}
invalidate slot_uop_cs.is_std
invalidate slot_uop_cs.is_sta
invalidate slot_uop_cs.is_load
invalidate slot_uop_cs.csr_cmd
invalidate slot_uop_cs.fcn_dw
invalidate slot_uop_cs.op_fcn
invalidate slot_uop_cs.imm_sel
invalidate slot_uop_cs.op2_sel
invalidate slot_uop_cs.op1_sel
invalidate slot_uop_cs.br_type
connect slot_uop_cs.br_type, UInt<4>(0h0)
connect slot_uop_cs.csr_cmd, UInt<3>(0h0)
connect slot_uop_cs.is_load, UInt<1>(0h0)
connect slot_uop_cs.is_sta, UInt<1>(0h0)
connect slot_uop_cs.is_std, UInt<1>(0h0)
connect slot_uop_uop.ctrl, slot_uop_cs
regreset slot_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock, reset, slot_uop_uop
node next_uop = mux(io.in_uop.valid, io.in_uop.bits, slot_uop)
when io.kill :
connect state, UInt<2>(0h0)
else :
when io.in_uop.valid :
connect state, io.in_uop.bits.iw_state
else :
when io.clear :
connect state, UInt<2>(0h0)
else :
connect state, next_state
connect next_state, state
connect next_uopc, slot_uop.uopc
connect next_lrs1_rtype, slot_uop.lrs1_rtype
connect next_lrs2_rtype, slot_uop.lrs2_rtype
when io.kill :
connect next_state, UInt<2>(0h0)
else :
node _T = eq(state, UInt<2>(0h1))
node _T_1 = and(io.grant, _T)
node _T_2 = eq(state, UInt<2>(0h2))
node _T_3 = and(io.grant, _T_2)
node _T_4 = and(_T_3, p1)
node _T_5 = and(_T_4, p2)
node _T_6 = and(_T_5, ppred)
node _T_7 = or(_T_1, _T_6)
when _T_7 :
node _T_8 = or(p1_poisoned, p2_poisoned)
node _T_9 = and(io.ldspec_miss, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
when _T_10 :
connect next_state, UInt<2>(0h0)
else :
node _T_11 = eq(state, UInt<2>(0h2))
node _T_12 = and(io.grant, _T_11)
when _T_12 :
node _T_13 = or(p1_poisoned, p2_poisoned)
node _T_14 = and(io.ldspec_miss, _T_13)
node _T_15 = eq(_T_14, UInt<1>(0h0))
when _T_15 :
connect next_state, UInt<2>(0h1)
when p1 :
connect slot_uop.uopc, UInt<7>(0h3)
connect next_uopc, UInt<7>(0h3)
connect slot_uop.lrs1_rtype, UInt<2>(0h2)
connect next_lrs1_rtype, UInt<2>(0h2)
else :
connect slot_uop.lrs2_rtype, UInt<2>(0h2)
connect next_lrs2_rtype, UInt<2>(0h2)
when io.in_uop.valid :
connect slot_uop, io.in_uop.bits
node _T_16 = eq(state, UInt<2>(0h0))
node _T_17 = or(_T_16, io.clear)
node _T_18 = or(_T_17, io.kill)
node _T_19 = asUInt(reset)
node _T_20 = eq(_T_19, UInt<1>(0h0))
when _T_20 :
node _T_21 = eq(_T_18, UInt<1>(0h0))
when _T_21 :
printf(clock, UInt<1>(0h1), "Assertion failed: trying to overwrite a valid issue slot.\n at issue-slot.scala:156 assert (is_invalid || io.clear || io.kill, \"trying to overwrite a valid issue slot.\")\n") : printf
assert(clock, _T_18, UInt<1>(0h1), "") : assert
wire next_p1 : UInt<1>
connect next_p1, p1
wire next_p2 : UInt<1>
connect next_p2, p2
wire next_p3 : UInt<1>
connect next_p3, p3
wire next_ppred : UInt<1>
connect next_ppred, ppred
when io.in_uop.valid :
node _p1_T = eq(io.in_uop.bits.prs1_busy, UInt<1>(0h0))
connect p1, _p1_T
node _p2_T = eq(io.in_uop.bits.prs2_busy, UInt<1>(0h0))
connect p2, _p2_T
node _p3_T = eq(io.in_uop.bits.prs3_busy, UInt<1>(0h0))
connect p3, _p3_T
node _ppred_T = eq(io.in_uop.bits.ppred_busy, UInt<1>(0h0))
connect ppred, _ppred_T
node _T_22 = and(io.ldspec_miss, next_p1_poisoned)
when _T_22 :
node _T_23 = neq(next_uop.prs1, UInt<1>(0h0))
node _T_24 = asUInt(reset)
node _T_25 = eq(_T_24, UInt<1>(0h0))
when _T_25 :
node _T_26 = eq(_T_23, UInt<1>(0h0))
when _T_26 :
printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs1=x0!\n at issue-slot.scala:176 assert(next_uop.prs1 =/= 0.U, \"Poison bit can't be set for prs1=x0!\")\n") : printf_1
assert(clock, _T_23, UInt<1>(0h1), "") : assert_1
connect p1, UInt<1>(0h0)
node _T_27 = and(io.ldspec_miss, next_p2_poisoned)
when _T_27 :
node _T_28 = neq(next_uop.prs2, UInt<1>(0h0))
node _T_29 = asUInt(reset)
node _T_30 = eq(_T_29, UInt<1>(0h0))
when _T_30 :
node _T_31 = eq(_T_28, UInt<1>(0h0))
when _T_31 :
printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs2=x0!\n at issue-slot.scala:180 assert(next_uop.prs2 =/= 0.U, \"Poison bit can't be set for prs2=x0!\")\n") : printf_2
assert(clock, _T_28, UInt<1>(0h1), "") : assert_2
connect p2, UInt<1>(0h0)
node _T_32 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs1)
node _T_33 = and(io.wakeup_ports[0].valid, _T_32)
when _T_33 :
connect p1, UInt<1>(0h1)
node _T_34 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs2)
node _T_35 = and(io.wakeup_ports[0].valid, _T_34)
when _T_35 :
connect p2, UInt<1>(0h1)
node _T_36 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs3)
node _T_37 = and(io.wakeup_ports[0].valid, _T_36)
when _T_37 :
connect p3, UInt<1>(0h1)
node _T_38 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs1)
node _T_39 = and(io.wakeup_ports[1].valid, _T_38)
when _T_39 :
connect p1, UInt<1>(0h1)
node _T_40 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs2)
node _T_41 = and(io.wakeup_ports[1].valid, _T_40)
when _T_41 :
connect p2, UInt<1>(0h1)
node _T_42 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs3)
node _T_43 = and(io.wakeup_ports[1].valid, _T_42)
when _T_43 :
connect p3, UInt<1>(0h1)
node _T_44 = eq(io.pred_wakeup_port.bits, next_uop.ppred)
node _T_45 = and(io.pred_wakeup_port.valid, _T_44)
when _T_45 :
connect ppred, UInt<1>(0h1)
node _T_46 = eq(io.spec_ld_wakeup[0].bits, UInt<1>(0h0))
node _T_47 = and(io.spec_ld_wakeup[0].valid, _T_46)
node _T_48 = eq(_T_47, UInt<1>(0h0))
node _T_49 = asUInt(reset)
node _T_50 = eq(_T_49, UInt<1>(0h0))
when _T_50 :
node _T_51 = eq(_T_48, UInt<1>(0h0))
when _T_51 :
printf(clock, UInt<1>(0h1), "Assertion failed: Loads to x0 should never speculatively wakeup other instructions\n at issue-slot.scala:203 assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),\n") : printf_3
assert(clock, _T_48, UInt<1>(0h1), "") : assert_3
node _T_52 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs1)
node _T_53 = and(io.spec_ld_wakeup[0].valid, _T_52)
node _T_54 = eq(next_uop.lrs1_rtype, UInt<2>(0h0))
node _T_55 = and(_T_53, _T_54)
when _T_55 :
connect p1, UInt<1>(0h1)
connect p1_poisoned, UInt<1>(0h1)
node _T_56 = eq(next_p1_poisoned, UInt<1>(0h0))
node _T_57 = asUInt(reset)
node _T_58 = eq(_T_57, UInt<1>(0h0))
when _T_58 :
node _T_59 = eq(_T_56, UInt<1>(0h0))
when _T_59 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:214 assert (!next_p1_poisoned)\n") : printf_4
assert(clock, _T_56, UInt<1>(0h1), "") : assert_4
node _T_60 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs2)
node _T_61 = and(io.spec_ld_wakeup[0].valid, _T_60)
node _T_62 = eq(next_uop.lrs2_rtype, UInt<2>(0h0))
node _T_63 = and(_T_61, _T_62)
when _T_63 :
connect p2, UInt<1>(0h1)
connect p2_poisoned, UInt<1>(0h1)
node _T_64 = eq(next_p2_poisoned, UInt<1>(0h0))
node _T_65 = asUInt(reset)
node _T_66 = eq(_T_65, UInt<1>(0h0))
when _T_66 :
node _T_67 = eq(_T_64, UInt<1>(0h0))
when _T_67 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:221 assert (!next_p2_poisoned)\n") : printf_5
assert(clock, _T_64, UInt<1>(0h1), "") : assert_5
node _next_br_mask_T = not(io.brupdate.b1.resolve_mask)
node next_br_mask = and(slot_uop.br_mask, _next_br_mask_T)
node _T_68 = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask)
node _T_69 = neq(_T_68, UInt<1>(0h0))
when _T_69 :
connect next_state, UInt<2>(0h0)
node _T_70 = eq(io.in_uop.valid, UInt<1>(0h0))
when _T_70 :
connect slot_uop.br_mask, next_br_mask
node _io_request_T = neq(state, UInt<2>(0h0))
node _io_request_T_1 = and(_io_request_T, p1)
node _io_request_T_2 = and(_io_request_T_1, p2)
node _io_request_T_3 = and(_io_request_T_2, p3)
node _io_request_T_4 = and(_io_request_T_3, ppred)
node _io_request_T_5 = eq(io.kill, UInt<1>(0h0))
node _io_request_T_6 = and(_io_request_T_4, _io_request_T_5)
connect io.request, _io_request_T_6
node _high_priority_T = or(slot_uop.is_br, slot_uop.is_jal)
node high_priority = or(_high_priority_T, slot_uop.is_jalr)
node _io_request_hp_T = and(io.request, high_priority)
connect io.request_hp, _io_request_hp_T
node _T_71 = eq(state, UInt<2>(0h1))
when _T_71 :
node _io_request_T_7 = and(p1, p2)
node _io_request_T_8 = and(_io_request_T_7, p3)
node _io_request_T_9 = and(_io_request_T_8, ppred)
node _io_request_T_10 = eq(io.kill, UInt<1>(0h0))
node _io_request_T_11 = and(_io_request_T_9, _io_request_T_10)
connect io.request, _io_request_T_11
else :
node _T_72 = eq(state, UInt<2>(0h2))
when _T_72 :
node _io_request_T_12 = or(p1, p2)
node _io_request_T_13 = and(_io_request_T_12, ppred)
node _io_request_T_14 = eq(io.kill, UInt<1>(0h0))
node _io_request_T_15 = and(_io_request_T_13, _io_request_T_14)
connect io.request, _io_request_T_15
else :
connect io.request, UInt<1>(0h0)
node _io_valid_T = neq(state, UInt<2>(0h0))
connect io.valid, _io_valid_T
connect io.uop, slot_uop
connect io.uop.iw_p1_poisoned, p1_poisoned
connect io.uop.iw_p2_poisoned, p2_poisoned
node _may_vacate_T = eq(state, UInt<2>(0h1))
node _may_vacate_T_1 = eq(state, UInt<2>(0h2))
node _may_vacate_T_2 = and(_may_vacate_T_1, p1)
node _may_vacate_T_3 = and(_may_vacate_T_2, p2)
node _may_vacate_T_4 = and(_may_vacate_T_3, ppred)
node _may_vacate_T_5 = or(_may_vacate_T, _may_vacate_T_4)
node may_vacate = and(io.grant, _may_vacate_T_5)
node _squash_grant_T = or(p1_poisoned, p2_poisoned)
node squash_grant = and(io.ldspec_miss, _squash_grant_T)
node _io_will_be_valid_T = neq(state, UInt<2>(0h0))
node _io_will_be_valid_T_1 = eq(squash_grant, UInt<1>(0h0))
node _io_will_be_valid_T_2 = and(may_vacate, _io_will_be_valid_T_1)
node _io_will_be_valid_T_3 = eq(_io_will_be_valid_T_2, UInt<1>(0h0))
node _io_will_be_valid_T_4 = and(_io_will_be_valid_T, _io_will_be_valid_T_3)
connect io.will_be_valid, _io_will_be_valid_T_4
connect io.out_uop, slot_uop
connect io.out_uop.iw_state, next_state
connect io.out_uop.uopc, next_uopc
connect io.out_uop.lrs1_rtype, next_lrs1_rtype
connect io.out_uop.lrs2_rtype, next_lrs2_rtype
connect io.out_uop.br_mask, next_br_mask
node _io_out_uop_prs1_busy_T = eq(p1, UInt<1>(0h0))
connect io.out_uop.prs1_busy, _io_out_uop_prs1_busy_T
node _io_out_uop_prs2_busy_T = eq(p2, UInt<1>(0h0))
connect io.out_uop.prs2_busy, _io_out_uop_prs2_busy_T
node _io_out_uop_prs3_busy_T = eq(p3, UInt<1>(0h0))
connect io.out_uop.prs3_busy, _io_out_uop_prs3_busy_T
node _io_out_uop_ppred_busy_T = eq(ppred, UInt<1>(0h0))
connect io.out_uop.ppred_busy, _io_out_uop_ppred_busy_T
connect io.out_uop.iw_p1_poisoned, p1_poisoned
connect io.out_uop.iw_p2_poisoned, p2_poisoned
node _T_73 = eq(state, UInt<2>(0h2))
when _T_73 :
node _T_74 = and(p1, p2)
node _T_75 = and(_T_74, ppred)
when _T_75 :
skip
else :
node _T_76 = and(p1, ppred)
when _T_76 :
connect io.uop.uopc, slot_uop.uopc
connect io.uop.lrs2_rtype, UInt<2>(0h2)
else :
node _T_77 = and(p2, ppred)
when _T_77 :
connect io.uop.uopc, UInt<7>(0h3)
connect io.uop.lrs1_rtype, UInt<2>(0h2)
connect io.debug.p1, p1
connect io.debug.p2, p2
connect io.debug.p3, p3
connect io.debug.ppred, ppred
connect io.debug.state, state | module IssueSlot_78( // @[issue-slot.scala:69:7]
input clock, // @[issue-slot.scala:69:7]
input reset, // @[issue-slot.scala:69:7]
output io_valid, // @[issue-slot.scala:73:14]
output io_will_be_valid, // @[issue-slot.scala:73:14]
output io_request, // @[issue-slot.scala:73:14]
output io_request_hp, // @[issue-slot.scala:73:14]
input io_grant, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14]
input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14]
input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14]
input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14]
input io_brupdate_b2_valid, // @[issue-slot.scala:73:14]
input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14]
input io_brupdate_b2_taken, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14]
input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14]
input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14]
input io_kill, // @[issue-slot.scala:73:14]
input io_clear, // @[issue-slot.scala:73:14]
input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14]
input io_in_uop_valid, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14]
input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14]
input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14]
input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14]
input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14]
input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14]
input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14]
input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14]
input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14]
input io_in_uop_bits_taken, // @[issue-slot.scala:73:14]
input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14]
input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14]
input io_in_uop_bits_exception, // @[issue-slot.scala:73:14]
input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14]
input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14]
input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14]
input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14]
input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14]
input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14]
input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14]
input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14]
output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14]
output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14]
output io_out_uop_is_rvc, // @[issue-slot.scala:73:14]
output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14]
output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14]
output io_out_uop_is_br, // @[issue-slot.scala:73:14]
output io_out_uop_is_jalr, // @[issue-slot.scala:73:14]
output io_out_uop_is_jal, // @[issue-slot.scala:73:14]
output io_out_uop_is_sfb, // @[issue-slot.scala:73:14]
output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14]
output io_out_uop_edge_inst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14]
output io_out_uop_taken, // @[issue-slot.scala:73:14]
output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14]
output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14]
output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14]
output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14]
output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14]
output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14]
output io_out_uop_exception, // @[issue-slot.scala:73:14]
output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14]
output io_out_uop_bypassable, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14]
output io_out_uop_mem_signed, // @[issue-slot.scala:73:14]
output io_out_uop_is_fence, // @[issue-slot.scala:73:14]
output io_out_uop_is_fencei, // @[issue-slot.scala:73:14]
output io_out_uop_is_amo, // @[issue-slot.scala:73:14]
output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14]
output io_out_uop_uses_stq, // @[issue-slot.scala:73:14]
output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
output io_out_uop_is_unique, // @[issue-slot.scala:73:14]
output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14]
output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14]
output io_out_uop_ldst_val, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
output io_out_uop_frs3_en, // @[issue-slot.scala:73:14]
output io_out_uop_fp_val, // @[issue-slot.scala:73:14]
output io_out_uop_fp_single, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14]
output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14]
output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14]
output [31:0] io_uop_inst, // @[issue-slot.scala:73:14]
output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14]
output io_uop_is_rvc, // @[issue-slot.scala:73:14]
output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14]
output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14]
output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14]
output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14]
output io_uop_is_br, // @[issue-slot.scala:73:14]
output io_uop_is_jalr, // @[issue-slot.scala:73:14]
output io_uop_is_jal, // @[issue-slot.scala:73:14]
output io_uop_is_sfb, // @[issue-slot.scala:73:14]
output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14]
output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14]
output io_uop_edge_inst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14]
output io_uop_taken, // @[issue-slot.scala:73:14]
output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14]
output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14]
output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14]
output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14]
output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14]
output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14]
output io_uop_prs1_busy, // @[issue-slot.scala:73:14]
output io_uop_prs2_busy, // @[issue-slot.scala:73:14]
output io_uop_prs3_busy, // @[issue-slot.scala:73:14]
output io_uop_ppred_busy, // @[issue-slot.scala:73:14]
output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14]
output io_uop_exception, // @[issue-slot.scala:73:14]
output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14]
output io_uop_bypassable, // @[issue-slot.scala:73:14]
output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14]
output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14]
output io_uop_mem_signed, // @[issue-slot.scala:73:14]
output io_uop_is_fence, // @[issue-slot.scala:73:14]
output io_uop_is_fencei, // @[issue-slot.scala:73:14]
output io_uop_is_amo, // @[issue-slot.scala:73:14]
output io_uop_uses_ldq, // @[issue-slot.scala:73:14]
output io_uop_uses_stq, // @[issue-slot.scala:73:14]
output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
output io_uop_is_unique, // @[issue-slot.scala:73:14]
output io_uop_flush_on_commit, // @[issue-slot.scala:73:14]
output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14]
output io_uop_ldst_val, // @[issue-slot.scala:73:14]
output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
output io_uop_frs3_en, // @[issue-slot.scala:73:14]
output io_uop_fp_val, // @[issue-slot.scala:73:14]
output io_uop_fp_single, // @[issue-slot.scala:73:14]
output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
output io_uop_bp_debug_if, // @[issue-slot.scala:73:14]
output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14]
output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14]
output io_debug_p1, // @[issue-slot.scala:73:14]
output io_debug_p2, // @[issue-slot.scala:73:14]
output io_debug_p3, // @[issue-slot.scala:73:14]
output io_debug_ppred, // @[issue-slot.scala:73:14]
output [1:0] io_debug_state // @[issue-slot.scala:73:14]
);
wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7]
wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7]
wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7]
wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7]
wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7]
wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7]
wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7]
wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7]
wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7]
wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7]
wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7]
wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7]
wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7]
wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7]
wire io_ldspec_miss = 1'h0; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7]
wire io_spec_ld_wakeup_0_valid = 1'h0; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire io_out_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire io_out_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire io_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire io_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire next_p1_poisoned = 1'h0; // @[issue-slot.scala:99:29]
wire next_p2_poisoned = 1'h0; // @[issue-slot.scala:100:29]
wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire _squash_grant_T = 1'h0; // @[issue-slot.scala:261:53]
wire squash_grant = 1'h0; // @[issue-slot.scala:261:37]
wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7]
wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [6:0] io_spec_ld_wakeup_0_bits = 7'h0; // @[issue-slot.scala:69:7]
wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire _io_will_be_valid_T_1 = 1'h1; // @[issue-slot.scala:262:51]
wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19]
wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire _io_valid_T; // @[issue-slot.scala:79:24]
wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32]
wire _io_request_hp_T; // @[issue-slot.scala:243:31]
wire [6:0] next_uopc; // @[issue-slot.scala:82:29]
wire [1:0] next_state; // @[issue-slot.scala:81:29]
wire [15:0] next_br_mask; // @[util.scala:85:25]
wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28]
wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28]
wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28]
wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28]
wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29]
wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29]
wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7]
wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7]
wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7]
wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7]
wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7]
wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7]
wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7]
wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7]
wire io_out_uop_taken_0; // @[issue-slot.scala:69:7]
wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7]
wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7]
wire io_out_uop_exception_0; // @[issue-slot.scala:69:7]
wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7]
wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7]
wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7]
wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7]
wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7]
wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7]
wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7]
wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7]
wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7]
wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7]
wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7]
wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7]
wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7]
wire io_uop_is_br_0; // @[issue-slot.scala:69:7]
wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7]
wire io_uop_is_jal_0; // @[issue-slot.scala:69:7]
wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7]
wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7]
wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7]
wire io_uop_taken_0; // @[issue-slot.scala:69:7]
wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7]
wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7]
wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7]
wire io_uop_exception_0; // @[issue-slot.scala:69:7]
wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7]
wire io_uop_bypassable_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7]
wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7]
wire io_uop_is_fence_0; // @[issue-slot.scala:69:7]
wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7]
wire io_uop_is_amo_0; // @[issue-slot.scala:69:7]
wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7]
wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7]
wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7]
wire io_uop_is_unique_0; // @[issue-slot.scala:69:7]
wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7]
wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7]
wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7]
wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7]
wire io_uop_fp_val_0; // @[issue-slot.scala:69:7]
wire io_uop_fp_single_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7]
wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7]
wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7]
wire io_debug_p1_0; // @[issue-slot.scala:69:7]
wire io_debug_p2_0; // @[issue-slot.scala:69:7]
wire io_debug_p3_0; // @[issue-slot.scala:69:7]
wire io_debug_ppred_0; // @[issue-slot.scala:69:7]
wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7]
wire io_valid_0; // @[issue-slot.scala:69:7]
wire io_will_be_valid_0; // @[issue-slot.scala:69:7]
wire io_request_0; // @[issue-slot.scala:69:7]
wire io_request_hp_0; // @[issue-slot.scala:69:7]
assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29]
assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29]
assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29]
assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29]
reg [1:0] state; // @[issue-slot.scala:86:22]
assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22]
reg p1; // @[issue-slot.scala:87:22]
assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22]
wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25]
reg p2; // @[issue-slot.scala:88:22]
assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22]
wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25]
reg p3; // @[issue-slot.scala:89:22]
assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22]
wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25]
reg ppred; // @[issue-slot.scala:90:22]
assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22]
wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28]
reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25]
reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25]
reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_rvc; // @[issue-slot.scala:102:25]
assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25]
reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25]
assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25]
reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25]
assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25]
assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25]
reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25]
reg slot_uop_is_br; // @[issue-slot.scala:102:25]
assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_jalr; // @[issue-slot.scala:102:25]
assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_jal; // @[issue-slot.scala:102:25]
assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_sfb; // @[issue-slot.scala:102:25]
assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25]
reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25]
assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25]
assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_edge_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25]
assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_taken; // @[issue-slot.scala:102:25]
assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25]
reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25]
assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25]
reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25]
assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25]
assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25]
assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25]
assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25]
assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25]
assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25]
assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25]
assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_exception; // @[issue-slot.scala:102:25]
assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25]
reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25]
assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bypassable; // @[issue-slot.scala:102:25]
assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_mem_signed; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_fence; // @[issue-slot.scala:102:25]
assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_fencei; // @[issue-slot.scala:102:25]
assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_amo; // @[issue-slot.scala:102:25]
assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25]
assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_uses_stq; // @[issue-slot.scala:102:25]
assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25]
assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_unique; // @[issue-slot.scala:102:25]
assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25]
assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ldst_val; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25]
assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25]
reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25]
reg slot_uop_frs3_en; // @[issue-slot.scala:102:25]
assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_fp_val; // @[issue-slot.scala:102:25]
assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_fp_single; // @[issue-slot.scala:102:25]
assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25]
assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25]
assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25]
wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_iw_p1_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_iw_p2_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25]
wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}]
wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25]
wire _GEN = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51]
wire _GEN_0 = _GEN | ~(_T_12 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17, :143:23]
assign next_uopc = _GEN_0 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51]
assign next_lrs1_rtype = _GEN_0 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51]
wire _GEN_1 = _GEN | ~_T_12 | p1; // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17]
assign next_lrs2_rtype = _GEN_1 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17] |
Generate the Verilog code corresponding to this FIRRTL code module SourceC_6 :
input clock : Clock
input reset : Reset
output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<9>, set : UInt<11>, way : UInt<4>, dirty : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, bs_adr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<4>, set : UInt<11>, beat : UInt<3>, mask : UInt<1>}}, flip bs_dat : { data : UInt<64>}, evict_req : { set : UInt<11>, way : UInt<4>}, flip evict_safe : UInt<1>}
inst queue of Queue12_TLBundleC_a32d64s4k3z3c_6
connect queue.clock, clock
connect queue.reset, reset
regreset fill : UInt<4>, clock, reset, UInt<4>(0h0)
regreset room : UInt<1>, clock, reset, UInt<1>(0h1)
node _T = and(queue.io.enq.ready, queue.io.enq.valid)
node _T_1 = and(queue.io.deq.ready, queue.io.deq.valid)
node _T_2 = neq(_T, _T_1)
when _T_2 :
node _fill_T = and(queue.io.enq.ready, queue.io.enq.valid)
node _fill_T_1 = not(UInt<4>(0h0))
node _fill_T_2 = mux(_fill_T, UInt<1>(0h1), _fill_T_1)
node _fill_T_3 = add(fill, _fill_T_2)
node _fill_T_4 = tail(_fill_T_3, 1)
connect fill, _fill_T_4
node _room_T = eq(fill, UInt<1>(0h0))
node _room_T_1 = eq(fill, UInt<1>(0h1))
node _room_T_2 = eq(fill, UInt<2>(0h2))
node _room_T_3 = or(_room_T_1, _room_T_2)
node _room_T_4 = and(queue.io.enq.ready, queue.io.enq.valid)
node _room_T_5 = eq(_room_T_4, UInt<1>(0h0))
node _room_T_6 = and(_room_T_3, _room_T_5)
node _room_T_7 = or(_room_T, _room_T_6)
connect room, _room_T_7
node _T_3 = leq(queue.io.count, UInt<1>(0h1))
node _T_4 = eq(room, _T_3)
node _T_5 = asUInt(reset)
node _T_6 = eq(_T_5, UInt<1>(0h0))
when _T_6 :
node _T_7 = eq(_T_4, UInt<1>(0h0))
when _T_7 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at SourceC.scala:64 assert (room === queue.io.count <= 1.U)\n") : printf
assert(clock, _T_4, UInt<1>(0h1), "") : assert
regreset busy : UInt<1>, clock, reset, UInt<1>(0h0)
regreset beat : UInt<3>, clock, reset, UInt<3>(0h0)
node _last_T = not(UInt<3>(0h0))
node last = eq(beat, _last_T)
node _req_T = eq(busy, UInt<1>(0h0))
node _req_T_1 = eq(busy, UInt<1>(0h0))
node _req_T_2 = and(_req_T_1, io.req.valid)
reg req_r : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<9>, set : UInt<11>, way : UInt<4>, dirty : UInt<1>}, clock
when _req_T_2 :
connect req_r, io.req.bits
node req = mux(_req_T, io.req.bits, req_r)
node _want_data_T = and(io.req.valid, room)
node _want_data_T_1 = and(_want_data_T, io.req.bits.dirty)
node want_data = or(busy, _want_data_T_1)
node _io_req_ready_T = eq(busy, UInt<1>(0h0))
node _io_req_ready_T_1 = and(_io_req_ready_T, room)
connect io.req.ready, _io_req_ready_T_1
connect io.evict_req.set, req.set
connect io.evict_req.way, req.way
node _io_bs_adr_valid_T = orr(beat)
node _io_bs_adr_valid_T_1 = or(_io_bs_adr_valid_T, io.evict_safe)
node _io_bs_adr_valid_T_2 = and(_io_bs_adr_valid_T_1, want_data)
connect io.bs_adr.valid, _io_bs_adr_valid_T_2
connect io.bs_adr.bits.noop, UInt<1>(0h0)
connect io.bs_adr.bits.way, req.way
connect io.bs_adr.bits.set, req.set
connect io.bs_adr.bits.beat, beat
node _io_bs_adr_bits_mask_T = not(UInt<1>(0h0))
connect io.bs_adr.bits.mask, _io_bs_adr_bits_mask_T
node _T_8 = and(io.req.valid, io.req.bits.dirty)
node _T_9 = and(_T_8, room)
node _T_10 = eq(io.evict_safe, UInt<1>(0h0))
node _T_11 = and(_T_9, _T_10)
node _T_12 = eq(io.bs_adr.ready, UInt<1>(0h0))
node _T_13 = and(io.bs_adr.valid, _T_12)
node _T_14 = and(io.req.valid, room)
node _T_15 = and(_T_14, io.req.bits.dirty)
when _T_15 :
connect busy, UInt<1>(0h1)
node _T_16 = and(io.bs_adr.ready, io.bs_adr.valid)
when _T_16 :
node _beat_T = add(beat, UInt<1>(0h1))
node _beat_T_1 = tail(_beat_T, 1)
connect beat, _beat_T_1
when last :
connect busy, UInt<1>(0h0)
connect beat, UInt<1>(0h0)
node _s2_latch_T = and(io.bs_adr.ready, io.bs_adr.valid)
node _s2_latch_T_1 = and(io.req.ready, io.req.valid)
node s2_latch = mux(want_data, _s2_latch_T, _s2_latch_T_1)
reg s2_valid : UInt<1>, clock
connect s2_valid, s2_latch
reg s2_req : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<9>, set : UInt<11>, way : UInt<4>, dirty : UInt<1>}, clock
when s2_latch :
connect s2_req, req
reg s2_beat : UInt<3>, clock
when s2_latch :
connect s2_beat, beat
reg s2_last : UInt<1>, clock
when s2_latch :
connect s2_last, last
reg s3_valid : UInt<1>, clock
connect s3_valid, s2_valid
reg s3_req : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<9>, set : UInt<11>, way : UInt<4>, dirty : UInt<1>}, clock
when s2_valid :
connect s3_req, s2_req
reg s3_beat : UInt<3>, clock
when s2_valid :
connect s3_beat, s2_beat
reg s3_last : UInt<1>, clock
when s2_valid :
connect s3_last, s2_last
wire c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect c.valid, s3_valid
connect c.bits.opcode, s3_req.opcode
connect c.bits.param, s3_req.param
connect c.bits.size, UInt<3>(0h6)
connect c.bits.source, s3_req.source
node c_bits_address_base_y = or(s3_req.tag, UInt<9>(0h0))
node _c_bits_address_base_T = shr(c_bits_address_base_y, 9)
node _c_bits_address_base_T_1 = eq(_c_bits_address_base_T, UInt<1>(0h0))
node _c_bits_address_base_T_2 = asUInt(reset)
node _c_bits_address_base_T_3 = eq(_c_bits_address_base_T_2, UInt<1>(0h0))
when _c_bits_address_base_T_3 :
node _c_bits_address_base_T_4 = eq(_c_bits_address_base_T_1, UInt<1>(0h0))
when _c_bits_address_base_T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Parameters.scala:222 assert (y >> width === 0.U)\n") : c_bits_address_base_printf
assert(clock, _c_bits_address_base_T_1, UInt<1>(0h1), "") : c_bits_address_base_assert
node _c_bits_address_base_T_5 = bits(c_bits_address_base_y, 8, 0)
node c_bits_address_base_y_1 = or(s3_req.set, UInt<11>(0h0))
node _c_bits_address_base_T_6 = shr(c_bits_address_base_y_1, 11)
node _c_bits_address_base_T_7 = eq(_c_bits_address_base_T_6, UInt<1>(0h0))
node _c_bits_address_base_T_8 = asUInt(reset)
node _c_bits_address_base_T_9 = eq(_c_bits_address_base_T_8, UInt<1>(0h0))
when _c_bits_address_base_T_9 :
node _c_bits_address_base_T_10 = eq(_c_bits_address_base_T_7, UInt<1>(0h0))
when _c_bits_address_base_T_10 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Parameters.scala:222 assert (y >> width === 0.U)\n") : c_bits_address_base_printf_1
assert(clock, _c_bits_address_base_T_7, UInt<1>(0h1), "") : c_bits_address_base_assert_1
node _c_bits_address_base_T_11 = bits(c_bits_address_base_y_1, 10, 0)
node c_bits_address_base_y_2 = or(UInt<1>(0h0), UInt<6>(0h0))
node _c_bits_address_base_T_12 = shr(c_bits_address_base_y_2, 6)
node _c_bits_address_base_T_13 = eq(_c_bits_address_base_T_12, UInt<1>(0h0))
node _c_bits_address_base_T_14 = asUInt(reset)
node _c_bits_address_base_T_15 = eq(_c_bits_address_base_T_14, UInt<1>(0h0))
when _c_bits_address_base_T_15 :
node _c_bits_address_base_T_16 = eq(_c_bits_address_base_T_13, UInt<1>(0h0))
when _c_bits_address_base_T_16 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Parameters.scala:222 assert (y >> width === 0.U)\n") : c_bits_address_base_printf_2
assert(clock, _c_bits_address_base_T_13, UInt<1>(0h1), "") : c_bits_address_base_assert_2
node _c_bits_address_base_T_17 = bits(c_bits_address_base_y_2, 5, 0)
node c_bits_address_base_hi = cat(_c_bits_address_base_T_5, _c_bits_address_base_T_11)
node c_bits_address_base = cat(c_bits_address_base_hi, _c_bits_address_base_T_17)
node _c_bits_address_T = bits(c_bits_address_base, 0, 0)
node _c_bits_address_T_1 = bits(c_bits_address_base, 1, 1)
node _c_bits_address_T_2 = bits(c_bits_address_base, 2, 2)
node _c_bits_address_T_3 = bits(c_bits_address_base, 3, 3)
node _c_bits_address_T_4 = bits(c_bits_address_base, 4, 4)
node _c_bits_address_T_5 = bits(c_bits_address_base, 5, 5)
node _c_bits_address_T_6 = bits(c_bits_address_base, 6, 6)
node _c_bits_address_T_7 = bits(c_bits_address_base, 7, 7)
node _c_bits_address_T_8 = bits(c_bits_address_base, 8, 8)
node _c_bits_address_T_9 = bits(c_bits_address_base, 9, 9)
node _c_bits_address_T_10 = bits(c_bits_address_base, 10, 10)
node _c_bits_address_T_11 = bits(c_bits_address_base, 11, 11)
node _c_bits_address_T_12 = bits(c_bits_address_base, 12, 12)
node _c_bits_address_T_13 = bits(c_bits_address_base, 13, 13)
node _c_bits_address_T_14 = bits(c_bits_address_base, 14, 14)
node _c_bits_address_T_15 = bits(c_bits_address_base, 15, 15)
node _c_bits_address_T_16 = bits(c_bits_address_base, 16, 16)
node _c_bits_address_T_17 = bits(c_bits_address_base, 17, 17)
node _c_bits_address_T_18 = bits(c_bits_address_base, 18, 18)
node _c_bits_address_T_19 = bits(c_bits_address_base, 19, 19)
node _c_bits_address_T_20 = bits(c_bits_address_base, 20, 20)
node _c_bits_address_T_21 = bits(c_bits_address_base, 21, 21)
node _c_bits_address_T_22 = bits(c_bits_address_base, 22, 22)
node _c_bits_address_T_23 = bits(c_bits_address_base, 23, 23)
node _c_bits_address_T_24 = bits(c_bits_address_base, 24, 24)
node _c_bits_address_T_25 = bits(c_bits_address_base, 25, 25)
node c_bits_address_lo_lo_lo_lo = cat(_c_bits_address_T_1, _c_bits_address_T)
node c_bits_address_lo_lo_lo_hi = cat(_c_bits_address_T_3, _c_bits_address_T_2)
node c_bits_address_lo_lo_lo = cat(c_bits_address_lo_lo_lo_hi, c_bits_address_lo_lo_lo_lo)
node c_bits_address_lo_lo_hi_lo = cat(_c_bits_address_T_5, _c_bits_address_T_4)
node c_bits_address_lo_lo_hi_hi = cat(UInt<1>(0h0), UInt<1>(0h0))
node c_bits_address_lo_lo_hi = cat(c_bits_address_lo_lo_hi_hi, c_bits_address_lo_lo_hi_lo)
node c_bits_address_lo_lo = cat(c_bits_address_lo_lo_hi, c_bits_address_lo_lo_lo)
node c_bits_address_lo_hi_lo_lo = cat(_c_bits_address_T_6, UInt<1>(0h0))
node c_bits_address_lo_hi_lo_hi = cat(_c_bits_address_T_8, _c_bits_address_T_7)
node c_bits_address_lo_hi_lo = cat(c_bits_address_lo_hi_lo_hi, c_bits_address_lo_hi_lo_lo)
node c_bits_address_lo_hi_hi_lo = cat(_c_bits_address_T_10, _c_bits_address_T_9)
node c_bits_address_lo_hi_hi_hi = cat(_c_bits_address_T_12, _c_bits_address_T_11)
node c_bits_address_lo_hi_hi = cat(c_bits_address_lo_hi_hi_hi, c_bits_address_lo_hi_hi_lo)
node c_bits_address_lo_hi = cat(c_bits_address_lo_hi_hi, c_bits_address_lo_hi_lo)
node c_bits_address_lo = cat(c_bits_address_lo_hi, c_bits_address_lo_lo)
node c_bits_address_hi_lo_lo_lo = cat(_c_bits_address_T_14, _c_bits_address_T_13)
node c_bits_address_hi_lo_lo_hi = cat(_c_bits_address_T_16, _c_bits_address_T_15)
node c_bits_address_hi_lo_lo = cat(c_bits_address_hi_lo_lo_hi, c_bits_address_hi_lo_lo_lo)
node c_bits_address_hi_lo_hi_lo = cat(_c_bits_address_T_18, _c_bits_address_T_17)
node c_bits_address_hi_lo_hi_hi = cat(_c_bits_address_T_20, _c_bits_address_T_19)
node c_bits_address_hi_lo_hi = cat(c_bits_address_hi_lo_hi_hi, c_bits_address_hi_lo_hi_lo)
node c_bits_address_hi_lo = cat(c_bits_address_hi_lo_hi, c_bits_address_hi_lo_lo)
node c_bits_address_hi_hi_lo_lo = cat(_c_bits_address_T_22, _c_bits_address_T_21)
node c_bits_address_hi_hi_lo_hi = cat(_c_bits_address_T_24, _c_bits_address_T_23)
node c_bits_address_hi_hi_lo = cat(c_bits_address_hi_hi_lo_hi, c_bits_address_hi_hi_lo_lo)
node c_bits_address_hi_hi_hi_lo = cat(UInt<1>(0h0), UInt<1>(0h0))
node c_bits_address_hi_hi_hi_hi = cat(_c_bits_address_T_25, UInt<1>(0h0))
node c_bits_address_hi_hi_hi = cat(c_bits_address_hi_hi_hi_hi, c_bits_address_hi_hi_hi_lo)
node c_bits_address_hi_hi = cat(c_bits_address_hi_hi_hi, c_bits_address_hi_hi_lo)
node c_bits_address_hi = cat(c_bits_address_hi_hi, c_bits_address_hi_lo)
node _c_bits_address_T_26 = cat(c_bits_address_hi, c_bits_address_lo)
connect c.bits.address, _c_bits_address_T_26
connect c.bits.data, io.bs_dat.data
connect c.bits.corrupt, UInt<1>(0h0)
node _T_17 = eq(c.valid, UInt<1>(0h0))
node _T_18 = or(_T_17, c.ready)
node _T_19 = asUInt(reset)
node _T_20 = eq(_T_19, UInt<1>(0h0))
when _T_20 :
node _T_21 = eq(_T_18, UInt<1>(0h0))
when _T_21 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at SourceC.scala:119 assert(!c.valid || c.ready)\n") : printf_1
assert(clock, _T_18, UInt<1>(0h1), "") : assert_1
node _T_22 = eq(c.ready, UInt<1>(0h0))
connect queue.io.enq, c
connect io.c.bits, queue.io.deq.bits
connect io.c.valid, queue.io.deq.valid
connect queue.io.deq.ready, io.c.ready | module SourceC_6( // @[SourceC.scala:35:7]
input clock, // @[SourceC.scala:35:7]
input reset, // @[SourceC.scala:35:7]
output io_req_ready, // @[SourceC.scala:37:14]
input io_req_valid, // @[SourceC.scala:37:14]
input [2:0] io_req_bits_opcode, // @[SourceC.scala:37:14]
input [2:0] io_req_bits_param, // @[SourceC.scala:37:14]
input [3:0] io_req_bits_source, // @[SourceC.scala:37:14]
input [8:0] io_req_bits_tag, // @[SourceC.scala:37:14]
input [10:0] io_req_bits_set, // @[SourceC.scala:37:14]
input [3:0] io_req_bits_way, // @[SourceC.scala:37:14]
input io_req_bits_dirty, // @[SourceC.scala:37:14]
input io_c_ready, // @[SourceC.scala:37:14]
output io_c_valid, // @[SourceC.scala:37:14]
output [2:0] io_c_bits_opcode, // @[SourceC.scala:37:14]
output [2:0] io_c_bits_param, // @[SourceC.scala:37:14]
output [2:0] io_c_bits_size, // @[SourceC.scala:37:14]
output [3:0] io_c_bits_source, // @[SourceC.scala:37:14]
output [31:0] io_c_bits_address, // @[SourceC.scala:37:14]
output [63:0] io_c_bits_data, // @[SourceC.scala:37:14]
output io_c_bits_corrupt, // @[SourceC.scala:37:14]
input io_bs_adr_ready, // @[SourceC.scala:37:14]
output io_bs_adr_valid, // @[SourceC.scala:37:14]
output [3:0] io_bs_adr_bits_way, // @[SourceC.scala:37:14]
output [10:0] io_bs_adr_bits_set, // @[SourceC.scala:37:14]
output [2:0] io_bs_adr_bits_beat, // @[SourceC.scala:37:14]
input [63:0] io_bs_dat_data, // @[SourceC.scala:37:14]
output [10:0] io_evict_req_set, // @[SourceC.scala:37:14]
output [3:0] io_evict_req_way, // @[SourceC.scala:37:14]
input io_evict_safe // @[SourceC.scala:37:14]
);
wire _queue_io_enq_ready; // @[SourceC.scala:54:21]
wire _queue_io_deq_valid; // @[SourceC.scala:54:21]
wire [3:0] _queue_io_count; // @[SourceC.scala:54:21]
wire io_req_valid_0 = io_req_valid; // @[SourceC.scala:35:7]
wire [2:0] io_req_bits_opcode_0 = io_req_bits_opcode; // @[SourceC.scala:35:7]
wire [2:0] io_req_bits_param_0 = io_req_bits_param; // @[SourceC.scala:35:7]
wire [3:0] io_req_bits_source_0 = io_req_bits_source; // @[SourceC.scala:35:7]
wire [8:0] io_req_bits_tag_0 = io_req_bits_tag; // @[SourceC.scala:35:7]
wire [10:0] io_req_bits_set_0 = io_req_bits_set; // @[SourceC.scala:35:7]
wire [3:0] io_req_bits_way_0 = io_req_bits_way; // @[SourceC.scala:35:7]
wire io_req_bits_dirty_0 = io_req_bits_dirty; // @[SourceC.scala:35:7]
wire io_c_ready_0 = io_c_ready; // @[SourceC.scala:35:7]
wire io_bs_adr_ready_0 = io_bs_adr_ready; // @[SourceC.scala:35:7]
wire [63:0] io_bs_dat_data_0 = io_bs_dat_data; // @[SourceC.scala:35:7]
wire io_evict_safe_0 = io_evict_safe; // @[SourceC.scala:35:7]
wire _c_bits_address_base_T_2 = reset; // @[Parameters.scala:222:12]
wire _c_bits_address_base_T_8 = reset; // @[Parameters.scala:222:12]
wire _c_bits_address_base_T_14 = reset; // @[Parameters.scala:222:12]
wire io_bs_adr_bits_noop = 1'h0; // @[SourceC.scala:35:7]
wire c_bits_corrupt = 1'h0; // @[SourceC.scala:108:15]
wire _c_bits_address_base_T = 1'h0; // @[Parameters.scala:222:15]
wire _c_bits_address_base_T_4 = 1'h0; // @[Parameters.scala:222:12]
wire _c_bits_address_base_T_6 = 1'h0; // @[Parameters.scala:222:15]
wire _c_bits_address_base_T_10 = 1'h0; // @[Parameters.scala:222:12]
wire _c_bits_address_base_T_12 = 1'h0; // @[Parameters.scala:222:15]
wire _c_bits_address_base_T_16 = 1'h0; // @[Parameters.scala:222:12]
wire io_bs_adr_bits_mask = 1'h1; // @[SourceC.scala:35:7]
wire _io_bs_adr_bits_mask_T = 1'h1; // @[SourceC.scala:82:26]
wire _c_bits_address_base_T_1 = 1'h1; // @[Parameters.scala:222:24]
wire _c_bits_address_base_T_7 = 1'h1; // @[Parameters.scala:222:24]
wire _c_bits_address_base_T_13 = 1'h1; // @[Parameters.scala:222:24]
wire [1:0] c_bits_address_lo_lo_hi_hi = 2'h0; // @[Parameters.scala:230:8]
wire [1:0] c_bits_address_hi_hi_hi_lo = 2'h0; // @[Parameters.scala:230:8]
wire [5:0] c_bits_address_base_y_2 = 6'h0; // @[Parameters.scala:221:15]
wire [5:0] _c_bits_address_base_T_17 = 6'h0; // @[Parameters.scala:223:6]
wire [2:0] c_bits_size = 3'h6; // @[SourceC.scala:108:15]
wire [2:0] _last_T = 3'h7; // @[SourceC.scala:68:99]
wire [3:0] _fill_T_1 = 4'hF; // @[SourceC.scala:61:48]
wire _io_req_ready_T_1; // @[SourceC.scala:72:25]
wire _io_bs_adr_valid_T_2; // @[SourceC.scala:77:50]
wire [3:0] req_way; // @[SourceC.scala:69:17]
wire [10:0] req_set; // @[SourceC.scala:69:17]
wire [63:0] c_bits_data = io_bs_dat_data_0; // @[SourceC.scala:35:7, :108:15]
wire io_req_ready_0; // @[SourceC.scala:35:7]
wire [2:0] io_c_bits_opcode_0; // @[SourceC.scala:35:7]
wire [2:0] io_c_bits_param_0; // @[SourceC.scala:35:7]
wire [2:0] io_c_bits_size_0; // @[SourceC.scala:35:7]
wire [3:0] io_c_bits_source_0; // @[SourceC.scala:35:7]
wire [31:0] io_c_bits_address_0; // @[SourceC.scala:35:7]
wire [63:0] io_c_bits_data_0; // @[SourceC.scala:35:7]
wire io_c_bits_corrupt_0; // @[SourceC.scala:35:7]
wire io_c_valid_0; // @[SourceC.scala:35:7]
wire [3:0] io_bs_adr_bits_way_0; // @[SourceC.scala:35:7]
wire [10:0] io_bs_adr_bits_set_0; // @[SourceC.scala:35:7]
wire [2:0] io_bs_adr_bits_beat_0; // @[SourceC.scala:35:7]
wire io_bs_adr_valid_0; // @[SourceC.scala:35:7]
wire [10:0] io_evict_req_set_0; // @[SourceC.scala:35:7]
wire [3:0] io_evict_req_way_0; // @[SourceC.scala:35:7]
reg [3:0] fill; // @[SourceC.scala:58:21]
reg room; // @[SourceC.scala:59:21]
wire c_valid; // @[SourceC.scala:108:15]
wire _T = _queue_io_enq_ready & c_valid; // @[Decoupled.scala:51:35]
wire _fill_T; // @[Decoupled.scala:51:35]
assign _fill_T = _T; // @[Decoupled.scala:51:35]
wire _room_T_4; // @[Decoupled.scala:51:35]
assign _room_T_4 = _T; // @[Decoupled.scala:51:35]
wire [3:0] _fill_T_2 = _fill_T ? 4'h1 : 4'hF; // @[Decoupled.scala:51:35]
wire [4:0] _fill_T_3 = {1'h0, fill} + {1'h0, _fill_T_2}; // @[SourceC.scala:58:21, :61:{18,23}]
wire [3:0] _fill_T_4 = _fill_T_3[3:0]; // @[SourceC.scala:61:18]
wire _room_T = fill == 4'h0; // @[SourceC.scala:58:21, :62:18]
wire _room_T_1 = fill == 4'h1; // @[SourceC.scala:58:21, :62:36]
wire _room_T_2 = fill == 4'h2; // @[SourceC.scala:58:21, :62:52]
wire _room_T_3 = _room_T_1 | _room_T_2; // @[SourceC.scala:62:{36,44,52}]
wire _room_T_5 = ~_room_T_4; // @[Decoupled.scala:51:35]
wire _room_T_6 = _room_T_3 & _room_T_5; // @[SourceC.scala:62:{44,61,64}]
wire _room_T_7 = _room_T | _room_T_6; // @[SourceC.scala:62:{18,26,61}]
reg busy; // @[SourceC.scala:66:21]
reg [2:0] beat; // @[SourceC.scala:67:21]
assign io_bs_adr_bits_beat_0 = beat; // @[SourceC.scala:35:7, :67:21]
wire last = &beat; // @[SourceC.scala:67:21, :68:95]
wire _req_T = ~busy; // @[SourceC.scala:66:21, :69:18]
wire _req_T_1 = ~busy; // @[SourceC.scala:66:21, :69:{18,61}]
wire _req_T_2 = _req_T_1 & io_req_valid_0; // @[SourceC.scala:35:7, :69:{61,67}]
reg [2:0] req_r_opcode; // @[SourceC.scala:69:47]
reg [2:0] req_r_param; // @[SourceC.scala:69:47]
reg [3:0] req_r_source; // @[SourceC.scala:69:47]
reg [8:0] req_r_tag; // @[SourceC.scala:69:47]
reg [10:0] req_r_set; // @[SourceC.scala:69:47]
reg [3:0] req_r_way; // @[SourceC.scala:69:47]
reg req_r_dirty; // @[SourceC.scala:69:47]
wire [2:0] req_opcode = _req_T ? io_req_bits_opcode_0 : req_r_opcode; // @[SourceC.scala:35:7, :69:{17,18,47}]
wire [2:0] req_param = _req_T ? io_req_bits_param_0 : req_r_param; // @[SourceC.scala:35:7, :69:{17,18,47}]
wire [3:0] req_source = _req_T ? io_req_bits_source_0 : req_r_source; // @[SourceC.scala:35:7, :69:{17,18,47}]
wire [8:0] req_tag = _req_T ? io_req_bits_tag_0 : req_r_tag; // @[SourceC.scala:35:7, :69:{17,18,47}]
assign req_set = _req_T ? io_req_bits_set_0 : req_r_set; // @[SourceC.scala:35:7, :69:{17,18,47}]
assign req_way = _req_T ? io_req_bits_way_0 : req_r_way; // @[SourceC.scala:35:7, :69:{17,18,47}]
wire req_dirty = _req_T ? io_req_bits_dirty_0 : req_r_dirty; // @[SourceC.scala:35:7, :69:{17,18,47}]
assign io_bs_adr_bits_set_0 = req_set; // @[SourceC.scala:35:7, :69:17]
assign io_evict_req_set_0 = req_set; // @[SourceC.scala:35:7, :69:17]
assign io_bs_adr_bits_way_0 = req_way; // @[SourceC.scala:35:7, :69:17]
assign io_evict_req_way_0 = req_way; // @[SourceC.scala:35:7, :69:17]
wire _want_data_T = io_req_valid_0 & room; // @[SourceC.scala:35:7, :59:21, :70:41]
wire _want_data_T_1 = _want_data_T & io_req_bits_dirty_0; // @[SourceC.scala:35:7, :70:{41,49}]
wire want_data = busy | _want_data_T_1; // @[SourceC.scala:66:21, :70:{24,49}]
wire _io_req_ready_T = ~busy; // @[SourceC.scala:66:21, :69:18, :72:19]
assign _io_req_ready_T_1 = _io_req_ready_T & room; // @[SourceC.scala:59:21, :72:{19,25}]
assign io_req_ready_0 = _io_req_ready_T_1; // @[SourceC.scala:35:7, :72:25]
wire _io_bs_adr_valid_T = |beat; // @[SourceC.scala:67:21, :77:28]
wire _io_bs_adr_valid_T_1 = _io_bs_adr_valid_T | io_evict_safe_0; // @[SourceC.scala:35:7, :77:{28,32}]
assign _io_bs_adr_valid_T_2 = _io_bs_adr_valid_T_1 & want_data; // @[SourceC.scala:70:24, :77:{32,50}]
assign io_bs_adr_valid_0 = _io_bs_adr_valid_T_2; // @[SourceC.scala:35:7, :77:50]
wire _s2_latch_T = io_bs_adr_ready_0 & io_bs_adr_valid_0; // @[Decoupled.scala:51:35]
wire [3:0] _beat_T = {1'h0, beat} + 4'h1; // @[SourceC.scala:67:21, :89:18]
wire [2:0] _beat_T_1 = _beat_T[2:0]; // @[SourceC.scala:89:18]
wire _s2_latch_T_1 = io_req_ready_0 & io_req_valid_0; // @[Decoupled.scala:51:35]
wire s2_latch = want_data ? _s2_latch_T : _s2_latch_T_1; // @[Decoupled.scala:51:35]
reg s2_valid; // @[SourceC.scala:97:25]
reg [2:0] s2_req_opcode; // @[SourceC.scala:98:25]
reg [2:0] s2_req_param; // @[SourceC.scala:98:25]
reg [3:0] s2_req_source; // @[SourceC.scala:98:25]
reg [8:0] s2_req_tag; // @[SourceC.scala:98:25]
reg [10:0] s2_req_set; // @[SourceC.scala:98:25]
reg [3:0] s2_req_way; // @[SourceC.scala:98:25]
reg s2_req_dirty; // @[SourceC.scala:98:25]
reg [2:0] s2_beat; // @[SourceC.scala:99:26]
reg s2_last; // @[SourceC.scala:100:26]
reg s3_valid; // @[SourceC.scala:103:25]
assign c_valid = s3_valid; // @[SourceC.scala:103:25, :108:15]
reg [2:0] s3_req_opcode; // @[SourceC.scala:104:25]
wire [2:0] c_bits_opcode = s3_req_opcode; // @[SourceC.scala:104:25, :108:15]
reg [2:0] s3_req_param; // @[SourceC.scala:104:25]
wire [2:0] c_bits_param = s3_req_param; // @[SourceC.scala:104:25, :108:15]
reg [3:0] s3_req_source; // @[SourceC.scala:104:25]
wire [3:0] c_bits_source = s3_req_source; // @[SourceC.scala:104:25, :108:15]
reg [8:0] s3_req_tag; // @[SourceC.scala:104:25]
wire [8:0] c_bits_address_base_y = s3_req_tag; // @[SourceC.scala:104:25]
reg [10:0] s3_req_set; // @[SourceC.scala:104:25]
wire [10:0] c_bits_address_base_y_1 = s3_req_set; // @[SourceC.scala:104:25]
reg [3:0] s3_req_way; // @[SourceC.scala:104:25]
reg s3_req_dirty; // @[SourceC.scala:104:25]
reg [2:0] s3_beat; // @[SourceC.scala:105:26]
reg s3_last; // @[SourceC.scala:106:26]
wire [31:0] _c_bits_address_T_26; // @[Parameters.scala:230:8]
wire [31:0] c_bits_address; // @[SourceC.scala:108:15]
wire c_ready; // @[SourceC.scala:108:15]
wire [8:0] _c_bits_address_base_T_5 = c_bits_address_base_y; // @[Parameters.scala:221:15, :223:6]
wire _c_bits_address_base_T_3 = ~_c_bits_address_base_T_2; // @[Parameters.scala:222:12]
wire [10:0] _c_bits_address_base_T_11 = c_bits_address_base_y_1; // @[Parameters.scala:221:15, :223:6]
wire _c_bits_address_base_T_9 = ~_c_bits_address_base_T_8; // @[Parameters.scala:222:12]
wire _c_bits_address_base_T_15 = ~_c_bits_address_base_T_14; // @[Parameters.scala:222:12]
wire [19:0] c_bits_address_base_hi = {_c_bits_address_base_T_5, _c_bits_address_base_T_11}; // @[Parameters.scala:223:6, :227:19]
wire [25:0] c_bits_address_base = {c_bits_address_base_hi, 6'h0}; // @[Parameters.scala:227:19]
wire _c_bits_address_T = c_bits_address_base[0]; // @[Parameters.scala:227:19, :229:72]
wire _c_bits_address_T_1 = c_bits_address_base[1]; // @[Parameters.scala:227:19, :229:72]
wire _c_bits_address_T_2 = c_bits_address_base[2]; // @[Parameters.scala:227:19, :229:72]
wire _c_bits_address_T_3 = c_bits_address_base[3]; // @[Parameters.scala:227:19, :229:72]
wire _c_bits_address_T_4 = c_bits_address_base[4]; // @[Parameters.scala:227:19, :229:72]
wire _c_bits_address_T_5 = c_bits_address_base[5]; // @[Parameters.scala:227:19, :229:72]
wire _c_bits_address_T_6 = c_bits_address_base[6]; // @[Parameters.scala:227:19, :229:72]
wire _c_bits_address_T_7 = c_bits_address_base[7]; // @[Parameters.scala:227:19, :229:72]
wire _c_bits_address_T_8 = c_bits_address_base[8]; // @[Parameters.scala:227:19, :229:72]
wire _c_bits_address_T_9 = c_bits_address_base[9]; // @[Parameters.scala:227:19, :229:72]
wire _c_bits_address_T_10 = c_bits_address_base[10]; // @[Parameters.scala:227:19, :229:72]
wire _c_bits_address_T_11 = c_bits_address_base[11]; // @[Parameters.scala:227:19, :229:72]
wire _c_bits_address_T_12 = c_bits_address_base[12]; // @[Parameters.scala:227:19, :229:72]
wire _c_bits_address_T_13 = c_bits_address_base[13]; // @[Parameters.scala:227:19, :229:72]
wire _c_bits_address_T_14 = c_bits_address_base[14]; // @[Parameters.scala:227:19, :229:72]
wire _c_bits_address_T_15 = c_bits_address_base[15]; // @[Parameters.scala:227:19, :229:72]
wire _c_bits_address_T_16 = c_bits_address_base[16]; // @[Parameters.scala:227:19, :229:72]
wire _c_bits_address_T_17 = c_bits_address_base[17]; // @[Parameters.scala:227:19, :229:72]
wire _c_bits_address_T_18 = c_bits_address_base[18]; // @[Parameters.scala:227:19, :229:72]
wire _c_bits_address_T_19 = c_bits_address_base[19]; // @[Parameters.scala:227:19, :229:72]
wire _c_bits_address_T_20 = c_bits_address_base[20]; // @[Parameters.scala:227:19, :229:72]
wire _c_bits_address_T_21 = c_bits_address_base[21]; // @[Parameters.scala:227:19, :229:72]
wire _c_bits_address_T_22 = c_bits_address_base[22]; // @[Parameters.scala:227:19, :229:72]
wire _c_bits_address_T_23 = c_bits_address_base[23]; // @[Parameters.scala:227:19, :229:72]
wire _c_bits_address_T_24 = c_bits_address_base[24]; // @[Parameters.scala:227:19, :229:72]
wire _c_bits_address_T_25 = c_bits_address_base[25]; // @[Parameters.scala:227:19, :229:72]
wire [1:0] c_bits_address_lo_lo_lo_lo = {_c_bits_address_T_1, _c_bits_address_T}; // @[Parameters.scala:229:72, :230:8]
wire [1:0] c_bits_address_lo_lo_lo_hi = {_c_bits_address_T_3, _c_bits_address_T_2}; // @[Parameters.scala:229:72, :230:8]
wire [3:0] c_bits_address_lo_lo_lo = {c_bits_address_lo_lo_lo_hi, c_bits_address_lo_lo_lo_lo}; // @[Parameters.scala:230:8]
wire [1:0] c_bits_address_lo_lo_hi_lo = {_c_bits_address_T_5, _c_bits_address_T_4}; // @[Parameters.scala:229:72, :230:8]
wire [3:0] c_bits_address_lo_lo_hi = {2'h0, c_bits_address_lo_lo_hi_lo}; // @[Parameters.scala:230:8]
wire [7:0] c_bits_address_lo_lo = {c_bits_address_lo_lo_hi, c_bits_address_lo_lo_lo}; // @[Parameters.scala:230:8]
wire [1:0] c_bits_address_lo_hi_lo_lo = {_c_bits_address_T_6, 1'h0}; // @[Parameters.scala:229:72, :230:8]
wire [1:0] c_bits_address_lo_hi_lo_hi = {_c_bits_address_T_8, _c_bits_address_T_7}; // @[Parameters.scala:229:72, :230:8]
wire [3:0] c_bits_address_lo_hi_lo = {c_bits_address_lo_hi_lo_hi, c_bits_address_lo_hi_lo_lo}; // @[Parameters.scala:230:8]
wire [1:0] c_bits_address_lo_hi_hi_lo = {_c_bits_address_T_10, _c_bits_address_T_9}; // @[Parameters.scala:229:72, :230:8]
wire [1:0] c_bits_address_lo_hi_hi_hi = {_c_bits_address_T_12, _c_bits_address_T_11}; // @[Parameters.scala:229:72, :230:8]
wire [3:0] c_bits_address_lo_hi_hi = {c_bits_address_lo_hi_hi_hi, c_bits_address_lo_hi_hi_lo}; // @[Parameters.scala:230:8]
wire [7:0] c_bits_address_lo_hi = {c_bits_address_lo_hi_hi, c_bits_address_lo_hi_lo}; // @[Parameters.scala:230:8]
wire [15:0] c_bits_address_lo = {c_bits_address_lo_hi, c_bits_address_lo_lo}; // @[Parameters.scala:230:8]
wire [1:0] c_bits_address_hi_lo_lo_lo = {_c_bits_address_T_14, _c_bits_address_T_13}; // @[Parameters.scala:229:72, :230:8]
wire [1:0] c_bits_address_hi_lo_lo_hi = {_c_bits_address_T_16, _c_bits_address_T_15}; // @[Parameters.scala:229:72, :230:8]
wire [3:0] c_bits_address_hi_lo_lo = {c_bits_address_hi_lo_lo_hi, c_bits_address_hi_lo_lo_lo}; // @[Parameters.scala:230:8]
wire [1:0] c_bits_address_hi_lo_hi_lo = {_c_bits_address_T_18, _c_bits_address_T_17}; // @[Parameters.scala:229:72, :230:8]
wire [1:0] c_bits_address_hi_lo_hi_hi = {_c_bits_address_T_20, _c_bits_address_T_19}; // @[Parameters.scala:229:72, :230:8]
wire [3:0] c_bits_address_hi_lo_hi = {c_bits_address_hi_lo_hi_hi, c_bits_address_hi_lo_hi_lo}; // @[Parameters.scala:230:8]
wire [7:0] c_bits_address_hi_lo = {c_bits_address_hi_lo_hi, c_bits_address_hi_lo_lo}; // @[Parameters.scala:230:8]
wire [1:0] c_bits_address_hi_hi_lo_lo = {_c_bits_address_T_22, _c_bits_address_T_21}; // @[Parameters.scala:229:72, :230:8]
wire [1:0] c_bits_address_hi_hi_lo_hi = {_c_bits_address_T_24, _c_bits_address_T_23}; // @[Parameters.scala:229:72, :230:8]
wire [3:0] c_bits_address_hi_hi_lo = {c_bits_address_hi_hi_lo_hi, c_bits_address_hi_hi_lo_lo}; // @[Parameters.scala:230:8]
wire [1:0] c_bits_address_hi_hi_hi_hi = {_c_bits_address_T_25, 1'h0}; // @[Parameters.scala:229:72, :230:8]
wire [3:0] c_bits_address_hi_hi_hi = {c_bits_address_hi_hi_hi_hi, 2'h0}; // @[Parameters.scala:230:8]
wire [7:0] c_bits_address_hi_hi = {c_bits_address_hi_hi_hi, c_bits_address_hi_hi_lo}; // @[Parameters.scala:230:8]
wire [15:0] c_bits_address_hi = {c_bits_address_hi_hi, c_bits_address_hi_lo}; // @[Parameters.scala:230:8]
assign _c_bits_address_T_26 = {c_bits_address_hi, c_bits_address_lo}; // @[Parameters.scala:230:8]
assign c_bits_address = _c_bits_address_T_26; // @[SourceC.scala:108:15] |
Generate the Verilog code corresponding to this FIRRTL code module MSHR_36 :
input clock : Clock
input reset : Reset
output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}}, status : { valid : UInt<1>, bits : { set : UInt<11>, tag : UInt<9>, way : UInt<4>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<9>, set : UInt<11>, param : UInt<3>, source : UInt<4>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<9>, set : UInt<11>, clients : UInt<1>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<9>, set : UInt<11>, way : UInt<4>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<11>, way : UInt<4>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<11>, tag : UInt<9>, source : UInt<6>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<4>}}, flip nestedwb : { set : UInt<11>, tag : UInt<9>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}}
regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>}, clock
regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}, clock
when meta_valid :
node _T = eq(meta.state, UInt<2>(0h0))
when _T :
node _T_1 = orr(meta.clients)
node _T_2 = eq(_T_1, UInt<1>(0h0))
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
node _T_6 = eq(meta.dirty, UInt<1>(0h0))
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1
assert(clock, _T_6, UInt<1>(0h1), "") : assert_1
node _T_10 = eq(meta.state, UInt<2>(0h1))
when _T_10 :
node _T_11 = eq(meta.dirty, UInt<1>(0h0))
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2
assert(clock, _T_11, UInt<1>(0h1), "") : assert_2
node _T_15 = eq(meta.state, UInt<2>(0h2))
when _T_15 :
node _T_16 = orr(meta.clients)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3
assert(clock, _T_16, UInt<1>(0h1), "") : assert_3
node _T_20 = sub(meta.clients, UInt<1>(0h1))
node _T_21 = tail(_T_20, 1)
node _T_22 = and(meta.clients, _T_21)
node _T_23 = eq(_T_22, UInt<1>(0h0))
node _T_24 = asUInt(reset)
node _T_25 = eq(_T_24, UInt<1>(0h0))
when _T_25 :
node _T_26 = eq(_T_23, UInt<1>(0h0))
when _T_26 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4
assert(clock, _T_23, UInt<1>(0h1), "") : assert_4
node _T_27 = eq(meta.state, UInt<2>(0h3))
when _T_27 :
skip
regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1)
reg sink : UInt<3>, clock
reg gotT : UInt<1>, clock
reg bad_grant : UInt<1>, clock
reg probes_done : UInt<1>, clock
reg probes_toN : UInt<1>, clock
reg probes_noT : UInt<1>, clock
node _T_28 = neq(meta.state, UInt<2>(0h0))
node _T_29 = and(meta_valid, _T_28)
node _T_30 = eq(io.nestedwb.set, request.set)
node _T_31 = and(_T_29, _T_30)
node _T_32 = eq(io.nestedwb.tag, meta.tag)
node _T_33 = and(_T_31, _T_32)
when _T_33 :
when io.nestedwb.b_clr_dirty :
connect meta.dirty, UInt<1>(0h0)
when io.nestedwb.c_set_dirty :
connect meta.dirty, UInt<1>(0h1)
when io.nestedwb.b_toB :
connect meta.state, UInt<2>(0h1)
when io.nestedwb.b_toN :
connect meta.hit, UInt<1>(0h0)
connect io.status.valid, request_valid
connect io.status.bits.set, request.set
connect io.status.bits.tag, request.tag
connect io.status.bits.way, meta.way
node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0))
node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0))
node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0))
node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2)
node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0))
node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4)
node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6)
node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7)
connect io.status.bits.blockB, _io_status_bits_blockB_T_8
node _io_status_bits_nestB_T = and(meta_valid, w_releaseack)
node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast)
node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast)
node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3)
connect io.status.bits.nestB, _io_status_bits_nestB_T_4
node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0))
connect io.status.bits.blockC, _io_status_bits_blockC_T
node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1)
node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3)
node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4)
connect io.status.bits.nestC, _io_status_bits_nestC_T_5
node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0))
node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0))
node _T_36 = or(_T_34, _T_35)
node _T_37 = asUInt(reset)
node _T_38 = eq(_T_37, UInt<1>(0h0))
when _T_38 :
node _T_39 = eq(_T_36, UInt<1>(0h0))
when _T_39 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB || !io.status.bits.blockB)\n") : printf_5
assert(clock, _T_36, UInt<1>(0h1), "") : assert_5
node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0))
node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0))
node _T_42 = or(_T_40, _T_41)
node _T_43 = asUInt(reset)
node _T_44 = eq(_T_43, UInt<1>(0h0))
when _T_44 :
node _T_45 = eq(_T_42, UInt<1>(0h0))
when _T_45 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC || !io.status.bits.blockC)\n") : printf_6
assert(clock, _T_42, UInt<1>(0h1), "") : assert_6
node _no_wait_T = and(w_rprobeacklast, w_releaseack)
node _no_wait_T_1 = and(_no_wait_T, w_grantlast)
node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast)
node no_wait = and(_no_wait_T_2, w_grantack)
node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0))
node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release)
node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe)
connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2
node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0))
node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1)
connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2
node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0))
node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst)
node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0))
node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst)
node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3)
connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4
node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0))
node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack)
node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant)
connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2
node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0))
node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst)
connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1
node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0))
node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack)
connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1
node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0))
node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst)
node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0))
node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait)
node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3)
connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4
connect io.schedule.bits.reload, no_wait
node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid)
node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid)
node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid)
node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid)
node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid)
node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid)
connect io.schedule.valid, _io_schedule_valid_T_5
when io.schedule.ready :
connect s_rprobe, UInt<1>(0h1)
when w_rprobeackfirst :
connect s_release, UInt<1>(0h1)
connect s_pprobe, UInt<1>(0h1)
node _T_46 = and(s_release, s_pprobe)
when _T_46 :
connect s_acquire, UInt<1>(0h1)
when w_releaseack :
connect s_flush, UInt<1>(0h1)
when w_pprobeackfirst :
connect s_probeack, UInt<1>(0h1)
when w_grantfirst :
connect s_grantack, UInt<1>(0h1)
node _T_47 = and(w_pprobeack, w_grant)
when _T_47 :
connect s_execute, UInt<1>(0h1)
when no_wait :
connect s_writeback, UInt<1>(0h1)
when no_wait :
connect request_valid, UInt<1>(0h0)
connect meta_valid, UInt<1>(0h0)
wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}
connect final_meta_writeback, meta
node req_clientBit = eq(request.source, UInt<6>(0h28))
node _req_needT_T = bits(request.opcode, 2, 2)
node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0))
node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5))
node _req_needT_T_3 = eq(request.param, UInt<1>(0h1))
node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3)
node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4)
node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6))
node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7))
node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7)
node _req_needT_T_9 = neq(request.param, UInt<2>(0h0))
node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9)
node req_needT = or(_req_needT_T_5, _req_needT_T_10)
node _req_acquire_T = eq(request.opcode, UInt<3>(0h6))
node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7))
node req_acquire = or(_req_acquire_T, _req_acquire_T_1)
node _meta_no_clients_T = orr(meta.clients)
node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0))
node _req_promoteT_T = eq(meta.state, UInt<2>(0h3))
node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T)
node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT)
node req_promoteT = and(req_acquire, _req_promoteT_T_2)
node _T_48 = and(request.prio[2], UInt<1>(0h1))
when _T_48 :
node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0)
node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T)
connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1
node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3))
node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2))
node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1)
node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state)
connect final_meta_writeback.state, _final_meta_writeback_state_T_3
node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1))
node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2))
node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1)
node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5))
node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3)
node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0))
node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5)
node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7
connect final_meta_writeback.hit, UInt<1>(0h1)
else :
node _T_49 = and(request.control, UInt<1>(0h1))
when _T_49 :
when meta.hit :
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h0)
node _final_meta_writeback_clients_T_8 = not(probes_toN)
node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9
connect final_meta_writeback.hit, UInt<1>(0h0)
else :
node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty)
node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2)
node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0))
node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4)
connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5
node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0))
node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1))
node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire)
node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state)
node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1))
node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state)
node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11)
node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state)
node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13)
node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15)
node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16)
connect final_meta_writeback.state, _final_meta_writeback_state_T_17
node _final_meta_writeback_clients_T_10 = not(probes_toN)
node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10)
node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0))
node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0))
node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14
connect final_meta_writeback.tag, request.tag
connect final_meta_writeback.hit, UInt<1>(0h1)
when bad_grant :
when meta.hit :
node _T_50 = eq(meta_valid, UInt<1>(0h0))
node _T_51 = eq(meta.state, UInt<2>(0h1))
node _T_52 = or(_T_50, _T_51)
node _T_53 = asUInt(reset)
node _T_54 = eq(_T_53, UInt<1>(0h0))
when _T_54 :
node _T_55 = eq(_T_52, UInt<1>(0h0))
when _T_55 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid || meta.state === BRANCH)\n") : printf_7
assert(clock, _T_52, UInt<1>(0h1), "") : assert_7
connect final_meta_writeback.hit, UInt<1>(0h1)
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h1)
node _final_meta_writeback_clients_T_15 = not(probes_toN)
node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16
else :
connect final_meta_writeback.hit, UInt<1>(0h0)
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h0)
connect final_meta_writeback.clients, UInt<1>(0h0)
wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}
connect invalid.dirty, UInt<1>(0h0)
connect invalid.state, UInt<2>(0h0)
connect invalid.clients, UInt<1>(0h0)
connect invalid.tag, UInt<1>(0h0)
node _honour_BtoT_T = and(meta.clients, req_clientBit)
node _honour_BtoT_T_1 = orr(_honour_BtoT_T)
node honour_BtoT = and(meta.hit, _honour_BtoT_T_1)
node _excluded_client_T = and(meta.hit, request.prio[0])
node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6))
node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7))
node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2)
node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4))
node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4)
node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5))
node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0))
node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7)
node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8)
node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0))
connect io.schedule.bits.a.bits.tag, request.tag
connect io.schedule.bits.a.bits.set, request.set
node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0))
connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1
node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6))
node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0))
node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7))
node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2)
node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0))
node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4)
connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5
connect io.schedule.bits.a.bits.source, UInt<1>(0h0)
node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1)
node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2)
connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3
node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag)
connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1
connect io.schedule.bits.b.bits.set, request.set
node _io_schedule_bits_b_bits_clients_T = not(excluded_client)
node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T)
connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1
node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6))
connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T
node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1))
node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1))
connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1
connect io.schedule.bits.c.bits.source, UInt<1>(0h0)
connect io.schedule.bits.c.bits.tag, meta.tag
connect io.schedule.bits.c.bits.set, request.set
connect io.schedule.bits.c.bits.way, meta.way
connect io.schedule.bits.c.bits.dirty, meta.dirty
connect io.schedule.bits.d.bits.set, request.set
connect io.schedule.bits.d.bits.put, request.put
connect io.schedule.bits.d.bits.offset, request.offset
connect io.schedule.bits.d.bits.tag, request.tag
connect io.schedule.bits.d.bits.source, request.source
connect io.schedule.bits.d.bits.size, request.size
connect io.schedule.bits.d.bits.param, request.param
connect io.schedule.bits.d.bits.opcode, request.opcode
connect io.schedule.bits.d.bits.control, request.control
connect io.schedule.bits.d.bits.prio, request.prio
node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0))
node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0))
node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param)
node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param)
node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param)
node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4)
node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param)
node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6)
node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8)
connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9
connect io.schedule.bits.d.bits.sink, UInt<1>(0h0)
connect io.schedule.bits.d.bits.way, meta.way
connect io.schedule.bits.d.bits.bad, bad_grant
connect io.schedule.bits.e.bits.sink, sink
connect io.schedule.bits.x.bits.fail, UInt<1>(0h0)
connect io.schedule.bits.dir.bits.set, request.set
connect io.schedule.bits.dir.bits.way, meta.way
node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0))
wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}
connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag
connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients
connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state
connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty
node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE)
connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1
node _evict_T = eq(meta.hit, UInt<1>(0h0))
wire evict : UInt
connect evict, UInt<1>(0h0)
node evict_c = orr(meta.clients)
node _evict_T_1 = eq(UInt<2>(0h1), meta.state)
when _evict_T_1 :
node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1))
connect evict, _evict_out_T
else :
node _evict_T_2 = eq(UInt<2>(0h2), meta.state)
when _evict_T_2 :
node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect evict, _evict_out_T_1
else :
node _evict_T_3 = eq(UInt<2>(0h3), meta.state)
when _evict_T_3 :
node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3)
connect evict, _evict_out_T_4
else :
node _evict_T_4 = eq(UInt<2>(0h0), meta.state)
when _evict_T_4 :
connect evict, UInt<4>(0h8)
node _evict_T_5 = eq(_evict_T, UInt<1>(0h0))
when _evict_T_5 :
connect evict, UInt<4>(0h8)
wire before : UInt
connect before, UInt<1>(0h0)
node before_c = orr(meta.clients)
node _before_T = eq(UInt<2>(0h1), meta.state)
when _before_T :
node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1))
connect before, _before_out_T
else :
node _before_T_1 = eq(UInt<2>(0h2), meta.state)
when _before_T_1 :
node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect before, _before_out_T_1
else :
node _before_T_2 = eq(UInt<2>(0h3), meta.state)
when _before_T_2 :
node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3)
connect before, _before_out_T_4
else :
node _before_T_3 = eq(UInt<2>(0h0), meta.state)
when _before_T_3 :
connect before, UInt<4>(0h8)
node _before_T_4 = eq(meta.hit, UInt<1>(0h0))
when _before_T_4 :
connect before, UInt<4>(0h8)
wire after : UInt
connect after, UInt<1>(0h0)
node after_c = orr(final_meta_writeback.clients)
node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state)
when _after_T :
node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1))
connect after, _after_out_T
else :
node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state)
when _after_T_1 :
node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect after, _after_out_T_1
else :
node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state)
when _after_T_2 :
node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3)
connect after, _after_out_T_4
else :
node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state)
when _after_T_3 :
connect after, UInt<4>(0h8)
node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0))
when _after_T_4 :
connect after, UInt<4>(0h8)
node _T_56 = eq(s_release, UInt<1>(0h0))
node _T_57 = and(_T_56, w_rprobeackfirst)
node _T_58 = and(_T_57, io.schedule.ready)
when _T_58 :
node _T_59 = eq(evict, UInt<1>(0h1))
node _T_60 = eq(_T_59, UInt<1>(0h0))
node _T_61 = asUInt(reset)
node _T_62 = eq(_T_61, UInt<1>(0h0))
when _T_62 :
node _T_63 = eq(_T_60, UInt<1>(0h0))
when _T_63 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8
assert(clock, _T_60, UInt<1>(0h1), "") : assert_8
node _T_64 = eq(before, UInt<1>(0h1))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(_T_65, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9
assert(clock, _T_65, UInt<1>(0h1), "") : assert_9
node _T_69 = eq(evict, UInt<1>(0h0))
node _T_70 = eq(_T_69, UInt<1>(0h0))
node _T_71 = asUInt(reset)
node _T_72 = eq(_T_71, UInt<1>(0h0))
when _T_72 :
node _T_73 = eq(_T_70, UInt<1>(0h0))
when _T_73 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10
assert(clock, _T_70, UInt<1>(0h1), "") : assert_10
node _T_74 = eq(before, UInt<1>(0h0))
node _T_75 = eq(_T_74, UInt<1>(0h0))
node _T_76 = asUInt(reset)
node _T_77 = eq(_T_76, UInt<1>(0h0))
when _T_77 :
node _T_78 = eq(_T_75, UInt<1>(0h0))
when _T_78 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11
assert(clock, _T_75, UInt<1>(0h1), "") : assert_11
node _T_79 = eq(evict, UInt<3>(0h7))
node _T_80 = eq(before, UInt<3>(0h7))
node _T_81 = eq(evict, UInt<3>(0h5))
node _T_82 = eq(before, UInt<3>(0h5))
node _T_83 = eq(evict, UInt<3>(0h4))
node _T_84 = eq(before, UInt<3>(0h4))
node _T_85 = eq(evict, UInt<3>(0h6))
node _T_86 = eq(before, UInt<3>(0h6))
node _T_87 = eq(evict, UInt<2>(0h3))
node _T_88 = eq(before, UInt<2>(0h3))
node _T_89 = eq(evict, UInt<2>(0h2))
node _T_90 = eq(before, UInt<2>(0h2))
node _T_91 = eq(s_writeback, UInt<1>(0h0))
node _T_92 = and(_T_91, no_wait)
node _T_93 = and(_T_92, io.schedule.ready)
when _T_93 :
node _T_94 = eq(before, UInt<4>(0h8))
node _T_95 = eq(after, UInt<1>(0h1))
node _T_96 = and(_T_94, _T_95)
node _T_97 = eq(_T_96, UInt<1>(0h0))
node _T_98 = asUInt(reset)
node _T_99 = eq(_T_98, UInt<1>(0h0))
when _T_99 :
node _T_100 = eq(_T_97, UInt<1>(0h0))
when _T_100 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12
assert(clock, _T_97, UInt<1>(0h1), "") : assert_12
node _T_101 = eq(before, UInt<4>(0h8))
node _T_102 = eq(after, UInt<1>(0h0))
node _T_103 = and(_T_101, _T_102)
node _T_104 = eq(_T_103, UInt<1>(0h0))
node _T_105 = asUInt(reset)
node _T_106 = eq(_T_105, UInt<1>(0h0))
when _T_106 :
node _T_107 = eq(_T_104, UInt<1>(0h0))
when _T_107 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13
assert(clock, _T_104, UInt<1>(0h1), "") : assert_13
node _T_108 = eq(before, UInt<4>(0h8))
node _T_109 = eq(after, UInt<3>(0h7))
node _T_110 = and(_T_108, _T_109)
node _T_111 = eq(before, UInt<4>(0h8))
node _T_112 = eq(after, UInt<3>(0h5))
node _T_113 = and(_T_111, _T_112)
node _T_114 = eq(_T_113, UInt<1>(0h0))
node _T_115 = asUInt(reset)
node _T_116 = eq(_T_115, UInt<1>(0h0))
when _T_116 :
node _T_117 = eq(_T_114, UInt<1>(0h0))
when _T_117 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14
assert(clock, _T_114, UInt<1>(0h1), "") : assert_14
node _T_118 = eq(before, UInt<4>(0h8))
node _T_119 = eq(after, UInt<3>(0h4))
node _T_120 = and(_T_118, _T_119)
node _T_121 = eq(_T_120, UInt<1>(0h0))
node _T_122 = asUInt(reset)
node _T_123 = eq(_T_122, UInt<1>(0h0))
when _T_123 :
node _T_124 = eq(_T_121, UInt<1>(0h0))
when _T_124 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15
assert(clock, _T_121, UInt<1>(0h1), "") : assert_15
node _T_125 = eq(before, UInt<4>(0h8))
node _T_126 = eq(after, UInt<3>(0h6))
node _T_127 = and(_T_125, _T_126)
node _T_128 = eq(before, UInt<4>(0h8))
node _T_129 = eq(after, UInt<2>(0h3))
node _T_130 = and(_T_128, _T_129)
node _T_131 = eq(before, UInt<4>(0h8))
node _T_132 = eq(after, UInt<2>(0h2))
node _T_133 = and(_T_131, _T_132)
node _T_134 = eq(_T_133, UInt<1>(0h0))
node _T_135 = asUInt(reset)
node _T_136 = eq(_T_135, UInt<1>(0h0))
when _T_136 :
node _T_137 = eq(_T_134, UInt<1>(0h0))
when _T_137 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16
assert(clock, _T_134, UInt<1>(0h1), "") : assert_16
node _T_138 = eq(before, UInt<1>(0h1))
node _T_139 = eq(after, UInt<4>(0h8))
node _T_140 = and(_T_138, _T_139)
node _T_141 = eq(_T_140, UInt<1>(0h0))
node _T_142 = asUInt(reset)
node _T_143 = eq(_T_142, UInt<1>(0h0))
when _T_143 :
node _T_144 = eq(_T_141, UInt<1>(0h0))
when _T_144 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17
assert(clock, _T_141, UInt<1>(0h1), "") : assert_17
node _T_145 = eq(before, UInt<1>(0h1))
node _T_146 = eq(after, UInt<1>(0h0))
node _T_147 = and(_T_145, _T_146)
node _T_148 = eq(_T_147, UInt<1>(0h0))
node _T_149 = asUInt(reset)
node _T_150 = eq(_T_149, UInt<1>(0h0))
when _T_150 :
node _T_151 = eq(_T_148, UInt<1>(0h0))
when _T_151 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18
assert(clock, _T_148, UInt<1>(0h1), "") : assert_18
node _T_152 = eq(before, UInt<1>(0h1))
node _T_153 = eq(after, UInt<3>(0h7))
node _T_154 = and(_T_152, _T_153)
node _T_155 = eq(_T_154, UInt<1>(0h0))
node _T_156 = asUInt(reset)
node _T_157 = eq(_T_156, UInt<1>(0h0))
when _T_157 :
node _T_158 = eq(_T_155, UInt<1>(0h0))
when _T_158 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19
assert(clock, _T_155, UInt<1>(0h1), "") : assert_19
node _T_159 = eq(before, UInt<1>(0h1))
node _T_160 = eq(after, UInt<3>(0h5))
node _T_161 = and(_T_159, _T_160)
node _T_162 = eq(_T_161, UInt<1>(0h0))
node _T_163 = asUInt(reset)
node _T_164 = eq(_T_163, UInt<1>(0h0))
when _T_164 :
node _T_165 = eq(_T_162, UInt<1>(0h0))
when _T_165 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20
assert(clock, _T_162, UInt<1>(0h1), "") : assert_20
node _T_166 = eq(before, UInt<1>(0h1))
node _T_167 = eq(after, UInt<3>(0h4))
node _T_168 = and(_T_166, _T_167)
node _T_169 = eq(_T_168, UInt<1>(0h0))
node _T_170 = asUInt(reset)
node _T_171 = eq(_T_170, UInt<1>(0h0))
when _T_171 :
node _T_172 = eq(_T_169, UInt<1>(0h0))
when _T_172 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21
assert(clock, _T_169, UInt<1>(0h1), "") : assert_21
node _T_173 = eq(before, UInt<1>(0h1))
node _T_174 = eq(after, UInt<3>(0h6))
node _T_175 = and(_T_173, _T_174)
node _T_176 = eq(_T_175, UInt<1>(0h0))
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_T_176, UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22
assert(clock, _T_176, UInt<1>(0h1), "") : assert_22
node _T_180 = eq(before, UInt<1>(0h1))
node _T_181 = eq(after, UInt<2>(0h3))
node _T_182 = and(_T_180, _T_181)
node _T_183 = eq(_T_182, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(before, UInt<1>(0h1))
node _T_188 = eq(after, UInt<2>(0h2))
node _T_189 = and(_T_187, _T_188)
node _T_190 = eq(_T_189, UInt<1>(0h0))
node _T_191 = asUInt(reset)
node _T_192 = eq(_T_191, UInt<1>(0h0))
when _T_192 :
node _T_193 = eq(_T_190, UInt<1>(0h0))
when _T_193 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24
assert(clock, _T_190, UInt<1>(0h1), "") : assert_24
node _T_194 = eq(before, UInt<1>(0h0))
node _T_195 = eq(after, UInt<4>(0h8))
node _T_196 = and(_T_194, _T_195)
node _T_197 = eq(_T_196, UInt<1>(0h0))
node _T_198 = asUInt(reset)
node _T_199 = eq(_T_198, UInt<1>(0h0))
when _T_199 :
node _T_200 = eq(_T_197, UInt<1>(0h0))
when _T_200 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25
assert(clock, _T_197, UInt<1>(0h1), "") : assert_25
node _T_201 = eq(before, UInt<1>(0h0))
node _T_202 = eq(after, UInt<1>(0h1))
node _T_203 = and(_T_201, _T_202)
node _T_204 = eq(_T_203, UInt<1>(0h0))
node _T_205 = asUInt(reset)
node _T_206 = eq(_T_205, UInt<1>(0h0))
when _T_206 :
node _T_207 = eq(_T_204, UInt<1>(0h0))
when _T_207 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26
assert(clock, _T_204, UInt<1>(0h1), "") : assert_26
node _T_208 = eq(before, UInt<1>(0h0))
node _T_209 = eq(after, UInt<3>(0h7))
node _T_210 = and(_T_208, _T_209)
node _T_211 = eq(_T_210, UInt<1>(0h0))
node _T_212 = asUInt(reset)
node _T_213 = eq(_T_212, UInt<1>(0h0))
when _T_213 :
node _T_214 = eq(_T_211, UInt<1>(0h0))
when _T_214 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27
assert(clock, _T_211, UInt<1>(0h1), "") : assert_27
node _T_215 = eq(before, UInt<1>(0h0))
node _T_216 = eq(after, UInt<3>(0h5))
node _T_217 = and(_T_215, _T_216)
node _T_218 = eq(_T_217, UInt<1>(0h0))
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28
assert(clock, _T_218, UInt<1>(0h1), "") : assert_28
node _T_222 = eq(before, UInt<1>(0h0))
node _T_223 = eq(after, UInt<3>(0h6))
node _T_224 = and(_T_222, _T_223)
node _T_225 = eq(_T_224, UInt<1>(0h0))
node _T_226 = asUInt(reset)
node _T_227 = eq(_T_226, UInt<1>(0h0))
when _T_227 :
node _T_228 = eq(_T_225, UInt<1>(0h0))
when _T_228 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29
assert(clock, _T_225, UInt<1>(0h1), "") : assert_29
node _T_229 = eq(before, UInt<1>(0h0))
node _T_230 = eq(after, UInt<3>(0h4))
node _T_231 = and(_T_229, _T_230)
node _T_232 = eq(_T_231, UInt<1>(0h0))
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30
assert(clock, _T_232, UInt<1>(0h1), "") : assert_30
node _T_236 = eq(before, UInt<1>(0h0))
node _T_237 = eq(after, UInt<2>(0h3))
node _T_238 = and(_T_236, _T_237)
node _T_239 = eq(_T_238, UInt<1>(0h0))
node _T_240 = asUInt(reset)
node _T_241 = eq(_T_240, UInt<1>(0h0))
when _T_241 :
node _T_242 = eq(_T_239, UInt<1>(0h0))
when _T_242 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31
assert(clock, _T_239, UInt<1>(0h1), "") : assert_31
node _T_243 = eq(before, UInt<1>(0h0))
node _T_244 = eq(after, UInt<2>(0h2))
node _T_245 = and(_T_243, _T_244)
node _T_246 = eq(_T_245, UInt<1>(0h0))
node _T_247 = asUInt(reset)
node _T_248 = eq(_T_247, UInt<1>(0h0))
when _T_248 :
node _T_249 = eq(_T_246, UInt<1>(0h0))
when _T_249 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32
assert(clock, _T_246, UInt<1>(0h1), "") : assert_32
node _T_250 = eq(before, UInt<3>(0h7))
node _T_251 = eq(after, UInt<4>(0h8))
node _T_252 = and(_T_250, _T_251)
node _T_253 = eq(_T_252, UInt<1>(0h0))
node _T_254 = asUInt(reset)
node _T_255 = eq(_T_254, UInt<1>(0h0))
when _T_255 :
node _T_256 = eq(_T_253, UInt<1>(0h0))
when _T_256 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33
assert(clock, _T_253, UInt<1>(0h1), "") : assert_33
node _T_257 = eq(before, UInt<3>(0h7))
node _T_258 = eq(after, UInt<1>(0h1))
node _T_259 = and(_T_257, _T_258)
node _T_260 = eq(_T_259, UInt<1>(0h0))
node _T_261 = asUInt(reset)
node _T_262 = eq(_T_261, UInt<1>(0h0))
when _T_262 :
node _T_263 = eq(_T_260, UInt<1>(0h0))
when _T_263 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34
assert(clock, _T_260, UInt<1>(0h1), "") : assert_34
node _T_264 = eq(before, UInt<3>(0h7))
node _T_265 = eq(after, UInt<1>(0h0))
node _T_266 = and(_T_264, _T_265)
node _T_267 = eq(_T_266, UInt<1>(0h0))
node _T_268 = asUInt(reset)
node _T_269 = eq(_T_268, UInt<1>(0h0))
when _T_269 :
node _T_270 = eq(_T_267, UInt<1>(0h0))
when _T_270 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35
assert(clock, _T_267, UInt<1>(0h1), "") : assert_35
node _T_271 = eq(before, UInt<3>(0h7))
node _T_272 = eq(after, UInt<3>(0h5))
node _T_273 = and(_T_271, _T_272)
node _T_274 = eq(_T_273, UInt<1>(0h0))
node _T_275 = asUInt(reset)
node _T_276 = eq(_T_275, UInt<1>(0h0))
when _T_276 :
node _T_277 = eq(_T_274, UInt<1>(0h0))
when _T_277 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36
assert(clock, _T_274, UInt<1>(0h1), "") : assert_36
node _T_278 = eq(before, UInt<3>(0h7))
node _T_279 = eq(after, UInt<3>(0h6))
node _T_280 = and(_T_278, _T_279)
node _T_281 = eq(before, UInt<3>(0h7))
node _T_282 = eq(after, UInt<3>(0h4))
node _T_283 = and(_T_281, _T_282)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = asUInt(reset)
node _T_286 = eq(_T_285, UInt<1>(0h0))
when _T_286 :
node _T_287 = eq(_T_284, UInt<1>(0h0))
when _T_287 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37
assert(clock, _T_284, UInt<1>(0h1), "") : assert_37
node _T_288 = eq(before, UInt<3>(0h7))
node _T_289 = eq(after, UInt<2>(0h3))
node _T_290 = and(_T_288, _T_289)
node _T_291 = eq(before, UInt<3>(0h7))
node _T_292 = eq(after, UInt<2>(0h2))
node _T_293 = and(_T_291, _T_292)
node _T_294 = eq(_T_293, UInt<1>(0h0))
node _T_295 = asUInt(reset)
node _T_296 = eq(_T_295, UInt<1>(0h0))
when _T_296 :
node _T_297 = eq(_T_294, UInt<1>(0h0))
when _T_297 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38
assert(clock, _T_294, UInt<1>(0h1), "") : assert_38
node _T_298 = eq(before, UInt<3>(0h5))
node _T_299 = eq(after, UInt<4>(0h8))
node _T_300 = and(_T_298, _T_299)
node _T_301 = eq(_T_300, UInt<1>(0h0))
node _T_302 = asUInt(reset)
node _T_303 = eq(_T_302, UInt<1>(0h0))
when _T_303 :
node _T_304 = eq(_T_301, UInt<1>(0h0))
when _T_304 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39
assert(clock, _T_301, UInt<1>(0h1), "") : assert_39
node _T_305 = eq(before, UInt<3>(0h5))
node _T_306 = eq(after, UInt<1>(0h1))
node _T_307 = and(_T_305, _T_306)
node _T_308 = eq(_T_307, UInt<1>(0h0))
node _T_309 = asUInt(reset)
node _T_310 = eq(_T_309, UInt<1>(0h0))
when _T_310 :
node _T_311 = eq(_T_308, UInt<1>(0h0))
when _T_311 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40
assert(clock, _T_308, UInt<1>(0h1), "") : assert_40
node _T_312 = eq(before, UInt<3>(0h5))
node _T_313 = eq(after, UInt<1>(0h0))
node _T_314 = and(_T_312, _T_313)
node _T_315 = eq(_T_314, UInt<1>(0h0))
node _T_316 = asUInt(reset)
node _T_317 = eq(_T_316, UInt<1>(0h0))
when _T_317 :
node _T_318 = eq(_T_315, UInt<1>(0h0))
when _T_318 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41
assert(clock, _T_315, UInt<1>(0h1), "") : assert_41
node _T_319 = eq(before, UInt<3>(0h5))
node _T_320 = eq(after, UInt<3>(0h7))
node _T_321 = and(_T_319, _T_320)
node _T_322 = eq(before, UInt<3>(0h5))
node _T_323 = eq(after, UInt<3>(0h6))
node _T_324 = and(_T_322, _T_323)
node _T_325 = eq(before, UInt<3>(0h5))
node _T_326 = eq(after, UInt<3>(0h4))
node _T_327 = and(_T_325, _T_326)
node _T_328 = eq(_T_327, UInt<1>(0h0))
node _T_329 = asUInt(reset)
node _T_330 = eq(_T_329, UInt<1>(0h0))
when _T_330 :
node _T_331 = eq(_T_328, UInt<1>(0h0))
when _T_331 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42
assert(clock, _T_328, UInt<1>(0h1), "") : assert_42
node _T_332 = eq(before, UInt<3>(0h5))
node _T_333 = eq(after, UInt<2>(0h3))
node _T_334 = and(_T_332, _T_333)
node _T_335 = eq(before, UInt<3>(0h5))
node _T_336 = eq(after, UInt<2>(0h2))
node _T_337 = and(_T_335, _T_336)
node _T_338 = eq(_T_337, UInt<1>(0h0))
node _T_339 = asUInt(reset)
node _T_340 = eq(_T_339, UInt<1>(0h0))
when _T_340 :
node _T_341 = eq(_T_338, UInt<1>(0h0))
when _T_341 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43
assert(clock, _T_338, UInt<1>(0h1), "") : assert_43
node _T_342 = eq(before, UInt<3>(0h6))
node _T_343 = eq(after, UInt<4>(0h8))
node _T_344 = and(_T_342, _T_343)
node _T_345 = eq(_T_344, UInt<1>(0h0))
node _T_346 = asUInt(reset)
node _T_347 = eq(_T_346, UInt<1>(0h0))
when _T_347 :
node _T_348 = eq(_T_345, UInt<1>(0h0))
when _T_348 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44
assert(clock, _T_345, UInt<1>(0h1), "") : assert_44
node _T_349 = eq(before, UInt<3>(0h6))
node _T_350 = eq(after, UInt<1>(0h1))
node _T_351 = and(_T_349, _T_350)
node _T_352 = eq(_T_351, UInt<1>(0h0))
node _T_353 = asUInt(reset)
node _T_354 = eq(_T_353, UInt<1>(0h0))
when _T_354 :
node _T_355 = eq(_T_352, UInt<1>(0h0))
when _T_355 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45
assert(clock, _T_352, UInt<1>(0h1), "") : assert_45
node _T_356 = eq(before, UInt<3>(0h6))
node _T_357 = eq(after, UInt<1>(0h0))
node _T_358 = and(_T_356, _T_357)
node _T_359 = eq(_T_358, UInt<1>(0h0))
node _T_360 = asUInt(reset)
node _T_361 = eq(_T_360, UInt<1>(0h0))
when _T_361 :
node _T_362 = eq(_T_359, UInt<1>(0h0))
when _T_362 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46
assert(clock, _T_359, UInt<1>(0h1), "") : assert_46
node _T_363 = eq(before, UInt<3>(0h6))
node _T_364 = eq(after, UInt<3>(0h7))
node _T_365 = and(_T_363, _T_364)
node _T_366 = eq(_T_365, UInt<1>(0h0))
node _T_367 = asUInt(reset)
node _T_368 = eq(_T_367, UInt<1>(0h0))
when _T_368 :
node _T_369 = eq(_T_366, UInt<1>(0h0))
when _T_369 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47
assert(clock, _T_366, UInt<1>(0h1), "") : assert_47
node _T_370 = eq(before, UInt<3>(0h6))
node _T_371 = eq(after, UInt<3>(0h5))
node _T_372 = and(_T_370, _T_371)
node _T_373 = eq(_T_372, UInt<1>(0h0))
node _T_374 = asUInt(reset)
node _T_375 = eq(_T_374, UInt<1>(0h0))
when _T_375 :
node _T_376 = eq(_T_373, UInt<1>(0h0))
when _T_376 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48
assert(clock, _T_373, UInt<1>(0h1), "") : assert_48
node _T_377 = eq(before, UInt<3>(0h6))
node _T_378 = eq(after, UInt<3>(0h4))
node _T_379 = and(_T_377, _T_378)
node _T_380 = eq(_T_379, UInt<1>(0h0))
node _T_381 = asUInt(reset)
node _T_382 = eq(_T_381, UInt<1>(0h0))
when _T_382 :
node _T_383 = eq(_T_380, UInt<1>(0h0))
when _T_383 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49
assert(clock, _T_380, UInt<1>(0h1), "") : assert_49
node _T_384 = eq(before, UInt<3>(0h6))
node _T_385 = eq(after, UInt<2>(0h3))
node _T_386 = and(_T_384, _T_385)
node _T_387 = eq(_T_386, UInt<1>(0h0))
node _T_388 = asUInt(reset)
node _T_389 = eq(_T_388, UInt<1>(0h0))
when _T_389 :
node _T_390 = eq(_T_387, UInt<1>(0h0))
when _T_390 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50
assert(clock, _T_387, UInt<1>(0h1), "") : assert_50
node _T_391 = eq(before, UInt<3>(0h6))
node _T_392 = eq(after, UInt<2>(0h2))
node _T_393 = and(_T_391, _T_392)
node _T_394 = eq(before, UInt<3>(0h4))
node _T_395 = eq(after, UInt<4>(0h8))
node _T_396 = and(_T_394, _T_395)
node _T_397 = eq(_T_396, UInt<1>(0h0))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51
assert(clock, _T_397, UInt<1>(0h1), "") : assert_51
node _T_401 = eq(before, UInt<3>(0h4))
node _T_402 = eq(after, UInt<1>(0h1))
node _T_403 = and(_T_401, _T_402)
node _T_404 = eq(_T_403, UInt<1>(0h0))
node _T_405 = asUInt(reset)
node _T_406 = eq(_T_405, UInt<1>(0h0))
when _T_406 :
node _T_407 = eq(_T_404, UInt<1>(0h0))
when _T_407 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52
assert(clock, _T_404, UInt<1>(0h1), "") : assert_52
node _T_408 = eq(before, UInt<3>(0h4))
node _T_409 = eq(after, UInt<1>(0h0))
node _T_410 = and(_T_408, _T_409)
node _T_411 = eq(_T_410, UInt<1>(0h0))
node _T_412 = asUInt(reset)
node _T_413 = eq(_T_412, UInt<1>(0h0))
when _T_413 :
node _T_414 = eq(_T_411, UInt<1>(0h0))
when _T_414 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53
assert(clock, _T_411, UInt<1>(0h1), "") : assert_53
node _T_415 = eq(before, UInt<3>(0h4))
node _T_416 = eq(after, UInt<3>(0h7))
node _T_417 = and(_T_415, _T_416)
node _T_418 = eq(_T_417, UInt<1>(0h0))
node _T_419 = asUInt(reset)
node _T_420 = eq(_T_419, UInt<1>(0h0))
when _T_420 :
node _T_421 = eq(_T_418, UInt<1>(0h0))
when _T_421 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54
assert(clock, _T_418, UInt<1>(0h1), "") : assert_54
node _T_422 = eq(before, UInt<3>(0h4))
node _T_423 = eq(after, UInt<3>(0h5))
node _T_424 = and(_T_422, _T_423)
node _T_425 = eq(_T_424, UInt<1>(0h0))
node _T_426 = asUInt(reset)
node _T_427 = eq(_T_426, UInt<1>(0h0))
when _T_427 :
node _T_428 = eq(_T_425, UInt<1>(0h0))
when _T_428 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55
assert(clock, _T_425, UInt<1>(0h1), "") : assert_55
node _T_429 = eq(before, UInt<3>(0h4))
node _T_430 = eq(after, UInt<3>(0h6))
node _T_431 = and(_T_429, _T_430)
node _T_432 = eq(before, UInt<3>(0h4))
node _T_433 = eq(after, UInt<2>(0h3))
node _T_434 = and(_T_432, _T_433)
node _T_435 = eq(_T_434, UInt<1>(0h0))
node _T_436 = asUInt(reset)
node _T_437 = eq(_T_436, UInt<1>(0h0))
when _T_437 :
node _T_438 = eq(_T_435, UInt<1>(0h0))
when _T_438 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56
assert(clock, _T_435, UInt<1>(0h1), "") : assert_56
node _T_439 = eq(before, UInt<3>(0h4))
node _T_440 = eq(after, UInt<2>(0h2))
node _T_441 = and(_T_439, _T_440)
node _T_442 = eq(before, UInt<2>(0h3))
node _T_443 = eq(after, UInt<4>(0h8))
node _T_444 = and(_T_442, _T_443)
node _T_445 = eq(_T_444, UInt<1>(0h0))
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57
assert(clock, _T_445, UInt<1>(0h1), "") : assert_57
node _T_449 = eq(before, UInt<2>(0h3))
node _T_450 = eq(after, UInt<1>(0h1))
node _T_451 = and(_T_449, _T_450)
node _T_452 = eq(_T_451, UInt<1>(0h0))
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(_T_452, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58
assert(clock, _T_452, UInt<1>(0h1), "") : assert_58
node _T_456 = eq(before, UInt<2>(0h3))
node _T_457 = eq(after, UInt<1>(0h0))
node _T_458 = and(_T_456, _T_457)
node _T_459 = eq(_T_458, UInt<1>(0h0))
node _T_460 = asUInt(reset)
node _T_461 = eq(_T_460, UInt<1>(0h0))
when _T_461 :
node _T_462 = eq(_T_459, UInt<1>(0h0))
when _T_462 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59
assert(clock, _T_459, UInt<1>(0h1), "") : assert_59
node _T_463 = eq(before, UInt<2>(0h3))
node _T_464 = eq(after, UInt<3>(0h7))
node _T_465 = and(_T_463, _T_464)
node _T_466 = eq(before, UInt<2>(0h3))
node _T_467 = eq(after, UInt<3>(0h5))
node _T_468 = and(_T_466, _T_467)
node _T_469 = eq(before, UInt<2>(0h3))
node _T_470 = eq(after, UInt<3>(0h6))
node _T_471 = and(_T_469, _T_470)
node _T_472 = eq(before, UInt<2>(0h3))
node _T_473 = eq(after, UInt<3>(0h4))
node _T_474 = and(_T_472, _T_473)
node _T_475 = eq(before, UInt<2>(0h3))
node _T_476 = eq(after, UInt<2>(0h2))
node _T_477 = and(_T_475, _T_476)
node _T_478 = eq(before, UInt<2>(0h2))
node _T_479 = eq(after, UInt<4>(0h8))
node _T_480 = and(_T_478, _T_479)
node _T_481 = eq(_T_480, UInt<1>(0h0))
node _T_482 = asUInt(reset)
node _T_483 = eq(_T_482, UInt<1>(0h0))
when _T_483 :
node _T_484 = eq(_T_481, UInt<1>(0h0))
when _T_484 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60
assert(clock, _T_481, UInt<1>(0h1), "") : assert_60
node _T_485 = eq(before, UInt<2>(0h2))
node _T_486 = eq(after, UInt<1>(0h1))
node _T_487 = and(_T_485, _T_486)
node _T_488 = eq(_T_487, UInt<1>(0h0))
node _T_489 = asUInt(reset)
node _T_490 = eq(_T_489, UInt<1>(0h0))
when _T_490 :
node _T_491 = eq(_T_488, UInt<1>(0h0))
when _T_491 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61
assert(clock, _T_488, UInt<1>(0h1), "") : assert_61
node _T_492 = eq(before, UInt<2>(0h2))
node _T_493 = eq(after, UInt<1>(0h0))
node _T_494 = and(_T_492, _T_493)
node _T_495 = eq(_T_494, UInt<1>(0h0))
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_T_495, UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62
assert(clock, _T_495, UInt<1>(0h1), "") : assert_62
node _T_499 = eq(before, UInt<2>(0h2))
node _T_500 = eq(after, UInt<3>(0h7))
node _T_501 = and(_T_499, _T_500)
node _T_502 = eq(_T_501, UInt<1>(0h0))
node _T_503 = asUInt(reset)
node _T_504 = eq(_T_503, UInt<1>(0h0))
when _T_504 :
node _T_505 = eq(_T_502, UInt<1>(0h0))
when _T_505 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63
assert(clock, _T_502, UInt<1>(0h1), "") : assert_63
node _T_506 = eq(before, UInt<2>(0h2))
node _T_507 = eq(after, UInt<3>(0h5))
node _T_508 = and(_T_506, _T_507)
node _T_509 = eq(_T_508, UInt<1>(0h0))
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64
assert(clock, _T_509, UInt<1>(0h1), "") : assert_64
node _T_513 = eq(before, UInt<2>(0h2))
node _T_514 = eq(after, UInt<3>(0h6))
node _T_515 = and(_T_513, _T_514)
node _T_516 = eq(before, UInt<2>(0h2))
node _T_517 = eq(after, UInt<3>(0h4))
node _T_518 = and(_T_516, _T_517)
node _T_519 = eq(before, UInt<2>(0h2))
node _T_520 = eq(after, UInt<2>(0h3))
node _T_521 = and(_T_519, _T_520)
node _T_522 = eq(_T_521, UInt<1>(0h0))
node _T_523 = asUInt(reset)
node _T_524 = eq(_T_523, UInt<1>(0h0))
when _T_524 :
node _T_525 = eq(_T_522, UInt<1>(0h0))
when _T_525 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65
assert(clock, _T_522, UInt<1>(0h1), "") : assert_65
node probe_bit = eq(io.sinkc.bits.source, UInt<6>(0h28))
node _last_probe_T = or(probes_done, probe_bit)
node _last_probe_T_1 = not(excluded_client)
node _last_probe_T_2 = and(meta.clients, _last_probe_T_1)
node last_probe = eq(_last_probe_T, _last_probe_T_2)
node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1))
node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2))
node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1)
node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5))
node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3)
when io.sinkc.valid :
node _T_526 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1))
node _T_527 = and(probe_toN, _T_526)
node _T_528 = eq(probe_toN, UInt<1>(0h0))
node _T_529 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1))
node _T_530 = and(_T_528, _T_529)
node _probes_done_T = or(probes_done, probe_bit)
connect probes_done, _probes_done_T
node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0))
node _probes_toN_T_1 = or(probes_toN, _probes_toN_T)
connect probes_toN, _probes_toN_T_1
node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3))
node _probes_noT_T_1 = or(probes_noT, _probes_noT_T)
connect probes_noT, _probes_noT_T_1
node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe)
connect w_rprobeackfirst, _w_rprobeackfirst_T
node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last)
node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T)
connect w_rprobeacklast, _w_rprobeacklast_T_1
node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe)
connect w_pprobeackfirst, _w_pprobeackfirst_T
node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last)
node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T)
connect w_pprobeacklast, _w_pprobeacklast_T_1
node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0))
node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T)
node set_pprobeack = and(last_probe, _set_pprobeack_T_1)
node _w_pprobeack_T = or(w_pprobeack, set_pprobeack)
connect w_pprobeack, _w_pprobeack_T
node _T_531 = eq(set_pprobeack, UInt<1>(0h0))
node _T_532 = and(_T_531, w_rprobeackfirst)
node _T_533 = and(set_pprobeack, w_rprobeackfirst)
node _T_534 = neq(meta.state, UInt<2>(0h0))
node _T_535 = eq(io.sinkc.bits.tag, meta.tag)
node _T_536 = and(_T_534, _T_535)
node _T_537 = and(_T_536, io.sinkc.bits.data)
when _T_537 :
connect meta.dirty, UInt<1>(0h1)
when io.sinkd.valid :
node _T_538 = eq(io.sinkd.bits.opcode, UInt<3>(0h4))
node _T_539 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_540 = or(_T_538, _T_539)
when _T_540 :
connect sink, io.sinkd.bits.sink
connect w_grantfirst, UInt<1>(0h1)
connect w_grantlast, io.sinkd.bits.last
connect bad_grant, io.sinkd.bits.denied
node _w_grant_T = eq(request.offset, UInt<1>(0h0))
node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last)
connect w_grant, _w_grant_T_1
node _T_541 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_542 = eq(request.offset, UInt<1>(0h0))
node _T_543 = and(_T_541, _T_542)
node _T_544 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_545 = neq(request.offset, UInt<1>(0h0))
node _T_546 = and(_T_544, _T_545)
node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0))
connect gotT, _gotT_T
else :
node _T_547 = eq(io.sinkd.bits.opcode, UInt<3>(0h6))
when _T_547 :
connect w_releaseack, UInt<1>(0h1)
when io.sinke.valid :
connect w_grantack, UInt<1>(0h1)
wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>}
connect allocate_as_full.set, io.allocate.bits.set
connect allocate_as_full.put, io.allocate.bits.put
connect allocate_as_full.offset, io.allocate.bits.offset
connect allocate_as_full.tag, io.allocate.bits.tag
connect allocate_as_full.source, io.allocate.bits.source
connect allocate_as_full.size, io.allocate.bits.size
connect allocate_as_full.param, io.allocate.bits.param
connect allocate_as_full.opcode, io.allocate.bits.opcode
connect allocate_as_full.control, io.allocate.bits.control
connect allocate_as_full.prio, io.allocate.bits.prio
node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat)
node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits)
node new_request = mux(io.allocate.valid, allocate_as_full, request)
node _new_needT_T = bits(new_request.opcode, 2, 2)
node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0))
node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5))
node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1))
node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3)
node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4)
node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6))
node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7))
node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7)
node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0))
node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9)
node new_needT = or(_new_needT_T_5, _new_needT_T_10)
node new_clientBit = eq(new_request.source, UInt<6>(0h28))
node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6))
node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7))
node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1)
node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4))
node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3)
node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5))
node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0))
node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6)
node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0))
wire prior : UInt
connect prior, UInt<1>(0h0)
node prior_c = orr(final_meta_writeback.clients)
node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state)
when _prior_T :
node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1))
connect prior, _prior_out_T
else :
node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state)
when _prior_T_1 :
node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect prior, _prior_out_T_1
else :
node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state)
when _prior_T_2 :
node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3)
connect prior, _prior_out_T_4
else :
node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state)
when _prior_T_3 :
connect prior, UInt<4>(0h8)
node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0))
when _prior_T_4 :
connect prior, UInt<4>(0h8)
node _T_548 = and(io.allocate.valid, io.allocate.bits.repeat)
when _T_548 :
node _T_549 = eq(prior, UInt<4>(0h8))
node _T_550 = eq(prior, UInt<1>(0h1))
node _T_551 = eq(_T_550, UInt<1>(0h0))
node _T_552 = asUInt(reset)
node _T_553 = eq(_T_552, UInt<1>(0h0))
when _T_553 :
node _T_554 = eq(_T_551, UInt<1>(0h0))
when _T_554 :
printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_66
assert(clock, _T_551, UInt<1>(0h1), "") : assert_66
node _T_555 = eq(prior, UInt<1>(0h0))
node _T_556 = eq(_T_555, UInt<1>(0h0))
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_67
assert(clock, _T_556, UInt<1>(0h1), "") : assert_67
node _T_560 = eq(prior, UInt<3>(0h7))
node _T_561 = eq(prior, UInt<3>(0h5))
node _T_562 = eq(prior, UInt<3>(0h4))
node _T_563 = eq(prior, UInt<3>(0h6))
node _T_564 = eq(prior, UInt<2>(0h3))
node _T_565 = eq(prior, UInt<2>(0h2))
when io.allocate.valid :
node _T_566 = eq(request_valid, UInt<1>(0h0))
node _T_567 = and(io.schedule.ready, io.schedule.valid)
node _T_568 = and(no_wait, _T_567)
node _T_569 = or(_T_566, _T_568)
node _T_570 = asUInt(reset)
node _T_571 = eq(_T_570, UInt<1>(0h0))
when _T_571 :
node _T_572 = eq(_T_569, UInt<1>(0h0))
when _T_572 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid || (no_wait && io.schedule.fire))\n") : printf_68
assert(clock, _T_569, UInt<1>(0h1), "") : assert_68
connect request_valid, UInt<1>(0h1)
connect request.set, io.allocate.bits.set
connect request.put, io.allocate.bits.put
connect request.offset, io.allocate.bits.offset
connect request.tag, io.allocate.bits.tag
connect request.source, io.allocate.bits.source
connect request.size, io.allocate.bits.size
connect request.param, io.allocate.bits.param
connect request.opcode, io.allocate.bits.opcode
connect request.control, io.allocate.bits.control
connect request.prio, io.allocate.bits.prio
node _T_573 = and(io.allocate.valid, io.allocate.bits.repeat)
node _T_574 = or(io.directory.valid, _T_573)
when _T_574 :
connect meta_valid, UInt<1>(0h1)
connect meta, new_meta
connect probes_done, UInt<1>(0h0)
connect probes_toN, UInt<1>(0h0)
connect probes_noT, UInt<1>(0h0)
connect gotT, UInt<1>(0h0)
connect bad_grant, UInt<1>(0h0)
connect s_rprobe, UInt<1>(0h1)
connect w_rprobeackfirst, UInt<1>(0h1)
connect w_rprobeacklast, UInt<1>(0h1)
connect s_release, UInt<1>(0h1)
connect w_releaseack, UInt<1>(0h1)
connect s_pprobe, UInt<1>(0h1)
connect s_acquire, UInt<1>(0h1)
connect s_flush, UInt<1>(0h1)
connect w_grantfirst, UInt<1>(0h1)
connect w_grantlast, UInt<1>(0h1)
connect w_grant, UInt<1>(0h1)
connect w_pprobeackfirst, UInt<1>(0h1)
connect w_pprobeacklast, UInt<1>(0h1)
connect w_pprobeack, UInt<1>(0h1)
connect s_probeack, UInt<1>(0h1)
connect s_grantack, UInt<1>(0h1)
connect s_execute, UInt<1>(0h1)
connect w_grantack, UInt<1>(0h1)
connect s_writeback, UInt<1>(0h1)
node _T_575 = and(new_request.prio[2], UInt<1>(0h1))
when _T_575 :
connect s_execute, UInt<1>(0h0)
node _T_576 = bits(new_request.opcode, 0, 0)
node _T_577 = eq(new_meta.dirty, UInt<1>(0h0))
node _T_578 = and(_T_576, _T_577)
when _T_578 :
connect s_writeback, UInt<1>(0h0)
node _T_579 = eq(new_request.param, UInt<3>(0h0))
node _T_580 = eq(new_request.param, UInt<3>(0h4))
node _T_581 = or(_T_579, _T_580)
node _T_582 = eq(new_meta.state, UInt<2>(0h2))
node _T_583 = and(_T_581, _T_582)
when _T_583 :
connect s_writeback, UInt<1>(0h0)
node _T_584 = eq(new_request.param, UInt<3>(0h1))
node _T_585 = eq(new_request.param, UInt<3>(0h2))
node _T_586 = or(_T_584, _T_585)
node _T_587 = eq(new_request.param, UInt<3>(0h5))
node _T_588 = or(_T_586, _T_587)
node _T_589 = and(new_meta.clients, new_clientBit)
node _T_590 = neq(_T_589, UInt<1>(0h0))
node _T_591 = and(_T_588, _T_590)
when _T_591 :
connect s_writeback, UInt<1>(0h0)
node _T_592 = asUInt(reset)
node _T_593 = eq(_T_592, UInt<1>(0h0))
when _T_593 :
node _T_594 = eq(new_meta.hit, UInt<1>(0h0))
when _T_594 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_69
assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_69
else :
node _T_595 = and(new_request.control, UInt<1>(0h1))
when _T_595 :
connect s_flush, UInt<1>(0h0)
when new_meta.hit :
connect s_release, UInt<1>(0h0)
connect w_releaseack, UInt<1>(0h0)
node _T_596 = neq(new_meta.clients, UInt<1>(0h0))
node _T_597 = and(UInt<1>(0h1), _T_596)
when _T_597 :
connect s_rprobe, UInt<1>(0h0)
connect w_rprobeackfirst, UInt<1>(0h0)
connect w_rprobeacklast, UInt<1>(0h0)
else :
connect s_execute, UInt<1>(0h0)
node _T_598 = eq(new_meta.hit, UInt<1>(0h0))
node _T_599 = neq(new_meta.state, UInt<2>(0h0))
node _T_600 = and(_T_598, _T_599)
when _T_600 :
connect s_release, UInt<1>(0h0)
connect w_releaseack, UInt<1>(0h0)
node _T_601 = neq(new_meta.clients, UInt<1>(0h0))
node _T_602 = and(UInt<1>(0h1), _T_601)
when _T_602 :
connect s_rprobe, UInt<1>(0h0)
connect w_rprobeackfirst, UInt<1>(0h0)
connect w_rprobeacklast, UInt<1>(0h0)
node _T_603 = eq(new_meta.hit, UInt<1>(0h0))
node _T_604 = eq(new_meta.state, UInt<2>(0h1))
node _T_605 = and(_T_604, new_needT)
node _T_606 = or(_T_603, _T_605)
when _T_606 :
connect s_acquire, UInt<1>(0h0)
connect w_grantfirst, UInt<1>(0h0)
connect w_grantlast, UInt<1>(0h0)
connect w_grant, UInt<1>(0h0)
connect s_grantack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_607 = eq(new_meta.state, UInt<2>(0h2))
node _T_608 = or(new_needT, _T_607)
node _T_609 = and(new_meta.hit, _T_608)
node _T_610 = not(new_skipProbe)
node _T_611 = and(new_meta.clients, _T_610)
node _T_612 = neq(_T_611, UInt<1>(0h0))
node _T_613 = and(_T_609, _T_612)
node _T_614 = and(UInt<1>(0h1), _T_613)
when _T_614 :
connect s_pprobe, UInt<1>(0h0)
connect w_pprobeackfirst, UInt<1>(0h0)
connect w_pprobeacklast, UInt<1>(0h0)
connect w_pprobeack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_615 = eq(new_request.opcode, UInt<3>(0h6))
node _T_616 = eq(new_request.opcode, UInt<3>(0h7))
node _T_617 = or(_T_615, _T_616)
when _T_617 :
connect w_grantack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_618 = bits(new_request.opcode, 2, 2)
node _T_619 = eq(_T_618, UInt<1>(0h0))
node _T_620 = and(_T_619, new_meta.hit)
node _T_621 = eq(new_meta.dirty, UInt<1>(0h0))
node _T_622 = and(_T_620, _T_621)
when _T_622 :
connect s_writeback, UInt<1>(0h0) | module MSHR_36( // @[MSHR.scala:84:7]
input clock, // @[MSHR.scala:84:7]
input reset, // @[MSHR.scala:84:7]
input io_allocate_valid, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_0, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_1, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_2, // @[MSHR.scala:86:14]
input io_allocate_bits_control, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14]
input [8:0] io_allocate_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14]
input [10:0] io_allocate_bits_set, // @[MSHR.scala:86:14]
input io_allocate_bits_repeat, // @[MSHR.scala:86:14]
input io_directory_valid, // @[MSHR.scala:86:14]
input io_directory_bits_dirty, // @[MSHR.scala:86:14]
input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14]
input io_directory_bits_clients, // @[MSHR.scala:86:14]
input [8:0] io_directory_bits_tag, // @[MSHR.scala:86:14]
input io_directory_bits_hit, // @[MSHR.scala:86:14]
input [3:0] io_directory_bits_way, // @[MSHR.scala:86:14]
output io_status_valid, // @[MSHR.scala:86:14]
output [10:0] io_status_bits_set, // @[MSHR.scala:86:14]
output [8:0] io_status_bits_tag, // @[MSHR.scala:86:14]
output [3:0] io_status_bits_way, // @[MSHR.scala:86:14]
output io_status_bits_blockB, // @[MSHR.scala:86:14]
output io_status_bits_nestB, // @[MSHR.scala:86:14]
output io_status_bits_blockC, // @[MSHR.scala:86:14]
output io_status_bits_nestC, // @[MSHR.scala:86:14]
input io_schedule_ready, // @[MSHR.scala:86:14]
output io_schedule_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_a_valid, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14]
output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14]
output io_schedule_bits_b_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14]
output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14]
output io_schedule_bits_c_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14]
output [3:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14]
output io_schedule_bits_d_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14]
output [3:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14]
output io_schedule_bits_e_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14]
output io_schedule_bits_x_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14]
output [3:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14]
output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14]
output io_schedule_bits_reload, // @[MSHR.scala:86:14]
input io_sinkc_valid, // @[MSHR.scala:86:14]
input io_sinkc_bits_last, // @[MSHR.scala:86:14]
input [10:0] io_sinkc_bits_set, // @[MSHR.scala:86:14]
input [8:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14]
input io_sinkc_bits_data, // @[MSHR.scala:86:14]
input io_sinkd_valid, // @[MSHR.scala:86:14]
input io_sinkd_bits_last, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14]
input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14]
input io_sinkd_bits_denied, // @[MSHR.scala:86:14]
input io_sinke_valid, // @[MSHR.scala:86:14]
input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14]
input [10:0] io_nestedwb_set, // @[MSHR.scala:86:14]
input [8:0] io_nestedwb_tag, // @[MSHR.scala:86:14]
input io_nestedwb_b_toN, // @[MSHR.scala:86:14]
input io_nestedwb_b_toB, // @[MSHR.scala:86:14]
input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14]
input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14]
);
wire [8:0] final_meta_writeback_tag; // @[MSHR.scala:215:38]
wire final_meta_writeback_clients; // @[MSHR.scala:215:38]
wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38]
wire final_meta_writeback_dirty; // @[MSHR.scala:215:38]
wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7]
wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7]
wire [8:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7]
wire [10:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7]
wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7]
wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7]
wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7]
wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7]
wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7]
wire [8:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7]
wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7]
wire [3:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7]
wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7]
wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7]
wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7]
wire [10:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7]
wire [8:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7]
wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7]
wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7]
wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7]
wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7]
wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7]
wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7]
wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7]
wire [10:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7]
wire [8:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7]
wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7]
wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7]
wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68]
wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80]
wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21]
wire invalid_clients = 1'h0; // @[MSHR.scala:268:21]
wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137]
wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137]
wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire [8:0] invalid_tag = 9'h0; // @[MSHR.scala:268:21]
wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21]
wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70]
wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34]
wire [8:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34]
wire [10:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34]
wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40]
wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93]
wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28]
wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39]
wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105]
wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55]
wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91]
wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41]
wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41]
wire [8:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41]
wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51]
wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64]
wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41]
wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41]
wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57]
wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41]
wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43]
wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40]
wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66]
wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41]
wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41]
wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41]
wire [8:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41]
wire no_wait; // @[MSHR.scala:183:83]
wire [10:0] io_status_bits_set_0; // @[MSHR.scala:84:7]
wire [8:0] io_status_bits_tag_0; // @[MSHR.scala:84:7]
wire [3:0] io_status_bits_way_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockB_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestB_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockC_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestC_0; // @[MSHR.scala:84:7]
wire io_status_valid_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7]
wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7]
wire io_schedule_valid_0; // @[MSHR.scala:84:7]
reg request_valid; // @[MSHR.scala:97:30]
assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30]
reg request_prio_0; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20]
reg request_prio_1; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20]
reg request_prio_2; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20]
reg request_control; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_opcode; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_param; // @[MSHR.scala:98:20]
reg [2:0] request_size; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_source; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20]
reg [8:0] request_tag; // @[MSHR.scala:98:20]
assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_offset; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_put; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20]
reg [10:0] request_set; // @[MSHR.scala:98:20]
assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
reg meta_valid; // @[MSHR.scala:99:27]
reg meta_dirty; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17]
reg [1:0] meta_state; // @[MSHR.scala:100:17]
reg meta_clients; // @[MSHR.scala:100:17]
wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39]
wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
reg [8:0] meta_tag; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17]
reg meta_hit; // @[MSHR.scala:100:17]
reg [3:0] meta_way; // @[MSHR.scala:100:17]
assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
wire [3:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38]
reg s_rprobe; // @[MSHR.scala:121:33]
reg w_rprobeackfirst; // @[MSHR.scala:122:33]
reg w_rprobeacklast; // @[MSHR.scala:123:33]
reg s_release; // @[MSHR.scala:124:33]
reg w_releaseack; // @[MSHR.scala:125:33]
reg s_pprobe; // @[MSHR.scala:126:33]
reg s_acquire; // @[MSHR.scala:127:33]
reg s_flush; // @[MSHR.scala:128:33]
reg w_grantfirst; // @[MSHR.scala:129:33]
reg w_grantlast; // @[MSHR.scala:130:33]
reg w_grant; // @[MSHR.scala:131:33]
reg w_pprobeackfirst; // @[MSHR.scala:132:33]
reg w_pprobeacklast; // @[MSHR.scala:133:33]
reg w_pprobeack; // @[MSHR.scala:134:33]
reg s_grantack; // @[MSHR.scala:136:33]
reg s_execute; // @[MSHR.scala:137:33]
reg w_grantack; // @[MSHR.scala:138:33]
reg s_writeback; // @[MSHR.scala:139:33]
reg [2:0] sink; // @[MSHR.scala:147:17]
assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17]
reg gotT; // @[MSHR.scala:148:17]
reg bad_grant; // @[MSHR.scala:149:22]
assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22]
reg probes_done; // @[MSHR.scala:150:24]
reg probes_toN; // @[MSHR.scala:151:23]
reg probes_noT; // @[MSHR.scala:152:23]
wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28]
wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45]
wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62]
wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}]
wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82]
wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}]
wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103]
wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}]
assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}]
assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40]
wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39]
wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}]
wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}]
wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96]
assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}]
assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93]
assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28]
assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28]
wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43]
wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64]
wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}]
wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85]
wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}]
assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}]
assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39]
wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33]
wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}]
wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}]
assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}]
assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83]
wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31]
wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}]
assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}]
assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55]
wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31]
wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44]
assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}]
assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41]
wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32]
wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}]
assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}]
assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64]
wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31]
wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}]
assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}]
assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57]
wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31]
assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}]
assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43]
wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31]
assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}]
assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40]
wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34]
wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}]
wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70]
wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}]
assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}]
assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66]
wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49]
wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}]
wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}]
wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49]
wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}]
assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}]
assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105]
wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71]
wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71]
wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71]
wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire [8:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71]
wire final_meta_writeback_hit; // @[MSHR.scala:215:38]
wire req_clientBit = request_source == 6'h28; // @[Parameters.scala:46:9]
wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12]
wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12]
wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _req_needT_T_2; // @[Parameters.scala:270:13]
assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13]
wire _excluded_client_T_6; // @[Parameters.scala:279:117]
assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117]
wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42]
wire _req_needT_T_3; // @[Parameters.scala:270:42]
assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42]
wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11]
assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11]
wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42]
wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _req_needT_T_6; // @[Parameters.scala:271:14]
assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14]
wire _req_acquire_T; // @[MSHR.scala:219:36]
assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14]
wire _excluded_client_T_1; // @[Parameters.scala:279:12]
assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12]
wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52]
wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89]
wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52]
wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}]
wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}]
wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81]
wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}]
wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}]
wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}]
wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65]
wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}]
wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55]
wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78]
wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78]
assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78]
wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70]
wire _evict_T_2; // @[MSHR.scala:317:26]
assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _before_T_1; // @[MSHR.scala:317:26]
assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}]
wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}]
wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43]
assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43]
wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75]
wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}]
wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9]
wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}]
wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}]
wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54]
wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}]
wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45]
wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}]
wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}]
wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40]
wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40]
assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40]
wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65]
assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65]
wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41]
wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}]
wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72]
wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}]
wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70]
wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70]
wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53]
assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53]
wire _evict_T_1; // @[MSHR.scala:317:26]
assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire _before_T; // @[MSHR.scala:317:26]
assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70]
wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70]
wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55]
wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70]
wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70]
wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66]
wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}]
wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}]
wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9]
wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40]
assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30]
wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54]
wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}]
assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21]
assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21]
assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36]
assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36]
wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9]
wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}]
wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}]
wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38]
wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}]
wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}]
wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}]
wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106]
wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:46:9]
wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56]
wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70]
assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}]
wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51]
wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55]
wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52]
wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}]
wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}]
assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38]
assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91]
wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42]
wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70]
wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}]
assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}]
assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41]
wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42]
assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}]
assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41]
wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53]
assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}]
assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51]
assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41]
assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41]
assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}]
assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41]
wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42]
wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53]
wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53]
wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89]
wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79]
assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41]
wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42]
assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 9'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}]
assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41]
wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32]
wire [3:0] evict; // @[MSHR.scala:314:26]
wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32]
wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32]
wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32]
assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32]
assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39]
wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39]
assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39]
assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76]
wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76]
assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76]
assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32]
assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] before_0; // @[MSHR.scala:314:26]
wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32]
wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11]
assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] after; // @[MSHR.scala:314:26]
wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26]
wire _after_T; // @[MSHR.scala:317:26]
assign _after_T = _GEN_9; // @[MSHR.scala:317:26]
wire _prior_T; // @[MSHR.scala:317:26]
assign _prior_T = _GEN_9; // @[MSHR.scala:317:26]
wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32]
wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26]
wire _after_T_1; // @[MSHR.scala:317:26]
assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire _prior_T_1; // @[MSHR.scala:317:26]
assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32]
wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32]
assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32]
assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39]
wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39]
assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39]
assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76]
wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76]
assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76]
assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26]
wire _after_T_3; // @[MSHR.scala:317:26]
assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26]
wire _prior_T_3; // @[MSHR.scala:317:26]
assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26]
assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire probe_bit = io_sinkc_bits_source_0 == 6'h28; // @[Parameters.scala:46:9]
wire _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:46:9]
wire _last_probe_T; // @[MSHR.scala:459:33]
assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33]
wire _probes_done_T; // @[MSHR.scala:467:32]
assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32]
wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66]
wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}]
wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}]
wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11]
wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43]
wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75]
wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}]
wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9]
wire _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}]
wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53]
wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}]
wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42]
wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55]
wire _w_rprobeacklast_T; // @[MSHR.scala:471:55]
assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55]
wire _w_pprobeacklast_T; // @[MSHR.scala:473:55]
assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55]
wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}]
wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42]
wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}]
wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77]
wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}]
wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}]
wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32]
wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33]
wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}]
wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35]
wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40]
wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [8:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [3:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [8:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [10:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12]
wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _new_needT_T_2; // @[Parameters.scala:270:13]
assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13]
wire _new_skipProbe_T_5; // @[Parameters.scala:279:117]
assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117]
wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42]
wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _new_needT_T_6; // @[Parameters.scala:271:14]
assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14]
wire _new_skipProbe_T; // @[Parameters.scala:279:12]
assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12]
wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52]
wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89]
wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire new_clientBit = new_request_source == 6'h28; // @[Parameters.scala:46:9]
wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}]
wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}]
wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}]
wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9]
wire [3:0] prior; // @[MSHR.scala:314:26]
wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32]
wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_167 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_source_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_188
connect io_out_source_valid.clock, clock
connect io_out_source_valid.reset, reset
connect io_out_source_valid.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_source_valid.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_167( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_188 io_out_source_valid ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a29d64s8k1z3u_1 :
input clock : Clock
input reset : Reset
output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
inst monitor of TLMonitor_8
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
connect auto.out, nodeOut
connect nodeIn, auto.in
inst nodeOut_a_q of Queue2_TLBundleA_a29d64s8k1z3u_1
connect nodeOut_a_q.clock, clock
connect nodeOut_a_q.reset, reset
connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid
connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt
connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data
connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask
connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address
connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source
connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size
connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param
connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode
connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready
connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits
connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid
connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready
inst nodeIn_d_q of Queue2_TLBundleD_a29d64s8k1z3u_1
connect nodeIn_d_q.clock, clock
connect nodeIn_d_q.reset, reset
connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid
connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt
connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data
connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied
connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink
connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source
connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size
connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param
connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode
connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready
connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits
connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid
connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<29>(0h0)
connect _WIRE.bits.source, UInt<8>(0h0)
connect _WIRE.bits.size, UInt<3>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.valid, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<29>(0h0)
connect _WIRE_2.bits.source, UInt<8>(0h0)
connect _WIRE_2.bits.size, UInt<3>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.ready, UInt<1>(0h1)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.mask, UInt<8>(0h0)
connect _WIRE_6.bits.address, UInt<29>(0h0)
connect _WIRE_6.bits.source, UInt<8>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<2>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
connect _WIRE_7.ready, UInt<1>(0h1)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<29>(0h0)
connect _WIRE_8.bits.source, UInt<8>(0h0)
connect _WIRE_8.bits.size, UInt<3>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
connect _WIRE_9.valid, UInt<1>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_10.bits.sink, UInt<1>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
connect _WIRE_11.valid, UInt<1>(0h0)
extmodule plusarg_reader_18 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_19 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLBuffer_a29d64s8k1z3u_1( // @[Buffer.scala:40:9]
input clock, // @[Buffer.scala:40:9]
input reset, // @[Buffer.scala:40:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [28:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [28:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [7:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [28:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9]
wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9]
wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire [7:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9]
wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9]
wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9]
wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9]
wire [7:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9]
wire [28:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9]
wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [7:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [28:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9]
wire [7:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_a_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
wire [7:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
wire [7:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
wire [28:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_out_a_valid_0; // @[Buffer.scala:40:9]
wire auto_out_d_ready_0; // @[Buffer.scala:40:9]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9]
TLMonitor_8 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
Queue2_TLBundleA_a29d64s8k1z3u_1 nodeOut_a_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_a_ready),
.io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_a_valid),
.io_deq_bits_opcode (nodeOut_a_bits_opcode),
.io_deq_bits_param (nodeOut_a_bits_param),
.io_deq_bits_size (nodeOut_a_bits_size),
.io_deq_bits_source (nodeOut_a_bits_source),
.io_deq_bits_address (nodeOut_a_bits_address),
.io_deq_bits_mask (nodeOut_a_bits_mask),
.io_deq_bits_data (nodeOut_a_bits_data),
.io_deq_bits_corrupt (nodeOut_a_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleD_a29d64s8k1z3u_1 nodeIn_d_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeOut_d_ready),
.io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17]
.io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17]
.io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17]
.io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17]
.io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17]
.io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17]
.io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17]
.io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17]
.io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_d_valid),
.io_deq_bits_opcode (nodeIn_d_bits_opcode),
.io_deq_bits_param (nodeIn_d_bits_param),
.io_deq_bits_size (nodeIn_d_bits_size),
.io_deq_bits_source (nodeIn_d_bits_source),
.io_deq_bits_sink (nodeIn_d_bits_sink),
.io_deq_bits_denied (nodeIn_d_bits_denied),
.io_deq_bits_data (nodeIn_d_bits_data),
.io_deq_bits_corrupt (nodeIn_d_bits_corrupt)
); // @[Decoupled.scala:362:21]
assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9]
assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_224 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_408
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_224( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_408 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_169 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_169( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_208 :
output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node rawIn_exp = bits(io.in, 31, 23)
node _rawIn_isZero_T = bits(rawIn_exp, 8, 6)
node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0))
node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7)
node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3))
wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T)
connect rawIn.isNaN, _rawIn_out_isNaN_T_1
node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0))
node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1)
connect rawIn.isInf, _rawIn_out_isInf_T_2
connect rawIn.isZero, rawIn_isZero
node _rawIn_out_sign_T = bits(io.in, 32, 32)
connect rawIn.sign, _rawIn_out_sign_T
node _rawIn_out_sExp_T = cvt(rawIn_exp)
connect rawIn.sExp, _rawIn_out_sExp_T
node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0))
node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T)
node _rawIn_out_sig_T_2 = bits(io.in, 22, 0)
node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2)
connect rawIn.sig, _rawIn_out_sig_T_3
node _io_out_T = shl(io.in, 0)
connect io.out, _io_out_T
node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22)
node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0))
node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0))
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RecFNToRecFN_208( // @[RecFNToRecFN.scala:44:5]
input [32:0] io_in, // @[RecFNToRecFN.scala:48:16]
output [32:0] io_out // @[RecFNToRecFN.scala:48:16]
);
wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5]
wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35]
wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54]
wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5]
wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5]
wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35]
wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}]
wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46]
assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54]
assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFN_e8_s24_16 :
output io : { flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
inst mulAddRecFNToRaw_preMul of MulAddRecFNToRaw_preMul_e8_s24_16
inst mulAddRecFNToRaw_postMul of MulAddRecFNToRaw_postMul_e8_s24_16
connect mulAddRecFNToRaw_preMul.io.op, io.op
connect mulAddRecFNToRaw_preMul.io.a, io.a
connect mulAddRecFNToRaw_preMul.io.b, io.b
connect mulAddRecFNToRaw_preMul.io.c, io.c
node _mulAddResult_T = mul(mulAddRecFNToRaw_preMul.io.mulAddA, mulAddRecFNToRaw_preMul.io.mulAddB)
node mulAddResult = add(_mulAddResult_T, mulAddRecFNToRaw_preMul.io.mulAddC)
connect mulAddRecFNToRaw_postMul.io.fromPreMul.bit0AlignedSigC, mulAddRecFNToRaw_preMul.io.toPostMul.bit0AlignedSigC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.highAlignedSigC, mulAddRecFNToRaw_preMul.io.toPostMul.highAlignedSigC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.CDom_CAlignDist, mulAddRecFNToRaw_preMul.io.toPostMul.CDom_CAlignDist
connect mulAddRecFNToRaw_postMul.io.fromPreMul.CIsDominant, mulAddRecFNToRaw_preMul.io.toPostMul.CIsDominant
connect mulAddRecFNToRaw_postMul.io.fromPreMul.doSubMags, mulAddRecFNToRaw_preMul.io.toPostMul.doSubMags
connect mulAddRecFNToRaw_postMul.io.fromPreMul.sExpSum, mulAddRecFNToRaw_preMul.io.toPostMul.sExpSum
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroC, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfC, mulAddRecFNToRaw_preMul.io.toPostMul.isInfC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNC, mulAddRecFNToRaw_preMul.io.toPostMul.isNaNC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.signProd, mulAddRecFNToRaw_preMul.io.toPostMul.signProd
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroB, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroB
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfB, mulAddRecFNToRaw_preMul.io.toPostMul.isInfB
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroA, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroA
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfA, mulAddRecFNToRaw_preMul.io.toPostMul.isInfA
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNAOrB, mulAddRecFNToRaw_preMul.io.toPostMul.isNaNAOrB
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isSigNaNAny, mulAddRecFNToRaw_preMul.io.toPostMul.isSigNaNAny
connect mulAddRecFNToRaw_postMul.io.mulAddResult, mulAddResult
connect mulAddRecFNToRaw_postMul.io.roundingMode, io.roundingMode
inst roundRawFNToRecFN of RoundRawFNToRecFN_e8_s24_28
connect roundRawFNToRecFN.io.invalidExc, mulAddRecFNToRaw_postMul.io.invalidExc
connect roundRawFNToRecFN.io.infiniteExc, UInt<1>(0h0)
connect roundRawFNToRecFN.io.in.sig, mulAddRecFNToRaw_postMul.io.rawOut.sig
connect roundRawFNToRecFN.io.in.sExp, mulAddRecFNToRaw_postMul.io.rawOut.sExp
connect roundRawFNToRecFN.io.in.sign, mulAddRecFNToRaw_postMul.io.rawOut.sign
connect roundRawFNToRecFN.io.in.isZero, mulAddRecFNToRaw_postMul.io.rawOut.isZero
connect roundRawFNToRecFN.io.in.isInf, mulAddRecFNToRaw_postMul.io.rawOut.isInf
connect roundRawFNToRecFN.io.in.isNaN, mulAddRecFNToRaw_postMul.io.rawOut.isNaN
connect roundRawFNToRecFN.io.roundingMode, io.roundingMode
connect roundRawFNToRecFN.io.detectTininess, io.detectTininess
connect io.out, roundRawFNToRecFN.io.out
connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags | module MulAddRecFN_e8_s24_16(); // @[MulAddRecFN.scala:300:7]
wire [47:0] _mulAddResult_T = 48'h400000000000; // @[MulAddRecFN.scala:327:45]
wire [48:0] mulAddResult = 49'h13FFFFFFFFFFF; // @[MulAddRecFN.scala:319:15, :328:50]
wire [4:0] io_exceptionFlags = 5'h0; // @[MulAddRecFN.scala:300:7, :303:16, :339:15]
wire io_detectTininess = 1'h1; // @[MulAddRecFN.scala:300:7, :303:16, :317:15, :319:15, :339:15]
wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:300:7, :303:16, :319:15, :339:15]
wire [32:0] io_c = 33'h15800000; // @[MulAddRecFN.scala:300:7, :303:16, :317:15]
wire [32:0] io_b = 33'h80000000; // @[MulAddRecFN.scala:300:7, :303:16, :317:15]
wire [32:0] io_a = 33'h180000000; // @[MulAddRecFN.scala:300:7, :303:16, :317:15, :339:15]
wire [32:0] io_out = 33'h180000000; // @[MulAddRecFN.scala:300:7, :303:16, :317:15, :339:15]
wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:300:7, :303:16, :317:15]
MulAddRecFNToRaw_preMul_e8_s24_16 mulAddRecFNToRaw_preMul (); // @[MulAddRecFN.scala:317:15]
MulAddRecFNToRaw_postMul_e8_s24_16 mulAddRecFNToRaw_postMul (); // @[MulAddRecFN.scala:319:15]
RoundRawFNToRecFN_e8_s24_28 roundRawFNToRecFN (); // @[MulAddRecFN.scala:339:15]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_271 :
input clock : Clock
input reset : Reset
output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}}
connect io.y, io.x | module OptimizationBarrier_TLBEntryData_271( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_ppp, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PTW_5 :
input clock : Clock
input reset : Reset
output io : { flip requestor : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<39>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[0], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[0]}}[1], mem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}}, s1_kill : UInt<1>, s1_data : { data : UInt<64>, mask : UInt<8>}, flip s2_nack : UInt<1>, flip s2_nack_cause_raw : UInt<1>, s2_kill : UInt<1>, flip s2_uncached : UInt<1>, flip s2_paddr : UInt<32>, flip resp : { valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, data : UInt<64>, mask : UInt<8>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, data_raw : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip s2_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, flip s2_gpa : UInt<40>, flip s2_gpa_is_pte : UInt<1>, flip ordered : UInt<1>, flip store_pending : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>, grant : UInt<1>, tlbMiss : UInt<1>, blocked : UInt<1>, canAcceptStoreThenLoad : UInt<1>, canAcceptStoreThenRMW : UInt<1>, canAcceptLoadThenLoad : UInt<1>, storeBufferEmptyAfterLoad : UInt<1>, storeBufferEmptyAfterStore : UInt<1>}, keep_clock_enabled : UInt<1>, flip clock_enabled : UInt<1>}, dpath : { flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[0], perf : { l2miss : UInt<1>, l2hit : UInt<1>, pte_miss : UInt<1>, pte_hit : UInt<1>}, flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[0]}, clock_enabled : UInt<1>}}
regreset state : UInt<3>, clock, reset, UInt<3>(0h0)
wire l2_refill_wire : UInt<1>
inst arb of Arbiter1_Valid_PTWReq_4
connect arb.clock, clock
connect arb.reset, reset
connect arb.io.in[0], io.requestor[0].req
node _arb_io_out_ready_T = eq(state, UInt<3>(0h0))
node _arb_io_out_ready_T_1 = eq(l2_refill_wire, UInt<1>(0h0))
node _arb_io_out_ready_T_2 = and(_arb_io_out_ready_T, _arb_io_out_ready_T_1)
connect arb.io.out.ready, _arb_io_out_ready_T_2
wire _resp_valid_WIRE : UInt<1>[1]
connect _resp_valid_WIRE[0], UInt<1>(0h0)
reg resp_valid : UInt<1>[1], clock
connect resp_valid, _resp_valid_WIRE
node _clock_en_T = neq(state, UInt<3>(0h0))
node _clock_en_T_1 = or(_clock_en_T, l2_refill_wire)
node _clock_en_T_2 = or(_clock_en_T_1, arb.io.out.valid)
node _clock_en_T_3 = or(_clock_en_T_2, io.dpath.sfence.valid)
node clock_en = or(_clock_en_T_3, UInt<1>(0h0))
node _io_dpath_clock_enabled_T = and(UInt<1>(0h1), clock_en)
connect io.dpath.clock_enabled, _io_dpath_clock_enabled_T
reg invalidated : UInt<1>, clock
reg count : UInt<2>, clock
reg resp_ae_ptw : UInt<1>, clock
reg resp_ae_final : UInt<1>, clock
reg resp_pf : UInt<1>, clock
reg resp_gf : UInt<1>, clock
reg resp_hr : UInt<1>, clock
reg resp_hw : UInt<1>, clock
reg resp_hx : UInt<1>, clock
reg resp_fragmented_superpage : UInt<1>, clock
reg r_req : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}, clock
reg r_req_dest : UInt, clock
reg r_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, clock
reg r_hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, clock
reg aux_count : UInt<2>, clock
reg aux_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, clock
reg gpa_pgoff : UInt<12>, clock
reg stage2 : UInt<1>, clock
reg stage2_final : UInt<1>, clock
node satp = mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp, io.dpath.ptbr)
node _r_hgatp_initial_count_T = sub(UInt<2>(0h3), UInt<2>(0h3))
node _r_hgatp_initial_count_T_1 = tail(_r_hgatp_initial_count_T, 1)
node _r_hgatp_initial_count_T_2 = sub(_r_hgatp_initial_count_T_1, UInt<1>(0h0))
node r_hgatp_initial_count = tail(_r_hgatp_initial_count_T_2, 1)
node do_both_stages = and(r_req.vstage1, r_req.stage2)
node _max_count_T = lt(count, aux_count)
node max_count = mux(_max_count_T, aux_count, count)
node _vpn_T = and(r_req.vstage1, stage2)
node vpn = mux(_vpn_T, aux_pte.ppn, r_req.addr)
reg mem_resp_valid : UInt<1>, clock
connect mem_resp_valid, io.mem.resp.valid
reg mem_resp_data : UInt, clock
connect mem_resp_data, io.mem.resp.bits.data
wire tmp : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
wire _tmp_WIRE : UInt<64>
connect _tmp_WIRE, mem_resp_data
node _tmp_T = bits(_tmp_WIRE, 0, 0)
connect tmp.v, _tmp_T
node _tmp_T_1 = bits(_tmp_WIRE, 1, 1)
connect tmp.r, _tmp_T_1
node _tmp_T_2 = bits(_tmp_WIRE, 2, 2)
connect tmp.w, _tmp_T_2
node _tmp_T_3 = bits(_tmp_WIRE, 3, 3)
connect tmp.x, _tmp_T_3
node _tmp_T_4 = bits(_tmp_WIRE, 4, 4)
connect tmp.u, _tmp_T_4
node _tmp_T_5 = bits(_tmp_WIRE, 5, 5)
connect tmp.g, _tmp_T_5
node _tmp_T_6 = bits(_tmp_WIRE, 6, 6)
connect tmp.a, _tmp_T_6
node _tmp_T_7 = bits(_tmp_WIRE, 7, 7)
connect tmp.d, _tmp_T_7
node _tmp_T_8 = bits(_tmp_WIRE, 9, 8)
connect tmp.reserved_for_software, _tmp_T_8
node _tmp_T_9 = bits(_tmp_WIRE, 53, 10)
connect tmp.ppn, _tmp_T_9
node _tmp_T_10 = bits(_tmp_WIRE, 63, 54)
connect tmp.reserved_for_future, _tmp_T_10
wire pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
connect pte, tmp
node _res_ppn_T = eq(stage2, UInt<1>(0h0))
node _res_ppn_T_1 = and(do_both_stages, _res_ppn_T)
node _res_ppn_T_2 = bits(tmp.ppn, 26, 0)
node _res_ppn_T_3 = bits(tmp.ppn, 19, 0)
node _res_ppn_T_4 = mux(_res_ppn_T_1, _res_ppn_T_2, _res_ppn_T_3)
connect pte.ppn, _res_ppn_T_4
node _T = or(tmp.r, tmp.w)
node _T_1 = or(_T, tmp.x)
when _T_1 :
node _T_2 = leq(count, UInt<1>(0h0))
node _T_3 = bits(tmp.ppn, 17, 9)
node _T_4 = neq(_T_3, UInt<1>(0h0))
node _T_5 = and(_T_2, _T_4)
when _T_5 :
connect pte.v, UInt<1>(0h0)
node _T_6 = leq(count, UInt<1>(0h1))
node _T_7 = bits(tmp.ppn, 8, 0)
node _T_8 = neq(_T_7, UInt<1>(0h0))
node _T_9 = and(_T_6, _T_8)
when _T_9 :
connect pte.v, UInt<1>(0h0)
node _T_10 = eq(stage2, UInt<1>(0h0))
node _T_11 = and(do_both_stages, _T_10)
node _T_12 = shr(tmp.ppn, 27)
node _T_13 = neq(_T_12, UInt<1>(0h0))
node _T_14 = shr(tmp.ppn, 20)
node _T_15 = neq(_T_14, UInt<1>(0h0))
node invalid_paddr = mux(_T_11, _T_13, _T_15)
node _T_16 = eq(stage2, UInt<1>(0h0))
node _T_17 = and(do_both_stages, _T_16)
node _count_T = sub(UInt<2>(0h3), UInt<2>(0h3))
node _count_T_1 = tail(_count_T, 1)
node _count_T_2 = sub(_count_T_1, UInt<1>(0h0))
node count_1 = tail(_count_T_2, 1)
node idxs_0 = shr(tmp.ppn, 29)
wire _WIRE : UInt<15>[1]
connect _WIRE[0], idxs_0
node _T_18 = or(count_1, UInt<0>(0h0))
node _T_19 = neq(_WIRE[0], UInt<1>(0h0))
node invalid_gpa = and(_T_17, _T_19)
node _traverse_T = eq(pte.r, UInt<1>(0h0))
node _traverse_T_1 = and(pte.v, _traverse_T)
node _traverse_T_2 = eq(pte.w, UInt<1>(0h0))
node _traverse_T_3 = and(_traverse_T_1, _traverse_T_2)
node _traverse_T_4 = eq(pte.x, UInt<1>(0h0))
node _traverse_T_5 = and(_traverse_T_3, _traverse_T_4)
node _traverse_T_6 = eq(pte.d, UInt<1>(0h0))
node _traverse_T_7 = and(_traverse_T_5, _traverse_T_6)
node _traverse_T_8 = eq(pte.a, UInt<1>(0h0))
node _traverse_T_9 = and(_traverse_T_7, _traverse_T_8)
node _traverse_T_10 = eq(pte.u, UInt<1>(0h0))
node _traverse_T_11 = and(_traverse_T_9, _traverse_T_10)
node _traverse_T_12 = eq(pte.reserved_for_future, UInt<1>(0h0))
node _traverse_T_13 = and(_traverse_T_11, _traverse_T_12)
node _traverse_T_14 = eq(invalid_paddr, UInt<1>(0h0))
node _traverse_T_15 = and(_traverse_T_13, _traverse_T_14)
node _traverse_T_16 = eq(invalid_gpa, UInt<1>(0h0))
node _traverse_T_17 = and(_traverse_T_15, _traverse_T_16)
node _traverse_T_18 = lt(count, UInt<2>(0h2))
node traverse = and(_traverse_T_17, _traverse_T_18)
node _pte_addr_vpn_idxs_T = shr(vpn, 18)
node pte_addr_vpn_idxs_0 = bits(_pte_addr_vpn_idxs_T, 8, 0)
node _pte_addr_vpn_idxs_T_1 = shr(vpn, 9)
node pte_addr_vpn_idxs_1 = bits(_pte_addr_vpn_idxs_T_1, 8, 0)
node _pte_addr_vpn_idxs_T_2 = shr(vpn, 0)
node pte_addr_vpn_idxs_2 = bits(_pte_addr_vpn_idxs_T_2, 8, 0)
node _pte_addr_mask_T = eq(count, r_hgatp_initial_count)
node _pte_addr_mask_T_1 = and(stage2, _pte_addr_mask_T)
node pte_addr_mask = mux(_pte_addr_mask_T_1, UInt<9>(0h1ff), UInt<9>(0h1ff))
node _pte_addr_vpn_idx_T = eq(count, UInt<1>(0h1))
node _pte_addr_vpn_idx_T_1 = mux(_pte_addr_vpn_idx_T, pte_addr_vpn_idxs_1, pte_addr_vpn_idxs_0)
node _pte_addr_vpn_idx_T_2 = eq(count, UInt<2>(0h2))
node _pte_addr_vpn_idx_T_3 = mux(_pte_addr_vpn_idx_T_2, pte_addr_vpn_idxs_2, _pte_addr_vpn_idx_T_1)
node _pte_addr_vpn_idx_T_4 = eq(count, UInt<2>(0h3))
node _pte_addr_vpn_idx_T_5 = mux(_pte_addr_vpn_idx_T_4, pte_addr_vpn_idxs_2, _pte_addr_vpn_idx_T_3)
node pte_addr_vpn_idx = and(_pte_addr_vpn_idx_T_5, pte_addr_mask)
node _pte_addr_raw_pte_addr_T = shl(r_pte.ppn, 9)
node _pte_addr_raw_pte_addr_T_1 = or(_pte_addr_raw_pte_addr_T, pte_addr_vpn_idx)
node pte_addr_raw_pte_addr = shl(_pte_addr_raw_pte_addr_T_1, 3)
node pte_addr = bits(pte_addr_raw_pte_addr, 31, 0)
reg pte_hit : UInt<1>, clock
connect pte_hit, UInt<1>(0h0)
connect io.dpath.perf.pte_miss, UInt<1>(0h0)
node _io_dpath_perf_pte_hit_T = eq(state, UInt<3>(0h1))
node _io_dpath_perf_pte_hit_T_1 = and(pte_hit, _io_dpath_perf_pte_hit_T)
node _io_dpath_perf_pte_hit_T_2 = eq(io.dpath.perf.l2hit, UInt<1>(0h0))
node _io_dpath_perf_pte_hit_T_3 = and(_io_dpath_perf_pte_hit_T_1, _io_dpath_perf_pte_hit_T_2)
connect io.dpath.perf.pte_hit, _io_dpath_perf_pte_hit_T_3
node _T_20 = or(io.dpath.perf.pte_miss, io.dpath.perf.pte_hit)
node _T_21 = and(io.dpath.perf.l2hit, _T_20)
node _T_22 = eq(_T_21, UInt<1>(0h0))
node _T_23 = asUInt(reset)
node _T_24 = eq(_T_23, UInt<1>(0h0))
when _T_24 :
node _T_25 = eq(_T_22, UInt<1>(0h0))
when _T_25 :
printf(clock, UInt<1>(0h1), "Assertion failed: PTE Cache Hit/Miss Performance Monitor Events are lower priority than L2TLB Hit event\n at PTW.scala:395 assert(!(io.dpath.perf.l2hit && (io.dpath.perf.pte_miss || io.dpath.perf.pte_hit)),\n") : printf
assert(clock, _T_22, UInt<1>(0h1), "") : assert
reg l2_refill : UInt<1>, clock
connect l2_refill, UInt<1>(0h0)
connect l2_refill_wire, l2_refill
connect io.dpath.perf.l2miss, UInt<1>(0h0)
connect io.dpath.perf.l2hit, UInt<1>(0h0)
wire _WIRE_1 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
connect _WIRE_1.v, UInt<1>(0h0)
connect _WIRE_1.r, UInt<1>(0h0)
connect _WIRE_1.w, UInt<1>(0h0)
connect _WIRE_1.x, UInt<1>(0h0)
connect _WIRE_1.u, UInt<1>(0h0)
connect _WIRE_1.g, UInt<1>(0h0)
connect _WIRE_1.a, UInt<1>(0h0)
connect _WIRE_1.d, UInt<1>(0h0)
connect _WIRE_1.reserved_for_software, UInt<2>(0h0)
connect _WIRE_1.ppn, UInt<44>(0h0)
connect _WIRE_1.reserved_for_future, UInt<10>(0h0)
wire l2_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
connect l2_pte, _WIRE_1
node _invalidated_T = neq(state, UInt<3>(0h0))
node _invalidated_T_1 = and(invalidated, _invalidated_T)
node _invalidated_T_2 = or(io.dpath.sfence.valid, _invalidated_T_1)
connect invalidated, _invalidated_T_2
connect io.mem.keep_clock_enabled, UInt<1>(0h0)
node _io_mem_req_valid_T = eq(state, UInt<3>(0h1))
node _io_mem_req_valid_T_1 = eq(state, UInt<3>(0h3))
node _io_mem_req_valid_T_2 = or(_io_mem_req_valid_T, _io_mem_req_valid_T_1)
connect io.mem.req.valid, _io_mem_req_valid_T_2
connect io.mem.req.bits.phys, UInt<1>(0h1)
connect io.mem.req.bits.cmd, UInt<1>(0h0)
connect io.mem.req.bits.size, UInt<2>(0h3)
connect io.mem.req.bits.signed, UInt<1>(0h0)
connect io.mem.req.bits.addr, pte_addr
connect io.mem.req.bits.dprv, UInt<1>(0h1)
node _io_mem_req_bits_dv_T = eq(stage2, UInt<1>(0h0))
node _io_mem_req_bits_dv_T_1 = and(do_both_stages, _io_mem_req_bits_dv_T)
connect io.mem.req.bits.dv, _io_mem_req_bits_dv_T_1
invalidate io.mem.req.bits.tag
connect io.mem.req.bits.no_resp, UInt<1>(0h0)
invalidate io.mem.req.bits.no_alloc
invalidate io.mem.req.bits.no_xcpt
invalidate io.mem.req.bits.data
invalidate io.mem.req.bits.mask
node _io_mem_s1_kill_T = neq(state, UInt<3>(0h2))
node _io_mem_s1_kill_T_1 = or(UInt<1>(0h0), _io_mem_s1_kill_T)
node _io_mem_s1_kill_T_2 = or(_io_mem_s1_kill_T_1, resp_gf)
connect io.mem.s1_kill, _io_mem_s1_kill_T_2
invalidate io.mem.s1_data.mask
invalidate io.mem.s1_data.data
connect io.mem.s2_kill, UInt<1>(0h0)
node _pmaPgLevelHomogeneous_T = shl(r_pte.ppn, 12)
node _pmaPgLevelHomogeneous_T_1 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_2 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_3 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_4 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_5 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_6 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_7 = shl(r_pte.ppn, 12)
node _pmaPgLevelHomogeneous_T_8 = xor(_pmaPgLevelHomogeneous_T_7, UInt<28>(0hc000000))
node _pmaPgLevelHomogeneous_T_9 = cvt(_pmaPgLevelHomogeneous_T_8)
node _pmaPgLevelHomogeneous_T_10 = and(_pmaPgLevelHomogeneous_T_9, asSInt(UInt<27>(0h4000000)))
node _pmaPgLevelHomogeneous_T_11 = asSInt(_pmaPgLevelHomogeneous_T_10)
node _pmaPgLevelHomogeneous_T_12 = eq(_pmaPgLevelHomogeneous_T_11, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_13 = xor(_pmaPgLevelHomogeneous_T_7, UInt<32>(0h80000000))
node _pmaPgLevelHomogeneous_T_14 = cvt(_pmaPgLevelHomogeneous_T_13)
node _pmaPgLevelHomogeneous_T_15 = and(_pmaPgLevelHomogeneous_T_14, asSInt(UInt<29>(0h10000000)))
node _pmaPgLevelHomogeneous_T_16 = asSInt(_pmaPgLevelHomogeneous_T_15)
node _pmaPgLevelHomogeneous_T_17 = eq(_pmaPgLevelHomogeneous_T_16, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_18 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_12)
node pmaPgLevelHomogeneous_1 = or(_pmaPgLevelHomogeneous_T_18, _pmaPgLevelHomogeneous_T_17)
node _pmaPgLevelHomogeneous_T_19 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_20 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_21 = xor(_pmaPgLevelHomogeneous_T_7, UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_22 = cvt(_pmaPgLevelHomogeneous_T_21)
node _pmaPgLevelHomogeneous_T_23 = and(_pmaPgLevelHomogeneous_T_22, asSInt(UInt<33>(0h80000000)))
node _pmaPgLevelHomogeneous_T_24 = asSInt(_pmaPgLevelHomogeneous_T_23)
node _pmaPgLevelHomogeneous_T_25 = eq(_pmaPgLevelHomogeneous_T_24, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_26 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_25)
node _pmaPgLevelHomogeneous_T_27 = eq(_pmaPgLevelHomogeneous_T_26, UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_28 = xor(_pmaPgLevelHomogeneous_T_7, UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_29 = cvt(_pmaPgLevelHomogeneous_T_28)
node _pmaPgLevelHomogeneous_T_30 = and(_pmaPgLevelHomogeneous_T_29, asSInt(UInt<33>(0h80000000)))
node _pmaPgLevelHomogeneous_T_31 = asSInt(_pmaPgLevelHomogeneous_T_30)
node _pmaPgLevelHomogeneous_T_32 = eq(_pmaPgLevelHomogeneous_T_31, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_33 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_32)
node _pmaPgLevelHomogeneous_T_34 = eq(_pmaPgLevelHomogeneous_T_33, UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_35 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_36 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_37 = shl(r_pte.ppn, 12)
node _pmaPgLevelHomogeneous_T_38 = xor(_pmaPgLevelHomogeneous_T_37, UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_39 = cvt(_pmaPgLevelHomogeneous_T_38)
node _pmaPgLevelHomogeneous_T_40 = and(_pmaPgLevelHomogeneous_T_39, asSInt(UInt<14>(0h2000)))
node _pmaPgLevelHomogeneous_T_41 = asSInt(_pmaPgLevelHomogeneous_T_40)
node _pmaPgLevelHomogeneous_T_42 = eq(_pmaPgLevelHomogeneous_T_41, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_43 = xor(_pmaPgLevelHomogeneous_T_37, UInt<14>(0h3000))
node _pmaPgLevelHomogeneous_T_44 = cvt(_pmaPgLevelHomogeneous_T_43)
node _pmaPgLevelHomogeneous_T_45 = and(_pmaPgLevelHomogeneous_T_44, asSInt(UInt<13>(0h1000)))
node _pmaPgLevelHomogeneous_T_46 = asSInt(_pmaPgLevelHomogeneous_T_45)
node _pmaPgLevelHomogeneous_T_47 = eq(_pmaPgLevelHomogeneous_T_46, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_48 = xor(_pmaPgLevelHomogeneous_T_37, UInt<17>(0h10000))
node _pmaPgLevelHomogeneous_T_49 = cvt(_pmaPgLevelHomogeneous_T_48)
node _pmaPgLevelHomogeneous_T_50 = and(_pmaPgLevelHomogeneous_T_49, asSInt(UInt<17>(0h10000)))
node _pmaPgLevelHomogeneous_T_51 = asSInt(_pmaPgLevelHomogeneous_T_50)
node _pmaPgLevelHomogeneous_T_52 = eq(_pmaPgLevelHomogeneous_T_51, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_53 = xor(_pmaPgLevelHomogeneous_T_37, UInt<18>(0h20000))
node _pmaPgLevelHomogeneous_T_54 = cvt(_pmaPgLevelHomogeneous_T_53)
node _pmaPgLevelHomogeneous_T_55 = and(_pmaPgLevelHomogeneous_T_54, asSInt(UInt<15>(0h4000)))
node _pmaPgLevelHomogeneous_T_56 = asSInt(_pmaPgLevelHomogeneous_T_55)
node _pmaPgLevelHomogeneous_T_57 = eq(_pmaPgLevelHomogeneous_T_56, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_58 = xor(_pmaPgLevelHomogeneous_T_37, UInt<18>(0h24000))
node _pmaPgLevelHomogeneous_T_59 = cvt(_pmaPgLevelHomogeneous_T_58)
node _pmaPgLevelHomogeneous_T_60 = and(_pmaPgLevelHomogeneous_T_59, asSInt(UInt<13>(0h1000)))
node _pmaPgLevelHomogeneous_T_61 = asSInt(_pmaPgLevelHomogeneous_T_60)
node _pmaPgLevelHomogeneous_T_62 = eq(_pmaPgLevelHomogeneous_T_61, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_63 = xor(_pmaPgLevelHomogeneous_T_37, UInt<21>(0h100000))
node _pmaPgLevelHomogeneous_T_64 = cvt(_pmaPgLevelHomogeneous_T_63)
node _pmaPgLevelHomogeneous_T_65 = and(_pmaPgLevelHomogeneous_T_64, asSInt(UInt<18>(0h2f000)))
node _pmaPgLevelHomogeneous_T_66 = asSInt(_pmaPgLevelHomogeneous_T_65)
node _pmaPgLevelHomogeneous_T_67 = eq(_pmaPgLevelHomogeneous_T_66, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_68 = xor(_pmaPgLevelHomogeneous_T_37, UInt<26>(0h2000000))
node _pmaPgLevelHomogeneous_T_69 = cvt(_pmaPgLevelHomogeneous_T_68)
node _pmaPgLevelHomogeneous_T_70 = and(_pmaPgLevelHomogeneous_T_69, asSInt(UInt<17>(0h10000)))
node _pmaPgLevelHomogeneous_T_71 = asSInt(_pmaPgLevelHomogeneous_T_70)
node _pmaPgLevelHomogeneous_T_72 = eq(_pmaPgLevelHomogeneous_T_71, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_73 = xor(_pmaPgLevelHomogeneous_T_37, UInt<26>(0h2010000))
node _pmaPgLevelHomogeneous_T_74 = cvt(_pmaPgLevelHomogeneous_T_73)
node _pmaPgLevelHomogeneous_T_75 = and(_pmaPgLevelHomogeneous_T_74, asSInt(UInt<13>(0h1000)))
node _pmaPgLevelHomogeneous_T_76 = asSInt(_pmaPgLevelHomogeneous_T_75)
node _pmaPgLevelHomogeneous_T_77 = eq(_pmaPgLevelHomogeneous_T_76, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_78 = xor(_pmaPgLevelHomogeneous_T_37, UInt<28>(0h8000000))
node _pmaPgLevelHomogeneous_T_79 = cvt(_pmaPgLevelHomogeneous_T_78)
node _pmaPgLevelHomogeneous_T_80 = and(_pmaPgLevelHomogeneous_T_79, asSInt(UInt<17>(0h10000)))
node _pmaPgLevelHomogeneous_T_81 = asSInt(_pmaPgLevelHomogeneous_T_80)
node _pmaPgLevelHomogeneous_T_82 = eq(_pmaPgLevelHomogeneous_T_81, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_83 = xor(_pmaPgLevelHomogeneous_T_37, UInt<28>(0hc000000))
node _pmaPgLevelHomogeneous_T_84 = cvt(_pmaPgLevelHomogeneous_T_83)
node _pmaPgLevelHomogeneous_T_85 = and(_pmaPgLevelHomogeneous_T_84, asSInt(UInt<27>(0h4000000)))
node _pmaPgLevelHomogeneous_T_86 = asSInt(_pmaPgLevelHomogeneous_T_85)
node _pmaPgLevelHomogeneous_T_87 = eq(_pmaPgLevelHomogeneous_T_86, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_88 = xor(_pmaPgLevelHomogeneous_T_37, UInt<29>(0h10020000))
node _pmaPgLevelHomogeneous_T_89 = cvt(_pmaPgLevelHomogeneous_T_88)
node _pmaPgLevelHomogeneous_T_90 = and(_pmaPgLevelHomogeneous_T_89, asSInt(UInt<13>(0h1000)))
node _pmaPgLevelHomogeneous_T_91 = asSInt(_pmaPgLevelHomogeneous_T_90)
node _pmaPgLevelHomogeneous_T_92 = eq(_pmaPgLevelHomogeneous_T_91, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_93 = xor(_pmaPgLevelHomogeneous_T_37, UInt<32>(0h80000000))
node _pmaPgLevelHomogeneous_T_94 = cvt(_pmaPgLevelHomogeneous_T_93)
node _pmaPgLevelHomogeneous_T_95 = and(_pmaPgLevelHomogeneous_T_94, asSInt(UInt<29>(0h10000000)))
node _pmaPgLevelHomogeneous_T_96 = asSInt(_pmaPgLevelHomogeneous_T_95)
node _pmaPgLevelHomogeneous_T_97 = eq(_pmaPgLevelHomogeneous_T_96, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_98 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_42)
node _pmaPgLevelHomogeneous_T_99 = or(_pmaPgLevelHomogeneous_T_98, _pmaPgLevelHomogeneous_T_47)
node _pmaPgLevelHomogeneous_T_100 = or(_pmaPgLevelHomogeneous_T_99, _pmaPgLevelHomogeneous_T_52)
node _pmaPgLevelHomogeneous_T_101 = or(_pmaPgLevelHomogeneous_T_100, _pmaPgLevelHomogeneous_T_57)
node _pmaPgLevelHomogeneous_T_102 = or(_pmaPgLevelHomogeneous_T_101, _pmaPgLevelHomogeneous_T_62)
node _pmaPgLevelHomogeneous_T_103 = or(_pmaPgLevelHomogeneous_T_102, _pmaPgLevelHomogeneous_T_67)
node _pmaPgLevelHomogeneous_T_104 = or(_pmaPgLevelHomogeneous_T_103, _pmaPgLevelHomogeneous_T_72)
node _pmaPgLevelHomogeneous_T_105 = or(_pmaPgLevelHomogeneous_T_104, _pmaPgLevelHomogeneous_T_77)
node _pmaPgLevelHomogeneous_T_106 = or(_pmaPgLevelHomogeneous_T_105, _pmaPgLevelHomogeneous_T_82)
node _pmaPgLevelHomogeneous_T_107 = or(_pmaPgLevelHomogeneous_T_106, _pmaPgLevelHomogeneous_T_87)
node _pmaPgLevelHomogeneous_T_108 = or(_pmaPgLevelHomogeneous_T_107, _pmaPgLevelHomogeneous_T_92)
node pmaPgLevelHomogeneous_2 = or(_pmaPgLevelHomogeneous_T_108, _pmaPgLevelHomogeneous_T_97)
node _pmaPgLevelHomogeneous_T_109 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_110 = xor(_pmaPgLevelHomogeneous_T_37, UInt<17>(0h10000))
node _pmaPgLevelHomogeneous_T_111 = cvt(_pmaPgLevelHomogeneous_T_110)
node _pmaPgLevelHomogeneous_T_112 = and(_pmaPgLevelHomogeneous_T_111, asSInt(UInt<33>(0h8a130000)))
node _pmaPgLevelHomogeneous_T_113 = asSInt(_pmaPgLevelHomogeneous_T_112)
node _pmaPgLevelHomogeneous_T_114 = eq(_pmaPgLevelHomogeneous_T_113, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_115 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_114)
node _pmaPgLevelHomogeneous_T_116 = eq(_pmaPgLevelHomogeneous_T_115, UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_117 = xor(_pmaPgLevelHomogeneous_T_37, UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_118 = cvt(_pmaPgLevelHomogeneous_T_117)
node _pmaPgLevelHomogeneous_T_119 = and(_pmaPgLevelHomogeneous_T_118, asSInt(UInt<33>(0hffff3000)))
node _pmaPgLevelHomogeneous_T_120 = asSInt(_pmaPgLevelHomogeneous_T_119)
node _pmaPgLevelHomogeneous_T_121 = eq(_pmaPgLevelHomogeneous_T_120, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_122 = xor(_pmaPgLevelHomogeneous_T_37, UInt<14>(0h3000))
node _pmaPgLevelHomogeneous_T_123 = cvt(_pmaPgLevelHomogeneous_T_122)
node _pmaPgLevelHomogeneous_T_124 = and(_pmaPgLevelHomogeneous_T_123, asSInt(UInt<33>(0hffff3000)))
node _pmaPgLevelHomogeneous_T_125 = asSInt(_pmaPgLevelHomogeneous_T_124)
node _pmaPgLevelHomogeneous_T_126 = eq(_pmaPgLevelHomogeneous_T_125, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_127 = xor(_pmaPgLevelHomogeneous_T_37, UInt<17>(0h10000))
node _pmaPgLevelHomogeneous_T_128 = cvt(_pmaPgLevelHomogeneous_T_127)
node _pmaPgLevelHomogeneous_T_129 = and(_pmaPgLevelHomogeneous_T_128, asSInt(UInt<33>(0hffff0000)))
node _pmaPgLevelHomogeneous_T_130 = asSInt(_pmaPgLevelHomogeneous_T_129)
node _pmaPgLevelHomogeneous_T_131 = eq(_pmaPgLevelHomogeneous_T_130, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_132 = xor(_pmaPgLevelHomogeneous_T_37, UInt<28>(0h8000000))
node _pmaPgLevelHomogeneous_T_133 = cvt(_pmaPgLevelHomogeneous_T_132)
node _pmaPgLevelHomogeneous_T_134 = and(_pmaPgLevelHomogeneous_T_133, asSInt(UInt<33>(0hffff0000)))
node _pmaPgLevelHomogeneous_T_135 = asSInt(_pmaPgLevelHomogeneous_T_134)
node _pmaPgLevelHomogeneous_T_136 = eq(_pmaPgLevelHomogeneous_T_135, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_137 = xor(_pmaPgLevelHomogeneous_T_37, UInt<32>(0h80000000))
node _pmaPgLevelHomogeneous_T_138 = cvt(_pmaPgLevelHomogeneous_T_137)
node _pmaPgLevelHomogeneous_T_139 = and(_pmaPgLevelHomogeneous_T_138, asSInt(UInt<33>(0hf0000000)))
node _pmaPgLevelHomogeneous_T_140 = asSInt(_pmaPgLevelHomogeneous_T_139)
node _pmaPgLevelHomogeneous_T_141 = eq(_pmaPgLevelHomogeneous_T_140, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_142 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_121)
node _pmaPgLevelHomogeneous_T_143 = or(_pmaPgLevelHomogeneous_T_142, _pmaPgLevelHomogeneous_T_126)
node _pmaPgLevelHomogeneous_T_144 = or(_pmaPgLevelHomogeneous_T_143, _pmaPgLevelHomogeneous_T_131)
node _pmaPgLevelHomogeneous_T_145 = or(_pmaPgLevelHomogeneous_T_144, _pmaPgLevelHomogeneous_T_136)
node _pmaPgLevelHomogeneous_T_146 = or(_pmaPgLevelHomogeneous_T_145, _pmaPgLevelHomogeneous_T_141)
node _pmaPgLevelHomogeneous_T_147 = xor(_pmaPgLevelHomogeneous_T_37, UInt<28>(0h8000000))
node _pmaPgLevelHomogeneous_T_148 = cvt(_pmaPgLevelHomogeneous_T_147)
node _pmaPgLevelHomogeneous_T_149 = and(_pmaPgLevelHomogeneous_T_148, asSInt(UInt<33>(0h8e020000)))
node _pmaPgLevelHomogeneous_T_150 = asSInt(_pmaPgLevelHomogeneous_T_149)
node _pmaPgLevelHomogeneous_T_151 = eq(_pmaPgLevelHomogeneous_T_150, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_152 = xor(_pmaPgLevelHomogeneous_T_37, UInt<32>(0h80000000))
node _pmaPgLevelHomogeneous_T_153 = cvt(_pmaPgLevelHomogeneous_T_152)
node _pmaPgLevelHomogeneous_T_154 = and(_pmaPgLevelHomogeneous_T_153, asSInt(UInt<33>(0h80000000)))
node _pmaPgLevelHomogeneous_T_155 = asSInt(_pmaPgLevelHomogeneous_T_154)
node _pmaPgLevelHomogeneous_T_156 = eq(_pmaPgLevelHomogeneous_T_155, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_157 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_151)
node _pmaPgLevelHomogeneous_T_158 = or(_pmaPgLevelHomogeneous_T_157, _pmaPgLevelHomogeneous_T_156)
node _pmaPgLevelHomogeneous_T_159 = xor(_pmaPgLevelHomogeneous_T_37, UInt<17>(0h10000))
node _pmaPgLevelHomogeneous_T_160 = cvt(_pmaPgLevelHomogeneous_T_159)
node _pmaPgLevelHomogeneous_T_161 = and(_pmaPgLevelHomogeneous_T_160, asSInt(UInt<33>(0h8a130000)))
node _pmaPgLevelHomogeneous_T_162 = asSInt(_pmaPgLevelHomogeneous_T_161)
node _pmaPgLevelHomogeneous_T_163 = eq(_pmaPgLevelHomogeneous_T_162, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_164 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_163)
node _pmaPgLevelHomogeneous_T_165 = eq(_pmaPgLevelHomogeneous_T_164, UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_166 = xor(_pmaPgLevelHomogeneous_T_37, UInt<17>(0h10000))
node _pmaPgLevelHomogeneous_T_167 = cvt(_pmaPgLevelHomogeneous_T_166)
node _pmaPgLevelHomogeneous_T_168 = and(_pmaPgLevelHomogeneous_T_167, asSInt(UInt<33>(0h8a130000)))
node _pmaPgLevelHomogeneous_T_169 = asSInt(_pmaPgLevelHomogeneous_T_168)
node _pmaPgLevelHomogeneous_T_170 = eq(_pmaPgLevelHomogeneous_T_169, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_171 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_170)
node _pmaPgLevelHomogeneous_T_172 = eq(_pmaPgLevelHomogeneous_T_171, UInt<1>(0h0))
node _pmaHomogeneous_T = eq(count, UInt<1>(0h1))
node _pmaHomogeneous_T_1 = mux(_pmaHomogeneous_T, pmaPgLevelHomogeneous_1, UInt<1>(0h0))
node _pmaHomogeneous_T_2 = eq(count, UInt<2>(0h2))
node _pmaHomogeneous_T_3 = mux(_pmaHomogeneous_T_2, pmaPgLevelHomogeneous_2, _pmaHomogeneous_T_1)
node _pmaHomogeneous_T_4 = eq(count, UInt<2>(0h3))
node pmaHomogeneous = mux(_pmaHomogeneous_T_4, pmaPgLevelHomogeneous_2, _pmaHomogeneous_T_3)
node _pmpHomogeneous_T = shl(r_pte.ppn, 12)
wire _pmpHomogeneous_WIRE : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect _pmpHomogeneous_WIRE.mask, UInt<32>(0h0)
connect _pmpHomogeneous_WIRE.addr, UInt<30>(0h0)
connect _pmpHomogeneous_WIRE.cfg.r, UInt<1>(0h0)
connect _pmpHomogeneous_WIRE.cfg.w, UInt<1>(0h0)
connect _pmpHomogeneous_WIRE.cfg.x, UInt<1>(0h0)
connect _pmpHomogeneous_WIRE.cfg.a, UInt<2>(0h0)
connect _pmpHomogeneous_WIRE.cfg.res, UInt<2>(0h0)
connect _pmpHomogeneous_WIRE.cfg.l, UInt<1>(0h0)
node homogeneous = and(pmaHomogeneous, UInt<1>(0h1))
connect io.requestor[0].resp.valid, resp_valid[0]
connect io.requestor[0].resp.bits.ae_ptw, resp_ae_ptw
connect io.requestor[0].resp.bits.ae_final, resp_ae_final
connect io.requestor[0].resp.bits.pf, resp_pf
connect io.requestor[0].resp.bits.gf, resp_gf
connect io.requestor[0].resp.bits.hr, resp_hr
connect io.requestor[0].resp.bits.hw, resp_hw
connect io.requestor[0].resp.bits.hx, resp_hx
connect io.requestor[0].resp.bits.pte, r_pte
connect io.requestor[0].resp.bits.level, max_count
node _io_requestor_0_resp_bits_homogeneous_T = or(homogeneous, UInt<1>(0h0))
connect io.requestor[0].resp.bits.homogeneous, _io_requestor_0_resp_bits_homogeneous_T
node _io_requestor_0_resp_bits_fragmented_superpage_T = and(resp_fragmented_superpage, UInt<1>(0h0))
connect io.requestor[0].resp.bits.fragmented_superpage, _io_requestor_0_resp_bits_fragmented_superpage_T
connect io.requestor[0].resp.bits.gpa.valid, r_req.need_gpa
node _io_requestor_0_resp_bits_gpa_bits_T = eq(stage2_final, UInt<1>(0h0))
node _io_requestor_0_resp_bits_gpa_bits_T_1 = eq(r_req.vstage1, UInt<1>(0h0))
node _io_requestor_0_resp_bits_gpa_bits_T_2 = or(_io_requestor_0_resp_bits_gpa_bits_T, _io_requestor_0_resp_bits_gpa_bits_T_1)
node _io_requestor_0_resp_bits_gpa_bits_T_3 = eq(aux_count, UInt<2>(0h2))
node _io_requestor_0_resp_bits_gpa_bits_T_4 = or(_io_requestor_0_resp_bits_gpa_bits_T_2, _io_requestor_0_resp_bits_gpa_bits_T_3)
node _io_requestor_0_resp_bits_gpa_bits_T_5 = shr(aux_pte.ppn, 18)
node _io_requestor_0_resp_bits_gpa_bits_T_6 = bits(r_req.addr, 17, 0)
node _io_requestor_0_resp_bits_gpa_bits_T_7 = cat(_io_requestor_0_resp_bits_gpa_bits_T_5, _io_requestor_0_resp_bits_gpa_bits_T_6)
node _io_requestor_0_resp_bits_gpa_bits_T_8 = shr(aux_pte.ppn, 9)
node _io_requestor_0_resp_bits_gpa_bits_T_9 = bits(r_req.addr, 8, 0)
node _io_requestor_0_resp_bits_gpa_bits_T_10 = cat(_io_requestor_0_resp_bits_gpa_bits_T_8, _io_requestor_0_resp_bits_gpa_bits_T_9)
node _io_requestor_0_resp_bits_gpa_bits_truncIdx_T = or(aux_count, UInt<1>(0h0))
node io_requestor_0_resp_bits_gpa_bits_truncIdx = bits(_io_requestor_0_resp_bits_gpa_bits_truncIdx_T, 0, 0)
node _io_requestor_0_resp_bits_gpa_bits_T_11 = eq(io_requestor_0_resp_bits_gpa_bits_truncIdx, UInt<1>(0h1))
node _io_requestor_0_resp_bits_gpa_bits_T_12 = mux(_io_requestor_0_resp_bits_gpa_bits_T_11, _io_requestor_0_resp_bits_gpa_bits_T_10, _io_requestor_0_resp_bits_gpa_bits_T_7)
node _io_requestor_0_resp_bits_gpa_bits_T_13 = mux(_io_requestor_0_resp_bits_gpa_bits_T_4, aux_pte.ppn, _io_requestor_0_resp_bits_gpa_bits_T_12)
node _io_requestor_0_resp_bits_gpa_bits_T_14 = cat(_io_requestor_0_resp_bits_gpa_bits_T_13, gpa_pgoff)
connect io.requestor[0].resp.bits.gpa.bits, _io_requestor_0_resp_bits_gpa_bits_T_14
node _io_requestor_0_resp_bits_gpa_is_pte_T = eq(stage2_final, UInt<1>(0h0))
connect io.requestor[0].resp.bits.gpa_is_pte, _io_requestor_0_resp_bits_gpa_is_pte_T
connect io.requestor[0].ptbr, io.dpath.ptbr
connect io.requestor[0].hgatp, io.dpath.hgatp
connect io.requestor[0].vsatp, io.dpath.vsatp
connect io.requestor[0].customCSRs, io.dpath.customCSRs
connect io.requestor[0].status, io.dpath.status
connect io.requestor[0].hstatus, io.dpath.hstatus
connect io.requestor[0].gstatus, io.dpath.gstatus
connect io.requestor[0].pmp, io.dpath.pmp
wire next_state : UInt
connect next_state, state
inst state_barrier of OptimizationBarrier_UInt_5
connect state_barrier.clock, clock
connect state_barrier.reset, reset
connect state_barrier.io.x, next_state
connect state, state_barrier.io.y
wire do_switch : UInt<1>
connect do_switch, UInt<1>(0h0)
node _T_26 = eq(UInt<3>(0h0), state)
when _T_26 :
node _T_27 = and(arb.io.out.ready, arb.io.out.valid)
when _T_27 :
node _satp_initial_count_T = sub(UInt<2>(0h3), UInt<2>(0h3))
node _satp_initial_count_T_1 = tail(_satp_initial_count_T, 1)
node _satp_initial_count_T_2 = sub(_satp_initial_count_T_1, UInt<1>(0h0))
node satp_initial_count = tail(_satp_initial_count_T_2, 1)
node _vsatp_initial_count_T = sub(UInt<2>(0h3), UInt<2>(0h3))
node _vsatp_initial_count_T_1 = tail(_vsatp_initial_count_T, 1)
node _vsatp_initial_count_T_2 = sub(_vsatp_initial_count_T_1, UInt<1>(0h0))
node vsatp_initial_count = tail(_vsatp_initial_count_T_2, 1)
node _hgatp_initial_count_T = sub(UInt<2>(0h3), UInt<2>(0h3))
node _hgatp_initial_count_T_1 = tail(_hgatp_initial_count_T, 1)
node _hgatp_initial_count_T_2 = sub(_hgatp_initial_count_T_1, UInt<1>(0h0))
node hgatp_initial_count = tail(_hgatp_initial_count_T_2, 1)
node aux_ppn = mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp.ppn, arb.io.out.bits.bits.addr)
connect r_req, arb.io.out.bits.bits
connect r_req_dest, arb.io.chosen
node _next_state_T = mux(arb.io.out.bits.valid, UInt<3>(0h1), UInt<3>(0h0))
connect next_state, _next_state_T
connect stage2, arb.io.out.bits.bits.stage2
node _stage2_final_T = eq(arb.io.out.bits.bits.vstage1, UInt<1>(0h0))
node _stage2_final_T_1 = and(arb.io.out.bits.bits.stage2, _stage2_final_T)
connect stage2_final, _stage2_final_T_1
node _count_T_3 = mux(arb.io.out.bits.bits.stage2, hgatp_initial_count, satp_initial_count)
connect count, _count_T_3
node _aux_count_T = mux(arb.io.out.bits.bits.vstage1, vsatp_initial_count, UInt<1>(0h0))
connect aux_count, _aux_count_T
connect aux_pte.ppn, aux_ppn
connect aux_pte.reserved_for_future, UInt<1>(0h0)
connect resp_ae_ptw, UInt<1>(0h0)
connect resp_ae_final, UInt<1>(0h0)
connect resp_pf, UInt<1>(0h0)
node _resp_gf_count_T = sub(UInt<2>(0h3), UInt<2>(0h3))
node _resp_gf_count_T_1 = tail(_resp_gf_count_T, 1)
node _resp_gf_count_T_2 = sub(_resp_gf_count_T_1, UInt<1>(0h0))
node resp_gf_count = tail(_resp_gf_count_T_2, 1)
node resp_gf_idxs_0 = shr(aux_ppn, 29)
wire _resp_gf_WIRE : UInt<15>[1]
connect _resp_gf_WIRE[0], resp_gf_idxs_0
node _resp_gf_T = or(resp_gf_count, UInt<0>(0h0))
node _resp_gf_T_1 = neq(_resp_gf_WIRE[0], UInt<1>(0h0))
node _resp_gf_T_2 = and(_resp_gf_T_1, arb.io.out.bits.bits.stage2)
connect resp_gf, _resp_gf_T_2
connect resp_hr, UInt<1>(0h1)
connect resp_hw, UInt<1>(0h1)
connect resp_hx, UInt<1>(0h1)
connect resp_fragmented_superpage, UInt<1>(0h0)
connect r_hgatp, io.dpath.hgatp
node _T_28 = eq(arb.io.out.bits.bits.need_gpa, UInt<1>(0h0))
node _T_29 = or(_T_28, arb.io.out.bits.bits.stage2)
node _T_30 = asUInt(reset)
node _T_31 = eq(_T_30, UInt<1>(0h0))
when _T_31 :
node _T_32 = eq(_T_29, UInt<1>(0h0))
when _T_32 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at PTW.scala:610 assert(!arb.io.out.bits.bits.need_gpa || arb.io.out.bits.bits.stage2)\n") : printf_1
assert(clock, _T_29, UInt<1>(0h1), "") : assert_1
else :
node _T_33 = eq(UInt<3>(0h1), state)
when _T_33 :
node _T_34 = eq(count, r_hgatp_initial_count)
node _T_35 = and(stage2, _T_34)
when _T_35 :
node _gpa_pgoff_T = eq(aux_count, UInt<2>(0h2))
node _gpa_pgoff_T_1 = shl(r_req.addr, 3)
node _gpa_pgoff_T_2 = mux(_gpa_pgoff_T, _gpa_pgoff_T_1, UInt<1>(0h0))
connect gpa_pgoff, _gpa_pgoff_T_2
when UInt<1>(0h0) :
node _aux_count_T_1 = add(aux_count, UInt<1>(0h1))
node _aux_count_T_2 = tail(_aux_count_T_1, 1)
connect aux_count, _aux_count_T_2
connect aux_pte.ppn, UInt<1>(0h0)
connect aux_pte.reserved_for_future, UInt<1>(0h0)
connect pte_hit, UInt<1>(0h1)
else :
when UInt<1>(0h0) :
node _count_T_4 = add(count, UInt<1>(0h1))
node _count_T_5 = tail(_count_T_4, 1)
connect count, _count_T_5
connect pte_hit, UInt<1>(0h1)
else :
node _next_state_T_1 = mux(io.mem.req.ready, UInt<3>(0h2), UInt<3>(0h1))
connect next_state, _next_state_T_1
when resp_gf :
connect next_state, UInt<3>(0h0)
wire _WIRE_2 : UInt
connect _WIRE_2, UInt<1>(0h0)
connect resp_valid[_WIRE_2], UInt<1>(0h1)
else :
node _T_36 = eq(UInt<3>(0h2), state)
when _T_36 :
node _next_state_T_2 = mux(UInt<1>(0h0), UInt<3>(0h1), UInt<3>(0h4))
connect next_state, _next_state_T_2
else :
node _T_37 = eq(UInt<3>(0h4), state)
when _T_37 :
connect next_state, UInt<3>(0h5)
node _io_dpath_perf_pte_miss_T = lt(count, UInt<2>(0h2))
connect io.dpath.perf.pte_miss, _io_dpath_perf_pte_miss_T
when io.mem.s2_xcpt.ae.ld :
connect resp_ae_ptw, UInt<1>(0h1)
connect next_state, UInt<3>(0h0)
wire _WIRE_3 : UInt
connect _WIRE_3, UInt<1>(0h0)
connect resp_valid[_WIRE_3], UInt<1>(0h1)
else :
node _T_38 = eq(UInt<3>(0h7), state)
when _T_38 :
connect next_state, UInt<3>(0h0)
wire _WIRE_4 : UInt
connect _WIRE_4, UInt<1>(0h0)
connect resp_valid[_WIRE_4], UInt<1>(0h1)
node _T_39 = eq(homogeneous, UInt<1>(0h0))
when _T_39 :
connect count, UInt<2>(0h2)
connect resp_fragmented_superpage, UInt<1>(0h1)
when do_both_stages :
connect resp_fragmented_superpage, UInt<1>(0h1)
node _merged_pte_superpage_mask_T = mux(stage2_final, max_count, UInt<2>(0h2))
node _merged_pte_superpage_mask_T_1 = eq(_merged_pte_superpage_mask_T, UInt<1>(0h1))
node _merged_pte_superpage_mask_T_2 = mux(_merged_pte_superpage_mask_T_1, UInt<44>(0hffffffffe00), UInt<44>(0hffffffc0000))
node _merged_pte_superpage_mask_T_3 = eq(_merged_pte_superpage_mask_T, UInt<2>(0h2))
node _merged_pte_superpage_mask_T_4 = mux(_merged_pte_superpage_mask_T_3, UInt<44>(0hfffffffffff), _merged_pte_superpage_mask_T_2)
node _merged_pte_superpage_mask_T_5 = eq(_merged_pte_superpage_mask_T, UInt<2>(0h3))
node merged_pte_superpage_mask = mux(_merged_pte_superpage_mask_T_5, UInt<44>(0hfffffffffff), _merged_pte_superpage_mask_T_4)
node _merged_pte_stage1_ppns_T = bits(pte.ppn, 43, 18)
node _merged_pte_stage1_ppns_T_1 = bits(aux_pte.ppn, 17, 0)
node merged_pte_stage1_ppns_0 = cat(_merged_pte_stage1_ppns_T, _merged_pte_stage1_ppns_T_1)
node _merged_pte_stage1_ppns_T_2 = bits(pte.ppn, 43, 9)
node _merged_pte_stage1_ppns_T_3 = bits(aux_pte.ppn, 8, 0)
node merged_pte_stage1_ppns_1 = cat(_merged_pte_stage1_ppns_T_2, _merged_pte_stage1_ppns_T_3)
node _merged_pte_stage1_ppn_T = eq(count, UInt<1>(0h1))
node _merged_pte_stage1_ppn_T_1 = mux(_merged_pte_stage1_ppn_T, merged_pte_stage1_ppns_1, merged_pte_stage1_ppns_0)
node _merged_pte_stage1_ppn_T_2 = eq(count, UInt<2>(0h2))
node _merged_pte_stage1_ppn_T_3 = mux(_merged_pte_stage1_ppn_T_2, pte.ppn, _merged_pte_stage1_ppn_T_1)
node _merged_pte_stage1_ppn_T_4 = eq(count, UInt<2>(0h3))
node merged_pte_stage1_ppn = mux(_merged_pte_stage1_ppn_T_4, pte.ppn, _merged_pte_stage1_ppn_T_3)
node _merged_pte_T = and(merged_pte_stage1_ppn, merged_pte_superpage_mask)
wire merged_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
connect merged_pte, aux_pte
connect merged_pte.ppn, _merged_pte_T
node _r_pte_T = eq(UInt<1>(0h0), UInt<1>(0h0))
node _r_pte_T_1 = and(UInt<1>(0h0), _r_pte_T)
node _r_pte_T_2 = eq(resp_gf, UInt<1>(0h0))
node _r_pte_T_3 = and(_r_pte_T_1, _r_pte_T_2)
node _r_pte_T_4 = eq(state, UInt<3>(0h1))
node _r_pte_T_5 = and(_r_pte_T_4, UInt<1>(0h0))
node _r_pte_count_T = sub(UInt<2>(0h3), UInt<2>(0h3))
node _r_pte_count_T_1 = tail(_r_pte_count_T, 1)
node _r_pte_count_T_2 = sub(_r_pte_count_T_1, UInt<1>(0h0))
node r_pte_count = tail(_r_pte_count_T_2, 1)
node r_pte_idxs_0 = shr(UInt<1>(0h0), 27)
wire r_pte_lsbs : UInt<2>
connect r_pte_lsbs, r_pte_idxs_0
wire r_pte_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
connect r_pte_pte, l2_pte
node _r_pte_pte_ppn_T = shr(r_hgatp.ppn, 2)
node _r_pte_pte_ppn_T_1 = cat(_r_pte_pte_ppn_T, r_pte_lsbs)
connect r_pte_pte.ppn, _r_pte_pte_ppn_T_1
node _r_pte_T_6 = eq(state, UInt<3>(0h1))
node _r_pte_T_7 = and(_r_pte_T_6, UInt<1>(0h0))
wire r_pte_pte_1 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
connect r_pte_pte_1, l2_pte
connect r_pte_pte_1.ppn, UInt<1>(0h0)
node _r_pte_count_T_3 = sub(UInt<2>(0h3), UInt<2>(0h3))
node _r_pte_count_T_4 = tail(_r_pte_count_T_3, 1)
node _r_pte_count_T_5 = sub(_r_pte_count_T_4, UInt<1>(0h0))
node r_pte_count_1 = tail(_r_pte_count_T_5, 1)
node r_pte_idxs_0_1 = shr(pte.ppn, 27)
wire r_pte_lsbs_1 : UInt<2>
connect r_pte_lsbs_1, r_pte_idxs_0_1
wire r_pte_pte_2 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
connect r_pte_pte_2, r_pte
node _r_pte_pte_ppn_T_2 = shr(r_hgatp.ppn, 2)
node _r_pte_pte_ppn_T_3 = cat(_r_pte_pte_ppn_T_2, r_pte_lsbs_1)
connect r_pte_pte_2.ppn, _r_pte_pte_ppn_T_3
node _r_pte_T_8 = eq(traverse, UInt<1>(0h0))
node _r_pte_T_9 = and(_r_pte_T_8, r_req.vstage1)
node _r_pte_T_10 = and(_r_pte_T_9, stage2)
node _r_pte_T_11 = mux(_r_pte_T_10, merged_pte, pte)
node _r_pte_T_12 = eq(state, UInt<3>(0h7))
node _r_pte_T_13 = eq(homogeneous, UInt<1>(0h0))
node _r_pte_T_14 = and(_r_pte_T_12, _r_pte_T_13)
node _r_pte_T_15 = neq(count, UInt<2>(0h2))
node _r_pte_T_16 = and(_r_pte_T_14, _r_pte_T_15)
node _r_pte_T_17 = shr(r_pte.ppn, 18)
node _r_pte_T_18 = bits(r_req.addr, 17, 0)
node _r_pte_T_19 = cat(_r_pte_T_17, _r_pte_T_18)
node _r_pte_T_20 = shr(r_pte.ppn, 9)
node _r_pte_T_21 = bits(r_req.addr, 8, 0)
node _r_pte_T_22 = cat(_r_pte_T_20, _r_pte_T_21)
node _r_pte_truncIdx_T = or(count, UInt<1>(0h0))
node r_pte_truncIdx = bits(_r_pte_truncIdx_T, 0, 0)
node _r_pte_T_23 = eq(r_pte_truncIdx, UInt<1>(0h1))
node _r_pte_T_24 = mux(_r_pte_T_23, _r_pte_T_22, _r_pte_T_19)
wire r_pte_pte_3 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
connect r_pte_pte_3, r_pte
connect r_pte_pte_3.ppn, _r_pte_T_24
node _r_pte_T_25 = and(arb.io.out.ready, arb.io.out.valid)
node _r_pte_count_T_6 = sub(UInt<2>(0h3), UInt<2>(0h3))
node _r_pte_count_T_7 = tail(_r_pte_count_T_6, 1)
node _r_pte_count_T_8 = sub(_r_pte_count_T_7, UInt<1>(0h0))
node r_pte_count_2 = tail(_r_pte_count_T_8, 1)
node r_pte_idxs_0_2 = shr(io.dpath.vsatp.ppn, 27)
wire r_pte_lsbs_2 : UInt<2>
connect r_pte_lsbs_2, r_pte_idxs_0_2
wire r_pte_pte_4 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
connect r_pte_pte_4, r_pte
node _r_pte_pte_ppn_T_4 = shr(io.dpath.hgatp.ppn, 2)
node _r_pte_pte_ppn_T_5 = cat(_r_pte_pte_ppn_T_4, r_pte_lsbs_2)
connect r_pte_pte_4.ppn, _r_pte_pte_ppn_T_5
wire r_pte_pte_5 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
connect r_pte_pte_5, r_pte
connect r_pte_pte_5.ppn, satp.ppn
node _r_pte_T_26 = mux(arb.io.out.bits.bits.stage2, r_pte_pte_4, r_pte_pte_5)
node _r_pte_T_27 = mux(_r_pte_T_25, _r_pte_T_26, r_pte)
node _r_pte_T_28 = mux(_r_pte_T_16, r_pte_pte_3, _r_pte_T_27)
node _r_pte_T_29 = mux(mem_resp_valid, _r_pte_T_11, _r_pte_T_28)
node _r_pte_T_30 = mux(do_switch, r_pte_pte_2, _r_pte_T_29)
node _r_pte_T_31 = mux(_r_pte_T_7, r_pte_pte_1, _r_pte_T_30)
node _r_pte_T_32 = mux(_r_pte_T_5, r_pte_pte, _r_pte_T_31)
node _r_pte_T_33 = mux(_r_pte_T_3, l2_pte, _r_pte_T_32)
inst r_pte_barrier of OptimizationBarrier_PTE_5
connect r_pte_barrier.clock, clock
connect r_pte_barrier.reset, reset
connect r_pte_barrier.io.x.v, _r_pte_T_33.v
connect r_pte_barrier.io.x.r, _r_pte_T_33.r
connect r_pte_barrier.io.x.w, _r_pte_T_33.w
connect r_pte_barrier.io.x.x, _r_pte_T_33.x
connect r_pte_barrier.io.x.u, _r_pte_T_33.u
connect r_pte_barrier.io.x.g, _r_pte_T_33.g
connect r_pte_barrier.io.x.a, _r_pte_T_33.a
connect r_pte_barrier.io.x.d, _r_pte_T_33.d
connect r_pte_barrier.io.x.reserved_for_software, _r_pte_T_33.reserved_for_software
connect r_pte_barrier.io.x.ppn, _r_pte_T_33.ppn
connect r_pte_barrier.io.x.reserved_for_future, _r_pte_T_33.reserved_for_future
connect r_pte, r_pte_barrier.io.y
node _T_40 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_41 = and(UInt<1>(0h0), _T_40)
node _T_42 = eq(resp_gf, UInt<1>(0h0))
node _T_43 = and(_T_41, _T_42)
when _T_43 :
node _T_44 = eq(state, UInt<3>(0h1))
node _T_45 = eq(state, UInt<3>(0h2))
node _T_46 = or(_T_44, _T_45)
node _T_47 = asUInt(reset)
node _T_48 = eq(_T_47, UInt<1>(0h0))
when _T_48 :
node _T_49 = eq(_T_46, UInt<1>(0h0))
when _T_49 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at PTW.scala:686 assert(state === s_req || state === s_wait1)\n") : printf_2
assert(clock, _T_46, UInt<1>(0h1), "") : assert_2
connect next_state, UInt<3>(0h0)
wire _WIRE_5 : UInt
connect _WIRE_5, UInt<1>(0h0)
connect resp_valid[_WIRE_5], UInt<1>(0h1)
connect count, UInt<2>(0h2)
when mem_resp_valid :
node _T_50 = eq(state, UInt<3>(0h5))
node _T_51 = asUInt(reset)
node _T_52 = eq(_T_51, UInt<1>(0h0))
when _T_52 :
node _T_53 = eq(_T_50, UInt<1>(0h0))
when _T_53 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at PTW.scala:692 assert(state === s_wait3)\n") : printf_3
assert(clock, _T_50, UInt<1>(0h1), "") : assert_3
connect next_state, UInt<3>(0h1)
when traverse :
node _T_54 = eq(stage2, UInt<1>(0h0))
node _T_55 = and(do_both_stages, _T_54)
when _T_55 :
connect do_switch, UInt<1>(0h1)
node _count_T_6 = add(count, UInt<1>(0h1))
node _count_T_7 = tail(_count_T_6, 1)
connect count, _count_T_7
else :
node _gf_T = eq(stage2_final, UInt<1>(0h0))
node _gf_T_1 = and(stage2, _gf_T)
node _gf_T_2 = eq(pte.w, UInt<1>(0h0))
node _gf_T_3 = and(pte.x, _gf_T_2)
node _gf_T_4 = or(pte.r, _gf_T_3)
node _gf_T_5 = and(pte.v, _gf_T_4)
node _gf_T_6 = and(_gf_T_5, pte.a)
node _gf_T_7 = and(_gf_T_6, pte.r)
node _gf_T_8 = and(_gf_T_7, pte.u)
node _gf_T_9 = eq(_gf_T_8, UInt<1>(0h0))
node _gf_T_10 = and(_gf_T_1, _gf_T_9)
node _gf_T_11 = eq(pte.w, UInt<1>(0h0))
node _gf_T_12 = and(pte.x, _gf_T_11)
node _gf_T_13 = or(pte.r, _gf_T_12)
node _gf_T_14 = and(pte.v, _gf_T_13)
node _gf_T_15 = and(_gf_T_14, pte.a)
node _gf_T_16 = eq(pte.reserved_for_future, UInt<1>(0h0))
node _gf_T_17 = and(_gf_T_15, _gf_T_16)
node _gf_T_18 = and(_gf_T_17, invalid_gpa)
node gf = or(_gf_T_10, _gf_T_18)
node ae = and(pte.v, invalid_paddr)
node _pf_T = neq(pte.reserved_for_future, UInt<1>(0h0))
node pf = and(pte.v, _pf_T)
node _success_T = eq(ae, UInt<1>(0h0))
node _success_T_1 = and(pte.v, _success_T)
node _success_T_2 = eq(pf, UInt<1>(0h0))
node _success_T_3 = and(_success_T_1, _success_T_2)
node _success_T_4 = eq(gf, UInt<1>(0h0))
node success = and(_success_T_3, _success_T_4)
node _T_56 = eq(stage2_final, UInt<1>(0h0))
node _T_57 = and(do_both_stages, _T_56)
node _T_58 = and(_T_57, success)
when _T_58 :
when stage2 :
connect stage2, UInt<1>(0h0)
connect count, aux_count
else :
connect stage2_final, UInt<1>(0h1)
connect do_switch, UInt<1>(0h1)
else :
node _l2_refill_T = eq(count, UInt<2>(0h2))
node _l2_refill_T_1 = and(success, _l2_refill_T)
node _l2_refill_T_2 = eq(r_req.need_gpa, UInt<1>(0h0))
node _l2_refill_T_3 = and(_l2_refill_T_1, _l2_refill_T_2)
node _l2_refill_T_4 = eq(r_req.vstage1, UInt<1>(0h0))
node _l2_refill_T_5 = eq(r_req.stage2, UInt<1>(0h0))
node _l2_refill_T_6 = and(_l2_refill_T_4, _l2_refill_T_5)
node _l2_refill_T_7 = eq(aux_count, UInt<2>(0h2))
node _l2_refill_T_8 = and(do_both_stages, _l2_refill_T_7)
node _l2_refill_T_9 = eq(pte.w, UInt<1>(0h0))
node _l2_refill_T_10 = and(pte.x, _l2_refill_T_9)
node _l2_refill_T_11 = or(pte.r, _l2_refill_T_10)
node _l2_refill_T_12 = and(pte.v, _l2_refill_T_11)
node _l2_refill_T_13 = and(_l2_refill_T_12, pte.a)
node _l2_refill_T_14 = and(_l2_refill_T_13, pte.w)
node _l2_refill_T_15 = and(_l2_refill_T_14, pte.d)
node _l2_refill_T_16 = and(_l2_refill_T_15, pte.u)
node _l2_refill_T_17 = eq(pte.w, UInt<1>(0h0))
node _l2_refill_T_18 = and(pte.x, _l2_refill_T_17)
node _l2_refill_T_19 = or(pte.r, _l2_refill_T_18)
node _l2_refill_T_20 = and(pte.v, _l2_refill_T_19)
node _l2_refill_T_21 = and(_l2_refill_T_20, pte.a)
node _l2_refill_T_22 = and(_l2_refill_T_21, pte.x)
node _l2_refill_T_23 = and(_l2_refill_T_22, pte.u)
node _l2_refill_T_24 = and(_l2_refill_T_16, _l2_refill_T_23)
node _l2_refill_T_25 = and(_l2_refill_T_8, _l2_refill_T_24)
node _l2_refill_T_26 = or(_l2_refill_T_6, _l2_refill_T_25)
node _l2_refill_T_27 = and(_l2_refill_T_3, _l2_refill_T_26)
connect l2_refill, _l2_refill_T_27
connect count, max_count
node _T_59 = eq(count, UInt<2>(0h2))
node _T_60 = eq(do_both_stages, UInt<1>(0h0))
node _T_61 = eq(aux_count, UInt<2>(0h2))
node _T_62 = or(_T_60, _T_61)
node _T_63 = and(_T_59, _T_62)
node _T_64 = eq(_T_63, UInt<1>(0h0))
node _T_65 = and(UInt<1>(0h0), _T_64)
when _T_65 :
connect next_state, UInt<3>(0h7)
else :
connect next_state, UInt<3>(0h0)
wire _WIRE_6 : UInt
connect _WIRE_6, UInt<1>(0h0)
connect resp_valid[_WIRE_6], UInt<1>(0h1)
node _resp_ae_ptw_T = lt(count, UInt<2>(0h2))
node _resp_ae_ptw_T_1 = and(ae, _resp_ae_ptw_T)
node _resp_ae_ptw_T_2 = eq(pte.r, UInt<1>(0h0))
node _resp_ae_ptw_T_3 = and(pte.v, _resp_ae_ptw_T_2)
node _resp_ae_ptw_T_4 = eq(pte.w, UInt<1>(0h0))
node _resp_ae_ptw_T_5 = and(_resp_ae_ptw_T_3, _resp_ae_ptw_T_4)
node _resp_ae_ptw_T_6 = eq(pte.x, UInt<1>(0h0))
node _resp_ae_ptw_T_7 = and(_resp_ae_ptw_T_5, _resp_ae_ptw_T_6)
node _resp_ae_ptw_T_8 = eq(pte.d, UInt<1>(0h0))
node _resp_ae_ptw_T_9 = and(_resp_ae_ptw_T_7, _resp_ae_ptw_T_8)
node _resp_ae_ptw_T_10 = eq(pte.a, UInt<1>(0h0))
node _resp_ae_ptw_T_11 = and(_resp_ae_ptw_T_9, _resp_ae_ptw_T_10)
node _resp_ae_ptw_T_12 = eq(pte.u, UInt<1>(0h0))
node _resp_ae_ptw_T_13 = and(_resp_ae_ptw_T_11, _resp_ae_ptw_T_12)
node _resp_ae_ptw_T_14 = eq(pte.reserved_for_future, UInt<1>(0h0))
node _resp_ae_ptw_T_15 = and(_resp_ae_ptw_T_13, _resp_ae_ptw_T_14)
node _resp_ae_ptw_T_16 = and(_resp_ae_ptw_T_1, _resp_ae_ptw_T_15)
connect resp_ae_ptw, _resp_ae_ptw_T_16
node _resp_ae_final_T = eq(pte.w, UInt<1>(0h0))
node _resp_ae_final_T_1 = and(pte.x, _resp_ae_final_T)
node _resp_ae_final_T_2 = or(pte.r, _resp_ae_final_T_1)
node _resp_ae_final_T_3 = and(pte.v, _resp_ae_final_T_2)
node _resp_ae_final_T_4 = and(_resp_ae_final_T_3, pte.a)
node _resp_ae_final_T_5 = and(ae, _resp_ae_final_T_4)
connect resp_ae_final, _resp_ae_final_T_5
node _resp_pf_T = eq(stage2, UInt<1>(0h0))
node _resp_pf_T_1 = and(pf, _resp_pf_T)
connect resp_pf, _resp_pf_T_1
node _resp_gf_T_3 = and(pf, stage2)
node _resp_gf_T_4 = or(gf, _resp_gf_T_3)
connect resp_gf, _resp_gf_T_4
node _resp_hr_T = eq(stage2, UInt<1>(0h0))
node _resp_hr_T_1 = eq(pf, UInt<1>(0h0))
node _resp_hr_T_2 = eq(gf, UInt<1>(0h0))
node _resp_hr_T_3 = and(_resp_hr_T_1, _resp_hr_T_2)
node _resp_hr_T_4 = eq(pte.w, UInt<1>(0h0))
node _resp_hr_T_5 = and(pte.x, _resp_hr_T_4)
node _resp_hr_T_6 = or(pte.r, _resp_hr_T_5)
node _resp_hr_T_7 = and(pte.v, _resp_hr_T_6)
node _resp_hr_T_8 = and(_resp_hr_T_7, pte.a)
node _resp_hr_T_9 = and(_resp_hr_T_8, pte.r)
node _resp_hr_T_10 = and(_resp_hr_T_9, pte.u)
node _resp_hr_T_11 = and(_resp_hr_T_3, _resp_hr_T_10)
node _resp_hr_T_12 = or(_resp_hr_T, _resp_hr_T_11)
connect resp_hr, _resp_hr_T_12
node _resp_hw_T = eq(stage2, UInt<1>(0h0))
node _resp_hw_T_1 = eq(pf, UInt<1>(0h0))
node _resp_hw_T_2 = eq(gf, UInt<1>(0h0))
node _resp_hw_T_3 = and(_resp_hw_T_1, _resp_hw_T_2)
node _resp_hw_T_4 = eq(pte.w, UInt<1>(0h0))
node _resp_hw_T_5 = and(pte.x, _resp_hw_T_4)
node _resp_hw_T_6 = or(pte.r, _resp_hw_T_5)
node _resp_hw_T_7 = and(pte.v, _resp_hw_T_6)
node _resp_hw_T_8 = and(_resp_hw_T_7, pte.a)
node _resp_hw_T_9 = and(_resp_hw_T_8, pte.w)
node _resp_hw_T_10 = and(_resp_hw_T_9, pte.d)
node _resp_hw_T_11 = and(_resp_hw_T_10, pte.u)
node _resp_hw_T_12 = and(_resp_hw_T_3, _resp_hw_T_11)
node _resp_hw_T_13 = or(_resp_hw_T, _resp_hw_T_12)
connect resp_hw, _resp_hw_T_13
node _resp_hx_T = eq(stage2, UInt<1>(0h0))
node _resp_hx_T_1 = eq(pf, UInt<1>(0h0))
node _resp_hx_T_2 = eq(gf, UInt<1>(0h0))
node _resp_hx_T_3 = and(_resp_hx_T_1, _resp_hx_T_2)
node _resp_hx_T_4 = eq(pte.w, UInt<1>(0h0))
node _resp_hx_T_5 = and(pte.x, _resp_hx_T_4)
node _resp_hx_T_6 = or(pte.r, _resp_hx_T_5)
node _resp_hx_T_7 = and(pte.v, _resp_hx_T_6)
node _resp_hx_T_8 = and(_resp_hx_T_7, pte.a)
node _resp_hx_T_9 = and(_resp_hx_T_8, pte.x)
node _resp_hx_T_10 = and(_resp_hx_T_9, pte.u)
node _resp_hx_T_11 = and(_resp_hx_T_3, _resp_hx_T_10)
node _resp_hx_T_12 = or(_resp_hx_T, _resp_hx_T_11)
connect resp_hx, _resp_hx_T_12
when io.mem.s2_nack :
node _T_66 = eq(state, UInt<3>(0h4))
node _T_67 = asUInt(reset)
node _T_68 = eq(_T_67, UInt<1>(0h0))
when _T_68 :
node _T_69 = eq(_T_66, UInt<1>(0h0))
when _T_69 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at PTW.scala:736 assert(state === s_wait2)\n") : printf_4
assert(clock, _T_66, UInt<1>(0h1), "") : assert_4
connect next_state, UInt<3>(0h1)
when do_switch :
node _aux_count_T_3 = add(count, UInt<1>(0h1))
node _aux_count_T_4 = tail(_aux_count_T_3, 1)
node _aux_count_T_5 = mux(traverse, _aux_count_T_4, count)
connect aux_count, _aux_count_T_5
connect count, r_hgatp_initial_count
node _aux_pte_s1_ppns_T = bits(pte.ppn, 43, 18)
node _aux_pte_s1_ppns_T_1 = bits(r_req.addr, 17, 0)
node aux_pte_s1_ppns_0 = cat(_aux_pte_s1_ppns_T, _aux_pte_s1_ppns_T_1)
node _aux_pte_s1_ppns_T_2 = bits(pte.ppn, 43, 9)
node _aux_pte_s1_ppns_T_3 = bits(r_req.addr, 8, 0)
node aux_pte_s1_ppns_1 = cat(_aux_pte_s1_ppns_T_2, _aux_pte_s1_ppns_T_3)
node _aux_pte_T = eq(count, UInt<1>(0h1))
node _aux_pte_T_1 = mux(_aux_pte_T, aux_pte_s1_ppns_1, aux_pte_s1_ppns_0)
node _aux_pte_T_2 = eq(count, UInt<2>(0h2))
node _aux_pte_T_3 = mux(_aux_pte_T_2, pte.ppn, _aux_pte_T_1)
node _aux_pte_T_4 = eq(count, UInt<2>(0h3))
node _aux_pte_T_5 = mux(_aux_pte_T_4, pte.ppn, _aux_pte_T_3)
wire aux_pte_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
connect aux_pte_pte, pte
connect aux_pte_pte.ppn, _aux_pte_T_5
node _aux_pte_T_6 = mux(traverse, pte, aux_pte_pte)
connect aux_pte, _aux_pte_T_6
connect stage2, UInt<1>(0h1)
node _leaf_T = eq(traverse, UInt<1>(0h0))
node _leaf_T_1 = and(mem_resp_valid, _leaf_T)
node _leaf_T_2 = eq(count, UInt<1>(0h0))
node leaf = and(_leaf_T_1, _leaf_T_2)
node _T_70 = and(leaf, pte.v)
node _T_71 = eq(invalid_paddr, UInt<1>(0h0))
node _T_72 = and(_T_70, _T_71)
node _T_73 = eq(invalid_gpa, UInt<1>(0h0))
node _T_74 = and(_T_72, _T_73)
node _T_75 = eq(pte.reserved_for_future, UInt<1>(0h0))
node _T_76 = and(_T_74, _T_75)
node _T_77 = and(leaf, pte.v)
node _T_78 = and(_T_77, invalid_paddr)
node _T_79 = and(leaf, pte.v)
node _T_80 = and(_T_79, invalid_gpa)
node _T_81 = and(leaf, pte.v)
node _T_82 = neq(pte.reserved_for_future, UInt<1>(0h0))
node _T_83 = and(_T_81, _T_82)
node _T_84 = bits(mem_resp_data, 0, 0)
node _T_85 = eq(_T_84, UInt<1>(0h0))
node _T_86 = and(leaf, _T_85)
node _T_87 = eq(pte.v, UInt<1>(0h0))
node _T_88 = and(leaf, _T_87)
node _T_89 = bits(mem_resp_data, 0, 0)
node _T_90 = and(_T_88, _T_89)
node _leaf_T_3 = eq(traverse, UInt<1>(0h0))
node _leaf_T_4 = and(mem_resp_valid, _leaf_T_3)
node _leaf_T_5 = eq(count, UInt<1>(0h1))
node leaf_1 = and(_leaf_T_4, _leaf_T_5)
node _T_91 = and(leaf_1, pte.v)
node _T_92 = eq(invalid_paddr, UInt<1>(0h0))
node _T_93 = and(_T_91, _T_92)
node _T_94 = eq(invalid_gpa, UInt<1>(0h0))
node _T_95 = and(_T_93, _T_94)
node _T_96 = eq(pte.reserved_for_future, UInt<1>(0h0))
node _T_97 = and(_T_95, _T_96)
node _T_98 = and(leaf_1, pte.v)
node _T_99 = and(_T_98, invalid_paddr)
node _T_100 = and(leaf_1, pte.v)
node _T_101 = and(_T_100, invalid_gpa)
node _T_102 = and(leaf_1, pte.v)
node _T_103 = neq(pte.reserved_for_future, UInt<1>(0h0))
node _T_104 = and(_T_102, _T_103)
node _T_105 = bits(mem_resp_data, 0, 0)
node _T_106 = eq(_T_105, UInt<1>(0h0))
node _T_107 = and(leaf_1, _T_106)
node _T_108 = eq(pte.v, UInt<1>(0h0))
node _T_109 = and(leaf_1, _T_108)
node _T_110 = bits(mem_resp_data, 0, 0)
node _T_111 = and(_T_109, _T_110)
node _leaf_T_6 = eq(traverse, UInt<1>(0h0))
node _leaf_T_7 = and(mem_resp_valid, _leaf_T_6)
node _leaf_T_8 = eq(count, UInt<2>(0h2))
node leaf_2 = and(_leaf_T_7, _leaf_T_8)
node _T_112 = and(leaf_2, pte.v)
node _T_113 = eq(invalid_paddr, UInt<1>(0h0))
node _T_114 = and(_T_112, _T_113)
node _T_115 = eq(invalid_gpa, UInt<1>(0h0))
node _T_116 = and(_T_114, _T_115)
node _T_117 = eq(pte.reserved_for_future, UInt<1>(0h0))
node _T_118 = and(_T_116, _T_117)
node _T_119 = and(leaf_2, pte.v)
node _T_120 = and(_T_119, invalid_paddr)
node _T_121 = and(leaf_2, pte.v)
node _T_122 = and(_T_121, invalid_gpa)
node _T_123 = and(leaf_2, pte.v)
node _T_124 = neq(pte.reserved_for_future, UInt<1>(0h0))
node _T_125 = and(_T_123, _T_124)
node _T_126 = bits(mem_resp_data, 0, 0)
node _T_127 = eq(_T_126, UInt<1>(0h0))
node _T_128 = and(leaf_2, _T_127)
node _T_129 = eq(count, UInt<2>(0h2))
node _T_130 = and(mem_resp_valid, _T_129)
node _T_131 = eq(pte.r, UInt<1>(0h0))
node _T_132 = and(pte.v, _T_131)
node _T_133 = eq(pte.w, UInt<1>(0h0))
node _T_134 = and(_T_132, _T_133)
node _T_135 = eq(pte.x, UInt<1>(0h0))
node _T_136 = and(_T_134, _T_135)
node _T_137 = eq(pte.d, UInt<1>(0h0))
node _T_138 = and(_T_136, _T_137)
node _T_139 = eq(pte.a, UInt<1>(0h0))
node _T_140 = and(_T_138, _T_139)
node _T_141 = eq(pte.u, UInt<1>(0h0))
node _T_142 = and(_T_140, _T_141)
node _T_143 = eq(pte.reserved_for_future, UInt<1>(0h0))
node _T_144 = and(_T_142, _T_143)
node _T_145 = and(_T_130, _T_144)
node _T_146 = eq(state, UInt<3>(0h4))
node _T_147 = and(_T_146, io.mem.s2_xcpt.ae.ld) | module PTW_5( // @[PTW.scala:219:7]
input clock, // @[PTW.scala:219:7]
input reset, // @[PTW.scala:219:7]
output io_requestor_0_req_ready, // @[PTW.scala:220:14]
input io_requestor_0_req_valid, // @[PTW.scala:220:14]
input [26:0] io_requestor_0_req_bits_bits_addr, // @[PTW.scala:220:14]
input io_requestor_0_req_bits_bits_need_gpa, // @[PTW.scala:220:14]
output io_requestor_0_resp_valid, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_ae_ptw, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_ae_final, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_pf, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_gf, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_hr, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_hw, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_hx, // @[PTW.scala:220:14]
output [9:0] io_requestor_0_resp_bits_pte_reserved_for_future, // @[PTW.scala:220:14]
output [43:0] io_requestor_0_resp_bits_pte_ppn, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_resp_bits_pte_reserved_for_software, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_pte_d, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_pte_a, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_pte_g, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_pte_u, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_pte_x, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_pte_w, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_pte_r, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_pte_v, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_resp_bits_level, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_homogeneous, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_gpa_valid, // @[PTW.scala:220:14]
output [38:0] io_requestor_0_resp_bits_gpa_bits, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_gpa_is_pte, // @[PTW.scala:220:14]
output [3:0] io_requestor_0_ptbr_mode, // @[PTW.scala:220:14]
output [15:0] io_requestor_0_ptbr_asid, // @[PTW.scala:220:14]
output [43:0] io_requestor_0_ptbr_ppn, // @[PTW.scala:220:14]
output io_requestor_0_status_debug, // @[PTW.scala:220:14]
output io_requestor_0_status_cease, // @[PTW.scala:220:14]
output io_requestor_0_status_wfi, // @[PTW.scala:220:14]
output [31:0] io_requestor_0_status_isa, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_status_dprv, // @[PTW.scala:220:14]
output io_requestor_0_status_dv, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_status_prv, // @[PTW.scala:220:14]
output io_requestor_0_status_v, // @[PTW.scala:220:14]
output io_requestor_0_status_sd, // @[PTW.scala:220:14]
output [22:0] io_requestor_0_status_zero2, // @[PTW.scala:220:14]
output io_requestor_0_status_mpv, // @[PTW.scala:220:14]
output io_requestor_0_status_gva, // @[PTW.scala:220:14]
output io_requestor_0_status_mbe, // @[PTW.scala:220:14]
output io_requestor_0_status_sbe, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_status_sxl, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_status_uxl, // @[PTW.scala:220:14]
output io_requestor_0_status_sd_rv32, // @[PTW.scala:220:14]
output [7:0] io_requestor_0_status_zero1, // @[PTW.scala:220:14]
output io_requestor_0_status_tsr, // @[PTW.scala:220:14]
output io_requestor_0_status_tw, // @[PTW.scala:220:14]
output io_requestor_0_status_tvm, // @[PTW.scala:220:14]
output io_requestor_0_status_mxr, // @[PTW.scala:220:14]
output io_requestor_0_status_sum, // @[PTW.scala:220:14]
output io_requestor_0_status_mprv, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_status_xs, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_status_fs, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_status_mpp, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_status_vs, // @[PTW.scala:220:14]
output io_requestor_0_status_spp, // @[PTW.scala:220:14]
output io_requestor_0_status_mpie, // @[PTW.scala:220:14]
output io_requestor_0_status_ube, // @[PTW.scala:220:14]
output io_requestor_0_status_spie, // @[PTW.scala:220:14]
output io_requestor_0_status_upie, // @[PTW.scala:220:14]
output io_requestor_0_status_mie, // @[PTW.scala:220:14]
output io_requestor_0_status_hie, // @[PTW.scala:220:14]
output io_requestor_0_status_sie, // @[PTW.scala:220:14]
output io_requestor_0_status_uie, // @[PTW.scala:220:14]
input io_mem_req_ready, // @[PTW.scala:220:14]
output io_mem_req_valid, // @[PTW.scala:220:14]
output [39:0] io_mem_req_bits_addr, // @[PTW.scala:220:14]
output io_mem_req_bits_dv, // @[PTW.scala:220:14]
output io_mem_s1_kill, // @[PTW.scala:220:14]
input io_mem_s2_nack, // @[PTW.scala:220:14]
input io_mem_s2_nack_cause_raw, // @[PTW.scala:220:14]
input io_mem_s2_uncached, // @[PTW.scala:220:14]
input [31:0] io_mem_s2_paddr, // @[PTW.scala:220:14]
input io_mem_resp_valid, // @[PTW.scala:220:14]
input [39:0] io_mem_resp_bits_addr, // @[PTW.scala:220:14]
input [7:0] io_mem_resp_bits_tag, // @[PTW.scala:220:14]
input [4:0] io_mem_resp_bits_cmd, // @[PTW.scala:220:14]
input [1:0] io_mem_resp_bits_size, // @[PTW.scala:220:14]
input io_mem_resp_bits_signed, // @[PTW.scala:220:14]
input [1:0] io_mem_resp_bits_dprv, // @[PTW.scala:220:14]
input io_mem_resp_bits_dv, // @[PTW.scala:220:14]
input [63:0] io_mem_resp_bits_data, // @[PTW.scala:220:14]
input [7:0] io_mem_resp_bits_mask, // @[PTW.scala:220:14]
input io_mem_resp_bits_replay, // @[PTW.scala:220:14]
input io_mem_resp_bits_has_data, // @[PTW.scala:220:14]
input [63:0] io_mem_resp_bits_data_word_bypass, // @[PTW.scala:220:14]
input [63:0] io_mem_resp_bits_data_raw, // @[PTW.scala:220:14]
input [63:0] io_mem_resp_bits_store_data, // @[PTW.scala:220:14]
input io_mem_replay_next, // @[PTW.scala:220:14]
input io_mem_s2_xcpt_ma_ld, // @[PTW.scala:220:14]
input io_mem_s2_xcpt_ma_st, // @[PTW.scala:220:14]
input io_mem_s2_xcpt_pf_ld, // @[PTW.scala:220:14]
input io_mem_s2_xcpt_pf_st, // @[PTW.scala:220:14]
input io_mem_s2_xcpt_ae_ld, // @[PTW.scala:220:14]
input io_mem_s2_xcpt_ae_st, // @[PTW.scala:220:14]
input [39:0] io_mem_s2_gpa, // @[PTW.scala:220:14]
input io_mem_ordered, // @[PTW.scala:220:14]
input io_mem_store_pending, // @[PTW.scala:220:14]
input io_mem_perf_acquire, // @[PTW.scala:220:14]
input io_mem_perf_release, // @[PTW.scala:220:14]
input io_mem_perf_grant, // @[PTW.scala:220:14]
input io_mem_perf_tlbMiss, // @[PTW.scala:220:14]
input io_mem_perf_blocked, // @[PTW.scala:220:14]
input io_mem_perf_canAcceptStoreThenLoad, // @[PTW.scala:220:14]
input io_mem_perf_canAcceptStoreThenRMW, // @[PTW.scala:220:14]
input io_mem_perf_canAcceptLoadThenLoad, // @[PTW.scala:220:14]
input io_mem_perf_storeBufferEmptyAfterLoad, // @[PTW.scala:220:14]
input io_mem_perf_storeBufferEmptyAfterStore, // @[PTW.scala:220:14]
input [3:0] io_dpath_ptbr_mode, // @[PTW.scala:220:14]
input [15:0] io_dpath_ptbr_asid, // @[PTW.scala:220:14]
input [43:0] io_dpath_ptbr_ppn, // @[PTW.scala:220:14]
input io_dpath_sfence_valid, // @[PTW.scala:220:14]
input io_dpath_status_debug, // @[PTW.scala:220:14]
input io_dpath_status_cease, // @[PTW.scala:220:14]
input io_dpath_status_wfi, // @[PTW.scala:220:14]
input [31:0] io_dpath_status_isa, // @[PTW.scala:220:14]
input [1:0] io_dpath_status_dprv, // @[PTW.scala:220:14]
input io_dpath_status_dv, // @[PTW.scala:220:14]
input [1:0] io_dpath_status_prv, // @[PTW.scala:220:14]
input io_dpath_status_v, // @[PTW.scala:220:14]
input io_dpath_status_sd, // @[PTW.scala:220:14]
input [22:0] io_dpath_status_zero2, // @[PTW.scala:220:14]
input io_dpath_status_mpv, // @[PTW.scala:220:14]
input io_dpath_status_gva, // @[PTW.scala:220:14]
input io_dpath_status_mbe, // @[PTW.scala:220:14]
input io_dpath_status_sbe, // @[PTW.scala:220:14]
input [1:0] io_dpath_status_sxl, // @[PTW.scala:220:14]
input [1:0] io_dpath_status_uxl, // @[PTW.scala:220:14]
input io_dpath_status_sd_rv32, // @[PTW.scala:220:14]
input [7:0] io_dpath_status_zero1, // @[PTW.scala:220:14]
input io_dpath_status_tsr, // @[PTW.scala:220:14]
input io_dpath_status_tw, // @[PTW.scala:220:14]
input io_dpath_status_tvm, // @[PTW.scala:220:14]
input io_dpath_status_mxr, // @[PTW.scala:220:14]
input io_dpath_status_sum, // @[PTW.scala:220:14]
input io_dpath_status_mprv, // @[PTW.scala:220:14]
input [1:0] io_dpath_status_xs, // @[PTW.scala:220:14]
input [1:0] io_dpath_status_fs, // @[PTW.scala:220:14]
input [1:0] io_dpath_status_mpp, // @[PTW.scala:220:14]
input [1:0] io_dpath_status_vs, // @[PTW.scala:220:14]
input io_dpath_status_spp, // @[PTW.scala:220:14]
input io_dpath_status_mpie, // @[PTW.scala:220:14]
input io_dpath_status_ube, // @[PTW.scala:220:14]
input io_dpath_status_spie, // @[PTW.scala:220:14]
input io_dpath_status_upie, // @[PTW.scala:220:14]
input io_dpath_status_mie, // @[PTW.scala:220:14]
input io_dpath_status_hie, // @[PTW.scala:220:14]
input io_dpath_status_sie, // @[PTW.scala:220:14]
input io_dpath_status_uie, // @[PTW.scala:220:14]
output io_dpath_perf_pte_miss, // @[PTW.scala:220:14]
output io_dpath_clock_enabled // @[PTW.scala:220:14]
);
wire tmp_r; // @[PTW.scala:304:37]
wire tmp_w; // @[PTW.scala:304:37]
wire tmp_x; // @[PTW.scala:304:37]
wire tmp_u; // @[PTW.scala:304:37]
wire tmp_g; // @[PTW.scala:304:37]
wire tmp_a; // @[PTW.scala:304:37]
wire tmp_d; // @[PTW.scala:304:37]
wire [1:0] tmp_reserved_for_software; // @[PTW.scala:304:37]
wire [9:0] tmp_reserved_for_future; // @[PTW.scala:304:37]
wire [9:0] _r_pte_barrier_io_y_reserved_for_future; // @[package.scala:267:25]
wire [43:0] _r_pte_barrier_io_y_ppn; // @[package.scala:267:25]
wire [1:0] _r_pte_barrier_io_y_reserved_for_software; // @[package.scala:267:25]
wire _r_pte_barrier_io_y_d; // @[package.scala:267:25]
wire _r_pte_barrier_io_y_a; // @[package.scala:267:25]
wire _r_pte_barrier_io_y_g; // @[package.scala:267:25]
wire _r_pte_barrier_io_y_u; // @[package.scala:267:25]
wire _r_pte_barrier_io_y_x; // @[package.scala:267:25]
wire _r_pte_barrier_io_y_w; // @[package.scala:267:25]
wire _r_pte_barrier_io_y_r; // @[package.scala:267:25]
wire _r_pte_barrier_io_y_v; // @[package.scala:267:25]
wire [2:0] _state_barrier_io_y; // @[package.scala:267:25]
wire _arb_io_out_valid; // @[PTW.scala:236:19]
wire [26:0] _arb_io_out_bits_bits_addr; // @[PTW.scala:236:19]
wire _arb_io_out_bits_bits_need_gpa; // @[PTW.scala:236:19]
wire io_requestor_0_req_valid_0 = io_requestor_0_req_valid; // @[PTW.scala:219:7]
wire [26:0] io_requestor_0_req_bits_bits_addr_0 = io_requestor_0_req_bits_bits_addr; // @[PTW.scala:219:7]
wire io_requestor_0_req_bits_bits_need_gpa_0 = io_requestor_0_req_bits_bits_need_gpa; // @[PTW.scala:219:7]
wire io_mem_req_ready_0 = io_mem_req_ready; // @[PTW.scala:219:7]
wire io_mem_s2_nack_0 = io_mem_s2_nack; // @[PTW.scala:219:7]
wire io_mem_s2_nack_cause_raw_0 = io_mem_s2_nack_cause_raw; // @[PTW.scala:219:7]
wire io_mem_s2_uncached_0 = io_mem_s2_uncached; // @[PTW.scala:219:7]
wire [31:0] io_mem_s2_paddr_0 = io_mem_s2_paddr; // @[PTW.scala:219:7]
wire io_mem_resp_valid_0 = io_mem_resp_valid; // @[PTW.scala:219:7]
wire [39:0] io_mem_resp_bits_addr_0 = io_mem_resp_bits_addr; // @[PTW.scala:219:7]
wire [7:0] io_mem_resp_bits_tag_0 = io_mem_resp_bits_tag; // @[PTW.scala:219:7]
wire [4:0] io_mem_resp_bits_cmd_0 = io_mem_resp_bits_cmd; // @[PTW.scala:219:7]
wire [1:0] io_mem_resp_bits_size_0 = io_mem_resp_bits_size; // @[PTW.scala:219:7]
wire io_mem_resp_bits_signed_0 = io_mem_resp_bits_signed; // @[PTW.scala:219:7]
wire [1:0] io_mem_resp_bits_dprv_0 = io_mem_resp_bits_dprv; // @[PTW.scala:219:7]
wire io_mem_resp_bits_dv_0 = io_mem_resp_bits_dv; // @[PTW.scala:219:7]
wire [63:0] io_mem_resp_bits_data_0 = io_mem_resp_bits_data; // @[PTW.scala:219:7]
wire [7:0] io_mem_resp_bits_mask_0 = io_mem_resp_bits_mask; // @[PTW.scala:219:7]
wire io_mem_resp_bits_replay_0 = io_mem_resp_bits_replay; // @[PTW.scala:219:7]
wire io_mem_resp_bits_has_data_0 = io_mem_resp_bits_has_data; // @[PTW.scala:219:7]
wire [63:0] io_mem_resp_bits_data_word_bypass_0 = io_mem_resp_bits_data_word_bypass; // @[PTW.scala:219:7]
wire [63:0] io_mem_resp_bits_data_raw_0 = io_mem_resp_bits_data_raw; // @[PTW.scala:219:7]
wire [63:0] io_mem_resp_bits_store_data_0 = io_mem_resp_bits_store_data; // @[PTW.scala:219:7]
wire io_mem_replay_next_0 = io_mem_replay_next; // @[PTW.scala:219:7]
wire io_mem_s2_xcpt_ma_ld_0 = io_mem_s2_xcpt_ma_ld; // @[PTW.scala:219:7]
wire io_mem_s2_xcpt_ma_st_0 = io_mem_s2_xcpt_ma_st; // @[PTW.scala:219:7]
wire io_mem_s2_xcpt_pf_ld_0 = io_mem_s2_xcpt_pf_ld; // @[PTW.scala:219:7]
wire io_mem_s2_xcpt_pf_st_0 = io_mem_s2_xcpt_pf_st; // @[PTW.scala:219:7]
wire io_mem_s2_xcpt_ae_ld_0 = io_mem_s2_xcpt_ae_ld; // @[PTW.scala:219:7]
wire io_mem_s2_xcpt_ae_st_0 = io_mem_s2_xcpt_ae_st; // @[PTW.scala:219:7]
wire [39:0] io_mem_s2_gpa_0 = io_mem_s2_gpa; // @[PTW.scala:219:7]
wire io_mem_ordered_0 = io_mem_ordered; // @[PTW.scala:219:7]
wire io_mem_store_pending_0 = io_mem_store_pending; // @[PTW.scala:219:7]
wire io_mem_perf_acquire_0 = io_mem_perf_acquire; // @[PTW.scala:219:7]
wire io_mem_perf_release_0 = io_mem_perf_release; // @[PTW.scala:219:7]
wire io_mem_perf_grant_0 = io_mem_perf_grant; // @[PTW.scala:219:7]
wire io_mem_perf_tlbMiss_0 = io_mem_perf_tlbMiss; // @[PTW.scala:219:7]
wire io_mem_perf_blocked_0 = io_mem_perf_blocked; // @[PTW.scala:219:7]
wire io_mem_perf_canAcceptStoreThenLoad_0 = io_mem_perf_canAcceptStoreThenLoad; // @[PTW.scala:219:7]
wire io_mem_perf_canAcceptStoreThenRMW_0 = io_mem_perf_canAcceptStoreThenRMW; // @[PTW.scala:219:7]
wire io_mem_perf_canAcceptLoadThenLoad_0 = io_mem_perf_canAcceptLoadThenLoad; // @[PTW.scala:219:7]
wire io_mem_perf_storeBufferEmptyAfterLoad_0 = io_mem_perf_storeBufferEmptyAfterLoad; // @[PTW.scala:219:7]
wire io_mem_perf_storeBufferEmptyAfterStore_0 = io_mem_perf_storeBufferEmptyAfterStore; // @[PTW.scala:219:7]
wire [3:0] io_dpath_ptbr_mode_0 = io_dpath_ptbr_mode; // @[PTW.scala:219:7]
wire [15:0] io_dpath_ptbr_asid_0 = io_dpath_ptbr_asid; // @[PTW.scala:219:7]
wire [43:0] io_dpath_ptbr_ppn_0 = io_dpath_ptbr_ppn; // @[PTW.scala:219:7]
wire io_dpath_sfence_valid_0 = io_dpath_sfence_valid; // @[PTW.scala:219:7]
wire io_dpath_status_debug_0 = io_dpath_status_debug; // @[PTW.scala:219:7]
wire io_dpath_status_cease_0 = io_dpath_status_cease; // @[PTW.scala:219:7]
wire io_dpath_status_wfi_0 = io_dpath_status_wfi; // @[PTW.scala:219:7]
wire [31:0] io_dpath_status_isa_0 = io_dpath_status_isa; // @[PTW.scala:219:7]
wire [1:0] io_dpath_status_dprv_0 = io_dpath_status_dprv; // @[PTW.scala:219:7]
wire io_dpath_status_dv_0 = io_dpath_status_dv; // @[PTW.scala:219:7]
wire [1:0] io_dpath_status_prv_0 = io_dpath_status_prv; // @[PTW.scala:219:7]
wire io_dpath_status_v_0 = io_dpath_status_v; // @[PTW.scala:219:7]
wire io_dpath_status_sd_0 = io_dpath_status_sd; // @[PTW.scala:219:7]
wire [22:0] io_dpath_status_zero2_0 = io_dpath_status_zero2; // @[PTW.scala:219:7]
wire io_dpath_status_mpv_0 = io_dpath_status_mpv; // @[PTW.scala:219:7]
wire io_dpath_status_gva_0 = io_dpath_status_gva; // @[PTW.scala:219:7]
wire io_dpath_status_mbe_0 = io_dpath_status_mbe; // @[PTW.scala:219:7]
wire io_dpath_status_sbe_0 = io_dpath_status_sbe; // @[PTW.scala:219:7]
wire [1:0] io_dpath_status_sxl_0 = io_dpath_status_sxl; // @[PTW.scala:219:7]
wire [1:0] io_dpath_status_uxl_0 = io_dpath_status_uxl; // @[PTW.scala:219:7]
wire io_dpath_status_sd_rv32_0 = io_dpath_status_sd_rv32; // @[PTW.scala:219:7]
wire [7:0] io_dpath_status_zero1_0 = io_dpath_status_zero1; // @[PTW.scala:219:7]
wire io_dpath_status_tsr_0 = io_dpath_status_tsr; // @[PTW.scala:219:7]
wire io_dpath_status_tw_0 = io_dpath_status_tw; // @[PTW.scala:219:7]
wire io_dpath_status_tvm_0 = io_dpath_status_tvm; // @[PTW.scala:219:7]
wire io_dpath_status_mxr_0 = io_dpath_status_mxr; // @[PTW.scala:219:7]
wire io_dpath_status_sum_0 = io_dpath_status_sum; // @[PTW.scala:219:7]
wire io_dpath_status_mprv_0 = io_dpath_status_mprv; // @[PTW.scala:219:7]
wire [1:0] io_dpath_status_xs_0 = io_dpath_status_xs; // @[PTW.scala:219:7]
wire [1:0] io_dpath_status_fs_0 = io_dpath_status_fs; // @[PTW.scala:219:7]
wire [1:0] io_dpath_status_mpp_0 = io_dpath_status_mpp; // @[PTW.scala:219:7]
wire [1:0] io_dpath_status_vs_0 = io_dpath_status_vs; // @[PTW.scala:219:7]
wire io_dpath_status_spp_0 = io_dpath_status_spp; // @[PTW.scala:219:7]
wire io_dpath_status_mpie_0 = io_dpath_status_mpie; // @[PTW.scala:219:7]
wire io_dpath_status_ube_0 = io_dpath_status_ube; // @[PTW.scala:219:7]
wire io_dpath_status_spie_0 = io_dpath_status_spie; // @[PTW.scala:219:7]
wire io_dpath_status_upie_0 = io_dpath_status_upie; // @[PTW.scala:219:7]
wire io_dpath_status_mie_0 = io_dpath_status_mie; // @[PTW.scala:219:7]
wire io_dpath_status_hie_0 = io_dpath_status_hie; // @[PTW.scala:219:7]
wire io_dpath_status_sie_0 = io_dpath_status_sie; // @[PTW.scala:219:7]
wire io_dpath_status_uie_0 = io_dpath_status_uie; // @[PTW.scala:219:7]
wire io_requestor_0_req_bits_bits_vstage1 = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_req_bits_bits_stage2 = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_fragmented_superpage = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_hstatus_vtw = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_hstatus_hu = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_hstatus_spvp = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_hstatus_spv = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_hstatus_gva = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_debug = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_cease = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_wfi = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_dv = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_v = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_sd = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_mpv = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_gva = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_mbe = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_sbe = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_tsr = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_tw = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_tvm = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_mxr = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_sum = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_mprv = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_spp = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_mpie = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_ube = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_spie = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_upie = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_mie = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_hie = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_sie = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_uie = 1'h0; // @[PTW.scala:219:7]
wire io_mem_req_bits_signed = 1'h0; // @[PTW.scala:219:7]
wire io_mem_req_bits_no_resp = 1'h0; // @[PTW.scala:219:7]
wire io_mem_req_bits_no_alloc = 1'h0; // @[PTW.scala:219:7]
wire io_mem_req_bits_no_xcpt = 1'h0; // @[PTW.scala:219:7]
wire io_mem_s2_kill = 1'h0; // @[PTW.scala:219:7]
wire io_mem_s2_xcpt_gf_ld = 1'h0; // @[PTW.scala:219:7]
wire io_mem_s2_xcpt_gf_st = 1'h0; // @[PTW.scala:219:7]
wire io_mem_s2_gpa_is_pte = 1'h0; // @[PTW.scala:219:7]
wire io_mem_keep_clock_enabled = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_sfence_bits_rs1 = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_sfence_bits_rs2 = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_sfence_bits_asid = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_sfence_bits_hv = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_sfence_bits_hg = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_hstatus_vtw = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_hstatus_hu = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_hstatus_spvp = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_hstatus_spv = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_hstatus_gva = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_gstatus_debug = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_gstatus_cease = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_gstatus_wfi = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_gstatus_dv = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_gstatus_v = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_gstatus_sd = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_gstatus_mpv = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_gstatus_gva = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_gstatus_mbe = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_gstatus_sbe = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_gstatus_tsr = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_gstatus_tw = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_gstatus_tvm = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_gstatus_mxr = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_gstatus_sum = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_gstatus_mprv = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_gstatus_spp = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_gstatus_mpie = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_gstatus_ube = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_gstatus_spie = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_gstatus_upie = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_gstatus_mie = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_gstatus_hie = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_gstatus_sie = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_gstatus_uie = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_perf_l2miss = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_perf_l2hit = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_perf_pte_hit = 1'h0; // @[PTW.scala:219:7]
wire _resp_valid_WIRE_0 = 1'h0; // @[PTW.scala:242:35]
wire _io_dpath_perf_pte_hit_T_1 = 1'h0; // @[PTW.scala:394:36]
wire _io_dpath_perf_pte_hit_T_3 = 1'h0; // @[PTW.scala:394:57]
wire l2_pte_d = 1'h0; // @[PTW.scala:403:113]
wire l2_pte_a = 1'h0; // @[PTW.scala:403:113]
wire l2_pte_g = 1'h0; // @[PTW.scala:403:113]
wire l2_pte_u = 1'h0; // @[PTW.scala:403:113]
wire l2_pte_x = 1'h0; // @[PTW.scala:403:113]
wire l2_pte_w = 1'h0; // @[PTW.scala:403:113]
wire l2_pte_r = 1'h0; // @[PTW.scala:403:113]
wire l2_pte_v = 1'h0; // @[PTW.scala:403:113]
wire _pmpHomogeneous_WIRE_cfg_l = 1'h0; // @[PMP.scala:137:40]
wire _pmpHomogeneous_WIRE_cfg_x = 1'h0; // @[PMP.scala:137:40]
wire _pmpHomogeneous_WIRE_cfg_w = 1'h0; // @[PMP.scala:137:40]
wire _pmpHomogeneous_WIRE_cfg_r = 1'h0; // @[PMP.scala:137:40]
wire _io_requestor_0_resp_bits_fragmented_superpage_T = 1'h0; // @[PTW.scala:563:81]
wire _stage2_final_T_1 = 1'h0; // @[PTW.scala:595:53]
wire _resp_gf_T_2 = 1'h0; // @[PTW.scala:603:71]
wire _r_pte_T_1 = 1'h0; // @[PTW.scala:670:16]
wire _r_pte_T_3 = 1'h0; // @[PTW.scala:670:29]
wire _r_pte_T_5 = 1'h0; // @[PTW.scala:672:25]
wire r_pte_idxs_0 = 1'h0; // @[PTW.scala:778:58]
wire r_pte_pte_d = 1'h0; // @[PTW.scala:780:26]
wire r_pte_pte_a = 1'h0; // @[PTW.scala:780:26]
wire r_pte_pte_g = 1'h0; // @[PTW.scala:780:26]
wire r_pte_pte_u = 1'h0; // @[PTW.scala:780:26]
wire r_pte_pte_x = 1'h0; // @[PTW.scala:780:26]
wire r_pte_pte_w = 1'h0; // @[PTW.scala:780:26]
wire r_pte_pte_r = 1'h0; // @[PTW.scala:780:26]
wire r_pte_pte_v = 1'h0; // @[PTW.scala:780:26]
wire _r_pte_T_7 = 1'h0; // @[PTW.scala:674:25]
wire r_pte_pte_1_d = 1'h0; // @[PTW.scala:771:26]
wire r_pte_pte_1_a = 1'h0; // @[PTW.scala:771:26]
wire r_pte_pte_1_g = 1'h0; // @[PTW.scala:771:26]
wire r_pte_pte_1_u = 1'h0; // @[PTW.scala:771:26]
wire r_pte_pte_1_x = 1'h0; // @[PTW.scala:771:26]
wire r_pte_pte_1_w = 1'h0; // @[PTW.scala:771:26]
wire r_pte_pte_1_r = 1'h0; // @[PTW.scala:771:26]
wire r_pte_pte_1_v = 1'h0; // @[PTW.scala:771:26]
wire io_requestor_0_req_bits_valid = 1'h1; // @[PTW.scala:219:7]
wire io_mem_req_bits_phys = 1'h1; // @[PTW.scala:219:7]
wire io_mem_clock_enabled = 1'h1; // @[PTW.scala:219:7]
wire _io_dpath_perf_pte_hit_T_2 = 1'h1; // @[PTW.scala:394:60]
wire _pmaPgLevelHomogeneous_T_1 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _pmaPgLevelHomogeneous_T_2 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _pmaPgLevelHomogeneous_T_3 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _pmaPgLevelHomogeneous_T_4 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _pmaPgLevelHomogeneous_T_5 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _pmaPgLevelHomogeneous_T_6 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _pmaPgLevelHomogeneous_T_19 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _pmaPgLevelHomogeneous_T_20 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _pmaPgLevelHomogeneous_T_35 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _pmaPgLevelHomogeneous_T_36 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _pmaPgLevelHomogeneous_T_109 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _stage2_final_T = 1'h1; // @[PTW.scala:595:56]
wire _r_pte_T = 1'h1; // @[PTW.scala:670:19]
wire [43:0] io_requestor_0_hgatp_ppn = 44'h0; // @[PTW.scala:219:7]
wire [43:0] io_requestor_0_vsatp_ppn = 44'h0; // @[PTW.scala:219:7]
wire [43:0] io_dpath_hgatp_ppn = 44'h0; // @[PTW.scala:219:7]
wire [43:0] io_dpath_vsatp_ppn = 44'h0; // @[PTW.scala:219:7]
wire [43:0] l2_pte_ppn = 44'h0; // @[PTW.scala:403:113]
wire [43:0] r_pte_pte_ppn = 44'h0; // @[PTW.scala:780:26]
wire [43:0] _r_pte_pte_ppn_T_1 = 44'h0; // @[PTW.scala:781:19]
wire [43:0] r_pte_pte_1_ppn = 44'h0; // @[PTW.scala:771:26]
wire [43:0] r_pte_pte_4_ppn = 44'h0; // @[PTW.scala:780:26]
wire [43:0] _r_pte_pte_ppn_T_5 = 44'h0; // @[PTW.scala:781:19]
wire [41:0] _r_pte_pte_ppn_T = 42'h0; // @[PTW.scala:781:30]
wire [41:0] _r_pte_pte_ppn_T_2 = 42'h0; // @[PTW.scala:781:30]
wire [41:0] _r_pte_pte_ppn_T_4 = 42'h0; // @[PTW.scala:781:30]
wire [15:0] io_requestor_0_hgatp_asid = 16'h0; // @[PTW.scala:219:7]
wire [15:0] io_requestor_0_vsatp_asid = 16'h0; // @[PTW.scala:219:7]
wire [15:0] io_dpath_hgatp_asid = 16'h0; // @[PTW.scala:219:7]
wire [15:0] io_dpath_vsatp_asid = 16'h0; // @[PTW.scala:219:7]
wire [3:0] io_requestor_0_hgatp_mode = 4'h0; // @[PTW.scala:219:7]
wire [3:0] io_requestor_0_vsatp_mode = 4'h0; // @[PTW.scala:219:7]
wire [3:0] io_dpath_hgatp_mode = 4'h0; // @[PTW.scala:219:7]
wire [3:0] io_dpath_vsatp_mode = 4'h0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_0_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7]
wire [29:0] io_dpath_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7]
wire [29:0] _pmpHomogeneous_WIRE_addr = 30'h0; // @[PMP.scala:137:40]
wire [1:0] io_requestor_0_hstatus_vsxl = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_gstatus_dprv = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_gstatus_prv = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_gstatus_sxl = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_gstatus_uxl = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_gstatus_xs = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_gstatus_fs = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_gstatus_mpp = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_gstatus_vs = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_hstatus_vsxl = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_gstatus_dprv = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_gstatus_prv = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_gstatus_sxl = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_gstatus_uxl = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_gstatus_xs = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_gstatus_fs = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_gstatus_mpp = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_gstatus_vs = 2'h0; // @[PTW.scala:219:7]
wire [1:0] _r_hgatp_initial_count_T_1 = 2'h0; // @[PTW.scala:286:42]
wire [1:0] r_hgatp_initial_count = 2'h0; // @[PTW.scala:286:58]
wire [1:0] _count_T_1 = 2'h0; // @[PTW.scala:786:28]
wire [1:0] count_1 = 2'h0; // @[PTW.scala:786:44]
wire [1:0] l2_pte_reserved_for_software = 2'h0; // @[PTW.scala:403:113]
wire [1:0] _pmpHomogeneous_WIRE_cfg_res = 2'h0; // @[PMP.scala:137:40]
wire [1:0] _pmpHomogeneous_WIRE_cfg_a = 2'h0; // @[PMP.scala:137:40]
wire [1:0] _satp_initial_count_T_1 = 2'h0; // @[PTW.scala:586:45]
wire [1:0] satp_initial_count = 2'h0; // @[PTW.scala:586:61]
wire [1:0] _vsatp_initial_count_T_1 = 2'h0; // @[PTW.scala:587:46]
wire [1:0] vsatp_initial_count = 2'h0; // @[PTW.scala:587:62]
wire [1:0] _hgatp_initial_count_T_1 = 2'h0; // @[PTW.scala:588:46]
wire [1:0] hgatp_initial_count = 2'h0; // @[PTW.scala:588:62]
wire [1:0] _count_T_3 = 2'h0; // @[PTW.scala:596:27]
wire [1:0] _aux_count_T = 2'h0; // @[PTW.scala:597:27]
wire [1:0] _resp_gf_count_T_1 = 2'h0; // @[PTW.scala:786:28]
wire [1:0] resp_gf_count = 2'h0; // @[PTW.scala:786:44]
wire [1:0] _resp_gf_T = 2'h0; // @[package.scala:24:40]
wire [1:0] _r_pte_count_T_1 = 2'h0; // @[PTW.scala:777:28]
wire [1:0] r_pte_count = 2'h0; // @[PTW.scala:777:44]
wire [1:0] r_pte_lsbs = 2'h0; // @[PTW.scala:779:27]
wire [1:0] r_pte_pte_reserved_for_software = 2'h0; // @[PTW.scala:780:26]
wire [1:0] r_pte_pte_1_reserved_for_software = 2'h0; // @[PTW.scala:771:26]
wire [1:0] _r_pte_count_T_4 = 2'h0; // @[PTW.scala:777:28]
wire [1:0] r_pte_count_1 = 2'h0; // @[PTW.scala:777:44]
wire [1:0] _r_pte_count_T_7 = 2'h0; // @[PTW.scala:777:28]
wire [1:0] r_pte_count_2 = 2'h0; // @[PTW.scala:777:44]
wire [1:0] r_pte_lsbs_2 = 2'h0; // @[PTW.scala:779:27]
wire [8:0] io_requestor_0_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7]
wire [8:0] io_dpath_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7]
wire [5:0] io_requestor_0_hstatus_vgein = 6'h0; // @[PTW.scala:219:7]
wire [5:0] io_dpath_hstatus_vgein = 6'h0; // @[PTW.scala:219:7]
wire [4:0] io_requestor_0_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7]
wire [4:0] io_mem_req_bits_cmd = 5'h0; // @[PTW.scala:219:7]
wire [4:0] io_dpath_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_0_gstatus_isa = 32'h0; // @[PTW.scala:219:7]
wire [31:0] io_dpath_gstatus_isa = 32'h0; // @[PTW.scala:219:7]
wire [31:0] _pmpHomogeneous_WIRE_mask = 32'h0; // @[PMP.scala:137:40]
wire [22:0] io_requestor_0_gstatus_zero2 = 23'h0; // @[PTW.scala:219:7]
wire [22:0] io_dpath_gstatus_zero2 = 23'h0; // @[PTW.scala:219:7]
wire [7:0] io_requestor_0_gstatus_zero1 = 8'h0; // @[PTW.scala:219:7]
wire [7:0] io_mem_req_bits_tag = 8'h0; // @[PTW.scala:219:7]
wire [7:0] io_mem_req_bits_mask = 8'h0; // @[PTW.scala:219:7]
wire [7:0] io_mem_s1_data_mask = 8'h0; // @[PTW.scala:219:7]
wire [7:0] io_dpath_gstatus_zero1 = 8'h0; // @[PTW.scala:219:7]
wire [1:0] io_mem_req_bits_size = 2'h3; // @[PTW.scala:219:7]
wire [1:0] io_mem_req_bits_dprv = 2'h1; // @[PTW.scala:219:7]
wire [63:0] io_mem_req_bits_data = 64'h0; // @[PTW.scala:219:7]
wire [63:0] io_mem_s1_data_data = 64'h0; // @[PTW.scala:219:7]
wire [38:0] io_dpath_sfence_bits_addr = 39'h0; // @[PTW.scala:219:7]
wire [16:0] r_pte_idxs_0_2 = 17'h0; // @[PTW.scala:778:58]
wire [2:0] _r_hgatp_initial_count_T = 3'h0; // @[PTW.scala:286:42]
wire [2:0] _r_hgatp_initial_count_T_2 = 3'h0; // @[PTW.scala:286:58]
wire [2:0] _count_T = 3'h0; // @[PTW.scala:786:28]
wire [2:0] _count_T_2 = 3'h0; // @[PTW.scala:786:44]
wire [2:0] _satp_initial_count_T = 3'h0; // @[PTW.scala:586:45]
wire [2:0] _satp_initial_count_T_2 = 3'h0; // @[PTW.scala:586:61]
wire [2:0] _vsatp_initial_count_T = 3'h0; // @[PTW.scala:587:46]
wire [2:0] _vsatp_initial_count_T_2 = 3'h0; // @[PTW.scala:587:62]
wire [2:0] _hgatp_initial_count_T = 3'h0; // @[PTW.scala:588:46]
wire [2:0] _hgatp_initial_count_T_2 = 3'h0; // @[PTW.scala:588:62]
wire [2:0] _resp_gf_count_T = 3'h0; // @[PTW.scala:786:28]
wire [2:0] _resp_gf_count_T_2 = 3'h0; // @[PTW.scala:786:44]
wire [2:0] _r_pte_count_T = 3'h0; // @[PTW.scala:777:28]
wire [2:0] _r_pte_count_T_2 = 3'h0; // @[PTW.scala:777:44]
wire [2:0] _r_pte_count_T_3 = 3'h0; // @[PTW.scala:777:28]
wire [2:0] _r_pte_count_T_5 = 3'h0; // @[PTW.scala:777:44]
wire [2:0] _r_pte_count_T_6 = 3'h0; // @[PTW.scala:777:28]
wire [2:0] _r_pte_count_T_8 = 3'h0; // @[PTW.scala:777:44]
wire [9:0] l2_pte_reserved_for_future = 10'h0; // @[PTW.scala:403:113]
wire [9:0] r_pte_pte_reserved_for_future = 10'h0; // @[PTW.scala:780:26]
wire [9:0] r_pte_pte_1_reserved_for_future = 10'h0; // @[PTW.scala:771:26]
wire [2:0] _next_state_T_2 = 3'h4; // @[PTW.scala:636:24]
wire [2:0] _next_state_T = 3'h1; // @[PTW.scala:593:26]
wire [8:0] pte_addr_mask = 9'h1FF; // @[PTW.scala:324:23]
wire [1:0] max_count; // @[PTW.scala:289:25]
wire _io_requestor_0_resp_bits_homogeneous_T; // @[PTW.scala:562:58]
wire _io_requestor_0_resp_bits_gpa_is_pte_T; // @[PTW.scala:567:45]
wire _io_mem_req_valid_T_2; // @[PTW.scala:515:39]
wire _io_mem_req_bits_dv_T_1; // @[PTW.scala:523:40]
wire _io_mem_s1_kill_T_2; // @[PTW.scala:531:51]
wire [3:0] io_requestor_0_ptbr_mode_0 = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7]
wire [3:0] satp_mode = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7, :285:17]
wire [15:0] io_requestor_0_ptbr_asid_0 = io_dpath_ptbr_asid_0; // @[PTW.scala:219:7]
wire [15:0] satp_asid = io_dpath_ptbr_asid_0; // @[PTW.scala:219:7, :285:17]
wire [43:0] io_requestor_0_ptbr_ppn_0 = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7]
wire [43:0] satp_ppn = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7, :285:17]
wire io_requestor_0_status_debug_0 = io_dpath_status_debug_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_cease_0 = io_dpath_status_cease_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_wfi_0 = io_dpath_status_wfi_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_0_status_isa_0 = io_dpath_status_isa_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_status_dprv_0 = io_dpath_status_dprv_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_dv_0 = io_dpath_status_dv_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_status_prv_0 = io_dpath_status_prv_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_v_0 = io_dpath_status_v_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_sd_0 = io_dpath_status_sd_0; // @[PTW.scala:219:7]
wire [22:0] io_requestor_0_status_zero2_0 = io_dpath_status_zero2_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_mpv_0 = io_dpath_status_mpv_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_gva_0 = io_dpath_status_gva_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_mbe_0 = io_dpath_status_mbe_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_sbe_0 = io_dpath_status_sbe_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_status_sxl_0 = io_dpath_status_sxl_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_status_uxl_0 = io_dpath_status_uxl_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_sd_rv32_0 = io_dpath_status_sd_rv32_0; // @[PTW.scala:219:7]
wire [7:0] io_requestor_0_status_zero1_0 = io_dpath_status_zero1_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_tsr_0 = io_dpath_status_tsr_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_tw_0 = io_dpath_status_tw_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_tvm_0 = io_dpath_status_tvm_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_mxr_0 = io_dpath_status_mxr_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_sum_0 = io_dpath_status_sum_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_mprv_0 = io_dpath_status_mprv_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_status_xs_0 = io_dpath_status_xs_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_status_fs_0 = io_dpath_status_fs_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_status_mpp_0 = io_dpath_status_mpp_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_status_vs_0 = io_dpath_status_vs_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_spp_0 = io_dpath_status_spp_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_mpie_0 = io_dpath_status_mpie_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_ube_0 = io_dpath_status_ube_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_spie_0 = io_dpath_status_spie_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_upie_0 = io_dpath_status_upie_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_mie_0 = io_dpath_status_mie_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_hie_0 = io_dpath_status_hie_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_sie_0 = io_dpath_status_sie_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_uie_0 = io_dpath_status_uie_0; // @[PTW.scala:219:7]
wire _io_dpath_clock_enabled_T; // @[PTW.scala:245:39]
wire io_requestor_0_req_ready_0; // @[PTW.scala:219:7]
wire [9:0] io_requestor_0_resp_bits_pte_reserved_for_future_0; // @[PTW.scala:219:7]
wire [43:0] io_requestor_0_resp_bits_pte_ppn_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_resp_bits_pte_reserved_for_software_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_pte_d_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_pte_a_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_pte_g_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_pte_u_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_pte_x_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_pte_w_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_pte_r_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_pte_v_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_gpa_valid_0; // @[PTW.scala:219:7]
wire [38:0] io_requestor_0_resp_bits_gpa_bits_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_ae_ptw_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_ae_final_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_pf_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_gf_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_hr_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_hw_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_hx_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_resp_bits_level_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_homogeneous_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_gpa_is_pte_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_valid_0; // @[PTW.scala:219:7]
wire [39:0] io_mem_req_bits_addr_0; // @[PTW.scala:219:7]
wire io_mem_req_bits_dv_0; // @[PTW.scala:219:7]
wire io_mem_req_valid_0; // @[PTW.scala:219:7]
wire io_mem_s1_kill_0; // @[PTW.scala:219:7]
wire io_dpath_perf_pte_miss_0; // @[PTW.scala:219:7]
wire io_dpath_clock_enabled_0; // @[PTW.scala:219:7]
reg [2:0] state; // @[PTW.scala:233:22]
wire l2_refill_wire; // @[PTW.scala:234:28]
wire _arb_io_out_ready_T = ~(|state); // @[PTW.scala:233:22, :240:30]
wire _arb_io_out_ready_T_1 = ~l2_refill_wire; // @[PTW.scala:234:28, :240:46]
wire _arb_io_out_ready_T_2 = _arb_io_out_ready_T & _arb_io_out_ready_T_1; // @[PTW.scala:240:{30,43,46}]
reg resp_valid_0; // @[PTW.scala:242:27]
assign io_requestor_0_resp_valid_0 = resp_valid_0; // @[PTW.scala:219:7, :242:27]
wire _clock_en_T = |state; // @[PTW.scala:233:22, :240:30, :244:24]
wire _clock_en_T_1 = _clock_en_T | l2_refill_wire; // @[PTW.scala:234:28, :244:{24,36}]
wire _clock_en_T_2 = _clock_en_T_1 | _arb_io_out_valid; // @[PTW.scala:236:19, :244:{36,54}]
wire _clock_en_T_3 = _clock_en_T_2 | io_dpath_sfence_valid_0; // @[PTW.scala:219:7, :244:{54,74}]
wire clock_en = _clock_en_T_3; // @[PTW.scala:244:{74,99}]
assign _io_dpath_clock_enabled_T = clock_en; // @[PTW.scala:244:99, :245:39]
assign io_dpath_clock_enabled_0 = _io_dpath_clock_enabled_T; // @[PTW.scala:219:7, :245:39]
reg invalidated; // @[PTW.scala:251:24]
reg [1:0] count; // @[PTW.scala:259:18]
wire [1:0] _r_pte_truncIdx_T = count; // @[package.scala:38:21]
reg resp_ae_ptw; // @[PTW.scala:260:24]
assign io_requestor_0_resp_bits_ae_ptw_0 = resp_ae_ptw; // @[PTW.scala:219:7, :260:24]
reg resp_ae_final; // @[PTW.scala:261:26]
assign io_requestor_0_resp_bits_ae_final_0 = resp_ae_final; // @[PTW.scala:219:7, :261:26]
reg resp_pf; // @[PTW.scala:262:20]
assign io_requestor_0_resp_bits_pf_0 = resp_pf; // @[PTW.scala:219:7, :262:20]
reg resp_gf; // @[PTW.scala:263:20]
assign io_requestor_0_resp_bits_gf_0 = resp_gf; // @[PTW.scala:219:7, :263:20]
reg resp_hr; // @[PTW.scala:264:20]
assign io_requestor_0_resp_bits_hr_0 = resp_hr; // @[PTW.scala:219:7, :264:20]
reg resp_hw; // @[PTW.scala:265:20]
assign io_requestor_0_resp_bits_hw_0 = resp_hw; // @[PTW.scala:219:7, :265:20]
reg resp_hx; // @[PTW.scala:266:20]
assign io_requestor_0_resp_bits_hx_0 = resp_hx; // @[PTW.scala:219:7, :266:20]
reg resp_fragmented_superpage; // @[PTW.scala:267:38]
reg [26:0] r_req_addr; // @[PTW.scala:270:18]
reg r_req_need_gpa; // @[PTW.scala:270:18]
assign io_requestor_0_resp_bits_gpa_valid_0 = r_req_need_gpa; // @[PTW.scala:219:7, :270:18]
reg r_req_vstage1; // @[PTW.scala:270:18]
reg r_req_stage2; // @[PTW.scala:270:18]
reg [9:0] r_pte_reserved_for_future; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_reserved_for_future_0 = r_pte_reserved_for_future; // @[PTW.scala:219:7, :275:18]
wire [9:0] r_pte_pte_2_reserved_for_future = r_pte_reserved_for_future; // @[PTW.scala:275:18, :780:26]
wire [9:0] r_pte_pte_3_reserved_for_future = r_pte_reserved_for_future; // @[PTW.scala:275:18, :771:26]
wire [9:0] r_pte_pte_4_reserved_for_future = r_pte_reserved_for_future; // @[PTW.scala:275:18, :780:26]
wire [9:0] r_pte_pte_5_reserved_for_future = r_pte_reserved_for_future; // @[PTW.scala:275:18, :771:26]
reg [43:0] r_pte_ppn; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_ppn_0 = r_pte_ppn; // @[PTW.scala:219:7, :275:18]
reg [1:0] r_pte_reserved_for_software; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_reserved_for_software_0 = r_pte_reserved_for_software; // @[PTW.scala:219:7, :275:18]
wire [1:0] r_pte_pte_2_reserved_for_software = r_pte_reserved_for_software; // @[PTW.scala:275:18, :780:26]
wire [1:0] r_pte_pte_3_reserved_for_software = r_pte_reserved_for_software; // @[PTW.scala:275:18, :771:26]
wire [1:0] r_pte_pte_4_reserved_for_software = r_pte_reserved_for_software; // @[PTW.scala:275:18, :780:26]
wire [1:0] r_pte_pte_5_reserved_for_software = r_pte_reserved_for_software; // @[PTW.scala:275:18, :771:26]
reg r_pte_d; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_d_0 = r_pte_d; // @[PTW.scala:219:7, :275:18]
wire r_pte_pte_2_d = r_pte_d; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_3_d = r_pte_d; // @[PTW.scala:275:18, :771:26]
wire r_pte_pte_4_d = r_pte_d; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_5_d = r_pte_d; // @[PTW.scala:275:18, :771:26]
reg r_pte_a; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_a_0 = r_pte_a; // @[PTW.scala:219:7, :275:18]
wire r_pte_pte_2_a = r_pte_a; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_3_a = r_pte_a; // @[PTW.scala:275:18, :771:26]
wire r_pte_pte_4_a = r_pte_a; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_5_a = r_pte_a; // @[PTW.scala:275:18, :771:26]
reg r_pte_g; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_g_0 = r_pte_g; // @[PTW.scala:219:7, :275:18]
wire r_pte_pte_2_g = r_pte_g; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_3_g = r_pte_g; // @[PTW.scala:275:18, :771:26]
wire r_pte_pte_4_g = r_pte_g; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_5_g = r_pte_g; // @[PTW.scala:275:18, :771:26]
reg r_pte_u; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_u_0 = r_pte_u; // @[PTW.scala:219:7, :275:18]
wire r_pte_pte_2_u = r_pte_u; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_3_u = r_pte_u; // @[PTW.scala:275:18, :771:26]
wire r_pte_pte_4_u = r_pte_u; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_5_u = r_pte_u; // @[PTW.scala:275:18, :771:26]
reg r_pte_x; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_x_0 = r_pte_x; // @[PTW.scala:219:7, :275:18]
wire r_pte_pte_2_x = r_pte_x; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_3_x = r_pte_x; // @[PTW.scala:275:18, :771:26]
wire r_pte_pte_4_x = r_pte_x; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_5_x = r_pte_x; // @[PTW.scala:275:18, :771:26]
reg r_pte_w; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_w_0 = r_pte_w; // @[PTW.scala:219:7, :275:18]
wire r_pte_pte_2_w = r_pte_w; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_3_w = r_pte_w; // @[PTW.scala:275:18, :771:26]
wire r_pte_pte_4_w = r_pte_w; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_5_w = r_pte_w; // @[PTW.scala:275:18, :771:26]
reg r_pte_r; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_r_0 = r_pte_r; // @[PTW.scala:219:7, :275:18]
wire r_pte_pte_2_r = r_pte_r; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_3_r = r_pte_r; // @[PTW.scala:275:18, :771:26]
wire r_pte_pte_4_r = r_pte_r; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_5_r = r_pte_r; // @[PTW.scala:275:18, :771:26]
reg r_pte_v; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_v_0 = r_pte_v; // @[PTW.scala:219:7, :275:18]
wire r_pte_pte_2_v = r_pte_v; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_3_v = r_pte_v; // @[PTW.scala:275:18, :771:26]
wire r_pte_pte_4_v = r_pte_v; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_5_v = r_pte_v; // @[PTW.scala:275:18, :771:26]
reg [1:0] aux_count; // @[PTW.scala:278:22]
wire [1:0] _io_requestor_0_resp_bits_gpa_bits_truncIdx_T = aux_count; // @[package.scala:38:21]
reg [9:0] aux_pte_reserved_for_future; // @[PTW.scala:280:20]
wire [9:0] merged_pte_reserved_for_future = aux_pte_reserved_for_future; // @[PTW.scala:280:20, :771:26]
reg [43:0] aux_pte_ppn; // @[PTW.scala:280:20]
reg [1:0] aux_pte_reserved_for_software; // @[PTW.scala:280:20]
wire [1:0] merged_pte_reserved_for_software = aux_pte_reserved_for_software; // @[PTW.scala:280:20, :771:26]
reg aux_pte_d; // @[PTW.scala:280:20]
wire merged_pte_d = aux_pte_d; // @[PTW.scala:280:20, :771:26]
reg aux_pte_a; // @[PTW.scala:280:20]
wire merged_pte_a = aux_pte_a; // @[PTW.scala:280:20, :771:26]
reg aux_pte_g; // @[PTW.scala:280:20]
wire merged_pte_g = aux_pte_g; // @[PTW.scala:280:20, :771:26]
reg aux_pte_u; // @[PTW.scala:280:20]
wire merged_pte_u = aux_pte_u; // @[PTW.scala:280:20, :771:26]
reg aux_pte_x; // @[PTW.scala:280:20]
wire merged_pte_x = aux_pte_x; // @[PTW.scala:280:20, :771:26]
reg aux_pte_w; // @[PTW.scala:280:20]
wire merged_pte_w = aux_pte_w; // @[PTW.scala:280:20, :771:26]
reg aux_pte_r; // @[PTW.scala:280:20]
wire merged_pte_r = aux_pte_r; // @[PTW.scala:280:20, :771:26]
reg aux_pte_v; // @[PTW.scala:280:20]
wire merged_pte_v = aux_pte_v; // @[PTW.scala:280:20, :771:26]
reg [11:0] gpa_pgoff; // @[PTW.scala:281:22]
reg stage2; // @[PTW.scala:282:19]
reg stage2_final; // @[PTW.scala:283:25]
wire [43:0] r_pte_pte_5_ppn = satp_ppn; // @[PTW.scala:285:17, :771:26]
wire do_both_stages = r_req_vstage1 & r_req_stage2; // @[PTW.scala:270:18, :288:38]
wire _max_count_T = count < aux_count; // @[PTW.scala:259:18, :278:22, :289:25]
assign max_count = _max_count_T ? aux_count : count; // @[PTW.scala:259:18, :278:22, :289:25]
assign io_requestor_0_resp_bits_level_0 = max_count; // @[PTW.scala:219:7, :289:25]
wire _vpn_T = r_req_vstage1 & stage2; // @[PTW.scala:270:18, :282:19, :290:31]
wire [43:0] vpn = _vpn_T ? aux_pte_ppn : {17'h0, r_req_addr}; // @[PTW.scala:270:18, :280:20, :290:{16,31}]
wire [43:0] _pte_addr_vpn_idxs_T_2 = vpn; // @[PTW.scala:290:16, :322:12]
reg mem_resp_valid; // @[PTW.scala:292:31]
reg [63:0] mem_resp_data; // @[PTW.scala:293:30]
wire [63:0] _tmp_WIRE = mem_resp_data; // @[PTW.scala:293:30, :304:37]
wire [9:0] _tmp_T_10; // @[PTW.scala:304:37]
wire [43:0] _tmp_T_9; // @[PTW.scala:304:37]
wire [9:0] pte_reserved_for_future = tmp_reserved_for_future; // @[PTW.scala:304:37, :305:26]
wire [1:0] _tmp_T_8; // @[PTW.scala:304:37]
wire _tmp_T_7; // @[PTW.scala:304:37]
wire [1:0] pte_reserved_for_software = tmp_reserved_for_software; // @[PTW.scala:304:37, :305:26]
wire _tmp_T_6; // @[PTW.scala:304:37]
wire pte_d = tmp_d; // @[PTW.scala:304:37, :305:26]
wire _tmp_T_5; // @[PTW.scala:304:37]
wire pte_a = tmp_a; // @[PTW.scala:304:37, :305:26]
wire _tmp_T_4; // @[PTW.scala:304:37]
wire pte_g = tmp_g; // @[PTW.scala:304:37, :305:26]
wire _tmp_T_3; // @[PTW.scala:304:37]
wire pte_u = tmp_u; // @[PTW.scala:304:37, :305:26]
wire _tmp_T_2; // @[PTW.scala:304:37]
wire pte_x = tmp_x; // @[PTW.scala:304:37, :305:26]
wire _tmp_T_1; // @[PTW.scala:304:37]
wire pte_w = tmp_w; // @[PTW.scala:304:37, :305:26]
wire _tmp_T; // @[PTW.scala:304:37]
wire pte_r = tmp_r; // @[PTW.scala:304:37, :305:26]
wire [43:0] tmp_ppn; // @[PTW.scala:304:37]
wire tmp_v; // @[PTW.scala:304:37]
assign _tmp_T = _tmp_WIRE[0]; // @[PTW.scala:304:37]
assign tmp_v = _tmp_T; // @[PTW.scala:304:37]
assign _tmp_T_1 = _tmp_WIRE[1]; // @[PTW.scala:304:37]
assign tmp_r = _tmp_T_1; // @[PTW.scala:304:37]
assign _tmp_T_2 = _tmp_WIRE[2]; // @[PTW.scala:304:37]
assign tmp_w = _tmp_T_2; // @[PTW.scala:304:37]
assign _tmp_T_3 = _tmp_WIRE[3]; // @[PTW.scala:304:37]
assign tmp_x = _tmp_T_3; // @[PTW.scala:304:37]
assign _tmp_T_4 = _tmp_WIRE[4]; // @[PTW.scala:304:37]
assign tmp_u = _tmp_T_4; // @[PTW.scala:304:37]
assign _tmp_T_5 = _tmp_WIRE[5]; // @[PTW.scala:304:37]
assign tmp_g = _tmp_T_5; // @[PTW.scala:304:37]
assign _tmp_T_6 = _tmp_WIRE[6]; // @[PTW.scala:304:37]
assign tmp_a = _tmp_T_6; // @[PTW.scala:304:37]
assign _tmp_T_7 = _tmp_WIRE[7]; // @[PTW.scala:304:37]
assign tmp_d = _tmp_T_7; // @[PTW.scala:304:37]
assign _tmp_T_8 = _tmp_WIRE[9:8]; // @[PTW.scala:304:37]
assign tmp_reserved_for_software = _tmp_T_8; // @[PTW.scala:304:37]
assign _tmp_T_9 = _tmp_WIRE[53:10]; // @[PTW.scala:304:37]
assign tmp_ppn = _tmp_T_9; // @[PTW.scala:304:37]
assign _tmp_T_10 = _tmp_WIRE[63:54]; // @[PTW.scala:304:37]
assign tmp_reserved_for_future = _tmp_T_10; // @[PTW.scala:304:37]
wire [9:0] aux_pte_pte_reserved_for_future = pte_reserved_for_future; // @[PTW.scala:305:26, :771:26]
wire [1:0] aux_pte_pte_reserved_for_software = pte_reserved_for_software; // @[PTW.scala:305:26, :771:26]
wire aux_pte_pte_d = pte_d; // @[PTW.scala:305:26, :771:26]
wire aux_pte_pte_a = pte_a; // @[PTW.scala:305:26, :771:26]
wire aux_pte_pte_g = pte_g; // @[PTW.scala:305:26, :771:26]
wire aux_pte_pte_u = pte_u; // @[PTW.scala:305:26, :771:26]
wire aux_pte_pte_x = pte_x; // @[PTW.scala:305:26, :771:26]
wire aux_pte_pte_w = pte_w; // @[PTW.scala:305:26, :771:26]
wire aux_pte_pte_r = pte_r; // @[PTW.scala:305:26, :771:26]
wire [43:0] pte_ppn; // @[PTW.scala:305:26]
wire pte_v; // @[PTW.scala:305:26]
wire aux_pte_pte_v = pte_v; // @[PTW.scala:305:26, :771:26]
wire _res_ppn_T = ~stage2; // @[PTW.scala:282:19, :306:38]
wire _res_ppn_T_1 = do_both_stages & _res_ppn_T; // @[PTW.scala:288:38, :306:{35,38}]
wire [26:0] _res_ppn_T_2 = tmp_ppn[26:0]; // @[PTW.scala:304:37, :306:54]
wire [19:0] _res_ppn_T_3 = tmp_ppn[19:0]; // @[PTW.scala:304:37, :306:99]
wire [26:0] _res_ppn_T_4 = _res_ppn_T_1 ? _res_ppn_T_2 : {7'h0, _res_ppn_T_3}; // @[PTW.scala:306:{19,35,54,99}]
assign pte_ppn = {17'h0, _res_ppn_T_4}; // @[PTW.scala:305:26, :306:{13,19}]
assign pte_v = ~((tmp_r | tmp_w | tmp_x) & (~(count[1]) & (|(tmp_ppn[8:0])) | count == 2'h0 & (|(tmp_ppn[17:9])))) & tmp_v; // @[PTW.scala:259:18, :304:37, :305:26, :307:{17,26,36}, :310:{21,28,38,97,106,114}]
wire invalid_paddr = do_both_stages & ~stage2 ? (|(tmp_ppn[43:27])) : (|(tmp_ppn[43:20])); // @[PTW.scala:282:19, :288:38, :304:37, :306:38, :313:{9,25,46,58,76,88}]
wire [14:0] idxs_0 = tmp_ppn[43:29]; // @[PTW.scala:304:37, :787:58]
wire invalid_gpa = do_both_stages & ~stage2 & (|idxs_0); // @[PTW.scala:282:19, :288:38, :306:38, :314:{21,32}, :787:58, :788:25]
wire _traverse_T = ~pte_r; // @[PTW.scala:139:36, :305:26]
wire _traverse_T_1 = pte_v & _traverse_T; // @[PTW.scala:139:{33,36}, :305:26]
wire _traverse_T_2 = ~pte_w; // @[PTW.scala:139:42, :305:26]
wire _traverse_T_3 = _traverse_T_1 & _traverse_T_2; // @[PTW.scala:139:{33,39,42}]
wire _traverse_T_4 = ~pte_x; // @[PTW.scala:139:48, :305:26]
wire _traverse_T_5 = _traverse_T_3 & _traverse_T_4; // @[PTW.scala:139:{39,45,48}]
wire _traverse_T_6 = ~pte_d; // @[PTW.scala:139:54, :305:26]
wire _traverse_T_7 = _traverse_T_5 & _traverse_T_6; // @[PTW.scala:139:{45,51,54}]
wire _traverse_T_8 = ~pte_a; // @[PTW.scala:139:60, :305:26]
wire _traverse_T_9 = _traverse_T_7 & _traverse_T_8; // @[PTW.scala:139:{51,57,60}]
wire _traverse_T_10 = ~pte_u; // @[PTW.scala:139:66, :305:26]
wire _traverse_T_11 = _traverse_T_9 & _traverse_T_10; // @[PTW.scala:139:{57,63,66}]
wire _traverse_T_12 = ~(|pte_reserved_for_future); // @[PTW.scala:139:92, :305:26]
wire _traverse_T_13 = _traverse_T_11 & _traverse_T_12; // @[PTW.scala:139:{63,69,92}]
wire _traverse_T_14 = ~invalid_paddr; // @[PTW.scala:313:9, :317:33]
wire _traverse_T_15 = _traverse_T_13 & _traverse_T_14; // @[PTW.scala:139:69, :317:{30,33}]
wire _traverse_T_16 = ~invalid_gpa; // @[PTW.scala:314:32, :317:51]
wire _traverse_T_17 = _traverse_T_15 & _traverse_T_16; // @[PTW.scala:317:{30,48,51}]
wire _traverse_T_18 = ~(count[1]); // @[PTW.scala:259:18, :310:21, :317:73]
wire traverse = _traverse_T_17 & _traverse_T_18; // @[PTW.scala:317:{48,64,73}]
wire [25:0] _pte_addr_vpn_idxs_T = vpn[43:18]; // @[PTW.scala:290:16, :322:12]
wire [8:0] pte_addr_vpn_idxs_0 = _pte_addr_vpn_idxs_T[8:0]; // @[PTW.scala:322:{12,48}]
wire [34:0] _pte_addr_vpn_idxs_T_1 = vpn[43:9]; // @[PTW.scala:290:16, :322:12]
wire [8:0] pte_addr_vpn_idxs_1 = _pte_addr_vpn_idxs_T_1[8:0]; // @[PTW.scala:322:{12,48}]
wire [8:0] pte_addr_vpn_idxs_2 = _pte_addr_vpn_idxs_T_2[8:0]; // @[PTW.scala:322:{12,48}]
wire _pte_addr_mask_T = ~(|count); // @[PTW.scala:259:18, :324:40]
wire _pte_addr_mask_T_1 = stage2 & _pte_addr_mask_T; // @[PTW.scala:282:19, :324:{31,40}]
wire _GEN = count == 2'h1; // @[package.scala:39:86]
wire _pte_addr_vpn_idx_T; // @[package.scala:39:86]
assign _pte_addr_vpn_idx_T = _GEN; // @[package.scala:39:86]
wire _pmaHomogeneous_T; // @[package.scala:39:86]
assign _pmaHomogeneous_T = _GEN; // @[package.scala:39:86]
wire _merged_pte_stage1_ppn_T; // @[package.scala:39:86]
assign _merged_pte_stage1_ppn_T = _GEN; // @[package.scala:39:86]
wire _aux_pte_T; // @[package.scala:39:86]
assign _aux_pte_T = _GEN; // @[package.scala:39:86]
wire _leaf_T_5; // @[PTW.scala:751:53]
assign _leaf_T_5 = _GEN; // @[package.scala:39:86]
wire [8:0] _pte_addr_vpn_idx_T_1 = _pte_addr_vpn_idx_T ? pte_addr_vpn_idxs_1 : pte_addr_vpn_idxs_0; // @[package.scala:39:{76,86}]
wire _T_129 = count == 2'h2; // @[package.scala:39:86]
wire _pte_addr_vpn_idx_T_2; // @[package.scala:39:86]
assign _pte_addr_vpn_idx_T_2 = _T_129; // @[package.scala:39:86]
wire _pmaHomogeneous_T_2; // @[package.scala:39:86]
assign _pmaHomogeneous_T_2 = _T_129; // @[package.scala:39:86]
wire _merged_pte_stage1_ppn_T_2; // @[package.scala:39:86]
assign _merged_pte_stage1_ppn_T_2 = _T_129; // @[package.scala:39:86]
wire _l2_refill_T; // @[PTW.scala:713:39]
assign _l2_refill_T = _T_129; // @[package.scala:39:86]
wire _aux_pte_T_2; // @[package.scala:39:86]
assign _aux_pte_T_2 = _T_129; // @[package.scala:39:86]
wire _leaf_T_8; // @[PTW.scala:751:53]
assign _leaf_T_8 = _T_129; // @[package.scala:39:86]
wire [8:0] _pte_addr_vpn_idx_T_3 = _pte_addr_vpn_idx_T_2 ? pte_addr_vpn_idxs_2 : _pte_addr_vpn_idx_T_1; // @[package.scala:39:{76,86}]
wire _pte_addr_vpn_idx_T_4 = &count; // @[package.scala:39:86]
wire [8:0] _pte_addr_vpn_idx_T_5 = _pte_addr_vpn_idx_T_4 ? pte_addr_vpn_idxs_2 : _pte_addr_vpn_idx_T_3; // @[package.scala:39:{76,86}]
wire [8:0] pte_addr_vpn_idx = _pte_addr_vpn_idx_T_5; // @[package.scala:39:76]
wire [52:0] _pte_addr_raw_pte_addr_T = {r_pte_ppn, 9'h0}; // @[PTW.scala:275:18, :326:36]
wire [52:0] _pte_addr_raw_pte_addr_T_1 = {_pte_addr_raw_pte_addr_T[52:9], _pte_addr_raw_pte_addr_T[8:0] | pte_addr_vpn_idx}; // @[PTW.scala:325:36, :326:{36,52}]
wire [55:0] pte_addr_raw_pte_addr = {_pte_addr_raw_pte_addr_T_1, 3'h0}; // @[PTW.scala:326:{52,63}]
wire [31:0] pte_addr = pte_addr_raw_pte_addr[31:0]; // @[PTW.scala:326:63, :330:23]
wire _T_44 = state == 3'h1; // @[PTW.scala:233:22, :394:46]
wire _io_dpath_perf_pte_hit_T; // @[PTW.scala:394:46]
assign _io_dpath_perf_pte_hit_T = _T_44; // @[PTW.scala:394:46]
wire _io_mem_req_valid_T; // @[PTW.scala:515:29]
assign _io_mem_req_valid_T = _T_44; // @[PTW.scala:394:46, :515:29]
wire _r_pte_T_4; // @[PTW.scala:672:15]
assign _r_pte_T_4 = _T_44; // @[PTW.scala:394:46, :672:15]
wire _r_pte_T_6; // @[PTW.scala:674:15]
assign _r_pte_T_6 = _T_44; // @[PTW.scala:394:46, :674:15]
reg l2_refill; // @[PTW.scala:398:26]
assign l2_refill_wire = l2_refill; // @[PTW.scala:234:28, :398:26]
wire _invalidated_T = |state; // @[PTW.scala:233:22, :240:30, :511:65]
wire _invalidated_T_1 = invalidated & _invalidated_T; // @[PTW.scala:251:24, :511:{56,65}]
wire _invalidated_T_2 = io_dpath_sfence_valid_0 | _invalidated_T_1; // @[PTW.scala:219:7, :511:{40,56}]
wire _io_mem_req_valid_T_1 = state == 3'h3; // @[PTW.scala:233:22, :515:48]
assign _io_mem_req_valid_T_2 = _io_mem_req_valid_T | _io_mem_req_valid_T_1; // @[PTW.scala:515:{29,39,48}]
assign io_mem_req_valid_0 = _io_mem_req_valid_T_2; // @[PTW.scala:219:7, :515:39]
assign io_mem_req_bits_addr_0 = {8'h0, pte_addr}; // @[PTW.scala:219:7, :330:23, :520:24]
wire _io_mem_req_bits_dv_T = ~stage2; // @[PTW.scala:282:19, :306:38, :523:43]
assign _io_mem_req_bits_dv_T_1 = do_both_stages & _io_mem_req_bits_dv_T; // @[PTW.scala:288:38, :523:{40,43}]
assign io_mem_req_bits_dv_0 = _io_mem_req_bits_dv_T_1; // @[PTW.scala:219:7, :523:40]
wire _io_mem_s1_kill_T = state != 3'h2; // @[PTW.scala:233:22, :531:38]
wire _io_mem_s1_kill_T_1 = _io_mem_s1_kill_T; // @[PTW.scala:531:{28,38}]
assign _io_mem_s1_kill_T_2 = _io_mem_s1_kill_T_1 | resp_gf; // @[PTW.scala:263:20, :531:{28,51}]
assign io_mem_s1_kill_0 = _io_mem_s1_kill_T_2; // @[PTW.scala:219:7, :531:51]
wire [55:0] _GEN_0 = {r_pte_ppn, 12'h0}; // @[PTW.scala:275:18, :544:96]
wire [55:0] _pmaPgLevelHomogeneous_T; // @[PTW.scala:544:96]
assign _pmaPgLevelHomogeneous_T = _GEN_0; // @[PTW.scala:544:96]
wire [55:0] _pmaPgLevelHomogeneous_T_7; // @[PTW.scala:544:96]
assign _pmaPgLevelHomogeneous_T_7 = _GEN_0; // @[PTW.scala:544:96]
wire [55:0] _pmaPgLevelHomogeneous_T_37; // @[PTW.scala:544:96]
assign _pmaPgLevelHomogeneous_T_37 = _GEN_0; // @[PTW.scala:544:96]
wire [55:0] _pmpHomogeneous_T; // @[PTW.scala:548:80]
assign _pmpHomogeneous_T = _GEN_0; // @[PTW.scala:544:96, :548:80]
wire [55:0] _pmaPgLevelHomogeneous_T_21 = _pmaPgLevelHomogeneous_T_7; // @[PTW.scala:544:96]
wire [55:0] _pmaPgLevelHomogeneous_T_28 = _pmaPgLevelHomogeneous_T_7; // @[PTW.scala:544:96]
wire [55:0] _pmaPgLevelHomogeneous_T_8 = {_pmaPgLevelHomogeneous_T_7[55:28], _pmaPgLevelHomogeneous_T_7[27:0] ^ 28'hC000000}; // @[PTW.scala:544:96]
wire [56:0] _pmaPgLevelHomogeneous_T_9 = {1'h0, _pmaPgLevelHomogeneous_T_8}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_10 = _pmaPgLevelHomogeneous_T_9 & 57'h1FFFFFFFC000000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_11 = _pmaPgLevelHomogeneous_T_10; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_12 = _pmaPgLevelHomogeneous_T_11 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_18 = _pmaPgLevelHomogeneous_T_12; // @[TLBPermissions.scala:101:65]
wire [55:0] _pmaPgLevelHomogeneous_T_13 = {_pmaPgLevelHomogeneous_T_7[55:32], _pmaPgLevelHomogeneous_T_7[31:0] ^ 32'h80000000}; // @[PTW.scala:544:96]
wire [56:0] _pmaPgLevelHomogeneous_T_14 = {1'h0, _pmaPgLevelHomogeneous_T_13}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_15 = _pmaPgLevelHomogeneous_T_14 & 57'h1FFFFFFF0000000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_16 = _pmaPgLevelHomogeneous_T_15; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_17 = _pmaPgLevelHomogeneous_T_16 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire pmaPgLevelHomogeneous_1 = _pmaPgLevelHomogeneous_T_18 | _pmaPgLevelHomogeneous_T_17; // @[TLBPermissions.scala:101:65]
wire [56:0] _pmaPgLevelHomogeneous_T_22 = {1'h0, _pmaPgLevelHomogeneous_T_21}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_23 = _pmaPgLevelHomogeneous_T_22 & 57'h80000000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_24 = _pmaPgLevelHomogeneous_T_23; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_25 = _pmaPgLevelHomogeneous_T_24 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_26 = _pmaPgLevelHomogeneous_T_25; // @[TLBPermissions.scala:87:66]
wire _pmaPgLevelHomogeneous_T_27 = ~_pmaPgLevelHomogeneous_T_26; // @[TLBPermissions.scala:87:{22,66}]
wire [56:0] _pmaPgLevelHomogeneous_T_29 = {1'h0, _pmaPgLevelHomogeneous_T_28}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_30 = _pmaPgLevelHomogeneous_T_29 & 57'h80000000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_31 = _pmaPgLevelHomogeneous_T_30; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_32 = _pmaPgLevelHomogeneous_T_31 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_33 = _pmaPgLevelHomogeneous_T_32; // @[TLBPermissions.scala:87:66]
wire _pmaPgLevelHomogeneous_T_34 = ~_pmaPgLevelHomogeneous_T_33; // @[TLBPermissions.scala:87:{22,66}]
wire [55:0] _pmaPgLevelHomogeneous_T_38 = _pmaPgLevelHomogeneous_T_37; // @[PTW.scala:544:96]
wire [55:0] _pmaPgLevelHomogeneous_T_117 = _pmaPgLevelHomogeneous_T_37; // @[PTW.scala:544:96]
wire [56:0] _pmaPgLevelHomogeneous_T_39 = {1'h0, _pmaPgLevelHomogeneous_T_38}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_40 = _pmaPgLevelHomogeneous_T_39 & 57'h1FFFFFFFFFFE000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_41 = _pmaPgLevelHomogeneous_T_40; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_42 = _pmaPgLevelHomogeneous_T_41 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_98 = _pmaPgLevelHomogeneous_T_42; // @[TLBPermissions.scala:101:65]
wire [55:0] _GEN_1 = {_pmaPgLevelHomogeneous_T_37[55:14], _pmaPgLevelHomogeneous_T_37[13:0] ^ 14'h3000}; // @[PTW.scala:544:96]
wire [55:0] _pmaPgLevelHomogeneous_T_43; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_43 = _GEN_1; // @[Parameters.scala:137:31]
wire [55:0] _pmaPgLevelHomogeneous_T_122; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_122 = _GEN_1; // @[Parameters.scala:137:31]
wire [56:0] _pmaPgLevelHomogeneous_T_44 = {1'h0, _pmaPgLevelHomogeneous_T_43}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_45 = _pmaPgLevelHomogeneous_T_44 & 57'h1FFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_46 = _pmaPgLevelHomogeneous_T_45; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_47 = _pmaPgLevelHomogeneous_T_46 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [55:0] _GEN_2 = {_pmaPgLevelHomogeneous_T_37[55:17], _pmaPgLevelHomogeneous_T_37[16:0] ^ 17'h10000}; // @[PTW.scala:544:96]
wire [55:0] _pmaPgLevelHomogeneous_T_48; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_48 = _GEN_2; // @[Parameters.scala:137:31]
wire [55:0] _pmaPgLevelHomogeneous_T_110; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_110 = _GEN_2; // @[Parameters.scala:137:31]
wire [55:0] _pmaPgLevelHomogeneous_T_127; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_127 = _GEN_2; // @[Parameters.scala:137:31]
wire [55:0] _pmaPgLevelHomogeneous_T_159; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_159 = _GEN_2; // @[Parameters.scala:137:31]
wire [55:0] _pmaPgLevelHomogeneous_T_166; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_166 = _GEN_2; // @[Parameters.scala:137:31]
wire [56:0] _pmaPgLevelHomogeneous_T_49 = {1'h0, _pmaPgLevelHomogeneous_T_48}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_50 = _pmaPgLevelHomogeneous_T_49 & 57'h1FFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_51 = _pmaPgLevelHomogeneous_T_50; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_52 = _pmaPgLevelHomogeneous_T_51 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [55:0] _pmaPgLevelHomogeneous_T_53 = {_pmaPgLevelHomogeneous_T_37[55:18], _pmaPgLevelHomogeneous_T_37[17:0] ^ 18'h20000}; // @[PTW.scala:544:96]
wire [56:0] _pmaPgLevelHomogeneous_T_54 = {1'h0, _pmaPgLevelHomogeneous_T_53}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_55 = _pmaPgLevelHomogeneous_T_54 & 57'h1FFFFFFFFFFC000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_56 = _pmaPgLevelHomogeneous_T_55; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_57 = _pmaPgLevelHomogeneous_T_56 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [55:0] _pmaPgLevelHomogeneous_T_58 = {_pmaPgLevelHomogeneous_T_37[55:18], _pmaPgLevelHomogeneous_T_37[17:0] ^ 18'h24000}; // @[PTW.scala:544:96]
wire [56:0] _pmaPgLevelHomogeneous_T_59 = {1'h0, _pmaPgLevelHomogeneous_T_58}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_60 = _pmaPgLevelHomogeneous_T_59 & 57'h1FFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_61 = _pmaPgLevelHomogeneous_T_60; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_62 = _pmaPgLevelHomogeneous_T_61 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [55:0] _pmaPgLevelHomogeneous_T_63 = {_pmaPgLevelHomogeneous_T_37[55:21], _pmaPgLevelHomogeneous_T_37[20:0] ^ 21'h100000}; // @[PTW.scala:544:96]
wire [56:0] _pmaPgLevelHomogeneous_T_64 = {1'h0, _pmaPgLevelHomogeneous_T_63}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_65 = _pmaPgLevelHomogeneous_T_64 & 57'h1FFFFFFFFFEF000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_66 = _pmaPgLevelHomogeneous_T_65; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_67 = _pmaPgLevelHomogeneous_T_66 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [55:0] _pmaPgLevelHomogeneous_T_68 = {_pmaPgLevelHomogeneous_T_37[55:26], _pmaPgLevelHomogeneous_T_37[25:0] ^ 26'h2000000}; // @[PTW.scala:544:96]
wire [56:0] _pmaPgLevelHomogeneous_T_69 = {1'h0, _pmaPgLevelHomogeneous_T_68}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_70 = _pmaPgLevelHomogeneous_T_69 & 57'h1FFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_71 = _pmaPgLevelHomogeneous_T_70; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_72 = _pmaPgLevelHomogeneous_T_71 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [55:0] _pmaPgLevelHomogeneous_T_73 = {_pmaPgLevelHomogeneous_T_37[55:26], _pmaPgLevelHomogeneous_T_37[25:0] ^ 26'h2010000}; // @[PTW.scala:544:96]
wire [56:0] _pmaPgLevelHomogeneous_T_74 = {1'h0, _pmaPgLevelHomogeneous_T_73}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_75 = _pmaPgLevelHomogeneous_T_74 & 57'h1FFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_76 = _pmaPgLevelHomogeneous_T_75; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_77 = _pmaPgLevelHomogeneous_T_76 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [55:0] _GEN_3 = {_pmaPgLevelHomogeneous_T_37[55:28], _pmaPgLevelHomogeneous_T_37[27:0] ^ 28'h8000000}; // @[PTW.scala:544:96]
wire [55:0] _pmaPgLevelHomogeneous_T_78; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_78 = _GEN_3; // @[Parameters.scala:137:31]
wire [55:0] _pmaPgLevelHomogeneous_T_132; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_132 = _GEN_3; // @[Parameters.scala:137:31]
wire [55:0] _pmaPgLevelHomogeneous_T_147; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_147 = _GEN_3; // @[Parameters.scala:137:31]
wire [56:0] _pmaPgLevelHomogeneous_T_79 = {1'h0, _pmaPgLevelHomogeneous_T_78}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_80 = _pmaPgLevelHomogeneous_T_79 & 57'h1FFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_81 = _pmaPgLevelHomogeneous_T_80; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_82 = _pmaPgLevelHomogeneous_T_81 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [55:0] _pmaPgLevelHomogeneous_T_83 = {_pmaPgLevelHomogeneous_T_37[55:28], _pmaPgLevelHomogeneous_T_37[27:0] ^ 28'hC000000}; // @[PTW.scala:544:96]
wire [56:0] _pmaPgLevelHomogeneous_T_84 = {1'h0, _pmaPgLevelHomogeneous_T_83}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_85 = _pmaPgLevelHomogeneous_T_84 & 57'h1FFFFFFFC000000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_86 = _pmaPgLevelHomogeneous_T_85; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_87 = _pmaPgLevelHomogeneous_T_86 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [55:0] _pmaPgLevelHomogeneous_T_88 = {_pmaPgLevelHomogeneous_T_37[55:29], _pmaPgLevelHomogeneous_T_37[28:0] ^ 29'h10020000}; // @[PTW.scala:544:96]
wire [56:0] _pmaPgLevelHomogeneous_T_89 = {1'h0, _pmaPgLevelHomogeneous_T_88}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_90 = _pmaPgLevelHomogeneous_T_89 & 57'h1FFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_91 = _pmaPgLevelHomogeneous_T_90; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_92 = _pmaPgLevelHomogeneous_T_91 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [55:0] _GEN_4 = {_pmaPgLevelHomogeneous_T_37[55:32], _pmaPgLevelHomogeneous_T_37[31:0] ^ 32'h80000000}; // @[PTW.scala:544:96]
wire [55:0] _pmaPgLevelHomogeneous_T_93; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_93 = _GEN_4; // @[Parameters.scala:137:31]
wire [55:0] _pmaPgLevelHomogeneous_T_137; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_137 = _GEN_4; // @[Parameters.scala:137:31]
wire [55:0] _pmaPgLevelHomogeneous_T_152; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_152 = _GEN_4; // @[Parameters.scala:137:31]
wire [56:0] _pmaPgLevelHomogeneous_T_94 = {1'h0, _pmaPgLevelHomogeneous_T_93}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_95 = _pmaPgLevelHomogeneous_T_94 & 57'h1FFFFFFF0000000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_96 = _pmaPgLevelHomogeneous_T_95; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_97 = _pmaPgLevelHomogeneous_T_96 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_99 = _pmaPgLevelHomogeneous_T_98 | _pmaPgLevelHomogeneous_T_47; // @[TLBPermissions.scala:101:65]
wire _pmaPgLevelHomogeneous_T_100 = _pmaPgLevelHomogeneous_T_99 | _pmaPgLevelHomogeneous_T_52; // @[TLBPermissions.scala:101:65]
wire _pmaPgLevelHomogeneous_T_101 = _pmaPgLevelHomogeneous_T_100 | _pmaPgLevelHomogeneous_T_57; // @[TLBPermissions.scala:101:65]
wire _pmaPgLevelHomogeneous_T_102 = _pmaPgLevelHomogeneous_T_101 | _pmaPgLevelHomogeneous_T_62; // @[TLBPermissions.scala:101:65]
wire _pmaPgLevelHomogeneous_T_103 = _pmaPgLevelHomogeneous_T_102 | _pmaPgLevelHomogeneous_T_67; // @[TLBPermissions.scala:101:65]
wire _pmaPgLevelHomogeneous_T_104 = _pmaPgLevelHomogeneous_T_103 | _pmaPgLevelHomogeneous_T_72; // @[TLBPermissions.scala:101:65]
wire _pmaPgLevelHomogeneous_T_105 = _pmaPgLevelHomogeneous_T_104 | _pmaPgLevelHomogeneous_T_77; // @[TLBPermissions.scala:101:65]
wire _pmaPgLevelHomogeneous_T_106 = _pmaPgLevelHomogeneous_T_105 | _pmaPgLevelHomogeneous_T_82; // @[TLBPermissions.scala:101:65]
wire _pmaPgLevelHomogeneous_T_107 = _pmaPgLevelHomogeneous_T_106 | _pmaPgLevelHomogeneous_T_87; // @[TLBPermissions.scala:101:65]
wire _pmaPgLevelHomogeneous_T_108 = _pmaPgLevelHomogeneous_T_107 | _pmaPgLevelHomogeneous_T_92; // @[TLBPermissions.scala:101:65]
wire pmaPgLevelHomogeneous_2 = _pmaPgLevelHomogeneous_T_108 | _pmaPgLevelHomogeneous_T_97; // @[TLBPermissions.scala:101:65]
wire [56:0] _pmaPgLevelHomogeneous_T_111 = {1'h0, _pmaPgLevelHomogeneous_T_110}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_112 = _pmaPgLevelHomogeneous_T_111 & 57'h8A130000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_113 = _pmaPgLevelHomogeneous_T_112; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_114 = _pmaPgLevelHomogeneous_T_113 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_115 = _pmaPgLevelHomogeneous_T_114; // @[TLBPermissions.scala:87:66]
wire _pmaPgLevelHomogeneous_T_116 = ~_pmaPgLevelHomogeneous_T_115; // @[TLBPermissions.scala:87:{22,66}]
wire [56:0] _pmaPgLevelHomogeneous_T_118 = {1'h0, _pmaPgLevelHomogeneous_T_117}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_119 = _pmaPgLevelHomogeneous_T_118 & 57'hFFFF3000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_120 = _pmaPgLevelHomogeneous_T_119; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_121 = _pmaPgLevelHomogeneous_T_120 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_142 = _pmaPgLevelHomogeneous_T_121; // @[TLBPermissions.scala:85:66]
wire [56:0] _pmaPgLevelHomogeneous_T_123 = {1'h0, _pmaPgLevelHomogeneous_T_122}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_124 = _pmaPgLevelHomogeneous_T_123 & 57'hFFFF3000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_125 = _pmaPgLevelHomogeneous_T_124; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_126 = _pmaPgLevelHomogeneous_T_125 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [56:0] _pmaPgLevelHomogeneous_T_128 = {1'h0, _pmaPgLevelHomogeneous_T_127}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_129 = _pmaPgLevelHomogeneous_T_128 & 57'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_130 = _pmaPgLevelHomogeneous_T_129; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_131 = _pmaPgLevelHomogeneous_T_130 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [56:0] _pmaPgLevelHomogeneous_T_133 = {1'h0, _pmaPgLevelHomogeneous_T_132}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_134 = _pmaPgLevelHomogeneous_T_133 & 57'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_135 = _pmaPgLevelHomogeneous_T_134; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_136 = _pmaPgLevelHomogeneous_T_135 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [56:0] _pmaPgLevelHomogeneous_T_138 = {1'h0, _pmaPgLevelHomogeneous_T_137}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_139 = _pmaPgLevelHomogeneous_T_138 & 57'hF0000000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_140 = _pmaPgLevelHomogeneous_T_139; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_141 = _pmaPgLevelHomogeneous_T_140 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_143 = _pmaPgLevelHomogeneous_T_142 | _pmaPgLevelHomogeneous_T_126; // @[TLBPermissions.scala:85:66]
wire _pmaPgLevelHomogeneous_T_144 = _pmaPgLevelHomogeneous_T_143 | _pmaPgLevelHomogeneous_T_131; // @[TLBPermissions.scala:85:66]
wire _pmaPgLevelHomogeneous_T_145 = _pmaPgLevelHomogeneous_T_144 | _pmaPgLevelHomogeneous_T_136; // @[TLBPermissions.scala:85:66]
wire _pmaPgLevelHomogeneous_T_146 = _pmaPgLevelHomogeneous_T_145 | _pmaPgLevelHomogeneous_T_141; // @[TLBPermissions.scala:85:66]
wire [56:0] _pmaPgLevelHomogeneous_T_148 = {1'h0, _pmaPgLevelHomogeneous_T_147}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_149 = _pmaPgLevelHomogeneous_T_148 & 57'h8E020000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_150 = _pmaPgLevelHomogeneous_T_149; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_151 = _pmaPgLevelHomogeneous_T_150 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_157 = _pmaPgLevelHomogeneous_T_151; // @[TLBPermissions.scala:85:66]
wire [56:0] _pmaPgLevelHomogeneous_T_153 = {1'h0, _pmaPgLevelHomogeneous_T_152}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_154 = _pmaPgLevelHomogeneous_T_153 & 57'h80000000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_155 = _pmaPgLevelHomogeneous_T_154; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_156 = _pmaPgLevelHomogeneous_T_155 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_158 = _pmaPgLevelHomogeneous_T_157 | _pmaPgLevelHomogeneous_T_156; // @[TLBPermissions.scala:85:66]
wire [56:0] _pmaPgLevelHomogeneous_T_160 = {1'h0, _pmaPgLevelHomogeneous_T_159}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_161 = _pmaPgLevelHomogeneous_T_160 & 57'h8A130000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_162 = _pmaPgLevelHomogeneous_T_161; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_163 = _pmaPgLevelHomogeneous_T_162 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_164 = _pmaPgLevelHomogeneous_T_163; // @[TLBPermissions.scala:87:66]
wire _pmaPgLevelHomogeneous_T_165 = ~_pmaPgLevelHomogeneous_T_164; // @[TLBPermissions.scala:87:{22,66}]
wire [56:0] _pmaPgLevelHomogeneous_T_167 = {1'h0, _pmaPgLevelHomogeneous_T_166}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_168 = _pmaPgLevelHomogeneous_T_167 & 57'h8A130000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_169 = _pmaPgLevelHomogeneous_T_168; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_170 = _pmaPgLevelHomogeneous_T_169 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_171 = _pmaPgLevelHomogeneous_T_170; // @[TLBPermissions.scala:87:66]
wire _pmaPgLevelHomogeneous_T_172 = ~_pmaPgLevelHomogeneous_T_171; // @[TLBPermissions.scala:87:{22,66}]
wire _pmaHomogeneous_T_1 = _pmaHomogeneous_T & pmaPgLevelHomogeneous_1; // @[package.scala:39:{76,86}]
wire _pmaHomogeneous_T_3 = _pmaHomogeneous_T_2 ? pmaPgLevelHomogeneous_2 : _pmaHomogeneous_T_1; // @[package.scala:39:{76,86}]
wire _pmaHomogeneous_T_4 = &count; // @[package.scala:39:86]
wire pmaHomogeneous = _pmaHomogeneous_T_4 ? pmaPgLevelHomogeneous_2 : _pmaHomogeneous_T_3; // @[package.scala:39:{76,86}]
wire homogeneous = pmaHomogeneous; // @[package.scala:39:76]
assign _io_requestor_0_resp_bits_homogeneous_T = homogeneous; // @[PTW.scala:549:36, :562:58]
assign io_requestor_0_resp_bits_homogeneous_0 = _io_requestor_0_resp_bits_homogeneous_T; // @[PTW.scala:219:7, :562:58]
wire _io_requestor_0_resp_bits_gpa_bits_T = ~stage2_final; // @[PTW.scala:283:25, :566:15]
wire _io_requestor_0_resp_bits_gpa_bits_T_1 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32]
wire _io_requestor_0_resp_bits_gpa_bits_T_2 = _io_requestor_0_resp_bits_gpa_bits_T | _io_requestor_0_resp_bits_gpa_bits_T_1; // @[PTW.scala:566:{15,29,32}]
wire _T_61 = aux_count == 2'h2; // @[PTW.scala:278:22, :566:60]
wire _io_requestor_0_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:60]
assign _io_requestor_0_resp_bits_gpa_bits_T_3 = _T_61; // @[PTW.scala:566:60]
wire _gpa_pgoff_T; // @[PTW.scala:615:36]
assign _gpa_pgoff_T = _T_61; // @[PTW.scala:566:60, :615:36]
wire _l2_refill_T_7; // @[PTW.scala:715:40]
assign _l2_refill_T_7 = _T_61; // @[PTW.scala:566:60, :715:40]
wire _io_requestor_0_resp_bits_gpa_bits_T_4 = _io_requestor_0_resp_bits_gpa_bits_T_2 | _io_requestor_0_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:{29,47,60}]
wire [25:0] _io_requestor_0_resp_bits_gpa_bits_T_5 = aux_pte_ppn[43:18]; // @[PTW.scala:280:20, :343:49]
wire [17:0] _io_requestor_0_resp_bits_gpa_bits_T_6 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79]
wire [17:0] _r_pte_T_18 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79]
wire [17:0] _aux_pte_s1_ppns_T_1 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79, :744:122]
wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_7 = {_io_requestor_0_resp_bits_gpa_bits_T_5, _io_requestor_0_resp_bits_gpa_bits_T_6}; // @[PTW.scala:343:{44,49,79}]
wire [34:0] _io_requestor_0_resp_bits_gpa_bits_T_8 = aux_pte_ppn[43:9]; // @[PTW.scala:280:20, :343:49]
wire [8:0] _io_requestor_0_resp_bits_gpa_bits_T_9 = r_req_addr[8:0]; // @[PTW.scala:270:18, :343:79]
wire [8:0] _r_pte_T_21 = r_req_addr[8:0]; // @[PTW.scala:270:18, :343:79]
wire [8:0] _aux_pte_s1_ppns_T_3 = r_req_addr[8:0]; // @[PTW.scala:270:18, :343:79, :744:122]
wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_10 = {_io_requestor_0_resp_bits_gpa_bits_T_8, _io_requestor_0_resp_bits_gpa_bits_T_9}; // @[PTW.scala:343:{44,49,79}]
wire io_requestor_0_resp_bits_gpa_bits_truncIdx = _io_requestor_0_resp_bits_gpa_bits_truncIdx_T[0]; // @[package.scala:38:{21,47}]
wire _io_requestor_0_resp_bits_gpa_bits_T_11 = io_requestor_0_resp_bits_gpa_bits_truncIdx; // @[package.scala:38:47, :39:86]
wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_12 = _io_requestor_0_resp_bits_gpa_bits_T_11 ? _io_requestor_0_resp_bits_gpa_bits_T_10 : _io_requestor_0_resp_bits_gpa_bits_T_7; // @[package.scala:39:{76,86}]
wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_13 = _io_requestor_0_resp_bits_gpa_bits_T_4 ? aux_pte_ppn : _io_requestor_0_resp_bits_gpa_bits_T_12; // @[package.scala:39:76]
wire [55:0] _io_requestor_0_resp_bits_gpa_bits_T_14 = {_io_requestor_0_resp_bits_gpa_bits_T_13, gpa_pgoff}; // @[PTW.scala:281:22, :566:{10,14}]
assign io_requestor_0_resp_bits_gpa_bits_0 = _io_requestor_0_resp_bits_gpa_bits_T_14[38:0]; // @[PTW.scala:219:7, :565:40, :566:10]
assign _io_requestor_0_resp_bits_gpa_is_pte_T = ~stage2_final; // @[PTW.scala:283:25, :566:15, :567:45]
assign io_requestor_0_resp_bits_gpa_is_pte_0 = _io_requestor_0_resp_bits_gpa_is_pte_T; // @[PTW.scala:219:7, :567:45]
wire [2:0] next_state; // @[PTW.scala:579:31]
wire do_switch; // @[PTW.scala:581:30]
wire _T_27 = _arb_io_out_ready_T_2 & _arb_io_out_valid; // @[Decoupled.scala:51:35]
wire _GEN_5 = ~(|state) & _T_27; // @[Decoupled.scala:51:35]
wire [43:0] aux_ppn = {17'h0, _arb_io_out_bits_bits_addr}; // @[PTW.scala:236:19, :589:38]
wire [14:0] resp_gf_idxs_0 = aux_ppn[43:29]; // @[PTW.scala:589:38, :787:58]
wire [14:0] _resp_gf_WIRE_0 = resp_gf_idxs_0; // @[package.scala:43:40]
wire _resp_gf_T_1 = |_resp_gf_WIRE_0; // @[package.scala:43:40]
wire [29:0] _gpa_pgoff_T_1 = {r_req_addr, 3'h0}; // @[PTW.scala:270:18, :615:67]
wire [29:0] _gpa_pgoff_T_2 = _gpa_pgoff_T ? _gpa_pgoff_T_1 : 30'h0; // @[PTW.scala:615:{25,36,67}]
wire [2:0] _aux_count_T_1 = {1'h0, aux_count} + 3'h1; // @[PTW.scala:278:22, :619:32]
wire [1:0] _aux_count_T_2 = _aux_count_T_1[1:0]; // @[PTW.scala:619:32]
wire [2:0] _GEN_6 = {1'h0, count} + 3'h1; // @[PTW.scala:259:18, :624:24]
wire [2:0] _count_T_4; // @[PTW.scala:624:24]
assign _count_T_4 = _GEN_6; // @[PTW.scala:624:24]
wire [2:0] _count_T_6; // @[PTW.scala:696:22]
assign _count_T_6 = _GEN_6; // @[PTW.scala:624:24, :696:22]
wire [2:0] _aux_count_T_3; // @[PTW.scala:741:38]
assign _aux_count_T_3 = _GEN_6; // @[PTW.scala:624:24, :741:38]
wire [1:0] _count_T_5 = _count_T_4[1:0]; // @[PTW.scala:624:24]
wire [2:0] _next_state_T_1 = io_mem_req_ready_0 ? 3'h2 : 3'h1; // @[PTW.scala:219:7, :627:26]
wire _T_36 = state == 3'h2; // @[PTW.scala:233:22, :583:18]
wire _T_37 = state == 3'h4; // @[PTW.scala:233:22, :583:18]
wire _io_dpath_perf_pte_miss_T = ~(count[1]); // @[PTW.scala:259:18, :310:21, :317:73, :640:39]
wire _GEN_7 = _T_44 | _T_36; // @[PTW.scala:393:26, :394:46, :583:18]
assign io_dpath_perf_pte_miss_0 = ~(~(|state) | _GEN_7) & _T_37 & _io_dpath_perf_pte_miss_T; // @[PTW.scala:219:7, :233:22, :240:30, :393:26, :583:18, :640:{30,39}]
wire [1:0] _merged_pte_superpage_mask_T = stage2_final ? max_count : 2'h2; // @[PTW.scala:283:25, :289:25, :662:45]
wire _merged_pte_superpage_mask_T_1 = _merged_pte_superpage_mask_T == 2'h1; // @[package.scala:39:86]
wire [43:0] _merged_pte_superpage_mask_T_2 = _merged_pte_superpage_mask_T_1 ? 44'hFFFFFFFFE00 : 44'hFFFFFFC0000; // @[package.scala:39:{76,86}]
wire _merged_pte_superpage_mask_T_3 = _merged_pte_superpage_mask_T == 2'h2; // @[package.scala:39:86]
wire [43:0] _merged_pte_superpage_mask_T_4 = _merged_pte_superpage_mask_T_3 ? 44'hFFFFFFFFFFF : _merged_pte_superpage_mask_T_2; // @[package.scala:39:{76,86}]
wire _merged_pte_superpage_mask_T_5 = &_merged_pte_superpage_mask_T; // @[package.scala:39:86]
wire [43:0] merged_pte_superpage_mask = _merged_pte_superpage_mask_T_5 ? 44'hFFFFFFFFFFF : _merged_pte_superpage_mask_T_4; // @[package.scala:39:{76,86}]
wire [25:0] _merged_pte_stage1_ppns_T = pte_ppn[43:18]; // @[PTW.scala:305:26, :663:64]
wire [25:0] _aux_pte_s1_ppns_T = pte_ppn[43:18]; // @[PTW.scala:305:26, :663:64, :744:62]
wire [17:0] _merged_pte_stage1_ppns_T_1 = aux_pte_ppn[17:0]; // @[PTW.scala:280:20, :663:125]
wire [43:0] merged_pte_stage1_ppns_0 = {_merged_pte_stage1_ppns_T, _merged_pte_stage1_ppns_T_1}; // @[PTW.scala:663:{56,64,125}]
wire [34:0] _merged_pte_stage1_ppns_T_2 = pte_ppn[43:9]; // @[PTW.scala:305:26, :663:64]
wire [34:0] _aux_pte_s1_ppns_T_2 = pte_ppn[43:9]; // @[PTW.scala:305:26, :663:64, :744:62]
wire [8:0] _merged_pte_stage1_ppns_T_3 = aux_pte_ppn[8:0]; // @[PTW.scala:280:20, :663:125]
wire [43:0] merged_pte_stage1_ppns_1 = {_merged_pte_stage1_ppns_T_2, _merged_pte_stage1_ppns_T_3}; // @[PTW.scala:663:{56,64,125}]
wire [43:0] _merged_pte_stage1_ppn_T_1 = _merged_pte_stage1_ppn_T ? merged_pte_stage1_ppns_1 : merged_pte_stage1_ppns_0; // @[package.scala:39:{76,86}]
wire [43:0] _merged_pte_stage1_ppn_T_3 = _merged_pte_stage1_ppn_T_2 ? pte_ppn : _merged_pte_stage1_ppn_T_1; // @[package.scala:39:{76,86}]
wire _merged_pte_stage1_ppn_T_4 = &count; // @[package.scala:39:86]
wire [43:0] merged_pte_stage1_ppn = _merged_pte_stage1_ppn_T_4 ? pte_ppn : _merged_pte_stage1_ppn_T_3; // @[package.scala:39:{76,86}]
wire [43:0] _merged_pte_T = merged_pte_stage1_ppn & merged_pte_superpage_mask; // @[package.scala:39:76]
wire [43:0] merged_pte_ppn = _merged_pte_T; // @[PTW.scala:665:24, :771:26]
wire _r_pte_T_2 = ~resp_gf; // @[PTW.scala:263:20, :670:32]
wire [16:0] r_pte_idxs_0_1 = pte_ppn[43:27]; // @[PTW.scala:305:26, :778:58]
wire [1:0] r_pte_lsbs_1; // @[PTW.scala:779:27]
assign r_pte_lsbs_1 = r_pte_idxs_0_1[1:0]; // @[PTW.scala:778:58, :779:27]
wire [43:0] _r_pte_pte_ppn_T_3; // @[PTW.scala:781:19]
wire [43:0] r_pte_pte_2_ppn; // @[PTW.scala:780:26]
assign _r_pte_pte_ppn_T_3 = {42'h0, r_pte_lsbs_1}; // @[PTW.scala:779:27, :781:19]
assign r_pte_pte_2_ppn = _r_pte_pte_ppn_T_3; // @[PTW.scala:780:26, :781:19]
wire _r_pte_T_8 = ~traverse; // @[PTW.scala:317:64, :678:29]
wire _r_pte_T_9 = _r_pte_T_8 & r_req_vstage1; // @[PTW.scala:270:18, :678:{29,39}]
wire _r_pte_T_10 = _r_pte_T_9 & stage2; // @[PTW.scala:282:19, :678:{39,56}]
wire [9:0] _r_pte_T_11_reserved_for_future = _r_pte_T_10 ? merged_pte_reserved_for_future : pte_reserved_for_future; // @[PTW.scala:305:26, :678:{28,56}, :771:26]
wire [43:0] _r_pte_T_11_ppn = _r_pte_T_10 ? merged_pte_ppn : pte_ppn; // @[PTW.scala:305:26, :678:{28,56}, :771:26]
wire [1:0] _r_pte_T_11_reserved_for_software = _r_pte_T_10 ? merged_pte_reserved_for_software : pte_reserved_for_software; // @[PTW.scala:305:26, :678:{28,56}, :771:26]
wire _r_pte_T_11_d = _r_pte_T_10 ? merged_pte_d : pte_d; // @[PTW.scala:305:26, :678:{28,56}, :771:26]
wire _r_pte_T_11_a = _r_pte_T_10 ? merged_pte_a : pte_a; // @[PTW.scala:305:26, :678:{28,56}, :771:26]
wire _r_pte_T_11_g = _r_pte_T_10 ? merged_pte_g : pte_g; // @[PTW.scala:305:26, :678:{28,56}, :771:26]
wire _r_pte_T_11_u = _r_pte_T_10 ? merged_pte_u : pte_u; // @[PTW.scala:305:26, :678:{28,56}, :771:26]
wire _r_pte_T_11_x = _r_pte_T_10 ? merged_pte_x : pte_x; // @[PTW.scala:305:26, :678:{28,56}, :771:26]
wire _r_pte_T_11_w = _r_pte_T_10 ? merged_pte_w : pte_w; // @[PTW.scala:305:26, :678:{28,56}, :771:26]
wire _r_pte_T_11_r = _r_pte_T_10 ? merged_pte_r : pte_r; // @[PTW.scala:305:26, :678:{28,56}, :771:26]
wire _r_pte_T_11_v = _r_pte_T_10 ? merged_pte_v : pte_v; // @[PTW.scala:305:26, :678:{28,56}, :771:26]
wire _r_pte_T_12 = &state; // @[PTW.scala:233:22, :680:15]
wire _r_pte_T_13 = ~homogeneous; // @[PTW.scala:549:36, :680:43]
wire _r_pte_T_14 = _r_pte_T_12 & _r_pte_T_13; // @[PTW.scala:680:{15,40,43}]
wire _r_pte_T_15 = count != 2'h2; // @[PTW.scala:259:18, :680:65]
wire _r_pte_T_16 = _r_pte_T_14 & _r_pte_T_15; // @[PTW.scala:680:{40,56,65}]
wire [25:0] _r_pte_T_17 = r_pte_ppn[43:18]; // @[PTW.scala:275:18, :343:49]
wire [43:0] _r_pte_T_19 = {_r_pte_T_17, _r_pte_T_18}; // @[PTW.scala:343:{44,49,79}]
wire [34:0] _r_pte_T_20 = r_pte_ppn[43:9]; // @[PTW.scala:275:18, :343:49]
wire [43:0] _r_pte_T_22 = {_r_pte_T_20, _r_pte_T_21}; // @[PTW.scala:343:{44,49,79}]
wire r_pte_truncIdx = _r_pte_truncIdx_T[0]; // @[package.scala:38:{21,47}]
wire _r_pte_T_23 = r_pte_truncIdx; // @[package.scala:38:47, :39:86]
wire [43:0] _r_pte_T_24 = _r_pte_T_23 ? _r_pte_T_22 : _r_pte_T_19; // @[package.scala:39:{76,86}]
wire [43:0] r_pte_pte_3_ppn = _r_pte_T_24; // @[package.scala:39:76]
wire _r_pte_T_25 = _arb_io_out_ready_T_2 & _arb_io_out_valid; // @[Decoupled.scala:51:35]
wire [9:0] _r_pte_T_26_reserved_for_future = r_pte_pte_5_reserved_for_future; // @[PTW.scala:682:29, :771:26]
wire [43:0] _r_pte_T_26_ppn = r_pte_pte_5_ppn; // @[PTW.scala:682:29, :771:26]
wire [1:0] _r_pte_T_26_reserved_for_software = r_pte_pte_5_reserved_for_software; // @[PTW.scala:682:29, :771:26]
wire _r_pte_T_26_d = r_pte_pte_5_d; // @[PTW.scala:682:29, :771:26]
wire _r_pte_T_26_a = r_pte_pte_5_a; // @[PTW.scala:682:29, :771:26]
wire _r_pte_T_26_g = r_pte_pte_5_g; // @[PTW.scala:682:29, :771:26]
wire _r_pte_T_26_u = r_pte_pte_5_u; // @[PTW.scala:682:29, :771:26]
wire _r_pte_T_26_x = r_pte_pte_5_x; // @[PTW.scala:682:29, :771:26]
wire _r_pte_T_26_w = r_pte_pte_5_w; // @[PTW.scala:682:29, :771:26]
wire _r_pte_T_26_r = r_pte_pte_5_r; // @[PTW.scala:682:29, :771:26]
wire _r_pte_T_26_v = r_pte_pte_5_v; // @[PTW.scala:682:29, :771:26]
wire [9:0] _r_pte_T_27_reserved_for_future = _r_pte_T_25 ? _r_pte_T_26_reserved_for_future : r_pte_reserved_for_future; // @[Decoupled.scala:51:35]
wire [43:0] _r_pte_T_27_ppn = _r_pte_T_25 ? _r_pte_T_26_ppn : r_pte_ppn; // @[Decoupled.scala:51:35]
wire [1:0] _r_pte_T_27_reserved_for_software = _r_pte_T_25 ? _r_pte_T_26_reserved_for_software : r_pte_reserved_for_software; // @[Decoupled.scala:51:35]
wire _r_pte_T_27_d = _r_pte_T_25 ? _r_pte_T_26_d : r_pte_d; // @[Decoupled.scala:51:35]
wire _r_pte_T_27_a = _r_pte_T_25 ? _r_pte_T_26_a : r_pte_a; // @[Decoupled.scala:51:35]
wire _r_pte_T_27_g = _r_pte_T_25 ? _r_pte_T_26_g : r_pte_g; // @[Decoupled.scala:51:35]
wire _r_pte_T_27_u = _r_pte_T_25 ? _r_pte_T_26_u : r_pte_u; // @[Decoupled.scala:51:35]
wire _r_pte_T_27_x = _r_pte_T_25 ? _r_pte_T_26_x : r_pte_x; // @[Decoupled.scala:51:35]
wire _r_pte_T_27_w = _r_pte_T_25 ? _r_pte_T_26_w : r_pte_w; // @[Decoupled.scala:51:35]
wire _r_pte_T_27_r = _r_pte_T_25 ? _r_pte_T_26_r : r_pte_r; // @[Decoupled.scala:51:35]
wire _r_pte_T_27_v = _r_pte_T_25 ? _r_pte_T_26_v : r_pte_v; // @[Decoupled.scala:51:35]
wire [9:0] _r_pte_T_28_reserved_for_future = _r_pte_T_16 ? r_pte_pte_3_reserved_for_future : _r_pte_T_27_reserved_for_future; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire [43:0] _r_pte_T_28_ppn = _r_pte_T_16 ? r_pte_pte_3_ppn : _r_pte_T_27_ppn; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire [1:0] _r_pte_T_28_reserved_for_software = _r_pte_T_16 ? r_pte_pte_3_reserved_for_software : _r_pte_T_27_reserved_for_software; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire _r_pte_T_28_d = _r_pte_T_16 ? r_pte_pte_3_d : _r_pte_T_27_d; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire _r_pte_T_28_a = _r_pte_T_16 ? r_pte_pte_3_a : _r_pte_T_27_a; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire _r_pte_T_28_g = _r_pte_T_16 ? r_pte_pte_3_g : _r_pte_T_27_g; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire _r_pte_T_28_u = _r_pte_T_16 ? r_pte_pte_3_u : _r_pte_T_27_u; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire _r_pte_T_28_x = _r_pte_T_16 ? r_pte_pte_3_x : _r_pte_T_27_x; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire _r_pte_T_28_w = _r_pte_T_16 ? r_pte_pte_3_w : _r_pte_T_27_w; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire _r_pte_T_28_r = _r_pte_T_16 ? r_pte_pte_3_r : _r_pte_T_27_r; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire _r_pte_T_28_v = _r_pte_T_16 ? r_pte_pte_3_v : _r_pte_T_27_v; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire [9:0] _r_pte_T_29_reserved_for_future = mem_resp_valid ? _r_pte_T_11_reserved_for_future : _r_pte_T_28_reserved_for_future; // @[PTW.scala:292:31, :678:{8,28}, :680:8]
wire [43:0] _r_pte_T_29_ppn = mem_resp_valid ? _r_pte_T_11_ppn : _r_pte_T_28_ppn; // @[PTW.scala:292:31, :678:{8,28}, :680:8]
wire [1:0] _r_pte_T_29_reserved_for_software = mem_resp_valid ? _r_pte_T_11_reserved_for_software : _r_pte_T_28_reserved_for_software; // @[PTW.scala:292:31, :678:{8,28}, :680:8]
wire _r_pte_T_29_d = mem_resp_valid ? _r_pte_T_11_d : _r_pte_T_28_d; // @[PTW.scala:292:31, :678:{8,28}, :680:8]
wire _r_pte_T_29_a = mem_resp_valid ? _r_pte_T_11_a : _r_pte_T_28_a; // @[PTW.scala:292:31, :678:{8,28}, :680:8]
wire _r_pte_T_29_g = mem_resp_valid ? _r_pte_T_11_g : _r_pte_T_28_g; // @[PTW.scala:292:31, :678:{8,28}, :680:8]
wire _r_pte_T_29_u = mem_resp_valid ? _r_pte_T_11_u : _r_pte_T_28_u; // @[PTW.scala:292:31, :678:{8,28}, :680:8]
wire _r_pte_T_29_x = mem_resp_valid ? _r_pte_T_11_x : _r_pte_T_28_x; // @[PTW.scala:292:31, :678:{8,28}, :680:8]
wire _r_pte_T_29_w = mem_resp_valid ? _r_pte_T_11_w : _r_pte_T_28_w; // @[PTW.scala:292:31, :678:{8,28}, :680:8]
wire _r_pte_T_29_r = mem_resp_valid ? _r_pte_T_11_r : _r_pte_T_28_r; // @[PTW.scala:292:31, :678:{8,28}, :680:8]
wire _r_pte_T_29_v = mem_resp_valid ? _r_pte_T_11_v : _r_pte_T_28_v; // @[PTW.scala:292:31, :678:{8,28}, :680:8]
wire [9:0] _r_pte_T_30_reserved_for_future = do_switch ? r_pte_pte_2_reserved_for_future : _r_pte_T_29_reserved_for_future; // @[PTW.scala:581:30, :676:8, :678:8, :780:26]
wire [43:0] _r_pte_T_30_ppn = do_switch ? r_pte_pte_2_ppn : _r_pte_T_29_ppn; // @[PTW.scala:581:30, :676:8, :678:8, :780:26]
wire [1:0] _r_pte_T_30_reserved_for_software = do_switch ? r_pte_pte_2_reserved_for_software : _r_pte_T_29_reserved_for_software; // @[PTW.scala:581:30, :676:8, :678:8, :780:26]
wire _r_pte_T_30_d = do_switch ? r_pte_pte_2_d : _r_pte_T_29_d; // @[PTW.scala:581:30, :676:8, :678:8, :780:26]
wire _r_pte_T_30_a = do_switch ? r_pte_pte_2_a : _r_pte_T_29_a; // @[PTW.scala:581:30, :676:8, :678:8, :780:26]
wire _r_pte_T_30_g = do_switch ? r_pte_pte_2_g : _r_pte_T_29_g; // @[PTW.scala:581:30, :676:8, :678:8, :780:26]
wire _r_pte_T_30_u = do_switch ? r_pte_pte_2_u : _r_pte_T_29_u; // @[PTW.scala:581:30, :676:8, :678:8, :780:26]
wire _r_pte_T_30_x = do_switch ? r_pte_pte_2_x : _r_pte_T_29_x; // @[PTW.scala:581:30, :676:8, :678:8, :780:26]
wire _r_pte_T_30_w = do_switch ? r_pte_pte_2_w : _r_pte_T_29_w; // @[PTW.scala:581:30, :676:8, :678:8, :780:26]
wire _r_pte_T_30_r = do_switch ? r_pte_pte_2_r : _r_pte_T_29_r; // @[PTW.scala:581:30, :676:8, :678:8, :780:26]
wire _r_pte_T_30_v = do_switch ? r_pte_pte_2_v : _r_pte_T_29_v; // @[PTW.scala:581:30, :676:8, :678:8, :780:26]
wire [9:0] _r_pte_T_31_reserved_for_future = _r_pte_T_30_reserved_for_future; // @[PTW.scala:674:8, :676:8]
wire [43:0] _r_pte_T_31_ppn = _r_pte_T_30_ppn; // @[PTW.scala:674:8, :676:8]
wire [1:0] _r_pte_T_31_reserved_for_software = _r_pte_T_30_reserved_for_software; // @[PTW.scala:674:8, :676:8]
wire _r_pte_T_31_d = _r_pte_T_30_d; // @[PTW.scala:674:8, :676:8]
wire _r_pte_T_31_a = _r_pte_T_30_a; // @[PTW.scala:674:8, :676:8]
wire _r_pte_T_31_g = _r_pte_T_30_g; // @[PTW.scala:674:8, :676:8]
wire _r_pte_T_31_u = _r_pte_T_30_u; // @[PTW.scala:674:8, :676:8]
wire _r_pte_T_31_x = _r_pte_T_30_x; // @[PTW.scala:674:8, :676:8]
wire _r_pte_T_31_w = _r_pte_T_30_w; // @[PTW.scala:674:8, :676:8]
wire _r_pte_T_31_r = _r_pte_T_30_r; // @[PTW.scala:674:8, :676:8]
wire _r_pte_T_31_v = _r_pte_T_30_v; // @[PTW.scala:674:8, :676:8]
wire [9:0] _r_pte_T_32_reserved_for_future = _r_pte_T_31_reserved_for_future; // @[PTW.scala:672:8, :674:8]
wire [43:0] _r_pte_T_32_ppn = _r_pte_T_31_ppn; // @[PTW.scala:672:8, :674:8]
wire [1:0] _r_pte_T_32_reserved_for_software = _r_pte_T_31_reserved_for_software; // @[PTW.scala:672:8, :674:8]
wire _r_pte_T_32_d = _r_pte_T_31_d; // @[PTW.scala:672:8, :674:8]
wire _r_pte_T_32_a = _r_pte_T_31_a; // @[PTW.scala:672:8, :674:8]
wire _r_pte_T_32_g = _r_pte_T_31_g; // @[PTW.scala:672:8, :674:8]
wire _r_pte_T_32_u = _r_pte_T_31_u; // @[PTW.scala:672:8, :674:8]
wire _r_pte_T_32_x = _r_pte_T_31_x; // @[PTW.scala:672:8, :674:8]
wire _r_pte_T_32_w = _r_pte_T_31_w; // @[PTW.scala:672:8, :674:8]
wire _r_pte_T_32_r = _r_pte_T_31_r; // @[PTW.scala:672:8, :674:8]
wire _r_pte_T_32_v = _r_pte_T_31_v; // @[PTW.scala:672:8, :674:8]
wire [9:0] _r_pte_T_33_reserved_for_future = _r_pte_T_32_reserved_for_future; // @[PTW.scala:670:8, :672:8]
wire [43:0] _r_pte_T_33_ppn = _r_pte_T_32_ppn; // @[PTW.scala:670:8, :672:8]
wire [1:0] _r_pte_T_33_reserved_for_software = _r_pte_T_32_reserved_for_software; // @[PTW.scala:670:8, :672:8]
wire _r_pte_T_33_d = _r_pte_T_32_d; // @[PTW.scala:670:8, :672:8]
wire _r_pte_T_33_a = _r_pte_T_32_a; // @[PTW.scala:670:8, :672:8]
wire _r_pte_T_33_g = _r_pte_T_32_g; // @[PTW.scala:670:8, :672:8]
wire _r_pte_T_33_u = _r_pte_T_32_u; // @[PTW.scala:670:8, :672:8]
wire _r_pte_T_33_x = _r_pte_T_32_x; // @[PTW.scala:670:8, :672:8]
wire _r_pte_T_33_w = _r_pte_T_32_w; // @[PTW.scala:670:8, :672:8]
wire _r_pte_T_33_r = _r_pte_T_32_r; // @[PTW.scala:670:8, :672:8]
wire _r_pte_T_33_v = _r_pte_T_32_v; // @[PTW.scala:670:8, :672:8]
wire [1:0] _count_T_7 = _count_T_6[1:0]; // @[PTW.scala:696:22]
wire _gf_T = ~stage2_final; // @[PTW.scala:283:25, :566:15, :698:27]
wire _gf_T_1 = stage2 & _gf_T; // @[PTW.scala:282:19, :698:{24,27}]
wire _gf_T_2 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26]
wire _gf_T_3 = pte_x & _gf_T_2; // @[PTW.scala:141:{44,47}, :305:26]
wire _gf_T_4 = pte_r | _gf_T_3; // @[PTW.scala:141:{38,44}, :305:26]
wire _gf_T_5 = pte_v & _gf_T_4; // @[PTW.scala:141:{32,38}, :305:26]
wire _gf_T_6 = _gf_T_5 & pte_a; // @[PTW.scala:141:{32,52}, :305:26]
wire _gf_T_7 = _gf_T_6 & pte_r; // @[PTW.scala:141:52, :149:35, :305:26]
wire _gf_T_8 = _gf_T_7 & pte_u; // @[PTW.scala:143:33, :149:35, :305:26]
wire _gf_T_9 = ~_gf_T_8; // @[PTW.scala:143:33, :698:44]
wire _gf_T_10 = _gf_T_1 & _gf_T_9; // @[PTW.scala:698:{24,41,44}]
wire _gf_T_11 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26]
wire _gf_T_12 = pte_x & _gf_T_11; // @[PTW.scala:141:{44,47}, :305:26]
wire _gf_T_13 = pte_r | _gf_T_12; // @[PTW.scala:141:{38,44}, :305:26]
wire _gf_T_14 = pte_v & _gf_T_13; // @[PTW.scala:141:{32,38}, :305:26]
wire _gf_T_15 = _gf_T_14 & pte_a; // @[PTW.scala:141:{32,52}, :305:26]
wire _gf_T_16 = ~(|pte_reserved_for_future); // @[PTW.scala:139:92, :305:26, :698:97]
wire _gf_T_17 = _gf_T_15 & _gf_T_16; // @[PTW.scala:141:52, :698:{70,97}]
wire _gf_T_18 = _gf_T_17 & invalid_gpa; // @[PTW.scala:314:32, :698:{70,105}]
wire gf = _gf_T_10 | _gf_T_18; // @[PTW.scala:698:{41,55,105}]
wire ae = pte_v & invalid_paddr; // @[PTW.scala:305:26, :313:9, :699:22]
wire _pf_T = |pte_reserved_for_future; // @[PTW.scala:139:92, :305:26, :700:49]
wire pf = pte_v & _pf_T; // @[PTW.scala:305:26, :700:{22,49}]
wire _success_T = ~ae; // @[PTW.scala:699:22, :701:30]
wire _success_T_1 = pte_v & _success_T; // @[PTW.scala:305:26, :701:{27,30}]
wire _success_T_2 = ~pf; // @[PTW.scala:700:22, :701:37]
wire _success_T_3 = _success_T_1 & _success_T_2; // @[PTW.scala:701:{27,34,37}]
wire _success_T_4 = ~gf; // @[PTW.scala:698:55, :701:44]
wire success = _success_T_3 & _success_T_4; // @[PTW.scala:701:{34,41,44}]
wire _T_58 = do_both_stages & ~stage2_final & success; // @[PTW.scala:283:25, :288:38, :566:15, :701:41, :703:{28,45}]
assign do_switch = mem_resp_valid & (traverse ? do_both_stages & ~stage2 : _T_58 & ~stage2); // @[PTW.scala:282:19, :288:38, :292:31, :306:38, :317:64, :581:30, :691:25, :694:21, :695:{28,40}, :703:{28,45,57}, :704:23, :709:21]
wire _l2_refill_T_1 = success & _l2_refill_T; // @[PTW.scala:701:41, :713:{30,39}]
wire _l2_refill_T_2 = ~r_req_need_gpa; // @[PTW.scala:270:18, :713:61]
wire _l2_refill_T_3 = _l2_refill_T_1 & _l2_refill_T_2; // @[PTW.scala:713:{30,58,61}]
wire _l2_refill_T_4 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32, :714:12]
wire _l2_refill_T_5 = ~r_req_stage2; // @[PTW.scala:270:18, :714:30]
wire _l2_refill_T_6 = _l2_refill_T_4 & _l2_refill_T_5; // @[PTW.scala:714:{12,27,30}]
wire _l2_refill_T_8 = do_both_stages & _l2_refill_T_7; // @[PTW.scala:288:38, :715:{27,40}]
wire _l2_refill_T_9 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26]
wire _l2_refill_T_10 = pte_x & _l2_refill_T_9; // @[PTW.scala:141:{44,47}, :305:26]
wire _l2_refill_T_11 = pte_r | _l2_refill_T_10; // @[PTW.scala:141:{38,44}, :305:26]
wire _l2_refill_T_12 = pte_v & _l2_refill_T_11; // @[PTW.scala:141:{32,38}, :305:26]
wire _l2_refill_T_13 = _l2_refill_T_12 & pte_a; // @[PTW.scala:141:{32,52}, :305:26]
wire _l2_refill_T_14 = _l2_refill_T_13 & pte_w; // @[PTW.scala:141:52, :151:35, :305:26]
wire _l2_refill_T_15 = _l2_refill_T_14 & pte_d; // @[PTW.scala:151:{35,40}, :305:26]
wire _l2_refill_T_16 = _l2_refill_T_15 & pte_u; // @[PTW.scala:145:33, :151:40, :305:26]
wire _l2_refill_T_17 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26]
wire _l2_refill_T_18 = pte_x & _l2_refill_T_17; // @[PTW.scala:141:{44,47}, :305:26]
wire _l2_refill_T_19 = pte_r | _l2_refill_T_18; // @[PTW.scala:141:{38,44}, :305:26]
wire _l2_refill_T_20 = pte_v & _l2_refill_T_19; // @[PTW.scala:141:{32,38}, :305:26]
wire _l2_refill_T_21 = _l2_refill_T_20 & pte_a; // @[PTW.scala:141:{32,52}, :305:26]
wire _l2_refill_T_22 = _l2_refill_T_21 & pte_x; // @[PTW.scala:141:52, :153:35, :305:26]
wire _l2_refill_T_23 = _l2_refill_T_22 & pte_u; // @[PTW.scala:147:33, :153:35, :305:26]
wire _l2_refill_T_24 = _l2_refill_T_16 & _l2_refill_T_23; // @[PTW.scala:145:33, :147:33, :155:41]
wire _l2_refill_T_25 = _l2_refill_T_8 & _l2_refill_T_24; // @[PTW.scala:155:41, :715:{27,59}]
wire _l2_refill_T_26 = _l2_refill_T_6 | _l2_refill_T_25; // @[PTW.scala:714:{27,44}, :715:59]
wire _l2_refill_T_27 = _l2_refill_T_3 & _l2_refill_T_26; // @[PTW.scala:713:{58,77}, :714:44]
wire _GEN_8 = traverse | _T_58; // @[PTW.scala:317:64, :398:26, :694:21, :703:{28,45,57}, :713:19]
wire _resp_ae_ptw_T = ~(count[1]); // @[PTW.scala:259:18, :310:21, :317:73, :725:36]
wire _resp_ae_ptw_T_1 = ae & _resp_ae_ptw_T; // @[PTW.scala:699:22, :725:{27,36}]
wire _resp_ae_ptw_T_2 = ~pte_r; // @[PTW.scala:139:36, :305:26]
wire _resp_ae_ptw_T_3 = pte_v & _resp_ae_ptw_T_2; // @[PTW.scala:139:{33,36}, :305:26]
wire _resp_ae_ptw_T_4 = ~pte_w; // @[PTW.scala:139:42, :305:26]
wire _resp_ae_ptw_T_5 = _resp_ae_ptw_T_3 & _resp_ae_ptw_T_4; // @[PTW.scala:139:{33,39,42}]
wire _resp_ae_ptw_T_6 = ~pte_x; // @[PTW.scala:139:48, :305:26]
wire _resp_ae_ptw_T_7 = _resp_ae_ptw_T_5 & _resp_ae_ptw_T_6; // @[PTW.scala:139:{39,45,48}]
wire _resp_ae_ptw_T_8 = ~pte_d; // @[PTW.scala:139:54, :305:26]
wire _resp_ae_ptw_T_9 = _resp_ae_ptw_T_7 & _resp_ae_ptw_T_8; // @[PTW.scala:139:{45,51,54}]
wire _resp_ae_ptw_T_10 = ~pte_a; // @[PTW.scala:139:60, :305:26]
wire _resp_ae_ptw_T_11 = _resp_ae_ptw_T_9 & _resp_ae_ptw_T_10; // @[PTW.scala:139:{51,57,60}]
wire _resp_ae_ptw_T_12 = ~pte_u; // @[PTW.scala:139:66, :305:26]
wire _resp_ae_ptw_T_13 = _resp_ae_ptw_T_11 & _resp_ae_ptw_T_12; // @[PTW.scala:139:{57,63,66}]
wire _resp_ae_ptw_T_14 = ~(|pte_reserved_for_future); // @[PTW.scala:139:92, :305:26]
wire _resp_ae_ptw_T_15 = _resp_ae_ptw_T_13 & _resp_ae_ptw_T_14; // @[PTW.scala:139:{63,69,92}]
wire _resp_ae_ptw_T_16 = _resp_ae_ptw_T_1 & _resp_ae_ptw_T_15; // @[PTW.scala:139:69, :725:{27,53}]
wire _resp_ae_final_T = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26]
wire _resp_ae_final_T_1 = pte_x & _resp_ae_final_T; // @[PTW.scala:141:{44,47}, :305:26]
wire _resp_ae_final_T_2 = pte_r | _resp_ae_final_T_1; // @[PTW.scala:141:{38,44}, :305:26]
wire _resp_ae_final_T_3 = pte_v & _resp_ae_final_T_2; // @[PTW.scala:141:{32,38}, :305:26]
wire _resp_ae_final_T_4 = _resp_ae_final_T_3 & pte_a; // @[PTW.scala:141:{32,52}, :305:26]
wire _resp_ae_final_T_5 = ae & _resp_ae_final_T_4; // @[PTW.scala:141:52, :699:22, :726:29]
wire _resp_pf_T = ~stage2; // @[PTW.scala:282:19, :306:38, :727:26]
wire _resp_pf_T_1 = pf & _resp_pf_T; // @[PTW.scala:700:22, :727:{23,26}]
wire _resp_gf_T_3 = pf & stage2; // @[PTW.scala:282:19, :700:22, :728:30]
wire _resp_gf_T_4 = gf | _resp_gf_T_3; // @[PTW.scala:698:55, :728:{23,30}]
wire _resp_hr_T = ~stage2; // @[PTW.scala:282:19, :306:38, :729:20]
wire _resp_hr_T_1 = ~pf; // @[PTW.scala:700:22, :701:37, :729:32]
wire _resp_hr_T_2 = ~gf; // @[PTW.scala:698:55, :701:44, :729:39]
wire _resp_hr_T_3 = _resp_hr_T_1 & _resp_hr_T_2; // @[PTW.scala:729:{32,36,39}]
wire _resp_hr_T_4 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26]
wire _resp_hr_T_5 = pte_x & _resp_hr_T_4; // @[PTW.scala:141:{44,47}, :305:26]
wire _resp_hr_T_6 = pte_r | _resp_hr_T_5; // @[PTW.scala:141:{38,44}, :305:26]
wire _resp_hr_T_7 = pte_v & _resp_hr_T_6; // @[PTW.scala:141:{32,38}, :305:26]
wire _resp_hr_T_8 = _resp_hr_T_7 & pte_a; // @[PTW.scala:141:{32,52}, :305:26]
wire _resp_hr_T_9 = _resp_hr_T_8 & pte_r; // @[PTW.scala:141:52, :149:35, :305:26]
wire _resp_hr_T_10 = _resp_hr_T_9 & pte_u; // @[PTW.scala:143:33, :149:35, :305:26]
wire _resp_hr_T_11 = _resp_hr_T_3 & _resp_hr_T_10; // @[PTW.scala:143:33, :729:{36,43}]
wire _resp_hr_T_12 = _resp_hr_T | _resp_hr_T_11; // @[PTW.scala:729:{20,28,43}]
wire _resp_hw_T = ~stage2; // @[PTW.scala:282:19, :306:38, :730:20]
wire _resp_hw_T_1 = ~pf; // @[PTW.scala:700:22, :701:37, :730:32]
wire _resp_hw_T_2 = ~gf; // @[PTW.scala:698:55, :701:44, :730:39]
wire _resp_hw_T_3 = _resp_hw_T_1 & _resp_hw_T_2; // @[PTW.scala:730:{32,36,39}]
wire _resp_hw_T_4 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26]
wire _resp_hw_T_5 = pte_x & _resp_hw_T_4; // @[PTW.scala:141:{44,47}, :305:26]
wire _resp_hw_T_6 = pte_r | _resp_hw_T_5; // @[PTW.scala:141:{38,44}, :305:26]
wire _resp_hw_T_7 = pte_v & _resp_hw_T_6; // @[PTW.scala:141:{32,38}, :305:26]
wire _resp_hw_T_8 = _resp_hw_T_7 & pte_a; // @[PTW.scala:141:{32,52}, :305:26]
wire _resp_hw_T_9 = _resp_hw_T_8 & pte_w; // @[PTW.scala:141:52, :151:35, :305:26]
wire _resp_hw_T_10 = _resp_hw_T_9 & pte_d; // @[PTW.scala:151:{35,40}, :305:26]
wire _resp_hw_T_11 = _resp_hw_T_10 & pte_u; // @[PTW.scala:145:33, :151:40, :305:26]
wire _resp_hw_T_12 = _resp_hw_T_3 & _resp_hw_T_11; // @[PTW.scala:145:33, :730:{36,43}]
wire _resp_hw_T_13 = _resp_hw_T | _resp_hw_T_12; // @[PTW.scala:730:{20,28,43}]
wire _resp_hx_T = ~stage2; // @[PTW.scala:282:19, :306:38, :731:20]
wire _resp_hx_T_1 = ~pf; // @[PTW.scala:700:22, :701:37, :731:32]
wire _resp_hx_T_2 = ~gf; // @[PTW.scala:698:55, :701:44, :731:39]
wire _resp_hx_T_3 = _resp_hx_T_1 & _resp_hx_T_2; // @[PTW.scala:731:{32,36,39}]
wire _resp_hx_T_4 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26]
wire _resp_hx_T_5 = pte_x & _resp_hx_T_4; // @[PTW.scala:141:{44,47}, :305:26]
wire _resp_hx_T_6 = pte_r | _resp_hx_T_5; // @[PTW.scala:141:{38,44}, :305:26]
wire _resp_hx_T_7 = pte_v & _resp_hx_T_6; // @[PTW.scala:141:{32,38}, :305:26]
wire _resp_hx_T_8 = _resp_hx_T_7 & pte_a; // @[PTW.scala:141:{32,52}, :305:26]
wire _resp_hx_T_9 = _resp_hx_T_8 & pte_x; // @[PTW.scala:141:52, :153:35, :305:26]
wire _resp_hx_T_10 = _resp_hx_T_9 & pte_u; // @[PTW.scala:147:33, :153:35, :305:26]
wire _resp_hx_T_11 = _resp_hx_T_3 & _resp_hx_T_10; // @[PTW.scala:147:33, :731:{36,43}]
wire _resp_hx_T_12 = _resp_hx_T | _resp_hx_T_11; // @[PTW.scala:731:{20,28,43}] |
Generate the Verilog code corresponding to this FIRRTL code module NullPrefetcher_1 :
input clock : Clock
input reset : Reset
output io : { flip mshr_avail : UInt<1>, flip req_val : UInt<1>, flip req_addr : UInt<34>, flip req_coh : { state : UInt<2>}, prefetch : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>}}}
connect io.prefetch.valid, UInt<1>(0h0)
invalidate io.prefetch.bits.is_hella
invalidate io.prefetch.bits.data
invalidate io.prefetch.bits.addr
invalidate io.prefetch.bits.uop.debug_tsrc
invalidate io.prefetch.bits.uop.debug_fsrc
invalidate io.prefetch.bits.uop.bp_xcpt_if
invalidate io.prefetch.bits.uop.bp_debug_if
invalidate io.prefetch.bits.uop.xcpt_ma_if
invalidate io.prefetch.bits.uop.xcpt_ae_if
invalidate io.prefetch.bits.uop.xcpt_pf_if
invalidate io.prefetch.bits.uop.fp_single
invalidate io.prefetch.bits.uop.fp_val
invalidate io.prefetch.bits.uop.frs3_en
invalidate io.prefetch.bits.uop.lrs2_rtype
invalidate io.prefetch.bits.uop.lrs1_rtype
invalidate io.prefetch.bits.uop.dst_rtype
invalidate io.prefetch.bits.uop.ldst_val
invalidate io.prefetch.bits.uop.lrs3
invalidate io.prefetch.bits.uop.lrs2
invalidate io.prefetch.bits.uop.lrs1
invalidate io.prefetch.bits.uop.ldst
invalidate io.prefetch.bits.uop.ldst_is_rs1
invalidate io.prefetch.bits.uop.flush_on_commit
invalidate io.prefetch.bits.uop.is_unique
invalidate io.prefetch.bits.uop.is_sys_pc2epc
invalidate io.prefetch.bits.uop.uses_stq
invalidate io.prefetch.bits.uop.uses_ldq
invalidate io.prefetch.bits.uop.is_amo
invalidate io.prefetch.bits.uop.is_fencei
invalidate io.prefetch.bits.uop.is_fence
invalidate io.prefetch.bits.uop.mem_signed
invalidate io.prefetch.bits.uop.mem_size
invalidate io.prefetch.bits.uop.mem_cmd
invalidate io.prefetch.bits.uop.bypassable
invalidate io.prefetch.bits.uop.exc_cause
invalidate io.prefetch.bits.uop.exception
invalidate io.prefetch.bits.uop.stale_pdst
invalidate io.prefetch.bits.uop.ppred_busy
invalidate io.prefetch.bits.uop.prs3_busy
invalidate io.prefetch.bits.uop.prs2_busy
invalidate io.prefetch.bits.uop.prs1_busy
invalidate io.prefetch.bits.uop.ppred
invalidate io.prefetch.bits.uop.prs3
invalidate io.prefetch.bits.uop.prs2
invalidate io.prefetch.bits.uop.prs1
invalidate io.prefetch.bits.uop.pdst
invalidate io.prefetch.bits.uop.rxq_idx
invalidate io.prefetch.bits.uop.stq_idx
invalidate io.prefetch.bits.uop.ldq_idx
invalidate io.prefetch.bits.uop.rob_idx
invalidate io.prefetch.bits.uop.csr_addr
invalidate io.prefetch.bits.uop.imm_packed
invalidate io.prefetch.bits.uop.taken
invalidate io.prefetch.bits.uop.pc_lob
invalidate io.prefetch.bits.uop.edge_inst
invalidate io.prefetch.bits.uop.ftq_idx
invalidate io.prefetch.bits.uop.br_tag
invalidate io.prefetch.bits.uop.br_mask
invalidate io.prefetch.bits.uop.is_sfb
invalidate io.prefetch.bits.uop.is_jal
invalidate io.prefetch.bits.uop.is_jalr
invalidate io.prefetch.bits.uop.is_br
invalidate io.prefetch.bits.uop.iw_p2_poisoned
invalidate io.prefetch.bits.uop.iw_p1_poisoned
invalidate io.prefetch.bits.uop.iw_state
invalidate io.prefetch.bits.uop.ctrl.is_std
invalidate io.prefetch.bits.uop.ctrl.is_sta
invalidate io.prefetch.bits.uop.ctrl.is_load
invalidate io.prefetch.bits.uop.ctrl.csr_cmd
invalidate io.prefetch.bits.uop.ctrl.fcn_dw
invalidate io.prefetch.bits.uop.ctrl.op_fcn
invalidate io.prefetch.bits.uop.ctrl.imm_sel
invalidate io.prefetch.bits.uop.ctrl.op2_sel
invalidate io.prefetch.bits.uop.ctrl.op1_sel
invalidate io.prefetch.bits.uop.ctrl.br_type
invalidate io.prefetch.bits.uop.fu_code
invalidate io.prefetch.bits.uop.iq_type
invalidate io.prefetch.bits.uop.debug_pc
invalidate io.prefetch.bits.uop.is_rvc
invalidate io.prefetch.bits.uop.debug_inst
invalidate io.prefetch.bits.uop.inst
invalidate io.prefetch.bits.uop.uopc | module NullPrefetcher_1( // @[prefetcher.scala:39:7]
input clock, // @[prefetcher.scala:39:7]
input reset, // @[prefetcher.scala:39:7]
input io_mshr_avail, // @[prefetcher.scala:26:14]
input io_req_val, // @[prefetcher.scala:26:14]
input [33:0] io_req_addr, // @[prefetcher.scala:26:14]
input [1:0] io_req_coh_state, // @[prefetcher.scala:26:14]
input io_prefetch_ready // @[prefetcher.scala:26:14]
);
wire io_mshr_avail_0 = io_mshr_avail; // @[prefetcher.scala:39:7]
wire io_req_val_0 = io_req_val; // @[prefetcher.scala:39:7]
wire [33:0] io_req_addr_0 = io_req_addr; // @[prefetcher.scala:39:7]
wire [1:0] io_req_coh_state_0 = io_req_coh_state; // @[prefetcher.scala:39:7]
wire io_prefetch_ready_0 = io_prefetch_ready; // @[prefetcher.scala:39:7]
wire [63:0] io_prefetch_bits_uop_exc_cause = 64'h0; // @[prefetcher.scala:39:7]
wire [63:0] io_prefetch_bits_data = 64'h0; // @[prefetcher.scala:39:7]
wire [11:0] io_prefetch_bits_uop_csr_addr = 12'h0; // @[prefetcher.scala:39:7]
wire [19:0] io_prefetch_bits_uop_imm_packed = 20'h0; // @[prefetcher.scala:39:7]
wire [5:0] io_prefetch_bits_uop_pc_lob = 6'h0; // @[prefetcher.scala:39:7]
wire [5:0] io_prefetch_bits_uop_rob_idx = 6'h0; // @[prefetcher.scala:39:7]
wire [5:0] io_prefetch_bits_uop_ldst = 6'h0; // @[prefetcher.scala:39:7]
wire [5:0] io_prefetch_bits_uop_lrs1 = 6'h0; // @[prefetcher.scala:39:7]
wire [5:0] io_prefetch_bits_uop_lrs2 = 6'h0; // @[prefetcher.scala:39:7]
wire [5:0] io_prefetch_bits_uop_lrs3 = 6'h0; // @[prefetcher.scala:39:7]
wire [4:0] io_prefetch_bits_uop_ctrl_op_fcn = 5'h0; // @[prefetcher.scala:39:7]
wire [4:0] io_prefetch_bits_uop_mem_cmd = 5'h0; // @[prefetcher.scala:39:7]
wire [1:0] io_prefetch_bits_uop_ctrl_op1_sel = 2'h0; // @[prefetcher.scala:39:7]
wire [1:0] io_prefetch_bits_uop_iw_state = 2'h0; // @[prefetcher.scala:39:7]
wire [1:0] io_prefetch_bits_uop_br_tag = 2'h0; // @[prefetcher.scala:39:7]
wire [1:0] io_prefetch_bits_uop_rxq_idx = 2'h0; // @[prefetcher.scala:39:7]
wire [1:0] io_prefetch_bits_uop_mem_size = 2'h0; // @[prefetcher.scala:39:7]
wire [1:0] io_prefetch_bits_uop_dst_rtype = 2'h0; // @[prefetcher.scala:39:7]
wire [1:0] io_prefetch_bits_uop_lrs1_rtype = 2'h0; // @[prefetcher.scala:39:7]
wire [1:0] io_prefetch_bits_uop_lrs2_rtype = 2'h0; // @[prefetcher.scala:39:7]
wire [1:0] io_prefetch_bits_uop_debug_fsrc = 2'h0; // @[prefetcher.scala:39:7]
wire [1:0] io_prefetch_bits_uop_debug_tsrc = 2'h0; // @[prefetcher.scala:39:7]
wire [3:0] io_prefetch_bits_uop_ctrl_br_type = 4'h0; // @[prefetcher.scala:39:7]
wire [3:0] io_prefetch_bits_uop_br_mask = 4'h0; // @[prefetcher.scala:39:7]
wire [3:0] io_prefetch_bits_uop_ftq_idx = 4'h0; // @[prefetcher.scala:39:7]
wire [3:0] io_prefetch_bits_uop_ldq_idx = 4'h0; // @[prefetcher.scala:39:7]
wire [3:0] io_prefetch_bits_uop_stq_idx = 4'h0; // @[prefetcher.scala:39:7]
wire [3:0] io_prefetch_bits_uop_ppred = 4'h0; // @[prefetcher.scala:39:7]
wire [9:0] io_prefetch_bits_uop_fu_code = 10'h0; // @[prefetcher.scala:39:7]
wire [2:0] io_prefetch_bits_uop_iq_type = 3'h0; // @[prefetcher.scala:39:7]
wire [2:0] io_prefetch_bits_uop_ctrl_op2_sel = 3'h0; // @[prefetcher.scala:39:7]
wire [2:0] io_prefetch_bits_uop_ctrl_imm_sel = 3'h0; // @[prefetcher.scala:39:7]
wire [2:0] io_prefetch_bits_uop_ctrl_csr_cmd = 3'h0; // @[prefetcher.scala:39:7]
wire [33:0] io_prefetch_bits_uop_debug_pc = 34'h0; // @[prefetcher.scala:39:7]
wire [33:0] io_prefetch_bits_addr = 34'h0; // @[prefetcher.scala:39:7]
wire [31:0] io_prefetch_bits_uop_inst = 32'h0; // @[prefetcher.scala:39:7]
wire [31:0] io_prefetch_bits_uop_debug_inst = 32'h0; // @[prefetcher.scala:39:7]
wire [6:0] io_prefetch_bits_uop_uopc = 7'h0; // @[prefetcher.scala:39:7]
wire [6:0] io_prefetch_bits_uop_pdst = 7'h0; // @[prefetcher.scala:39:7]
wire [6:0] io_prefetch_bits_uop_prs1 = 7'h0; // @[prefetcher.scala:39:7]
wire [6:0] io_prefetch_bits_uop_prs2 = 7'h0; // @[prefetcher.scala:39:7]
wire [6:0] io_prefetch_bits_uop_prs3 = 7'h0; // @[prefetcher.scala:39:7]
wire [6:0] io_prefetch_bits_uop_stale_pdst = 7'h0; // @[prefetcher.scala:39:7]
wire io_prefetch_valid = 1'h0; // @[prefetcher.scala:39:7]
wire io_prefetch_bits_uop_is_rvc = 1'h0; // @[prefetcher.scala:39:7]
wire io_prefetch_bits_uop_ctrl_fcn_dw = 1'h0; // @[prefetcher.scala:39:7]
wire io_prefetch_bits_uop_ctrl_is_load = 1'h0; // @[prefetcher.scala:39:7]
wire io_prefetch_bits_uop_ctrl_is_sta = 1'h0; // @[prefetcher.scala:39:7]
wire io_prefetch_bits_uop_ctrl_is_std = 1'h0; // @[prefetcher.scala:39:7]
wire io_prefetch_bits_uop_iw_p1_poisoned = 1'h0; // @[prefetcher.scala:39:7]
wire io_prefetch_bits_uop_iw_p2_poisoned = 1'h0; // @[prefetcher.scala:39:7]
wire io_prefetch_bits_uop_is_br = 1'h0; // @[prefetcher.scala:39:7]
wire io_prefetch_bits_uop_is_jalr = 1'h0; // @[prefetcher.scala:39:7]
wire io_prefetch_bits_uop_is_jal = 1'h0; // @[prefetcher.scala:39:7]
wire io_prefetch_bits_uop_is_sfb = 1'h0; // @[prefetcher.scala:39:7]
wire io_prefetch_bits_uop_edge_inst = 1'h0; // @[prefetcher.scala:39:7]
wire io_prefetch_bits_uop_taken = 1'h0; // @[prefetcher.scala:39:7]
wire io_prefetch_bits_uop_prs1_busy = 1'h0; // @[prefetcher.scala:39:7]
wire io_prefetch_bits_uop_prs2_busy = 1'h0; // @[prefetcher.scala:39:7]
wire io_prefetch_bits_uop_prs3_busy = 1'h0; // @[prefetcher.scala:39:7]
wire io_prefetch_bits_uop_ppred_busy = 1'h0; // @[prefetcher.scala:39:7]
wire io_prefetch_bits_uop_exception = 1'h0; // @[prefetcher.scala:39:7]
wire io_prefetch_bits_uop_bypassable = 1'h0; // @[prefetcher.scala:39:7]
wire io_prefetch_bits_uop_mem_signed = 1'h0; // @[prefetcher.scala:39:7]
wire io_prefetch_bits_uop_is_fence = 1'h0; // @[prefetcher.scala:39:7]
wire io_prefetch_bits_uop_is_fencei = 1'h0; // @[prefetcher.scala:39:7]
wire io_prefetch_bits_uop_is_amo = 1'h0; // @[prefetcher.scala:39:7]
wire io_prefetch_bits_uop_uses_ldq = 1'h0; // @[prefetcher.scala:39:7]
wire io_prefetch_bits_uop_uses_stq = 1'h0; // @[prefetcher.scala:39:7]
wire io_prefetch_bits_uop_is_sys_pc2epc = 1'h0; // @[prefetcher.scala:39:7]
wire io_prefetch_bits_uop_is_unique = 1'h0; // @[prefetcher.scala:39:7]
wire io_prefetch_bits_uop_flush_on_commit = 1'h0; // @[prefetcher.scala:39:7]
wire io_prefetch_bits_uop_ldst_is_rs1 = 1'h0; // @[prefetcher.scala:39:7]
wire io_prefetch_bits_uop_ldst_val = 1'h0; // @[prefetcher.scala:39:7]
wire io_prefetch_bits_uop_frs3_en = 1'h0; // @[prefetcher.scala:39:7]
wire io_prefetch_bits_uop_fp_val = 1'h0; // @[prefetcher.scala:39:7]
wire io_prefetch_bits_uop_fp_single = 1'h0; // @[prefetcher.scala:39:7]
wire io_prefetch_bits_uop_xcpt_pf_if = 1'h0; // @[prefetcher.scala:39:7]
wire io_prefetch_bits_uop_xcpt_ae_if = 1'h0; // @[prefetcher.scala:39:7]
wire io_prefetch_bits_uop_xcpt_ma_if = 1'h0; // @[prefetcher.scala:39:7]
wire io_prefetch_bits_uop_bp_debug_if = 1'h0; // @[prefetcher.scala:39:7]
wire io_prefetch_bits_uop_bp_xcpt_if = 1'h0; // @[prefetcher.scala:39:7]
wire io_prefetch_bits_is_hella = 1'h0; // @[prefetcher.scala:39:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_471 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_471( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFN_e8_s24_76 :
output io : { flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
inst mulAddRecFNToRaw_preMul of MulAddRecFNToRaw_preMul_e8_s24_76
inst mulAddRecFNToRaw_postMul of MulAddRecFNToRaw_postMul_e8_s24_76
connect mulAddRecFNToRaw_preMul.io.op, io.op
connect mulAddRecFNToRaw_preMul.io.a, io.a
connect mulAddRecFNToRaw_preMul.io.b, io.b
connect mulAddRecFNToRaw_preMul.io.c, io.c
node _mulAddResult_T = mul(mulAddRecFNToRaw_preMul.io.mulAddA, mulAddRecFNToRaw_preMul.io.mulAddB)
node mulAddResult = add(_mulAddResult_T, mulAddRecFNToRaw_preMul.io.mulAddC)
connect mulAddRecFNToRaw_postMul.io.fromPreMul.bit0AlignedSigC, mulAddRecFNToRaw_preMul.io.toPostMul.bit0AlignedSigC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.highAlignedSigC, mulAddRecFNToRaw_preMul.io.toPostMul.highAlignedSigC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.CDom_CAlignDist, mulAddRecFNToRaw_preMul.io.toPostMul.CDom_CAlignDist
connect mulAddRecFNToRaw_postMul.io.fromPreMul.CIsDominant, mulAddRecFNToRaw_preMul.io.toPostMul.CIsDominant
connect mulAddRecFNToRaw_postMul.io.fromPreMul.doSubMags, mulAddRecFNToRaw_preMul.io.toPostMul.doSubMags
connect mulAddRecFNToRaw_postMul.io.fromPreMul.sExpSum, mulAddRecFNToRaw_preMul.io.toPostMul.sExpSum
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroC, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfC, mulAddRecFNToRaw_preMul.io.toPostMul.isInfC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNC, mulAddRecFNToRaw_preMul.io.toPostMul.isNaNC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.signProd, mulAddRecFNToRaw_preMul.io.toPostMul.signProd
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroB, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroB
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfB, mulAddRecFNToRaw_preMul.io.toPostMul.isInfB
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroA, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroA
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfA, mulAddRecFNToRaw_preMul.io.toPostMul.isInfA
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNAOrB, mulAddRecFNToRaw_preMul.io.toPostMul.isNaNAOrB
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isSigNaNAny, mulAddRecFNToRaw_preMul.io.toPostMul.isSigNaNAny
connect mulAddRecFNToRaw_postMul.io.mulAddResult, mulAddResult
connect mulAddRecFNToRaw_postMul.io.roundingMode, io.roundingMode
inst roundRawFNToRecFN of RoundRawFNToRecFN_e8_s24_124
connect roundRawFNToRecFN.io.invalidExc, mulAddRecFNToRaw_postMul.io.invalidExc
connect roundRawFNToRecFN.io.infiniteExc, UInt<1>(0h0)
connect roundRawFNToRecFN.io.in.sig, mulAddRecFNToRaw_postMul.io.rawOut.sig
connect roundRawFNToRecFN.io.in.sExp, mulAddRecFNToRaw_postMul.io.rawOut.sExp
connect roundRawFNToRecFN.io.in.sign, mulAddRecFNToRaw_postMul.io.rawOut.sign
connect roundRawFNToRecFN.io.in.isZero, mulAddRecFNToRaw_postMul.io.rawOut.isZero
connect roundRawFNToRecFN.io.in.isInf, mulAddRecFNToRaw_postMul.io.rawOut.isInf
connect roundRawFNToRecFN.io.in.isNaN, mulAddRecFNToRaw_postMul.io.rawOut.isNaN
connect roundRawFNToRecFN.io.roundingMode, io.roundingMode
connect roundRawFNToRecFN.io.detectTininess, io.detectTininess
connect io.out, roundRawFNToRecFN.io.out
connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags | module MulAddRecFN_e8_s24_76( // @[MulAddRecFN.scala:300:7]
input [32:0] io_a, // @[MulAddRecFN.scala:303:16]
input [32:0] io_b, // @[MulAddRecFN.scala:303:16]
input [32:0] io_c, // @[MulAddRecFN.scala:303:16]
output [32:0] io_out // @[MulAddRecFN.scala:303:16]
);
wire _mulAddRecFNToRaw_postMul_io_invalidExc; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[MulAddRecFN.scala:319:15]
wire [9:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[MulAddRecFN.scala:319:15]
wire [26:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[MulAddRecFN.scala:319:15]
wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddA; // @[MulAddRecFN.scala:317:15]
wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddB; // @[MulAddRecFN.scala:317:15]
wire [47:0] _mulAddRecFNToRaw_preMul_io_mulAddC; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; // @[MulAddRecFN.scala:317:15]
wire [9:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; // @[MulAddRecFN.scala:317:15]
wire [4:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[MulAddRecFN.scala:317:15]
wire [25:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[MulAddRecFN.scala:317:15]
wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:300:7]
wire [32:0] io_b_0 = io_b; // @[MulAddRecFN.scala:300:7]
wire [32:0] io_c_0 = io_c; // @[MulAddRecFN.scala:300:7]
wire io_detectTininess = 1'h1; // @[MulAddRecFN.scala:300:7, :303:16, :339:15]
wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:300:7, :303:16, :319:15, :339:15]
wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:300:7, :303:16, :317:15]
wire [32:0] io_out_0; // @[MulAddRecFN.scala:300:7]
wire [4:0] io_exceptionFlags; // @[MulAddRecFN.scala:300:7]
wire [47:0] _mulAddResult_T = {24'h0, _mulAddRecFNToRaw_preMul_io_mulAddA} * {24'h0, _mulAddRecFNToRaw_preMul_io_mulAddB}; // @[MulAddRecFN.scala:317:15, :327:45]
wire [48:0] mulAddResult = {1'h0, _mulAddResult_T} + {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC}; // @[MulAddRecFN.scala:317:15, :327:45, :328:50]
MulAddRecFNToRaw_preMul_e8_s24_76 mulAddRecFNToRaw_preMul ( // @[MulAddRecFN.scala:317:15]
.io_a (io_a_0), // @[MulAddRecFN.scala:300:7]
.io_b (io_b_0), // @[MulAddRecFN.scala:300:7]
.io_c (io_c_0), // @[MulAddRecFN.scala:300:7]
.io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA),
.io_mulAddB (_mulAddRecFNToRaw_preMul_io_mulAddB),
.io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC),
.io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny),
.io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB),
.io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA),
.io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA),
.io_toPostMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB),
.io_toPostMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB),
.io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd),
.io_toPostMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC),
.io_toPostMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC),
.io_toPostMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC),
.io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum),
.io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags),
.io_toPostMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant),
.io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist),
.io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC),
.io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC)
); // @[MulAddRecFN.scala:317:15]
MulAddRecFNToRaw_postMul_e8_s24_76 mulAddRecFNToRaw_postMul ( // @[MulAddRecFN.scala:319:15]
.io_fromPreMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC), // @[MulAddRecFN.scala:317:15]
.io_mulAddResult (mulAddResult), // @[MulAddRecFN.scala:328:50]
.io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc),
.io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN),
.io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf),
.io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero),
.io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign),
.io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp),
.io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig)
); // @[MulAddRecFN.scala:319:15]
RoundRawFNToRecFN_e8_s24_124 roundRawFNToRecFN ( // @[MulAddRecFN.scala:339:15]
.io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), // @[MulAddRecFN.scala:319:15]
.io_in_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), // @[MulAddRecFN.scala:319:15]
.io_in_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), // @[MulAddRecFN.scala:319:15]
.io_in_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), // @[MulAddRecFN.scala:319:15]
.io_in_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), // @[MulAddRecFN.scala:319:15]
.io_in_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), // @[MulAddRecFN.scala:319:15]
.io_in_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig), // @[MulAddRecFN.scala:319:15]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags)
); // @[MulAddRecFN.scala:339:15]
assign io_out = io_out_0; // @[MulAddRecFN.scala:300:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module Tile_75 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>}
inst tile_0_0 of PE_331
connect tile_0_0.clock, clock
connect tile_0_0.reset, reset
connect tile_0_0.io.in_a, io.in_a[0]
connect tile_0_0.io.in_b, io.in_b[0]
connect tile_0_0.io.in_d, io.in_d[0]
connect tile_0_0.io.in_control.shift, io.in_control[0].shift
connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate
connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow
connect tile_0_0.io.in_valid, io.in_valid[0]
connect tile_0_0.io.in_id, io.in_id[0]
connect tile_0_0.io.in_last, io.in_last[0]
connect io.out_c[0], tile_0_0.io.out_c
connect io.out_control[0], tile_0_0.io.out_control
connect io.out_id[0], tile_0_0.io.out_id
connect io.out_last[0], tile_0_0.io.out_last
connect io.out_valid[0], tile_0_0.io.out_valid
connect io.out_b[0], tile_0_0.io.out_b
connect io.bad_dataflow, tile_0_0.io.bad_dataflow
connect io.out_a[0], tile_0_0.io.out_a | module Tile_75( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0, // @[Tile.scala:17:14]
output io_bad_dataflow // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
wire io_bad_dataflow_0; // @[Tile.scala:16:7]
PE_331 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0),
.io_bad_dataflow (io_bad_dataflow_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLDebugModuleInnerAsync :
output auto : { flip dmiXing_in : { a : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip b : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, c : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip d : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, e : { mem : { sink : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}}, dmInner_sb2tlOpt_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}}, flip dmInner_custom_in : { flip addr : UInt<1>, data : UInt<0>, ready : UInt<1>, flip valid : UInt<1>}, flip dmInner_tl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
output io : { flip debug_clock : Clock, flip debug_reset : Reset, flip tl_clock : Clock, flip tl_reset : Reset, flip dmactive : UInt<1>, flip innerCtrl : { mem : { resumereq : UInt<1>, hartsel : UInt<10>, ackhavereset : UInt<1>, hasel : UInt<1>, hamask : UInt<1>[1], hrmask : UInt<1>[1]}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip debugUnavail : UInt<1>[1], hgDebugInt : UInt<1>[1], flip hartIsInReset : UInt<1>[1]}
input rf_reset : Reset
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
inst dmInner of TLDebugModuleInner
connect dmInner.clock, childClock
connect dmInner.reset, childReset
inst dmiXing of TLAsyncCrossingSink_a9d32s1k1z2u
connect dmiXing.clock, childClock
connect dmiXing.reset, childReset
connect dmInner.auto.dmi_in, dmiXing.auto.out
connect dmInner.auto.tl_in, auto.dmInner_tl_in
connect dmInner.auto.custom_in, auto.dmInner_custom_in
connect dmInner.auto.sb2tlOpt_out.d, auto.dmInner_sb2tlOpt_out.d
connect auto.dmInner_sb2tlOpt_out.a.bits, dmInner.auto.sb2tlOpt_out.a.bits
connect auto.dmInner_sb2tlOpt_out.a.valid, dmInner.auto.sb2tlOpt_out.a.valid
connect dmInner.auto.sb2tlOpt_out.a.ready, auto.dmInner_sb2tlOpt_out.a.ready
connect dmiXing.auto.in, auto.dmiXing_in
connect childClock, io.debug_clock
connect childReset, io.debug_reset
inst dmactive_synced_dmactive_synced_dmactiveSync of AsyncResetSynchronizerShiftReg_w1_d3_i0_27
connect dmactive_synced_dmactive_synced_dmactiveSync.clock, childClock
connect dmactive_synced_dmactive_synced_dmactiveSync.reset, childReset
connect dmactive_synced_dmactive_synced_dmactiveSync.io.d, io.dmactive
wire dmactive_synced : UInt<1>
connect dmactive_synced, dmactive_synced_dmactive_synced_dmactiveSync.io.q
connect dmInner.clock, io.debug_clock
connect dmInner.reset, io.debug_reset
connect dmInner.io.tl_clock, io.tl_clock
connect dmInner.io.tl_reset, io.tl_reset
connect dmInner.io.dmactive, dmactive_synced
inst dmactive_synced_dmInner_io_innerCtrl_sink of AsyncQueueSink_DebugInternalBundle
connect dmactive_synced_dmInner_io_innerCtrl_sink.clock, childClock
connect dmactive_synced_dmInner_io_innerCtrl_sink.reset, childReset
connect dmactive_synced_dmInner_io_innerCtrl_sink.io.async, io.innerCtrl
connect dmInner.io.innerCtrl, dmactive_synced_dmInner_io_innerCtrl_sink.io.deq
connect dmInner.io.debugUnavail[0], io.debugUnavail[0]
connect io.hgDebugInt, dmInner.io.hgDebugInt
connect dmInner.io.hartIsInReset[0], io.hartIsInReset[0] | module TLDebugModuleInnerAsync( // @[Debug.scala:1871:9]
input [2:0] auto_dmiXing_in_a_mem_0_opcode, // @[LazyModuleImp.scala:107:25]
input [8:0] auto_dmiXing_in_a_mem_0_address, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_dmiXing_in_a_mem_0_data, // @[LazyModuleImp.scala:107:25]
output auto_dmiXing_in_a_ridx, // @[LazyModuleImp.scala:107:25]
input auto_dmiXing_in_a_widx, // @[LazyModuleImp.scala:107:25]
output auto_dmiXing_in_a_safe_ridx_valid, // @[LazyModuleImp.scala:107:25]
input auto_dmiXing_in_a_safe_widx_valid, // @[LazyModuleImp.scala:107:25]
input auto_dmiXing_in_a_safe_source_reset_n, // @[LazyModuleImp.scala:107:25]
output auto_dmiXing_in_a_safe_sink_reset_n, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_dmiXing_in_d_mem_0_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_dmiXing_in_d_mem_0_size, // @[LazyModuleImp.scala:107:25]
output auto_dmiXing_in_d_mem_0_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_dmiXing_in_d_mem_0_data, // @[LazyModuleImp.scala:107:25]
input auto_dmiXing_in_d_ridx, // @[LazyModuleImp.scala:107:25]
output auto_dmiXing_in_d_widx, // @[LazyModuleImp.scala:107:25]
input auto_dmiXing_in_d_safe_ridx_valid, // @[LazyModuleImp.scala:107:25]
output auto_dmiXing_in_d_safe_widx_valid, // @[LazyModuleImp.scala:107:25]
output auto_dmiXing_in_d_safe_source_reset_n, // @[LazyModuleImp.scala:107:25]
input auto_dmiXing_in_d_safe_sink_reset_n, // @[LazyModuleImp.scala:107:25]
input auto_dmInner_sb2tlOpt_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_dmInner_sb2tlOpt_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_dmInner_sb2tlOpt_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_dmInner_sb2tlOpt_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_dmInner_sb2tlOpt_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_dmInner_sb2tlOpt_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_dmInner_sb2tlOpt_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_dmInner_sb2tlOpt_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dmInner_sb2tlOpt_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dmInner_sb2tlOpt_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_dmInner_sb2tlOpt_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input auto_dmInner_sb2tlOpt_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_dmInner_sb2tlOpt_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_dmInner_sb2tlOpt_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_dmInner_sb2tlOpt_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_dmInner_tl_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_dmInner_tl_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dmInner_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dmInner_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dmInner_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [10:0] auto_dmInner_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [11:0] auto_dmInner_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_dmInner_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_dmInner_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_dmInner_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_dmInner_tl_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_dmInner_tl_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_dmInner_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_dmInner_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [10:0] auto_dmInner_tl_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_dmInner_tl_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
input io_debug_clock, // @[Debug.scala:1877:16]
input io_debug_reset, // @[Debug.scala:1877:16]
input io_tl_clock, // @[Debug.scala:1877:16]
input io_tl_reset, // @[Debug.scala:1877:16]
input io_dmactive, // @[Debug.scala:1877:16]
input io_innerCtrl_mem_0_resumereq, // @[Debug.scala:1877:16]
input [9:0] io_innerCtrl_mem_0_hartsel, // @[Debug.scala:1877:16]
input io_innerCtrl_mem_0_ackhavereset, // @[Debug.scala:1877:16]
input io_innerCtrl_mem_0_hrmask_0, // @[Debug.scala:1877:16]
output io_innerCtrl_ridx, // @[Debug.scala:1877:16]
input io_innerCtrl_widx, // @[Debug.scala:1877:16]
output io_innerCtrl_safe_ridx_valid, // @[Debug.scala:1877:16]
input io_innerCtrl_safe_widx_valid, // @[Debug.scala:1877:16]
input io_innerCtrl_safe_source_reset_n, // @[Debug.scala:1877:16]
output io_innerCtrl_safe_sink_reset_n, // @[Debug.scala:1877:16]
output io_hgDebugInt_0, // @[Debug.scala:1877:16]
input io_hartIsInReset_0, // @[Debug.scala:1877:16]
input rf_reset // @[Debug.scala:1904:22]
);
wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_valid; // @[AsyncQueue.scala:211:22]
wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_resumereq; // @[AsyncQueue.scala:211:22]
wire [9:0] _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hartsel; // @[AsyncQueue.scala:211:22]
wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_ackhavereset; // @[AsyncQueue.scala:211:22]
wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hasel; // @[AsyncQueue.scala:211:22]
wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_0; // @[AsyncQueue.scala:211:22]
wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_0; // @[AsyncQueue.scala:211:22]
wire _dmiXing_auto_out_a_valid; // @[Debug.scala:1858:27]
wire [2:0] _dmiXing_auto_out_a_bits_opcode; // @[Debug.scala:1858:27]
wire [2:0] _dmiXing_auto_out_a_bits_param; // @[Debug.scala:1858:27]
wire [1:0] _dmiXing_auto_out_a_bits_size; // @[Debug.scala:1858:27]
wire _dmiXing_auto_out_a_bits_source; // @[Debug.scala:1858:27]
wire [8:0] _dmiXing_auto_out_a_bits_address; // @[Debug.scala:1858:27]
wire [3:0] _dmiXing_auto_out_a_bits_mask; // @[Debug.scala:1858:27]
wire [31:0] _dmiXing_auto_out_a_bits_data; // @[Debug.scala:1858:27]
wire _dmiXing_auto_out_a_bits_corrupt; // @[Debug.scala:1858:27]
wire _dmiXing_auto_out_d_ready; // @[Debug.scala:1858:27]
wire _dmInner_auto_dmi_in_a_ready; // @[Debug.scala:1857:27]
wire _dmInner_auto_dmi_in_d_valid; // @[Debug.scala:1857:27]
wire [2:0] _dmInner_auto_dmi_in_d_bits_opcode; // @[Debug.scala:1857:27]
wire [1:0] _dmInner_auto_dmi_in_d_bits_size; // @[Debug.scala:1857:27]
wire _dmInner_auto_dmi_in_d_bits_source; // @[Debug.scala:1857:27]
wire [31:0] _dmInner_auto_dmi_in_d_bits_data; // @[Debug.scala:1857:27]
wire [2:0] auto_dmiXing_in_a_mem_0_opcode_0 = auto_dmiXing_in_a_mem_0_opcode; // @[Debug.scala:1871:9]
wire [8:0] auto_dmiXing_in_a_mem_0_address_0 = auto_dmiXing_in_a_mem_0_address; // @[Debug.scala:1871:9]
wire [31:0] auto_dmiXing_in_a_mem_0_data_0 = auto_dmiXing_in_a_mem_0_data; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_a_widx_0 = auto_dmiXing_in_a_widx; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_a_safe_widx_valid_0 = auto_dmiXing_in_a_safe_widx_valid; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_a_safe_source_reset_n_0 = auto_dmiXing_in_a_safe_source_reset_n; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_d_ridx_0 = auto_dmiXing_in_d_ridx; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_d_safe_ridx_valid_0 = auto_dmiXing_in_d_safe_ridx_valid; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_d_safe_sink_reset_n_0 = auto_dmiXing_in_d_safe_sink_reset_n; // @[Debug.scala:1871:9]
wire auto_dmInner_sb2tlOpt_out_a_ready_0 = auto_dmInner_sb2tlOpt_out_a_ready; // @[Debug.scala:1871:9]
wire auto_dmInner_sb2tlOpt_out_d_valid_0 = auto_dmInner_sb2tlOpt_out_d_valid; // @[Debug.scala:1871:9]
wire [2:0] auto_dmInner_sb2tlOpt_out_d_bits_opcode_0 = auto_dmInner_sb2tlOpt_out_d_bits_opcode; // @[Debug.scala:1871:9]
wire [1:0] auto_dmInner_sb2tlOpt_out_d_bits_param_0 = auto_dmInner_sb2tlOpt_out_d_bits_param; // @[Debug.scala:1871:9]
wire [3:0] auto_dmInner_sb2tlOpt_out_d_bits_size_0 = auto_dmInner_sb2tlOpt_out_d_bits_size; // @[Debug.scala:1871:9]
wire auto_dmInner_sb2tlOpt_out_d_bits_sink_0 = auto_dmInner_sb2tlOpt_out_d_bits_sink; // @[Debug.scala:1871:9]
wire auto_dmInner_sb2tlOpt_out_d_bits_denied_0 = auto_dmInner_sb2tlOpt_out_d_bits_denied; // @[Debug.scala:1871:9]
wire [7:0] auto_dmInner_sb2tlOpt_out_d_bits_data_0 = auto_dmInner_sb2tlOpt_out_d_bits_data; // @[Debug.scala:1871:9]
wire auto_dmInner_sb2tlOpt_out_d_bits_corrupt_0 = auto_dmInner_sb2tlOpt_out_d_bits_corrupt; // @[Debug.scala:1871:9]
wire auto_dmInner_tl_in_a_valid_0 = auto_dmInner_tl_in_a_valid; // @[Debug.scala:1871:9]
wire [2:0] auto_dmInner_tl_in_a_bits_opcode_0 = auto_dmInner_tl_in_a_bits_opcode; // @[Debug.scala:1871:9]
wire [2:0] auto_dmInner_tl_in_a_bits_param_0 = auto_dmInner_tl_in_a_bits_param; // @[Debug.scala:1871:9]
wire [1:0] auto_dmInner_tl_in_a_bits_size_0 = auto_dmInner_tl_in_a_bits_size; // @[Debug.scala:1871:9]
wire [10:0] auto_dmInner_tl_in_a_bits_source_0 = auto_dmInner_tl_in_a_bits_source; // @[Debug.scala:1871:9]
wire [11:0] auto_dmInner_tl_in_a_bits_address_0 = auto_dmInner_tl_in_a_bits_address; // @[Debug.scala:1871:9]
wire [7:0] auto_dmInner_tl_in_a_bits_mask_0 = auto_dmInner_tl_in_a_bits_mask; // @[Debug.scala:1871:9]
wire [63:0] auto_dmInner_tl_in_a_bits_data_0 = auto_dmInner_tl_in_a_bits_data; // @[Debug.scala:1871:9]
wire auto_dmInner_tl_in_a_bits_corrupt_0 = auto_dmInner_tl_in_a_bits_corrupt; // @[Debug.scala:1871:9]
wire auto_dmInner_tl_in_d_ready_0 = auto_dmInner_tl_in_d_ready; // @[Debug.scala:1871:9]
wire io_debug_clock_0 = io_debug_clock; // @[Debug.scala:1871:9]
wire io_debug_reset_0 = io_debug_reset; // @[Debug.scala:1871:9]
wire io_tl_clock_0 = io_tl_clock; // @[Debug.scala:1871:9]
wire io_tl_reset_0 = io_tl_reset; // @[Debug.scala:1871:9]
wire io_dmactive_0 = io_dmactive; // @[Debug.scala:1871:9]
wire io_innerCtrl_mem_0_resumereq_0 = io_innerCtrl_mem_0_resumereq; // @[Debug.scala:1871:9]
wire [9:0] io_innerCtrl_mem_0_hartsel_0 = io_innerCtrl_mem_0_hartsel; // @[Debug.scala:1871:9]
wire io_innerCtrl_mem_0_ackhavereset_0 = io_innerCtrl_mem_0_ackhavereset; // @[Debug.scala:1871:9]
wire io_innerCtrl_mem_0_hrmask_0_0 = io_innerCtrl_mem_0_hrmask_0; // @[Debug.scala:1871:9]
wire io_innerCtrl_widx_0 = io_innerCtrl_widx; // @[Debug.scala:1871:9]
wire io_innerCtrl_safe_widx_valid_0 = io_innerCtrl_safe_widx_valid; // @[Debug.scala:1871:9]
wire io_innerCtrl_safe_source_reset_n_0 = io_innerCtrl_safe_source_reset_n; // @[Debug.scala:1871:9]
wire io_hartIsInReset_0_0 = io_hartIsInReset_0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_a_mem_0_source = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_a_mem_0_corrupt = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_b_mem_0_source = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_b_mem_0_corrupt = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_b_ridx = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_b_widx = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_b_safe_ridx_valid = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_b_safe_widx_valid = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_b_safe_source_reset_n = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_b_safe_sink_reset_n = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_c_mem_0_source = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_c_mem_0_corrupt = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_c_ridx = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_c_widx = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_c_safe_ridx_valid = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_c_safe_widx_valid = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_c_safe_source_reset_n = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_c_safe_sink_reset_n = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_d_mem_0_sink = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_d_mem_0_denied = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_d_mem_0_corrupt = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_e_mem_0_sink = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_e_ridx = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_e_widx = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_e_safe_ridx_valid = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_e_safe_widx_valid = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_e_safe_source_reset_n = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_e_safe_sink_reset_n = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmInner_sb2tlOpt_out_a_bits_source = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmInner_sb2tlOpt_out_a_bits_corrupt = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmInner_sb2tlOpt_out_d_bits_source = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmInner_custom_in_addr = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmInner_custom_in_ready = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmInner_custom_in_valid = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmInner_tl_in_d_bits_sink = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmInner_tl_in_d_bits_denied = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmInner_tl_in_d_bits_corrupt = 1'h0; // @[Debug.scala:1871:9]
wire io_innerCtrl_mem_0_hasel = 1'h0; // @[Debug.scala:1871:9]
wire io_innerCtrl_mem_0_hamask_0 = 1'h0; // @[Debug.scala:1871:9]
wire io_debugUnavail_0 = 1'h0; // @[Debug.scala:1871:9]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire auto_dmInner_sb2tlOpt_out_a_bits_mask = 1'h1; // @[AsyncQueue.scala:211:22]
wire [31:0] auto_dmiXing_in_b_mem_0_data = 32'h0; // @[Debug.scala:1858:27, :1871:9]
wire [31:0] auto_dmiXing_in_c_mem_0_data = 32'h0; // @[Debug.scala:1858:27, :1871:9]
wire [3:0] auto_dmiXing_in_b_mem_0_mask = 4'h0; // @[Debug.scala:1858:27, :1871:9]
wire [8:0] auto_dmiXing_in_b_mem_0_address = 9'h0; // @[Debug.scala:1858:27, :1871:9]
wire [8:0] auto_dmiXing_in_c_mem_0_address = 9'h0; // @[Debug.scala:1858:27, :1871:9]
wire [1:0] auto_dmiXing_in_b_mem_0_param = 2'h0; // @[Debug.scala:1871:9]
wire [1:0] auto_dmiXing_in_b_mem_0_size = 2'h0; // @[Debug.scala:1871:9]
wire [1:0] auto_dmiXing_in_c_mem_0_size = 2'h0; // @[Debug.scala:1871:9]
wire [1:0] auto_dmiXing_in_d_mem_0_param = 2'h0; // @[Debug.scala:1871:9]
wire [1:0] auto_dmInner_tl_in_d_bits_param = 2'h0; // @[Debug.scala:1871:9]
wire [3:0] auto_dmiXing_in_a_mem_0_mask = 4'hF; // @[Debug.scala:1858:27, :1871:9]
wire [1:0] auto_dmiXing_in_a_mem_0_size = 2'h2; // @[Debug.scala:1858:27, :1871:9]
wire [2:0] auto_dmiXing_in_a_mem_0_param = 3'h0; // @[Debug.scala:1871:9]
wire [2:0] auto_dmiXing_in_b_mem_0_opcode = 3'h0; // @[Debug.scala:1871:9]
wire [2:0] auto_dmiXing_in_c_mem_0_opcode = 3'h0; // @[Debug.scala:1871:9]
wire [2:0] auto_dmiXing_in_c_mem_0_param = 3'h0; // @[Debug.scala:1871:9]
wire [2:0] auto_dmInner_sb2tlOpt_out_a_bits_param = 3'h0; // @[Debug.scala:1871:9]
wire childClock = io_debug_clock_0; // @[Debug.scala:1871:9]
wire childReset = io_debug_reset_0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_a_safe_ridx_valid_0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_a_safe_sink_reset_n_0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_a_ridx_0; // @[Debug.scala:1871:9]
wire [2:0] auto_dmiXing_in_d_mem_0_opcode_0; // @[Debug.scala:1871:9]
wire [1:0] auto_dmiXing_in_d_mem_0_size_0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_d_mem_0_source_0; // @[Debug.scala:1871:9]
wire [31:0] auto_dmiXing_in_d_mem_0_data_0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_d_safe_widx_valid_0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_d_safe_source_reset_n_0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_d_widx_0; // @[Debug.scala:1871:9]
wire [2:0] auto_dmInner_sb2tlOpt_out_a_bits_opcode_0; // @[Debug.scala:1871:9]
wire [3:0] auto_dmInner_sb2tlOpt_out_a_bits_size_0; // @[Debug.scala:1871:9]
wire [31:0] auto_dmInner_sb2tlOpt_out_a_bits_address_0; // @[Debug.scala:1871:9]
wire [7:0] auto_dmInner_sb2tlOpt_out_a_bits_data_0; // @[Debug.scala:1871:9]
wire auto_dmInner_sb2tlOpt_out_a_valid_0; // @[Debug.scala:1871:9]
wire auto_dmInner_sb2tlOpt_out_d_ready_0; // @[Debug.scala:1871:9]
wire auto_dmInner_tl_in_a_ready_0; // @[Debug.scala:1871:9]
wire [2:0] auto_dmInner_tl_in_d_bits_opcode_0; // @[Debug.scala:1871:9]
wire [1:0] auto_dmInner_tl_in_d_bits_size_0; // @[Debug.scala:1871:9]
wire [10:0] auto_dmInner_tl_in_d_bits_source_0; // @[Debug.scala:1871:9]
wire [63:0] auto_dmInner_tl_in_d_bits_data_0; // @[Debug.scala:1871:9]
wire auto_dmInner_tl_in_d_valid_0; // @[Debug.scala:1871:9]
wire io_innerCtrl_safe_ridx_valid_0; // @[Debug.scala:1871:9]
wire io_innerCtrl_safe_sink_reset_n_0; // @[Debug.scala:1871:9]
wire io_innerCtrl_ridx_0; // @[Debug.scala:1871:9]
wire io_hgDebugInt_0_0; // @[Debug.scala:1871:9]
wire dmactive_synced; // @[ShiftReg.scala:48:24]
TLDebugModuleInner dmInner ( // @[Debug.scala:1857:27]
.clock (io_debug_clock_0), // @[Debug.scala:1871:9]
.reset (io_debug_reset_0), // @[Debug.scala:1871:9]
.auto_sb2tlOpt_out_a_ready (auto_dmInner_sb2tlOpt_out_a_ready_0), // @[Debug.scala:1871:9]
.auto_sb2tlOpt_out_a_valid (auto_dmInner_sb2tlOpt_out_a_valid_0),
.auto_sb2tlOpt_out_a_bits_opcode (auto_dmInner_sb2tlOpt_out_a_bits_opcode_0),
.auto_sb2tlOpt_out_a_bits_size (auto_dmInner_sb2tlOpt_out_a_bits_size_0),
.auto_sb2tlOpt_out_a_bits_address (auto_dmInner_sb2tlOpt_out_a_bits_address_0),
.auto_sb2tlOpt_out_a_bits_data (auto_dmInner_sb2tlOpt_out_a_bits_data_0),
.auto_sb2tlOpt_out_d_ready (auto_dmInner_sb2tlOpt_out_d_ready_0),
.auto_sb2tlOpt_out_d_valid (auto_dmInner_sb2tlOpt_out_d_valid_0), // @[Debug.scala:1871:9]
.auto_sb2tlOpt_out_d_bits_opcode (auto_dmInner_sb2tlOpt_out_d_bits_opcode_0), // @[Debug.scala:1871:9]
.auto_sb2tlOpt_out_d_bits_param (auto_dmInner_sb2tlOpt_out_d_bits_param_0), // @[Debug.scala:1871:9]
.auto_sb2tlOpt_out_d_bits_size (auto_dmInner_sb2tlOpt_out_d_bits_size_0), // @[Debug.scala:1871:9]
.auto_sb2tlOpt_out_d_bits_sink (auto_dmInner_sb2tlOpt_out_d_bits_sink_0), // @[Debug.scala:1871:9]
.auto_sb2tlOpt_out_d_bits_denied (auto_dmInner_sb2tlOpt_out_d_bits_denied_0), // @[Debug.scala:1871:9]
.auto_sb2tlOpt_out_d_bits_data (auto_dmInner_sb2tlOpt_out_d_bits_data_0), // @[Debug.scala:1871:9]
.auto_sb2tlOpt_out_d_bits_corrupt (auto_dmInner_sb2tlOpt_out_d_bits_corrupt_0), // @[Debug.scala:1871:9]
.auto_tl_in_a_ready (auto_dmInner_tl_in_a_ready_0),
.auto_tl_in_a_valid (auto_dmInner_tl_in_a_valid_0), // @[Debug.scala:1871:9]
.auto_tl_in_a_bits_opcode (auto_dmInner_tl_in_a_bits_opcode_0), // @[Debug.scala:1871:9]
.auto_tl_in_a_bits_param (auto_dmInner_tl_in_a_bits_param_0), // @[Debug.scala:1871:9]
.auto_tl_in_a_bits_size (auto_dmInner_tl_in_a_bits_size_0), // @[Debug.scala:1871:9]
.auto_tl_in_a_bits_source (auto_dmInner_tl_in_a_bits_source_0), // @[Debug.scala:1871:9]
.auto_tl_in_a_bits_address (auto_dmInner_tl_in_a_bits_address_0), // @[Debug.scala:1871:9]
.auto_tl_in_a_bits_mask (auto_dmInner_tl_in_a_bits_mask_0), // @[Debug.scala:1871:9]
.auto_tl_in_a_bits_data (auto_dmInner_tl_in_a_bits_data_0), // @[Debug.scala:1871:9]
.auto_tl_in_a_bits_corrupt (auto_dmInner_tl_in_a_bits_corrupt_0), // @[Debug.scala:1871:9]
.auto_tl_in_d_ready (auto_dmInner_tl_in_d_ready_0), // @[Debug.scala:1871:9]
.auto_tl_in_d_valid (auto_dmInner_tl_in_d_valid_0),
.auto_tl_in_d_bits_opcode (auto_dmInner_tl_in_d_bits_opcode_0),
.auto_tl_in_d_bits_size (auto_dmInner_tl_in_d_bits_size_0),
.auto_tl_in_d_bits_source (auto_dmInner_tl_in_d_bits_source_0),
.auto_tl_in_d_bits_data (auto_dmInner_tl_in_d_bits_data_0),
.auto_dmi_in_a_ready (_dmInner_auto_dmi_in_a_ready),
.auto_dmi_in_a_valid (_dmiXing_auto_out_a_valid), // @[Debug.scala:1858:27]
.auto_dmi_in_a_bits_opcode (_dmiXing_auto_out_a_bits_opcode), // @[Debug.scala:1858:27]
.auto_dmi_in_a_bits_param (_dmiXing_auto_out_a_bits_param), // @[Debug.scala:1858:27]
.auto_dmi_in_a_bits_size (_dmiXing_auto_out_a_bits_size), // @[Debug.scala:1858:27]
.auto_dmi_in_a_bits_source (_dmiXing_auto_out_a_bits_source), // @[Debug.scala:1858:27]
.auto_dmi_in_a_bits_address (_dmiXing_auto_out_a_bits_address), // @[Debug.scala:1858:27]
.auto_dmi_in_a_bits_mask (_dmiXing_auto_out_a_bits_mask), // @[Debug.scala:1858:27]
.auto_dmi_in_a_bits_data (_dmiXing_auto_out_a_bits_data), // @[Debug.scala:1858:27]
.auto_dmi_in_a_bits_corrupt (_dmiXing_auto_out_a_bits_corrupt), // @[Debug.scala:1858:27]
.auto_dmi_in_d_ready (_dmiXing_auto_out_d_ready), // @[Debug.scala:1858:27]
.auto_dmi_in_d_valid (_dmInner_auto_dmi_in_d_valid),
.auto_dmi_in_d_bits_opcode (_dmInner_auto_dmi_in_d_bits_opcode),
.auto_dmi_in_d_bits_size (_dmInner_auto_dmi_in_d_bits_size),
.auto_dmi_in_d_bits_source (_dmInner_auto_dmi_in_d_bits_source),
.auto_dmi_in_d_bits_data (_dmInner_auto_dmi_in_d_bits_data),
.io_dmactive (dmactive_synced), // @[ShiftReg.scala:48:24]
.io_innerCtrl_valid (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_valid), // @[AsyncQueue.scala:211:22]
.io_innerCtrl_bits_resumereq (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_resumereq), // @[AsyncQueue.scala:211:22]
.io_innerCtrl_bits_hartsel (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hartsel), // @[AsyncQueue.scala:211:22]
.io_innerCtrl_bits_ackhavereset (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_ackhavereset), // @[AsyncQueue.scala:211:22]
.io_innerCtrl_bits_hasel (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hasel), // @[AsyncQueue.scala:211:22]
.io_innerCtrl_bits_hamask_0 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_0), // @[AsyncQueue.scala:211:22]
.io_innerCtrl_bits_hrmask_0 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_0), // @[AsyncQueue.scala:211:22]
.io_hgDebugInt_0 (io_hgDebugInt_0_0),
.io_hartIsInReset_0 (io_hartIsInReset_0_0), // @[Debug.scala:1871:9]
.io_tl_clock (io_tl_clock_0), // @[Debug.scala:1871:9]
.io_tl_reset (io_tl_reset_0) // @[Debug.scala:1871:9]
); // @[Debug.scala:1857:27]
TLAsyncCrossingSink_a9d32s1k1z2u dmiXing ( // @[Debug.scala:1858:27]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_in_a_mem_0_opcode (auto_dmiXing_in_a_mem_0_opcode_0), // @[Debug.scala:1871:9]
.auto_in_a_mem_0_address (auto_dmiXing_in_a_mem_0_address_0), // @[Debug.scala:1871:9]
.auto_in_a_mem_0_data (auto_dmiXing_in_a_mem_0_data_0), // @[Debug.scala:1871:9]
.auto_in_a_ridx (auto_dmiXing_in_a_ridx_0),
.auto_in_a_widx (auto_dmiXing_in_a_widx_0), // @[Debug.scala:1871:9]
.auto_in_a_safe_ridx_valid (auto_dmiXing_in_a_safe_ridx_valid_0),
.auto_in_a_safe_widx_valid (auto_dmiXing_in_a_safe_widx_valid_0), // @[Debug.scala:1871:9]
.auto_in_a_safe_source_reset_n (auto_dmiXing_in_a_safe_source_reset_n_0), // @[Debug.scala:1871:9]
.auto_in_a_safe_sink_reset_n (auto_dmiXing_in_a_safe_sink_reset_n_0),
.auto_in_d_mem_0_opcode (auto_dmiXing_in_d_mem_0_opcode_0),
.auto_in_d_mem_0_size (auto_dmiXing_in_d_mem_0_size_0),
.auto_in_d_mem_0_source (auto_dmiXing_in_d_mem_0_source_0),
.auto_in_d_mem_0_data (auto_dmiXing_in_d_mem_0_data_0),
.auto_in_d_ridx (auto_dmiXing_in_d_ridx_0), // @[Debug.scala:1871:9]
.auto_in_d_widx (auto_dmiXing_in_d_widx_0),
.auto_in_d_safe_ridx_valid (auto_dmiXing_in_d_safe_ridx_valid_0), // @[Debug.scala:1871:9]
.auto_in_d_safe_widx_valid (auto_dmiXing_in_d_safe_widx_valid_0),
.auto_in_d_safe_source_reset_n (auto_dmiXing_in_d_safe_source_reset_n_0),
.auto_in_d_safe_sink_reset_n (auto_dmiXing_in_d_safe_sink_reset_n_0), // @[Debug.scala:1871:9]
.auto_out_a_ready (_dmInner_auto_dmi_in_a_ready), // @[Debug.scala:1857:27]
.auto_out_a_valid (_dmiXing_auto_out_a_valid),
.auto_out_a_bits_opcode (_dmiXing_auto_out_a_bits_opcode),
.auto_out_a_bits_param (_dmiXing_auto_out_a_bits_param),
.auto_out_a_bits_size (_dmiXing_auto_out_a_bits_size),
.auto_out_a_bits_source (_dmiXing_auto_out_a_bits_source),
.auto_out_a_bits_address (_dmiXing_auto_out_a_bits_address),
.auto_out_a_bits_mask (_dmiXing_auto_out_a_bits_mask),
.auto_out_a_bits_data (_dmiXing_auto_out_a_bits_data),
.auto_out_a_bits_corrupt (_dmiXing_auto_out_a_bits_corrupt),
.auto_out_d_ready (_dmiXing_auto_out_d_ready),
.auto_out_d_valid (_dmInner_auto_dmi_in_d_valid), // @[Debug.scala:1857:27]
.auto_out_d_bits_opcode (_dmInner_auto_dmi_in_d_bits_opcode), // @[Debug.scala:1857:27]
.auto_out_d_bits_size (_dmInner_auto_dmi_in_d_bits_size), // @[Debug.scala:1857:27]
.auto_out_d_bits_source (_dmInner_auto_dmi_in_d_bits_source), // @[Debug.scala:1857:27]
.auto_out_d_bits_data (_dmInner_auto_dmi_in_d_bits_data) // @[Debug.scala:1857:27]
); // @[Debug.scala:1858:27]
AsyncResetSynchronizerShiftReg_w1_d3_i0_27 dmactive_synced_dmactive_synced_dmactiveSync ( // @[ShiftReg.scala:45:23]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.io_d (io_dmactive_0), // @[Debug.scala:1871:9]
.io_q (dmactive_synced)
); // @[ShiftReg.scala:45:23]
AsyncQueueSink_DebugInternalBundle dmactive_synced_dmInner_io_innerCtrl_sink ( // @[AsyncQueue.scala:211:22]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.io_deq_valid (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_valid),
.io_deq_bits_resumereq (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_resumereq),
.io_deq_bits_hartsel (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hartsel),
.io_deq_bits_ackhavereset (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_ackhavereset),
.io_deq_bits_hasel (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hasel),
.io_deq_bits_hamask_0 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_0),
.io_deq_bits_hrmask_0 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_0),
.io_async_mem_0_resumereq (io_innerCtrl_mem_0_resumereq_0), // @[Debug.scala:1871:9]
.io_async_mem_0_hartsel (io_innerCtrl_mem_0_hartsel_0), // @[Debug.scala:1871:9]
.io_async_mem_0_ackhavereset (io_innerCtrl_mem_0_ackhavereset_0), // @[Debug.scala:1871:9]
.io_async_mem_0_hrmask_0 (io_innerCtrl_mem_0_hrmask_0_0), // @[Debug.scala:1871:9]
.io_async_ridx (io_innerCtrl_ridx_0),
.io_async_widx (io_innerCtrl_widx_0), // @[Debug.scala:1871:9]
.io_async_safe_ridx_valid (io_innerCtrl_safe_ridx_valid_0),
.io_async_safe_widx_valid (io_innerCtrl_safe_widx_valid_0), // @[Debug.scala:1871:9]
.io_async_safe_source_reset_n (io_innerCtrl_safe_source_reset_n_0), // @[Debug.scala:1871:9]
.io_async_safe_sink_reset_n (io_innerCtrl_safe_sink_reset_n_0)
); // @[AsyncQueue.scala:211:22]
assign auto_dmiXing_in_a_ridx = auto_dmiXing_in_a_ridx_0; // @[Debug.scala:1871:9]
assign auto_dmiXing_in_a_safe_ridx_valid = auto_dmiXing_in_a_safe_ridx_valid_0; // @[Debug.scala:1871:9]
assign auto_dmiXing_in_a_safe_sink_reset_n = auto_dmiXing_in_a_safe_sink_reset_n_0; // @[Debug.scala:1871:9]
assign auto_dmiXing_in_d_mem_0_opcode = auto_dmiXing_in_d_mem_0_opcode_0; // @[Debug.scala:1871:9]
assign auto_dmiXing_in_d_mem_0_size = auto_dmiXing_in_d_mem_0_size_0; // @[Debug.scala:1871:9]
assign auto_dmiXing_in_d_mem_0_source = auto_dmiXing_in_d_mem_0_source_0; // @[Debug.scala:1871:9]
assign auto_dmiXing_in_d_mem_0_data = auto_dmiXing_in_d_mem_0_data_0; // @[Debug.scala:1871:9]
assign auto_dmiXing_in_d_widx = auto_dmiXing_in_d_widx_0; // @[Debug.scala:1871:9]
assign auto_dmiXing_in_d_safe_widx_valid = auto_dmiXing_in_d_safe_widx_valid_0; // @[Debug.scala:1871:9]
assign auto_dmiXing_in_d_safe_source_reset_n = auto_dmiXing_in_d_safe_source_reset_n_0; // @[Debug.scala:1871:9]
assign auto_dmInner_sb2tlOpt_out_a_valid = auto_dmInner_sb2tlOpt_out_a_valid_0; // @[Debug.scala:1871:9]
assign auto_dmInner_sb2tlOpt_out_a_bits_opcode = auto_dmInner_sb2tlOpt_out_a_bits_opcode_0; // @[Debug.scala:1871:9]
assign auto_dmInner_sb2tlOpt_out_a_bits_size = auto_dmInner_sb2tlOpt_out_a_bits_size_0; // @[Debug.scala:1871:9]
assign auto_dmInner_sb2tlOpt_out_a_bits_address = auto_dmInner_sb2tlOpt_out_a_bits_address_0; // @[Debug.scala:1871:9]
assign auto_dmInner_sb2tlOpt_out_a_bits_data = auto_dmInner_sb2tlOpt_out_a_bits_data_0; // @[Debug.scala:1871:9]
assign auto_dmInner_sb2tlOpt_out_d_ready = auto_dmInner_sb2tlOpt_out_d_ready_0; // @[Debug.scala:1871:9]
assign auto_dmInner_tl_in_a_ready = auto_dmInner_tl_in_a_ready_0; // @[Debug.scala:1871:9]
assign auto_dmInner_tl_in_d_valid = auto_dmInner_tl_in_d_valid_0; // @[Debug.scala:1871:9]
assign auto_dmInner_tl_in_d_bits_opcode = auto_dmInner_tl_in_d_bits_opcode_0; // @[Debug.scala:1871:9]
assign auto_dmInner_tl_in_d_bits_size = auto_dmInner_tl_in_d_bits_size_0; // @[Debug.scala:1871:9]
assign auto_dmInner_tl_in_d_bits_source = auto_dmInner_tl_in_d_bits_source_0; // @[Debug.scala:1871:9]
assign auto_dmInner_tl_in_d_bits_data = auto_dmInner_tl_in_d_bits_data_0; // @[Debug.scala:1871:9]
assign io_innerCtrl_ridx = io_innerCtrl_ridx_0; // @[Debug.scala:1871:9]
assign io_innerCtrl_safe_ridx_valid = io_innerCtrl_safe_ridx_valid_0; // @[Debug.scala:1871:9]
assign io_innerCtrl_safe_sink_reset_n = io_innerCtrl_safe_sink_reset_n_0; // @[Debug.scala:1871:9]
assign io_hgDebugInt_0 = io_hgDebugInt_0_0; // @[Debug.scala:1871:9]
endmodule |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.